1 /*- 2 * Copyright (c) 2008-2009 Semihalf, Rafal Jaworowski 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/bus.h> 34 #include <sys/pcpu.h> 35 #include <sys/proc.h> 36 #include <sys/smp.h> 37 38 #include <machine/bus.h> 39 #include <machine/cpu.h> 40 #include <machine/hid.h> 41 #include <machine/platform.h> 42 #include <machine/platformvar.h> 43 #include <machine/smp.h> 44 #include <machine/spr.h> 45 #include <machine/vmparam.h> 46 47 #include <dev/fdt/fdt_common.h> 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 #include <dev/ofw/openfirm.h> 51 52 #include <powerpc/mpc85xx/mpc85xx.h> 53 54 #include "platform_if.h" 55 56 #ifdef SMP 57 extern void *ap_pcpu; 58 extern uint8_t __boot_page[]; /* Boot page body */ 59 extern uint32_t kernload; /* Kernel physical load address */ 60 #endif 61 62 extern uint32_t *bootinfo; 63 64 static int cpu, maxcpu; 65 66 static int bare_probe(platform_t); 67 static void bare_mem_regions(platform_t, struct mem_region **phys, int *physsz, 68 struct mem_region **avail, int *availsz); 69 static u_long bare_timebase_freq(platform_t, struct cpuref *cpuref); 70 static int bare_smp_first_cpu(platform_t, struct cpuref *cpuref); 71 static int bare_smp_next_cpu(platform_t, struct cpuref *cpuref); 72 static int bare_smp_get_bsp(platform_t, struct cpuref *cpuref); 73 static int bare_smp_start_cpu(platform_t, struct pcpu *cpu); 74 75 static void e500_reset(platform_t); 76 77 static platform_method_t bare_methods[] = { 78 PLATFORMMETHOD(platform_probe, bare_probe), 79 PLATFORMMETHOD(platform_mem_regions, bare_mem_regions), 80 PLATFORMMETHOD(platform_timebase_freq, bare_timebase_freq), 81 82 PLATFORMMETHOD(platform_smp_first_cpu, bare_smp_first_cpu), 83 PLATFORMMETHOD(platform_smp_next_cpu, bare_smp_next_cpu), 84 PLATFORMMETHOD(platform_smp_get_bsp, bare_smp_get_bsp), 85 PLATFORMMETHOD(platform_smp_start_cpu, bare_smp_start_cpu), 86 87 PLATFORMMETHOD(platform_reset, e500_reset), 88 89 { 0, 0 } 90 }; 91 92 static platform_def_t bare_platform = { 93 "bare metal", 94 bare_methods, 95 0 96 }; 97 98 PLATFORM_DEF(bare_platform); 99 100 static int 101 bare_probe(platform_t plat) 102 { 103 uint32_t ver, sr; 104 int i, law_max, tgt; 105 106 ver = SVR_VER(mfspr(SPR_SVR)); 107 if (ver == SVR_MPC8572E || ver == SVR_MPC8572) 108 maxcpu = 2; 109 else 110 maxcpu = 1; 111 112 /* 113 * Clear local access windows. Skip DRAM entries, so we don't shoot 114 * ourselves in the foot. 115 */ 116 law_max = law_getmax(); 117 for (i = 0; i < law_max; i++) { 118 sr = ccsr_read4(OCP85XX_LAWSR(i)); 119 if ((sr & 0x80000000) == 0) 120 continue; 121 tgt = (sr & 0x01f00000) >> 20; 122 if (tgt == OCP85XX_TGTIF_RAM1 || tgt == OCP85XX_TGTIF_RAM2 || 123 tgt == OCP85XX_TGTIF_RAM_INTL) 124 continue; 125 126 ccsr_write4(OCP85XX_LAWSR(i), sr & 0x7fffffff); 127 } 128 129 return (BUS_PROBE_GENERIC); 130 } 131 132 #define MEM_REGIONS 8 133 static struct mem_region avail_regions[MEM_REGIONS]; 134 135 void 136 bare_mem_regions(platform_t plat, struct mem_region **phys, int *physsz, 137 struct mem_region **avail, int *availsz) 138 { 139 uint32_t memsize; 140 int i, rv; 141 142 rv = fdt_get_mem_regions(avail_regions, availsz, &memsize); 143 144 if (rv != 0) 145 return; 146 147 for (i = 0; i < *availsz; i++) { 148 if (avail_regions[i].mr_start < 1048576) { 149 avail_regions[i].mr_size = 150 avail_regions[i].mr_size - 151 (1048576 - avail_regions[i].mr_start); 152 avail_regions[i].mr_start = 1048576; 153 } 154 } 155 *avail = avail_regions; 156 157 /* On the bare metal platform phys == avail memory */ 158 *physsz = *availsz; 159 *phys = *avail; 160 } 161 162 static u_long 163 bare_timebase_freq(platform_t plat, struct cpuref *cpuref) 164 { 165 u_long ticks; 166 phandle_t cpus, child; 167 pcell_t freq; 168 169 /* Backward compatibility. See 8-STABLE. */ 170 ticks = bootinfo[3] >> 3; 171 172 if ((cpus = OF_finddevice("/cpus")) == 0) 173 goto out; 174 175 if ((child = OF_child(cpus)) == 0) 176 goto out; 177 178 freq = 0; 179 if (OF_getprop(child, "bus-frequency", (void *)&freq, 180 sizeof(freq)) <= 0) 181 goto out; 182 183 /* 184 * Time Base and Decrementer are updated every 8 CCB bus clocks. 185 * HID0[SEL_TBCLK] = 0 186 */ 187 if (freq != 0) 188 ticks = freq / 8; 189 190 out: 191 if (ticks <= 0) 192 panic("Unable to determine timebase frequency!"); 193 194 return (ticks); 195 } 196 197 static int 198 bare_smp_first_cpu(platform_t plat, struct cpuref *cpuref) 199 { 200 201 cpu = 0; 202 cpuref->cr_cpuid = cpu; 203 cpuref->cr_hwref = cpuref->cr_cpuid; 204 if (bootverbose) 205 printf("powerpc_smp_first_cpu: cpuid %d\n", cpuref->cr_cpuid); 206 cpu++; 207 208 return (0); 209 } 210 211 static int 212 bare_smp_next_cpu(platform_t plat, struct cpuref *cpuref) 213 { 214 215 if (cpu >= maxcpu) 216 return (ENOENT); 217 218 cpuref->cr_cpuid = cpu++; 219 cpuref->cr_hwref = cpuref->cr_cpuid; 220 if (bootverbose) 221 printf("powerpc_smp_next_cpu: cpuid %d\n", cpuref->cr_cpuid); 222 223 return (0); 224 } 225 226 static int 227 bare_smp_get_bsp(platform_t plat, struct cpuref *cpuref) 228 { 229 230 cpuref->cr_cpuid = mfspr(SPR_PIR); 231 cpuref->cr_hwref = cpuref->cr_cpuid; 232 233 return (0); 234 } 235 236 static int 237 bare_smp_start_cpu(platform_t plat, struct pcpu *pc) 238 { 239 #ifdef SMP 240 uint32_t bptr, eebpcr; 241 int timeout; 242 243 eebpcr = ccsr_read4(OCP85XX_EEBPCR); 244 if ((eebpcr & (pc->pc_cpumask << 24)) != 0) { 245 printf("%s: CPU=%d already out of hold-off state!\n", 246 __func__, pc->pc_cpuid); 247 return (ENXIO); 248 } 249 250 ap_pcpu = pc; 251 __asm __volatile("msync; isync"); 252 253 /* 254 * Set BPTR to the physical address of the boot page 255 */ 256 bptr = ((uint32_t)__boot_page - KERNBASE) + kernload; 257 ccsr_write4(OCP85XX_BPTR, (bptr >> 12) | 0x80000000); 258 259 /* 260 * Release AP from hold-off state 261 */ 262 eebpcr |= (pc->pc_cpumask << 24); 263 ccsr_write4(OCP85XX_EEBPCR, eebpcr); 264 __asm __volatile("isync; msync"); 265 266 timeout = 500; 267 while (!pc->pc_awake && timeout--) 268 DELAY(1000); /* wait 1ms */ 269 270 return ((pc->pc_awake) ? 0 : EBUSY); 271 #else 272 /* No SMP support */ 273 return (ENXIO); 274 #endif 275 } 276 277 static void 278 e500_reset(platform_t plat) 279 { 280 uint32_t ver = SVR_VER(mfspr(SPR_SVR)); 281 282 if (ver == SVR_MPC8572E || ver == SVR_MPC8572 || 283 ver == SVR_MPC8548E || ver == SVR_MPC8548) 284 /* Systems with dedicated reset register */ 285 ccsr_write4(OCP85XX_RSTCR, 2); 286 else { 287 /* Clear DBCR0, disables debug interrupts and events. */ 288 mtspr(SPR_DBCR0, 0); 289 __asm __volatile("isync"); 290 291 /* Enable Debug Interrupts in MSR. */ 292 mtmsr(mfmsr() | PSL_DE); 293 294 /* Enable debug interrupts and issue reset. */ 295 mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | 296 DBCR0_RST_SYSTEM); 297 } 298 299 printf("Reset failed...\n"); 300 while (1); 301 } 302 303