1/* $FreeBSD$ */ 2/* $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ */ 3 4/*- 5 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 6 * Copyright (C) 1995, 1996 TooLs GmbH. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by TooLs GmbH. 20 * 4. The name of TooLs GmbH may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/* 36 * NOTICE: This is not a standalone file. to use it, #include it in 37 * your port's locore.S, like so: 38 * 39 * #include <powerpc/aim/trap_subr.S> 40 */ 41 42/* 43 * Save/restore segment registers 44 */ 45 46/* 47 * Restore SRs for a pmap 48 * 49 * Requires that r28-r31 be scratch, with r28 initialized to the SLB cache 50 */ 51 52/* 53 * User SRs are loaded through a pointer to the current pmap. 54 */ 55restore_usersrs: 56 GET_CPUINFO(%r28) 57 ld %r28,PC_USERSLB(%r28) 58 li %r29, 0 /* Set the counter to zero */ 59 60 slbia 61 slbmfee %r31,%r29 62 clrrdi %r31,%r31,28 63 slbie %r31 641: ld %r31, 0(%r28) /* Load SLB entry pointer */ 65 cmpli 0, %r31, 0 /* If NULL, stop */ 66 beqlr 67 68 ld %r30, 0(%r31) /* Load SLBV */ 69 ld %r31, 8(%r31) /* Load SLBE */ 70 or %r31, %r31, %r29 /* Set SLBE slot */ 71 slbmte %r30, %r31 /* Install SLB entry */ 72 73 addi %r28, %r28, 8 /* Advance pointer */ 74 addi %r29, %r29, 1 75 b 1b /* Repeat */ 76 77/* 78 * Kernel SRs are loaded directly from the PCPU fields 79 */ 80restore_kernsrs: 81 GET_CPUINFO(%r28) 82 addi %r28,%r28,PC_KERNSLB 83 li %r29, 0 /* Set the counter to zero */ 84 85 slbia 86 slbmfee %r31,%r29 87 clrrdi %r31,%r31,28 88 slbie %r31 891: cmpli 0, %r29, USER_SLB_SLOT /* Skip the user slot */ 90 beq- 2f 91 92 ld %r31, 8(%r28) /* Load SLBE */ 93 cmpli 0, %r31, 0 /* If SLBE is not valid, stop */ 94 beqlr 95 ld %r30, 0(%r28) /* Load SLBV */ 96 slbmte %r30, %r31 /* Install SLB entry */ 97 982: addi %r28, %r28, 16 /* Advance pointer */ 99 addi %r29, %r29, 1 100 cmpli 0, %r29, 64 /* Repeat if we are not at the end */ 101 blt 1b 102 blr 103 104/* 105 * FRAME_SETUP assumes: 106 * SPRG1 SP (1) 107 * SPRG3 trap type 108 * savearea r27-r31,DAR,DSISR (DAR & DSISR only for DSI traps) 109 * r28 LR 110 * r29 CR 111 * r30 scratch 112 * r31 scratch 113 * r1 kernel stack 114 * SRR0/1 as at start of trap 115 */ 116#define FRAME_SETUP(savearea) \ 117/* Have to enable translation to allow access of kernel stack: */ \ 118 GET_CPUINFO(%r31); \ 119 mfsrr0 %r30; \ 120 std %r30,(savearea+CPUSAVE_SRR0)(%r31); /* save SRR0 */ \ 121 mfsrr1 %r30; \ 122 std %r30,(savearea+CPUSAVE_SRR1)(%r31); /* save SRR1 */ \ 123 mfmsr %r30; \ 124 ori %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \ 125 mtmsr %r30; /* stack can now be accessed */ \ 126 isync; \ 127 mfsprg1 %r31; /* get saved SP */ \ 128 stdu %r31,-(FRAMELEN+288)(%r1); /* save it in the callframe */ \ 129 std %r0, FRAME_0+48(%r1); /* save r0 in the trapframe */ \ 130 std %r31,FRAME_1+48(%r1); /* save SP " " */ \ 131 std %r2, FRAME_2+48(%r1); /* save r2 " " */ \ 132 std %r28,FRAME_LR+48(%r1); /* save LR " " */ \ 133 std %r29,FRAME_CR+48(%r1); /* save CR " " */ \ 134 GET_CPUINFO(%r2); \ 135 ld %r27,(savearea+CPUSAVE_R27)(%r2); /* get saved r27 */ \ 136 ld %r28,(savearea+CPUSAVE_R28)(%r2); /* get saved r28 */ \ 137 ld %r29,(savearea+CPUSAVE_R29)(%r2); /* get saved r29 */ \ 138 ld %r30,(savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \ 139 ld %r31,(savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \ 140 std %r3, FRAME_3+48(%r1); /* save r3-r31 */ \ 141 std %r4, FRAME_4+48(%r1); \ 142 std %r5, FRAME_5+48(%r1); \ 143 std %r6, FRAME_6+48(%r1); \ 144 std %r7, FRAME_7+48(%r1); \ 145 std %r8, FRAME_8+48(%r1); \ 146 std %r9, FRAME_9+48(%r1); \ 147 std %r10, FRAME_10+48(%r1); \ 148 std %r11, FRAME_11+48(%r1); \ 149 std %r12, FRAME_12+48(%r1); \ 150 std %r13, FRAME_13+48(%r1); \ 151 std %r14, FRAME_14+48(%r1); \ 152 std %r15, FRAME_15+48(%r1); \ 153 std %r16, FRAME_16+48(%r1); \ 154 std %r17, FRAME_17+48(%r1); \ 155 std %r18, FRAME_18+48(%r1); \ 156 std %r19, FRAME_19+48(%r1); \ 157 std %r20, FRAME_20+48(%r1); \ 158 std %r21, FRAME_21+48(%r1); \ 159 std %r22, FRAME_22+48(%r1); \ 160 std %r23, FRAME_23+48(%r1); \ 161 std %r24, FRAME_24+48(%r1); \ 162 std %r25, FRAME_25+48(%r1); \ 163 std %r26, FRAME_26+48(%r1); \ 164 std %r27, FRAME_27+48(%r1); \ 165 std %r28, FRAME_28+48(%r1); \ 166 std %r29, FRAME_29+48(%r1); \ 167 std %r30, FRAME_30+48(%r1); \ 168 std %r31, FRAME_31+48(%r1); \ 169 ld %r28,(savearea+CPUSAVE_AIM_DAR)(%r2); /* saved DAR */ \ 170 ld %r29,(savearea+CPUSAVE_AIM_DSISR)(%r2);/* saved DSISR */\ 171 ld %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */ \ 172 ld %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \ 173 mfxer %r3; \ 174 mfctr %r4; \ 175 mfsprg3 %r5; \ 176 std %r3, FRAME_XER+48(1); /* save xer/ctr/exc */ \ 177 std %r4, FRAME_CTR+48(1); \ 178 std %r5, FRAME_EXC+48(1); \ 179 std %r28,FRAME_AIM_DAR+48(1); \ 180 std %r29,FRAME_AIM_DSISR+48(1); /* save dsisr/srr0/srr1 */ \ 181 std %r30,FRAME_SRR0+48(1); \ 182 std %r31,FRAME_SRR1+48(1); \ 183 ld %r13,PC_CURTHREAD(%r2) /* set kernel curthread */ 184 185#define FRAME_LEAVE(savearea) \ 186/* Disable exceptions: */ \ 187 mfmsr %r2; \ 188 andi. %r2,%r2,~PSL_EE@l; \ 189 mtmsr %r2; \ 190 isync; \ 191/* Now restore regs: */ \ 192 ld %r2,FRAME_SRR0+48(%r1); \ 193 ld %r3,FRAME_SRR1+48(%r1); \ 194 ld %r4,FRAME_CTR+48(%r1); \ 195 ld %r5,FRAME_XER+48(%r1); \ 196 ld %r6,FRAME_LR+48(%r1); \ 197 GET_CPUINFO(%r7); \ 198 std %r2,(savearea+CPUSAVE_SRR0)(%r7); /* save SRR0 */ \ 199 std %r3,(savearea+CPUSAVE_SRR1)(%r7); /* save SRR1 */ \ 200 ld %r7,FRAME_CR+48(%r1); \ 201 mtctr %r4; \ 202 mtxer %r5; \ 203 mtlr %r6; \ 204 mtsprg1 %r7; /* save cr */ \ 205 ld %r31,FRAME_31+48(%r1); /* restore r0-31 */ \ 206 ld %r30,FRAME_30+48(%r1); \ 207 ld %r29,FRAME_29+48(%r1); \ 208 ld %r28,FRAME_28+48(%r1); \ 209 ld %r27,FRAME_27+48(%r1); \ 210 ld %r26,FRAME_26+48(%r1); \ 211 ld %r25,FRAME_25+48(%r1); \ 212 ld %r24,FRAME_24+48(%r1); \ 213 ld %r23,FRAME_23+48(%r1); \ 214 ld %r22,FRAME_22+48(%r1); \ 215 ld %r21,FRAME_21+48(%r1); \ 216 ld %r20,FRAME_20+48(%r1); \ 217 ld %r19,FRAME_19+48(%r1); \ 218 ld %r18,FRAME_18+48(%r1); \ 219 ld %r17,FRAME_17+48(%r1); \ 220 ld %r16,FRAME_16+48(%r1); \ 221 ld %r15,FRAME_15+48(%r1); \ 222 ld %r14,FRAME_14+48(%r1); \ 223 ld %r13,FRAME_13+48(%r1); \ 224 ld %r12,FRAME_12+48(%r1); \ 225 ld %r11,FRAME_11+48(%r1); \ 226 ld %r10,FRAME_10+48(%r1); \ 227 ld %r9, FRAME_9+48(%r1); \ 228 ld %r8, FRAME_8+48(%r1); \ 229 ld %r7, FRAME_7+48(%r1); \ 230 ld %r6, FRAME_6+48(%r1); \ 231 ld %r5, FRAME_5+48(%r1); \ 232 ld %r4, FRAME_4+48(%r1); \ 233 ld %r3, FRAME_3+48(%r1); \ 234 ld %r2, FRAME_2+48(%r1); \ 235 ld %r0, FRAME_0+48(%r1); \ 236 ld %r1, FRAME_1+48(%r1); \ 237/* Can't touch %r1 from here on */ \ 238 mtsprg2 %r2; /* save r2 & r3 */ \ 239 mtsprg3 %r3; \ 240/* Disable translation, machine check and recoverability: */ \ 241 mfmsr %r2; \ 242 andi. %r2,%r2,~(PSL_DR|PSL_IR|PSL_ME|PSL_RI)@l; \ 243 mtmsr %r2; \ 244 isync; \ 245/* Decide whether we return to user mode: */ \ 246 GET_CPUINFO(%r2); \ 247 ld %r3,(savearea+CPUSAVE_SRR1)(%r2); \ 248 mtcr %r3; \ 249 bf 17,1f; /* branch if PSL_PR is false */ \ 250/* Restore user SRs */ \ 251 GET_CPUINFO(%r3); \ 252 std %r27,(savearea+CPUSAVE_R27)(%r3); \ 253 std %r28,(savearea+CPUSAVE_R28)(%r3); \ 254 std %r29,(savearea+CPUSAVE_R29)(%r3); \ 255 std %r30,(savearea+CPUSAVE_R30)(%r3); \ 256 std %r31,(savearea+CPUSAVE_R31)(%r3); \ 257 mflr %r27; /* preserve LR */ \ 258 bl restore_usersrs; /* uses r28-r31 */ \ 259 mtlr %r27; \ 260 ld %r31,(savearea+CPUSAVE_R31)(%r3); \ 261 ld %r30,(savearea+CPUSAVE_R30)(%r3); \ 262 ld %r29,(savearea+CPUSAVE_R29)(%r3); \ 263 ld %r28,(savearea+CPUSAVE_R28)(%r3); \ 264 ld %r27,(savearea+CPUSAVE_R27)(%r3); \ 2651: mfsprg1 %r2; /* restore cr */ \ 266 mtcr %r2; \ 267 GET_CPUINFO(%r2); \ 268 ld %r3,(savearea+CPUSAVE_SRR0)(%r2); /* restore srr0 */ \ 269 mtsrr0 %r3; \ 270 ld %r3,(savearea+CPUSAVE_SRR1)(%r2); /* restore srr1 */ \ 271 mtsrr1 %r3; \ 272 mfsprg2 %r2; /* restore r2 & r3 */ \ 273 mfsprg3 %r3 274 275#ifdef SMP 276/* 277 * Processor reset exception handler. These are typically 278 * the first instructions the processor executes after a 279 * software reset. We do this in two bits so that we are 280 * not still hanging around in the trap handling region 281 * once the MMU is turned on. 282 */ 283 .globl CNAME(rstcode), CNAME(rstsize) 284CNAME(rstcode): 285 /* Explicitly set MSR[SF] */ 286 mfmsr %r9 287 li %r8,1 288 insrdi %r9,%r8,1,0 289 mtmsrd %r9 290 isync 291 292 ba cpu_reset 293CNAME(rstsize) = . - CNAME(rstcode) 294 295cpu_reset: 296 lis %r1,(tmpstk+TMPSTKSZ-48)@ha /* get new SP */ 297 addi %r1,%r1,(tmpstk+TMPSTKSZ-48)@l 298 299 lis %r3,tocbase@ha 300 ld %r2,tocbase@l(%r3) 301 lis %r3,1@l 302 bl CNAME(cpudep_ap_early_bootstrap) /* Set PCPU */ 303 nop 304 bl CNAME(pmap_cpu_bootstrap) /* Turn on virtual memory */ 305 nop 306 bl CNAME(cpudep_ap_bootstrap) /* Set up PCPU and stack */ 307 nop 308 mr %r1,%r3 /* Use new stack */ 309 bl CNAME(machdep_ap_bootstrap) /* And away! */ 310 nop 311 312 /* Should not be reached */ 3139: 314 b 9b 315#endif 316 317/* 318 * This code gets copied to all the trap vectors 319 * (except ISI/DSI, ALI, and the interrupts) 320 */ 321 322 .globl CNAME(trapcode),CNAME(trapsize) 323CNAME(trapcode): 324 mtsprg1 %r1 /* save SP */ 325 mflr %r1 /* Save the old LR in r1 */ 326 mtsprg2 %r1 /* And then in SPRG2 */ 327 li %r1, 0xA0 /* How to get the vector from LR */ 328 bla generictrap /* LR & SPRG3 is exception # */ 329CNAME(trapsize) = .-CNAME(trapcode) 330 331/* 332 * For ALI: has to save DSISR and DAR 333 */ 334 .globl CNAME(alitrap),CNAME(alisize) 335CNAME(alitrap): 336 mtsprg1 %r1 /* save SP */ 337 GET_CPUINFO(%r1) 338 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */ 339 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 340 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 341 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 342 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 343 mfdar %r30 344 mfdsisr %r31 345 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 346 std %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 347 mfsprg1 %r1 /* restore SP, in case of branch */ 348 mflr %r28 /* save LR */ 349 mfcr %r29 /* save CR */ 350 351 /* Put our exception vector in SPRG3 */ 352 li %r31, EXC_ALI 353 mtsprg3 %r31 354 355 /* Test whether we already had PR set */ 356 mfsrr1 %r31 357 mtcr %r31 358 bla s_trap 359CNAME(alisize) = .-CNAME(alitrap) 360 361/* 362 * Similar to the above for DSI 363 * Has to handle BAT spills 364 * and standard pagetable spills 365 */ 366 .globl CNAME(dsitrap),CNAME(dsisize) 367CNAME(dsitrap): 368 mtsprg1 %r1 /* save SP */ 369 GET_CPUINFO(%r1) 370 std %r27,(PC_DISISAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */ 371 std %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) 372 std %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1) 373 std %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 374 std %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 375 mfsprg1 %r1 /* restore SP */ 376 mfcr %r29 /* save CR */ 377 mfxer %r30 /* save XER */ 378 mtsprg2 %r30 /* in SPRG2 */ 379 mfsrr1 %r31 /* test kernel mode */ 380 mtcr %r31 381 mflr %r28 /* save LR (SP already saved) */ 382 bla disitrap 383CNAME(dsisize) = .-CNAME(dsitrap) 384 385/* 386 * Preamble code for DSI/ISI traps 387 */ 388disitrap: 389 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 390 mflr %r1 391 andi. %r1,%r1,0xff00 392 mtsprg3 %r1 393 394 GET_CPUINFO(%r1) 395 ld %r31,(PC_DISISAVE+CPUSAVE_R27)(%r1) 396 std %r31,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) 397 ld %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) 398 std %r30,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 399 ld %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) 400 std %r31,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 401 ld %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) 402 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 403 ld %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) 404 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 405 mfdar %r30 406 mfdsisr %r31 407 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 408 std %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) 409 410#ifdef KDB 411 /* Try and detect a kernel stack overflow */ 412 mfsrr1 %r31 413 mtcr %r31 414 bt 17,realtrap /* branch is user mode */ 415 mfsprg1 %r31 /* get old SP */ 416 sub. %r30,%r31,%r30 /* SP - DAR */ 417 bge 1f 418 neg %r30,%r30 /* modulo value */ 4191: cmpldi %cr0,%r30,4096 /* is DAR within a page of SP? */ 420 bge %cr0,realtrap /* no, too far away. */ 421 422 /* Now convert this DSI into a DDB trap. */ 423 GET_CPUINFO(%r1) 424 ld %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) /* get DAR */ 425 std %r30,(PC_DBSAVE +CPUSAVE_AIM_DAR)(%r1) /* save DAR */ 426 ld %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) /* get DSISR */ 427 std %r30,(PC_DBSAVE +CPUSAVE_AIM_DSISR)(%r1) /* save DSISR */ 428 ld %r31,(PC_DISISAVE+CPUSAVE_R27)(%r1) /* get r27 */ 429 std %r31,(PC_DBSAVE +CPUSAVE_R27)(%r1) /* save r27 */ 430 ld %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get r28 */ 431 std %r30,(PC_DBSAVE +CPUSAVE_R28)(%r1) /* save r28 */ 432 ld %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get r29 */ 433 std %r31,(PC_DBSAVE +CPUSAVE_R29)(%r1) /* save r29 */ 434 ld %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) /* get r30 */ 435 std %r30,(PC_DBSAVE +CPUSAVE_R30)(%r1) /* save r30 */ 436 ld %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) /* get r31 */ 437 std %r31,(PC_DBSAVE +CPUSAVE_R31)(%r1) /* save r31 */ 438 b dbtrap 439#endif 440 441 /* XXX need stack probe here */ 442realtrap: 443/* Test whether we already had PR set */ 444 mfsrr1 %r1 445 mtcr %r1 446 mfsprg1 %r1 /* restore SP (might have been 447 overwritten) */ 448 bf 17,k_trap /* branch if PSL_PR is false */ 449 GET_CPUINFO(%r1) 450 ld %r1,PC_CURPCB(%r1) 451 mr %r27,%r28 /* Save LR, r29 */ 452 mtsprg2 %r29 453 bl restore_kernsrs /* enable kernel mapping */ 454 mfsprg2 %r29 455 mr %r28,%r27 456 ba s_trap 457 458/* 459 * generictrap does some standard setup for trap handling to minimize 460 * the code that need be installed in the actual vectors. It expects 461 * the following conditions. 462 * 463 * R1 - Trap vector = LR & (0xff00 | R1) 464 * SPRG1 - Original R1 contents 465 * SPRG2 - Original LR 466 */ 467 468generictrap: 469 /* Save R1 for computing the exception vector */ 470 mtsprg3 %r1 471 472 /* Save interesting registers */ 473 GET_CPUINFO(%r1) 474 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */ 475 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 476 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 477 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 478 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 479 mfdar %r30 480 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) 481 mfsprg1 %r1 /* restore SP, in case of branch */ 482 mfsprg2 %r28 /* save LR */ 483 mfcr %r29 /* save CR */ 484 485 /* Compute the exception vector from the link register */ 486 mfsprg3 %r31 487 ori %r31,%r31,0xff00 488 mflr %r30 489 and %r30,%r30,%r31 490 mtsprg3 %r30 491 492 /* Test whether we already had PR set */ 493 mfsrr1 %r31 494 mtcr %r31 495 496s_trap: 497 bf 17,k_trap /* branch if PSL_PR is false */ 498 GET_CPUINFO(%r1) 499u_trap: 500 ld %r1,PC_CURPCB(%r1) 501 mr %r27,%r28 /* Save LR, r29 */ 502 mtsprg2 %r29 503 bl restore_kernsrs /* enable kernel mapping */ 504 mfsprg2 %r29 505 mr %r28,%r27 506 507/* 508 * Now the common trap catching code. 509 */ 510k_trap: 511 FRAME_SETUP(PC_TEMPSAVE) 512/* Call C interrupt dispatcher: */ 513trapagain: 514 lis %r3,tocbase@ha 515 ld %r2,tocbase@l(%r3) 516 addi %r3,%r1,48 517 bl CNAME(powerpc_interrupt) 518 nop 519 520 .globl CNAME(trapexit) /* backtrace code sentinel */ 521CNAME(trapexit): 522/* Disable interrupts: */ 523 mfmsr %r3 524 andi. %r3,%r3,~PSL_EE@l 525 mtmsr %r3 526 isync 527/* Test AST pending: */ 528 ld %r5,FRAME_SRR1+48(%r1) 529 mtcr %r5 530 bf 17,1f /* branch if PSL_PR is false */ 531 532 GET_CPUINFO(%r3) /* get per-CPU pointer */ 533 lwz %r4, TD_FLAGS(%r13) /* get thread flags value */ 534 lis %r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@h 535 ori %r5,%r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@l 536 and. %r4,%r4,%r5 537 beq 1f 538 mfmsr %r3 /* re-enable interrupts */ 539 ori %r3,%r3,PSL_EE@l 540 mtmsr %r3 541 isync 542 lis %r3,tocbase@ha 543 ld %r2,tocbase@l(%r3) 544 addi %r3,%r1,48 545 bl CNAME(ast) 546 nop 547 .globl CNAME(asttrapexit) /* backtrace code sentinel #2 */ 548CNAME(asttrapexit): 549 b trapexit /* test ast ret value ? */ 5501: 551 FRAME_LEAVE(PC_TEMPSAVE) 552 rfid 553 554#if defined(KDB) 555/* 556 * Deliberate entry to dbtrap 557 */ 558ASENTRY(breakpoint) 559 mtsprg1 %r1 560 mfmsr %r3 561 mtsrr1 %r3 562 andi. %r3,%r3,~(PSL_EE|PSL_ME)@l 563 mtmsr %r3 /* disable interrupts */ 564 isync 565 GET_CPUINFO(%r3) 566 std %r27,(PC_DBSAVE+CPUSAVE_R27)(%r3) 567 std %r28,(PC_DBSAVE+CPUSAVE_R28)(%r3) 568 std %r29,(PC_DBSAVE+CPUSAVE_R29)(%r3) 569 std %r30,(PC_DBSAVE+CPUSAVE_R30)(%r3) 570 std %r31,(PC_DBSAVE+CPUSAVE_R31)(%r3) 571 mflr %r28 572 li %r29,EXC_BPT 573 mtlr %r29 574 mfcr %r29 575 mtsrr0 %r28 576 577/* 578 * Now the kdb trap catching code. 579 */ 580dbtrap: 581 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */ 582 mflr %r1 583 andi. %r1,%r1,0xff00 584 mtsprg3 %r1 585 586 lis %r1,(tmpstk+TMPSTKSZ-48)@ha /* get new SP */ 587 addi %r1,%r1,(tmpstk+TMPSTKSZ-48)@l 588 589 FRAME_SETUP(PC_DBSAVE) 590/* Call C trap code: */ 591 lis %r3,tocbase@ha 592 ld %r2,tocbase@l(%r3) 593 addi %r3,%r1,48 594 bl CNAME(db_trap_glue) 595 nop 596 or. %r3,%r3,%r3 597 bne dbleave 598/* This wasn't for KDB, so switch to real trap: */ 599 ld %r3,FRAME_EXC+48(%r1) /* save exception */ 600 GET_CPUINFO(%r4) 601 std %r3,(PC_DBSAVE+CPUSAVE_R31)(%r4) 602 FRAME_LEAVE(PC_DBSAVE) 603 mtsprg1 %r1 /* prepare for entrance to realtrap */ 604 GET_CPUINFO(%r1) 605 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) 606 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) 607 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) 608 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) 609 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) 610 mflr %r28 611 mfcr %r29 612 ld %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) 613 mtsprg3 %r31 /* SPRG3 was clobbered by FRAME_LEAVE */ 614 mfsprg1 %r1 615 b realtrap 616dbleave: 617 FRAME_LEAVE(PC_DBSAVE) 618 rfid 619 620/* 621 * In case of KDB we want a separate trap catcher for it 622 */ 623 .globl CNAME(dblow),CNAME(dbsize) 624CNAME(dblow): 625 mtsprg1 %r1 /* save SP */ 626 mtsprg2 %r29 /* save r29 */ 627 mfcr %r29 /* save CR in r29 */ 628 mfsrr1 %r1 629 mtcr %r1 630 bf 17,1f /* branch if privileged */ 631 632 /* Unprivileged case */ 633 mtcr %r29 /* put the condition register back */ 634 mfsprg2 %r29 /* ... and r29 */ 635 mflr %r1 /* save LR */ 636 mtsprg2 %r1 /* And then in SPRG2 */ 637 li %r1, 0 /* How to get the vector from LR */ 638 639 bla generictrap /* and we look like a generic trap */ 6401: 641 /* Privileged, so drop to KDB */ 642 GET_CPUINFO(%r1) 643 std %r27,(PC_DBSAVE+CPUSAVE_R27)(%r1) /* free r27 */ 644 std %r28,(PC_DBSAVE+CPUSAVE_R28)(%r1) /* free r28 */ 645 mfsprg2 %r28 /* r29 holds cr... */ 646 std %r28,(PC_DBSAVE+CPUSAVE_R29)(%r1) /* free r29 */ 647 std %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */ 648 std %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */ 649 mflr %r28 /* save LR */ 650 bla dbtrap 651CNAME(dbsize) = .-CNAME(dblow) 652#endif /* KDB */ 653