1 /*- 2 * Copyright (c) 2008 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/bus.h> 34 #include <sys/pcpu.h> 35 #include <sys/proc.h> 36 #include <sys/smp.h> 37 38 #include <machine/bus.h> 39 #include <machine/cpu.h> 40 #include <machine/hid.h> 41 #include <machine/intr_machdep.h> 42 #include <machine/pcb.h> 43 #include <machine/psl.h> 44 #include <machine/smp.h> 45 #include <machine/spr.h> 46 #include <machine/trap_aim.h> 47 48 #include <dev/ofw/openfirm.h> 49 #include <machine/ofw_machdep.h> 50 51 void *ap_pcpu; 52 53 static register_t bsp_state[8] __aligned(8); 54 55 static void cpudep_save_config(void *dummy); 56 SYSINIT(cpu_save_config, SI_SUB_CPU, SI_ORDER_ANY, cpudep_save_config, NULL); 57 58 void 59 cpudep_ap_early_bootstrap(void) 60 { 61 register_t reg; 62 63 __asm __volatile("mtsprg 0, %0" :: "r"(ap_pcpu)); 64 powerpc_sync(); 65 66 switch (mfpvr() >> 16) { 67 case IBM970: 68 case IBM970FX: 69 case IBM970MP: 70 /* Restore HID4 and HID5, which are necessary for the MMU */ 71 72 __asm __volatile("ld %0, 16(%2); sync; isync; \ 73 mtspr %1, %0; sync; isync;" 74 : "=r"(reg) : "K"(SPR_HID4), "r"(bsp_state)); 75 __asm __volatile("ld %0, 24(%2); sync; isync; \ 76 mtspr %1, %0; sync; isync;" 77 : "=r"(reg) : "K"(SPR_HID5), "r"(bsp_state)); 78 powerpc_sync(); 79 break; 80 } 81 } 82 83 uintptr_t 84 cpudep_ap_bootstrap(void) 85 { 86 register_t msr, sp; 87 88 msr = PSL_KERNSET & ~PSL_EE; 89 mtmsr(msr); 90 isync(); 91 92 pcpup->pc_curthread = pcpup->pc_idlethread; 93 pcpup->pc_curpcb = pcpup->pc_curthread->td_pcb; 94 sp = pcpup->pc_curpcb->pcb_sp; 95 96 return (sp); 97 } 98 99 static register_t 100 mpc74xx_l2_enable(register_t l2cr_config) 101 { 102 register_t ccr, bit; 103 uint16_t vers; 104 105 vers = mfpvr() >> 16; 106 switch (vers) { 107 case MPC7400: 108 case MPC7410: 109 bit = L2CR_L2IP; 110 break; 111 default: 112 bit = L2CR_L2I; 113 break; 114 } 115 116 ccr = mfspr(SPR_L2CR); 117 if (ccr & L2CR_L2E) 118 return (ccr); 119 120 /* Configure L2 cache. */ 121 ccr = l2cr_config & ~L2CR_L2E; 122 mtspr(SPR_L2CR, ccr | L2CR_L2I); 123 do { 124 ccr = mfspr(SPR_L2CR); 125 } while (ccr & bit); 126 powerpc_sync(); 127 mtspr(SPR_L2CR, l2cr_config); 128 powerpc_sync(); 129 130 return (l2cr_config); 131 } 132 133 static register_t 134 mpc745x_l3_enable(register_t l3cr_config) 135 { 136 register_t ccr; 137 138 ccr = mfspr(SPR_L3CR); 139 if (ccr & L3CR_L3E) 140 return (ccr); 141 142 /* Configure L3 cache. */ 143 ccr = l3cr_config & ~(L3CR_L3E | L3CR_L3I | L3CR_L3PE | L3CR_L3CLKEN); 144 mtspr(SPR_L3CR, ccr); 145 ccr |= 0x4000000; /* Magic, but documented. */ 146 mtspr(SPR_L3CR, ccr); 147 ccr |= L3CR_L3CLKEN; 148 mtspr(SPR_L3CR, ccr); 149 mtspr(SPR_L3CR, ccr | L3CR_L3I); 150 while (mfspr(SPR_L3CR) & L3CR_L3I) 151 ; 152 mtspr(SPR_L3CR, ccr & ~L3CR_L3CLKEN); 153 powerpc_sync(); 154 DELAY(100); 155 mtspr(SPR_L3CR, ccr); 156 powerpc_sync(); 157 DELAY(100); 158 ccr |= L3CR_L3E; 159 mtspr(SPR_L3CR, ccr); 160 powerpc_sync(); 161 162 return(ccr); 163 } 164 165 static register_t 166 mpc74xx_l1d_enable(void) 167 { 168 register_t hid; 169 170 hid = mfspr(SPR_HID0); 171 if (hid & HID0_DCE) 172 return (hid); 173 174 /* Enable L1 D-cache */ 175 hid |= HID0_DCE; 176 powerpc_sync(); 177 mtspr(SPR_HID0, hid | HID0_DCFI); 178 powerpc_sync(); 179 180 return (hid); 181 } 182 183 static register_t 184 mpc74xx_l1i_enable(void) 185 { 186 register_t hid; 187 188 hid = mfspr(SPR_HID0); 189 if (hid & HID0_ICE) 190 return (hid); 191 192 /* Enable L1 I-cache */ 193 hid |= HID0_ICE; 194 isync(); 195 mtspr(SPR_HID0, hid | HID0_ICFI); 196 isync(); 197 198 return (hid); 199 } 200 201 static void 202 cpudep_save_config(void *dummy) 203 { 204 uint16_t vers; 205 206 vers = mfpvr() >> 16; 207 208 switch(vers) { 209 case IBM970: 210 case IBM970FX: 211 case IBM970MP: 212 #ifdef __powerpc64__ 213 bsp_state[0] = mfspr(SPR_HID0); 214 bsp_state[1] = mfspr(SPR_HID1); 215 bsp_state[2] = mfspr(SPR_HID4); 216 bsp_state[3] = mfspr(SPR_HID5); 217 #else 218 __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32" 219 : "=r" (bsp_state[0]),"=r" (bsp_state[1]) : "K" (SPR_HID0)); 220 __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32" 221 : "=r" (bsp_state[2]),"=r" (bsp_state[3]) : "K" (SPR_HID1)); 222 __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32" 223 : "=r" (bsp_state[4]),"=r" (bsp_state[5]) : "K" (SPR_HID4)); 224 __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32" 225 : "=r" (bsp_state[6]),"=r" (bsp_state[7]) : "K" (SPR_HID5)); 226 #endif 227 228 powerpc_sync(); 229 230 break; 231 case IBMCELLBE: 232 #ifdef NOTYET /* Causes problems if in instruction stream on 970 */ 233 if (mfmsr() & PSL_HV) { 234 bsp_state[0] = mfspr(SPR_HID0); 235 bsp_state[1] = mfspr(SPR_HID1); 236 bsp_state[2] = mfspr(SPR_HID4); 237 bsp_state[3] = mfspr(SPR_HID6); 238 239 bsp_state[4] = mfspr(SPR_CELL_TSCR); 240 } 241 #endif 242 243 bsp_state[5] = mfspr(SPR_CELL_TSRL); 244 245 break; 246 case MPC7450: 247 case MPC7455: 248 case MPC7457: 249 /* Only MPC745x CPUs have an L3 cache. */ 250 bsp_state[3] = mfspr(SPR_L3CR); 251 252 /* Fallthrough */ 253 case MPC7400: 254 case MPC7410: 255 case MPC7447A: 256 case MPC7448: 257 bsp_state[2] = mfspr(SPR_L2CR); 258 bsp_state[1] = mfspr(SPR_HID1); 259 bsp_state[0] = mfspr(SPR_HID0); 260 break; 261 } 262 } 263 264 void 265 cpudep_ap_setup() 266 { 267 register_t reg; 268 uint16_t vers; 269 270 vers = mfpvr() >> 16; 271 272 switch(vers) { 273 case IBM970: 274 case IBM970FX: 275 case IBM970MP: 276 /* Set HIOR to 0 */ 277 __asm __volatile("mtspr 311,%0" :: "r"(0)); 278 powerpc_sync(); 279 280 /* 281 * The 970 has strange rules about how to update HID registers. 282 * See Table 2-3, 970MP manual 283 */ 284 285 __asm __volatile("mtasr %0; sync" :: "r"(0)); 286 __asm __volatile(" \ 287 ld %0,0(%2); \ 288 sync; isync; \ 289 mtspr %1, %0; \ 290 mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \ 291 mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \ 292 sync; isync" 293 : "=r"(reg) : "K"(SPR_HID0), "r"(bsp_state)); 294 __asm __volatile("ld %0, 8(%2); sync; isync; \ 295 mtspr %1, %0; mtspr %1, %0; sync; isync" 296 : "=r"(reg) : "K"(SPR_HID1), "r"(bsp_state)); 297 __asm __volatile("ld %0, 16(%2); sync; isync; \ 298 mtspr %1, %0; sync; isync;" 299 : "=r"(reg) : "K"(SPR_HID4), "r"(bsp_state)); 300 __asm __volatile("ld %0, 24(%2); sync; isync; \ 301 mtspr %1, %0; sync; isync;" 302 : "=r"(reg) : "K"(SPR_HID5), "r"(bsp_state)); 303 304 powerpc_sync(); 305 break; 306 case IBMCELLBE: 307 #ifdef NOTYET /* Causes problems if in instruction stream on 970 */ 308 if (mfmsr() & PSL_HV) { 309 mtspr(SPR_HID0, bsp_state[0]); 310 mtspr(SPR_HID1, bsp_state[1]); 311 mtspr(SPR_HID4, bsp_state[2]); 312 mtspr(SPR_HID6, bsp_state[3]); 313 314 mtspr(SPR_CELL_TSCR, bsp_state[4]); 315 } 316 #endif 317 318 mtspr(SPR_CELL_TSRL, bsp_state[5]); 319 320 break; 321 case MPC7450: 322 case MPC7455: 323 case MPC7457: 324 /* Only MPC745x CPUs have an L3 cache. */ 325 reg = mpc745x_l3_enable(bsp_state[3]); 326 327 /* Fallthrough */ 328 case MPC7400: 329 case MPC7410: 330 case MPC7447A: 331 case MPC7448: 332 /* XXX: Program the CPU ID into PIR */ 333 __asm __volatile("mtspr 1023,%0" :: "r"(PCPU_GET(cpuid))); 334 335 powerpc_sync(); 336 isync(); 337 338 mtspr(SPR_HID0, bsp_state[0]); isync(); 339 mtspr(SPR_HID1, bsp_state[1]); isync(); 340 341 reg = mpc74xx_l2_enable(bsp_state[2]); 342 reg = mpc74xx_l1d_enable(); 343 reg = mpc74xx_l1i_enable(); 344 345 break; 346 default: 347 printf("WARNING: Unknown CPU type. Cache performace may be " 348 "suboptimal.\n"); 349 break; 350 } 351 } 352 353