1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 /*- 30 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 31 * Copyright (C) 1995, 1996 TooLs GmbH. 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. All advertising materials mentioning features or use of this software 43 * must display the following acknowledgement: 44 * This product includes software developed by TooLs GmbH. 45 * 4. The name of TooLs GmbH may not be used to endorse or promote products 46 * derived from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 51 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 52 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 53 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 54 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 55 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 56 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 57 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 * 59 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 60 */ 61 /*- 62 * Copyright (C) 2001 Benno Rice. 63 * All rights reserved. 64 * 65 * Redistribution and use in source and binary forms, with or without 66 * modification, are permitted provided that the following conditions 67 * are met: 68 * 1. Redistributions of source code must retain the above copyright 69 * notice, this list of conditions and the following disclaimer. 70 * 2. Redistributions in binary form must reproduce the above copyright 71 * notice, this list of conditions and the following disclaimer in the 72 * documentation and/or other materials provided with the distribution. 73 * 74 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 75 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 76 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 77 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 78 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 79 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 80 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 81 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 82 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 83 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 84 */ 85 86 #include <sys/cdefs.h> 87 __FBSDID("$FreeBSD$"); 88 89 /* 90 * Manages physical address maps. 91 * 92 * Since the information managed by this module is also stored by the 93 * logical address mapping module, this module may throw away valid virtual 94 * to physical mappings at almost any time. However, invalidations of 95 * mappings must be done as requested. 96 * 97 * In order to cope with hardware architectures which make virtual to 98 * physical map invalidates expensive, this module may delay invalidate 99 * reduced protection operations until such time as they are actually 100 * necessary. This module is given full information as to which processors 101 * are currently using which maps, and to when physical maps must be made 102 * correct. 103 */ 104 105 #include "opt_kstack_pages.h" 106 107 #include <sys/param.h> 108 #include <sys/kernel.h> 109 #include <sys/conf.h> 110 #include <sys/queue.h> 111 #include <sys/cpuset.h> 112 #include <sys/kerneldump.h> 113 #include <sys/ktr.h> 114 #include <sys/lock.h> 115 #include <sys/msgbuf.h> 116 #include <sys/mutex.h> 117 #include <sys/proc.h> 118 #include <sys/rwlock.h> 119 #include <sys/sched.h> 120 #include <sys/sysctl.h> 121 #include <sys/systm.h> 122 #include <sys/vmmeter.h> 123 124 #include <dev/ofw/openfirm.h> 125 126 #include <vm/vm.h> 127 #include <vm/vm_param.h> 128 #include <vm/vm_kern.h> 129 #include <vm/vm_page.h> 130 #include <vm/vm_map.h> 131 #include <vm/vm_object.h> 132 #include <vm/vm_extern.h> 133 #include <vm/vm_pageout.h> 134 #include <vm/uma.h> 135 136 #include <machine/cpu.h> 137 #include <machine/platform.h> 138 #include <machine/bat.h> 139 #include <machine/frame.h> 140 #include <machine/md_var.h> 141 #include <machine/psl.h> 142 #include <machine/pte.h> 143 #include <machine/smp.h> 144 #include <machine/sr.h> 145 #include <machine/mmuvar.h> 146 #include <machine/trap.h> 147 148 #include "mmu_if.h" 149 150 #define MOEA_DEBUG 151 152 #define TODO panic("%s: not implemented", __func__); 153 154 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 155 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 156 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 157 158 struct ofw_map { 159 vm_offset_t om_va; 160 vm_size_t om_len; 161 vm_offset_t om_pa; 162 u_int om_mode; 163 }; 164 165 extern unsigned char _etext[]; 166 extern unsigned char _end[]; 167 168 /* 169 * Map of physical memory regions. 170 */ 171 static struct mem_region *regions; 172 static struct mem_region *pregions; 173 static u_int phys_avail_count; 174 static int regions_sz, pregions_sz; 175 static struct ofw_map *translations; 176 177 /* 178 * Lock for the pteg and pvo tables. 179 */ 180 struct mtx moea_table_mutex; 181 struct mtx moea_vsid_mutex; 182 183 /* tlbie instruction synchronization */ 184 static struct mtx tlbie_mtx; 185 186 /* 187 * PTEG data. 188 */ 189 static struct pteg *moea_pteg_table; 190 u_int moea_pteg_count; 191 u_int moea_pteg_mask; 192 193 /* 194 * PVO data. 195 */ 196 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 197 struct pvo_head moea_pvo_kunmanaged = 198 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 199 200 static struct rwlock_padalign pvh_global_lock; 201 202 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 203 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 204 205 #define BPVO_POOL_SIZE 32768 206 static struct pvo_entry *moea_bpvo_pool; 207 static int moea_bpvo_pool_index = 0; 208 209 #define VSID_NBPW (sizeof(u_int32_t) * 8) 210 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 211 212 static boolean_t moea_initialized = FALSE; 213 214 /* 215 * Statistics. 216 */ 217 u_int moea_pte_valid = 0; 218 u_int moea_pte_overflow = 0; 219 u_int moea_pte_replacements = 0; 220 u_int moea_pvo_entries = 0; 221 u_int moea_pvo_enter_calls = 0; 222 u_int moea_pvo_remove_calls = 0; 223 u_int moea_pte_spills = 0; 224 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 225 0, ""); 226 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 227 &moea_pte_overflow, 0, ""); 228 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 229 &moea_pte_replacements, 0, ""); 230 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 231 0, ""); 232 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 233 &moea_pvo_enter_calls, 0, ""); 234 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 235 &moea_pvo_remove_calls, 0, ""); 236 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 237 &moea_pte_spills, 0, ""); 238 239 /* 240 * Allocate physical memory for use in moea_bootstrap. 241 */ 242 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 243 244 /* 245 * PTE calls. 246 */ 247 static int moea_pte_insert(u_int, struct pte *); 248 249 /* 250 * PVO calls. 251 */ 252 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 253 vm_offset_t, vm_offset_t, u_int, int); 254 static void moea_pvo_remove(struct pvo_entry *, int); 255 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 256 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 257 258 /* 259 * Utility routines. 260 */ 261 static int moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 262 vm_prot_t, u_int, int8_t); 263 static void moea_syncicache(vm_offset_t, vm_size_t); 264 static boolean_t moea_query_bit(vm_page_t, int); 265 static u_int moea_clear_bit(vm_page_t, int); 266 static void moea_kremove(mmu_t, vm_offset_t); 267 int moea_pte_spill(vm_offset_t); 268 269 /* 270 * Kernel MMU interface 271 */ 272 void moea_clear_modify(mmu_t, vm_page_t); 273 void moea_copy_page(mmu_t, vm_page_t, vm_page_t); 274 void moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 275 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 276 int moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, u_int, 277 int8_t); 278 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 279 vm_prot_t); 280 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 281 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 282 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 283 void moea_init(mmu_t); 284 boolean_t moea_is_modified(mmu_t, vm_page_t); 285 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 286 boolean_t moea_is_referenced(mmu_t, vm_page_t); 287 int moea_ts_referenced(mmu_t, vm_page_t); 288 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 289 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 290 int moea_page_wired_mappings(mmu_t, vm_page_t); 291 void moea_pinit(mmu_t, pmap_t); 292 void moea_pinit0(mmu_t, pmap_t); 293 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 294 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 295 void moea_qremove(mmu_t, vm_offset_t, int); 296 void moea_release(mmu_t, pmap_t); 297 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 298 void moea_remove_all(mmu_t, vm_page_t); 299 void moea_remove_write(mmu_t, vm_page_t); 300 void moea_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 301 void moea_zero_page(mmu_t, vm_page_t); 302 void moea_zero_page_area(mmu_t, vm_page_t, int, int); 303 void moea_zero_page_idle(mmu_t, vm_page_t); 304 void moea_activate(mmu_t, struct thread *); 305 void moea_deactivate(mmu_t, struct thread *); 306 void moea_cpu_bootstrap(mmu_t, int); 307 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 308 void *moea_mapdev(mmu_t, vm_paddr_t, vm_size_t); 309 void *moea_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 310 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 311 vm_paddr_t moea_kextract(mmu_t, vm_offset_t); 312 void moea_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t); 313 void moea_kenter(mmu_t, vm_offset_t, vm_paddr_t); 314 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma); 315 boolean_t moea_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 316 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 317 void moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va); 318 void moea_scan_init(mmu_t mmu); 319 320 static mmu_method_t moea_methods[] = { 321 MMUMETHOD(mmu_clear_modify, moea_clear_modify), 322 MMUMETHOD(mmu_copy_page, moea_copy_page), 323 MMUMETHOD(mmu_copy_pages, moea_copy_pages), 324 MMUMETHOD(mmu_enter, moea_enter), 325 MMUMETHOD(mmu_enter_object, moea_enter_object), 326 MMUMETHOD(mmu_enter_quick, moea_enter_quick), 327 MMUMETHOD(mmu_extract, moea_extract), 328 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 329 MMUMETHOD(mmu_init, moea_init), 330 MMUMETHOD(mmu_is_modified, moea_is_modified), 331 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable), 332 MMUMETHOD(mmu_is_referenced, moea_is_referenced), 333 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 334 MMUMETHOD(mmu_map, moea_map), 335 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 336 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 337 MMUMETHOD(mmu_pinit, moea_pinit), 338 MMUMETHOD(mmu_pinit0, moea_pinit0), 339 MMUMETHOD(mmu_protect, moea_protect), 340 MMUMETHOD(mmu_qenter, moea_qenter), 341 MMUMETHOD(mmu_qremove, moea_qremove), 342 MMUMETHOD(mmu_release, moea_release), 343 MMUMETHOD(mmu_remove, moea_remove), 344 MMUMETHOD(mmu_remove_all, moea_remove_all), 345 MMUMETHOD(mmu_remove_write, moea_remove_write), 346 MMUMETHOD(mmu_sync_icache, moea_sync_icache), 347 MMUMETHOD(mmu_unwire, moea_unwire), 348 MMUMETHOD(mmu_zero_page, moea_zero_page), 349 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 350 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle), 351 MMUMETHOD(mmu_activate, moea_activate), 352 MMUMETHOD(mmu_deactivate, moea_deactivate), 353 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr), 354 355 /* Internal interfaces */ 356 MMUMETHOD(mmu_bootstrap, moea_bootstrap), 357 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap), 358 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr), 359 MMUMETHOD(mmu_mapdev, moea_mapdev), 360 MMUMETHOD(mmu_unmapdev, moea_unmapdev), 361 MMUMETHOD(mmu_kextract, moea_kextract), 362 MMUMETHOD(mmu_kenter, moea_kenter), 363 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr), 364 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 365 MMUMETHOD(mmu_scan_init, moea_scan_init), 366 MMUMETHOD(mmu_dumpsys_map, moea_dumpsys_map), 367 368 { 0, 0 } 369 }; 370 371 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0); 372 373 static __inline uint32_t 374 moea_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 375 { 376 uint32_t pte_lo; 377 int i; 378 379 if (ma != VM_MEMATTR_DEFAULT) { 380 switch (ma) { 381 case VM_MEMATTR_UNCACHEABLE: 382 return (PTE_I | PTE_G); 383 case VM_MEMATTR_WRITE_COMBINING: 384 case VM_MEMATTR_WRITE_BACK: 385 case VM_MEMATTR_PREFETCHABLE: 386 return (PTE_I); 387 case VM_MEMATTR_WRITE_THROUGH: 388 return (PTE_W | PTE_M); 389 } 390 } 391 392 /* 393 * Assume the page is cache inhibited and access is guarded unless 394 * it's in our available memory array. 395 */ 396 pte_lo = PTE_I | PTE_G; 397 for (i = 0; i < pregions_sz; i++) { 398 if ((pa >= pregions[i].mr_start) && 399 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 400 pte_lo = PTE_M; 401 break; 402 } 403 } 404 405 return pte_lo; 406 } 407 408 static void 409 tlbie(vm_offset_t va) 410 { 411 412 mtx_lock_spin(&tlbie_mtx); 413 __asm __volatile("ptesync"); 414 __asm __volatile("tlbie %0" :: "r"(va)); 415 __asm __volatile("eieio; tlbsync; ptesync"); 416 mtx_unlock_spin(&tlbie_mtx); 417 } 418 419 static void 420 tlbia(void) 421 { 422 vm_offset_t va; 423 424 for (va = 0; va < 0x00040000; va += 0x00001000) { 425 __asm __volatile("tlbie %0" :: "r"(va)); 426 powerpc_sync(); 427 } 428 __asm __volatile("tlbsync"); 429 powerpc_sync(); 430 } 431 432 static __inline int 433 va_to_sr(u_int *sr, vm_offset_t va) 434 { 435 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 436 } 437 438 static __inline u_int 439 va_to_pteg(u_int sr, vm_offset_t addr) 440 { 441 u_int hash; 442 443 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 444 ADDR_PIDX_SHFT); 445 return (hash & moea_pteg_mask); 446 } 447 448 static __inline struct pvo_head * 449 vm_page_to_pvoh(vm_page_t m) 450 { 451 452 return (&m->md.mdpg_pvoh); 453 } 454 455 static __inline void 456 moea_attr_clear(vm_page_t m, int ptebit) 457 { 458 459 rw_assert(&pvh_global_lock, RA_WLOCKED); 460 m->md.mdpg_attrs &= ~ptebit; 461 } 462 463 static __inline int 464 moea_attr_fetch(vm_page_t m) 465 { 466 467 return (m->md.mdpg_attrs); 468 } 469 470 static __inline void 471 moea_attr_save(vm_page_t m, int ptebit) 472 { 473 474 rw_assert(&pvh_global_lock, RA_WLOCKED); 475 m->md.mdpg_attrs |= ptebit; 476 } 477 478 static __inline int 479 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 480 { 481 if (pt->pte_hi == pvo_pt->pte_hi) 482 return (1); 483 484 return (0); 485 } 486 487 static __inline int 488 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 489 { 490 return (pt->pte_hi & ~PTE_VALID) == 491 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 492 ((va >> ADDR_API_SHFT) & PTE_API) | which); 493 } 494 495 static __inline void 496 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 497 { 498 499 mtx_assert(&moea_table_mutex, MA_OWNED); 500 501 /* 502 * Construct a PTE. Default to IMB initially. Valid bit only gets 503 * set when the real pte is set in memory. 504 * 505 * Note: Don't set the valid bit for correct operation of tlb update. 506 */ 507 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 508 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 509 pt->pte_lo = pte_lo; 510 } 511 512 static __inline void 513 moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 514 { 515 516 mtx_assert(&moea_table_mutex, MA_OWNED); 517 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 518 } 519 520 static __inline void 521 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 522 { 523 524 mtx_assert(&moea_table_mutex, MA_OWNED); 525 526 /* 527 * As shown in Section 7.6.3.2.3 528 */ 529 pt->pte_lo &= ~ptebit; 530 tlbie(va); 531 } 532 533 static __inline void 534 moea_pte_set(struct pte *pt, struct pte *pvo_pt) 535 { 536 537 mtx_assert(&moea_table_mutex, MA_OWNED); 538 pvo_pt->pte_hi |= PTE_VALID; 539 540 /* 541 * Update the PTE as defined in section 7.6.3.1. 542 * Note that the REF/CHG bits are from pvo_pt and thus should have 543 * been saved so this routine can restore them (if desired). 544 */ 545 pt->pte_lo = pvo_pt->pte_lo; 546 powerpc_sync(); 547 pt->pte_hi = pvo_pt->pte_hi; 548 powerpc_sync(); 549 moea_pte_valid++; 550 } 551 552 static __inline void 553 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 554 { 555 556 mtx_assert(&moea_table_mutex, MA_OWNED); 557 pvo_pt->pte_hi &= ~PTE_VALID; 558 559 /* 560 * Force the reg & chg bits back into the PTEs. 561 */ 562 powerpc_sync(); 563 564 /* 565 * Invalidate the pte. 566 */ 567 pt->pte_hi &= ~PTE_VALID; 568 569 tlbie(va); 570 571 /* 572 * Save the reg & chg bits. 573 */ 574 moea_pte_synch(pt, pvo_pt); 575 moea_pte_valid--; 576 } 577 578 static __inline void 579 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 580 { 581 582 /* 583 * Invalidate the PTE 584 */ 585 moea_pte_unset(pt, pvo_pt, va); 586 moea_pte_set(pt, pvo_pt); 587 } 588 589 /* 590 * Quick sort callout for comparing memory regions. 591 */ 592 static int om_cmp(const void *a, const void *b); 593 594 static int 595 om_cmp(const void *a, const void *b) 596 { 597 const struct ofw_map *mapa; 598 const struct ofw_map *mapb; 599 600 mapa = a; 601 mapb = b; 602 if (mapa->om_pa < mapb->om_pa) 603 return (-1); 604 else if (mapa->om_pa > mapb->om_pa) 605 return (1); 606 else 607 return (0); 608 } 609 610 void 611 moea_cpu_bootstrap(mmu_t mmup, int ap) 612 { 613 u_int sdr; 614 int i; 615 616 if (ap) { 617 powerpc_sync(); 618 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 619 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 620 isync(); 621 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 622 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 623 isync(); 624 } 625 626 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 627 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 628 isync(); 629 630 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 631 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 632 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 633 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 634 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 635 isync(); 636 637 for (i = 0; i < 16; i++) 638 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 639 powerpc_sync(); 640 641 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 642 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 643 isync(); 644 645 tlbia(); 646 } 647 648 void 649 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 650 { 651 ihandle_t mmui; 652 phandle_t chosen, mmu; 653 int sz; 654 int i, j; 655 vm_size_t size, physsz, hwphyssz; 656 vm_offset_t pa, va, off; 657 void *dpcpu; 658 register_t msr; 659 660 /* 661 * Set up BAT0 to map the lowest 256 MB area 662 */ 663 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 664 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 665 666 /* 667 * Map PCI memory space. 668 */ 669 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 670 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 671 672 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 673 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 674 675 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 676 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 677 678 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 679 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 680 681 /* 682 * Map obio devices. 683 */ 684 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 685 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 686 687 /* 688 * Use an IBAT and a DBAT to map the bottom segment of memory 689 * where we are. Turn off instruction relocation temporarily 690 * to prevent faults while reprogramming the IBAT. 691 */ 692 msr = mfmsr(); 693 mtmsr(msr & ~PSL_IR); 694 __asm (".balign 32; \n" 695 "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 696 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 697 :: "r"(battable[0].batu), "r"(battable[0].batl)); 698 mtmsr(msr); 699 700 /* map pci space */ 701 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 702 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 703 isync(); 704 705 /* set global direct map flag */ 706 hw_direct_map = 1; 707 708 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 709 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 710 711 for (i = 0; i < pregions_sz; i++) { 712 vm_offset_t pa; 713 vm_offset_t end; 714 715 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 716 pregions[i].mr_start, 717 pregions[i].mr_start + pregions[i].mr_size, 718 pregions[i].mr_size); 719 /* 720 * Install entries into the BAT table to allow all 721 * of physmem to be convered by on-demand BAT entries. 722 * The loop will sometimes set the same battable element 723 * twice, but that's fine since they won't be used for 724 * a while yet. 725 */ 726 pa = pregions[i].mr_start & 0xf0000000; 727 end = pregions[i].mr_start + pregions[i].mr_size; 728 do { 729 u_int n = pa >> ADDR_SR_SHFT; 730 731 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 732 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 733 pa += SEGMENT_LENGTH; 734 } while (pa < end); 735 } 736 737 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 738 panic("moea_bootstrap: phys_avail too small"); 739 740 phys_avail_count = 0; 741 physsz = 0; 742 hwphyssz = 0; 743 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 744 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 745 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 746 regions[i].mr_start + regions[i].mr_size, 747 regions[i].mr_size); 748 if (hwphyssz != 0 && 749 (physsz + regions[i].mr_size) >= hwphyssz) { 750 if (physsz < hwphyssz) { 751 phys_avail[j] = regions[i].mr_start; 752 phys_avail[j + 1] = regions[i].mr_start + 753 hwphyssz - physsz; 754 physsz = hwphyssz; 755 phys_avail_count++; 756 } 757 break; 758 } 759 phys_avail[j] = regions[i].mr_start; 760 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 761 phys_avail_count++; 762 physsz += regions[i].mr_size; 763 } 764 765 /* Check for overlap with the kernel and exception vectors */ 766 for (j = 0; j < 2*phys_avail_count; j+=2) { 767 if (phys_avail[j] < EXC_LAST) 768 phys_avail[j] += EXC_LAST; 769 770 if (kernelstart >= phys_avail[j] && 771 kernelstart < phys_avail[j+1]) { 772 if (kernelend < phys_avail[j+1]) { 773 phys_avail[2*phys_avail_count] = 774 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 775 phys_avail[2*phys_avail_count + 1] = 776 phys_avail[j+1]; 777 phys_avail_count++; 778 } 779 780 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 781 } 782 783 if (kernelend >= phys_avail[j] && 784 kernelend < phys_avail[j+1]) { 785 if (kernelstart > phys_avail[j]) { 786 phys_avail[2*phys_avail_count] = phys_avail[j]; 787 phys_avail[2*phys_avail_count + 1] = 788 kernelstart & ~PAGE_MASK; 789 phys_avail_count++; 790 } 791 792 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 793 } 794 } 795 796 physmem = btoc(physsz); 797 798 /* 799 * Allocate PTEG table. 800 */ 801 #ifdef PTEGCOUNT 802 moea_pteg_count = PTEGCOUNT; 803 #else 804 moea_pteg_count = 0x1000; 805 806 while (moea_pteg_count < physmem) 807 moea_pteg_count <<= 1; 808 809 moea_pteg_count >>= 1; 810 #endif /* PTEGCOUNT */ 811 812 size = moea_pteg_count * sizeof(struct pteg); 813 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 814 size); 815 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 816 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 817 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 818 moea_pteg_mask = moea_pteg_count - 1; 819 820 /* 821 * Allocate pv/overflow lists. 822 */ 823 size = sizeof(struct pvo_head) * moea_pteg_count; 824 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 825 PAGE_SIZE); 826 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 827 for (i = 0; i < moea_pteg_count; i++) 828 LIST_INIT(&moea_pvo_table[i]); 829 830 /* 831 * Initialize the lock that synchronizes access to the pteg and pvo 832 * tables. 833 */ 834 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 835 MTX_RECURSE); 836 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 837 838 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 839 840 /* 841 * Initialise the unmanaged pvo pool. 842 */ 843 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 844 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 845 moea_bpvo_pool_index = 0; 846 847 /* 848 * Make sure kernel vsid is allocated as well as VSID 0. 849 */ 850 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 851 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 852 moea_vsid_bitmap[0] |= 1; 853 854 /* 855 * Initialize the kernel pmap (which is statically allocated). 856 */ 857 PMAP_LOCK_INIT(kernel_pmap); 858 for (i = 0; i < 16; i++) 859 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 860 CPU_FILL(&kernel_pmap->pm_active); 861 RB_INIT(&kernel_pmap->pmap_pvo); 862 863 /* 864 * Initialize the global pv list lock. 865 */ 866 rw_init(&pvh_global_lock, "pmap pv global"); 867 868 /* 869 * Set up the Open Firmware mappings 870 */ 871 chosen = OF_finddevice("/chosen"); 872 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 && 873 (mmu = OF_instance_to_package(mmui)) != -1 && 874 (sz = OF_getproplen(mmu, "translations")) != -1) { 875 translations = NULL; 876 for (i = 0; phys_avail[i] != 0; i += 2) { 877 if (phys_avail[i + 1] >= sz) { 878 translations = (struct ofw_map *)phys_avail[i]; 879 break; 880 } 881 } 882 if (translations == NULL) 883 panic("moea_bootstrap: no space to copy translations"); 884 bzero(translations, sz); 885 if (OF_getprop(mmu, "translations", translations, sz) == -1) 886 panic("moea_bootstrap: can't get ofw translations"); 887 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 888 sz /= sizeof(*translations); 889 qsort(translations, sz, sizeof (*translations), om_cmp); 890 for (i = 0; i < sz; i++) { 891 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 892 translations[i].om_pa, translations[i].om_va, 893 translations[i].om_len); 894 895 /* 896 * If the mapping is 1:1, let the RAM and device 897 * on-demand BAT tables take care of the translation. 898 */ 899 if (translations[i].om_va == translations[i].om_pa) 900 continue; 901 902 /* Enter the pages */ 903 for (off = 0; off < translations[i].om_len; 904 off += PAGE_SIZE) 905 moea_kenter(mmup, translations[i].om_va + off, 906 translations[i].om_pa + off); 907 } 908 } 909 910 /* 911 * Calculate the last available physical address. 912 */ 913 for (i = 0; phys_avail[i + 2] != 0; i += 2) 914 ; 915 Maxmem = powerpc_btop(phys_avail[i + 1]); 916 917 moea_cpu_bootstrap(mmup,0); 918 919 pmap_bootstrapped++; 920 921 /* 922 * Set the start and end of kva. 923 */ 924 virtual_avail = VM_MIN_KERNEL_ADDRESS; 925 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 926 927 /* 928 * Allocate a kernel stack with a guard page for thread0 and map it 929 * into the kernel page map. 930 */ 931 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 932 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 933 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 934 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 935 thread0.td_kstack = va; 936 thread0.td_kstack_pages = KSTACK_PAGES; 937 for (i = 0; i < KSTACK_PAGES; i++) { 938 moea_kenter(mmup, va, pa); 939 pa += PAGE_SIZE; 940 va += PAGE_SIZE; 941 } 942 943 /* 944 * Allocate virtual address space for the message buffer. 945 */ 946 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE); 947 msgbufp = (struct msgbuf *)virtual_avail; 948 va = virtual_avail; 949 virtual_avail += round_page(msgbufsize); 950 while (va < virtual_avail) { 951 moea_kenter(mmup, va, pa); 952 pa += PAGE_SIZE; 953 va += PAGE_SIZE; 954 } 955 956 /* 957 * Allocate virtual address space for the dynamic percpu area. 958 */ 959 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 960 dpcpu = (void *)virtual_avail; 961 va = virtual_avail; 962 virtual_avail += DPCPU_SIZE; 963 while (va < virtual_avail) { 964 moea_kenter(mmup, va, pa); 965 pa += PAGE_SIZE; 966 va += PAGE_SIZE; 967 } 968 dpcpu_init(dpcpu, 0); 969 } 970 971 /* 972 * Activate a user pmap. The pmap must be activated before it's address 973 * space can be accessed in any way. 974 */ 975 void 976 moea_activate(mmu_t mmu, struct thread *td) 977 { 978 pmap_t pm, pmr; 979 980 /* 981 * Load all the data we need up front to encourage the compiler to 982 * not issue any loads while we have interrupts disabled below. 983 */ 984 pm = &td->td_proc->p_vmspace->vm_pmap; 985 pmr = pm->pmap_phys; 986 987 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 988 PCPU_SET(curpmap, pmr); 989 } 990 991 void 992 moea_deactivate(mmu_t mmu, struct thread *td) 993 { 994 pmap_t pm; 995 996 pm = &td->td_proc->p_vmspace->vm_pmap; 997 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 998 PCPU_SET(curpmap, NULL); 999 } 1000 1001 void 1002 moea_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1003 { 1004 struct pvo_entry key, *pvo; 1005 1006 PMAP_LOCK(pm); 1007 key.pvo_vaddr = sva; 1008 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1009 pvo != NULL && PVO_VADDR(pvo) < eva; 1010 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1011 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1012 panic("moea_unwire: pvo %p is missing PVO_WIRED", pvo); 1013 pvo->pvo_vaddr &= ~PVO_WIRED; 1014 pm->pm_stats.wired_count--; 1015 } 1016 PMAP_UNLOCK(pm); 1017 } 1018 1019 void 1020 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1021 { 1022 vm_offset_t dst; 1023 vm_offset_t src; 1024 1025 dst = VM_PAGE_TO_PHYS(mdst); 1026 src = VM_PAGE_TO_PHYS(msrc); 1027 1028 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1029 } 1030 1031 void 1032 moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1033 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1034 { 1035 void *a_cp, *b_cp; 1036 vm_offset_t a_pg_offset, b_pg_offset; 1037 int cnt; 1038 1039 while (xfersize > 0) { 1040 a_pg_offset = a_offset & PAGE_MASK; 1041 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1042 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1043 a_pg_offset; 1044 b_pg_offset = b_offset & PAGE_MASK; 1045 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1046 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1047 b_pg_offset; 1048 bcopy(a_cp, b_cp, cnt); 1049 a_offset += cnt; 1050 b_offset += cnt; 1051 xfersize -= cnt; 1052 } 1053 } 1054 1055 /* 1056 * Zero a page of physical memory by temporarily mapping it into the tlb. 1057 */ 1058 void 1059 moea_zero_page(mmu_t mmu, vm_page_t m) 1060 { 1061 vm_offset_t off, pa = VM_PAGE_TO_PHYS(m); 1062 1063 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1064 __asm __volatile("dcbz 0,%0" :: "r"(pa + off)); 1065 } 1066 1067 void 1068 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1069 { 1070 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1071 void *va = (void *)(pa + off); 1072 1073 bzero(va, size); 1074 } 1075 1076 void 1077 moea_zero_page_idle(mmu_t mmu, vm_page_t m) 1078 { 1079 1080 moea_zero_page(mmu, m); 1081 } 1082 1083 /* 1084 * Map the given physical page at the specified virtual address in the 1085 * target pmap with the protection requested. If specified the page 1086 * will be wired down. 1087 */ 1088 int 1089 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1090 u_int flags, int8_t psind) 1091 { 1092 int error; 1093 1094 for (;;) { 1095 rw_wlock(&pvh_global_lock); 1096 PMAP_LOCK(pmap); 1097 error = moea_enter_locked(pmap, va, m, prot, flags, psind); 1098 rw_wunlock(&pvh_global_lock); 1099 PMAP_UNLOCK(pmap); 1100 if (error != ENOMEM) 1101 return (KERN_SUCCESS); 1102 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1103 return (KERN_RESOURCE_SHORTAGE); 1104 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1105 VM_WAIT; 1106 } 1107 } 1108 1109 /* 1110 * Map the given physical page at the specified virtual address in the 1111 * target pmap with the protection requested. If specified the page 1112 * will be wired down. 1113 * 1114 * The global pvh and pmap must be locked. 1115 */ 1116 static int 1117 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1118 u_int flags, int8_t psind __unused) 1119 { 1120 struct pvo_head *pvo_head; 1121 uma_zone_t zone; 1122 u_int pte_lo, pvo_flags; 1123 int error; 1124 1125 if (pmap_bootstrapped) 1126 rw_assert(&pvh_global_lock, RA_WLOCKED); 1127 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1128 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1129 VM_OBJECT_ASSERT_LOCKED(m->object); 1130 1131 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea_initialized) { 1132 pvo_head = &moea_pvo_kunmanaged; 1133 zone = moea_upvo_zone; 1134 pvo_flags = 0; 1135 } else { 1136 pvo_head = vm_page_to_pvoh(m); 1137 zone = moea_mpvo_zone; 1138 pvo_flags = PVO_MANAGED; 1139 } 1140 1141 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1142 1143 if (prot & VM_PROT_WRITE) { 1144 pte_lo |= PTE_BW; 1145 if (pmap_bootstrapped && 1146 (m->oflags & VPO_UNMANAGED) == 0) 1147 vm_page_aflag_set(m, PGA_WRITEABLE); 1148 } else 1149 pte_lo |= PTE_BR; 1150 1151 if ((flags & PMAP_ENTER_WIRED) != 0) 1152 pvo_flags |= PVO_WIRED; 1153 1154 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1155 pte_lo, pvo_flags); 1156 1157 /* 1158 * Flush the real page from the instruction cache. This has be done 1159 * for all user mappings to prevent information leakage via the 1160 * instruction cache. moea_pvo_enter() returns ENOENT for the first 1161 * mapping for a page. 1162 */ 1163 if (pmap != kernel_pmap && error == ENOENT && 1164 (pte_lo & (PTE_I | PTE_G)) == 0) 1165 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1166 1167 return (error); 1168 } 1169 1170 /* 1171 * Maps a sequence of resident pages belonging to the same object. 1172 * The sequence begins with the given page m_start. This page is 1173 * mapped at the given virtual address start. Each subsequent page is 1174 * mapped at a virtual address that is offset from start by the same 1175 * amount as the page is offset from m_start within the object. The 1176 * last page in the sequence is the page with the largest offset from 1177 * m_start that can be mapped at a virtual address less than the given 1178 * virtual address end. Not every virtual page between start and end 1179 * is mapped; only those for which a resident page exists with the 1180 * corresponding offset from m_start are mapped. 1181 */ 1182 void 1183 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1184 vm_page_t m_start, vm_prot_t prot) 1185 { 1186 vm_page_t m; 1187 vm_pindex_t diff, psize; 1188 1189 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1190 1191 psize = atop(end - start); 1192 m = m_start; 1193 rw_wlock(&pvh_global_lock); 1194 PMAP_LOCK(pm); 1195 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1196 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1197 (VM_PROT_READ | VM_PROT_EXECUTE), 0, 0); 1198 m = TAILQ_NEXT(m, listq); 1199 } 1200 rw_wunlock(&pvh_global_lock); 1201 PMAP_UNLOCK(pm); 1202 } 1203 1204 void 1205 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1206 vm_prot_t prot) 1207 { 1208 1209 rw_wlock(&pvh_global_lock); 1210 PMAP_LOCK(pm); 1211 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1212 0, 0); 1213 rw_wunlock(&pvh_global_lock); 1214 PMAP_UNLOCK(pm); 1215 } 1216 1217 vm_paddr_t 1218 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1219 { 1220 struct pvo_entry *pvo; 1221 vm_paddr_t pa; 1222 1223 PMAP_LOCK(pm); 1224 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1225 if (pvo == NULL) 1226 pa = 0; 1227 else 1228 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1229 PMAP_UNLOCK(pm); 1230 return (pa); 1231 } 1232 1233 /* 1234 * Atomically extract and hold the physical page with the given 1235 * pmap and virtual address pair if that mapping permits the given 1236 * protection. 1237 */ 1238 vm_page_t 1239 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1240 { 1241 struct pvo_entry *pvo; 1242 vm_page_t m; 1243 vm_paddr_t pa; 1244 1245 m = NULL; 1246 pa = 0; 1247 PMAP_LOCK(pmap); 1248 retry: 1249 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1250 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1251 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1252 (prot & VM_PROT_WRITE) == 0)) { 1253 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa)) 1254 goto retry; 1255 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1256 vm_page_hold(m); 1257 } 1258 PA_UNLOCK_COND(pa); 1259 PMAP_UNLOCK(pmap); 1260 return (m); 1261 } 1262 1263 void 1264 moea_init(mmu_t mmu) 1265 { 1266 1267 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1268 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1269 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1270 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1271 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1272 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1273 moea_initialized = TRUE; 1274 } 1275 1276 boolean_t 1277 moea_is_referenced(mmu_t mmu, vm_page_t m) 1278 { 1279 boolean_t rv; 1280 1281 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1282 ("moea_is_referenced: page %p is not managed", m)); 1283 rw_wlock(&pvh_global_lock); 1284 rv = moea_query_bit(m, PTE_REF); 1285 rw_wunlock(&pvh_global_lock); 1286 return (rv); 1287 } 1288 1289 boolean_t 1290 moea_is_modified(mmu_t mmu, vm_page_t m) 1291 { 1292 boolean_t rv; 1293 1294 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1295 ("moea_is_modified: page %p is not managed", m)); 1296 1297 /* 1298 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1299 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1300 * is clear, no PTEs can have PTE_CHG set. 1301 */ 1302 VM_OBJECT_ASSERT_WLOCKED(m->object); 1303 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1304 return (FALSE); 1305 rw_wlock(&pvh_global_lock); 1306 rv = moea_query_bit(m, PTE_CHG); 1307 rw_wunlock(&pvh_global_lock); 1308 return (rv); 1309 } 1310 1311 boolean_t 1312 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1313 { 1314 struct pvo_entry *pvo; 1315 boolean_t rv; 1316 1317 PMAP_LOCK(pmap); 1318 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1319 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0; 1320 PMAP_UNLOCK(pmap); 1321 return (rv); 1322 } 1323 1324 void 1325 moea_clear_modify(mmu_t mmu, vm_page_t m) 1326 { 1327 1328 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1329 ("moea_clear_modify: page %p is not managed", m)); 1330 VM_OBJECT_ASSERT_WLOCKED(m->object); 1331 KASSERT(!vm_page_xbusied(m), 1332 ("moea_clear_modify: page %p is exclusive busy", m)); 1333 1334 /* 1335 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG 1336 * set. If the object containing the page is locked and the page is 1337 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1338 */ 1339 if ((m->aflags & PGA_WRITEABLE) == 0) 1340 return; 1341 rw_wlock(&pvh_global_lock); 1342 moea_clear_bit(m, PTE_CHG); 1343 rw_wunlock(&pvh_global_lock); 1344 } 1345 1346 /* 1347 * Clear the write and modified bits in each of the given page's mappings. 1348 */ 1349 void 1350 moea_remove_write(mmu_t mmu, vm_page_t m) 1351 { 1352 struct pvo_entry *pvo; 1353 struct pte *pt; 1354 pmap_t pmap; 1355 u_int lo; 1356 1357 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1358 ("moea_remove_write: page %p is not managed", m)); 1359 1360 /* 1361 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1362 * set by another thread while the object is locked. Thus, 1363 * if PGA_WRITEABLE is clear, no page table entries need updating. 1364 */ 1365 VM_OBJECT_ASSERT_WLOCKED(m->object); 1366 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1367 return; 1368 rw_wlock(&pvh_global_lock); 1369 lo = moea_attr_fetch(m); 1370 powerpc_sync(); 1371 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1372 pmap = pvo->pvo_pmap; 1373 PMAP_LOCK(pmap); 1374 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1375 pt = moea_pvo_to_pte(pvo, -1); 1376 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1377 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1378 if (pt != NULL) { 1379 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1380 lo |= pvo->pvo_pte.pte.pte_lo; 1381 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1382 moea_pte_change(pt, &pvo->pvo_pte.pte, 1383 pvo->pvo_vaddr); 1384 mtx_unlock(&moea_table_mutex); 1385 } 1386 } 1387 PMAP_UNLOCK(pmap); 1388 } 1389 if ((lo & PTE_CHG) != 0) { 1390 moea_attr_clear(m, PTE_CHG); 1391 vm_page_dirty(m); 1392 } 1393 vm_page_aflag_clear(m, PGA_WRITEABLE); 1394 rw_wunlock(&pvh_global_lock); 1395 } 1396 1397 /* 1398 * moea_ts_referenced: 1399 * 1400 * Return a count of reference bits for a page, clearing those bits. 1401 * It is not necessary for every reference bit to be cleared, but it 1402 * is necessary that 0 only be returned when there are truly no 1403 * reference bits set. 1404 * 1405 * XXX: The exact number of bits to check and clear is a matter that 1406 * should be tested and standardized at some point in the future for 1407 * optimal aging of shared pages. 1408 */ 1409 int 1410 moea_ts_referenced(mmu_t mmu, vm_page_t m) 1411 { 1412 int count; 1413 1414 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1415 ("moea_ts_referenced: page %p is not managed", m)); 1416 rw_wlock(&pvh_global_lock); 1417 count = moea_clear_bit(m, PTE_REF); 1418 rw_wunlock(&pvh_global_lock); 1419 return (count); 1420 } 1421 1422 /* 1423 * Modify the WIMG settings of all mappings for a page. 1424 */ 1425 void 1426 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1427 { 1428 struct pvo_entry *pvo; 1429 struct pvo_head *pvo_head; 1430 struct pte *pt; 1431 pmap_t pmap; 1432 u_int lo; 1433 1434 if ((m->oflags & VPO_UNMANAGED) != 0) { 1435 m->md.mdpg_cache_attrs = ma; 1436 return; 1437 } 1438 1439 rw_wlock(&pvh_global_lock); 1440 pvo_head = vm_page_to_pvoh(m); 1441 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1442 1443 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1444 pmap = pvo->pvo_pmap; 1445 PMAP_LOCK(pmap); 1446 pt = moea_pvo_to_pte(pvo, -1); 1447 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG; 1448 pvo->pvo_pte.pte.pte_lo |= lo; 1449 if (pt != NULL) { 1450 moea_pte_change(pt, &pvo->pvo_pte.pte, 1451 pvo->pvo_vaddr); 1452 if (pvo->pvo_pmap == kernel_pmap) 1453 isync(); 1454 } 1455 mtx_unlock(&moea_table_mutex); 1456 PMAP_UNLOCK(pmap); 1457 } 1458 m->md.mdpg_cache_attrs = ma; 1459 rw_wunlock(&pvh_global_lock); 1460 } 1461 1462 /* 1463 * Map a wired page into kernel virtual address space. 1464 */ 1465 void 1466 moea_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1467 { 1468 1469 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1470 } 1471 1472 void 1473 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1474 { 1475 u_int pte_lo; 1476 int error; 1477 1478 #if 0 1479 if (va < VM_MIN_KERNEL_ADDRESS) 1480 panic("moea_kenter: attempt to enter non-kernel address %#x", 1481 va); 1482 #endif 1483 1484 pte_lo = moea_calc_wimg(pa, ma); 1485 1486 PMAP_LOCK(kernel_pmap); 1487 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1488 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1489 1490 if (error != 0 && error != ENOENT) 1491 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1492 pa, error); 1493 1494 PMAP_UNLOCK(kernel_pmap); 1495 } 1496 1497 /* 1498 * Extract the physical page address associated with the given kernel virtual 1499 * address. 1500 */ 1501 vm_paddr_t 1502 moea_kextract(mmu_t mmu, vm_offset_t va) 1503 { 1504 struct pvo_entry *pvo; 1505 vm_paddr_t pa; 1506 1507 /* 1508 * Allow direct mappings on 32-bit OEA 1509 */ 1510 if (va < VM_MIN_KERNEL_ADDRESS) { 1511 return (va); 1512 } 1513 1514 PMAP_LOCK(kernel_pmap); 1515 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1516 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1517 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1518 PMAP_UNLOCK(kernel_pmap); 1519 return (pa); 1520 } 1521 1522 /* 1523 * Remove a wired page from kernel virtual address space. 1524 */ 1525 void 1526 moea_kremove(mmu_t mmu, vm_offset_t va) 1527 { 1528 1529 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1530 } 1531 1532 /* 1533 * Map a range of physical addresses into kernel virtual address space. 1534 * 1535 * The value passed in *virt is a suggested virtual address for the mapping. 1536 * Architectures which can support a direct-mapped physical to virtual region 1537 * can return the appropriate address within that region, leaving '*virt' 1538 * unchanged. We cannot and therefore do not; *virt is updated with the 1539 * first usable address after the mapped region. 1540 */ 1541 vm_offset_t 1542 moea_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1543 vm_paddr_t pa_end, int prot) 1544 { 1545 vm_offset_t sva, va; 1546 1547 sva = *virt; 1548 va = sva; 1549 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1550 moea_kenter(mmu, va, pa_start); 1551 *virt = va; 1552 return (sva); 1553 } 1554 1555 /* 1556 * Returns true if the pmap's pv is one of the first 1557 * 16 pvs linked to from this page. This count may 1558 * be changed upwards or downwards in the future; it 1559 * is only necessary that true be returned for a small 1560 * subset of pmaps for proper page aging. 1561 */ 1562 boolean_t 1563 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1564 { 1565 int loops; 1566 struct pvo_entry *pvo; 1567 boolean_t rv; 1568 1569 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1570 ("moea_page_exists_quick: page %p is not managed", m)); 1571 loops = 0; 1572 rv = FALSE; 1573 rw_wlock(&pvh_global_lock); 1574 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1575 if (pvo->pvo_pmap == pmap) { 1576 rv = TRUE; 1577 break; 1578 } 1579 if (++loops >= 16) 1580 break; 1581 } 1582 rw_wunlock(&pvh_global_lock); 1583 return (rv); 1584 } 1585 1586 /* 1587 * Return the number of managed mappings to the given physical page 1588 * that are wired. 1589 */ 1590 int 1591 moea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1592 { 1593 struct pvo_entry *pvo; 1594 int count; 1595 1596 count = 0; 1597 if ((m->oflags & VPO_UNMANAGED) != 0) 1598 return (count); 1599 rw_wlock(&pvh_global_lock); 1600 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1601 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1602 count++; 1603 rw_wunlock(&pvh_global_lock); 1604 return (count); 1605 } 1606 1607 static u_int moea_vsidcontext; 1608 1609 void 1610 moea_pinit(mmu_t mmu, pmap_t pmap) 1611 { 1612 int i, mask; 1613 u_int entropy; 1614 1615 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1616 RB_INIT(&pmap->pmap_pvo); 1617 1618 entropy = 0; 1619 __asm __volatile("mftb %0" : "=r"(entropy)); 1620 1621 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap)) 1622 == NULL) { 1623 pmap->pmap_phys = pmap; 1624 } 1625 1626 1627 mtx_lock(&moea_vsid_mutex); 1628 /* 1629 * Allocate some segment registers for this pmap. 1630 */ 1631 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1632 u_int hash, n; 1633 1634 /* 1635 * Create a new value by mutiplying by a prime and adding in 1636 * entropy from the timebase register. This is to make the 1637 * VSID more random so that the PT hash function collides 1638 * less often. (Note that the prime casues gcc to do shifts 1639 * instead of a multiply.) 1640 */ 1641 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1642 hash = moea_vsidcontext & (NPMAPS - 1); 1643 if (hash == 0) /* 0 is special, avoid it */ 1644 continue; 1645 n = hash >> 5; 1646 mask = 1 << (hash & (VSID_NBPW - 1)); 1647 hash = (moea_vsidcontext & 0xfffff); 1648 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1649 /* anything free in this bucket? */ 1650 if (moea_vsid_bitmap[n] == 0xffffffff) { 1651 entropy = (moea_vsidcontext >> 20); 1652 continue; 1653 } 1654 i = ffs(~moea_vsid_bitmap[n]) - 1; 1655 mask = 1 << i; 1656 hash &= 0xfffff & ~(VSID_NBPW - 1); 1657 hash |= i; 1658 } 1659 KASSERT(!(moea_vsid_bitmap[n] & mask), 1660 ("Allocating in-use VSID group %#x\n", hash)); 1661 moea_vsid_bitmap[n] |= mask; 1662 for (i = 0; i < 16; i++) 1663 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1664 mtx_unlock(&moea_vsid_mutex); 1665 return; 1666 } 1667 1668 mtx_unlock(&moea_vsid_mutex); 1669 panic("moea_pinit: out of segments"); 1670 } 1671 1672 /* 1673 * Initialize the pmap associated with process 0. 1674 */ 1675 void 1676 moea_pinit0(mmu_t mmu, pmap_t pm) 1677 { 1678 1679 PMAP_LOCK_INIT(pm); 1680 moea_pinit(mmu, pm); 1681 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1682 } 1683 1684 /* 1685 * Set the physical protection on the specified range of this map as requested. 1686 */ 1687 void 1688 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1689 vm_prot_t prot) 1690 { 1691 struct pvo_entry *pvo, *tpvo, key; 1692 struct pte *pt; 1693 1694 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1695 ("moea_protect: non current pmap")); 1696 1697 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1698 moea_remove(mmu, pm, sva, eva); 1699 return; 1700 } 1701 1702 rw_wlock(&pvh_global_lock); 1703 PMAP_LOCK(pm); 1704 key.pvo_vaddr = sva; 1705 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1706 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1707 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1708 1709 /* 1710 * Grab the PTE pointer before we diddle with the cached PTE 1711 * copy. 1712 */ 1713 pt = moea_pvo_to_pte(pvo, -1); 1714 /* 1715 * Change the protection of the page. 1716 */ 1717 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1718 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1719 1720 /* 1721 * If the PVO is in the page table, update that pte as well. 1722 */ 1723 if (pt != NULL) { 1724 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1725 mtx_unlock(&moea_table_mutex); 1726 } 1727 } 1728 rw_wunlock(&pvh_global_lock); 1729 PMAP_UNLOCK(pm); 1730 } 1731 1732 /* 1733 * Map a list of wired pages into kernel virtual address space. This is 1734 * intended for temporary mappings which do not need page modification or 1735 * references recorded. Existing mappings in the region are overwritten. 1736 */ 1737 void 1738 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1739 { 1740 vm_offset_t va; 1741 1742 va = sva; 1743 while (count-- > 0) { 1744 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1745 va += PAGE_SIZE; 1746 m++; 1747 } 1748 } 1749 1750 /* 1751 * Remove page mappings from kernel virtual address space. Intended for 1752 * temporary mappings entered by moea_qenter. 1753 */ 1754 void 1755 moea_qremove(mmu_t mmu, vm_offset_t sva, int count) 1756 { 1757 vm_offset_t va; 1758 1759 va = sva; 1760 while (count-- > 0) { 1761 moea_kremove(mmu, va); 1762 va += PAGE_SIZE; 1763 } 1764 } 1765 1766 void 1767 moea_release(mmu_t mmu, pmap_t pmap) 1768 { 1769 int idx, mask; 1770 1771 /* 1772 * Free segment register's VSID 1773 */ 1774 if (pmap->pm_sr[0] == 0) 1775 panic("moea_release"); 1776 1777 mtx_lock(&moea_vsid_mutex); 1778 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1779 mask = 1 << (idx % VSID_NBPW); 1780 idx /= VSID_NBPW; 1781 moea_vsid_bitmap[idx] &= ~mask; 1782 mtx_unlock(&moea_vsid_mutex); 1783 } 1784 1785 /* 1786 * Remove the given range of addresses from the specified map. 1787 */ 1788 void 1789 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1790 { 1791 struct pvo_entry *pvo, *tpvo, key; 1792 1793 rw_wlock(&pvh_global_lock); 1794 PMAP_LOCK(pm); 1795 key.pvo_vaddr = sva; 1796 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1797 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1798 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1799 moea_pvo_remove(pvo, -1); 1800 } 1801 PMAP_UNLOCK(pm); 1802 rw_wunlock(&pvh_global_lock); 1803 } 1804 1805 /* 1806 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1807 * will reflect changes in pte's back to the vm_page. 1808 */ 1809 void 1810 moea_remove_all(mmu_t mmu, vm_page_t m) 1811 { 1812 struct pvo_head *pvo_head; 1813 struct pvo_entry *pvo, *next_pvo; 1814 pmap_t pmap; 1815 1816 rw_wlock(&pvh_global_lock); 1817 pvo_head = vm_page_to_pvoh(m); 1818 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1819 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1820 1821 pmap = pvo->pvo_pmap; 1822 PMAP_LOCK(pmap); 1823 moea_pvo_remove(pvo, -1); 1824 PMAP_UNLOCK(pmap); 1825 } 1826 if ((m->aflags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) { 1827 moea_attr_clear(m, PTE_CHG); 1828 vm_page_dirty(m); 1829 } 1830 vm_page_aflag_clear(m, PGA_WRITEABLE); 1831 rw_wunlock(&pvh_global_lock); 1832 } 1833 1834 /* 1835 * Allocate a physical page of memory directly from the phys_avail map. 1836 * Can only be called from moea_bootstrap before avail start and end are 1837 * calculated. 1838 */ 1839 static vm_offset_t 1840 moea_bootstrap_alloc(vm_size_t size, u_int align) 1841 { 1842 vm_offset_t s, e; 1843 int i, j; 1844 1845 size = round_page(size); 1846 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1847 if (align != 0) 1848 s = (phys_avail[i] + align - 1) & ~(align - 1); 1849 else 1850 s = phys_avail[i]; 1851 e = s + size; 1852 1853 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1854 continue; 1855 1856 if (s == phys_avail[i]) { 1857 phys_avail[i] += size; 1858 } else if (e == phys_avail[i + 1]) { 1859 phys_avail[i + 1] -= size; 1860 } else { 1861 for (j = phys_avail_count * 2; j > i; j -= 2) { 1862 phys_avail[j] = phys_avail[j - 2]; 1863 phys_avail[j + 1] = phys_avail[j - 1]; 1864 } 1865 1866 phys_avail[i + 3] = phys_avail[i + 1]; 1867 phys_avail[i + 1] = s; 1868 phys_avail[i + 2] = e; 1869 phys_avail_count++; 1870 } 1871 1872 return (s); 1873 } 1874 panic("moea_bootstrap_alloc: could not allocate memory"); 1875 } 1876 1877 static void 1878 moea_syncicache(vm_offset_t pa, vm_size_t len) 1879 { 1880 __syncicache((void *)pa, len); 1881 } 1882 1883 static int 1884 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1885 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 1886 { 1887 struct pvo_entry *pvo; 1888 u_int sr; 1889 int first; 1890 u_int ptegidx; 1891 int i; 1892 int bootstrap; 1893 1894 moea_pvo_enter_calls++; 1895 first = 0; 1896 bootstrap = 0; 1897 1898 /* 1899 * Compute the PTE Group index. 1900 */ 1901 va &= ~ADDR_POFF; 1902 sr = va_to_sr(pm->pm_sr, va); 1903 ptegidx = va_to_pteg(sr, va); 1904 1905 /* 1906 * Remove any existing mapping for this page. Reuse the pvo entry if 1907 * there is a mapping. 1908 */ 1909 mtx_lock(&moea_table_mutex); 1910 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 1911 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1912 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 1913 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 1914 (pte_lo & PTE_PP)) { 1915 /* 1916 * The PTE is not changing. Instead, this may 1917 * be a request to change the mapping's wired 1918 * attribute. 1919 */ 1920 mtx_unlock(&moea_table_mutex); 1921 if ((flags & PVO_WIRED) != 0 && 1922 (pvo->pvo_vaddr & PVO_WIRED) == 0) { 1923 pvo->pvo_vaddr |= PVO_WIRED; 1924 pm->pm_stats.wired_count++; 1925 } else if ((flags & PVO_WIRED) == 0 && 1926 (pvo->pvo_vaddr & PVO_WIRED) != 0) { 1927 pvo->pvo_vaddr &= ~PVO_WIRED; 1928 pm->pm_stats.wired_count--; 1929 } 1930 return (0); 1931 } 1932 moea_pvo_remove(pvo, -1); 1933 break; 1934 } 1935 } 1936 1937 /* 1938 * If we aren't overwriting a mapping, try to allocate. 1939 */ 1940 if (moea_initialized) { 1941 pvo = uma_zalloc(zone, M_NOWAIT); 1942 } else { 1943 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 1944 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 1945 moea_bpvo_pool_index, BPVO_POOL_SIZE, 1946 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1947 } 1948 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 1949 moea_bpvo_pool_index++; 1950 bootstrap = 1; 1951 } 1952 1953 if (pvo == NULL) { 1954 mtx_unlock(&moea_table_mutex); 1955 return (ENOMEM); 1956 } 1957 1958 moea_pvo_entries++; 1959 pvo->pvo_vaddr = va; 1960 pvo->pvo_pmap = pm; 1961 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 1962 pvo->pvo_vaddr &= ~ADDR_POFF; 1963 if (flags & PVO_WIRED) 1964 pvo->pvo_vaddr |= PVO_WIRED; 1965 if (pvo_head != &moea_pvo_kunmanaged) 1966 pvo->pvo_vaddr |= PVO_MANAGED; 1967 if (bootstrap) 1968 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1969 1970 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 1971 1972 /* 1973 * Add to pmap list 1974 */ 1975 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 1976 1977 /* 1978 * Remember if the list was empty and therefore will be the first 1979 * item. 1980 */ 1981 if (LIST_FIRST(pvo_head) == NULL) 1982 first = 1; 1983 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 1984 1985 if (pvo->pvo_vaddr & PVO_WIRED) 1986 pm->pm_stats.wired_count++; 1987 pm->pm_stats.resident_count++; 1988 1989 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 1990 KASSERT(i < 8, ("Invalid PTE index")); 1991 if (i >= 0) { 1992 PVO_PTEGIDX_SET(pvo, i); 1993 } else { 1994 panic("moea_pvo_enter: overflow"); 1995 moea_pte_overflow++; 1996 } 1997 mtx_unlock(&moea_table_mutex); 1998 1999 return (first ? ENOENT : 0); 2000 } 2001 2002 static void 2003 moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 2004 { 2005 struct pte *pt; 2006 2007 /* 2008 * If there is an active pte entry, we need to deactivate it (and 2009 * save the ref & cfg bits). 2010 */ 2011 pt = moea_pvo_to_pte(pvo, pteidx); 2012 if (pt != NULL) { 2013 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 2014 mtx_unlock(&moea_table_mutex); 2015 PVO_PTEGIDX_CLR(pvo); 2016 } else { 2017 moea_pte_overflow--; 2018 } 2019 2020 /* 2021 * Update our statistics. 2022 */ 2023 pvo->pvo_pmap->pm_stats.resident_count--; 2024 if (pvo->pvo_vaddr & PVO_WIRED) 2025 pvo->pvo_pmap->pm_stats.wired_count--; 2026 2027 /* 2028 * Save the REF/CHG bits into their cache if the page is managed. 2029 */ 2030 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) { 2031 struct vm_page *pg; 2032 2033 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 2034 if (pg != NULL) { 2035 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 2036 (PTE_REF | PTE_CHG)); 2037 } 2038 } 2039 2040 /* 2041 * Remove this PVO from the PV and pmap lists. 2042 */ 2043 LIST_REMOVE(pvo, pvo_vlink); 2044 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2045 2046 /* 2047 * Remove this from the overflow list and return it to the pool 2048 * if we aren't going to reuse it. 2049 */ 2050 LIST_REMOVE(pvo, pvo_olink); 2051 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2052 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2053 moea_upvo_zone, pvo); 2054 moea_pvo_entries--; 2055 moea_pvo_remove_calls++; 2056 } 2057 2058 static __inline int 2059 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2060 { 2061 int pteidx; 2062 2063 /* 2064 * We can find the actual pte entry without searching by grabbing 2065 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2066 * noticing the HID bit. 2067 */ 2068 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2069 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2070 pteidx ^= moea_pteg_mask * 8; 2071 2072 return (pteidx); 2073 } 2074 2075 static struct pvo_entry * 2076 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2077 { 2078 struct pvo_entry *pvo; 2079 int ptegidx; 2080 u_int sr; 2081 2082 va &= ~ADDR_POFF; 2083 sr = va_to_sr(pm->pm_sr, va); 2084 ptegidx = va_to_pteg(sr, va); 2085 2086 mtx_lock(&moea_table_mutex); 2087 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2088 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2089 if (pteidx_p) 2090 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2091 break; 2092 } 2093 } 2094 mtx_unlock(&moea_table_mutex); 2095 2096 return (pvo); 2097 } 2098 2099 static struct pte * 2100 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2101 { 2102 struct pte *pt; 2103 2104 /* 2105 * If we haven't been supplied the ptegidx, calculate it. 2106 */ 2107 if (pteidx == -1) { 2108 int ptegidx; 2109 u_int sr; 2110 2111 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2112 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2113 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2114 } 2115 2116 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2117 mtx_lock(&moea_table_mutex); 2118 2119 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2120 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2121 "valid pte index", pvo); 2122 } 2123 2124 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2125 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2126 "pvo but no valid pte", pvo); 2127 } 2128 2129 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2130 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2131 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2132 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2133 } 2134 2135 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2136 != 0) { 2137 panic("moea_pvo_to_pte: pvo %p pte does not match " 2138 "pte %p in moea_pteg_table", pvo, pt); 2139 } 2140 2141 mtx_assert(&moea_table_mutex, MA_OWNED); 2142 return (pt); 2143 } 2144 2145 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2146 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2147 "moea_pteg_table but valid in pvo: %8x, %8x", pvo, pt, pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2148 } 2149 2150 mtx_unlock(&moea_table_mutex); 2151 return (NULL); 2152 } 2153 2154 /* 2155 * XXX: THIS STUFF SHOULD BE IN pte.c? 2156 */ 2157 int 2158 moea_pte_spill(vm_offset_t addr) 2159 { 2160 struct pvo_entry *source_pvo, *victim_pvo; 2161 struct pvo_entry *pvo; 2162 int ptegidx, i, j; 2163 u_int sr; 2164 struct pteg *pteg; 2165 struct pte *pt; 2166 2167 moea_pte_spills++; 2168 2169 sr = mfsrin(addr); 2170 ptegidx = va_to_pteg(sr, addr); 2171 2172 /* 2173 * Have to substitute some entry. Use the primary hash for this. 2174 * Use low bits of timebase as random generator. 2175 */ 2176 pteg = &moea_pteg_table[ptegidx]; 2177 mtx_lock(&moea_table_mutex); 2178 __asm __volatile("mftb %0" : "=r"(i)); 2179 i &= 7; 2180 pt = &pteg->pt[i]; 2181 2182 source_pvo = NULL; 2183 victim_pvo = NULL; 2184 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2185 /* 2186 * We need to find a pvo entry for this address. 2187 */ 2188 if (source_pvo == NULL && 2189 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2190 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2191 /* 2192 * Now found an entry to be spilled into the pteg. 2193 * The PTE is now valid, so we know it's active. 2194 */ 2195 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2196 2197 if (j >= 0) { 2198 PVO_PTEGIDX_SET(pvo, j); 2199 moea_pte_overflow--; 2200 mtx_unlock(&moea_table_mutex); 2201 return (1); 2202 } 2203 2204 source_pvo = pvo; 2205 2206 if (victim_pvo != NULL) 2207 break; 2208 } 2209 2210 /* 2211 * We also need the pvo entry of the victim we are replacing 2212 * so save the R & C bits of the PTE. 2213 */ 2214 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2215 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2216 victim_pvo = pvo; 2217 if (source_pvo != NULL) 2218 break; 2219 } 2220 } 2221 2222 if (source_pvo == NULL) { 2223 mtx_unlock(&moea_table_mutex); 2224 return (0); 2225 } 2226 2227 if (victim_pvo == NULL) { 2228 if ((pt->pte_hi & PTE_HID) == 0) 2229 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2230 "entry", pt); 2231 2232 /* 2233 * If this is a secondary PTE, we need to search it's primary 2234 * pvo bucket for the matching PVO. 2235 */ 2236 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2237 pvo_olink) { 2238 /* 2239 * We also need the pvo entry of the victim we are 2240 * replacing so save the R & C bits of the PTE. 2241 */ 2242 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2243 victim_pvo = pvo; 2244 break; 2245 } 2246 } 2247 2248 if (victim_pvo == NULL) 2249 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2250 "entry", pt); 2251 } 2252 2253 /* 2254 * We are invalidating the TLB entry for the EA we are replacing even 2255 * though it's valid. If we don't, we lose any ref/chg bit changes 2256 * contained in the TLB entry. 2257 */ 2258 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2259 2260 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2261 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2262 2263 PVO_PTEGIDX_CLR(victim_pvo); 2264 PVO_PTEGIDX_SET(source_pvo, i); 2265 moea_pte_replacements++; 2266 2267 mtx_unlock(&moea_table_mutex); 2268 return (1); 2269 } 2270 2271 static __inline struct pvo_entry * 2272 moea_pte_spillable_ident(u_int ptegidx) 2273 { 2274 struct pte *pt; 2275 struct pvo_entry *pvo_walk, *pvo = NULL; 2276 2277 LIST_FOREACH(pvo_walk, &moea_pvo_table[ptegidx], pvo_olink) { 2278 if (pvo_walk->pvo_vaddr & PVO_WIRED) 2279 continue; 2280 2281 if (!(pvo_walk->pvo_pte.pte.pte_hi & PTE_VALID)) 2282 continue; 2283 2284 pt = moea_pvo_to_pte(pvo_walk, -1); 2285 2286 if (pt == NULL) 2287 continue; 2288 2289 pvo = pvo_walk; 2290 2291 mtx_unlock(&moea_table_mutex); 2292 if (!(pt->pte_lo & PTE_REF)) 2293 return (pvo_walk); 2294 } 2295 2296 return (pvo); 2297 } 2298 2299 static int 2300 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2301 { 2302 struct pte *pt; 2303 struct pvo_entry *victim_pvo; 2304 int i; 2305 int victim_idx; 2306 u_int pteg_bkpidx = ptegidx; 2307 2308 mtx_assert(&moea_table_mutex, MA_OWNED); 2309 2310 /* 2311 * First try primary hash. 2312 */ 2313 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2314 if ((pt->pte_hi & PTE_VALID) == 0) { 2315 pvo_pt->pte_hi &= ~PTE_HID; 2316 moea_pte_set(pt, pvo_pt); 2317 return (i); 2318 } 2319 } 2320 2321 /* 2322 * Now try secondary hash. 2323 */ 2324 ptegidx ^= moea_pteg_mask; 2325 2326 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2327 if ((pt->pte_hi & PTE_VALID) == 0) { 2328 pvo_pt->pte_hi |= PTE_HID; 2329 moea_pte_set(pt, pvo_pt); 2330 return (i); 2331 } 2332 } 2333 2334 /* Try again, but this time try to force a PTE out. */ 2335 ptegidx = pteg_bkpidx; 2336 2337 victim_pvo = moea_pte_spillable_ident(ptegidx); 2338 if (victim_pvo == NULL) { 2339 ptegidx ^= moea_pteg_mask; 2340 victim_pvo = moea_pte_spillable_ident(ptegidx); 2341 } 2342 2343 if (victim_pvo == NULL) { 2344 panic("moea_pte_insert: overflow"); 2345 return (-1); 2346 } 2347 2348 victim_idx = moea_pvo_pte_index(victim_pvo, ptegidx); 2349 2350 if (pteg_bkpidx == ptegidx) 2351 pvo_pt->pte_hi &= ~PTE_HID; 2352 else 2353 pvo_pt->pte_hi |= PTE_HID; 2354 2355 /* 2356 * Synchronize the sacrifice PTE with its PVO, then mark both 2357 * invalid. The PVO will be reused when/if the VM system comes 2358 * here after a fault. 2359 */ 2360 pt = &moea_pteg_table[victim_idx >> 3].pt[victim_idx & 7]; 2361 2362 if (pt->pte_hi != victim_pvo->pvo_pte.pte.pte_hi) 2363 panic("Victim PVO doesn't match PTE! PVO: %8x, PTE: %8x", victim_pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2364 2365 /* 2366 * Set the new PTE. 2367 */ 2368 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2369 PVO_PTEGIDX_CLR(victim_pvo); 2370 moea_pte_overflow++; 2371 moea_pte_set(pt, pvo_pt); 2372 2373 return (victim_idx & 7); 2374 } 2375 2376 static boolean_t 2377 moea_query_bit(vm_page_t m, int ptebit) 2378 { 2379 struct pvo_entry *pvo; 2380 struct pte *pt; 2381 2382 rw_assert(&pvh_global_lock, RA_WLOCKED); 2383 if (moea_attr_fetch(m) & ptebit) 2384 return (TRUE); 2385 2386 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2387 2388 /* 2389 * See if we saved the bit off. If so, cache it and return 2390 * success. 2391 */ 2392 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2393 moea_attr_save(m, ptebit); 2394 return (TRUE); 2395 } 2396 } 2397 2398 /* 2399 * No luck, now go through the hard part of looking at the PTEs 2400 * themselves. Sync so that any pending REF/CHG bits are flushed to 2401 * the PTEs. 2402 */ 2403 powerpc_sync(); 2404 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2405 2406 /* 2407 * See if this pvo has a valid PTE. if so, fetch the 2408 * REF/CHG bits from the valid PTE. If the appropriate 2409 * ptebit is set, cache it and return success. 2410 */ 2411 pt = moea_pvo_to_pte(pvo, -1); 2412 if (pt != NULL) { 2413 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2414 mtx_unlock(&moea_table_mutex); 2415 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2416 moea_attr_save(m, ptebit); 2417 return (TRUE); 2418 } 2419 } 2420 } 2421 2422 return (FALSE); 2423 } 2424 2425 static u_int 2426 moea_clear_bit(vm_page_t m, int ptebit) 2427 { 2428 u_int count; 2429 struct pvo_entry *pvo; 2430 struct pte *pt; 2431 2432 rw_assert(&pvh_global_lock, RA_WLOCKED); 2433 2434 /* 2435 * Clear the cached value. 2436 */ 2437 moea_attr_clear(m, ptebit); 2438 2439 /* 2440 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2441 * we can reset the right ones). note that since the pvo entries and 2442 * list heads are accessed via BAT0 and are never placed in the page 2443 * table, we don't have to worry about further accesses setting the 2444 * REF/CHG bits. 2445 */ 2446 powerpc_sync(); 2447 2448 /* 2449 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2450 * valid pte clear the ptebit from the valid pte. 2451 */ 2452 count = 0; 2453 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2454 pt = moea_pvo_to_pte(pvo, -1); 2455 if (pt != NULL) { 2456 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2457 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2458 count++; 2459 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2460 } 2461 mtx_unlock(&moea_table_mutex); 2462 } 2463 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2464 } 2465 2466 return (count); 2467 } 2468 2469 /* 2470 * Return true if the physical range is encompassed by the battable[idx] 2471 */ 2472 static int 2473 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2474 { 2475 u_int prot; 2476 u_int32_t start; 2477 u_int32_t end; 2478 u_int32_t bat_ble; 2479 2480 /* 2481 * Return immediately if not a valid mapping 2482 */ 2483 if (!(battable[idx].batu & BAT_Vs)) 2484 return (EINVAL); 2485 2486 /* 2487 * The BAT entry must be cache-inhibited, guarded, and r/w 2488 * so it can function as an i/o page 2489 */ 2490 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2491 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2492 return (EPERM); 2493 2494 /* 2495 * The address should be within the BAT range. Assume that the 2496 * start address in the BAT has the correct alignment (thus 2497 * not requiring masking) 2498 */ 2499 start = battable[idx].batl & BAT_PBS; 2500 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2501 end = start | (bat_ble << 15) | 0x7fff; 2502 2503 if ((pa < start) || ((pa + size) > end)) 2504 return (ERANGE); 2505 2506 return (0); 2507 } 2508 2509 boolean_t 2510 moea_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2511 { 2512 int i; 2513 2514 /* 2515 * This currently does not work for entries that 2516 * overlap 256M BAT segments. 2517 */ 2518 2519 for(i = 0; i < 16; i++) 2520 if (moea_bat_mapped(i, pa, size) == 0) 2521 return (0); 2522 2523 return (EFAULT); 2524 } 2525 2526 /* 2527 * Map a set of physical memory pages into the kernel virtual 2528 * address space. Return a pointer to where it is mapped. This 2529 * routine is intended to be used for mapping device memory, 2530 * NOT real memory. 2531 */ 2532 void * 2533 moea_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2534 { 2535 2536 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2537 } 2538 2539 void * 2540 moea_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2541 { 2542 vm_offset_t va, tmpva, ppa, offset; 2543 int i; 2544 2545 ppa = trunc_page(pa); 2546 offset = pa & PAGE_MASK; 2547 size = roundup(offset + size, PAGE_SIZE); 2548 2549 /* 2550 * If the physical address lies within a valid BAT table entry, 2551 * return the 1:1 mapping. This currently doesn't work 2552 * for regions that overlap 256M BAT segments. 2553 */ 2554 for (i = 0; i < 16; i++) { 2555 if (moea_bat_mapped(i, pa, size) == 0) 2556 return ((void *) pa); 2557 } 2558 2559 va = kva_alloc(size); 2560 if (!va) 2561 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2562 2563 for (tmpva = va; size > 0;) { 2564 moea_kenter_attr(mmu, tmpva, ppa, ma); 2565 tlbie(tmpva); 2566 size -= PAGE_SIZE; 2567 tmpva += PAGE_SIZE; 2568 ppa += PAGE_SIZE; 2569 } 2570 2571 return ((void *)(va + offset)); 2572 } 2573 2574 void 2575 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2576 { 2577 vm_offset_t base, offset; 2578 2579 /* 2580 * If this is outside kernel virtual space, then it's a 2581 * battable entry and doesn't require unmapping 2582 */ 2583 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2584 base = trunc_page(va); 2585 offset = va & PAGE_MASK; 2586 size = roundup(offset + size, PAGE_SIZE); 2587 kva_free(base, size); 2588 } 2589 } 2590 2591 static void 2592 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2593 { 2594 struct pvo_entry *pvo; 2595 vm_offset_t lim; 2596 vm_paddr_t pa; 2597 vm_size_t len; 2598 2599 PMAP_LOCK(pm); 2600 while (sz > 0) { 2601 lim = round_page(va); 2602 len = MIN(lim - va, sz); 2603 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2604 if (pvo != NULL) { 2605 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2606 (va & ADDR_POFF); 2607 moea_syncicache(pa, len); 2608 } 2609 va += len; 2610 sz -= len; 2611 } 2612 PMAP_UNLOCK(pm); 2613 } 2614 2615 void 2616 moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2617 { 2618 2619 *va = (void *)pa; 2620 } 2621 2622 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2623 2624 void 2625 moea_scan_init(mmu_t mmu) 2626 { 2627 struct pvo_entry *pvo; 2628 vm_offset_t va; 2629 int i; 2630 2631 if (!do_minidump) { 2632 /* Initialize phys. segments for dumpsys(). */ 2633 memset(&dump_map, 0, sizeof(dump_map)); 2634 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2635 for (i = 0; i < pregions_sz; i++) { 2636 dump_map[i].pa_start = pregions[i].mr_start; 2637 dump_map[i].pa_size = pregions[i].mr_size; 2638 } 2639 return; 2640 } 2641 2642 /* Virtual segments for minidumps: */ 2643 memset(&dump_map, 0, sizeof(dump_map)); 2644 2645 /* 1st: kernel .data and .bss. */ 2646 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2647 dump_map[0].pa_size = 2648 round_page((uintptr_t)_end) - dump_map[0].pa_start; 2649 2650 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2651 dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr; 2652 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2653 2654 /* 3rd: kernel VM. */ 2655 va = dump_map[1].pa_start + dump_map[1].pa_size; 2656 /* Find start of next chunk (from va). */ 2657 while (va < virtual_end) { 2658 /* Don't dump the buffer cache. */ 2659 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2660 va = kmi.buffer_eva; 2661 continue; 2662 } 2663 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 2664 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2665 break; 2666 va += PAGE_SIZE; 2667 } 2668 if (va < virtual_end) { 2669 dump_map[2].pa_start = va; 2670 va += PAGE_SIZE; 2671 /* Find last page in chunk. */ 2672 while (va < virtual_end) { 2673 /* Don't run into the buffer cache. */ 2674 if (va == kmi.buffer_sva) 2675 break; 2676 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, 2677 NULL); 2678 if (pvo == NULL || 2679 !(pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2680 break; 2681 va += PAGE_SIZE; 2682 } 2683 dump_map[2].pa_size = va - dump_map[2].pa_start; 2684 } 2685 } 2686