1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0 3 * 4 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 * 34 * $FreeBSD$ 35 */ 36 37 #ifndef MLX5_ABI_USER_H 38 #define MLX5_ABI_USER_H 39 40 #ifdef _KERNEL 41 #include <linux/types.h> 42 #else 43 #include <infiniband/types.h> 44 #endif 45 46 enum { 47 MLX5_QP_FLAG_SIGNATURE = 1 << 0, 48 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1, 49 MLX5_QP_FLAG_BFREG_INDEX = 1 << 3, 50 MLX5_QP_FLAG_UAR_PAGE_INDEX = 1 << 10, 51 }; 52 53 enum { 54 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0, 55 }; 56 57 enum { 58 MLX5_WQ_FLAG_SIGNATURE = 1 << 0, 59 }; 60 61 /* Increment this value if any changes that break userspace ABI 62 * compatibility are made. 63 */ 64 #define MLX5_IB_UVERBS_ABI_VERSION 1 65 66 /* Make sure that all structs defined in this file remain laid out so 67 * that they pack the same way on 32-bit and 64-bit architectures (to 68 * avoid incompatibility between 32-bit userspace and 64-bit kernels). 69 * In particular do not use pointer types -- pass pointers in __u64 70 * instead. 71 */ 72 73 struct mlx5_ib_alloc_ucontext_req { 74 __u32 total_num_bfregs; 75 __u32 num_low_latency_bfregs; 76 }; 77 78 enum mlx5_lib_caps { 79 MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0, 80 MLX5_LIB_CAP_DYN_UAR = (__u64)1 << 1, 81 }; 82 83 enum mlx5_ib_alloc_uctx_v2_flags { 84 MLX5_IB_ALLOC_UCTX_DEVX = 1 << 0, 85 }; 86 struct mlx5_ib_alloc_ucontext_req_v2 { 87 __u32 total_num_bfregs; 88 __u32 num_low_latency_bfregs; 89 __u32 flags; 90 __u32 comp_mask; 91 __u8 max_cqe_version; 92 __u8 reserved0; 93 __u16 reserved1; 94 __u32 reserved2; 95 __aligned_u64 lib_caps; 96 }; 97 98 enum mlx5_ib_alloc_ucontext_resp_mask { 99 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0, 100 }; 101 102 enum mlx5_user_cmds_supp_uhw { 103 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0, 104 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1, 105 }; 106 107 struct mlx5_ib_alloc_ucontext_resp { 108 __u32 qp_tab_size; 109 __u32 bf_reg_size; 110 __u32 tot_bfregs; 111 __u32 cache_line_size; 112 __u16 max_sq_desc_sz; 113 __u16 max_rq_desc_sz; 114 __u32 max_send_wqebb; 115 __u32 max_recv_wr; 116 __u32 max_srq_recv_wr; 117 __u16 num_ports; 118 __u16 reserved1; 119 __u32 comp_mask; 120 __u32 response_length; 121 __u8 cqe_version; 122 __u8 cmds_supp_uhw; 123 __u16 reserved2; 124 __u64 hca_core_clock_offset; 125 __u32 log_uar_size; 126 __u32 num_uars_per_page; 127 __u32 num_dyn_bfregs; 128 }; 129 130 struct mlx5_ib_alloc_pd_resp { 131 __u32 pdn; 132 }; 133 134 struct mlx5_ib_tso_caps { 135 __u32 max_tso; /* Maximum tso payload size in bytes */ 136 137 /* Corresponding bit will be set if qp type from 138 * 'enum ib_qp_type' is supported, e.g. 139 * supported_qpts |= 1 << IB_QPT_UD 140 */ 141 __u32 supported_qpts; 142 }; 143 144 struct mlx5_ib_rss_caps { 145 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 146 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 147 __u8 reserved[7]; 148 }; 149 150 struct mlx5_ib_query_device_resp { 151 __u32 comp_mask; 152 __u32 response_length; 153 struct mlx5_ib_tso_caps tso_caps; 154 struct mlx5_ib_rss_caps rss_caps; 155 }; 156 157 enum mlx5_ib_create_cq_flags { 158 MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0, 159 MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX = 1 << 1, 160 }; 161 162 struct mlx5_ib_create_cq { 163 __u64 buf_addr; 164 __u64 db_addr; 165 __u32 cqe_size; 166 __u16 flags; 167 __u16 uar_page_index; 168 }; 169 170 struct mlx5_ib_create_cq_resp { 171 __u32 cqn; 172 __u32 reserved; 173 }; 174 175 struct mlx5_ib_resize_cq { 176 __u64 buf_addr; 177 __u16 cqe_size; 178 __u16 reserved0; 179 __u32 reserved1; 180 }; 181 182 struct mlx5_ib_create_srq { 183 __u64 buf_addr; 184 __u64 db_addr; 185 __u32 flags; 186 __u32 reserved0; /* explicit padding (optional on i386) */ 187 __u32 uidx; 188 __u32 reserved1; 189 }; 190 191 struct mlx5_ib_create_srq_resp { 192 __u32 srqn; 193 __u32 reserved; 194 }; 195 196 struct mlx5_ib_create_qp { 197 __u64 buf_addr; 198 __u64 db_addr; 199 __u32 sq_wqe_count; 200 __u32 rq_wqe_count; 201 __u32 rq_wqe_shift; 202 __u32 flags; 203 __u32 uidx; 204 __u32 bfreg_index; 205 __u64 sq_buf_addr; 206 }; 207 208 /* RX Hash function flags */ 209 enum mlx5_rx_hash_function_flags { 210 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0, 211 }; 212 213 /* 214 * RX Hash flags, these flags allows to set which incoming packet's field should 215 * participates in RX Hash. Each flag represent certain packet's field, 216 * when the flag is set the field that is represented by the flag will 217 * participate in RX Hash calculation. 218 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP 219 * and *TCP and *UDP flags can't be enabled together on the same QP. 220 */ 221 enum mlx5_rx_hash_fields { 222 MLX5_RX_HASH_SRC_IPV4 = 1 << 0, 223 MLX5_RX_HASH_DST_IPV4 = 1 << 1, 224 MLX5_RX_HASH_SRC_IPV6 = 1 << 2, 225 MLX5_RX_HASH_DST_IPV6 = 1 << 3, 226 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4, 227 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5, 228 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6, 229 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7 230 }; 231 232 struct mlx5_ib_create_qp_rss { 233 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 234 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 235 __u8 rx_key_len; /* valid only for Toeplitz */ 236 __u8 reserved[6]; 237 __u8 rx_hash_key[128]; /* valid only for Toeplitz */ 238 __u32 comp_mask; 239 __u32 reserved1; 240 }; 241 242 struct mlx5_ib_create_qp_resp { 243 __u32 bfreg_index; 244 }; 245 246 struct mlx5_ib_alloc_mw { 247 __u32 comp_mask; 248 __u8 num_klms; 249 __u8 reserved1; 250 __u16 reserved2; 251 }; 252 253 struct mlx5_ib_create_wq { 254 __u64 buf_addr; 255 __u64 db_addr; 256 __u32 rq_wqe_count; 257 __u32 rq_wqe_shift; 258 __u32 user_index; 259 __u32 flags; 260 __u32 comp_mask; 261 __u32 reserved; 262 }; 263 264 struct mlx5_ib_create_ah_resp { 265 __u32 response_length; 266 __u8 dmac[ETH_ALEN]; 267 __u8 reserved[6]; 268 }; 269 270 struct mlx5_ib_create_wq_resp { 271 __u32 response_length; 272 __u32 reserved; 273 }; 274 275 struct mlx5_ib_create_rwq_ind_tbl_resp { 276 __u32 response_length; 277 __u32 reserved; 278 }; 279 280 struct mlx5_ib_modify_wq { 281 __u32 comp_mask; 282 __u32 reserved; 283 }; 284 #endif /* MLX5_ABI_USER_H */ 285