1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/pfil.h> 63 #include <net/vnet.h> 64 65 #include <netinet/in.h> 66 #include <netinet/in_pcb.h> 67 #include <netinet/tcp_lro.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/if_ether.h> 70 #include <netinet/ip.h> 71 #include <netinet/ip6.h> 72 #include <netinet/tcp.h> 73 #include <netinet/ip_var.h> 74 #include <netinet/netdump/netdump.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 #include <net/iflib_private.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 120 /* 121 * File organization: 122 * - private structures 123 * - iflib private utility functions 124 * - ifnet functions 125 * - vlan registry and other exported functions 126 * - iflib public core functions 127 * 128 * 129 */ 130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 131 132 struct iflib_txq; 133 typedef struct iflib_txq *iflib_txq_t; 134 struct iflib_rxq; 135 typedef struct iflib_rxq *iflib_rxq_t; 136 struct iflib_fl; 137 typedef struct iflib_fl *iflib_fl_t; 138 139 struct iflib_ctx; 140 141 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 142 static void iflib_timer(void *arg); 143 144 typedef struct iflib_filter_info { 145 driver_filter_t *ifi_filter; 146 void *ifi_filter_arg; 147 struct grouptask *ifi_task; 148 void *ifi_ctx; 149 } *iflib_filter_info_t; 150 151 struct iflib_ctx { 152 KOBJ_FIELDS; 153 /* 154 * Pointer to hardware driver's softc 155 */ 156 void *ifc_softc; 157 device_t ifc_dev; 158 if_t ifc_ifp; 159 160 cpuset_t ifc_cpus; 161 if_shared_ctx_t ifc_sctx; 162 struct if_softc_ctx ifc_softc_ctx; 163 164 struct sx ifc_ctx_sx; 165 struct mtx ifc_state_mtx; 166 167 iflib_txq_t ifc_txqs; 168 iflib_rxq_t ifc_rxqs; 169 uint32_t ifc_if_flags; 170 uint32_t ifc_flags; 171 uint32_t ifc_max_fl_buf_size; 172 uint32_t ifc_rx_mbuf_sz; 173 174 int ifc_link_state; 175 int ifc_watchdog_events; 176 struct cdev *ifc_led_dev; 177 struct resource *ifc_msix_mem; 178 179 struct if_irq ifc_legacy_irq; 180 struct grouptask ifc_admin_task; 181 struct grouptask ifc_vflr_task; 182 struct iflib_filter_info ifc_filter_info; 183 struct ifmedia ifc_media; 184 struct ifmedia *ifc_mediap; 185 186 struct sysctl_oid *ifc_sysctl_node; 187 uint16_t ifc_sysctl_ntxqs; 188 uint16_t ifc_sysctl_nrxqs; 189 uint16_t ifc_sysctl_qs_eq_override; 190 uint16_t ifc_sysctl_rx_budget; 191 uint16_t ifc_sysctl_tx_abdicate; 192 uint16_t ifc_sysctl_core_offset; 193 #define CORE_OFFSET_UNSPECIFIED 0xffff 194 uint8_t ifc_sysctl_separate_txrx; 195 196 qidx_t ifc_sysctl_ntxds[8]; 197 qidx_t ifc_sysctl_nrxds[8]; 198 struct if_txrx ifc_txrx; 199 #define isc_txd_encap ifc_txrx.ift_txd_encap 200 #define isc_txd_flush ifc_txrx.ift_txd_flush 201 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 202 #define isc_rxd_available ifc_txrx.ift_rxd_available 203 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 204 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 205 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 206 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 208 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 209 eventhandler_tag ifc_vlan_attach_event; 210 eventhandler_tag ifc_vlan_detach_event; 211 struct ether_addr ifc_mac; 212 }; 213 214 void * 215 iflib_get_softc(if_ctx_t ctx) 216 { 217 218 return (ctx->ifc_softc); 219 } 220 221 device_t 222 iflib_get_dev(if_ctx_t ctx) 223 { 224 225 return (ctx->ifc_dev); 226 } 227 228 if_t 229 iflib_get_ifp(if_ctx_t ctx) 230 { 231 232 return (ctx->ifc_ifp); 233 } 234 235 struct ifmedia * 236 iflib_get_media(if_ctx_t ctx) 237 { 238 239 return (ctx->ifc_mediap); 240 } 241 242 uint32_t 243 iflib_get_flags(if_ctx_t ctx) 244 { 245 return (ctx->ifc_flags); 246 } 247 248 void 249 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 250 { 251 252 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 253 } 254 255 if_softc_ctx_t 256 iflib_get_softc_ctx(if_ctx_t ctx) 257 { 258 259 return (&ctx->ifc_softc_ctx); 260 } 261 262 if_shared_ctx_t 263 iflib_get_sctx(if_ctx_t ctx) 264 { 265 266 return (ctx->ifc_sctx); 267 } 268 269 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 270 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 271 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 272 273 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 274 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 275 276 typedef struct iflib_sw_rx_desc_array { 277 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 278 struct mbuf **ifsd_m; /* pkthdr mbufs */ 279 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 280 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 281 } iflib_rxsd_array_t; 282 283 typedef struct iflib_sw_tx_desc_array { 284 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 285 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 286 struct mbuf **ifsd_m; /* pkthdr mbufs */ 287 } if_txsd_vec_t; 288 289 /* magic number that should be high enough for any hardware */ 290 #define IFLIB_MAX_TX_SEGS 128 291 #define IFLIB_RX_COPY_THRESH 128 292 #define IFLIB_MAX_RX_REFRESH 32 293 /* The minimum descriptors per second before we start coalescing */ 294 #define IFLIB_MIN_DESC_SEC 16384 295 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 296 #define IFLIB_QUEUE_IDLE 0 297 #define IFLIB_QUEUE_HUNG 1 298 #define IFLIB_QUEUE_WORKING 2 299 /* maximum number of txqs that can share an rx interrupt */ 300 #define IFLIB_MAX_TX_SHARED_INTR 4 301 302 /* this should really scale with ring size - this is a fairly arbitrary value */ 303 #define TX_BATCH_SIZE 32 304 305 #define IFLIB_RESTART_BUDGET 8 306 307 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 308 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 309 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 310 311 struct iflib_txq { 312 qidx_t ift_in_use; 313 qidx_t ift_cidx; 314 qidx_t ift_cidx_processed; 315 qidx_t ift_pidx; 316 uint8_t ift_gen; 317 uint8_t ift_br_offset; 318 uint16_t ift_npending; 319 uint16_t ift_db_pending; 320 uint16_t ift_rs_pending; 321 /* implicit pad */ 322 uint8_t ift_txd_size[8]; 323 uint64_t ift_processed; 324 uint64_t ift_cleaned; 325 uint64_t ift_cleaned_prev; 326 #if MEMORY_LOGGING 327 uint64_t ift_enqueued; 328 uint64_t ift_dequeued; 329 #endif 330 uint64_t ift_no_tx_dma_setup; 331 uint64_t ift_no_desc_avail; 332 uint64_t ift_mbuf_defrag_failed; 333 uint64_t ift_mbuf_defrag; 334 uint64_t ift_map_failed; 335 uint64_t ift_txd_encap_efbig; 336 uint64_t ift_pullups; 337 uint64_t ift_last_timer_tick; 338 339 struct mtx ift_mtx; 340 struct mtx ift_db_mtx; 341 342 /* constant values */ 343 if_ctx_t ift_ctx; 344 struct ifmp_ring *ift_br; 345 struct grouptask ift_task; 346 qidx_t ift_size; 347 uint16_t ift_id; 348 struct callout ift_timer; 349 350 if_txsd_vec_t ift_sds; 351 uint8_t ift_qstatus; 352 uint8_t ift_closed; 353 uint8_t ift_update_freq; 354 struct iflib_filter_info ift_filter_info; 355 bus_dma_tag_t ift_buf_tag; 356 bus_dma_tag_t ift_tso_buf_tag; 357 iflib_dma_info_t ift_ifdi; 358 #define MTX_NAME_LEN 16 359 char ift_mtx_name[MTX_NAME_LEN]; 360 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 361 #ifdef IFLIB_DIAGNOSTICS 362 uint64_t ift_cpu_exec_count[256]; 363 #endif 364 } __aligned(CACHE_LINE_SIZE); 365 366 struct iflib_fl { 367 qidx_t ifl_cidx; 368 qidx_t ifl_pidx; 369 qidx_t ifl_credits; 370 uint8_t ifl_gen; 371 uint8_t ifl_rxd_size; 372 #if MEMORY_LOGGING 373 uint64_t ifl_m_enqueued; 374 uint64_t ifl_m_dequeued; 375 uint64_t ifl_cl_enqueued; 376 uint64_t ifl_cl_dequeued; 377 #endif 378 /* implicit pad */ 379 bitstr_t *ifl_rx_bitmap; 380 qidx_t ifl_fragidx; 381 /* constant */ 382 qidx_t ifl_size; 383 uint16_t ifl_buf_size; 384 uint16_t ifl_cltype; 385 uma_zone_t ifl_zone; 386 iflib_rxsd_array_t ifl_sds; 387 iflib_rxq_t ifl_rxq; 388 uint8_t ifl_id; 389 bus_dma_tag_t ifl_buf_tag; 390 iflib_dma_info_t ifl_ifdi; 391 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 392 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 393 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 394 } __aligned(CACHE_LINE_SIZE); 395 396 static inline qidx_t 397 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 398 { 399 qidx_t used; 400 401 if (pidx > cidx) 402 used = pidx - cidx; 403 else if (pidx < cidx) 404 used = size - cidx + pidx; 405 else if (gen == 0 && pidx == cidx) 406 used = 0; 407 else if (gen == 1 && pidx == cidx) 408 used = size; 409 else 410 panic("bad state"); 411 412 return (used); 413 } 414 415 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 416 417 #define IDXDIFF(head, tail, wrap) \ 418 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 419 420 struct iflib_rxq { 421 if_ctx_t ifr_ctx; 422 iflib_fl_t ifr_fl; 423 uint64_t ifr_rx_irq; 424 struct pfil_head *pfil; 425 /* 426 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 427 * the command queue consumer index. Otherwise it's unused. 428 */ 429 qidx_t ifr_cq_cidx; 430 uint16_t ifr_id; 431 uint8_t ifr_nfl; 432 uint8_t ifr_ntxqirq; 433 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 434 uint8_t ifr_fl_offset; 435 struct lro_ctrl ifr_lc; 436 struct grouptask ifr_task; 437 struct iflib_filter_info ifr_filter_info; 438 iflib_dma_info_t ifr_ifdi; 439 440 /* dynamically allocate if any drivers need a value substantially larger than this */ 441 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 442 #ifdef IFLIB_DIAGNOSTICS 443 uint64_t ifr_cpu_exec_count[256]; 444 #endif 445 } __aligned(CACHE_LINE_SIZE); 446 447 typedef struct if_rxsd { 448 caddr_t *ifsd_cl; 449 iflib_fl_t ifsd_fl; 450 qidx_t ifsd_cidx; 451 } *if_rxsd_t; 452 453 /* multiple of word size */ 454 #ifdef __LP64__ 455 #define PKT_INFO_SIZE 6 456 #define RXD_INFO_SIZE 5 457 #define PKT_TYPE uint64_t 458 #else 459 #define PKT_INFO_SIZE 11 460 #define RXD_INFO_SIZE 8 461 #define PKT_TYPE uint32_t 462 #endif 463 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 464 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 465 466 typedef struct if_pkt_info_pad { 467 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 468 } *if_pkt_info_pad_t; 469 typedef struct if_rxd_info_pad { 470 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 471 } *if_rxd_info_pad_t; 472 473 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 474 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 475 476 477 static inline void 478 pkt_info_zero(if_pkt_info_t pi) 479 { 480 if_pkt_info_pad_t pi_pad; 481 482 pi_pad = (if_pkt_info_pad_t)pi; 483 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 484 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 485 #ifndef __LP64__ 486 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 487 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 488 #endif 489 } 490 491 static device_method_t iflib_pseudo_methods[] = { 492 DEVMETHOD(device_attach, noop_attach), 493 DEVMETHOD(device_detach, iflib_pseudo_detach), 494 DEVMETHOD_END 495 }; 496 497 driver_t iflib_pseudodriver = { 498 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 499 }; 500 501 static inline void 502 rxd_info_zero(if_rxd_info_t ri) 503 { 504 if_rxd_info_pad_t ri_pad; 505 int i; 506 507 ri_pad = (if_rxd_info_pad_t)ri; 508 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 509 ri_pad->rxd_val[i] = 0; 510 ri_pad->rxd_val[i+1] = 0; 511 ri_pad->rxd_val[i+2] = 0; 512 ri_pad->rxd_val[i+3] = 0; 513 } 514 #ifdef __LP64__ 515 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 516 #endif 517 } 518 519 /* 520 * Only allow a single packet to take up most 1/nth of the tx ring 521 */ 522 #define MAX_SINGLE_PACKET_FRACTION 12 523 #define IF_BAD_DMA (bus_addr_t)-1 524 525 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 526 527 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 528 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 529 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 530 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 531 532 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 533 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 534 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 535 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 536 537 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 538 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 539 540 void 541 iflib_set_detach(if_ctx_t ctx) 542 { 543 STATE_LOCK(ctx); 544 ctx->ifc_flags |= IFC_IN_DETACH; 545 STATE_UNLOCK(ctx); 546 } 547 548 /* Our boot-time initialization hook */ 549 static int iflib_module_event_handler(module_t, int, void *); 550 551 static moduledata_t iflib_moduledata = { 552 "iflib", 553 iflib_module_event_handler, 554 NULL 555 }; 556 557 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 558 MODULE_VERSION(iflib, 1); 559 560 MODULE_DEPEND(iflib, pci, 1, 1, 1); 561 MODULE_DEPEND(iflib, ether, 1, 1, 1); 562 563 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 564 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 565 566 #ifndef IFLIB_DEBUG_COUNTERS 567 #ifdef INVARIANTS 568 #define IFLIB_DEBUG_COUNTERS 1 569 #else 570 #define IFLIB_DEBUG_COUNTERS 0 571 #endif /* !INVARIANTS */ 572 #endif 573 574 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 575 "iflib driver parameters"); 576 577 /* 578 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 579 */ 580 static int iflib_min_tx_latency = 0; 581 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 582 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 583 static int iflib_no_tx_batch = 0; 584 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 585 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 586 587 588 #if IFLIB_DEBUG_COUNTERS 589 590 static int iflib_tx_seen; 591 static int iflib_tx_sent; 592 static int iflib_tx_encap; 593 static int iflib_rx_allocs; 594 static int iflib_fl_refills; 595 static int iflib_fl_refills_large; 596 static int iflib_tx_frees; 597 598 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 599 &iflib_tx_seen, 0, "# TX mbufs seen"); 600 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 601 &iflib_tx_sent, 0, "# TX mbufs sent"); 602 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 603 &iflib_tx_encap, 0, "# TX mbufs encapped"); 604 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 605 &iflib_tx_frees, 0, "# TX frees"); 606 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 607 &iflib_rx_allocs, 0, "# RX allocations"); 608 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 609 &iflib_fl_refills, 0, "# refills"); 610 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 611 &iflib_fl_refills_large, 0, "# large refills"); 612 613 614 static int iflib_txq_drain_flushing; 615 static int iflib_txq_drain_oactive; 616 static int iflib_txq_drain_notready; 617 618 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 619 &iflib_txq_drain_flushing, 0, "# drain flushes"); 620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 621 &iflib_txq_drain_oactive, 0, "# drain oactives"); 622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 623 &iflib_txq_drain_notready, 0, "# drain notready"); 624 625 626 static int iflib_encap_load_mbuf_fail; 627 static int iflib_encap_pad_mbuf_fail; 628 static int iflib_encap_txq_avail_fail; 629 static int iflib_encap_txd_encap_fail; 630 631 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 632 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 633 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 634 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 635 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 636 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 638 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 639 640 static int iflib_task_fn_rxs; 641 static int iflib_rx_intr_enables; 642 static int iflib_fast_intrs; 643 static int iflib_rx_unavail; 644 static int iflib_rx_ctx_inactive; 645 static int iflib_rx_if_input; 646 static int iflib_rxd_flush; 647 648 static int iflib_verbose_debug; 649 650 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 651 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 652 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 653 &iflib_rx_intr_enables, 0, "# RX intr enables"); 654 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 655 &iflib_fast_intrs, 0, "# fast_intr calls"); 656 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 657 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 658 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 659 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 660 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 661 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 663 &iflib_rxd_flush, 0, "# times rxd_flush called"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 665 &iflib_verbose_debug, 0, "enable verbose debugging"); 666 667 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 668 static void 669 iflib_debug_reset(void) 670 { 671 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 672 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 673 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 674 iflib_txq_drain_notready = 675 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 676 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 677 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 678 iflib_rx_unavail = 679 iflib_rx_ctx_inactive = iflib_rx_if_input = 680 iflib_rxd_flush = 0; 681 } 682 683 #else 684 #define DBG_COUNTER_INC(name) 685 static void iflib_debug_reset(void) {} 686 #endif 687 688 #define IFLIB_DEBUG 0 689 690 static void iflib_tx_structures_free(if_ctx_t ctx); 691 static void iflib_rx_structures_free(if_ctx_t ctx); 692 static int iflib_queues_alloc(if_ctx_t ctx); 693 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 694 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 695 static int iflib_qset_structures_setup(if_ctx_t ctx); 696 static int iflib_msix_init(if_ctx_t ctx); 697 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 698 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 699 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 700 #ifdef ALTQ 701 static void iflib_altq_if_start(if_t ifp); 702 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 703 #endif 704 static int iflib_register(if_ctx_t); 705 static void iflib_init_locked(if_ctx_t ctx); 706 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 707 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 708 static void iflib_ifmp_purge(iflib_txq_t txq); 709 static void _iflib_pre_assert(if_softc_ctx_t scctx); 710 static void iflib_if_init_locked(if_ctx_t ctx); 711 static void iflib_free_intr_mem(if_ctx_t ctx); 712 #ifndef __NO_STRICT_ALIGNMENT 713 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 714 #endif 715 716 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 717 SLIST_HEAD_INITIALIZER(cpu_offsets); 718 struct cpu_offset { 719 SLIST_ENTRY(cpu_offset) entries; 720 cpuset_t set; 721 unsigned int refcount; 722 uint16_t offset; 723 }; 724 static struct mtx cpu_offset_mtx; 725 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 726 MTX_DEF); 727 728 NETDUMP_DEFINE(iflib); 729 730 #ifdef DEV_NETMAP 731 #include <sys/selinfo.h> 732 #include <net/netmap.h> 733 #include <dev/netmap/netmap_kern.h> 734 735 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 736 737 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 738 739 /* 740 * device-specific sysctl variables: 741 * 742 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 743 * During regular operations the CRC is stripped, but on some 744 * hardware reception of frames not multiple of 64 is slower, 745 * so using crcstrip=0 helps in benchmarks. 746 * 747 * iflib_rx_miss, iflib_rx_miss_bufs: 748 * count packets that might be missed due to lost interrupts. 749 */ 750 SYSCTL_DECL(_dev_netmap); 751 /* 752 * The xl driver by default strips CRCs and we do not override it. 753 */ 754 755 int iflib_crcstrip = 1; 756 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 757 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 758 759 int iflib_rx_miss, iflib_rx_miss_bufs; 760 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 761 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 763 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 764 765 /* 766 * Register/unregister. We are already under netmap lock. 767 * Only called on the first register or the last unregister. 768 */ 769 static int 770 iflib_netmap_register(struct netmap_adapter *na, int onoff) 771 { 772 if_t ifp = na->ifp; 773 if_ctx_t ctx = ifp->if_softc; 774 int status; 775 776 CTX_LOCK(ctx); 777 IFDI_INTR_DISABLE(ctx); 778 779 /* Tell the stack that the interface is no longer active */ 780 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 781 782 if (!CTX_IS_VF(ctx)) 783 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 784 785 /* enable or disable flags and callbacks in na and ifp */ 786 if (onoff) { 787 nm_set_native_flags(na); 788 } else { 789 nm_clear_native_flags(na); 790 } 791 iflib_stop(ctx); 792 iflib_init_locked(ctx); 793 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 794 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 795 if (status) 796 nm_clear_native_flags(na); 797 CTX_UNLOCK(ctx); 798 return (status); 799 } 800 801 static int 802 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 803 { 804 struct netmap_adapter *na = kring->na; 805 u_int const lim = kring->nkr_num_slots - 1; 806 u_int head = kring->rhead; 807 struct netmap_ring *ring = kring->ring; 808 bus_dmamap_t *map; 809 struct if_rxd_update iru; 810 if_ctx_t ctx = rxq->ifr_ctx; 811 iflib_fl_t fl = &rxq->ifr_fl[0]; 812 uint32_t refill_pidx, nic_i; 813 #if IFLIB_DEBUG_COUNTERS 814 int rf_count = 0; 815 #endif 816 817 if (nm_i == head && __predict_true(!init)) 818 return 0; 819 iru_init(&iru, rxq, 0 /* flid */); 820 map = fl->ifl_sds.ifsd_map; 821 refill_pidx = netmap_idx_k2n(kring, nm_i); 822 /* 823 * IMPORTANT: we must leave one free slot in the ring, 824 * so move head back by one unit 825 */ 826 head = nm_prev(head, lim); 827 nic_i = UINT_MAX; 828 DBG_COUNTER_INC(fl_refills); 829 while (nm_i != head) { 830 #if IFLIB_DEBUG_COUNTERS 831 if (++rf_count == 9) 832 DBG_COUNTER_INC(fl_refills_large); 833 #endif 834 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 835 struct netmap_slot *slot = &ring->slot[nm_i]; 836 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 837 uint32_t nic_i_dma = refill_pidx; 838 nic_i = netmap_idx_k2n(kring, nm_i); 839 840 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 841 842 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 843 return netmap_ring_reinit(kring); 844 845 fl->ifl_vm_addrs[tmp_pidx] = addr; 846 if (__predict_false(init)) { 847 netmap_load_map(na, fl->ifl_buf_tag, 848 map[nic_i], addr); 849 } else if (slot->flags & NS_BUF_CHANGED) { 850 /* buffer has changed, reload map */ 851 netmap_reload_map(na, fl->ifl_buf_tag, 852 map[nic_i], addr); 853 } 854 slot->flags &= ~NS_BUF_CHANGED; 855 856 nm_i = nm_next(nm_i, lim); 857 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 858 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 859 continue; 860 861 iru.iru_pidx = refill_pidx; 862 iru.iru_count = tmp_pidx+1; 863 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 864 refill_pidx = nic_i; 865 for (int n = 0; n < iru.iru_count; n++) { 866 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma], 867 BUS_DMASYNC_PREREAD); 868 /* XXX - change this to not use the netmap func*/ 869 nic_i_dma = nm_next(nic_i_dma, lim); 870 } 871 } 872 } 873 kring->nr_hwcur = head; 874 875 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 876 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 877 if (__predict_true(nic_i != UINT_MAX)) { 878 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 879 DBG_COUNTER_INC(rxd_flush); 880 } 881 return (0); 882 } 883 884 /* 885 * Reconcile kernel and user view of the transmit ring. 886 * 887 * All information is in the kring. 888 * Userspace wants to send packets up to the one before kring->rhead, 889 * kernel knows kring->nr_hwcur is the first unsent packet. 890 * 891 * Here we push packets out (as many as possible), and possibly 892 * reclaim buffers from previously completed transmission. 893 * 894 * The caller (netmap) guarantees that there is only one instance 895 * running at any time. Any interference with other driver 896 * methods should be handled by the individual drivers. 897 */ 898 static int 899 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 900 { 901 struct netmap_adapter *na = kring->na; 902 if_t ifp = na->ifp; 903 struct netmap_ring *ring = kring->ring; 904 u_int nm_i; /* index into the netmap kring */ 905 u_int nic_i; /* index into the NIC ring */ 906 u_int n; 907 u_int const lim = kring->nkr_num_slots - 1; 908 u_int const head = kring->rhead; 909 struct if_pkt_info pi; 910 911 /* 912 * interrupts on every tx packet are expensive so request 913 * them every half ring, or where NS_REPORT is set 914 */ 915 u_int report_frequency = kring->nkr_num_slots >> 1; 916 /* device-specific */ 917 if_ctx_t ctx = ifp->if_softc; 918 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 919 920 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 921 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 922 923 /* 924 * First part: process new packets to send. 925 * nm_i is the current index in the netmap kring, 926 * nic_i is the corresponding index in the NIC ring. 927 * 928 * If we have packets to send (nm_i != head) 929 * iterate over the netmap ring, fetch length and update 930 * the corresponding slot in the NIC ring. Some drivers also 931 * need to update the buffer's physical address in the NIC slot 932 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 933 * 934 * The netmap_reload_map() calls is especially expensive, 935 * even when (as in this case) the tag is 0, so do only 936 * when the buffer has actually changed. 937 * 938 * If possible do not set the report/intr bit on all slots, 939 * but only a few times per ring or when NS_REPORT is set. 940 * 941 * Finally, on 10G and faster drivers, it might be useful 942 * to prefetch the next slot and txr entry. 943 */ 944 945 nm_i = kring->nr_hwcur; 946 if (nm_i != head) { /* we have new packets to send */ 947 pkt_info_zero(&pi); 948 pi.ipi_segs = txq->ift_segs; 949 pi.ipi_qsidx = kring->ring_id; 950 nic_i = netmap_idx_k2n(kring, nm_i); 951 952 __builtin_prefetch(&ring->slot[nm_i]); 953 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 954 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 955 956 for (n = 0; nm_i != head; n++) { 957 struct netmap_slot *slot = &ring->slot[nm_i]; 958 u_int len = slot->len; 959 uint64_t paddr; 960 void *addr = PNMB(na, slot, &paddr); 961 int flags = (slot->flags & NS_REPORT || 962 nic_i == 0 || nic_i == report_frequency) ? 963 IPI_TX_INTR : 0; 964 965 /* device-specific */ 966 pi.ipi_len = len; 967 pi.ipi_segs[0].ds_addr = paddr; 968 pi.ipi_segs[0].ds_len = len; 969 pi.ipi_nsegs = 1; 970 pi.ipi_ndescs = 0; 971 pi.ipi_pidx = nic_i; 972 pi.ipi_flags = flags; 973 974 /* Fill the slot in the NIC ring. */ 975 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 976 DBG_COUNTER_INC(tx_encap); 977 978 /* prefetch for next round */ 979 __builtin_prefetch(&ring->slot[nm_i + 1]); 980 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 981 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 982 983 NM_CHECK_ADDR_LEN(na, addr, len); 984 985 if (slot->flags & NS_BUF_CHANGED) { 986 /* buffer has changed, reload map */ 987 netmap_reload_map(na, txq->ift_buf_tag, 988 txq->ift_sds.ifsd_map[nic_i], addr); 989 } 990 /* make sure changes to the buffer are synced */ 991 bus_dmamap_sync(txq->ift_buf_tag, 992 txq->ift_sds.ifsd_map[nic_i], 993 BUS_DMASYNC_PREWRITE); 994 995 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 996 nm_i = nm_next(nm_i, lim); 997 nic_i = nm_next(nic_i, lim); 998 } 999 kring->nr_hwcur = nm_i; 1000 1001 /* synchronize the NIC ring */ 1002 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1003 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1004 1005 /* (re)start the tx unit up to slot nic_i (excluded) */ 1006 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1007 } 1008 1009 /* 1010 * Second part: reclaim buffers for completed transmissions. 1011 * 1012 * If there are unclaimed buffers, attempt to reclaim them. 1013 * If none are reclaimed, and TX IRQs are not in use, do an initial 1014 * minimal delay, then trigger the tx handler which will spin in the 1015 * group task queue. 1016 */ 1017 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1018 if (iflib_tx_credits_update(ctx, txq)) { 1019 /* some tx completed, increment avail */ 1020 nic_i = txq->ift_cidx_processed; 1021 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1022 } 1023 } 1024 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1025 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1026 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000, 1027 iflib_timer, txq, txq->ift_timer.c_cpu); 1028 } 1029 return (0); 1030 } 1031 1032 /* 1033 * Reconcile kernel and user view of the receive ring. 1034 * Same as for the txsync, this routine must be efficient. 1035 * The caller guarantees a single invocations, but races against 1036 * the rest of the driver should be handled here. 1037 * 1038 * On call, kring->rhead is the first packet that userspace wants 1039 * to keep, and kring->rcur is the wakeup point. 1040 * The kernel has previously reported packets up to kring->rtail. 1041 * 1042 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1043 * of whether or not we received an interrupt. 1044 */ 1045 static int 1046 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1047 { 1048 struct netmap_adapter *na = kring->na; 1049 struct netmap_ring *ring = kring->ring; 1050 if_t ifp = na->ifp; 1051 iflib_fl_t fl; 1052 uint32_t nm_i; /* index into the netmap ring */ 1053 uint32_t nic_i; /* index into the NIC ring */ 1054 u_int i, n; 1055 u_int const lim = kring->nkr_num_slots - 1; 1056 u_int const head = kring->rhead; 1057 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1058 struct if_rxd_info ri; 1059 1060 if_ctx_t ctx = ifp->if_softc; 1061 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1062 if (head > lim) 1063 return netmap_ring_reinit(kring); 1064 1065 /* 1066 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far. 1067 */ 1068 1069 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1070 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1071 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1072 } 1073 1074 /* 1075 * First part: import newly received packets. 1076 * 1077 * nm_i is the index of the next free slot in the netmap ring, 1078 * nic_i is the index of the next received packet in the NIC ring, 1079 * and they may differ in case if_init() has been called while 1080 * in netmap mode. For the receive ring we have 1081 * 1082 * nic_i = rxr->next_check; 1083 * nm_i = kring->nr_hwtail (previous) 1084 * and 1085 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1086 * 1087 * rxr->next_check is set to 0 on a ring reinit 1088 */ 1089 if (netmap_no_pendintr || force_update) { 1090 int crclen = iflib_crcstrip ? 0 : 4; 1091 int error, avail; 1092 1093 for (i = 0; i < rxq->ifr_nfl; i++) { 1094 fl = &rxq->ifr_fl[i]; 1095 nic_i = fl->ifl_cidx; 1096 nm_i = netmap_idx_n2k(kring, nic_i); 1097 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1098 rxq->ifr_id, nic_i, USHRT_MAX); 1099 for (n = 0; avail > 0; n++, avail--) { 1100 rxd_info_zero(&ri); 1101 ri.iri_frags = rxq->ifr_frags; 1102 ri.iri_qsidx = kring->ring_id; 1103 ri.iri_ifp = ctx->ifc_ifp; 1104 ri.iri_cidx = nic_i; 1105 1106 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1107 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1108 ring->slot[nm_i].flags = 0; 1109 bus_dmamap_sync(fl->ifl_buf_tag, 1110 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1111 nm_i = nm_next(nm_i, lim); 1112 nic_i = nm_next(nic_i, lim); 1113 } 1114 if (n) { /* update the state variables */ 1115 if (netmap_no_pendintr && !force_update) { 1116 /* diagnostics */ 1117 iflib_rx_miss ++; 1118 iflib_rx_miss_bufs += n; 1119 } 1120 fl->ifl_cidx = nic_i; 1121 kring->nr_hwtail = nm_i; 1122 } 1123 kring->nr_kflags &= ~NKR_PENDINTR; 1124 } 1125 } 1126 /* 1127 * Second part: skip past packets that userspace has released. 1128 * (kring->nr_hwcur to head excluded), 1129 * and make the buffers available for reception. 1130 * As usual nm_i is the index in the netmap ring, 1131 * nic_i is the index in the NIC ring, and 1132 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1133 */ 1134 /* XXX not sure how this will work with multiple free lists */ 1135 nm_i = kring->nr_hwcur; 1136 1137 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1138 } 1139 1140 static void 1141 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1142 { 1143 if_ctx_t ctx = na->ifp->if_softc; 1144 1145 CTX_LOCK(ctx); 1146 if (onoff) { 1147 IFDI_INTR_ENABLE(ctx); 1148 } else { 1149 IFDI_INTR_DISABLE(ctx); 1150 } 1151 CTX_UNLOCK(ctx); 1152 } 1153 1154 1155 static int 1156 iflib_netmap_attach(if_ctx_t ctx) 1157 { 1158 struct netmap_adapter na; 1159 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1160 1161 bzero(&na, sizeof(na)); 1162 1163 na.ifp = ctx->ifc_ifp; 1164 na.na_flags = NAF_BDG_MAYSLEEP; 1165 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1166 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1167 1168 na.num_tx_desc = scctx->isc_ntxd[0]; 1169 na.num_rx_desc = scctx->isc_nrxd[0]; 1170 na.nm_txsync = iflib_netmap_txsync; 1171 na.nm_rxsync = iflib_netmap_rxsync; 1172 na.nm_register = iflib_netmap_register; 1173 na.nm_intr = iflib_netmap_intr; 1174 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1175 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1176 return (netmap_attach(&na)); 1177 } 1178 1179 static void 1180 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1181 { 1182 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1183 struct netmap_slot *slot; 1184 1185 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1186 if (slot == NULL) 1187 return; 1188 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1189 1190 /* 1191 * In netmap mode, set the map for the packet buffer. 1192 * NOTE: Some drivers (not this one) also need to set 1193 * the physical buffer address in the NIC ring. 1194 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1195 * netmap slot index, si 1196 */ 1197 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1198 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1199 NMB(na, slot + si)); 1200 } 1201 } 1202 1203 static void 1204 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1205 { 1206 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1207 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1208 struct netmap_slot *slot; 1209 uint32_t nm_i; 1210 1211 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1212 if (slot == NULL) 1213 return; 1214 nm_i = netmap_idx_n2k(kring, 0); 1215 netmap_fl_refill(rxq, kring, nm_i, true); 1216 } 1217 1218 static void 1219 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on) 1220 { 1221 struct netmap_kring *kring; 1222 uint16_t txqid; 1223 1224 txqid = txq->ift_id; 1225 kring = NA(ctx->ifc_ifp)->tx_rings[txqid]; 1226 1227 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) { 1228 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1229 BUS_DMASYNC_POSTREAD); 1230 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) 1231 netmap_tx_irq(ctx->ifc_ifp, txqid); 1232 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1233 if (hz < 2000) 1234 *reset_on = 1; 1235 else 1236 *reset_on = hz / 1000; 1237 } 1238 } 1239 } 1240 1241 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1242 1243 #else 1244 #define iflib_netmap_txq_init(ctx, txq) 1245 #define iflib_netmap_rxq_init(ctx, rxq) 1246 #define iflib_netmap_detach(ifp) 1247 1248 #define iflib_netmap_attach(ctx) (0) 1249 #define netmap_rx_irq(ifp, qid, budget) (0) 1250 #define netmap_tx_irq(ifp, qid) do {} while (0) 1251 #define iflib_netmap_timer_adjust(ctx, txq, reset_on) 1252 #endif 1253 1254 #if defined(__i386__) || defined(__amd64__) 1255 static __inline void 1256 prefetch(void *x) 1257 { 1258 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1259 } 1260 static __inline void 1261 prefetch2cachelines(void *x) 1262 { 1263 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1264 #if (CACHE_LINE_SIZE < 128) 1265 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1266 #endif 1267 } 1268 #else 1269 #define prefetch(x) 1270 #define prefetch2cachelines(x) 1271 #endif 1272 1273 static void 1274 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1275 { 1276 iflib_fl_t fl; 1277 1278 fl = &rxq->ifr_fl[flid]; 1279 iru->iru_paddrs = fl->ifl_bus_addrs; 1280 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1281 iru->iru_idxs = fl->ifl_rxd_idxs; 1282 iru->iru_qsidx = rxq->ifr_id; 1283 iru->iru_buf_size = fl->ifl_buf_size; 1284 iru->iru_flidx = fl->ifl_id; 1285 } 1286 1287 static void 1288 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1289 { 1290 if (err) 1291 return; 1292 *(bus_addr_t *) arg = segs[0].ds_addr; 1293 } 1294 1295 int 1296 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1297 { 1298 int err; 1299 device_t dev = ctx->ifc_dev; 1300 1301 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1302 align, 0, /* alignment, bounds */ 1303 BUS_SPACE_MAXADDR, /* lowaddr */ 1304 BUS_SPACE_MAXADDR, /* highaddr */ 1305 NULL, NULL, /* filter, filterarg */ 1306 size, /* maxsize */ 1307 1, /* nsegments */ 1308 size, /* maxsegsize */ 1309 BUS_DMA_ALLOCNOW, /* flags */ 1310 NULL, /* lockfunc */ 1311 NULL, /* lockarg */ 1312 &dma->idi_tag); 1313 if (err) { 1314 device_printf(dev, 1315 "%s: bus_dma_tag_create failed: %d\n", 1316 __func__, err); 1317 goto fail_0; 1318 } 1319 1320 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1321 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1322 if (err) { 1323 device_printf(dev, 1324 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1325 __func__, (uintmax_t)size, err); 1326 goto fail_1; 1327 } 1328 1329 dma->idi_paddr = IF_BAD_DMA; 1330 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1331 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1332 if (err || dma->idi_paddr == IF_BAD_DMA) { 1333 device_printf(dev, 1334 "%s: bus_dmamap_load failed: %d\n", 1335 __func__, err); 1336 goto fail_2; 1337 } 1338 1339 dma->idi_size = size; 1340 return (0); 1341 1342 fail_2: 1343 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1344 fail_1: 1345 bus_dma_tag_destroy(dma->idi_tag); 1346 fail_0: 1347 dma->idi_tag = NULL; 1348 1349 return (err); 1350 } 1351 1352 int 1353 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1354 { 1355 if_shared_ctx_t sctx = ctx->ifc_sctx; 1356 1357 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1358 1359 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1360 } 1361 1362 int 1363 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1364 { 1365 int i, err; 1366 iflib_dma_info_t *dmaiter; 1367 1368 dmaiter = dmalist; 1369 for (i = 0; i < count; i++, dmaiter++) { 1370 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1371 break; 1372 } 1373 if (err) 1374 iflib_dma_free_multi(dmalist, i); 1375 return (err); 1376 } 1377 1378 void 1379 iflib_dma_free(iflib_dma_info_t dma) 1380 { 1381 if (dma->idi_tag == NULL) 1382 return; 1383 if (dma->idi_paddr != IF_BAD_DMA) { 1384 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1385 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1386 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1387 dma->idi_paddr = IF_BAD_DMA; 1388 } 1389 if (dma->idi_vaddr != NULL) { 1390 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1391 dma->idi_vaddr = NULL; 1392 } 1393 bus_dma_tag_destroy(dma->idi_tag); 1394 dma->idi_tag = NULL; 1395 } 1396 1397 void 1398 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1399 { 1400 int i; 1401 iflib_dma_info_t *dmaiter = dmalist; 1402 1403 for (i = 0; i < count; i++, dmaiter++) 1404 iflib_dma_free(*dmaiter); 1405 } 1406 1407 #ifdef EARLY_AP_STARTUP 1408 static const int iflib_started = 1; 1409 #else 1410 /* 1411 * We used to abuse the smp_started flag to decide if the queues have been 1412 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1413 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1414 * is set. Run a SYSINIT() strictly after that to just set a usable 1415 * completion flag. 1416 */ 1417 1418 static int iflib_started; 1419 1420 static void 1421 iflib_record_started(void *arg) 1422 { 1423 iflib_started = 1; 1424 } 1425 1426 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1427 iflib_record_started, NULL); 1428 #endif 1429 1430 static int 1431 iflib_fast_intr(void *arg) 1432 { 1433 iflib_filter_info_t info = arg; 1434 struct grouptask *gtask = info->ifi_task; 1435 int result; 1436 1437 if (!iflib_started) 1438 return (FILTER_STRAY); 1439 1440 DBG_COUNTER_INC(fast_intrs); 1441 if (info->ifi_filter != NULL) { 1442 result = info->ifi_filter(info->ifi_filter_arg); 1443 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1444 return (result); 1445 } 1446 1447 GROUPTASK_ENQUEUE(gtask); 1448 return (FILTER_HANDLED); 1449 } 1450 1451 static int 1452 iflib_fast_intr_rxtx(void *arg) 1453 { 1454 iflib_filter_info_t info = arg; 1455 struct grouptask *gtask = info->ifi_task; 1456 if_ctx_t ctx; 1457 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1458 iflib_txq_t txq; 1459 void *sc; 1460 int i, cidx, result; 1461 qidx_t txqid; 1462 bool intr_enable, intr_legacy; 1463 1464 if (!iflib_started) 1465 return (FILTER_STRAY); 1466 1467 DBG_COUNTER_INC(fast_intrs); 1468 if (info->ifi_filter != NULL) { 1469 result = info->ifi_filter(info->ifi_filter_arg); 1470 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1471 return (result); 1472 } 1473 1474 ctx = rxq->ifr_ctx; 1475 sc = ctx->ifc_softc; 1476 intr_enable = false; 1477 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1478 MPASS(rxq->ifr_ntxqirq); 1479 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1480 txqid = rxq->ifr_txqid[i]; 1481 txq = &ctx->ifc_txqs[txqid]; 1482 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1483 BUS_DMASYNC_POSTREAD); 1484 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1485 if (intr_legacy) 1486 intr_enable = true; 1487 else 1488 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1489 continue; 1490 } 1491 GROUPTASK_ENQUEUE(&txq->ift_task); 1492 } 1493 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1494 cidx = rxq->ifr_cq_cidx; 1495 else 1496 cidx = rxq->ifr_fl[0].ifl_cidx; 1497 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1498 GROUPTASK_ENQUEUE(gtask); 1499 else { 1500 if (intr_legacy) 1501 intr_enable = true; 1502 else 1503 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1504 DBG_COUNTER_INC(rx_intr_enables); 1505 } 1506 if (intr_enable) 1507 IFDI_INTR_ENABLE(ctx); 1508 return (FILTER_HANDLED); 1509 } 1510 1511 1512 static int 1513 iflib_fast_intr_ctx(void *arg) 1514 { 1515 iflib_filter_info_t info = arg; 1516 struct grouptask *gtask = info->ifi_task; 1517 int result; 1518 1519 if (!iflib_started) 1520 return (FILTER_STRAY); 1521 1522 DBG_COUNTER_INC(fast_intrs); 1523 if (info->ifi_filter != NULL) { 1524 result = info->ifi_filter(info->ifi_filter_arg); 1525 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1526 return (result); 1527 } 1528 1529 GROUPTASK_ENQUEUE(gtask); 1530 return (FILTER_HANDLED); 1531 } 1532 1533 static int 1534 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1535 driver_filter_t filter, driver_intr_t handler, void *arg, 1536 const char *name) 1537 { 1538 struct resource *res; 1539 void *tag = NULL; 1540 device_t dev = ctx->ifc_dev; 1541 int flags, i, rc; 1542 1543 flags = RF_ACTIVE; 1544 if (ctx->ifc_flags & IFC_LEGACY) 1545 flags |= RF_SHAREABLE; 1546 MPASS(rid < 512); 1547 i = rid; 1548 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1549 if (res == NULL) { 1550 device_printf(dev, 1551 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1552 return (ENOMEM); 1553 } 1554 irq->ii_res = res; 1555 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1556 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1557 filter, handler, arg, &tag); 1558 if (rc != 0) { 1559 device_printf(dev, 1560 "failed to setup interrupt for rid %d, name %s: %d\n", 1561 rid, name ? name : "unknown", rc); 1562 return (rc); 1563 } else if (name) 1564 bus_describe_intr(dev, res, tag, "%s", name); 1565 1566 irq->ii_tag = tag; 1567 return (0); 1568 } 1569 1570 /********************************************************************* 1571 * 1572 * Allocate DMA resources for TX buffers as well as memory for the TX 1573 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1574 * iflib_sw_tx_desc_array structure, storing all the information that 1575 * is needed to transmit a packet on the wire. This is called only 1576 * once at attach, setup is done every reset. 1577 * 1578 **********************************************************************/ 1579 static int 1580 iflib_txsd_alloc(iflib_txq_t txq) 1581 { 1582 if_ctx_t ctx = txq->ift_ctx; 1583 if_shared_ctx_t sctx = ctx->ifc_sctx; 1584 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1585 device_t dev = ctx->ifc_dev; 1586 bus_size_t tsomaxsize; 1587 int err, nsegments, ntsosegments; 1588 bool tso; 1589 1590 nsegments = scctx->isc_tx_nsegments; 1591 ntsosegments = scctx->isc_tx_tso_segments_max; 1592 tsomaxsize = scctx->isc_tx_tso_size_max; 1593 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1594 tsomaxsize += sizeof(struct ether_vlan_header); 1595 MPASS(scctx->isc_ntxd[0] > 0); 1596 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1597 MPASS(nsegments > 0); 1598 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1599 MPASS(ntsosegments > 0); 1600 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1601 } 1602 1603 /* 1604 * Set up DMA tags for TX buffers. 1605 */ 1606 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1607 1, 0, /* alignment, bounds */ 1608 BUS_SPACE_MAXADDR, /* lowaddr */ 1609 BUS_SPACE_MAXADDR, /* highaddr */ 1610 NULL, NULL, /* filter, filterarg */ 1611 sctx->isc_tx_maxsize, /* maxsize */ 1612 nsegments, /* nsegments */ 1613 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1614 0, /* flags */ 1615 NULL, /* lockfunc */ 1616 NULL, /* lockfuncarg */ 1617 &txq->ift_buf_tag))) { 1618 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1619 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1620 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1621 goto fail; 1622 } 1623 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1624 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1625 1, 0, /* alignment, bounds */ 1626 BUS_SPACE_MAXADDR, /* lowaddr */ 1627 BUS_SPACE_MAXADDR, /* highaddr */ 1628 NULL, NULL, /* filter, filterarg */ 1629 tsomaxsize, /* maxsize */ 1630 ntsosegments, /* nsegments */ 1631 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1632 0, /* flags */ 1633 NULL, /* lockfunc */ 1634 NULL, /* lockfuncarg */ 1635 &txq->ift_tso_buf_tag))) { 1636 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1637 err); 1638 goto fail; 1639 } 1640 1641 /* Allocate memory for the TX mbuf map. */ 1642 if (!(txq->ift_sds.ifsd_m = 1643 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1644 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1645 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1646 err = ENOMEM; 1647 goto fail; 1648 } 1649 1650 /* 1651 * Create the DMA maps for TX buffers. 1652 */ 1653 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1654 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1655 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1656 device_printf(dev, 1657 "Unable to allocate TX buffer DMA map memory\n"); 1658 err = ENOMEM; 1659 goto fail; 1660 } 1661 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1662 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1663 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1664 device_printf(dev, 1665 "Unable to allocate TSO TX buffer map memory\n"); 1666 err = ENOMEM; 1667 goto fail; 1668 } 1669 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1670 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1671 &txq->ift_sds.ifsd_map[i]); 1672 if (err != 0) { 1673 device_printf(dev, "Unable to create TX DMA map\n"); 1674 goto fail; 1675 } 1676 if (!tso) 1677 continue; 1678 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1679 &txq->ift_sds.ifsd_tso_map[i]); 1680 if (err != 0) { 1681 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1682 goto fail; 1683 } 1684 } 1685 return (0); 1686 fail: 1687 /* We free all, it handles case where we are in the middle */ 1688 iflib_tx_structures_free(ctx); 1689 return (err); 1690 } 1691 1692 static void 1693 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1694 { 1695 bus_dmamap_t map; 1696 1697 map = NULL; 1698 if (txq->ift_sds.ifsd_map != NULL) 1699 map = txq->ift_sds.ifsd_map[i]; 1700 if (map != NULL) { 1701 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1702 bus_dmamap_unload(txq->ift_buf_tag, map); 1703 bus_dmamap_destroy(txq->ift_buf_tag, map); 1704 txq->ift_sds.ifsd_map[i] = NULL; 1705 } 1706 1707 map = NULL; 1708 if (txq->ift_sds.ifsd_tso_map != NULL) 1709 map = txq->ift_sds.ifsd_tso_map[i]; 1710 if (map != NULL) { 1711 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1712 BUS_DMASYNC_POSTWRITE); 1713 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1714 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1715 txq->ift_sds.ifsd_tso_map[i] = NULL; 1716 } 1717 } 1718 1719 static void 1720 iflib_txq_destroy(iflib_txq_t txq) 1721 { 1722 if_ctx_t ctx = txq->ift_ctx; 1723 1724 for (int i = 0; i < txq->ift_size; i++) 1725 iflib_txsd_destroy(ctx, txq, i); 1726 if (txq->ift_sds.ifsd_map != NULL) { 1727 free(txq->ift_sds.ifsd_map, M_IFLIB); 1728 txq->ift_sds.ifsd_map = NULL; 1729 } 1730 if (txq->ift_sds.ifsd_tso_map != NULL) { 1731 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1732 txq->ift_sds.ifsd_tso_map = NULL; 1733 } 1734 if (txq->ift_sds.ifsd_m != NULL) { 1735 free(txq->ift_sds.ifsd_m, M_IFLIB); 1736 txq->ift_sds.ifsd_m = NULL; 1737 } 1738 if (txq->ift_buf_tag != NULL) { 1739 bus_dma_tag_destroy(txq->ift_buf_tag); 1740 txq->ift_buf_tag = NULL; 1741 } 1742 if (txq->ift_tso_buf_tag != NULL) { 1743 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1744 txq->ift_tso_buf_tag = NULL; 1745 } 1746 } 1747 1748 static void 1749 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1750 { 1751 struct mbuf **mp; 1752 1753 mp = &txq->ift_sds.ifsd_m[i]; 1754 if (*mp == NULL) 1755 return; 1756 1757 if (txq->ift_sds.ifsd_map != NULL) { 1758 bus_dmamap_sync(txq->ift_buf_tag, 1759 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1760 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1761 } 1762 if (txq->ift_sds.ifsd_tso_map != NULL) { 1763 bus_dmamap_sync(txq->ift_tso_buf_tag, 1764 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1765 bus_dmamap_unload(txq->ift_tso_buf_tag, 1766 txq->ift_sds.ifsd_tso_map[i]); 1767 } 1768 m_free(*mp); 1769 DBG_COUNTER_INC(tx_frees); 1770 *mp = NULL; 1771 } 1772 1773 static int 1774 iflib_txq_setup(iflib_txq_t txq) 1775 { 1776 if_ctx_t ctx = txq->ift_ctx; 1777 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1778 if_shared_ctx_t sctx = ctx->ifc_sctx; 1779 iflib_dma_info_t di; 1780 int i; 1781 1782 /* Set number of descriptors available */ 1783 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1784 /* XXX make configurable */ 1785 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1786 1787 /* Reset indices */ 1788 txq->ift_cidx_processed = 0; 1789 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1790 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1791 1792 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1793 bzero((void *)di->idi_vaddr, di->idi_size); 1794 1795 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1796 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1797 bus_dmamap_sync(di->idi_tag, di->idi_map, 1798 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1799 return (0); 1800 } 1801 1802 /********************************************************************* 1803 * 1804 * Allocate DMA resources for RX buffers as well as memory for the RX 1805 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1806 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1807 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1808 * Since we use use one entry in iflib_sw_rx_desc_array per received 1809 * packet, the maximum number of entries we'll need is equal to the 1810 * number of hardware receive descriptors that we've allocated. 1811 * 1812 **********************************************************************/ 1813 static int 1814 iflib_rxsd_alloc(iflib_rxq_t rxq) 1815 { 1816 if_ctx_t ctx = rxq->ifr_ctx; 1817 if_shared_ctx_t sctx = ctx->ifc_sctx; 1818 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1819 device_t dev = ctx->ifc_dev; 1820 iflib_fl_t fl; 1821 int err; 1822 1823 MPASS(scctx->isc_nrxd[0] > 0); 1824 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1825 1826 fl = rxq->ifr_fl; 1827 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1828 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1829 /* Set up DMA tag for RX buffers. */ 1830 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1831 1, 0, /* alignment, bounds */ 1832 BUS_SPACE_MAXADDR, /* lowaddr */ 1833 BUS_SPACE_MAXADDR, /* highaddr */ 1834 NULL, NULL, /* filter, filterarg */ 1835 sctx->isc_rx_maxsize, /* maxsize */ 1836 sctx->isc_rx_nsegments, /* nsegments */ 1837 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1838 0, /* flags */ 1839 NULL, /* lockfunc */ 1840 NULL, /* lockarg */ 1841 &fl->ifl_buf_tag); 1842 if (err) { 1843 device_printf(dev, 1844 "Unable to allocate RX DMA tag: %d\n", err); 1845 goto fail; 1846 } 1847 1848 /* Allocate memory for the RX mbuf map. */ 1849 if (!(fl->ifl_sds.ifsd_m = 1850 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1851 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1852 device_printf(dev, 1853 "Unable to allocate RX mbuf map memory\n"); 1854 err = ENOMEM; 1855 goto fail; 1856 } 1857 1858 /* Allocate memory for the direct RX cluster pointer map. */ 1859 if (!(fl->ifl_sds.ifsd_cl = 1860 (caddr_t *) malloc(sizeof(caddr_t) * 1861 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1862 device_printf(dev, 1863 "Unable to allocate RX cluster map memory\n"); 1864 err = ENOMEM; 1865 goto fail; 1866 } 1867 1868 /* Allocate memory for the RX cluster bus address map. */ 1869 if (!(fl->ifl_sds.ifsd_ba = 1870 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1871 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1872 device_printf(dev, 1873 "Unable to allocate RX bus address map memory\n"); 1874 err = ENOMEM; 1875 goto fail; 1876 } 1877 1878 /* 1879 * Create the DMA maps for RX buffers. 1880 */ 1881 if (!(fl->ifl_sds.ifsd_map = 1882 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1883 device_printf(dev, 1884 "Unable to allocate RX buffer DMA map memory\n"); 1885 err = ENOMEM; 1886 goto fail; 1887 } 1888 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1889 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 1890 &fl->ifl_sds.ifsd_map[i]); 1891 if (err != 0) { 1892 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1893 goto fail; 1894 } 1895 } 1896 } 1897 return (0); 1898 1899 fail: 1900 iflib_rx_structures_free(ctx); 1901 return (err); 1902 } 1903 1904 1905 /* 1906 * Internal service routines 1907 */ 1908 1909 struct rxq_refill_cb_arg { 1910 int error; 1911 bus_dma_segment_t seg; 1912 int nseg; 1913 }; 1914 1915 static void 1916 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1917 { 1918 struct rxq_refill_cb_arg *cb_arg = arg; 1919 1920 cb_arg->error = error; 1921 cb_arg->seg = segs[0]; 1922 cb_arg->nseg = nseg; 1923 } 1924 1925 /** 1926 * _iflib_fl_refill - refill an rxq free-buffer list 1927 * @ctx: the iflib context 1928 * @fl: the free list to refill 1929 * @count: the number of new buffers to allocate 1930 * 1931 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 1932 * The caller must assure that @count does not exceed the queue's capacity. 1933 */ 1934 static void 1935 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1936 { 1937 struct if_rxd_update iru; 1938 struct rxq_refill_cb_arg cb_arg; 1939 struct mbuf *m; 1940 caddr_t cl, *sd_cl; 1941 struct mbuf **sd_m; 1942 bus_dmamap_t *sd_map; 1943 bus_addr_t bus_addr, *sd_ba; 1944 int err, frag_idx, i, idx, n, pidx; 1945 qidx_t credits; 1946 1947 sd_m = fl->ifl_sds.ifsd_m; 1948 sd_map = fl->ifl_sds.ifsd_map; 1949 sd_cl = fl->ifl_sds.ifsd_cl; 1950 sd_ba = fl->ifl_sds.ifsd_ba; 1951 pidx = fl->ifl_pidx; 1952 idx = pidx; 1953 frag_idx = fl->ifl_fragidx; 1954 credits = fl->ifl_credits; 1955 1956 i = 0; 1957 n = count; 1958 MPASS(n > 0); 1959 MPASS(credits + n <= fl->ifl_size); 1960 1961 if (pidx < fl->ifl_cidx) 1962 MPASS(pidx + n <= fl->ifl_cidx); 1963 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1964 MPASS(fl->ifl_gen == 0); 1965 if (pidx > fl->ifl_cidx) 1966 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1967 1968 DBG_COUNTER_INC(fl_refills); 1969 if (n > 8) 1970 DBG_COUNTER_INC(fl_refills_large); 1971 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1972 while (n--) { 1973 /* 1974 * We allocate an uninitialized mbuf + cluster, mbuf is 1975 * initialized after rx. 1976 * 1977 * If the cluster is still set then we know a minimum sized packet was received 1978 */ 1979 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 1980 &frag_idx); 1981 if (frag_idx < 0) 1982 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1983 MPASS(frag_idx >= 0); 1984 if ((cl = sd_cl[frag_idx]) == NULL) { 1985 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1986 break; 1987 1988 cb_arg.error = 0; 1989 MPASS(sd_map != NULL); 1990 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 1991 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 1992 BUS_DMA_NOWAIT); 1993 if (err != 0 || cb_arg.error) { 1994 /* 1995 * !zone_pack ? 1996 */ 1997 if (fl->ifl_zone == zone_pack) 1998 uma_zfree(fl->ifl_zone, cl); 1999 break; 2000 } 2001 2002 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2003 sd_cl[frag_idx] = cl; 2004 #if MEMORY_LOGGING 2005 fl->ifl_cl_enqueued++; 2006 #endif 2007 } else { 2008 bus_addr = sd_ba[frag_idx]; 2009 } 2010 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2011 BUS_DMASYNC_PREREAD); 2012 2013 if (sd_m[frag_idx] == NULL) { 2014 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 2015 break; 2016 } 2017 sd_m[frag_idx] = m; 2018 } 2019 bit_set(fl->ifl_rx_bitmap, frag_idx); 2020 #if MEMORY_LOGGING 2021 fl->ifl_m_enqueued++; 2022 #endif 2023 2024 DBG_COUNTER_INC(rx_allocs); 2025 fl->ifl_rxd_idxs[i] = frag_idx; 2026 fl->ifl_bus_addrs[i] = bus_addr; 2027 fl->ifl_vm_addrs[i] = cl; 2028 credits++; 2029 i++; 2030 MPASS(credits <= fl->ifl_size); 2031 if (++idx == fl->ifl_size) { 2032 fl->ifl_gen = 1; 2033 idx = 0; 2034 } 2035 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2036 iru.iru_pidx = pidx; 2037 iru.iru_count = i; 2038 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2039 i = 0; 2040 pidx = idx; 2041 fl->ifl_pidx = idx; 2042 fl->ifl_credits = credits; 2043 } 2044 } 2045 2046 if (i) { 2047 iru.iru_pidx = pidx; 2048 iru.iru_count = i; 2049 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2050 fl->ifl_pidx = idx; 2051 fl->ifl_credits = credits; 2052 } 2053 DBG_COUNTER_INC(rxd_flush); 2054 if (fl->ifl_pidx == 0) 2055 pidx = fl->ifl_size - 1; 2056 else 2057 pidx = fl->ifl_pidx - 1; 2058 2059 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2060 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2061 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 2062 fl->ifl_fragidx = frag_idx; 2063 } 2064 2065 static __inline void 2066 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 2067 { 2068 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2069 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2070 #ifdef INVARIANTS 2071 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2072 #endif 2073 2074 MPASS(fl->ifl_credits <= fl->ifl_size); 2075 MPASS(reclaimable == delta); 2076 2077 if (reclaimable > 0) 2078 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 2079 } 2080 2081 uint8_t 2082 iflib_in_detach(if_ctx_t ctx) 2083 { 2084 bool in_detach; 2085 2086 STATE_LOCK(ctx); 2087 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2088 STATE_UNLOCK(ctx); 2089 return (in_detach); 2090 } 2091 2092 static void 2093 iflib_fl_bufs_free(iflib_fl_t fl) 2094 { 2095 iflib_dma_info_t idi = fl->ifl_ifdi; 2096 bus_dmamap_t sd_map; 2097 uint32_t i; 2098 2099 for (i = 0; i < fl->ifl_size; i++) { 2100 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2101 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2102 2103 if (*sd_cl != NULL) { 2104 sd_map = fl->ifl_sds.ifsd_map[i]; 2105 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2106 BUS_DMASYNC_POSTREAD); 2107 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2108 if (*sd_cl != NULL) 2109 uma_zfree(fl->ifl_zone, *sd_cl); 2110 // XXX: Should this get moved out? 2111 if (iflib_in_detach(fl->ifl_rxq->ifr_ctx)) 2112 bus_dmamap_destroy(fl->ifl_buf_tag, sd_map); 2113 if (*sd_m != NULL) { 2114 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2115 uma_zfree(zone_mbuf, *sd_m); 2116 } 2117 } else { 2118 MPASS(*sd_cl == NULL); 2119 MPASS(*sd_m == NULL); 2120 } 2121 #if MEMORY_LOGGING 2122 fl->ifl_m_dequeued++; 2123 fl->ifl_cl_dequeued++; 2124 #endif 2125 *sd_cl = NULL; 2126 *sd_m = NULL; 2127 } 2128 #ifdef INVARIANTS 2129 for (i = 0; i < fl->ifl_size; i++) { 2130 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2131 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2132 } 2133 #endif 2134 /* 2135 * Reset free list values 2136 */ 2137 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2138 bzero(idi->idi_vaddr, idi->idi_size); 2139 } 2140 2141 /********************************************************************* 2142 * 2143 * Initialize a free list and its buffers. 2144 * 2145 **********************************************************************/ 2146 static int 2147 iflib_fl_setup(iflib_fl_t fl) 2148 { 2149 iflib_rxq_t rxq = fl->ifl_rxq; 2150 if_ctx_t ctx = rxq->ifr_ctx; 2151 2152 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2153 /* 2154 ** Free current RX buffer structs and their mbufs 2155 */ 2156 iflib_fl_bufs_free(fl); 2157 /* Now replenish the mbufs */ 2158 MPASS(fl->ifl_credits == 0); 2159 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2160 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2161 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2162 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2163 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2164 2165 2166 /* avoid pre-allocating zillions of clusters to an idle card 2167 * potentially speeding up attach 2168 */ 2169 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2170 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2171 if (min(128, fl->ifl_size) != fl->ifl_credits) 2172 return (ENOBUFS); 2173 /* 2174 * handle failure 2175 */ 2176 MPASS(rxq != NULL); 2177 MPASS(fl->ifl_ifdi != NULL); 2178 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2179 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2180 return (0); 2181 } 2182 2183 /********************************************************************* 2184 * 2185 * Free receive ring data structures 2186 * 2187 **********************************************************************/ 2188 static void 2189 iflib_rx_sds_free(iflib_rxq_t rxq) 2190 { 2191 iflib_fl_t fl; 2192 int i, j; 2193 2194 if (rxq->ifr_fl != NULL) { 2195 for (i = 0; i < rxq->ifr_nfl; i++) { 2196 fl = &rxq->ifr_fl[i]; 2197 if (fl->ifl_buf_tag != NULL) { 2198 if (fl->ifl_sds.ifsd_map != NULL) { 2199 for (j = 0; j < fl->ifl_size; j++) { 2200 if (fl->ifl_sds.ifsd_map[j] == 2201 NULL) 2202 continue; 2203 bus_dmamap_sync( 2204 fl->ifl_buf_tag, 2205 fl->ifl_sds.ifsd_map[j], 2206 BUS_DMASYNC_POSTREAD); 2207 bus_dmamap_unload( 2208 fl->ifl_buf_tag, 2209 fl->ifl_sds.ifsd_map[j]); 2210 } 2211 } 2212 bus_dma_tag_destroy(fl->ifl_buf_tag); 2213 fl->ifl_buf_tag = NULL; 2214 } 2215 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2216 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2217 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2218 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2219 fl->ifl_sds.ifsd_m = NULL; 2220 fl->ifl_sds.ifsd_cl = NULL; 2221 fl->ifl_sds.ifsd_ba = NULL; 2222 fl->ifl_sds.ifsd_map = NULL; 2223 } 2224 free(rxq->ifr_fl, M_IFLIB); 2225 rxq->ifr_fl = NULL; 2226 rxq->ifr_cq_cidx = 0; 2227 } 2228 } 2229 2230 /* 2231 * Timer routine 2232 */ 2233 static void 2234 iflib_timer(void *arg) 2235 { 2236 iflib_txq_t txq = arg; 2237 if_ctx_t ctx = txq->ift_ctx; 2238 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2239 uint64_t this_tick = ticks; 2240 uint32_t reset_on = hz / 2; 2241 2242 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2243 return; 2244 2245 /* 2246 ** Check on the state of the TX queue(s), this 2247 ** can be done without the lock because its RO 2248 ** and the HUNG state will be static if set. 2249 */ 2250 if (this_tick - txq->ift_last_timer_tick >= hz / 2) { 2251 txq->ift_last_timer_tick = this_tick; 2252 IFDI_TIMER(ctx, txq->ift_id); 2253 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2254 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2255 (sctx->isc_pause_frames == 0))) 2256 goto hung; 2257 2258 if (ifmp_ring_is_stalled(txq->ift_br)) 2259 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2260 txq->ift_cleaned_prev = txq->ift_cleaned; 2261 } 2262 #ifdef DEV_NETMAP 2263 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 2264 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 2265 #endif 2266 /* handle any laggards */ 2267 if (txq->ift_db_pending) 2268 GROUPTASK_ENQUEUE(&txq->ift_task); 2269 2270 sctx->isc_pause_frames = 0; 2271 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2272 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 2273 return; 2274 2275 hung: 2276 device_printf(ctx->ifc_dev, 2277 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2278 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2279 STATE_LOCK(ctx); 2280 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2281 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2282 iflib_admin_intr_deferred(ctx); 2283 STATE_UNLOCK(ctx); 2284 } 2285 2286 static void 2287 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2288 { 2289 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2290 2291 /* 2292 * XXX don't set the max_frame_size to larger 2293 * than the hardware can handle 2294 */ 2295 if (sctx->isc_max_frame_size <= MCLBYTES) 2296 ctx->ifc_rx_mbuf_sz = MCLBYTES; 2297 else 2298 ctx->ifc_rx_mbuf_sz = MJUMPAGESIZE; 2299 } 2300 2301 uint32_t 2302 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2303 { 2304 2305 return (ctx->ifc_rx_mbuf_sz); 2306 } 2307 2308 static void 2309 iflib_init_locked(if_ctx_t ctx) 2310 { 2311 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2312 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2313 if_t ifp = ctx->ifc_ifp; 2314 iflib_fl_t fl; 2315 iflib_txq_t txq; 2316 iflib_rxq_t rxq; 2317 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2318 2319 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2320 IFDI_INTR_DISABLE(ctx); 2321 2322 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2323 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2324 /* Set hardware offload abilities */ 2325 if_clearhwassist(ifp); 2326 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2327 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2328 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2329 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2330 if (if_getcapenable(ifp) & IFCAP_TSO4) 2331 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2332 if (if_getcapenable(ifp) & IFCAP_TSO6) 2333 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2334 2335 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2336 CALLOUT_LOCK(txq); 2337 callout_stop(&txq->ift_timer); 2338 CALLOUT_UNLOCK(txq); 2339 iflib_netmap_txq_init(ctx, txq); 2340 } 2341 2342 /* 2343 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2344 * that drivers can use the value when setting up the hardware receive 2345 * buffers. 2346 */ 2347 iflib_calc_rx_mbuf_sz(ctx); 2348 2349 #ifdef INVARIANTS 2350 i = if_getdrvflags(ifp); 2351 #endif 2352 IFDI_INIT(ctx); 2353 MPASS(if_getdrvflags(ifp) == i); 2354 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2355 /* XXX this should really be done on a per-queue basis */ 2356 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2357 MPASS(rxq->ifr_id == i); 2358 iflib_netmap_rxq_init(ctx, rxq); 2359 continue; 2360 } 2361 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2362 if (iflib_fl_setup(fl)) { 2363 device_printf(ctx->ifc_dev, 2364 "setting up free list %d failed - " 2365 "check cluster settings\n", j); 2366 goto done; 2367 } 2368 } 2369 } 2370 done: 2371 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2372 IFDI_INTR_ENABLE(ctx); 2373 txq = ctx->ifc_txqs; 2374 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2375 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2376 txq->ift_timer.c_cpu); 2377 } 2378 2379 static int 2380 iflib_media_change(if_t ifp) 2381 { 2382 if_ctx_t ctx = if_getsoftc(ifp); 2383 int err; 2384 2385 CTX_LOCK(ctx); 2386 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2387 iflib_init_locked(ctx); 2388 CTX_UNLOCK(ctx); 2389 return (err); 2390 } 2391 2392 static void 2393 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2394 { 2395 if_ctx_t ctx = if_getsoftc(ifp); 2396 2397 CTX_LOCK(ctx); 2398 IFDI_UPDATE_ADMIN_STATUS(ctx); 2399 IFDI_MEDIA_STATUS(ctx, ifmr); 2400 CTX_UNLOCK(ctx); 2401 } 2402 2403 void 2404 iflib_stop(if_ctx_t ctx) 2405 { 2406 iflib_txq_t txq = ctx->ifc_txqs; 2407 iflib_rxq_t rxq = ctx->ifc_rxqs; 2408 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2409 if_shared_ctx_t sctx = ctx->ifc_sctx; 2410 iflib_dma_info_t di; 2411 iflib_fl_t fl; 2412 int i, j; 2413 2414 /* Tell the stack that the interface is no longer active */ 2415 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2416 2417 IFDI_INTR_DISABLE(ctx); 2418 DELAY(1000); 2419 IFDI_STOP(ctx); 2420 DELAY(1000); 2421 2422 iflib_debug_reset(); 2423 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2424 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2425 /* make sure all transmitters have completed before proceeding XXX */ 2426 2427 CALLOUT_LOCK(txq); 2428 callout_stop(&txq->ift_timer); 2429 CALLOUT_UNLOCK(txq); 2430 2431 /* clean any enqueued buffers */ 2432 iflib_ifmp_purge(txq); 2433 /* Free any existing tx buffers. */ 2434 for (j = 0; j < txq->ift_size; j++) { 2435 iflib_txsd_free(ctx, txq, j); 2436 } 2437 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2438 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2439 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2440 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2441 txq->ift_pullups = 0; 2442 ifmp_ring_reset_stats(txq->ift_br); 2443 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2444 bzero((void *)di->idi_vaddr, di->idi_size); 2445 } 2446 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2447 /* make sure all transmitters have completed before proceeding XXX */ 2448 2449 rxq->ifr_cq_cidx = 0; 2450 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2451 bzero((void *)di->idi_vaddr, di->idi_size); 2452 /* also resets the free lists pidx/cidx */ 2453 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2454 iflib_fl_bufs_free(fl); 2455 } 2456 } 2457 2458 static inline caddr_t 2459 calc_next_rxd(iflib_fl_t fl, int cidx) 2460 { 2461 qidx_t size; 2462 int nrxd; 2463 caddr_t start, end, cur, next; 2464 2465 nrxd = fl->ifl_size; 2466 size = fl->ifl_rxd_size; 2467 start = fl->ifl_ifdi->idi_vaddr; 2468 2469 if (__predict_false(size == 0)) 2470 return (start); 2471 cur = start + size*cidx; 2472 end = start + size*nrxd; 2473 next = CACHE_PTR_NEXT(cur); 2474 return (next < end ? next : start); 2475 } 2476 2477 static inline void 2478 prefetch_pkts(iflib_fl_t fl, int cidx) 2479 { 2480 int nextptr; 2481 int nrxd = fl->ifl_size; 2482 caddr_t next_rxd; 2483 2484 2485 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2486 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2487 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2488 next_rxd = calc_next_rxd(fl, cidx); 2489 prefetch(next_rxd); 2490 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2491 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2492 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2493 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2494 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2495 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2496 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2497 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2498 } 2499 2500 static struct mbuf * 2501 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2502 int *pf_rv, if_rxd_info_t ri) 2503 { 2504 bus_dmamap_t map; 2505 iflib_fl_t fl; 2506 caddr_t payload; 2507 struct mbuf *m; 2508 int flid, cidx, len, next; 2509 2510 map = NULL; 2511 flid = irf->irf_flid; 2512 cidx = irf->irf_idx; 2513 fl = &rxq->ifr_fl[flid]; 2514 sd->ifsd_fl = fl; 2515 sd->ifsd_cidx = cidx; 2516 m = fl->ifl_sds.ifsd_m[cidx]; 2517 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2518 fl->ifl_credits--; 2519 #if MEMORY_LOGGING 2520 fl->ifl_m_dequeued++; 2521 #endif 2522 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2523 prefetch_pkts(fl, cidx); 2524 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2525 prefetch(&fl->ifl_sds.ifsd_map[next]); 2526 map = fl->ifl_sds.ifsd_map[cidx]; 2527 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2528 2529 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2530 MPASS(fl->ifl_cidx == cidx); 2531 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2532 2533 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL) { 2534 payload = *sd->ifsd_cl; 2535 payload += ri->iri_pad; 2536 len = ri->iri_len - ri->iri_pad; 2537 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp, 2538 len | PFIL_MEMPTR | PFIL_IN, NULL); 2539 switch (*pf_rv) { 2540 case PFIL_DROPPED: 2541 case PFIL_CONSUMED: 2542 /* 2543 * The filter ate it. Everything is recycled. 2544 */ 2545 m = NULL; 2546 unload = 0; 2547 break; 2548 case PFIL_REALLOCED: 2549 /* 2550 * The filter copied it. Everything is recycled. 2551 */ 2552 m = pfil_mem2mbuf(payload); 2553 unload = 0; 2554 break; 2555 case PFIL_PASS: 2556 /* 2557 * Filter said it was OK, so receive like 2558 * normal 2559 */ 2560 fl->ifl_sds.ifsd_m[cidx] = NULL; 2561 break; 2562 default: 2563 MPASS(0); 2564 } 2565 } else { 2566 fl->ifl_sds.ifsd_m[cidx] = NULL; 2567 *pf_rv = PFIL_PASS; 2568 } 2569 2570 if (unload) 2571 bus_dmamap_unload(fl->ifl_buf_tag, map); 2572 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2573 if (__predict_false(fl->ifl_cidx == 0)) 2574 fl->ifl_gen = 0; 2575 bit_clear(fl->ifl_rx_bitmap, cidx); 2576 return (m); 2577 } 2578 2579 static struct mbuf * 2580 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2581 { 2582 struct mbuf *m, *mh, *mt; 2583 caddr_t cl; 2584 int *pf_rv_ptr, flags, i, padlen; 2585 bool consumed; 2586 2587 i = 0; 2588 mh = NULL; 2589 consumed = false; 2590 *pf_rv = PFIL_PASS; 2591 pf_rv_ptr = pf_rv; 2592 do { 2593 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2594 pf_rv_ptr, ri); 2595 2596 MPASS(*sd->ifsd_cl != NULL); 2597 2598 /* 2599 * Exclude zero-length frags & frags from 2600 * packets the filter has consumed or dropped 2601 */ 2602 if (ri->iri_frags[i].irf_len == 0 || consumed || 2603 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2604 if (mh == NULL) { 2605 /* everything saved here */ 2606 consumed = true; 2607 pf_rv_ptr = NULL; 2608 continue; 2609 } 2610 /* XXX we can save the cluster here, but not the mbuf */ 2611 m_init(m, M_NOWAIT, MT_DATA, 0); 2612 m_free(m); 2613 continue; 2614 } 2615 if (mh == NULL) { 2616 flags = M_PKTHDR|M_EXT; 2617 mh = mt = m; 2618 padlen = ri->iri_pad; 2619 } else { 2620 flags = M_EXT; 2621 mt->m_next = m; 2622 mt = m; 2623 /* assuming padding is only on the first fragment */ 2624 padlen = 0; 2625 } 2626 cl = *sd->ifsd_cl; 2627 *sd->ifsd_cl = NULL; 2628 2629 /* Can these two be made one ? */ 2630 m_init(m, M_NOWAIT, MT_DATA, flags); 2631 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2632 /* 2633 * These must follow m_init and m_cljset 2634 */ 2635 m->m_data += padlen; 2636 ri->iri_len -= padlen; 2637 m->m_len = ri->iri_frags[i].irf_len; 2638 } while (++i < ri->iri_nfrags); 2639 2640 return (mh); 2641 } 2642 2643 /* 2644 * Process one software descriptor 2645 */ 2646 static struct mbuf * 2647 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2648 { 2649 struct if_rxsd sd; 2650 struct mbuf *m; 2651 int pf_rv; 2652 2653 /* should I merge this back in now that the two paths are basically duplicated? */ 2654 if (ri->iri_nfrags == 1 && 2655 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2656 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2657 &pf_rv, ri); 2658 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2659 return (m); 2660 if (pf_rv == PFIL_PASS) { 2661 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2662 #ifndef __NO_STRICT_ALIGNMENT 2663 if (!IP_ALIGNED(m)) 2664 m->m_data += 2; 2665 #endif 2666 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2667 m->m_len = ri->iri_frags[0].irf_len; 2668 } 2669 } else { 2670 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2671 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2672 return (m); 2673 } 2674 m->m_pkthdr.len = ri->iri_len; 2675 m->m_pkthdr.rcvif = ri->iri_ifp; 2676 m->m_flags |= ri->iri_flags; 2677 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2678 m->m_pkthdr.flowid = ri->iri_flowid; 2679 M_HASHTYPE_SET(m, ri->iri_rsstype); 2680 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2681 m->m_pkthdr.csum_data = ri->iri_csum_data; 2682 return (m); 2683 } 2684 2685 #if defined(INET6) || defined(INET) 2686 static void 2687 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2688 { 2689 CURVNET_SET(lc->ifp->if_vnet); 2690 #if defined(INET6) 2691 *v6 = V_ip6_forwarding; 2692 #endif 2693 #if defined(INET) 2694 *v4 = V_ipforwarding; 2695 #endif 2696 CURVNET_RESTORE(); 2697 } 2698 2699 /* 2700 * Returns true if it's possible this packet could be LROed. 2701 * if it returns false, it is guaranteed that tcp_lro_rx() 2702 * would not return zero. 2703 */ 2704 static bool 2705 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2706 { 2707 struct ether_header *eh; 2708 2709 eh = mtod(m, struct ether_header *); 2710 switch (eh->ether_type) { 2711 #if defined(INET6) 2712 case htons(ETHERTYPE_IPV6): 2713 return (!v6_forwarding); 2714 #endif 2715 #if defined (INET) 2716 case htons(ETHERTYPE_IP): 2717 return (!v4_forwarding); 2718 #endif 2719 } 2720 2721 return false; 2722 } 2723 #else 2724 static void 2725 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2726 { 2727 } 2728 #endif 2729 2730 static bool 2731 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2732 { 2733 if_t ifp; 2734 if_ctx_t ctx = rxq->ifr_ctx; 2735 if_shared_ctx_t sctx = ctx->ifc_sctx; 2736 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2737 int avail, i; 2738 qidx_t *cidxp; 2739 struct if_rxd_info ri; 2740 int err, budget_left, rx_bytes, rx_pkts; 2741 iflib_fl_t fl; 2742 int lro_enabled; 2743 bool v4_forwarding, v6_forwarding, lro_possible; 2744 2745 /* 2746 * XXX early demux data packets so that if_input processing only handles 2747 * acks in interrupt context 2748 */ 2749 struct mbuf *m, *mh, *mt, *mf; 2750 2751 lro_possible = v4_forwarding = v6_forwarding = false; 2752 ifp = ctx->ifc_ifp; 2753 mh = mt = NULL; 2754 MPASS(budget > 0); 2755 rx_pkts = rx_bytes = 0; 2756 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2757 cidxp = &rxq->ifr_cq_cidx; 2758 else 2759 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2760 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2761 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2762 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2763 DBG_COUNTER_INC(rx_unavail); 2764 return (false); 2765 } 2766 2767 /* pfil needs the vnet to be set */ 2768 CURVNET_SET_QUIET(ifp->if_vnet); 2769 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2770 if (__predict_false(!CTX_ACTIVE(ctx))) { 2771 DBG_COUNTER_INC(rx_ctx_inactive); 2772 break; 2773 } 2774 /* 2775 * Reset client set fields to their default values 2776 */ 2777 rxd_info_zero(&ri); 2778 ri.iri_qsidx = rxq->ifr_id; 2779 ri.iri_cidx = *cidxp; 2780 ri.iri_ifp = ifp; 2781 ri.iri_frags = rxq->ifr_frags; 2782 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2783 2784 if (err) 2785 goto err; 2786 rx_pkts += 1; 2787 rx_bytes += ri.iri_len; 2788 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2789 *cidxp = ri.iri_cidx; 2790 /* Update our consumer index */ 2791 /* XXX NB: shurd - check if this is still safe */ 2792 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2793 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2794 /* was this only a completion queue message? */ 2795 if (__predict_false(ri.iri_nfrags == 0)) 2796 continue; 2797 } 2798 MPASS(ri.iri_nfrags != 0); 2799 MPASS(ri.iri_len != 0); 2800 2801 /* will advance the cidx on the corresponding free lists */ 2802 m = iflib_rxd_pkt_get(rxq, &ri); 2803 avail--; 2804 budget_left--; 2805 if (avail == 0 && budget_left) 2806 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2807 2808 if (__predict_false(m == NULL)) 2809 continue; 2810 2811 /* imm_pkt: -- cxgb */ 2812 if (mh == NULL) 2813 mh = mt = m; 2814 else { 2815 mt->m_nextpkt = m; 2816 mt = m; 2817 } 2818 } 2819 CURVNET_RESTORE(); 2820 /* make sure that we can refill faster than drain */ 2821 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2822 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2823 2824 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2825 if (lro_enabled) 2826 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2827 mt = mf = NULL; 2828 while (mh != NULL) { 2829 m = mh; 2830 mh = mh->m_nextpkt; 2831 m->m_nextpkt = NULL; 2832 #ifndef __NO_STRICT_ALIGNMENT 2833 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2834 continue; 2835 #endif 2836 rx_bytes += m->m_pkthdr.len; 2837 rx_pkts++; 2838 #if defined(INET6) || defined(INET) 2839 if (lro_enabled) { 2840 if (!lro_possible) { 2841 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2842 if (lro_possible && mf != NULL) { 2843 ifp->if_input(ifp, mf); 2844 DBG_COUNTER_INC(rx_if_input); 2845 mt = mf = NULL; 2846 } 2847 } 2848 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2849 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2850 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2851 continue; 2852 } 2853 } 2854 #endif 2855 if (lro_possible) { 2856 ifp->if_input(ifp, m); 2857 DBG_COUNTER_INC(rx_if_input); 2858 continue; 2859 } 2860 2861 if (mf == NULL) 2862 mf = m; 2863 if (mt != NULL) 2864 mt->m_nextpkt = m; 2865 mt = m; 2866 } 2867 if (mf != NULL) { 2868 ifp->if_input(ifp, mf); 2869 DBG_COUNTER_INC(rx_if_input); 2870 } 2871 2872 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2873 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2874 2875 /* 2876 * Flush any outstanding LRO work 2877 */ 2878 #if defined(INET6) || defined(INET) 2879 tcp_lro_flush_all(&rxq->ifr_lc); 2880 #endif 2881 if (avail) 2882 return true; 2883 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2884 err: 2885 STATE_LOCK(ctx); 2886 ctx->ifc_flags |= IFC_DO_RESET; 2887 iflib_admin_intr_deferred(ctx); 2888 STATE_UNLOCK(ctx); 2889 return (false); 2890 } 2891 2892 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2893 static inline qidx_t 2894 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2895 { 2896 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2897 qidx_t minthresh = txq->ift_size / 8; 2898 if (in_use > 4*minthresh) 2899 return (notify_count); 2900 if (in_use > 2*minthresh) 2901 return (notify_count >> 1); 2902 if (in_use > minthresh) 2903 return (notify_count >> 3); 2904 return (0); 2905 } 2906 2907 static inline qidx_t 2908 txq_max_rs_deferred(iflib_txq_t txq) 2909 { 2910 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2911 qidx_t minthresh = txq->ift_size / 8; 2912 if (txq->ift_in_use > 4*minthresh) 2913 return (notify_count); 2914 if (txq->ift_in_use > 2*minthresh) 2915 return (notify_count >> 1); 2916 if (txq->ift_in_use > minthresh) 2917 return (notify_count >> 2); 2918 return (2); 2919 } 2920 2921 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2922 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2923 2924 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2925 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2926 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2927 2928 /* forward compatibility for cxgb */ 2929 #define FIRST_QSET(ctx) 0 2930 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2931 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2932 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2933 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2934 2935 /* XXX we should be setting this to something other than zero */ 2936 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2937 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 2938 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 2939 2940 static inline bool 2941 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2942 { 2943 qidx_t dbval, max; 2944 bool rang; 2945 2946 rang = false; 2947 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2948 if (ring || txq->ift_db_pending >= max) { 2949 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2950 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 2951 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2952 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2953 txq->ift_db_pending = txq->ift_npending = 0; 2954 rang = true; 2955 } 2956 return (rang); 2957 } 2958 2959 #ifdef PKT_DEBUG 2960 static void 2961 print_pkt(if_pkt_info_t pi) 2962 { 2963 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2964 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2965 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2966 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2967 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2968 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2969 } 2970 #endif 2971 2972 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2973 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 2974 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2975 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 2976 2977 static int 2978 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2979 { 2980 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2981 struct ether_vlan_header *eh; 2982 struct mbuf *m; 2983 2984 m = *mp; 2985 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2986 M_WRITABLE(m) == 0) { 2987 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2988 return (ENOMEM); 2989 } else { 2990 m_freem(*mp); 2991 DBG_COUNTER_INC(tx_frees); 2992 *mp = m; 2993 } 2994 } 2995 2996 /* 2997 * Determine where frame payload starts. 2998 * Jump over vlan headers if already present, 2999 * helpful for QinQ too. 3000 */ 3001 if (__predict_false(m->m_len < sizeof(*eh))) { 3002 txq->ift_pullups++; 3003 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3004 return (ENOMEM); 3005 } 3006 eh = mtod(m, struct ether_vlan_header *); 3007 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3008 pi->ipi_etype = ntohs(eh->evl_proto); 3009 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3010 } else { 3011 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3012 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3013 } 3014 3015 switch (pi->ipi_etype) { 3016 #ifdef INET 3017 case ETHERTYPE_IP: 3018 { 3019 struct mbuf *n; 3020 struct ip *ip = NULL; 3021 struct tcphdr *th = NULL; 3022 int minthlen; 3023 3024 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3025 if (__predict_false(m->m_len < minthlen)) { 3026 /* 3027 * if this code bloat is causing too much of a hit 3028 * move it to a separate function and mark it noinline 3029 */ 3030 if (m->m_len == pi->ipi_ehdrlen) { 3031 n = m->m_next; 3032 MPASS(n); 3033 if (n->m_len >= sizeof(*ip)) { 3034 ip = (struct ip *)n->m_data; 3035 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3036 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3037 } else { 3038 txq->ift_pullups++; 3039 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3040 return (ENOMEM); 3041 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3042 } 3043 } else { 3044 txq->ift_pullups++; 3045 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3046 return (ENOMEM); 3047 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3048 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3049 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3050 } 3051 } else { 3052 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3053 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3054 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3055 } 3056 pi->ipi_ip_hlen = ip->ip_hl << 2; 3057 pi->ipi_ipproto = ip->ip_p; 3058 pi->ipi_flags |= IPI_TX_IPV4; 3059 3060 /* TCP checksum offload may require TCP header length */ 3061 if (IS_TX_OFFLOAD4(pi)) { 3062 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3063 if (__predict_false(th == NULL)) { 3064 txq->ift_pullups++; 3065 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3066 return (ENOMEM); 3067 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3068 } 3069 pi->ipi_tcp_hflags = th->th_flags; 3070 pi->ipi_tcp_hlen = th->th_off << 2; 3071 pi->ipi_tcp_seq = th->th_seq; 3072 } 3073 if (IS_TSO4(pi)) { 3074 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3075 return (ENXIO); 3076 /* 3077 * TSO always requires hardware checksum offload. 3078 */ 3079 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3080 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3081 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3082 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3083 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3084 ip->ip_sum = 0; 3085 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3086 } 3087 } 3088 } 3089 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3090 ip->ip_sum = 0; 3091 3092 break; 3093 } 3094 #endif 3095 #ifdef INET6 3096 case ETHERTYPE_IPV6: 3097 { 3098 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3099 struct tcphdr *th; 3100 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3101 3102 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3103 txq->ift_pullups++; 3104 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3105 return (ENOMEM); 3106 } 3107 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3108 3109 /* XXX-BZ this will go badly in case of ext hdrs. */ 3110 pi->ipi_ipproto = ip6->ip6_nxt; 3111 pi->ipi_flags |= IPI_TX_IPV6; 3112 3113 /* TCP checksum offload may require TCP header length */ 3114 if (IS_TX_OFFLOAD6(pi)) { 3115 if (pi->ipi_ipproto == IPPROTO_TCP) { 3116 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3117 txq->ift_pullups++; 3118 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3119 return (ENOMEM); 3120 } 3121 pi->ipi_tcp_hflags = th->th_flags; 3122 pi->ipi_tcp_hlen = th->th_off << 2; 3123 pi->ipi_tcp_seq = th->th_seq; 3124 } 3125 if (IS_TSO6(pi)) { 3126 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3127 return (ENXIO); 3128 /* 3129 * TSO always requires hardware checksum offload. 3130 */ 3131 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3132 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3133 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3134 } 3135 } 3136 break; 3137 } 3138 #endif 3139 default: 3140 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3141 pi->ipi_ip_hlen = 0; 3142 break; 3143 } 3144 *mp = m; 3145 3146 return (0); 3147 } 3148 3149 /* 3150 * If dodgy hardware rejects the scatter gather chain we've handed it 3151 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3152 * m_defrag'd mbufs 3153 */ 3154 static __noinline struct mbuf * 3155 iflib_remove_mbuf(iflib_txq_t txq) 3156 { 3157 int ntxd, pidx; 3158 struct mbuf *m, **ifsd_m; 3159 3160 ifsd_m = txq->ift_sds.ifsd_m; 3161 ntxd = txq->ift_size; 3162 pidx = txq->ift_pidx & (ntxd - 1); 3163 ifsd_m = txq->ift_sds.ifsd_m; 3164 m = ifsd_m[pidx]; 3165 ifsd_m[pidx] = NULL; 3166 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3167 if (txq->ift_sds.ifsd_tso_map != NULL) 3168 bus_dmamap_unload(txq->ift_tso_buf_tag, 3169 txq->ift_sds.ifsd_tso_map[pidx]); 3170 #if MEMORY_LOGGING 3171 txq->ift_dequeued++; 3172 #endif 3173 return (m); 3174 } 3175 3176 static inline caddr_t 3177 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3178 { 3179 qidx_t size; 3180 int ntxd; 3181 caddr_t start, end, cur, next; 3182 3183 ntxd = txq->ift_size; 3184 size = txq->ift_txd_size[qid]; 3185 start = txq->ift_ifdi[qid].idi_vaddr; 3186 3187 if (__predict_false(size == 0)) 3188 return (start); 3189 cur = start + size*cidx; 3190 end = start + size*ntxd; 3191 next = CACHE_PTR_NEXT(cur); 3192 return (next < end ? next : start); 3193 } 3194 3195 /* 3196 * Pad an mbuf to ensure a minimum ethernet frame size. 3197 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3198 */ 3199 static __noinline int 3200 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3201 { 3202 /* 3203 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3204 * and ARP message is the smallest common payload I can think of 3205 */ 3206 static char pad[18]; /* just zeros */ 3207 int n; 3208 struct mbuf *new_head; 3209 3210 if (!M_WRITABLE(*m_head)) { 3211 new_head = m_dup(*m_head, M_NOWAIT); 3212 if (new_head == NULL) { 3213 m_freem(*m_head); 3214 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3215 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3216 DBG_COUNTER_INC(tx_frees); 3217 return ENOMEM; 3218 } 3219 m_freem(*m_head); 3220 *m_head = new_head; 3221 } 3222 3223 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3224 n > 0; n -= sizeof(pad)) 3225 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3226 break; 3227 3228 if (n > 0) { 3229 m_freem(*m_head); 3230 device_printf(dev, "cannot pad short frame\n"); 3231 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3232 DBG_COUNTER_INC(tx_frees); 3233 return (ENOBUFS); 3234 } 3235 3236 return 0; 3237 } 3238 3239 static int 3240 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3241 { 3242 if_ctx_t ctx; 3243 if_shared_ctx_t sctx; 3244 if_softc_ctx_t scctx; 3245 bus_dma_tag_t buf_tag; 3246 bus_dma_segment_t *segs; 3247 struct mbuf *m_head, **ifsd_m; 3248 void *next_txd; 3249 bus_dmamap_t map; 3250 struct if_pkt_info pi; 3251 int remap = 0; 3252 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3253 3254 ctx = txq->ift_ctx; 3255 sctx = ctx->ifc_sctx; 3256 scctx = &ctx->ifc_softc_ctx; 3257 segs = txq->ift_segs; 3258 ntxd = txq->ift_size; 3259 m_head = *m_headp; 3260 map = NULL; 3261 3262 /* 3263 * If we're doing TSO the next descriptor to clean may be quite far ahead 3264 */ 3265 cidx = txq->ift_cidx; 3266 pidx = txq->ift_pidx; 3267 if (ctx->ifc_flags & IFC_PREFETCH) { 3268 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3269 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3270 next_txd = calc_next_txd(txq, cidx, 0); 3271 prefetch(next_txd); 3272 } 3273 3274 /* prefetch the next cache line of mbuf pointers and flags */ 3275 prefetch(&txq->ift_sds.ifsd_m[next]); 3276 prefetch(&txq->ift_sds.ifsd_map[next]); 3277 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3278 } 3279 map = txq->ift_sds.ifsd_map[pidx]; 3280 ifsd_m = txq->ift_sds.ifsd_m; 3281 3282 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3283 buf_tag = txq->ift_tso_buf_tag; 3284 max_segs = scctx->isc_tx_tso_segments_max; 3285 map = txq->ift_sds.ifsd_tso_map[pidx]; 3286 MPASS(buf_tag != NULL); 3287 MPASS(max_segs > 0); 3288 } else { 3289 buf_tag = txq->ift_buf_tag; 3290 max_segs = scctx->isc_tx_nsegments; 3291 map = txq->ift_sds.ifsd_map[pidx]; 3292 } 3293 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3294 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3295 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3296 if (err) { 3297 DBG_COUNTER_INC(encap_txd_encap_fail); 3298 return err; 3299 } 3300 } 3301 m_head = *m_headp; 3302 3303 pkt_info_zero(&pi); 3304 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3305 pi.ipi_pidx = pidx; 3306 pi.ipi_qsidx = txq->ift_id; 3307 pi.ipi_len = m_head->m_pkthdr.len; 3308 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3309 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3310 3311 /* deliberate bitwise OR to make one condition */ 3312 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3313 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3314 DBG_COUNTER_INC(encap_txd_encap_fail); 3315 return (err); 3316 } 3317 m_head = *m_headp; 3318 } 3319 3320 retry: 3321 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3322 BUS_DMA_NOWAIT); 3323 defrag: 3324 if (__predict_false(err)) { 3325 switch (err) { 3326 case EFBIG: 3327 /* try collapse once and defrag once */ 3328 if (remap == 0) { 3329 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3330 /* try defrag if collapsing fails */ 3331 if (m_head == NULL) 3332 remap++; 3333 } 3334 if (remap == 1) { 3335 txq->ift_mbuf_defrag++; 3336 m_head = m_defrag(*m_headp, M_NOWAIT); 3337 } 3338 /* 3339 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3340 * failed to map an mbuf that was run through m_defrag 3341 */ 3342 MPASS(remap <= 1); 3343 if (__predict_false(m_head == NULL || remap > 1)) 3344 goto defrag_failed; 3345 remap++; 3346 *m_headp = m_head; 3347 goto retry; 3348 break; 3349 case ENOMEM: 3350 txq->ift_no_tx_dma_setup++; 3351 break; 3352 default: 3353 txq->ift_no_tx_dma_setup++; 3354 m_freem(*m_headp); 3355 DBG_COUNTER_INC(tx_frees); 3356 *m_headp = NULL; 3357 break; 3358 } 3359 txq->ift_map_failed++; 3360 DBG_COUNTER_INC(encap_load_mbuf_fail); 3361 DBG_COUNTER_INC(encap_txd_encap_fail); 3362 return (err); 3363 } 3364 ifsd_m[pidx] = m_head; 3365 /* 3366 * XXX assumes a 1 to 1 relationship between segments and 3367 * descriptors - this does not hold true on all drivers, e.g. 3368 * cxgb 3369 */ 3370 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3371 txq->ift_no_desc_avail++; 3372 bus_dmamap_unload(buf_tag, map); 3373 DBG_COUNTER_INC(encap_txq_avail_fail); 3374 DBG_COUNTER_INC(encap_txd_encap_fail); 3375 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3376 GROUPTASK_ENQUEUE(&txq->ift_task); 3377 return (ENOBUFS); 3378 } 3379 /* 3380 * On Intel cards we can greatly reduce the number of TX interrupts 3381 * we see by only setting report status on every Nth descriptor. 3382 * However, this also means that the driver will need to keep track 3383 * of the descriptors that RS was set on to check them for the DD bit. 3384 */ 3385 txq->ift_rs_pending += nsegs + 1; 3386 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3387 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3388 pi.ipi_flags |= IPI_TX_INTR; 3389 txq->ift_rs_pending = 0; 3390 } 3391 3392 pi.ipi_segs = segs; 3393 pi.ipi_nsegs = nsegs; 3394 3395 MPASS(pidx >= 0 && pidx < txq->ift_size); 3396 #ifdef PKT_DEBUG 3397 print_pkt(&pi); 3398 #endif 3399 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3400 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3401 DBG_COUNTER_INC(tx_encap); 3402 MPASS(pi.ipi_new_pidx < txq->ift_size); 3403 3404 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3405 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3406 ndesc += txq->ift_size; 3407 txq->ift_gen = 1; 3408 } 3409 /* 3410 * drivers can need as many as 3411 * two sentinels 3412 */ 3413 MPASS(ndesc <= pi.ipi_nsegs + 2); 3414 MPASS(pi.ipi_new_pidx != pidx); 3415 MPASS(ndesc > 0); 3416 txq->ift_in_use += ndesc; 3417 3418 /* 3419 * We update the last software descriptor again here because there may 3420 * be a sentinel and/or there may be more mbufs than segments 3421 */ 3422 txq->ift_pidx = pi.ipi_new_pidx; 3423 txq->ift_npending += pi.ipi_ndescs; 3424 } else { 3425 *m_headp = m_head = iflib_remove_mbuf(txq); 3426 if (err == EFBIG) { 3427 txq->ift_txd_encap_efbig++; 3428 if (remap < 2) { 3429 remap = 1; 3430 goto defrag; 3431 } 3432 } 3433 goto defrag_failed; 3434 } 3435 /* 3436 * err can't possibly be non-zero here, so we don't neet to test it 3437 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3438 */ 3439 return (err); 3440 3441 defrag_failed: 3442 txq->ift_mbuf_defrag_failed++; 3443 txq->ift_map_failed++; 3444 m_freem(*m_headp); 3445 DBG_COUNTER_INC(tx_frees); 3446 *m_headp = NULL; 3447 DBG_COUNTER_INC(encap_txd_encap_fail); 3448 return (ENOMEM); 3449 } 3450 3451 static void 3452 iflib_tx_desc_free(iflib_txq_t txq, int n) 3453 { 3454 uint32_t qsize, cidx, mask, gen; 3455 struct mbuf *m, **ifsd_m; 3456 bool do_prefetch; 3457 3458 cidx = txq->ift_cidx; 3459 gen = txq->ift_gen; 3460 qsize = txq->ift_size; 3461 mask = qsize-1; 3462 ifsd_m = txq->ift_sds.ifsd_m; 3463 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3464 3465 while (n-- > 0) { 3466 if (do_prefetch) { 3467 prefetch(ifsd_m[(cidx + 3) & mask]); 3468 prefetch(ifsd_m[(cidx + 4) & mask]); 3469 } 3470 if ((m = ifsd_m[cidx]) != NULL) { 3471 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3472 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3473 bus_dmamap_sync(txq->ift_tso_buf_tag, 3474 txq->ift_sds.ifsd_tso_map[cidx], 3475 BUS_DMASYNC_POSTWRITE); 3476 bus_dmamap_unload(txq->ift_tso_buf_tag, 3477 txq->ift_sds.ifsd_tso_map[cidx]); 3478 } else { 3479 bus_dmamap_sync(txq->ift_buf_tag, 3480 txq->ift_sds.ifsd_map[cidx], 3481 BUS_DMASYNC_POSTWRITE); 3482 bus_dmamap_unload(txq->ift_buf_tag, 3483 txq->ift_sds.ifsd_map[cidx]); 3484 } 3485 /* XXX we don't support any drivers that batch packets yet */ 3486 MPASS(m->m_nextpkt == NULL); 3487 m_freem(m); 3488 ifsd_m[cidx] = NULL; 3489 #if MEMORY_LOGGING 3490 txq->ift_dequeued++; 3491 #endif 3492 DBG_COUNTER_INC(tx_frees); 3493 } 3494 if (__predict_false(++cidx == qsize)) { 3495 cidx = 0; 3496 gen = 0; 3497 } 3498 } 3499 txq->ift_cidx = cidx; 3500 txq->ift_gen = gen; 3501 } 3502 3503 static __inline int 3504 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3505 { 3506 int reclaim; 3507 if_ctx_t ctx = txq->ift_ctx; 3508 3509 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3510 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3511 3512 /* 3513 * Need a rate-limiting check so that this isn't called every time 3514 */ 3515 iflib_tx_credits_update(ctx, txq); 3516 reclaim = DESC_RECLAIMABLE(txq); 3517 3518 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3519 #ifdef INVARIANTS 3520 if (iflib_verbose_debug) { 3521 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3522 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3523 reclaim, thresh); 3524 3525 } 3526 #endif 3527 return (0); 3528 } 3529 iflib_tx_desc_free(txq, reclaim); 3530 txq->ift_cleaned += reclaim; 3531 txq->ift_in_use -= reclaim; 3532 3533 return (reclaim); 3534 } 3535 3536 static struct mbuf ** 3537 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3538 { 3539 int next, size; 3540 struct mbuf **items; 3541 3542 size = r->size; 3543 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3544 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3545 3546 prefetch(items[(cidx + offset) & (size-1)]); 3547 if (remaining > 1) { 3548 prefetch2cachelines(&items[next]); 3549 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3550 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3551 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3552 } 3553 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3554 } 3555 3556 static void 3557 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3558 { 3559 3560 ifmp_ring_check_drainage(txq->ift_br, budget); 3561 } 3562 3563 static uint32_t 3564 iflib_txq_can_drain(struct ifmp_ring *r) 3565 { 3566 iflib_txq_t txq = r->cookie; 3567 if_ctx_t ctx = txq->ift_ctx; 3568 3569 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3570 return (1); 3571 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3572 BUS_DMASYNC_POSTREAD); 3573 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3574 false)); 3575 } 3576 3577 static uint32_t 3578 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3579 { 3580 iflib_txq_t txq = r->cookie; 3581 if_ctx_t ctx = txq->ift_ctx; 3582 if_t ifp = ctx->ifc_ifp; 3583 struct mbuf *m, **mp; 3584 int avail, bytes_sent, consumed, count, err, i, in_use_prev; 3585 int mcast_sent, pkt_sent, reclaimed, txq_avail; 3586 bool do_prefetch, rang, ring; 3587 3588 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3589 !LINK_ACTIVE(ctx))) { 3590 DBG_COUNTER_INC(txq_drain_notready); 3591 return (0); 3592 } 3593 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3594 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3595 avail = IDXDIFF(pidx, cidx, r->size); 3596 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3597 DBG_COUNTER_INC(txq_drain_flushing); 3598 for (i = 0; i < avail; i++) { 3599 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3600 m_free(r->items[(cidx + i) & (r->size-1)]); 3601 r->items[(cidx + i) & (r->size-1)] = NULL; 3602 } 3603 return (avail); 3604 } 3605 3606 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3607 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3608 CALLOUT_LOCK(txq); 3609 callout_stop(&txq->ift_timer); 3610 CALLOUT_UNLOCK(txq); 3611 DBG_COUNTER_INC(txq_drain_oactive); 3612 return (0); 3613 } 3614 if (reclaimed) 3615 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3616 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3617 count = MIN(avail, TX_BATCH_SIZE); 3618 #ifdef INVARIANTS 3619 if (iflib_verbose_debug) 3620 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3621 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3622 #endif 3623 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3624 txq_avail = TXQ_AVAIL(txq); 3625 err = 0; 3626 for (i = 0; i < count && txq_avail > MAX_TX_DESC(ctx) + 2; i++) { 3627 int rem = do_prefetch ? count - i : 0; 3628 3629 mp = _ring_peek_one(r, cidx, i, rem); 3630 MPASS(mp != NULL && *mp != NULL); 3631 if (__predict_false(*mp == (struct mbuf *)txq)) { 3632 consumed++; 3633 continue; 3634 } 3635 in_use_prev = txq->ift_in_use; 3636 err = iflib_encap(txq, mp); 3637 if (__predict_false(err)) { 3638 /* no room - bail out */ 3639 if (err == ENOBUFS) 3640 break; 3641 consumed++; 3642 /* we can't send this packet - skip it */ 3643 continue; 3644 } 3645 consumed++; 3646 pkt_sent++; 3647 m = *mp; 3648 DBG_COUNTER_INC(tx_sent); 3649 bytes_sent += m->m_pkthdr.len; 3650 mcast_sent += !!(m->m_flags & M_MCAST); 3651 txq_avail = TXQ_AVAIL(txq); 3652 3653 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3654 ETHER_BPF_MTAP(ifp, m); 3655 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3656 break; 3657 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3658 } 3659 3660 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3661 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3662 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3663 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3664 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3665 if (mcast_sent) 3666 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3667 #ifdef INVARIANTS 3668 if (iflib_verbose_debug) 3669 printf("consumed=%d\n", consumed); 3670 #endif 3671 return (consumed); 3672 } 3673 3674 static uint32_t 3675 iflib_txq_drain_always(struct ifmp_ring *r) 3676 { 3677 return (1); 3678 } 3679 3680 static uint32_t 3681 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3682 { 3683 int i, avail; 3684 struct mbuf **mp; 3685 iflib_txq_t txq; 3686 3687 txq = r->cookie; 3688 3689 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3690 CALLOUT_LOCK(txq); 3691 callout_stop(&txq->ift_timer); 3692 CALLOUT_UNLOCK(txq); 3693 3694 avail = IDXDIFF(pidx, cidx, r->size); 3695 for (i = 0; i < avail; i++) { 3696 mp = _ring_peek_one(r, cidx, i, avail - i); 3697 if (__predict_false(*mp == (struct mbuf *)txq)) 3698 continue; 3699 m_freem(*mp); 3700 DBG_COUNTER_INC(tx_frees); 3701 } 3702 MPASS(ifmp_ring_is_stalled(r) == 0); 3703 return (avail); 3704 } 3705 3706 static void 3707 iflib_ifmp_purge(iflib_txq_t txq) 3708 { 3709 struct ifmp_ring *r; 3710 3711 r = txq->ift_br; 3712 r->drain = iflib_txq_drain_free; 3713 r->can_drain = iflib_txq_drain_always; 3714 3715 ifmp_ring_check_drainage(r, r->size); 3716 3717 r->drain = iflib_txq_drain; 3718 r->can_drain = iflib_txq_can_drain; 3719 } 3720 3721 static void 3722 _task_fn_tx(void *context) 3723 { 3724 iflib_txq_t txq = context; 3725 if_ctx_t ctx = txq->ift_ctx; 3726 #if defined(ALTQ) || defined(DEV_NETMAP) 3727 if_t ifp = ctx->ifc_ifp; 3728 #endif 3729 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3730 3731 #ifdef IFLIB_DIAGNOSTICS 3732 txq->ift_cpu_exec_count[curcpu]++; 3733 #endif 3734 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3735 return; 3736 #ifdef DEV_NETMAP 3737 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3738 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3739 BUS_DMASYNC_POSTREAD); 3740 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3741 netmap_tx_irq(ifp, txq->ift_id); 3742 if (ctx->ifc_flags & IFC_LEGACY) 3743 IFDI_INTR_ENABLE(ctx); 3744 else 3745 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3746 return; 3747 } 3748 #endif 3749 #ifdef ALTQ 3750 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3751 iflib_altq_if_start(ifp); 3752 #endif 3753 if (txq->ift_db_pending) 3754 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3755 else if (!abdicate) 3756 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3757 /* 3758 * When abdicating, we always need to check drainage, not just when we don't enqueue 3759 */ 3760 if (abdicate) 3761 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3762 if (ctx->ifc_flags & IFC_LEGACY) 3763 IFDI_INTR_ENABLE(ctx); 3764 else 3765 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3766 } 3767 3768 static void 3769 _task_fn_rx(void *context) 3770 { 3771 iflib_rxq_t rxq = context; 3772 if_ctx_t ctx = rxq->ifr_ctx; 3773 bool more; 3774 uint16_t budget; 3775 3776 #ifdef IFLIB_DIAGNOSTICS 3777 rxq->ifr_cpu_exec_count[curcpu]++; 3778 #endif 3779 DBG_COUNTER_INC(task_fn_rxs); 3780 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3781 return; 3782 more = true; 3783 #ifdef DEV_NETMAP 3784 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3785 u_int work = 0; 3786 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3787 more = false; 3788 } 3789 } 3790 #endif 3791 budget = ctx->ifc_sysctl_rx_budget; 3792 if (budget == 0) 3793 budget = 16; /* XXX */ 3794 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3795 if (ctx->ifc_flags & IFC_LEGACY) 3796 IFDI_INTR_ENABLE(ctx); 3797 else 3798 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3799 DBG_COUNTER_INC(rx_intr_enables); 3800 } 3801 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3802 return; 3803 if (more) 3804 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3805 } 3806 3807 static void 3808 _task_fn_admin(void *context) 3809 { 3810 if_ctx_t ctx = context; 3811 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3812 iflib_txq_t txq; 3813 int i; 3814 bool oactive, running, do_reset, do_watchdog, in_detach; 3815 uint32_t reset_on = hz / 2; 3816 3817 STATE_LOCK(ctx); 3818 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3819 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3820 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3821 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3822 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3823 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3824 STATE_UNLOCK(ctx); 3825 3826 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3827 return; 3828 if (in_detach) 3829 return; 3830 3831 CTX_LOCK(ctx); 3832 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3833 CALLOUT_LOCK(txq); 3834 callout_stop(&txq->ift_timer); 3835 CALLOUT_UNLOCK(txq); 3836 } 3837 if (do_watchdog) { 3838 ctx->ifc_watchdog_events++; 3839 IFDI_WATCHDOG_RESET(ctx); 3840 } 3841 IFDI_UPDATE_ADMIN_STATUS(ctx); 3842 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3843 #ifdef DEV_NETMAP 3844 reset_on = hz / 2; 3845 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 3846 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 3847 #endif 3848 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 3849 } 3850 IFDI_LINK_INTR_ENABLE(ctx); 3851 if (do_reset) 3852 iflib_if_init_locked(ctx); 3853 CTX_UNLOCK(ctx); 3854 3855 if (LINK_ACTIVE(ctx) == 0) 3856 return; 3857 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3858 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3859 } 3860 3861 3862 static void 3863 _task_fn_iov(void *context) 3864 { 3865 if_ctx_t ctx = context; 3866 3867 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3868 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3869 return; 3870 3871 CTX_LOCK(ctx); 3872 IFDI_VFLR_HANDLE(ctx); 3873 CTX_UNLOCK(ctx); 3874 } 3875 3876 static int 3877 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3878 { 3879 int err; 3880 if_int_delay_info_t info; 3881 if_ctx_t ctx; 3882 3883 info = (if_int_delay_info_t)arg1; 3884 ctx = info->iidi_ctx; 3885 info->iidi_req = req; 3886 info->iidi_oidp = oidp; 3887 CTX_LOCK(ctx); 3888 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3889 CTX_UNLOCK(ctx); 3890 return (err); 3891 } 3892 3893 /********************************************************************* 3894 * 3895 * IFNET FUNCTIONS 3896 * 3897 **********************************************************************/ 3898 3899 static void 3900 iflib_if_init_locked(if_ctx_t ctx) 3901 { 3902 iflib_stop(ctx); 3903 iflib_init_locked(ctx); 3904 } 3905 3906 3907 static void 3908 iflib_if_init(void *arg) 3909 { 3910 if_ctx_t ctx = arg; 3911 3912 CTX_LOCK(ctx); 3913 iflib_if_init_locked(ctx); 3914 CTX_UNLOCK(ctx); 3915 } 3916 3917 static int 3918 iflib_if_transmit(if_t ifp, struct mbuf *m) 3919 { 3920 if_ctx_t ctx = if_getsoftc(ifp); 3921 3922 iflib_txq_t txq; 3923 int err, qidx; 3924 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3925 3926 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3927 DBG_COUNTER_INC(tx_frees); 3928 m_freem(m); 3929 return (ENETDOWN); 3930 } 3931 3932 MPASS(m->m_nextpkt == NULL); 3933 /* ALTQ-enabled interfaces always use queue 0. */ 3934 qidx = 0; 3935 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 3936 qidx = QIDX(ctx, m); 3937 /* 3938 * XXX calculate buf_ring based on flowid (divvy up bits?) 3939 */ 3940 txq = &ctx->ifc_txqs[qidx]; 3941 3942 #ifdef DRIVER_BACKPRESSURE 3943 if (txq->ift_closed) { 3944 while (m != NULL) { 3945 next = m->m_nextpkt; 3946 m->m_nextpkt = NULL; 3947 m_freem(m); 3948 DBG_COUNTER_INC(tx_frees); 3949 m = next; 3950 } 3951 return (ENOBUFS); 3952 } 3953 #endif 3954 #ifdef notyet 3955 qidx = count = 0; 3956 mp = marr; 3957 next = m; 3958 do { 3959 count++; 3960 next = next->m_nextpkt; 3961 } while (next != NULL); 3962 3963 if (count > nitems(marr)) 3964 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3965 /* XXX check nextpkt */ 3966 m_freem(m); 3967 /* XXX simplify for now */ 3968 DBG_COUNTER_INC(tx_frees); 3969 return (ENOBUFS); 3970 } 3971 for (next = m, i = 0; next != NULL; i++) { 3972 mp[i] = next; 3973 next = next->m_nextpkt; 3974 mp[i]->m_nextpkt = NULL; 3975 } 3976 #endif 3977 DBG_COUNTER_INC(tx_seen); 3978 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 3979 3980 if (abdicate) 3981 GROUPTASK_ENQUEUE(&txq->ift_task); 3982 if (err) { 3983 if (!abdicate) 3984 GROUPTASK_ENQUEUE(&txq->ift_task); 3985 /* support forthcoming later */ 3986 #ifdef DRIVER_BACKPRESSURE 3987 txq->ift_closed = TRUE; 3988 #endif 3989 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3990 m_freem(m); 3991 DBG_COUNTER_INC(tx_frees); 3992 } 3993 3994 return (err); 3995 } 3996 3997 #ifdef ALTQ 3998 /* 3999 * The overall approach to integrating iflib with ALTQ is to continue to use 4000 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4001 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4002 * is redundant/unnecessary, but doing so minimizes the amount of 4003 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4004 * redundantly queueing to an intermediate mp_ring is swamped by the 4005 * performance limitations inherent in using ALTQ. 4006 * 4007 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4008 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4009 * given interface. If ALTQ is enabled for an interface, then all 4010 * transmitted packets for that interface will be submitted to the ALTQ 4011 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4012 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4013 * update stats that the iflib machinery handles, and which is sensitve to 4014 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4015 * will be installed as the start routine for use by ALTQ facilities that 4016 * need to trigger queue drains on a scheduled basis. 4017 * 4018 */ 4019 static void 4020 iflib_altq_if_start(if_t ifp) 4021 { 4022 struct ifaltq *ifq = &ifp->if_snd; 4023 struct mbuf *m; 4024 4025 IFQ_LOCK(ifq); 4026 IFQ_DEQUEUE_NOLOCK(ifq, m); 4027 while (m != NULL) { 4028 iflib_if_transmit(ifp, m); 4029 IFQ_DEQUEUE_NOLOCK(ifq, m); 4030 } 4031 IFQ_UNLOCK(ifq); 4032 } 4033 4034 static int 4035 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4036 { 4037 int err; 4038 4039 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4040 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4041 if (err == 0) 4042 iflib_altq_if_start(ifp); 4043 } else 4044 err = iflib_if_transmit(ifp, m); 4045 4046 return (err); 4047 } 4048 #endif /* ALTQ */ 4049 4050 static void 4051 iflib_if_qflush(if_t ifp) 4052 { 4053 if_ctx_t ctx = if_getsoftc(ifp); 4054 iflib_txq_t txq = ctx->ifc_txqs; 4055 int i; 4056 4057 STATE_LOCK(ctx); 4058 ctx->ifc_flags |= IFC_QFLUSH; 4059 STATE_UNLOCK(ctx); 4060 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4061 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4062 iflib_txq_check_drain(txq, 0); 4063 STATE_LOCK(ctx); 4064 ctx->ifc_flags &= ~IFC_QFLUSH; 4065 STATE_UNLOCK(ctx); 4066 4067 /* 4068 * When ALTQ is enabled, this will also take care of purging the 4069 * ALTQ queue(s). 4070 */ 4071 if_qflush(ifp); 4072 } 4073 4074 4075 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4076 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4077 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4078 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM) 4079 4080 static int 4081 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4082 { 4083 if_ctx_t ctx = if_getsoftc(ifp); 4084 struct ifreq *ifr = (struct ifreq *)data; 4085 #if defined(INET) || defined(INET6) 4086 struct ifaddr *ifa = (struct ifaddr *)data; 4087 #endif 4088 bool avoid_reset = false; 4089 int err = 0, reinit = 0, bits; 4090 4091 switch (command) { 4092 case SIOCSIFADDR: 4093 #ifdef INET 4094 if (ifa->ifa_addr->sa_family == AF_INET) 4095 avoid_reset = true; 4096 #endif 4097 #ifdef INET6 4098 if (ifa->ifa_addr->sa_family == AF_INET6) 4099 avoid_reset = true; 4100 #endif 4101 /* 4102 ** Calling init results in link renegotiation, 4103 ** so we avoid doing it when possible. 4104 */ 4105 if (avoid_reset) { 4106 if_setflagbits(ifp, IFF_UP,0); 4107 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4108 reinit = 1; 4109 #ifdef INET 4110 if (!(if_getflags(ifp) & IFF_NOARP)) 4111 arp_ifinit(ifp, ifa); 4112 #endif 4113 } else 4114 err = ether_ioctl(ifp, command, data); 4115 break; 4116 case SIOCSIFMTU: 4117 CTX_LOCK(ctx); 4118 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4119 CTX_UNLOCK(ctx); 4120 break; 4121 } 4122 bits = if_getdrvflags(ifp); 4123 /* stop the driver and free any clusters before proceeding */ 4124 iflib_stop(ctx); 4125 4126 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4127 STATE_LOCK(ctx); 4128 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4129 ctx->ifc_flags |= IFC_MULTISEG; 4130 else 4131 ctx->ifc_flags &= ~IFC_MULTISEG; 4132 STATE_UNLOCK(ctx); 4133 err = if_setmtu(ifp, ifr->ifr_mtu); 4134 } 4135 iflib_init_locked(ctx); 4136 STATE_LOCK(ctx); 4137 if_setdrvflags(ifp, bits); 4138 STATE_UNLOCK(ctx); 4139 CTX_UNLOCK(ctx); 4140 break; 4141 case SIOCSIFFLAGS: 4142 CTX_LOCK(ctx); 4143 if (if_getflags(ifp) & IFF_UP) { 4144 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4145 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4146 (IFF_PROMISC | IFF_ALLMULTI)) { 4147 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4148 } 4149 } else 4150 reinit = 1; 4151 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4152 iflib_stop(ctx); 4153 } 4154 ctx->ifc_if_flags = if_getflags(ifp); 4155 CTX_UNLOCK(ctx); 4156 break; 4157 case SIOCADDMULTI: 4158 case SIOCDELMULTI: 4159 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4160 CTX_LOCK(ctx); 4161 IFDI_INTR_DISABLE(ctx); 4162 IFDI_MULTI_SET(ctx); 4163 IFDI_INTR_ENABLE(ctx); 4164 CTX_UNLOCK(ctx); 4165 } 4166 break; 4167 case SIOCSIFMEDIA: 4168 CTX_LOCK(ctx); 4169 IFDI_MEDIA_SET(ctx); 4170 CTX_UNLOCK(ctx); 4171 /* FALLTHROUGH */ 4172 case SIOCGIFMEDIA: 4173 case SIOCGIFXMEDIA: 4174 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4175 break; 4176 case SIOCGI2C: 4177 { 4178 struct ifi2creq i2c; 4179 4180 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4181 if (err != 0) 4182 break; 4183 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4184 err = EINVAL; 4185 break; 4186 } 4187 if (i2c.len > sizeof(i2c.data)) { 4188 err = EINVAL; 4189 break; 4190 } 4191 4192 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4193 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4194 sizeof(i2c)); 4195 break; 4196 } 4197 case SIOCSIFCAP: 4198 { 4199 int mask, setmask, oldmask; 4200 4201 oldmask = if_getcapenable(ifp); 4202 mask = ifr->ifr_reqcap ^ oldmask; 4203 mask &= ctx->ifc_softc_ctx.isc_capabilities; 4204 setmask = 0; 4205 #ifdef TCP_OFFLOAD 4206 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4207 #endif 4208 setmask |= (mask & IFCAP_FLAGS); 4209 setmask |= (mask & IFCAP_WOL); 4210 4211 /* 4212 * If any RX csum has changed, change all the ones that 4213 * are supported by the driver. 4214 */ 4215 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4216 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4217 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4218 } 4219 4220 /* 4221 * want to ensure that traffic has stopped before we change any of the flags 4222 */ 4223 if (setmask) { 4224 CTX_LOCK(ctx); 4225 bits = if_getdrvflags(ifp); 4226 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4227 iflib_stop(ctx); 4228 STATE_LOCK(ctx); 4229 if_togglecapenable(ifp, setmask); 4230 STATE_UNLOCK(ctx); 4231 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4232 iflib_init_locked(ctx); 4233 STATE_LOCK(ctx); 4234 if_setdrvflags(ifp, bits); 4235 STATE_UNLOCK(ctx); 4236 CTX_UNLOCK(ctx); 4237 } 4238 if_vlancap(ifp); 4239 break; 4240 } 4241 case SIOCGPRIVATE_0: 4242 case SIOCSDRVSPEC: 4243 case SIOCGDRVSPEC: 4244 CTX_LOCK(ctx); 4245 err = IFDI_PRIV_IOCTL(ctx, command, data); 4246 CTX_UNLOCK(ctx); 4247 break; 4248 default: 4249 err = ether_ioctl(ifp, command, data); 4250 break; 4251 } 4252 if (reinit) 4253 iflib_if_init(ctx); 4254 return (err); 4255 } 4256 4257 static uint64_t 4258 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4259 { 4260 if_ctx_t ctx = if_getsoftc(ifp); 4261 4262 return (IFDI_GET_COUNTER(ctx, cnt)); 4263 } 4264 4265 /********************************************************************* 4266 * 4267 * OTHER FUNCTIONS EXPORTED TO THE STACK 4268 * 4269 **********************************************************************/ 4270 4271 static void 4272 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4273 { 4274 if_ctx_t ctx = if_getsoftc(ifp); 4275 4276 if ((void *)ctx != arg) 4277 return; 4278 4279 if ((vtag == 0) || (vtag > 4095)) 4280 return; 4281 4282 CTX_LOCK(ctx); 4283 IFDI_VLAN_REGISTER(ctx, vtag); 4284 /* Re-init to load the changes */ 4285 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4286 iflib_if_init_locked(ctx); 4287 CTX_UNLOCK(ctx); 4288 } 4289 4290 static void 4291 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4292 { 4293 if_ctx_t ctx = if_getsoftc(ifp); 4294 4295 if ((void *)ctx != arg) 4296 return; 4297 4298 if ((vtag == 0) || (vtag > 4095)) 4299 return; 4300 4301 CTX_LOCK(ctx); 4302 IFDI_VLAN_UNREGISTER(ctx, vtag); 4303 /* Re-init to load the changes */ 4304 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4305 iflib_if_init_locked(ctx); 4306 CTX_UNLOCK(ctx); 4307 } 4308 4309 static void 4310 iflib_led_func(void *arg, int onoff) 4311 { 4312 if_ctx_t ctx = arg; 4313 4314 CTX_LOCK(ctx); 4315 IFDI_LED_FUNC(ctx, onoff); 4316 CTX_UNLOCK(ctx); 4317 } 4318 4319 /********************************************************************* 4320 * 4321 * BUS FUNCTION DEFINITIONS 4322 * 4323 **********************************************************************/ 4324 4325 int 4326 iflib_device_probe(device_t dev) 4327 { 4328 const pci_vendor_info_t *ent; 4329 if_shared_ctx_t sctx; 4330 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4331 uint16_t pci_vendor_id; 4332 4333 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4334 return (ENOTSUP); 4335 4336 pci_vendor_id = pci_get_vendor(dev); 4337 pci_device_id = pci_get_device(dev); 4338 pci_subvendor_id = pci_get_subvendor(dev); 4339 pci_subdevice_id = pci_get_subdevice(dev); 4340 pci_rev_id = pci_get_revid(dev); 4341 if (sctx->isc_parse_devinfo != NULL) 4342 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4343 4344 ent = sctx->isc_vendor_info; 4345 while (ent->pvi_vendor_id != 0) { 4346 if (pci_vendor_id != ent->pvi_vendor_id) { 4347 ent++; 4348 continue; 4349 } 4350 if ((pci_device_id == ent->pvi_device_id) && 4351 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4352 (ent->pvi_subvendor_id == 0)) && 4353 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4354 (ent->pvi_subdevice_id == 0)) && 4355 ((pci_rev_id == ent->pvi_rev_id) || 4356 (ent->pvi_rev_id == 0))) { 4357 4358 device_set_desc_copy(dev, ent->pvi_name); 4359 /* this needs to be changed to zero if the bus probing code 4360 * ever stops re-probing on best match because the sctx 4361 * may have its values over written by register calls 4362 * in subsequent probes 4363 */ 4364 return (BUS_PROBE_DEFAULT); 4365 } 4366 ent++; 4367 } 4368 return (ENXIO); 4369 } 4370 4371 int 4372 iflib_device_probe_vendor(device_t dev) 4373 { 4374 int probe; 4375 4376 probe = iflib_device_probe(dev); 4377 if (probe == BUS_PROBE_DEFAULT) 4378 return (BUS_PROBE_VENDOR); 4379 else 4380 return (probe); 4381 } 4382 4383 static void 4384 iflib_reset_qvalues(if_ctx_t ctx) 4385 { 4386 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4387 if_shared_ctx_t sctx = ctx->ifc_sctx; 4388 device_t dev = ctx->ifc_dev; 4389 int i; 4390 4391 if (ctx->ifc_sysctl_ntxqs != 0) 4392 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4393 if (ctx->ifc_sysctl_nrxqs != 0) 4394 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4395 4396 for (i = 0; i < sctx->isc_ntxqs; i++) { 4397 if (ctx->ifc_sysctl_ntxds[i] != 0) 4398 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4399 else 4400 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4401 } 4402 4403 for (i = 0; i < sctx->isc_nrxqs; i++) { 4404 if (ctx->ifc_sysctl_nrxds[i] != 0) 4405 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4406 else 4407 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4408 } 4409 4410 for (i = 0; i < sctx->isc_nrxqs; i++) { 4411 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4412 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4413 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4414 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4415 } 4416 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4417 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4418 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4419 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4420 } 4421 if (!powerof2(scctx->isc_nrxd[i])) { 4422 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4423 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4424 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4425 } 4426 } 4427 4428 for (i = 0; i < sctx->isc_ntxqs; i++) { 4429 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4430 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4431 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4432 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4433 } 4434 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4435 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4436 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4437 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4438 } 4439 if (!powerof2(scctx->isc_ntxd[i])) { 4440 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4441 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4442 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4443 } 4444 } 4445 } 4446 4447 static void 4448 iflib_add_pfil(if_ctx_t ctx) 4449 { 4450 struct pfil_head *pfil; 4451 struct pfil_head_args pa; 4452 iflib_rxq_t rxq; 4453 int i; 4454 4455 pa.pa_version = PFIL_VERSION; 4456 pa.pa_flags = PFIL_IN; 4457 pa.pa_type = PFIL_TYPE_ETHERNET; 4458 pa.pa_headname = ctx->ifc_ifp->if_xname; 4459 pfil = pfil_head_register(&pa); 4460 4461 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4462 rxq->pfil = pfil; 4463 } 4464 } 4465 4466 static void 4467 iflib_rem_pfil(if_ctx_t ctx) 4468 { 4469 struct pfil_head *pfil; 4470 iflib_rxq_t rxq; 4471 int i; 4472 4473 rxq = ctx->ifc_rxqs; 4474 pfil = rxq->pfil; 4475 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4476 rxq->pfil = NULL; 4477 } 4478 pfil_head_unregister(pfil); 4479 } 4480 4481 static uint16_t 4482 get_ctx_core_offset(if_ctx_t ctx) 4483 { 4484 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4485 struct cpu_offset *op; 4486 uint16_t qc; 4487 uint16_t ret = ctx->ifc_sysctl_core_offset; 4488 4489 if (ret != CORE_OFFSET_UNSPECIFIED) 4490 return (ret); 4491 4492 if (ctx->ifc_sysctl_separate_txrx) 4493 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets; 4494 else 4495 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets); 4496 4497 mtx_lock(&cpu_offset_mtx); 4498 SLIST_FOREACH(op, &cpu_offsets, entries) { 4499 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4500 ret = op->offset; 4501 op->offset += qc; 4502 MPASS(op->refcount < UINT_MAX); 4503 op->refcount++; 4504 break; 4505 } 4506 } 4507 if (ret == CORE_OFFSET_UNSPECIFIED) { 4508 ret = 0; 4509 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 4510 M_NOWAIT | M_ZERO); 4511 if (op == NULL) { 4512 device_printf(ctx->ifc_dev, 4513 "allocation for cpu offset failed.\n"); 4514 } else { 4515 op->offset = qc; 4516 op->refcount = 1; 4517 CPU_COPY(&ctx->ifc_cpus, &op->set); 4518 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 4519 } 4520 } 4521 mtx_unlock(&cpu_offset_mtx); 4522 4523 return (ret); 4524 } 4525 4526 static void 4527 unref_ctx_core_offset(if_ctx_t ctx) 4528 { 4529 struct cpu_offset *op, *top; 4530 4531 mtx_lock(&cpu_offset_mtx); 4532 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 4533 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4534 MPASS(op->refcount > 0); 4535 op->refcount--; 4536 if (op->refcount == 0) { 4537 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 4538 free(op, M_IFLIB); 4539 } 4540 break; 4541 } 4542 } 4543 mtx_unlock(&cpu_offset_mtx); 4544 } 4545 4546 int 4547 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4548 { 4549 if_ctx_t ctx; 4550 if_t ifp; 4551 if_softc_ctx_t scctx; 4552 kobjop_desc_t kobj_desc; 4553 kobj_method_t *kobj_method; 4554 int err, msix, rid; 4555 uint16_t main_rxq, main_txq; 4556 4557 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4558 4559 if (sc == NULL) { 4560 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4561 device_set_softc(dev, ctx); 4562 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4563 } 4564 4565 ctx->ifc_sctx = sctx; 4566 ctx->ifc_dev = dev; 4567 ctx->ifc_softc = sc; 4568 4569 if ((err = iflib_register(ctx)) != 0) { 4570 device_printf(dev, "iflib_register failed %d\n", err); 4571 goto fail_ctx_free; 4572 } 4573 iflib_add_device_sysctl_pre(ctx); 4574 4575 scctx = &ctx->ifc_softc_ctx; 4576 ifp = ctx->ifc_ifp; 4577 4578 iflib_reset_qvalues(ctx); 4579 CTX_LOCK(ctx); 4580 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4581 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4582 goto fail_unlock; 4583 } 4584 _iflib_pre_assert(scctx); 4585 ctx->ifc_txrx = *scctx->isc_txrx; 4586 4587 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 4588 ctx->ifc_mediap = scctx->isc_media; 4589 4590 #ifdef INVARIANTS 4591 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4592 MPASS(scctx->isc_tx_csum_flags); 4593 #endif 4594 4595 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS); 4596 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4597 4598 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4599 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4600 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4601 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4602 4603 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4604 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4605 4606 /* XXX change for per-queue sizes */ 4607 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4608 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4609 4610 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4611 MAX_SINGLE_PACKET_FRACTION) 4612 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4613 MAX_SINGLE_PACKET_FRACTION); 4614 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4615 MAX_SINGLE_PACKET_FRACTION) 4616 scctx->isc_tx_tso_segments_max = max(1, 4617 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4618 4619 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4620 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4621 /* 4622 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4623 * but some MACs do. 4624 */ 4625 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4626 IP_MAXPACKET)); 4627 /* 4628 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4629 * into account. In the worst case, each of these calls will 4630 * add another mbuf and, thus, the requirement for another DMA 4631 * segment. So for best performance, it doesn't make sense to 4632 * advertize a maximum of TSO segments that typically will 4633 * require defragmentation in iflib_encap(). 4634 */ 4635 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4636 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4637 } 4638 if (scctx->isc_rss_table_size == 0) 4639 scctx->isc_rss_table_size = 64; 4640 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4641 4642 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4643 /* XXX format name */ 4644 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4645 NULL, NULL, "admin"); 4646 4647 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4648 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4649 device_printf(dev, "Unable to fetch CPU list\n"); 4650 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4651 } 4652 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4653 4654 /* 4655 ** Now set up MSI or MSI-X, should return us the number of supported 4656 ** vectors (will be 1 for a legacy interrupt and MSI). 4657 */ 4658 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4659 msix = scctx->isc_vectors; 4660 } else if (scctx->isc_msix_bar != 0) 4661 /* 4662 * The simple fact that isc_msix_bar is not 0 does not mean we 4663 * we have a good value there that is known to work. 4664 */ 4665 msix = iflib_msix_init(ctx); 4666 else { 4667 scctx->isc_vectors = 1; 4668 scctx->isc_ntxqsets = 1; 4669 scctx->isc_nrxqsets = 1; 4670 scctx->isc_intr = IFLIB_INTR_LEGACY; 4671 msix = 0; 4672 } 4673 /* Get memory for the station queues */ 4674 if ((err = iflib_queues_alloc(ctx))) { 4675 device_printf(dev, "Unable to allocate queue memory\n"); 4676 goto fail_intr_free; 4677 } 4678 4679 if ((err = iflib_qset_structures_setup(ctx))) 4680 goto fail_queues; 4681 4682 /* 4683 * Now that we know how many queues there are, get the core offset. 4684 */ 4685 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 4686 4687 /* 4688 * Group taskqueues aren't properly set up until SMP is started, 4689 * so we disable interrupts until we can handle them post 4690 * SI_SUB_SMP. 4691 * 4692 * XXX: disabling interrupts doesn't actually work, at least for 4693 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4694 * we do null handling and depend on this not causing too large an 4695 * interrupt storm. 4696 */ 4697 IFDI_INTR_DISABLE(ctx); 4698 4699 if (msix > 1) { 4700 /* 4701 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 4702 * aren't the default NULL implementation. 4703 */ 4704 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 4705 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4706 kobj_desc); 4707 if (kobj_method == &kobj_desc->deflt) { 4708 device_printf(dev, 4709 "MSI-X requires ifdi_rx_queue_intr_enable method"); 4710 err = EOPNOTSUPP; 4711 goto fail_queues; 4712 } 4713 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 4714 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4715 kobj_desc); 4716 if (kobj_method == &kobj_desc->deflt) { 4717 device_printf(dev, 4718 "MSI-X requires ifdi_tx_queue_intr_enable method"); 4719 err = EOPNOTSUPP; 4720 goto fail_queues; 4721 } 4722 4723 /* 4724 * Assign the MSI-X vectors. 4725 * Note that the default NULL ifdi_msix_intr_assign method will 4726 * fail here, too. 4727 */ 4728 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 4729 if (err != 0) { 4730 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 4731 err); 4732 goto fail_queues; 4733 } 4734 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 4735 rid = 0; 4736 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4737 MPASS(msix == 1); 4738 rid = 1; 4739 } 4740 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4741 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4742 goto fail_queues; 4743 } 4744 } else { 4745 device_printf(dev, 4746 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 4747 err = ENODEV; 4748 goto fail_intr_free; 4749 } 4750 4751 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4752 4753 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4754 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4755 goto fail_detach; 4756 } 4757 4758 /* 4759 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4760 * This must appear after the call to ether_ifattach() because 4761 * ether_ifattach() sets if_hdrlen to the default value. 4762 */ 4763 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4764 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4765 4766 if ((err = iflib_netmap_attach(ctx))) { 4767 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4768 goto fail_detach; 4769 } 4770 *ctxp = ctx; 4771 4772 NETDUMP_SET(ctx->ifc_ifp, iflib); 4773 4774 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4775 iflib_add_device_sysctl_post(ctx); 4776 iflib_add_pfil(ctx); 4777 ctx->ifc_flags |= IFC_INIT_DONE; 4778 CTX_UNLOCK(ctx); 4779 4780 return (0); 4781 4782 fail_detach: 4783 ether_ifdetach(ctx->ifc_ifp); 4784 fail_intr_free: 4785 iflib_free_intr_mem(ctx); 4786 fail_queues: 4787 iflib_tx_structures_free(ctx); 4788 iflib_rx_structures_free(ctx); 4789 taskqgroup_detach(qgroup_if_config_tqg, &ctx->ifc_admin_task); 4790 IFDI_DETACH(ctx); 4791 fail_unlock: 4792 CTX_UNLOCK(ctx); 4793 fail_ctx_free: 4794 device_set_softc(ctx->ifc_dev, NULL); 4795 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4796 free(ctx->ifc_softc, M_IFLIB); 4797 free(ctx, M_IFLIB); 4798 return (err); 4799 } 4800 4801 int 4802 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4803 struct iflib_cloneattach_ctx *clctx) 4804 { 4805 int err; 4806 if_ctx_t ctx; 4807 if_t ifp; 4808 if_softc_ctx_t scctx; 4809 int i; 4810 void *sc; 4811 uint16_t main_txq; 4812 uint16_t main_rxq; 4813 4814 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4815 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4816 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4817 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4818 ctx->ifc_flags |= IFC_PSEUDO; 4819 4820 ctx->ifc_sctx = sctx; 4821 ctx->ifc_softc = sc; 4822 ctx->ifc_dev = dev; 4823 4824 if ((err = iflib_register(ctx)) != 0) { 4825 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4826 goto fail_ctx_free; 4827 } 4828 iflib_add_device_sysctl_pre(ctx); 4829 4830 scctx = &ctx->ifc_softc_ctx; 4831 ifp = ctx->ifc_ifp; 4832 4833 iflib_reset_qvalues(ctx); 4834 CTX_LOCK(ctx); 4835 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4836 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4837 goto fail_unlock; 4838 } 4839 if (sctx->isc_flags & IFLIB_GEN_MAC) 4840 ether_gen_addr(ifp, &ctx->ifc_mac); 4841 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4842 clctx->cc_params)) != 0) { 4843 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4844 goto fail_ctx_free; 4845 } 4846 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4847 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 4848 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 4849 4850 #ifdef INVARIANTS 4851 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4852 MPASS(scctx->isc_tx_csum_flags); 4853 #endif 4854 4855 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4856 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4857 4858 ifp->if_flags |= IFF_NOGROUP; 4859 if (sctx->isc_flags & IFLIB_PSEUDO) { 4860 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4861 4862 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4863 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4864 goto fail_detach; 4865 } 4866 *ctxp = ctx; 4867 4868 /* 4869 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4870 * This must appear after the call to ether_ifattach() because 4871 * ether_ifattach() sets if_hdrlen to the default value. 4872 */ 4873 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4874 if_setifheaderlen(ifp, 4875 sizeof(struct ether_vlan_header)); 4876 4877 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4878 iflib_add_device_sysctl_post(ctx); 4879 ctx->ifc_flags |= IFC_INIT_DONE; 4880 return (0); 4881 } 4882 _iflib_pre_assert(scctx); 4883 ctx->ifc_txrx = *scctx->isc_txrx; 4884 4885 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4886 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4887 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4888 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4889 4890 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4891 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4892 4893 /* XXX change for per-queue sizes */ 4894 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4895 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4896 4897 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4898 MAX_SINGLE_PACKET_FRACTION) 4899 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4900 MAX_SINGLE_PACKET_FRACTION); 4901 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4902 MAX_SINGLE_PACKET_FRACTION) 4903 scctx->isc_tx_tso_segments_max = max(1, 4904 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4905 4906 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4907 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4908 /* 4909 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4910 * but some MACs do. 4911 */ 4912 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4913 IP_MAXPACKET)); 4914 /* 4915 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4916 * into account. In the worst case, each of these calls will 4917 * add another mbuf and, thus, the requirement for another DMA 4918 * segment. So for best performance, it doesn't make sense to 4919 * advertize a maximum of TSO segments that typically will 4920 * require defragmentation in iflib_encap(). 4921 */ 4922 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4923 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4924 } 4925 if (scctx->isc_rss_table_size == 0) 4926 scctx->isc_rss_table_size = 64; 4927 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4928 4929 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4930 /* XXX format name */ 4931 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4932 NULL, NULL, "admin"); 4933 4934 /* XXX --- can support > 1 -- but keep it simple for now */ 4935 scctx->isc_intr = IFLIB_INTR_LEGACY; 4936 4937 /* Get memory for the station queues */ 4938 if ((err = iflib_queues_alloc(ctx))) { 4939 device_printf(dev, "Unable to allocate queue memory\n"); 4940 goto fail_iflib_detach; 4941 } 4942 4943 if ((err = iflib_qset_structures_setup(ctx))) { 4944 device_printf(dev, "qset structure setup failed %d\n", err); 4945 goto fail_queues; 4946 } 4947 4948 /* 4949 * XXX What if anything do we want to do about interrupts? 4950 */ 4951 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4952 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4953 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4954 goto fail_detach; 4955 } 4956 4957 /* 4958 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4959 * This must appear after the call to ether_ifattach() because 4960 * ether_ifattach() sets if_hdrlen to the default value. 4961 */ 4962 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4963 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4964 4965 /* XXX handle more than one queue */ 4966 for (i = 0; i < scctx->isc_nrxqsets; i++) 4967 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 4968 4969 *ctxp = ctx; 4970 4971 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4972 iflib_add_device_sysctl_post(ctx); 4973 ctx->ifc_flags |= IFC_INIT_DONE; 4974 CTX_UNLOCK(ctx); 4975 4976 return (0); 4977 fail_detach: 4978 ether_ifdetach(ctx->ifc_ifp); 4979 fail_queues: 4980 iflib_tx_structures_free(ctx); 4981 iflib_rx_structures_free(ctx); 4982 fail_iflib_detach: 4983 IFDI_DETACH(ctx); 4984 fail_unlock: 4985 CTX_UNLOCK(ctx); 4986 fail_ctx_free: 4987 free(ctx->ifc_softc, M_IFLIB); 4988 free(ctx, M_IFLIB); 4989 return (err); 4990 } 4991 4992 int 4993 iflib_pseudo_deregister(if_ctx_t ctx) 4994 { 4995 if_t ifp = ctx->ifc_ifp; 4996 iflib_txq_t txq; 4997 iflib_rxq_t rxq; 4998 int i, j; 4999 struct taskqgroup *tqg; 5000 iflib_fl_t fl; 5001 5002 /* Unregister VLAN events */ 5003 if (ctx->ifc_vlan_attach_event != NULL) 5004 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5005 if (ctx->ifc_vlan_detach_event != NULL) 5006 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5007 5008 ether_ifdetach(ifp); 5009 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5010 CTX_LOCK_DESTROY(ctx); 5011 /* XXX drain any dependent tasks */ 5012 tqg = qgroup_if_io_tqg; 5013 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5014 callout_drain(&txq->ift_timer); 5015 if (txq->ift_task.gt_uniq != NULL) 5016 taskqgroup_detach(tqg, &txq->ift_task); 5017 } 5018 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5019 if (rxq->ifr_task.gt_uniq != NULL) 5020 taskqgroup_detach(tqg, &rxq->ifr_task); 5021 5022 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5023 free(fl->ifl_rx_bitmap, M_IFLIB); 5024 } 5025 tqg = qgroup_if_config_tqg; 5026 if (ctx->ifc_admin_task.gt_uniq != NULL) 5027 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5028 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5029 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5030 5031 if_free(ifp); 5032 5033 iflib_tx_structures_free(ctx); 5034 iflib_rx_structures_free(ctx); 5035 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5036 free(ctx->ifc_softc, M_IFLIB); 5037 free(ctx, M_IFLIB); 5038 return (0); 5039 } 5040 5041 int 5042 iflib_device_attach(device_t dev) 5043 { 5044 if_ctx_t ctx; 5045 if_shared_ctx_t sctx; 5046 5047 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5048 return (ENOTSUP); 5049 5050 pci_enable_busmaster(dev); 5051 5052 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5053 } 5054 5055 int 5056 iflib_device_deregister(if_ctx_t ctx) 5057 { 5058 if_t ifp = ctx->ifc_ifp; 5059 iflib_txq_t txq; 5060 iflib_rxq_t rxq; 5061 device_t dev = ctx->ifc_dev; 5062 int i, j; 5063 struct taskqgroup *tqg; 5064 iflib_fl_t fl; 5065 5066 /* Make sure VLANS are not using driver */ 5067 if (if_vlantrunkinuse(ifp)) { 5068 device_printf(dev, "Vlan in use, detach first\n"); 5069 return (EBUSY); 5070 } 5071 #ifdef PCI_IOV 5072 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5073 device_printf(dev, "SR-IOV in use; detach first.\n"); 5074 return (EBUSY); 5075 } 5076 #endif 5077 5078 STATE_LOCK(ctx); 5079 ctx->ifc_flags |= IFC_IN_DETACH; 5080 STATE_UNLOCK(ctx); 5081 5082 CTX_LOCK(ctx); 5083 iflib_stop(ctx); 5084 CTX_UNLOCK(ctx); 5085 5086 /* Unregister VLAN events */ 5087 if (ctx->ifc_vlan_attach_event != NULL) 5088 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5089 if (ctx->ifc_vlan_detach_event != NULL) 5090 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5091 5092 iflib_netmap_detach(ifp); 5093 ether_ifdetach(ifp); 5094 iflib_rem_pfil(ctx); 5095 if (ctx->ifc_led_dev != NULL) 5096 led_destroy(ctx->ifc_led_dev); 5097 /* XXX drain any dependent tasks */ 5098 tqg = qgroup_if_io_tqg; 5099 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5100 callout_drain(&txq->ift_timer); 5101 if (txq->ift_task.gt_uniq != NULL) 5102 taskqgroup_detach(tqg, &txq->ift_task); 5103 } 5104 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5105 if (rxq->ifr_task.gt_uniq != NULL) 5106 taskqgroup_detach(tqg, &rxq->ifr_task); 5107 5108 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5109 free(fl->ifl_rx_bitmap, M_IFLIB); 5110 } 5111 tqg = qgroup_if_config_tqg; 5112 if (ctx->ifc_admin_task.gt_uniq != NULL) 5113 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5114 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5115 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5116 CTX_LOCK(ctx); 5117 IFDI_DETACH(ctx); 5118 CTX_UNLOCK(ctx); 5119 5120 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5121 CTX_LOCK_DESTROY(ctx); 5122 device_set_softc(ctx->ifc_dev, NULL); 5123 iflib_free_intr_mem(ctx); 5124 5125 bus_generic_detach(dev); 5126 if_free(ifp); 5127 5128 iflib_tx_structures_free(ctx); 5129 iflib_rx_structures_free(ctx); 5130 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5131 free(ctx->ifc_softc, M_IFLIB); 5132 unref_ctx_core_offset(ctx); 5133 STATE_LOCK_DESTROY(ctx); 5134 free(ctx, M_IFLIB); 5135 return (0); 5136 } 5137 5138 static void 5139 iflib_free_intr_mem(if_ctx_t ctx) 5140 { 5141 5142 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5143 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5144 } 5145 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5146 pci_release_msi(ctx->ifc_dev); 5147 } 5148 if (ctx->ifc_msix_mem != NULL) { 5149 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5150 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5151 ctx->ifc_msix_mem = NULL; 5152 } 5153 } 5154 5155 int 5156 iflib_device_detach(device_t dev) 5157 { 5158 if_ctx_t ctx = device_get_softc(dev); 5159 5160 return (iflib_device_deregister(ctx)); 5161 } 5162 5163 int 5164 iflib_device_suspend(device_t dev) 5165 { 5166 if_ctx_t ctx = device_get_softc(dev); 5167 5168 CTX_LOCK(ctx); 5169 IFDI_SUSPEND(ctx); 5170 CTX_UNLOCK(ctx); 5171 5172 return bus_generic_suspend(dev); 5173 } 5174 int 5175 iflib_device_shutdown(device_t dev) 5176 { 5177 if_ctx_t ctx = device_get_softc(dev); 5178 5179 CTX_LOCK(ctx); 5180 IFDI_SHUTDOWN(ctx); 5181 CTX_UNLOCK(ctx); 5182 5183 return bus_generic_suspend(dev); 5184 } 5185 5186 5187 int 5188 iflib_device_resume(device_t dev) 5189 { 5190 if_ctx_t ctx = device_get_softc(dev); 5191 iflib_txq_t txq = ctx->ifc_txqs; 5192 5193 CTX_LOCK(ctx); 5194 IFDI_RESUME(ctx); 5195 iflib_if_init_locked(ctx); 5196 CTX_UNLOCK(ctx); 5197 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5198 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5199 5200 return (bus_generic_resume(dev)); 5201 } 5202 5203 int 5204 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5205 { 5206 int error; 5207 if_ctx_t ctx = device_get_softc(dev); 5208 5209 CTX_LOCK(ctx); 5210 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5211 CTX_UNLOCK(ctx); 5212 5213 return (error); 5214 } 5215 5216 void 5217 iflib_device_iov_uninit(device_t dev) 5218 { 5219 if_ctx_t ctx = device_get_softc(dev); 5220 5221 CTX_LOCK(ctx); 5222 IFDI_IOV_UNINIT(ctx); 5223 CTX_UNLOCK(ctx); 5224 } 5225 5226 int 5227 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5228 { 5229 int error; 5230 if_ctx_t ctx = device_get_softc(dev); 5231 5232 CTX_LOCK(ctx); 5233 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5234 CTX_UNLOCK(ctx); 5235 5236 return (error); 5237 } 5238 5239 /********************************************************************* 5240 * 5241 * MODULE FUNCTION DEFINITIONS 5242 * 5243 **********************************************************************/ 5244 5245 /* 5246 * - Start a fast taskqueue thread for each core 5247 * - Start a taskqueue for control operations 5248 */ 5249 static int 5250 iflib_module_init(void) 5251 { 5252 return (0); 5253 } 5254 5255 static int 5256 iflib_module_event_handler(module_t mod, int what, void *arg) 5257 { 5258 int err; 5259 5260 switch (what) { 5261 case MOD_LOAD: 5262 if ((err = iflib_module_init()) != 0) 5263 return (err); 5264 break; 5265 case MOD_UNLOAD: 5266 return (EBUSY); 5267 default: 5268 return (EOPNOTSUPP); 5269 } 5270 5271 return (0); 5272 } 5273 5274 /********************************************************************* 5275 * 5276 * PUBLIC FUNCTION DEFINITIONS 5277 * ordered as in iflib.h 5278 * 5279 **********************************************************************/ 5280 5281 5282 static void 5283 _iflib_assert(if_shared_ctx_t sctx) 5284 { 5285 int i; 5286 5287 MPASS(sctx->isc_tx_maxsize); 5288 MPASS(sctx->isc_tx_maxsegsize); 5289 5290 MPASS(sctx->isc_rx_maxsize); 5291 MPASS(sctx->isc_rx_nsegments); 5292 MPASS(sctx->isc_rx_maxsegsize); 5293 5294 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5295 for (i = 0; i < sctx->isc_nrxqs; i++) { 5296 MPASS(sctx->isc_nrxd_min[i]); 5297 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5298 MPASS(sctx->isc_nrxd_max[i]); 5299 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5300 MPASS(sctx->isc_nrxd_default[i]); 5301 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5302 } 5303 5304 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5305 for (i = 0; i < sctx->isc_ntxqs; i++) { 5306 MPASS(sctx->isc_ntxd_min[i]); 5307 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5308 MPASS(sctx->isc_ntxd_max[i]); 5309 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5310 MPASS(sctx->isc_ntxd_default[i]); 5311 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5312 } 5313 } 5314 5315 static void 5316 _iflib_pre_assert(if_softc_ctx_t scctx) 5317 { 5318 5319 MPASS(scctx->isc_txrx->ift_txd_encap); 5320 MPASS(scctx->isc_txrx->ift_txd_flush); 5321 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5322 MPASS(scctx->isc_txrx->ift_rxd_available); 5323 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5324 MPASS(scctx->isc_txrx->ift_rxd_refill); 5325 MPASS(scctx->isc_txrx->ift_rxd_flush); 5326 } 5327 5328 static int 5329 iflib_register(if_ctx_t ctx) 5330 { 5331 if_shared_ctx_t sctx = ctx->ifc_sctx; 5332 driver_t *driver = sctx->isc_driver; 5333 device_t dev = ctx->ifc_dev; 5334 if_t ifp; 5335 5336 _iflib_assert(sctx); 5337 5338 CTX_LOCK_INIT(ctx); 5339 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5340 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER); 5341 if (ifp == NULL) { 5342 device_printf(dev, "can not allocate ifnet structure\n"); 5343 return (ENOMEM); 5344 } 5345 5346 /* 5347 * Initialize our context's device specific methods 5348 */ 5349 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5350 kobj_class_compile((kobj_class_t) driver); 5351 5352 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5353 if_setsoftc(ifp, ctx); 5354 if_setdev(ifp, dev); 5355 if_setinitfn(ifp, iflib_if_init); 5356 if_setioctlfn(ifp, iflib_if_ioctl); 5357 #ifdef ALTQ 5358 if_setstartfn(ifp, iflib_altq_if_start); 5359 if_settransmitfn(ifp, iflib_altq_if_transmit); 5360 if_setsendqready(ifp); 5361 #else 5362 if_settransmitfn(ifp, iflib_if_transmit); 5363 #endif 5364 if_setqflushfn(ifp, iflib_if_qflush); 5365 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5366 5367 ctx->ifc_vlan_attach_event = 5368 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5369 EVENTHANDLER_PRI_FIRST); 5370 ctx->ifc_vlan_detach_event = 5371 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5372 EVENTHANDLER_PRI_FIRST); 5373 5374 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5375 ctx->ifc_mediap = &ctx->ifc_media; 5376 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5377 iflib_media_change, iflib_media_status); 5378 } 5379 return (0); 5380 } 5381 5382 static int 5383 iflib_queues_alloc(if_ctx_t ctx) 5384 { 5385 if_shared_ctx_t sctx = ctx->ifc_sctx; 5386 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5387 device_t dev = ctx->ifc_dev; 5388 int nrxqsets = scctx->isc_nrxqsets; 5389 int ntxqsets = scctx->isc_ntxqsets; 5390 iflib_txq_t txq; 5391 iflib_rxq_t rxq; 5392 iflib_fl_t fl = NULL; 5393 int i, j, cpu, err, txconf, rxconf; 5394 iflib_dma_info_t ifdip; 5395 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5396 uint32_t *txqsizes = scctx->isc_txqsizes; 5397 uint8_t nrxqs = sctx->isc_nrxqs; 5398 uint8_t ntxqs = sctx->isc_ntxqs; 5399 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5400 caddr_t *vaddrs; 5401 uint64_t *paddrs; 5402 5403 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5404 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5405 5406 /* Allocate the TX ring struct memory */ 5407 if (!(ctx->ifc_txqs = 5408 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5409 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5410 device_printf(dev, "Unable to allocate TX ring memory\n"); 5411 err = ENOMEM; 5412 goto fail; 5413 } 5414 5415 /* Now allocate the RX */ 5416 if (!(ctx->ifc_rxqs = 5417 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5418 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5419 device_printf(dev, "Unable to allocate RX ring memory\n"); 5420 err = ENOMEM; 5421 goto rx_fail; 5422 } 5423 5424 txq = ctx->ifc_txqs; 5425 rxq = ctx->ifc_rxqs; 5426 5427 /* 5428 * XXX handle allocation failure 5429 */ 5430 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5431 /* Set up some basics */ 5432 5433 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5434 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5435 device_printf(dev, 5436 "Unable to allocate TX DMA info memory\n"); 5437 err = ENOMEM; 5438 goto err_tx_desc; 5439 } 5440 txq->ift_ifdi = ifdip; 5441 for (j = 0; j < ntxqs; j++, ifdip++) { 5442 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5443 device_printf(dev, 5444 "Unable to allocate TX descriptors\n"); 5445 err = ENOMEM; 5446 goto err_tx_desc; 5447 } 5448 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5449 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5450 } 5451 txq->ift_ctx = ctx; 5452 txq->ift_id = i; 5453 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5454 txq->ift_br_offset = 1; 5455 } else { 5456 txq->ift_br_offset = 0; 5457 } 5458 /* XXX fix this */ 5459 txq->ift_timer.c_cpu = cpu; 5460 5461 if (iflib_txsd_alloc(txq)) { 5462 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5463 err = ENOMEM; 5464 goto err_tx_desc; 5465 } 5466 5467 /* Initialize the TX lock */ 5468 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5469 device_get_nameunit(dev), txq->ift_id); 5470 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5471 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5472 5473 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5474 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5475 if (err) { 5476 /* XXX free any allocated rings */ 5477 device_printf(dev, "Unable to allocate buf_ring\n"); 5478 goto err_tx_desc; 5479 } 5480 } 5481 5482 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5483 /* Set up some basics */ 5484 5485 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5486 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5487 device_printf(dev, 5488 "Unable to allocate RX DMA info memory\n"); 5489 err = ENOMEM; 5490 goto err_tx_desc; 5491 } 5492 5493 rxq->ifr_ifdi = ifdip; 5494 /* XXX this needs to be changed if #rx queues != #tx queues */ 5495 rxq->ifr_ntxqirq = 1; 5496 rxq->ifr_txqid[0] = i; 5497 for (j = 0; j < nrxqs; j++, ifdip++) { 5498 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5499 device_printf(dev, 5500 "Unable to allocate RX descriptors\n"); 5501 err = ENOMEM; 5502 goto err_tx_desc; 5503 } 5504 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5505 } 5506 rxq->ifr_ctx = ctx; 5507 rxq->ifr_id = i; 5508 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5509 rxq->ifr_fl_offset = 1; 5510 } else { 5511 rxq->ifr_fl_offset = 0; 5512 } 5513 rxq->ifr_nfl = nfree_lists; 5514 if (!(fl = 5515 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5516 device_printf(dev, "Unable to allocate free list memory\n"); 5517 err = ENOMEM; 5518 goto err_tx_desc; 5519 } 5520 rxq->ifr_fl = fl; 5521 for (j = 0; j < nfree_lists; j++) { 5522 fl[j].ifl_rxq = rxq; 5523 fl[j].ifl_id = j; 5524 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5525 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5526 } 5527 /* Allocate receive buffers for the ring */ 5528 if (iflib_rxsd_alloc(rxq)) { 5529 device_printf(dev, 5530 "Critical Failure setting up receive buffers\n"); 5531 err = ENOMEM; 5532 goto err_rx_desc; 5533 } 5534 5535 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5536 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5537 M_WAITOK); 5538 } 5539 5540 /* TXQs */ 5541 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5542 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5543 for (i = 0; i < ntxqsets; i++) { 5544 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5545 5546 for (j = 0; j < ntxqs; j++, di++) { 5547 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5548 paddrs[i*ntxqs + j] = di->idi_paddr; 5549 } 5550 } 5551 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5552 device_printf(ctx->ifc_dev, 5553 "Unable to allocate device TX queue\n"); 5554 iflib_tx_structures_free(ctx); 5555 free(vaddrs, M_IFLIB); 5556 free(paddrs, M_IFLIB); 5557 goto err_rx_desc; 5558 } 5559 free(vaddrs, M_IFLIB); 5560 free(paddrs, M_IFLIB); 5561 5562 /* RXQs */ 5563 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5564 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5565 for (i = 0; i < nrxqsets; i++) { 5566 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5567 5568 for (j = 0; j < nrxqs; j++, di++) { 5569 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5570 paddrs[i*nrxqs + j] = di->idi_paddr; 5571 } 5572 } 5573 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5574 device_printf(ctx->ifc_dev, 5575 "Unable to allocate device RX queue\n"); 5576 iflib_tx_structures_free(ctx); 5577 free(vaddrs, M_IFLIB); 5578 free(paddrs, M_IFLIB); 5579 goto err_rx_desc; 5580 } 5581 free(vaddrs, M_IFLIB); 5582 free(paddrs, M_IFLIB); 5583 5584 return (0); 5585 5586 /* XXX handle allocation failure changes */ 5587 err_rx_desc: 5588 err_tx_desc: 5589 rx_fail: 5590 if (ctx->ifc_rxqs != NULL) 5591 free(ctx->ifc_rxqs, M_IFLIB); 5592 ctx->ifc_rxqs = NULL; 5593 if (ctx->ifc_txqs != NULL) 5594 free(ctx->ifc_txqs, M_IFLIB); 5595 ctx->ifc_txqs = NULL; 5596 fail: 5597 return (err); 5598 } 5599 5600 static int 5601 iflib_tx_structures_setup(if_ctx_t ctx) 5602 { 5603 iflib_txq_t txq = ctx->ifc_txqs; 5604 int i; 5605 5606 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5607 iflib_txq_setup(txq); 5608 5609 return (0); 5610 } 5611 5612 static void 5613 iflib_tx_structures_free(if_ctx_t ctx) 5614 { 5615 iflib_txq_t txq = ctx->ifc_txqs; 5616 if_shared_ctx_t sctx = ctx->ifc_sctx; 5617 int i, j; 5618 5619 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5620 iflib_txq_destroy(txq); 5621 for (j = 0; j < sctx->isc_ntxqs; j++) 5622 iflib_dma_free(&txq->ift_ifdi[j]); 5623 } 5624 free(ctx->ifc_txqs, M_IFLIB); 5625 ctx->ifc_txqs = NULL; 5626 IFDI_QUEUES_FREE(ctx); 5627 } 5628 5629 /********************************************************************* 5630 * 5631 * Initialize all receive rings. 5632 * 5633 **********************************************************************/ 5634 static int 5635 iflib_rx_structures_setup(if_ctx_t ctx) 5636 { 5637 iflib_rxq_t rxq = ctx->ifc_rxqs; 5638 int q; 5639 #if defined(INET6) || defined(INET) 5640 int err, i; 5641 #endif 5642 5643 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5644 #if defined(INET6) || defined(INET) 5645 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) { 5646 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5647 TCP_LRO_ENTRIES, min(1024, 5648 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 5649 if (err != 0) { 5650 device_printf(ctx->ifc_dev, 5651 "LRO Initialization failed!\n"); 5652 goto fail; 5653 } 5654 } 5655 #endif 5656 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5657 } 5658 return (0); 5659 #if defined(INET6) || defined(INET) 5660 fail: 5661 /* 5662 * Free LRO resources allocated so far, we will only handle 5663 * the rings that completed, the failing case will have 5664 * cleaned up for itself. 'q' failed, so its the terminus. 5665 */ 5666 rxq = ctx->ifc_rxqs; 5667 for (i = 0; i < q; ++i, rxq++) { 5668 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5669 tcp_lro_free(&rxq->ifr_lc); 5670 } 5671 return (err); 5672 #endif 5673 } 5674 5675 /********************************************************************* 5676 * 5677 * Free all receive rings. 5678 * 5679 **********************************************************************/ 5680 static void 5681 iflib_rx_structures_free(if_ctx_t ctx) 5682 { 5683 iflib_rxq_t rxq = ctx->ifc_rxqs; 5684 int i; 5685 5686 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5687 iflib_rx_sds_free(rxq); 5688 #if defined(INET6) || defined(INET) 5689 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5690 tcp_lro_free(&rxq->ifr_lc); 5691 #endif 5692 } 5693 free(ctx->ifc_rxqs, M_IFLIB); 5694 ctx->ifc_rxqs = NULL; 5695 } 5696 5697 static int 5698 iflib_qset_structures_setup(if_ctx_t ctx) 5699 { 5700 int err; 5701 5702 /* 5703 * It is expected that the caller takes care of freeing queues if this 5704 * fails. 5705 */ 5706 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5707 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5708 return (err); 5709 } 5710 5711 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5712 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5713 5714 return (err); 5715 } 5716 5717 int 5718 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5719 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5720 { 5721 5722 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5723 } 5724 5725 #ifdef SMP 5726 static int 5727 find_nth(if_ctx_t ctx, int qid) 5728 { 5729 cpuset_t cpus; 5730 int i, cpuid, eqid, count; 5731 5732 CPU_COPY(&ctx->ifc_cpus, &cpus); 5733 count = CPU_COUNT(&cpus); 5734 eqid = qid % count; 5735 /* clear up to the qid'th bit */ 5736 for (i = 0; i < eqid; i++) { 5737 cpuid = CPU_FFS(&cpus); 5738 MPASS(cpuid != 0); 5739 CPU_CLR(cpuid-1, &cpus); 5740 } 5741 cpuid = CPU_FFS(&cpus); 5742 MPASS(cpuid != 0); 5743 return (cpuid-1); 5744 } 5745 5746 #ifdef SCHED_ULE 5747 extern struct cpu_group *cpu_top; /* CPU topology */ 5748 5749 static int 5750 find_child_with_core(int cpu, struct cpu_group *grp) 5751 { 5752 int i; 5753 5754 if (grp->cg_children == 0) 5755 return -1; 5756 5757 MPASS(grp->cg_child); 5758 for (i = 0; i < grp->cg_children; i++) { 5759 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5760 return i; 5761 } 5762 5763 return -1; 5764 } 5765 5766 /* 5767 * Find the nth "close" core to the specified core 5768 * "close" is defined as the deepest level that shares 5769 * at least an L2 cache. With threads, this will be 5770 * threads on the same core. If the shared cache is L3 5771 * or higher, simply returns the same core. 5772 */ 5773 static int 5774 find_close_core(int cpu, int core_offset) 5775 { 5776 struct cpu_group *grp; 5777 int i; 5778 int fcpu; 5779 cpuset_t cs; 5780 5781 grp = cpu_top; 5782 if (grp == NULL) 5783 return cpu; 5784 i = 0; 5785 while ((i = find_child_with_core(cpu, grp)) != -1) { 5786 /* If the child only has one cpu, don't descend */ 5787 if (grp->cg_child[i].cg_count <= 1) 5788 break; 5789 grp = &grp->cg_child[i]; 5790 } 5791 5792 /* If they don't share at least an L2 cache, use the same CPU */ 5793 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5794 return cpu; 5795 5796 /* Now pick one */ 5797 CPU_COPY(&grp->cg_mask, &cs); 5798 5799 /* Add the selected CPU offset to core offset. */ 5800 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5801 if (fcpu - 1 == cpu) 5802 break; 5803 CPU_CLR(fcpu - 1, &cs); 5804 } 5805 MPASS(fcpu); 5806 5807 core_offset += i; 5808 5809 CPU_COPY(&grp->cg_mask, &cs); 5810 for (i = core_offset % grp->cg_count; i > 0; i--) { 5811 MPASS(CPU_FFS(&cs)); 5812 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5813 } 5814 MPASS(CPU_FFS(&cs)); 5815 return CPU_FFS(&cs) - 1; 5816 } 5817 #else 5818 static int 5819 find_close_core(int cpu, int core_offset __unused) 5820 { 5821 return cpu; 5822 } 5823 #endif 5824 5825 static int 5826 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5827 { 5828 switch (type) { 5829 case IFLIB_INTR_TX: 5830 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5831 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5832 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5833 case IFLIB_INTR_RX: 5834 case IFLIB_INTR_RXTX: 5835 /* RX queues get the specified core */ 5836 return qid / CPU_COUNT(&ctx->ifc_cpus); 5837 default: 5838 return -1; 5839 } 5840 } 5841 #else 5842 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5843 #define find_close_core(cpuid, tid) CPU_FIRST() 5844 #define find_nth(ctx, gid) CPU_FIRST() 5845 #endif 5846 5847 /* Just to avoid copy/paste */ 5848 static inline int 5849 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 5850 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 5851 const char *name) 5852 { 5853 device_t dev; 5854 int co, cpuid, err, tid; 5855 5856 dev = ctx->ifc_dev; 5857 co = ctx->ifc_sysctl_core_offset; 5858 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX) 5859 co += ctx->ifc_softc_ctx.isc_nrxqsets; 5860 cpuid = find_nth(ctx, qid + co); 5861 tid = get_core_offset(ctx, type, qid); 5862 if (tid < 0) { 5863 device_printf(dev, "get_core_offset failed\n"); 5864 return (EOPNOTSUPP); 5865 } 5866 cpuid = find_close_core(cpuid, tid); 5867 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res, 5868 name); 5869 if (err) { 5870 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 5871 return (err); 5872 } 5873 #ifdef notyet 5874 if (cpuid > ctx->ifc_cpuid_highest) 5875 ctx->ifc_cpuid_highest = cpuid; 5876 #endif 5877 return (0); 5878 } 5879 5880 int 5881 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5882 iflib_intr_type_t type, driver_filter_t *filter, 5883 void *filter_arg, int qid, const char *name) 5884 { 5885 device_t dev; 5886 struct grouptask *gtask; 5887 struct taskqgroup *tqg; 5888 iflib_filter_info_t info; 5889 gtask_fn_t *fn; 5890 int tqrid, err; 5891 driver_filter_t *intr_fast; 5892 void *q; 5893 5894 info = &ctx->ifc_filter_info; 5895 tqrid = rid; 5896 5897 switch (type) { 5898 /* XXX merge tx/rx for netmap? */ 5899 case IFLIB_INTR_TX: 5900 q = &ctx->ifc_txqs[qid]; 5901 info = &ctx->ifc_txqs[qid].ift_filter_info; 5902 gtask = &ctx->ifc_txqs[qid].ift_task; 5903 tqg = qgroup_if_io_tqg; 5904 fn = _task_fn_tx; 5905 intr_fast = iflib_fast_intr; 5906 GROUPTASK_INIT(gtask, 0, fn, q); 5907 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 5908 break; 5909 case IFLIB_INTR_RX: 5910 q = &ctx->ifc_rxqs[qid]; 5911 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5912 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5913 tqg = qgroup_if_io_tqg; 5914 fn = _task_fn_rx; 5915 intr_fast = iflib_fast_intr; 5916 GROUPTASK_INIT(gtask, 0, fn, q); 5917 break; 5918 case IFLIB_INTR_RXTX: 5919 q = &ctx->ifc_rxqs[qid]; 5920 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5921 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5922 tqg = qgroup_if_io_tqg; 5923 fn = _task_fn_rx; 5924 intr_fast = iflib_fast_intr_rxtx; 5925 GROUPTASK_INIT(gtask, 0, fn, q); 5926 break; 5927 case IFLIB_INTR_ADMIN: 5928 q = ctx; 5929 tqrid = -1; 5930 info = &ctx->ifc_filter_info; 5931 gtask = &ctx->ifc_admin_task; 5932 tqg = qgroup_if_config_tqg; 5933 fn = _task_fn_admin; 5934 intr_fast = iflib_fast_intr_ctx; 5935 break; 5936 default: 5937 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 5938 __func__); 5939 return (EINVAL); 5940 } 5941 5942 info->ifi_filter = filter; 5943 info->ifi_filter_arg = filter_arg; 5944 info->ifi_task = gtask; 5945 info->ifi_ctx = q; 5946 5947 dev = ctx->ifc_dev; 5948 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5949 if (err != 0) { 5950 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 5951 return (err); 5952 } 5953 if (type == IFLIB_INTR_ADMIN) 5954 return (0); 5955 5956 if (tqrid != -1) { 5957 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 5958 q, name); 5959 if (err) 5960 return (err); 5961 } else { 5962 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 5963 } 5964 5965 return (0); 5966 } 5967 5968 void 5969 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 5970 { 5971 struct grouptask *gtask; 5972 struct taskqgroup *tqg; 5973 gtask_fn_t *fn; 5974 void *q; 5975 int err; 5976 5977 switch (type) { 5978 case IFLIB_INTR_TX: 5979 q = &ctx->ifc_txqs[qid]; 5980 gtask = &ctx->ifc_txqs[qid].ift_task; 5981 tqg = qgroup_if_io_tqg; 5982 fn = _task_fn_tx; 5983 break; 5984 case IFLIB_INTR_RX: 5985 q = &ctx->ifc_rxqs[qid]; 5986 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5987 tqg = qgroup_if_io_tqg; 5988 fn = _task_fn_rx; 5989 break; 5990 case IFLIB_INTR_IOV: 5991 q = ctx; 5992 gtask = &ctx->ifc_vflr_task; 5993 tqg = qgroup_if_config_tqg; 5994 fn = _task_fn_iov; 5995 break; 5996 default: 5997 panic("unknown net intr type"); 5998 } 5999 GROUPTASK_INIT(gtask, 0, fn, q); 6000 if (irq != NULL) { 6001 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6002 q, name); 6003 if (err) 6004 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev, 6005 irq->ii_res, name); 6006 } else { 6007 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name); 6008 } 6009 } 6010 6011 void 6012 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6013 { 6014 6015 if (irq->ii_tag) 6016 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6017 6018 if (irq->ii_res) 6019 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6020 rman_get_rid(irq->ii_res), irq->ii_res); 6021 } 6022 6023 static int 6024 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6025 { 6026 iflib_txq_t txq = ctx->ifc_txqs; 6027 iflib_rxq_t rxq = ctx->ifc_rxqs; 6028 if_irq_t irq = &ctx->ifc_legacy_irq; 6029 iflib_filter_info_t info; 6030 device_t dev; 6031 struct grouptask *gtask; 6032 struct resource *res; 6033 struct taskqgroup *tqg; 6034 gtask_fn_t *fn; 6035 void *q; 6036 int err, tqrid; 6037 6038 q = &ctx->ifc_rxqs[0]; 6039 info = &rxq[0].ifr_filter_info; 6040 gtask = &rxq[0].ifr_task; 6041 tqg = qgroup_if_io_tqg; 6042 tqrid = *rid; 6043 fn = _task_fn_rx; 6044 6045 ctx->ifc_flags |= IFC_LEGACY; 6046 info->ifi_filter = filter; 6047 info->ifi_filter_arg = filter_arg; 6048 info->ifi_task = gtask; 6049 info->ifi_ctx = q; 6050 6051 dev = ctx->ifc_dev; 6052 /* We allocate a single interrupt resource */ 6053 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_rxtx, 6054 NULL, info, name)) != 0) 6055 return (err); 6056 GROUPTASK_INIT(gtask, 0, fn, q); 6057 res = irq->ii_res; 6058 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6059 6060 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6061 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6062 "tx"); 6063 return (0); 6064 } 6065 6066 void 6067 iflib_led_create(if_ctx_t ctx) 6068 { 6069 6070 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6071 device_get_nameunit(ctx->ifc_dev)); 6072 } 6073 6074 void 6075 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6076 { 6077 6078 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6079 } 6080 6081 void 6082 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6083 { 6084 6085 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6086 } 6087 6088 void 6089 iflib_admin_intr_deferred(if_ctx_t ctx) 6090 { 6091 #ifdef INVARIANTS 6092 struct grouptask *gtask; 6093 6094 gtask = &ctx->ifc_admin_task; 6095 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 6096 #endif 6097 6098 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6099 } 6100 6101 void 6102 iflib_iov_intr_deferred(if_ctx_t ctx) 6103 { 6104 6105 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6106 } 6107 6108 void 6109 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6110 { 6111 6112 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6113 name); 6114 } 6115 6116 void 6117 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6118 const char *name) 6119 { 6120 6121 GROUPTASK_INIT(gtask, 0, fn, ctx); 6122 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6123 name); 6124 } 6125 6126 void 6127 iflib_config_gtask_deinit(struct grouptask *gtask) 6128 { 6129 6130 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6131 } 6132 6133 void 6134 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6135 { 6136 if_t ifp = ctx->ifc_ifp; 6137 iflib_txq_t txq = ctx->ifc_txqs; 6138 6139 if_setbaudrate(ifp, baudrate); 6140 if (baudrate >= IF_Gbps(10)) { 6141 STATE_LOCK(ctx); 6142 ctx->ifc_flags |= IFC_PREFETCH; 6143 STATE_UNLOCK(ctx); 6144 } 6145 /* If link down, disable watchdog */ 6146 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6147 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6148 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6149 } 6150 ctx->ifc_link_state = link_state; 6151 if_link_state_change(ifp, link_state); 6152 } 6153 6154 static int 6155 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6156 { 6157 int credits; 6158 #ifdef INVARIANTS 6159 int credits_pre = txq->ift_cidx_processed; 6160 #endif 6161 6162 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6163 BUS_DMASYNC_POSTREAD); 6164 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6165 return (0); 6166 6167 txq->ift_processed += credits; 6168 txq->ift_cidx_processed += credits; 6169 6170 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6171 if (txq->ift_cidx_processed >= txq->ift_size) 6172 txq->ift_cidx_processed -= txq->ift_size; 6173 return (credits); 6174 } 6175 6176 static int 6177 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6178 { 6179 iflib_fl_t fl; 6180 u_int i; 6181 6182 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6183 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6184 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6185 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6186 budget)); 6187 } 6188 6189 void 6190 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6191 const char *description, if_int_delay_info_t info, 6192 int offset, int value) 6193 { 6194 info->iidi_ctx = ctx; 6195 info->iidi_offset = offset; 6196 info->iidi_value = value; 6197 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6198 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6199 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 6200 info, 0, iflib_sysctl_int_delay, "I", description); 6201 } 6202 6203 struct sx * 6204 iflib_ctx_lock_get(if_ctx_t ctx) 6205 { 6206 6207 return (&ctx->ifc_ctx_sx); 6208 } 6209 6210 static int 6211 iflib_msix_init(if_ctx_t ctx) 6212 { 6213 device_t dev = ctx->ifc_dev; 6214 if_shared_ctx_t sctx = ctx->ifc_sctx; 6215 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6216 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6217 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6218 6219 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6220 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6221 6222 if (bootverbose) 6223 device_printf(dev, "msix_init qsets capped at %d\n", 6224 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6225 6226 /* Override by tuneable */ 6227 if (scctx->isc_disable_msix) 6228 goto msi; 6229 6230 /* First try MSI-X */ 6231 if ((msgs = pci_msix_count(dev)) == 0) { 6232 if (bootverbose) 6233 device_printf(dev, "MSI-X not supported or disabled\n"); 6234 goto msi; 6235 } 6236 6237 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6238 /* 6239 * bar == -1 => "trust me I know what I'm doing" 6240 * Some drivers are for hardware that is so shoddily 6241 * documented that no one knows which bars are which 6242 * so the developer has to map all bars. This hack 6243 * allows shoddy garbage to use MSI-X in this framework. 6244 */ 6245 if (bar != -1) { 6246 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6247 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6248 if (ctx->ifc_msix_mem == NULL) { 6249 device_printf(dev, "Unable to map MSI-X table\n"); 6250 goto msi; 6251 } 6252 } 6253 6254 admincnt = sctx->isc_admin_intrcnt; 6255 #if IFLIB_DEBUG 6256 /* use only 1 qset in debug mode */ 6257 queuemsgs = min(msgs - admincnt, 1); 6258 #else 6259 queuemsgs = msgs - admincnt; 6260 #endif 6261 #ifdef RSS 6262 queues = imin(queuemsgs, rss_getnumbuckets()); 6263 #else 6264 queues = queuemsgs; 6265 #endif 6266 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6267 if (bootverbose) 6268 device_printf(dev, 6269 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6270 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6271 #ifdef RSS 6272 /* If we're doing RSS, clamp at the number of RSS buckets */ 6273 if (queues > rss_getnumbuckets()) 6274 queues = rss_getnumbuckets(); 6275 #endif 6276 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6277 rx_queues = iflib_num_rx_queues; 6278 else 6279 rx_queues = queues; 6280 6281 if (rx_queues > scctx->isc_nrxqsets) 6282 rx_queues = scctx->isc_nrxqsets; 6283 6284 /* 6285 * We want this to be all logical CPUs by default 6286 */ 6287 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6288 tx_queues = iflib_num_tx_queues; 6289 else 6290 tx_queues = mp_ncpus; 6291 6292 if (tx_queues > scctx->isc_ntxqsets) 6293 tx_queues = scctx->isc_ntxqsets; 6294 6295 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6296 #ifdef INVARIANTS 6297 if (tx_queues != rx_queues) 6298 device_printf(dev, 6299 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6300 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6301 #endif 6302 tx_queues = min(rx_queues, tx_queues); 6303 rx_queues = min(rx_queues, tx_queues); 6304 } 6305 6306 vectors = rx_queues + admincnt; 6307 if (msgs < vectors) { 6308 device_printf(dev, 6309 "insufficient number of MSI-X vectors " 6310 "(supported %d, need %d)\n", msgs, vectors); 6311 goto msi; 6312 } 6313 6314 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6315 tx_queues); 6316 msgs = vectors; 6317 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6318 if (vectors != msgs) { 6319 device_printf(dev, 6320 "Unable to allocate sufficient MSI-X vectors " 6321 "(got %d, need %d)\n", vectors, msgs); 6322 pci_release_msi(dev); 6323 if (bar != -1) { 6324 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6325 ctx->ifc_msix_mem); 6326 ctx->ifc_msix_mem = NULL; 6327 } 6328 goto msi; 6329 } 6330 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6331 vectors); 6332 scctx->isc_vectors = vectors; 6333 scctx->isc_nrxqsets = rx_queues; 6334 scctx->isc_ntxqsets = tx_queues; 6335 scctx->isc_intr = IFLIB_INTR_MSIX; 6336 6337 return (vectors); 6338 } else { 6339 device_printf(dev, 6340 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6341 err); 6342 if (bar != -1) { 6343 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6344 ctx->ifc_msix_mem); 6345 ctx->ifc_msix_mem = NULL; 6346 } 6347 } 6348 6349 msi: 6350 vectors = pci_msi_count(dev); 6351 scctx->isc_nrxqsets = 1; 6352 scctx->isc_ntxqsets = 1; 6353 scctx->isc_vectors = vectors; 6354 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6355 device_printf(dev,"Using an MSI interrupt\n"); 6356 scctx->isc_intr = IFLIB_INTR_MSI; 6357 } else { 6358 scctx->isc_vectors = 1; 6359 device_printf(dev,"Using a Legacy interrupt\n"); 6360 scctx->isc_intr = IFLIB_INTR_LEGACY; 6361 } 6362 6363 return (vectors); 6364 } 6365 6366 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6367 6368 static int 6369 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6370 { 6371 int rc; 6372 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6373 struct sbuf *sb; 6374 const char *ring_state = "UNKNOWN"; 6375 6376 /* XXX needed ? */ 6377 rc = sysctl_wire_old_buffer(req, 0); 6378 MPASS(rc == 0); 6379 if (rc != 0) 6380 return (rc); 6381 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6382 MPASS(sb != NULL); 6383 if (sb == NULL) 6384 return (ENOMEM); 6385 if (state[3] <= 3) 6386 ring_state = ring_states[state[3]]; 6387 6388 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6389 state[0], state[1], state[2], ring_state); 6390 rc = sbuf_finish(sb); 6391 sbuf_delete(sb); 6392 return(rc); 6393 } 6394 6395 enum iflib_ndesc_handler { 6396 IFLIB_NTXD_HANDLER, 6397 IFLIB_NRXD_HANDLER, 6398 }; 6399 6400 static int 6401 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6402 { 6403 if_ctx_t ctx = (void *)arg1; 6404 enum iflib_ndesc_handler type = arg2; 6405 char buf[256] = {0}; 6406 qidx_t *ndesc; 6407 char *p, *next; 6408 int nqs, rc, i; 6409 6410 nqs = 8; 6411 switch(type) { 6412 case IFLIB_NTXD_HANDLER: 6413 ndesc = ctx->ifc_sysctl_ntxds; 6414 if (ctx->ifc_sctx) 6415 nqs = ctx->ifc_sctx->isc_ntxqs; 6416 break; 6417 case IFLIB_NRXD_HANDLER: 6418 ndesc = ctx->ifc_sysctl_nrxds; 6419 if (ctx->ifc_sctx) 6420 nqs = ctx->ifc_sctx->isc_nrxqs; 6421 break; 6422 default: 6423 printf("%s: unhandled type\n", __func__); 6424 return (EINVAL); 6425 } 6426 if (nqs == 0) 6427 nqs = 8; 6428 6429 for (i=0; i<8; i++) { 6430 if (i >= nqs) 6431 break; 6432 if (i) 6433 strcat(buf, ","); 6434 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6435 } 6436 6437 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6438 if (rc || req->newptr == NULL) 6439 return rc; 6440 6441 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6442 i++, p = strsep(&next, " ,")) { 6443 ndesc[i] = strtoul(p, NULL, 10); 6444 } 6445 6446 return(rc); 6447 } 6448 6449 #define NAME_BUFLEN 32 6450 static void 6451 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6452 { 6453 device_t dev = iflib_get_dev(ctx); 6454 struct sysctl_oid_list *child, *oid_list; 6455 struct sysctl_ctx_list *ctx_list; 6456 struct sysctl_oid *node; 6457 6458 ctx_list = device_get_sysctl_ctx(dev); 6459 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6460 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6461 CTLFLAG_RD, NULL, "IFLIB fields"); 6462 oid_list = SYSCTL_CHILDREN(node); 6463 6464 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6465 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6466 "driver version"); 6467 6468 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6469 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6470 "# of txqs to use, 0 => use default #"); 6471 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6472 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6473 "# of rxqs to use, 0 => use default #"); 6474 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6475 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6476 "permit #txq != #rxq"); 6477 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6478 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6479 "disable MSI-X (default 0)"); 6480 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6481 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6482 "set the RX budget"); 6483 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6484 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6485 "cause TX to abdicate instead of running to completion"); 6486 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6487 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6488 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6489 "offset to start using cores at"); 6490 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6491 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6492 "use separate cores for TX and RX"); 6493 6494 /* XXX change for per-queue sizes */ 6495 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6496 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 6497 mp_ndesc_handler, "A", 6498 "list of # of TX descriptors to use, 0 = use default #"); 6499 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6500 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 6501 mp_ndesc_handler, "A", 6502 "list of # of RX descriptors to use, 0 = use default #"); 6503 } 6504 6505 static void 6506 iflib_add_device_sysctl_post(if_ctx_t ctx) 6507 { 6508 if_shared_ctx_t sctx = ctx->ifc_sctx; 6509 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6510 device_t dev = iflib_get_dev(ctx); 6511 struct sysctl_oid_list *child; 6512 struct sysctl_ctx_list *ctx_list; 6513 iflib_fl_t fl; 6514 iflib_txq_t txq; 6515 iflib_rxq_t rxq; 6516 int i, j; 6517 char namebuf[NAME_BUFLEN]; 6518 char *qfmt; 6519 struct sysctl_oid *queue_node, *fl_node, *node; 6520 struct sysctl_oid_list *queue_list, *fl_list; 6521 ctx_list = device_get_sysctl_ctx(dev); 6522 6523 node = ctx->ifc_sysctl_node; 6524 child = SYSCTL_CHILDREN(node); 6525 6526 if (scctx->isc_ntxqsets > 100) 6527 qfmt = "txq%03d"; 6528 else if (scctx->isc_ntxqsets > 10) 6529 qfmt = "txq%02d"; 6530 else 6531 qfmt = "txq%d"; 6532 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6533 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6534 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6535 CTLFLAG_RD, NULL, "Queue Name"); 6536 queue_list = SYSCTL_CHILDREN(queue_node); 6537 #if MEMORY_LOGGING 6538 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6539 CTLFLAG_RD, 6540 &txq->ift_dequeued, "total mbufs freed"); 6541 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6542 CTLFLAG_RD, 6543 &txq->ift_enqueued, "total mbufs enqueued"); 6544 #endif 6545 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6546 CTLFLAG_RD, 6547 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6548 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6549 CTLFLAG_RD, 6550 &txq->ift_pullups, "# of times m_pullup was called"); 6551 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6552 CTLFLAG_RD, 6553 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6554 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6555 CTLFLAG_RD, 6556 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6557 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6558 CTLFLAG_RD, 6559 &txq->ift_map_failed, "# of times DMA map failed"); 6560 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6561 CTLFLAG_RD, 6562 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6563 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6564 CTLFLAG_RD, 6565 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6566 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6567 CTLFLAG_RD, 6568 &txq->ift_pidx, 1, "Producer Index"); 6569 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6570 CTLFLAG_RD, 6571 &txq->ift_cidx, 1, "Consumer Index"); 6572 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6573 CTLFLAG_RD, 6574 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6575 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6576 CTLFLAG_RD, 6577 &txq->ift_in_use, 1, "descriptors in use"); 6578 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6579 CTLFLAG_RD, 6580 &txq->ift_processed, "descriptors procesed for clean"); 6581 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6582 CTLFLAG_RD, 6583 &txq->ift_cleaned, "total cleaned"); 6584 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6585 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 6586 0, mp_ring_state_handler, "A", "soft ring state"); 6587 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6588 CTLFLAG_RD, &txq->ift_br->enqueues, 6589 "# of enqueues to the mp_ring for this queue"); 6590 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6591 CTLFLAG_RD, &txq->ift_br->drops, 6592 "# of drops in the mp_ring for this queue"); 6593 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6594 CTLFLAG_RD, &txq->ift_br->starts, 6595 "# of normal consumer starts in the mp_ring for this queue"); 6596 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6597 CTLFLAG_RD, &txq->ift_br->stalls, 6598 "# of consumer stalls in the mp_ring for this queue"); 6599 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6600 CTLFLAG_RD, &txq->ift_br->restarts, 6601 "# of consumer restarts in the mp_ring for this queue"); 6602 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6603 CTLFLAG_RD, &txq->ift_br->abdications, 6604 "# of consumer abdications in the mp_ring for this queue"); 6605 } 6606 6607 if (scctx->isc_nrxqsets > 100) 6608 qfmt = "rxq%03d"; 6609 else if (scctx->isc_nrxqsets > 10) 6610 qfmt = "rxq%02d"; 6611 else 6612 qfmt = "rxq%d"; 6613 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6614 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6615 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6616 CTLFLAG_RD, NULL, "Queue Name"); 6617 queue_list = SYSCTL_CHILDREN(queue_node); 6618 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6619 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6620 CTLFLAG_RD, 6621 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6622 } 6623 6624 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6625 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6626 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6627 CTLFLAG_RD, NULL, "freelist Name"); 6628 fl_list = SYSCTL_CHILDREN(fl_node); 6629 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6630 CTLFLAG_RD, 6631 &fl->ifl_pidx, 1, "Producer Index"); 6632 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6633 CTLFLAG_RD, 6634 &fl->ifl_cidx, 1, "Consumer Index"); 6635 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6636 CTLFLAG_RD, 6637 &fl->ifl_credits, 1, "credits available"); 6638 #if MEMORY_LOGGING 6639 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6640 CTLFLAG_RD, 6641 &fl->ifl_m_enqueued, "mbufs allocated"); 6642 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6643 CTLFLAG_RD, 6644 &fl->ifl_m_dequeued, "mbufs freed"); 6645 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6646 CTLFLAG_RD, 6647 &fl->ifl_cl_enqueued, "clusters allocated"); 6648 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6649 CTLFLAG_RD, 6650 &fl->ifl_cl_dequeued, "clusters freed"); 6651 #endif 6652 6653 } 6654 } 6655 6656 } 6657 6658 void 6659 iflib_request_reset(if_ctx_t ctx) 6660 { 6661 6662 STATE_LOCK(ctx); 6663 ctx->ifc_flags |= IFC_DO_RESET; 6664 STATE_UNLOCK(ctx); 6665 } 6666 6667 #ifndef __NO_STRICT_ALIGNMENT 6668 static struct mbuf * 6669 iflib_fixup_rx(struct mbuf *m) 6670 { 6671 struct mbuf *n; 6672 6673 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6674 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6675 m->m_data += ETHER_HDR_LEN; 6676 n = m; 6677 } else { 6678 MGETHDR(n, M_NOWAIT, MT_DATA); 6679 if (n == NULL) { 6680 m_freem(m); 6681 return (NULL); 6682 } 6683 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6684 m->m_data += ETHER_HDR_LEN; 6685 m->m_len -= ETHER_HDR_LEN; 6686 n->m_len = ETHER_HDR_LEN; 6687 M_MOVE_PKTHDR(n, m); 6688 n->m_next = m; 6689 } 6690 return (n); 6691 } 6692 #endif 6693 6694 #ifdef NETDUMP 6695 static void 6696 iflib_netdump_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 6697 { 6698 if_ctx_t ctx; 6699 6700 ctx = if_getsoftc(ifp); 6701 CTX_LOCK(ctx); 6702 *nrxr = NRXQSETS(ctx); 6703 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6704 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6705 CTX_UNLOCK(ctx); 6706 } 6707 6708 static void 6709 iflib_netdump_event(if_t ifp, enum netdump_ev event) 6710 { 6711 if_ctx_t ctx; 6712 if_softc_ctx_t scctx; 6713 iflib_fl_t fl; 6714 iflib_rxq_t rxq; 6715 int i, j; 6716 6717 ctx = if_getsoftc(ifp); 6718 scctx = &ctx->ifc_softc_ctx; 6719 6720 switch (event) { 6721 case NETDUMP_START: 6722 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6723 rxq = &ctx->ifc_rxqs[i]; 6724 for (j = 0; j < rxq->ifr_nfl; j++) { 6725 fl = rxq->ifr_fl; 6726 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6727 } 6728 } 6729 iflib_no_tx_batch = 1; 6730 break; 6731 default: 6732 break; 6733 } 6734 } 6735 6736 static int 6737 iflib_netdump_transmit(if_t ifp, struct mbuf *m) 6738 { 6739 if_ctx_t ctx; 6740 iflib_txq_t txq; 6741 int error; 6742 6743 ctx = if_getsoftc(ifp); 6744 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6745 IFF_DRV_RUNNING) 6746 return (EBUSY); 6747 6748 txq = &ctx->ifc_txqs[0]; 6749 error = iflib_encap(txq, &m); 6750 if (error == 0) 6751 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6752 return (error); 6753 } 6754 6755 static int 6756 iflib_netdump_poll(if_t ifp, int count) 6757 { 6758 if_ctx_t ctx; 6759 if_softc_ctx_t scctx; 6760 iflib_txq_t txq; 6761 int i; 6762 6763 ctx = if_getsoftc(ifp); 6764 scctx = &ctx->ifc_softc_ctx; 6765 6766 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6767 IFF_DRV_RUNNING) 6768 return (EBUSY); 6769 6770 txq = &ctx->ifc_txqs[0]; 6771 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6772 6773 for (i = 0; i < scctx->isc_nrxqsets; i++) 6774 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6775 return (0); 6776 } 6777 #endif /* NETDUMP */ 6778