1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/vnet.h> 63 64 #include <netinet/in.h> 65 #include <netinet/in_pcb.h> 66 #include <netinet/tcp_lro.h> 67 #include <netinet/in_systm.h> 68 #include <netinet/if_ether.h> 69 #include <netinet/ip.h> 70 #include <netinet/ip6.h> 71 #include <netinet/tcp.h> 72 #include <netinet/ip_var.h> 73 #include <netinet/netdump/netdump.h> 74 #include <netinet6/ip6_var.h> 75 76 #include <machine/bus.h> 77 #include <machine/in_cksum.h> 78 79 #include <vm/vm.h> 80 #include <vm/pmap.h> 81 82 #include <dev/led/led.h> 83 #include <dev/pci/pcireg.h> 84 #include <dev/pci/pcivar.h> 85 #include <dev/pci/pci_private.h> 86 87 #include <net/iflib.h> 88 #include <net/iflib_private.h> 89 90 #include "ifdi_if.h" 91 92 #ifdef PCI_IOV 93 #include <dev/pci/pci_iov.h> 94 #endif 95 96 #include <sys/bitstring.h> 97 /* 98 * enable accounting of every mbuf as it comes in to and goes out of 99 * iflib's software descriptor references 100 */ 101 #define MEMORY_LOGGING 0 102 /* 103 * Enable mbuf vectors for compressing long mbuf chains 104 */ 105 106 /* 107 * NB: 108 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 109 * we prefetch needs to be determined by the time spent in m_free vis a vis 110 * the cost of a prefetch. This will of course vary based on the workload: 111 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 112 * is quite expensive, thus suggesting very little prefetch. 113 * - small packet forwarding which is just returning a single mbuf to 114 * UMA will typically be very fast vis a vis the cost of a memory 115 * access. 116 */ 117 118 119 /* 120 * File organization: 121 * - private structures 122 * - iflib private utility functions 123 * - ifnet functions 124 * - vlan registry and other exported functions 125 * - iflib public core functions 126 * 127 * 128 */ 129 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 130 131 struct iflib_txq; 132 typedef struct iflib_txq *iflib_txq_t; 133 struct iflib_rxq; 134 typedef struct iflib_rxq *iflib_rxq_t; 135 struct iflib_fl; 136 typedef struct iflib_fl *iflib_fl_t; 137 138 struct iflib_ctx; 139 140 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 141 static void iflib_timer(void *arg); 142 143 typedef struct iflib_filter_info { 144 driver_filter_t *ifi_filter; 145 void *ifi_filter_arg; 146 struct grouptask *ifi_task; 147 void *ifi_ctx; 148 } *iflib_filter_info_t; 149 150 struct iflib_ctx { 151 KOBJ_FIELDS; 152 /* 153 * Pointer to hardware driver's softc 154 */ 155 void *ifc_softc; 156 device_t ifc_dev; 157 if_t ifc_ifp; 158 159 cpuset_t ifc_cpus; 160 if_shared_ctx_t ifc_sctx; 161 struct if_softc_ctx ifc_softc_ctx; 162 163 struct sx ifc_ctx_sx; 164 struct mtx ifc_state_mtx; 165 166 iflib_txq_t ifc_txqs; 167 iflib_rxq_t ifc_rxqs; 168 uint32_t ifc_if_flags; 169 uint32_t ifc_flags; 170 uint32_t ifc_max_fl_buf_size; 171 uint32_t ifc_rx_mbuf_sz; 172 173 int ifc_link_state; 174 int ifc_link_irq; 175 int ifc_watchdog_events; 176 struct cdev *ifc_led_dev; 177 struct resource *ifc_msix_mem; 178 179 struct if_irq ifc_legacy_irq; 180 struct grouptask ifc_admin_task; 181 struct grouptask ifc_vflr_task; 182 struct iflib_filter_info ifc_filter_info; 183 struct ifmedia ifc_media; 184 185 struct sysctl_oid *ifc_sysctl_node; 186 uint16_t ifc_sysctl_ntxqs; 187 uint16_t ifc_sysctl_nrxqs; 188 uint16_t ifc_sysctl_qs_eq_override; 189 uint16_t ifc_sysctl_rx_budget; 190 uint16_t ifc_sysctl_tx_abdicate; 191 192 qidx_t ifc_sysctl_ntxds[8]; 193 qidx_t ifc_sysctl_nrxds[8]; 194 struct if_txrx ifc_txrx; 195 #define isc_txd_encap ifc_txrx.ift_txd_encap 196 #define isc_txd_flush ifc_txrx.ift_txd_flush 197 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 198 #define isc_rxd_available ifc_txrx.ift_rxd_available 199 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 200 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 201 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 202 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 203 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 204 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 205 eventhandler_tag ifc_vlan_attach_event; 206 eventhandler_tag ifc_vlan_detach_event; 207 struct ether_addr ifc_mac; 208 char ifc_mtx_name[16]; 209 }; 210 211 212 void * 213 iflib_get_softc(if_ctx_t ctx) 214 { 215 216 return (ctx->ifc_softc); 217 } 218 219 device_t 220 iflib_get_dev(if_ctx_t ctx) 221 { 222 223 return (ctx->ifc_dev); 224 } 225 226 if_t 227 iflib_get_ifp(if_ctx_t ctx) 228 { 229 230 return (ctx->ifc_ifp); 231 } 232 233 struct ifmedia * 234 iflib_get_media(if_ctx_t ctx) 235 { 236 237 return (&ctx->ifc_media); 238 } 239 240 uint32_t 241 iflib_get_flags(if_ctx_t ctx) 242 { 243 return (ctx->ifc_flags); 244 } 245 246 void 247 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 248 { 249 250 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 251 } 252 253 if_softc_ctx_t 254 iflib_get_softc_ctx(if_ctx_t ctx) 255 { 256 257 return (&ctx->ifc_softc_ctx); 258 } 259 260 if_shared_ctx_t 261 iflib_get_sctx(if_ctx_t ctx) 262 { 263 264 return (ctx->ifc_sctx); 265 } 266 267 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 268 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 269 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 270 271 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 272 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 273 274 typedef struct iflib_sw_rx_desc_array { 275 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 276 struct mbuf **ifsd_m; /* pkthdr mbufs */ 277 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 278 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 279 } iflib_rxsd_array_t; 280 281 typedef struct iflib_sw_tx_desc_array { 282 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 283 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 284 struct mbuf **ifsd_m; /* pkthdr mbufs */ 285 } if_txsd_vec_t; 286 287 288 /* magic number that should be high enough for any hardware */ 289 #define IFLIB_MAX_TX_SEGS 128 290 #define IFLIB_RX_COPY_THRESH 128 291 #define IFLIB_MAX_RX_REFRESH 32 292 /* The minimum descriptors per second before we start coalescing */ 293 #define IFLIB_MIN_DESC_SEC 16384 294 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 295 #define IFLIB_QUEUE_IDLE 0 296 #define IFLIB_QUEUE_HUNG 1 297 #define IFLIB_QUEUE_WORKING 2 298 /* maximum number of txqs that can share an rx interrupt */ 299 #define IFLIB_MAX_TX_SHARED_INTR 4 300 301 /* this should really scale with ring size - this is a fairly arbitrary value */ 302 #define TX_BATCH_SIZE 32 303 304 #define IFLIB_RESTART_BUDGET 8 305 306 307 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 308 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 309 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 310 struct iflib_txq { 311 qidx_t ift_in_use; 312 qidx_t ift_cidx; 313 qidx_t ift_cidx_processed; 314 qidx_t ift_pidx; 315 uint8_t ift_gen; 316 uint8_t ift_br_offset; 317 uint16_t ift_npending; 318 uint16_t ift_db_pending; 319 uint16_t ift_rs_pending; 320 /* implicit pad */ 321 uint8_t ift_txd_size[8]; 322 uint64_t ift_processed; 323 uint64_t ift_cleaned; 324 uint64_t ift_cleaned_prev; 325 #if MEMORY_LOGGING 326 uint64_t ift_enqueued; 327 uint64_t ift_dequeued; 328 #endif 329 uint64_t ift_no_tx_dma_setup; 330 uint64_t ift_no_desc_avail; 331 uint64_t ift_mbuf_defrag_failed; 332 uint64_t ift_mbuf_defrag; 333 uint64_t ift_map_failed; 334 uint64_t ift_txd_encap_efbig; 335 uint64_t ift_pullups; 336 uint64_t ift_last_timer_tick; 337 338 struct mtx ift_mtx; 339 struct mtx ift_db_mtx; 340 341 /* constant values */ 342 if_ctx_t ift_ctx; 343 struct ifmp_ring *ift_br; 344 struct grouptask ift_task; 345 qidx_t ift_size; 346 uint16_t ift_id; 347 struct callout ift_timer; 348 349 if_txsd_vec_t ift_sds; 350 uint8_t ift_qstatus; 351 uint8_t ift_closed; 352 uint8_t ift_update_freq; 353 struct iflib_filter_info ift_filter_info; 354 bus_dma_tag_t ift_buf_tag; 355 bus_dma_tag_t ift_tso_buf_tag; 356 iflib_dma_info_t ift_ifdi; 357 #define MTX_NAME_LEN 16 358 char ift_mtx_name[MTX_NAME_LEN]; 359 char ift_db_mtx_name[MTX_NAME_LEN]; 360 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 361 #ifdef IFLIB_DIAGNOSTICS 362 uint64_t ift_cpu_exec_count[256]; 363 #endif 364 } __aligned(CACHE_LINE_SIZE); 365 366 struct iflib_fl { 367 qidx_t ifl_cidx; 368 qidx_t ifl_pidx; 369 qidx_t ifl_credits; 370 uint8_t ifl_gen; 371 uint8_t ifl_rxd_size; 372 #if MEMORY_LOGGING 373 uint64_t ifl_m_enqueued; 374 uint64_t ifl_m_dequeued; 375 uint64_t ifl_cl_enqueued; 376 uint64_t ifl_cl_dequeued; 377 #endif 378 /* implicit pad */ 379 380 bitstr_t *ifl_rx_bitmap; 381 qidx_t ifl_fragidx; 382 /* constant */ 383 qidx_t ifl_size; 384 uint16_t ifl_buf_size; 385 uint16_t ifl_cltype; 386 uma_zone_t ifl_zone; 387 iflib_rxsd_array_t ifl_sds; 388 iflib_rxq_t ifl_rxq; 389 uint8_t ifl_id; 390 bus_dma_tag_t ifl_buf_tag; 391 iflib_dma_info_t ifl_ifdi; 392 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 393 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 394 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 395 } __aligned(CACHE_LINE_SIZE); 396 397 static inline qidx_t 398 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 399 { 400 qidx_t used; 401 402 if (pidx > cidx) 403 used = pidx - cidx; 404 else if (pidx < cidx) 405 used = size - cidx + pidx; 406 else if (gen == 0 && pidx == cidx) 407 used = 0; 408 else if (gen == 1 && pidx == cidx) 409 used = size; 410 else 411 panic("bad state"); 412 413 return (used); 414 } 415 416 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 417 418 #define IDXDIFF(head, tail, wrap) \ 419 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 420 421 struct iflib_rxq { 422 /* If there is a separate completion queue - 423 * these are the cq cidx and pidx. Otherwise 424 * these are unused. 425 */ 426 qidx_t ifr_size; 427 qidx_t ifr_cq_cidx; 428 qidx_t ifr_cq_pidx; 429 uint8_t ifr_cq_gen; 430 uint8_t ifr_fl_offset; 431 432 if_ctx_t ifr_ctx; 433 iflib_fl_t ifr_fl; 434 uint64_t ifr_rx_irq; 435 uint16_t ifr_id; 436 uint8_t ifr_lro_enabled; 437 uint8_t ifr_nfl; 438 uint8_t ifr_ntxqirq; 439 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 440 struct lro_ctrl ifr_lc; 441 struct grouptask ifr_task; 442 struct iflib_filter_info ifr_filter_info; 443 iflib_dma_info_t ifr_ifdi; 444 445 /* dynamically allocate if any drivers need a value substantially larger than this */ 446 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 447 #ifdef IFLIB_DIAGNOSTICS 448 uint64_t ifr_cpu_exec_count[256]; 449 #endif 450 } __aligned(CACHE_LINE_SIZE); 451 452 typedef struct if_rxsd { 453 caddr_t *ifsd_cl; 454 struct mbuf **ifsd_m; 455 iflib_fl_t ifsd_fl; 456 qidx_t ifsd_cidx; 457 } *if_rxsd_t; 458 459 /* multiple of word size */ 460 #ifdef __LP64__ 461 #define PKT_INFO_SIZE 6 462 #define RXD_INFO_SIZE 5 463 #define PKT_TYPE uint64_t 464 #else 465 #define PKT_INFO_SIZE 11 466 #define RXD_INFO_SIZE 8 467 #define PKT_TYPE uint32_t 468 #endif 469 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 470 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 471 472 typedef struct if_pkt_info_pad { 473 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 474 } *if_pkt_info_pad_t; 475 typedef struct if_rxd_info_pad { 476 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 477 } *if_rxd_info_pad_t; 478 479 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 480 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 481 482 483 static inline void 484 pkt_info_zero(if_pkt_info_t pi) 485 { 486 if_pkt_info_pad_t pi_pad; 487 488 pi_pad = (if_pkt_info_pad_t)pi; 489 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 490 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 491 #ifndef __LP64__ 492 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 493 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 494 #endif 495 } 496 497 static device_method_t iflib_pseudo_methods[] = { 498 DEVMETHOD(device_attach, noop_attach), 499 DEVMETHOD(device_detach, iflib_pseudo_detach), 500 DEVMETHOD_END 501 }; 502 503 driver_t iflib_pseudodriver = { 504 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 505 }; 506 507 static inline void 508 rxd_info_zero(if_rxd_info_t ri) 509 { 510 if_rxd_info_pad_t ri_pad; 511 int i; 512 513 ri_pad = (if_rxd_info_pad_t)ri; 514 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 515 ri_pad->rxd_val[i] = 0; 516 ri_pad->rxd_val[i+1] = 0; 517 ri_pad->rxd_val[i+2] = 0; 518 ri_pad->rxd_val[i+3] = 0; 519 } 520 #ifdef __LP64__ 521 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 522 #endif 523 } 524 525 /* 526 * Only allow a single packet to take up most 1/nth of the tx ring 527 */ 528 #define MAX_SINGLE_PACKET_FRACTION 12 529 #define IF_BAD_DMA (bus_addr_t)-1 530 531 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 532 533 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 534 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 535 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 536 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 537 538 539 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 540 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 541 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 542 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 543 544 545 546 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 547 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 548 549 void 550 iflib_set_detach(if_ctx_t ctx) 551 { 552 STATE_LOCK(ctx); 553 ctx->ifc_flags |= IFC_IN_DETACH; 554 STATE_UNLOCK(ctx); 555 } 556 557 /* Our boot-time initialization hook */ 558 static int iflib_module_event_handler(module_t, int, void *); 559 560 static moduledata_t iflib_moduledata = { 561 "iflib", 562 iflib_module_event_handler, 563 NULL 564 }; 565 566 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 567 MODULE_VERSION(iflib, 1); 568 569 MODULE_DEPEND(iflib, pci, 1, 1, 1); 570 MODULE_DEPEND(iflib, ether, 1, 1, 1); 571 572 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 573 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 574 575 #ifndef IFLIB_DEBUG_COUNTERS 576 #ifdef INVARIANTS 577 #define IFLIB_DEBUG_COUNTERS 1 578 #else 579 #define IFLIB_DEBUG_COUNTERS 0 580 #endif /* !INVARIANTS */ 581 #endif 582 583 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 584 "iflib driver parameters"); 585 586 /* 587 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 588 */ 589 static int iflib_min_tx_latency = 0; 590 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 591 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 592 static int iflib_no_tx_batch = 0; 593 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 594 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 595 596 597 #if IFLIB_DEBUG_COUNTERS 598 599 static int iflib_tx_seen; 600 static int iflib_tx_sent; 601 static int iflib_tx_encap; 602 static int iflib_rx_allocs; 603 static int iflib_fl_refills; 604 static int iflib_fl_refills_large; 605 static int iflib_tx_frees; 606 607 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 608 &iflib_tx_seen, 0, "# tx mbufs seen"); 609 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 610 &iflib_tx_sent, 0, "# tx mbufs sent"); 611 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 612 &iflib_tx_encap, 0, "# tx mbufs encapped"); 613 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 614 &iflib_tx_frees, 0, "# tx frees"); 615 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 616 &iflib_rx_allocs, 0, "# rx allocations"); 617 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 618 &iflib_fl_refills, 0, "# refills"); 619 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 620 &iflib_fl_refills_large, 0, "# large refills"); 621 622 623 static int iflib_txq_drain_flushing; 624 static int iflib_txq_drain_oactive; 625 static int iflib_txq_drain_notready; 626 627 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 628 &iflib_txq_drain_flushing, 0, "# drain flushes"); 629 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 630 &iflib_txq_drain_oactive, 0, "# drain oactives"); 631 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 632 &iflib_txq_drain_notready, 0, "# drain notready"); 633 634 635 static int iflib_encap_load_mbuf_fail; 636 static int iflib_encap_pad_mbuf_fail; 637 static int iflib_encap_txq_avail_fail; 638 static int iflib_encap_txd_encap_fail; 639 640 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 641 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 642 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 643 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 644 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 645 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 646 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 647 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 648 649 static int iflib_task_fn_rxs; 650 static int iflib_rx_intr_enables; 651 static int iflib_fast_intrs; 652 static int iflib_rx_unavail; 653 static int iflib_rx_ctx_inactive; 654 static int iflib_rx_if_input; 655 static int iflib_rx_mbuf_null; 656 static int iflib_rxd_flush; 657 658 static int iflib_verbose_debug; 659 660 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 661 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 663 &iflib_rx_intr_enables, 0, "# rx intr enables"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 665 &iflib_fast_intrs, 0, "# fast_intr calls"); 666 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 667 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 668 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 669 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 670 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 671 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 672 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 673 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 674 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 675 &iflib_rxd_flush, 0, "# times rxd_flush called"); 676 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 677 &iflib_verbose_debug, 0, "enable verbose debugging"); 678 679 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 680 static void 681 iflib_debug_reset(void) 682 { 683 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 684 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 685 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 686 iflib_txq_drain_notready = 687 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 688 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 689 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 690 iflib_rx_unavail = 691 iflib_rx_ctx_inactive = iflib_rx_if_input = 692 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 693 } 694 695 #else 696 #define DBG_COUNTER_INC(name) 697 static void iflib_debug_reset(void) {} 698 #endif 699 700 #define IFLIB_DEBUG 0 701 702 static void iflib_tx_structures_free(if_ctx_t ctx); 703 static void iflib_rx_structures_free(if_ctx_t ctx); 704 static int iflib_queues_alloc(if_ctx_t ctx); 705 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 706 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 707 static int iflib_qset_structures_setup(if_ctx_t ctx); 708 static int iflib_msix_init(if_ctx_t ctx); 709 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 710 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 711 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 712 #ifdef ALTQ 713 static void iflib_altq_if_start(if_t ifp); 714 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 715 #endif 716 static int iflib_register(if_ctx_t); 717 static void iflib_init_locked(if_ctx_t ctx); 718 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 719 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 720 static void iflib_ifmp_purge(iflib_txq_t txq); 721 static void _iflib_pre_assert(if_softc_ctx_t scctx); 722 static void iflib_if_init_locked(if_ctx_t ctx); 723 static void iflib_free_intr_mem(if_ctx_t ctx); 724 #ifndef __NO_STRICT_ALIGNMENT 725 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 726 #endif 727 728 NETDUMP_DEFINE(iflib); 729 730 #ifdef DEV_NETMAP 731 #include <sys/selinfo.h> 732 #include <net/netmap.h> 733 #include <dev/netmap/netmap_kern.h> 734 735 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 736 737 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 738 739 /* 740 * device-specific sysctl variables: 741 * 742 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 743 * During regular operations the CRC is stripped, but on some 744 * hardware reception of frames not multiple of 64 is slower, 745 * so using crcstrip=0 helps in benchmarks. 746 * 747 * iflib_rx_miss, iflib_rx_miss_bufs: 748 * count packets that might be missed due to lost interrupts. 749 */ 750 SYSCTL_DECL(_dev_netmap); 751 /* 752 * The xl driver by default strips CRCs and we do not override it. 753 */ 754 755 int iflib_crcstrip = 1; 756 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 757 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 758 759 int iflib_rx_miss, iflib_rx_miss_bufs; 760 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 761 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 763 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 764 765 /* 766 * Register/unregister. We are already under netmap lock. 767 * Only called on the first register or the last unregister. 768 */ 769 static int 770 iflib_netmap_register(struct netmap_adapter *na, int onoff) 771 { 772 struct ifnet *ifp = na->ifp; 773 if_ctx_t ctx = ifp->if_softc; 774 int status; 775 776 CTX_LOCK(ctx); 777 IFDI_INTR_DISABLE(ctx); 778 779 /* Tell the stack that the interface is no longer active */ 780 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 781 782 if (!CTX_IS_VF(ctx)) 783 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 784 785 /* enable or disable flags and callbacks in na and ifp */ 786 if (onoff) { 787 nm_set_native_flags(na); 788 } else { 789 nm_clear_native_flags(na); 790 } 791 iflib_stop(ctx); 792 iflib_init_locked(ctx); 793 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 794 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 795 if (status) 796 nm_clear_native_flags(na); 797 CTX_UNLOCK(ctx); 798 return (status); 799 } 800 801 static int 802 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 803 { 804 struct netmap_adapter *na = kring->na; 805 u_int const lim = kring->nkr_num_slots - 1; 806 u_int head = kring->rhead; 807 struct netmap_ring *ring = kring->ring; 808 bus_dmamap_t *map; 809 struct if_rxd_update iru; 810 if_ctx_t ctx = rxq->ifr_ctx; 811 iflib_fl_t fl = &rxq->ifr_fl[0]; 812 uint32_t refill_pidx, nic_i; 813 #if IFLIB_DEBUG_COUNTERS 814 int rf_count = 0; 815 #endif 816 817 if (nm_i == head && __predict_true(!init)) 818 return 0; 819 iru_init(&iru, rxq, 0 /* flid */); 820 map = fl->ifl_sds.ifsd_map; 821 refill_pidx = netmap_idx_k2n(kring, nm_i); 822 /* 823 * IMPORTANT: we must leave one free slot in the ring, 824 * so move head back by one unit 825 */ 826 head = nm_prev(head, lim); 827 nic_i = UINT_MAX; 828 DBG_COUNTER_INC(fl_refills); 829 while (nm_i != head) { 830 #if IFLIB_DEBUG_COUNTERS 831 if (++rf_count == 9) 832 DBG_COUNTER_INC(fl_refills_large); 833 #endif 834 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 835 struct netmap_slot *slot = &ring->slot[nm_i]; 836 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 837 uint32_t nic_i_dma = refill_pidx; 838 nic_i = netmap_idx_k2n(kring, nm_i); 839 840 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 841 842 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 843 return netmap_ring_reinit(kring); 844 845 fl->ifl_vm_addrs[tmp_pidx] = addr; 846 if (__predict_false(init)) { 847 netmap_load_map(na, fl->ifl_buf_tag, 848 map[nic_i], addr); 849 } else if (slot->flags & NS_BUF_CHANGED) { 850 /* buffer has changed, reload map */ 851 netmap_reload_map(na, fl->ifl_buf_tag, 852 map[nic_i], addr); 853 } 854 slot->flags &= ~NS_BUF_CHANGED; 855 856 nm_i = nm_next(nm_i, lim); 857 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 858 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 859 continue; 860 861 iru.iru_pidx = refill_pidx; 862 iru.iru_count = tmp_pidx+1; 863 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 864 refill_pidx = nic_i; 865 for (int n = 0; n < iru.iru_count; n++) { 866 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma], 867 BUS_DMASYNC_PREREAD); 868 /* XXX - change this to not use the netmap func*/ 869 nic_i_dma = nm_next(nic_i_dma, lim); 870 } 871 } 872 } 873 kring->nr_hwcur = head; 874 875 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 876 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 877 if (__predict_true(nic_i != UINT_MAX)) { 878 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 879 DBG_COUNTER_INC(rxd_flush); 880 } 881 return (0); 882 } 883 884 /* 885 * Reconcile kernel and user view of the transmit ring. 886 * 887 * All information is in the kring. 888 * Userspace wants to send packets up to the one before kring->rhead, 889 * kernel knows kring->nr_hwcur is the first unsent packet. 890 * 891 * Here we push packets out (as many as possible), and possibly 892 * reclaim buffers from previously completed transmission. 893 * 894 * The caller (netmap) guarantees that there is only one instance 895 * running at any time. Any interference with other driver 896 * methods should be handled by the individual drivers. 897 */ 898 static int 899 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 900 { 901 struct netmap_adapter *na = kring->na; 902 struct ifnet *ifp = na->ifp; 903 struct netmap_ring *ring = kring->ring; 904 u_int nm_i; /* index into the netmap kring */ 905 u_int nic_i; /* index into the NIC ring */ 906 u_int n; 907 u_int const lim = kring->nkr_num_slots - 1; 908 u_int const head = kring->rhead; 909 struct if_pkt_info pi; 910 911 /* 912 * interrupts on every tx packet are expensive so request 913 * them every half ring, or where NS_REPORT is set 914 */ 915 u_int report_frequency = kring->nkr_num_slots >> 1; 916 /* device-specific */ 917 if_ctx_t ctx = ifp->if_softc; 918 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 919 920 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 921 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 922 923 /* 924 * First part: process new packets to send. 925 * nm_i is the current index in the netmap kring, 926 * nic_i is the corresponding index in the NIC ring. 927 * 928 * If we have packets to send (nm_i != head) 929 * iterate over the netmap ring, fetch length and update 930 * the corresponding slot in the NIC ring. Some drivers also 931 * need to update the buffer's physical address in the NIC slot 932 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 933 * 934 * The netmap_reload_map() calls is especially expensive, 935 * even when (as in this case) the tag is 0, so do only 936 * when the buffer has actually changed. 937 * 938 * If possible do not set the report/intr bit on all slots, 939 * but only a few times per ring or when NS_REPORT is set. 940 * 941 * Finally, on 10G and faster drivers, it might be useful 942 * to prefetch the next slot and txr entry. 943 */ 944 945 nm_i = kring->nr_hwcur; 946 if (nm_i != head) { /* we have new packets to send */ 947 pkt_info_zero(&pi); 948 pi.ipi_segs = txq->ift_segs; 949 pi.ipi_qsidx = kring->ring_id; 950 nic_i = netmap_idx_k2n(kring, nm_i); 951 952 __builtin_prefetch(&ring->slot[nm_i]); 953 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 954 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 955 956 for (n = 0; nm_i != head; n++) { 957 struct netmap_slot *slot = &ring->slot[nm_i]; 958 u_int len = slot->len; 959 uint64_t paddr; 960 void *addr = PNMB(na, slot, &paddr); 961 int flags = (slot->flags & NS_REPORT || 962 nic_i == 0 || nic_i == report_frequency) ? 963 IPI_TX_INTR : 0; 964 965 /* device-specific */ 966 pi.ipi_len = len; 967 pi.ipi_segs[0].ds_addr = paddr; 968 pi.ipi_segs[0].ds_len = len; 969 pi.ipi_nsegs = 1; 970 pi.ipi_ndescs = 0; 971 pi.ipi_pidx = nic_i; 972 pi.ipi_flags = flags; 973 974 /* Fill the slot in the NIC ring. */ 975 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 976 DBG_COUNTER_INC(tx_encap); 977 978 /* prefetch for next round */ 979 __builtin_prefetch(&ring->slot[nm_i + 1]); 980 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 981 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 982 983 NM_CHECK_ADDR_LEN(na, addr, len); 984 985 if (slot->flags & NS_BUF_CHANGED) { 986 /* buffer has changed, reload map */ 987 netmap_reload_map(na, txq->ift_buf_tag, 988 txq->ift_sds.ifsd_map[nic_i], addr); 989 } 990 /* make sure changes to the buffer are synced */ 991 bus_dmamap_sync(txq->ift_buf_tag, 992 txq->ift_sds.ifsd_map[nic_i], 993 BUS_DMASYNC_PREWRITE); 994 995 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 996 nm_i = nm_next(nm_i, lim); 997 nic_i = nm_next(nic_i, lim); 998 } 999 kring->nr_hwcur = nm_i; 1000 1001 /* synchronize the NIC ring */ 1002 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1003 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1004 1005 /* (re)start the tx unit up to slot nic_i (excluded) */ 1006 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1007 } 1008 1009 /* 1010 * Second part: reclaim buffers for completed transmissions. 1011 * 1012 * If there are unclaimed buffers, attempt to reclaim them. 1013 * If none are reclaimed, and TX IRQs are not in use, do an initial 1014 * minimal delay, then trigger the tx handler which will spin in the 1015 * group task queue. 1016 */ 1017 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1018 if (iflib_tx_credits_update(ctx, txq)) { 1019 /* some tx completed, increment avail */ 1020 nic_i = txq->ift_cidx_processed; 1021 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1022 } 1023 } 1024 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1025 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1026 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000, 1027 iflib_timer, txq, txq->ift_timer.c_cpu); 1028 } 1029 return (0); 1030 } 1031 1032 /* 1033 * Reconcile kernel and user view of the receive ring. 1034 * Same as for the txsync, this routine must be efficient. 1035 * The caller guarantees a single invocations, but races against 1036 * the rest of the driver should be handled here. 1037 * 1038 * On call, kring->rhead is the first packet that userspace wants 1039 * to keep, and kring->rcur is the wakeup point. 1040 * The kernel has previously reported packets up to kring->rtail. 1041 * 1042 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1043 * of whether or not we received an interrupt. 1044 */ 1045 static int 1046 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1047 { 1048 struct netmap_adapter *na = kring->na; 1049 struct netmap_ring *ring = kring->ring; 1050 iflib_fl_t fl; 1051 uint32_t nm_i; /* index into the netmap ring */ 1052 uint32_t nic_i; /* index into the NIC ring */ 1053 u_int i, n; 1054 u_int const lim = kring->nkr_num_slots - 1; 1055 u_int const head = kring->rhead; 1056 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1057 struct if_rxd_info ri; 1058 1059 struct ifnet *ifp = na->ifp; 1060 if_ctx_t ctx = ifp->if_softc; 1061 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1062 if (head > lim) 1063 return netmap_ring_reinit(kring); 1064 1065 /* 1066 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far. 1067 */ 1068 1069 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1070 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1071 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1072 } 1073 1074 /* 1075 * First part: import newly received packets. 1076 * 1077 * nm_i is the index of the next free slot in the netmap ring, 1078 * nic_i is the index of the next received packet in the NIC ring, 1079 * and they may differ in case if_init() has been called while 1080 * in netmap mode. For the receive ring we have 1081 * 1082 * nic_i = rxr->next_check; 1083 * nm_i = kring->nr_hwtail (previous) 1084 * and 1085 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1086 * 1087 * rxr->next_check is set to 0 on a ring reinit 1088 */ 1089 if (netmap_no_pendintr || force_update) { 1090 int crclen = iflib_crcstrip ? 0 : 4; 1091 int error, avail; 1092 1093 for (i = 0; i < rxq->ifr_nfl; i++) { 1094 fl = &rxq->ifr_fl[i]; 1095 nic_i = fl->ifl_cidx; 1096 nm_i = netmap_idx_n2k(kring, nic_i); 1097 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1098 rxq->ifr_id, nic_i, USHRT_MAX); 1099 for (n = 0; avail > 0; n++, avail--) { 1100 rxd_info_zero(&ri); 1101 ri.iri_frags = rxq->ifr_frags; 1102 ri.iri_qsidx = kring->ring_id; 1103 ri.iri_ifp = ctx->ifc_ifp; 1104 ri.iri_cidx = nic_i; 1105 1106 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1107 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1108 ring->slot[nm_i].flags = 0; 1109 bus_dmamap_sync(fl->ifl_buf_tag, 1110 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1111 nm_i = nm_next(nm_i, lim); 1112 nic_i = nm_next(nic_i, lim); 1113 } 1114 if (n) { /* update the state variables */ 1115 if (netmap_no_pendintr && !force_update) { 1116 /* diagnostics */ 1117 iflib_rx_miss ++; 1118 iflib_rx_miss_bufs += n; 1119 } 1120 fl->ifl_cidx = nic_i; 1121 kring->nr_hwtail = nm_i; 1122 } 1123 kring->nr_kflags &= ~NKR_PENDINTR; 1124 } 1125 } 1126 /* 1127 * Second part: skip past packets that userspace has released. 1128 * (kring->nr_hwcur to head excluded), 1129 * and make the buffers available for reception. 1130 * As usual nm_i is the index in the netmap ring, 1131 * nic_i is the index in the NIC ring, and 1132 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1133 */ 1134 /* XXX not sure how this will work with multiple free lists */ 1135 nm_i = kring->nr_hwcur; 1136 1137 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1138 } 1139 1140 static void 1141 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1142 { 1143 struct ifnet *ifp = na->ifp; 1144 if_ctx_t ctx = ifp->if_softc; 1145 1146 CTX_LOCK(ctx); 1147 if (onoff) { 1148 IFDI_INTR_ENABLE(ctx); 1149 } else { 1150 IFDI_INTR_DISABLE(ctx); 1151 } 1152 CTX_UNLOCK(ctx); 1153 } 1154 1155 1156 static int 1157 iflib_netmap_attach(if_ctx_t ctx) 1158 { 1159 struct netmap_adapter na; 1160 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1161 1162 bzero(&na, sizeof(na)); 1163 1164 na.ifp = ctx->ifc_ifp; 1165 na.na_flags = NAF_BDG_MAYSLEEP; 1166 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1167 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1168 1169 na.num_tx_desc = scctx->isc_ntxd[0]; 1170 na.num_rx_desc = scctx->isc_nrxd[0]; 1171 na.nm_txsync = iflib_netmap_txsync; 1172 na.nm_rxsync = iflib_netmap_rxsync; 1173 na.nm_register = iflib_netmap_register; 1174 na.nm_intr = iflib_netmap_intr; 1175 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1176 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1177 return (netmap_attach(&na)); 1178 } 1179 1180 static void 1181 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1182 { 1183 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1184 struct netmap_slot *slot; 1185 1186 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1187 if (slot == NULL) 1188 return; 1189 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1190 1191 /* 1192 * In netmap mode, set the map for the packet buffer. 1193 * NOTE: Some drivers (not this one) also need to set 1194 * the physical buffer address in the NIC ring. 1195 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1196 * netmap slot index, si 1197 */ 1198 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1199 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1200 NMB(na, slot + si)); 1201 } 1202 } 1203 1204 static void 1205 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1206 { 1207 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1208 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1209 struct netmap_slot *slot; 1210 uint32_t nm_i; 1211 1212 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1213 if (slot == NULL) 1214 return; 1215 nm_i = netmap_idx_n2k(kring, 0); 1216 netmap_fl_refill(rxq, kring, nm_i, true); 1217 } 1218 1219 static void 1220 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on) 1221 { 1222 struct netmap_kring *kring; 1223 uint16_t txqid; 1224 1225 txqid = txq->ift_id; 1226 kring = NA(ctx->ifc_ifp)->tx_rings[txqid]; 1227 1228 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) { 1229 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1230 BUS_DMASYNC_POSTREAD); 1231 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) 1232 netmap_tx_irq(ctx->ifc_ifp, txqid); 1233 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1234 if (hz < 2000) 1235 *reset_on = 1; 1236 else 1237 *reset_on = hz / 1000; 1238 } 1239 } 1240 } 1241 1242 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1243 1244 #else 1245 #define iflib_netmap_txq_init(ctx, txq) 1246 #define iflib_netmap_rxq_init(ctx, rxq) 1247 #define iflib_netmap_detach(ifp) 1248 1249 #define iflib_netmap_attach(ctx) (0) 1250 #define netmap_rx_irq(ifp, qid, budget) (0) 1251 #define netmap_tx_irq(ifp, qid) do {} while (0) 1252 #define iflib_netmap_timer_adjust(ctx, txq, reset_on) 1253 1254 #endif 1255 1256 #if defined(__i386__) || defined(__amd64__) 1257 static __inline void 1258 prefetch(void *x) 1259 { 1260 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1261 } 1262 static __inline void 1263 prefetch2cachelines(void *x) 1264 { 1265 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1266 #if (CACHE_LINE_SIZE < 128) 1267 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1268 #endif 1269 } 1270 #else 1271 #define prefetch(x) 1272 #define prefetch2cachelines(x) 1273 #endif 1274 1275 static void 1276 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1277 { 1278 iflib_fl_t fl; 1279 1280 fl = &rxq->ifr_fl[flid]; 1281 iru->iru_paddrs = fl->ifl_bus_addrs; 1282 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1283 iru->iru_idxs = fl->ifl_rxd_idxs; 1284 iru->iru_qsidx = rxq->ifr_id; 1285 iru->iru_buf_size = fl->ifl_buf_size; 1286 iru->iru_flidx = fl->ifl_id; 1287 } 1288 1289 static void 1290 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1291 { 1292 if (err) 1293 return; 1294 *(bus_addr_t *) arg = segs[0].ds_addr; 1295 } 1296 1297 int 1298 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1299 { 1300 int err; 1301 device_t dev = ctx->ifc_dev; 1302 1303 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1304 align, 0, /* alignment, bounds */ 1305 BUS_SPACE_MAXADDR, /* lowaddr */ 1306 BUS_SPACE_MAXADDR, /* highaddr */ 1307 NULL, NULL, /* filter, filterarg */ 1308 size, /* maxsize */ 1309 1, /* nsegments */ 1310 size, /* maxsegsize */ 1311 BUS_DMA_ALLOCNOW, /* flags */ 1312 NULL, /* lockfunc */ 1313 NULL, /* lockarg */ 1314 &dma->idi_tag); 1315 if (err) { 1316 device_printf(dev, 1317 "%s: bus_dma_tag_create failed: %d\n", 1318 __func__, err); 1319 goto fail_0; 1320 } 1321 1322 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1323 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1324 if (err) { 1325 device_printf(dev, 1326 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1327 __func__, (uintmax_t)size, err); 1328 goto fail_1; 1329 } 1330 1331 dma->idi_paddr = IF_BAD_DMA; 1332 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1333 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1334 if (err || dma->idi_paddr == IF_BAD_DMA) { 1335 device_printf(dev, 1336 "%s: bus_dmamap_load failed: %d\n", 1337 __func__, err); 1338 goto fail_2; 1339 } 1340 1341 dma->idi_size = size; 1342 return (0); 1343 1344 fail_2: 1345 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1346 fail_1: 1347 bus_dma_tag_destroy(dma->idi_tag); 1348 fail_0: 1349 dma->idi_tag = NULL; 1350 1351 return (err); 1352 } 1353 1354 int 1355 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1356 { 1357 if_shared_ctx_t sctx = ctx->ifc_sctx; 1358 1359 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1360 1361 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1362 } 1363 1364 int 1365 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1366 { 1367 int i, err; 1368 iflib_dma_info_t *dmaiter; 1369 1370 dmaiter = dmalist; 1371 for (i = 0; i < count; i++, dmaiter++) { 1372 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1373 break; 1374 } 1375 if (err) 1376 iflib_dma_free_multi(dmalist, i); 1377 return (err); 1378 } 1379 1380 void 1381 iflib_dma_free(iflib_dma_info_t dma) 1382 { 1383 if (dma->idi_tag == NULL) 1384 return; 1385 if (dma->idi_paddr != IF_BAD_DMA) { 1386 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1387 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1388 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1389 dma->idi_paddr = IF_BAD_DMA; 1390 } 1391 if (dma->idi_vaddr != NULL) { 1392 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1393 dma->idi_vaddr = NULL; 1394 } 1395 bus_dma_tag_destroy(dma->idi_tag); 1396 dma->idi_tag = NULL; 1397 } 1398 1399 void 1400 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1401 { 1402 int i; 1403 iflib_dma_info_t *dmaiter = dmalist; 1404 1405 for (i = 0; i < count; i++, dmaiter++) 1406 iflib_dma_free(*dmaiter); 1407 } 1408 1409 #ifdef EARLY_AP_STARTUP 1410 static const int iflib_started = 1; 1411 #else 1412 /* 1413 * We used to abuse the smp_started flag to decide if the queues have been 1414 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1415 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1416 * is set. Run a SYSINIT() strictly after that to just set a usable 1417 * completion flag. 1418 */ 1419 1420 static int iflib_started; 1421 1422 static void 1423 iflib_record_started(void *arg) 1424 { 1425 iflib_started = 1; 1426 } 1427 1428 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1429 iflib_record_started, NULL); 1430 #endif 1431 1432 static int 1433 iflib_fast_intr(void *arg) 1434 { 1435 iflib_filter_info_t info = arg; 1436 struct grouptask *gtask = info->ifi_task; 1437 int result; 1438 1439 if (!iflib_started) 1440 return (FILTER_STRAY); 1441 1442 DBG_COUNTER_INC(fast_intrs); 1443 if (info->ifi_filter != NULL) { 1444 result = info->ifi_filter(info->ifi_filter_arg); 1445 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1446 return (result); 1447 } 1448 1449 GROUPTASK_ENQUEUE(gtask); 1450 return (FILTER_HANDLED); 1451 } 1452 1453 static int 1454 iflib_fast_intr_rxtx(void *arg) 1455 { 1456 iflib_filter_info_t info = arg; 1457 struct grouptask *gtask = info->ifi_task; 1458 if_ctx_t ctx; 1459 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1460 iflib_txq_t txq; 1461 void *sc; 1462 int i, cidx, result; 1463 qidx_t txqid; 1464 1465 if (!iflib_started) 1466 return (FILTER_STRAY); 1467 1468 DBG_COUNTER_INC(fast_intrs); 1469 if (info->ifi_filter != NULL) { 1470 result = info->ifi_filter(info->ifi_filter_arg); 1471 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1472 return (result); 1473 } 1474 1475 ctx = rxq->ifr_ctx; 1476 sc = ctx->ifc_softc; 1477 MPASS(rxq->ifr_ntxqirq); 1478 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1479 txqid = rxq->ifr_txqid[i]; 1480 txq = &ctx->ifc_txqs[txqid]; 1481 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1482 BUS_DMASYNC_POSTREAD); 1483 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1484 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1485 continue; 1486 } 1487 GROUPTASK_ENQUEUE(&txq->ift_task); 1488 } 1489 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1490 cidx = rxq->ifr_cq_cidx; 1491 else 1492 cidx = rxq->ifr_fl[0].ifl_cidx; 1493 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1494 GROUPTASK_ENQUEUE(gtask); 1495 else { 1496 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1497 DBG_COUNTER_INC(rx_intr_enables); 1498 } 1499 return (FILTER_HANDLED); 1500 } 1501 1502 1503 static int 1504 iflib_fast_intr_ctx(void *arg) 1505 { 1506 iflib_filter_info_t info = arg; 1507 struct grouptask *gtask = info->ifi_task; 1508 int result; 1509 1510 if (!iflib_started) 1511 return (FILTER_STRAY); 1512 1513 DBG_COUNTER_INC(fast_intrs); 1514 if (info->ifi_filter != NULL) { 1515 result = info->ifi_filter(info->ifi_filter_arg); 1516 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1517 return (result); 1518 } 1519 1520 GROUPTASK_ENQUEUE(gtask); 1521 return (FILTER_HANDLED); 1522 } 1523 1524 static int 1525 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1526 driver_filter_t filter, driver_intr_t handler, void *arg, 1527 const char *name) 1528 { 1529 int rc, flags; 1530 struct resource *res; 1531 void *tag = NULL; 1532 device_t dev = ctx->ifc_dev; 1533 1534 flags = RF_ACTIVE; 1535 if (ctx->ifc_flags & IFC_LEGACY) 1536 flags |= RF_SHAREABLE; 1537 MPASS(rid < 512); 1538 irq->ii_rid = rid; 1539 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1540 if (res == NULL) { 1541 device_printf(dev, 1542 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1543 return (ENOMEM); 1544 } 1545 irq->ii_res = res; 1546 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1547 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1548 filter, handler, arg, &tag); 1549 if (rc != 0) { 1550 device_printf(dev, 1551 "failed to setup interrupt for rid %d, name %s: %d\n", 1552 rid, name ? name : "unknown", rc); 1553 return (rc); 1554 } else if (name) 1555 bus_describe_intr(dev, res, tag, "%s", name); 1556 1557 irq->ii_tag = tag; 1558 return (0); 1559 } 1560 1561 1562 /********************************************************************* 1563 * 1564 * Allocate DMA resources for TX buffers as well as memory for the TX 1565 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1566 * iflib_sw_tx_desc_array structure, storing all the information that 1567 * is needed to transmit a packet on the wire. This is called only 1568 * once at attach, setup is done every reset. 1569 * 1570 **********************************************************************/ 1571 static int 1572 iflib_txsd_alloc(iflib_txq_t txq) 1573 { 1574 if_ctx_t ctx = txq->ift_ctx; 1575 if_shared_ctx_t sctx = ctx->ifc_sctx; 1576 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1577 device_t dev = ctx->ifc_dev; 1578 bus_size_t tsomaxsize; 1579 int err, nsegments, ntsosegments; 1580 bool tso; 1581 1582 nsegments = scctx->isc_tx_nsegments; 1583 ntsosegments = scctx->isc_tx_tso_segments_max; 1584 tsomaxsize = scctx->isc_tx_tso_size_max; 1585 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1586 tsomaxsize += sizeof(struct ether_vlan_header); 1587 MPASS(scctx->isc_ntxd[0] > 0); 1588 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1589 MPASS(nsegments > 0); 1590 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1591 MPASS(ntsosegments > 0); 1592 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1593 } 1594 1595 /* 1596 * Set up DMA tags for TX buffers. 1597 */ 1598 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1599 1, 0, /* alignment, bounds */ 1600 BUS_SPACE_MAXADDR, /* lowaddr */ 1601 BUS_SPACE_MAXADDR, /* highaddr */ 1602 NULL, NULL, /* filter, filterarg */ 1603 sctx->isc_tx_maxsize, /* maxsize */ 1604 nsegments, /* nsegments */ 1605 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1606 0, /* flags */ 1607 NULL, /* lockfunc */ 1608 NULL, /* lockfuncarg */ 1609 &txq->ift_buf_tag))) { 1610 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1611 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1612 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1613 goto fail; 1614 } 1615 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1616 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1617 1, 0, /* alignment, bounds */ 1618 BUS_SPACE_MAXADDR, /* lowaddr */ 1619 BUS_SPACE_MAXADDR, /* highaddr */ 1620 NULL, NULL, /* filter, filterarg */ 1621 tsomaxsize, /* maxsize */ 1622 ntsosegments, /* nsegments */ 1623 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1624 0, /* flags */ 1625 NULL, /* lockfunc */ 1626 NULL, /* lockfuncarg */ 1627 &txq->ift_tso_buf_tag))) { 1628 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1629 err); 1630 goto fail; 1631 } 1632 1633 /* Allocate memory for the TX mbuf map. */ 1634 if (!(txq->ift_sds.ifsd_m = 1635 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1636 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1637 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1638 err = ENOMEM; 1639 goto fail; 1640 } 1641 1642 /* 1643 * Create the DMA maps for TX buffers. 1644 */ 1645 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1646 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1647 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1648 device_printf(dev, 1649 "Unable to allocate TX buffer DMA map memory\n"); 1650 err = ENOMEM; 1651 goto fail; 1652 } 1653 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1654 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1655 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1656 device_printf(dev, 1657 "Unable to allocate TSO TX buffer map memory\n"); 1658 err = ENOMEM; 1659 goto fail; 1660 } 1661 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1662 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1663 &txq->ift_sds.ifsd_map[i]); 1664 if (err != 0) { 1665 device_printf(dev, "Unable to create TX DMA map\n"); 1666 goto fail; 1667 } 1668 if (!tso) 1669 continue; 1670 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1671 &txq->ift_sds.ifsd_tso_map[i]); 1672 if (err != 0) { 1673 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1674 goto fail; 1675 } 1676 } 1677 return (0); 1678 fail: 1679 /* We free all, it handles case where we are in the middle */ 1680 iflib_tx_structures_free(ctx); 1681 return (err); 1682 } 1683 1684 static void 1685 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1686 { 1687 bus_dmamap_t map; 1688 1689 map = NULL; 1690 if (txq->ift_sds.ifsd_map != NULL) 1691 map = txq->ift_sds.ifsd_map[i]; 1692 if (map != NULL) { 1693 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1694 bus_dmamap_unload(txq->ift_buf_tag, map); 1695 bus_dmamap_destroy(txq->ift_buf_tag, map); 1696 txq->ift_sds.ifsd_map[i] = NULL; 1697 } 1698 1699 map = NULL; 1700 if (txq->ift_sds.ifsd_tso_map != NULL) 1701 map = txq->ift_sds.ifsd_tso_map[i]; 1702 if (map != NULL) { 1703 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1704 BUS_DMASYNC_POSTWRITE); 1705 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1706 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1707 txq->ift_sds.ifsd_tso_map[i] = NULL; 1708 } 1709 } 1710 1711 static void 1712 iflib_txq_destroy(iflib_txq_t txq) 1713 { 1714 if_ctx_t ctx = txq->ift_ctx; 1715 1716 for (int i = 0; i < txq->ift_size; i++) 1717 iflib_txsd_destroy(ctx, txq, i); 1718 if (txq->ift_sds.ifsd_map != NULL) { 1719 free(txq->ift_sds.ifsd_map, M_IFLIB); 1720 txq->ift_sds.ifsd_map = NULL; 1721 } 1722 if (txq->ift_sds.ifsd_tso_map != NULL) { 1723 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1724 txq->ift_sds.ifsd_tso_map = NULL; 1725 } 1726 if (txq->ift_sds.ifsd_m != NULL) { 1727 free(txq->ift_sds.ifsd_m, M_IFLIB); 1728 txq->ift_sds.ifsd_m = NULL; 1729 } 1730 if (txq->ift_buf_tag != NULL) { 1731 bus_dma_tag_destroy(txq->ift_buf_tag); 1732 txq->ift_buf_tag = NULL; 1733 } 1734 if (txq->ift_tso_buf_tag != NULL) { 1735 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1736 txq->ift_tso_buf_tag = NULL; 1737 } 1738 } 1739 1740 static void 1741 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1742 { 1743 struct mbuf **mp; 1744 1745 mp = &txq->ift_sds.ifsd_m[i]; 1746 if (*mp == NULL) 1747 return; 1748 1749 if (txq->ift_sds.ifsd_map != NULL) { 1750 bus_dmamap_sync(txq->ift_buf_tag, 1751 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1752 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1753 } 1754 if (txq->ift_sds.ifsd_tso_map != NULL) { 1755 bus_dmamap_sync(txq->ift_tso_buf_tag, 1756 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1757 bus_dmamap_unload(txq->ift_tso_buf_tag, 1758 txq->ift_sds.ifsd_tso_map[i]); 1759 } 1760 m_free(*mp); 1761 DBG_COUNTER_INC(tx_frees); 1762 *mp = NULL; 1763 } 1764 1765 static int 1766 iflib_txq_setup(iflib_txq_t txq) 1767 { 1768 if_ctx_t ctx = txq->ift_ctx; 1769 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1770 if_shared_ctx_t sctx = ctx->ifc_sctx; 1771 iflib_dma_info_t di; 1772 int i; 1773 1774 /* Set number of descriptors available */ 1775 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1776 /* XXX make configurable */ 1777 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1778 1779 /* Reset indices */ 1780 txq->ift_cidx_processed = 0; 1781 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1782 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1783 1784 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1785 bzero((void *)di->idi_vaddr, di->idi_size); 1786 1787 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1788 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1789 bus_dmamap_sync(di->idi_tag, di->idi_map, 1790 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1791 return (0); 1792 } 1793 1794 /********************************************************************* 1795 * 1796 * Allocate DMA resources for RX buffers as well as memory for the RX 1797 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1798 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1799 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1800 * Since we use use one entry in iflib_sw_rx_desc_array per received 1801 * packet, the maximum number of entries we'll need is equal to the 1802 * number of hardware receive descriptors that we've allocated. 1803 * 1804 **********************************************************************/ 1805 static int 1806 iflib_rxsd_alloc(iflib_rxq_t rxq) 1807 { 1808 if_ctx_t ctx = rxq->ifr_ctx; 1809 if_shared_ctx_t sctx = ctx->ifc_sctx; 1810 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1811 device_t dev = ctx->ifc_dev; 1812 iflib_fl_t fl; 1813 int err; 1814 1815 MPASS(scctx->isc_nrxd[0] > 0); 1816 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1817 1818 fl = rxq->ifr_fl; 1819 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1820 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1821 /* Set up DMA tag for RX buffers. */ 1822 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1823 1, 0, /* alignment, bounds */ 1824 BUS_SPACE_MAXADDR, /* lowaddr */ 1825 BUS_SPACE_MAXADDR, /* highaddr */ 1826 NULL, NULL, /* filter, filterarg */ 1827 sctx->isc_rx_maxsize, /* maxsize */ 1828 sctx->isc_rx_nsegments, /* nsegments */ 1829 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1830 0, /* flags */ 1831 NULL, /* lockfunc */ 1832 NULL, /* lockarg */ 1833 &fl->ifl_buf_tag); 1834 if (err) { 1835 device_printf(dev, 1836 "Unable to allocate RX DMA tag: %d\n", err); 1837 goto fail; 1838 } 1839 1840 /* Allocate memory for the RX mbuf map. */ 1841 if (!(fl->ifl_sds.ifsd_m = 1842 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1843 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1844 device_printf(dev, 1845 "Unable to allocate RX mbuf map memory\n"); 1846 err = ENOMEM; 1847 goto fail; 1848 } 1849 1850 /* Allocate memory for the direct RX cluster pointer map. */ 1851 if (!(fl->ifl_sds.ifsd_cl = 1852 (caddr_t *) malloc(sizeof(caddr_t) * 1853 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1854 device_printf(dev, 1855 "Unable to allocate RX cluster map memory\n"); 1856 err = ENOMEM; 1857 goto fail; 1858 } 1859 1860 /* Allocate memory for the RX cluster bus address map. */ 1861 if (!(fl->ifl_sds.ifsd_ba = 1862 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1863 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1864 device_printf(dev, 1865 "Unable to allocate RX bus address map memory\n"); 1866 err = ENOMEM; 1867 goto fail; 1868 } 1869 1870 /* 1871 * Create the DMA maps for RX buffers. 1872 */ 1873 if (!(fl->ifl_sds.ifsd_map = 1874 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1875 device_printf(dev, 1876 "Unable to allocate RX buffer DMA map memory\n"); 1877 err = ENOMEM; 1878 goto fail; 1879 } 1880 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1881 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 1882 &fl->ifl_sds.ifsd_map[i]); 1883 if (err != 0) { 1884 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1885 goto fail; 1886 } 1887 } 1888 } 1889 return (0); 1890 1891 fail: 1892 iflib_rx_structures_free(ctx); 1893 return (err); 1894 } 1895 1896 1897 /* 1898 * Internal service routines 1899 */ 1900 1901 struct rxq_refill_cb_arg { 1902 int error; 1903 bus_dma_segment_t seg; 1904 int nseg; 1905 }; 1906 1907 static void 1908 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1909 { 1910 struct rxq_refill_cb_arg *cb_arg = arg; 1911 1912 cb_arg->error = error; 1913 cb_arg->seg = segs[0]; 1914 cb_arg->nseg = nseg; 1915 } 1916 1917 /** 1918 * rxq_refill - refill an rxq free-buffer list 1919 * @ctx: the iflib context 1920 * @rxq: the free-list to refill 1921 * @n: the number of new buffers to allocate 1922 * 1923 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1924 * The caller must assure that @n does not exceed the queue's capacity. 1925 */ 1926 static void 1927 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1928 { 1929 struct if_rxd_update iru; 1930 struct rxq_refill_cb_arg cb_arg; 1931 struct mbuf *m; 1932 caddr_t cl, *sd_cl; 1933 struct mbuf **sd_m; 1934 bus_dmamap_t *sd_map; 1935 bus_addr_t bus_addr, *sd_ba; 1936 int err, frag_idx, i, idx, n, pidx; 1937 qidx_t credits; 1938 1939 sd_m = fl->ifl_sds.ifsd_m; 1940 sd_map = fl->ifl_sds.ifsd_map; 1941 sd_cl = fl->ifl_sds.ifsd_cl; 1942 sd_ba = fl->ifl_sds.ifsd_ba; 1943 pidx = fl->ifl_pidx; 1944 idx = pidx; 1945 frag_idx = fl->ifl_fragidx; 1946 credits = fl->ifl_credits; 1947 1948 i = 0; 1949 n = count; 1950 MPASS(n > 0); 1951 MPASS(credits + n <= fl->ifl_size); 1952 1953 if (pidx < fl->ifl_cidx) 1954 MPASS(pidx + n <= fl->ifl_cidx); 1955 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1956 MPASS(fl->ifl_gen == 0); 1957 if (pidx > fl->ifl_cidx) 1958 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1959 1960 DBG_COUNTER_INC(fl_refills); 1961 if (n > 8) 1962 DBG_COUNTER_INC(fl_refills_large); 1963 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1964 while (n--) { 1965 /* 1966 * We allocate an uninitialized mbuf + cluster, mbuf is 1967 * initialized after rx. 1968 * 1969 * If the cluster is still set then we know a minimum sized packet was received 1970 */ 1971 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 1972 &frag_idx); 1973 if (frag_idx < 0) 1974 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1975 MPASS(frag_idx >= 0); 1976 if ((cl = sd_cl[frag_idx]) == NULL) { 1977 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1978 break; 1979 1980 cb_arg.error = 0; 1981 MPASS(sd_map != NULL); 1982 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 1983 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 1984 BUS_DMA_NOWAIT); 1985 if (err != 0 || cb_arg.error) { 1986 /* 1987 * !zone_pack ? 1988 */ 1989 if (fl->ifl_zone == zone_pack) 1990 uma_zfree(fl->ifl_zone, cl); 1991 break; 1992 } 1993 1994 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 1995 sd_cl[frag_idx] = cl; 1996 #if MEMORY_LOGGING 1997 fl->ifl_cl_enqueued++; 1998 #endif 1999 } else { 2000 bus_addr = sd_ba[frag_idx]; 2001 } 2002 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2003 BUS_DMASYNC_PREREAD); 2004 2005 MPASS(sd_m[frag_idx] == NULL); 2006 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 2007 break; 2008 } 2009 sd_m[frag_idx] = m; 2010 bit_set(fl->ifl_rx_bitmap, frag_idx); 2011 #if MEMORY_LOGGING 2012 fl->ifl_m_enqueued++; 2013 #endif 2014 2015 DBG_COUNTER_INC(rx_allocs); 2016 fl->ifl_rxd_idxs[i] = frag_idx; 2017 fl->ifl_bus_addrs[i] = bus_addr; 2018 fl->ifl_vm_addrs[i] = cl; 2019 credits++; 2020 i++; 2021 MPASS(credits <= fl->ifl_size); 2022 if (++idx == fl->ifl_size) { 2023 fl->ifl_gen = 1; 2024 idx = 0; 2025 } 2026 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2027 iru.iru_pidx = pidx; 2028 iru.iru_count = i; 2029 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2030 i = 0; 2031 pidx = idx; 2032 fl->ifl_pidx = idx; 2033 fl->ifl_credits = credits; 2034 } 2035 } 2036 2037 if (i) { 2038 iru.iru_pidx = pidx; 2039 iru.iru_count = i; 2040 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2041 fl->ifl_pidx = idx; 2042 fl->ifl_credits = credits; 2043 } 2044 DBG_COUNTER_INC(rxd_flush); 2045 if (fl->ifl_pidx == 0) 2046 pidx = fl->ifl_size - 1; 2047 else 2048 pidx = fl->ifl_pidx - 1; 2049 2050 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2051 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2052 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 2053 fl->ifl_fragidx = frag_idx; 2054 } 2055 2056 static __inline void 2057 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 2058 { 2059 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2060 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2061 #ifdef INVARIANTS 2062 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2063 #endif 2064 2065 MPASS(fl->ifl_credits <= fl->ifl_size); 2066 MPASS(reclaimable == delta); 2067 2068 if (reclaimable > 0) 2069 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 2070 } 2071 2072 uint8_t 2073 iflib_in_detach(if_ctx_t ctx) 2074 { 2075 bool in_detach; 2076 STATE_LOCK(ctx); 2077 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2078 STATE_UNLOCK(ctx); 2079 return (in_detach); 2080 } 2081 2082 static void 2083 iflib_fl_bufs_free(iflib_fl_t fl) 2084 { 2085 iflib_dma_info_t idi = fl->ifl_ifdi; 2086 bus_dmamap_t sd_map; 2087 uint32_t i; 2088 2089 for (i = 0; i < fl->ifl_size; i++) { 2090 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2091 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2092 2093 if (*sd_cl != NULL) { 2094 sd_map = fl->ifl_sds.ifsd_map[i]; 2095 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2096 BUS_DMASYNC_POSTREAD); 2097 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2098 if (*sd_cl != NULL) 2099 uma_zfree(fl->ifl_zone, *sd_cl); 2100 // XXX: Should this get moved out? 2101 if (iflib_in_detach(fl->ifl_rxq->ifr_ctx)) 2102 bus_dmamap_destroy(fl->ifl_buf_tag, sd_map); 2103 if (*sd_m != NULL) { 2104 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2105 uma_zfree(zone_mbuf, *sd_m); 2106 } 2107 } else { 2108 MPASS(*sd_cl == NULL); 2109 MPASS(*sd_m == NULL); 2110 } 2111 #if MEMORY_LOGGING 2112 fl->ifl_m_dequeued++; 2113 fl->ifl_cl_dequeued++; 2114 #endif 2115 *sd_cl = NULL; 2116 *sd_m = NULL; 2117 } 2118 #ifdef INVARIANTS 2119 for (i = 0; i < fl->ifl_size; i++) { 2120 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2121 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2122 } 2123 #endif 2124 /* 2125 * Reset free list values 2126 */ 2127 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2128 bzero(idi->idi_vaddr, idi->idi_size); 2129 } 2130 2131 /********************************************************************* 2132 * 2133 * Initialize a receive ring and its buffers. 2134 * 2135 **********************************************************************/ 2136 static int 2137 iflib_fl_setup(iflib_fl_t fl) 2138 { 2139 iflib_rxq_t rxq = fl->ifl_rxq; 2140 if_ctx_t ctx = rxq->ifr_ctx; 2141 2142 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2143 /* 2144 ** Free current RX buffer structs and their mbufs 2145 */ 2146 iflib_fl_bufs_free(fl); 2147 /* Now replenish the mbufs */ 2148 MPASS(fl->ifl_credits == 0); 2149 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2150 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2151 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2152 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2153 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2154 2155 2156 /* avoid pre-allocating zillions of clusters to an idle card 2157 * potentially speeding up attach 2158 */ 2159 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2160 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2161 if (min(128, fl->ifl_size) != fl->ifl_credits) 2162 return (ENOBUFS); 2163 /* 2164 * handle failure 2165 */ 2166 MPASS(rxq != NULL); 2167 MPASS(fl->ifl_ifdi != NULL); 2168 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2169 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2170 return (0); 2171 } 2172 2173 /********************************************************************* 2174 * 2175 * Free receive ring data structures 2176 * 2177 **********************************************************************/ 2178 static void 2179 iflib_rx_sds_free(iflib_rxq_t rxq) 2180 { 2181 iflib_fl_t fl; 2182 int i, j; 2183 2184 if (rxq->ifr_fl != NULL) { 2185 for (i = 0; i < rxq->ifr_nfl; i++) { 2186 fl = &rxq->ifr_fl[i]; 2187 if (fl->ifl_buf_tag != NULL) { 2188 if (fl->ifl_sds.ifsd_map != NULL) { 2189 for (j = 0; j < fl->ifl_size; j++) { 2190 if (fl->ifl_sds.ifsd_map[j] == 2191 NULL) 2192 continue; 2193 bus_dmamap_sync( 2194 fl->ifl_buf_tag, 2195 fl->ifl_sds.ifsd_map[j], 2196 BUS_DMASYNC_POSTREAD); 2197 bus_dmamap_unload( 2198 fl->ifl_buf_tag, 2199 fl->ifl_sds.ifsd_map[j]); 2200 } 2201 } 2202 bus_dma_tag_destroy(fl->ifl_buf_tag); 2203 fl->ifl_buf_tag = NULL; 2204 } 2205 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2206 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2207 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2208 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2209 fl->ifl_sds.ifsd_m = NULL; 2210 fl->ifl_sds.ifsd_cl = NULL; 2211 fl->ifl_sds.ifsd_ba = NULL; 2212 fl->ifl_sds.ifsd_map = NULL; 2213 } 2214 free(rxq->ifr_fl, M_IFLIB); 2215 rxq->ifr_fl = NULL; 2216 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2217 } 2218 } 2219 2220 /* 2221 * MI independent logic 2222 * 2223 */ 2224 static void 2225 iflib_timer(void *arg) 2226 { 2227 iflib_txq_t txq = arg; 2228 if_ctx_t ctx = txq->ift_ctx; 2229 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2230 uint64_t this_tick = ticks; 2231 uint32_t reset_on = hz / 2; 2232 2233 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2234 return; 2235 /* 2236 ** Check on the state of the TX queue(s), this 2237 ** can be done without the lock because its RO 2238 ** and the HUNG state will be static if set. 2239 */ 2240 if (this_tick - txq->ift_last_timer_tick >= hz / 2) { 2241 txq->ift_last_timer_tick = this_tick; 2242 IFDI_TIMER(ctx, txq->ift_id); 2243 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2244 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2245 (sctx->isc_pause_frames == 0))) 2246 goto hung; 2247 2248 if (ifmp_ring_is_stalled(txq->ift_br)) 2249 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2250 txq->ift_cleaned_prev = txq->ift_cleaned; 2251 } 2252 #ifdef DEV_NETMAP 2253 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 2254 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 2255 #endif 2256 /* handle any laggards */ 2257 if (txq->ift_db_pending) 2258 GROUPTASK_ENQUEUE(&txq->ift_task); 2259 2260 sctx->isc_pause_frames = 0; 2261 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2262 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 2263 return; 2264 hung: 2265 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2266 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2267 STATE_LOCK(ctx); 2268 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2269 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2270 iflib_admin_intr_deferred(ctx); 2271 STATE_UNLOCK(ctx); 2272 } 2273 2274 static void 2275 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2276 { 2277 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2278 2279 /* 2280 * XXX don't set the max_frame_size to larger 2281 * than the hardware can handle 2282 */ 2283 if (sctx->isc_max_frame_size <= MCLBYTES) 2284 ctx->ifc_rx_mbuf_sz = MCLBYTES; 2285 else 2286 ctx->ifc_rx_mbuf_sz = MJUMPAGESIZE; 2287 } 2288 2289 uint32_t 2290 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2291 { 2292 return (ctx->ifc_rx_mbuf_sz); 2293 } 2294 2295 static void 2296 iflib_init_locked(if_ctx_t ctx) 2297 { 2298 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2299 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2300 if_t ifp = ctx->ifc_ifp; 2301 iflib_fl_t fl; 2302 iflib_txq_t txq; 2303 iflib_rxq_t rxq; 2304 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2305 2306 2307 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2308 IFDI_INTR_DISABLE(ctx); 2309 2310 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2311 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2312 /* Set hardware offload abilities */ 2313 if_clearhwassist(ifp); 2314 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2315 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2316 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2317 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2318 if (if_getcapenable(ifp) & IFCAP_TSO4) 2319 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2320 if (if_getcapenable(ifp) & IFCAP_TSO6) 2321 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2322 2323 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2324 CALLOUT_LOCK(txq); 2325 callout_stop(&txq->ift_timer); 2326 CALLOUT_UNLOCK(txq); 2327 iflib_netmap_txq_init(ctx, txq); 2328 } 2329 2330 /* 2331 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2332 * that drivers can use the value when setting up the hardware receive 2333 * buffers. 2334 */ 2335 iflib_calc_rx_mbuf_sz(ctx); 2336 2337 #ifdef INVARIANTS 2338 i = if_getdrvflags(ifp); 2339 #endif 2340 IFDI_INIT(ctx); 2341 MPASS(if_getdrvflags(ifp) == i); 2342 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2343 /* XXX this should really be done on a per-queue basis */ 2344 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2345 MPASS(rxq->ifr_id == i); 2346 iflib_netmap_rxq_init(ctx, rxq); 2347 continue; 2348 } 2349 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2350 if (iflib_fl_setup(fl)) { 2351 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2352 goto done; 2353 } 2354 } 2355 } 2356 done: 2357 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2358 IFDI_INTR_ENABLE(ctx); 2359 txq = ctx->ifc_txqs; 2360 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2361 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2362 txq->ift_timer.c_cpu); 2363 } 2364 2365 static int 2366 iflib_media_change(if_t ifp) 2367 { 2368 if_ctx_t ctx = if_getsoftc(ifp); 2369 int err; 2370 2371 CTX_LOCK(ctx); 2372 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2373 iflib_init_locked(ctx); 2374 CTX_UNLOCK(ctx); 2375 return (err); 2376 } 2377 2378 static void 2379 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2380 { 2381 if_ctx_t ctx = if_getsoftc(ifp); 2382 2383 CTX_LOCK(ctx); 2384 IFDI_UPDATE_ADMIN_STATUS(ctx); 2385 IFDI_MEDIA_STATUS(ctx, ifmr); 2386 CTX_UNLOCK(ctx); 2387 } 2388 2389 void 2390 iflib_stop(if_ctx_t ctx) 2391 { 2392 iflib_txq_t txq = ctx->ifc_txqs; 2393 iflib_rxq_t rxq = ctx->ifc_rxqs; 2394 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2395 if_shared_ctx_t sctx = ctx->ifc_sctx; 2396 iflib_dma_info_t di; 2397 iflib_fl_t fl; 2398 int i, j; 2399 2400 /* Tell the stack that the interface is no longer active */ 2401 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2402 2403 IFDI_INTR_DISABLE(ctx); 2404 DELAY(1000); 2405 IFDI_STOP(ctx); 2406 DELAY(1000); 2407 2408 iflib_debug_reset(); 2409 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2410 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2411 /* make sure all transmitters have completed before proceeding XXX */ 2412 2413 CALLOUT_LOCK(txq); 2414 callout_stop(&txq->ift_timer); 2415 CALLOUT_UNLOCK(txq); 2416 2417 /* clean any enqueued buffers */ 2418 iflib_ifmp_purge(txq); 2419 /* Free any existing tx buffers. */ 2420 for (j = 0; j < txq->ift_size; j++) { 2421 iflib_txsd_free(ctx, txq, j); 2422 } 2423 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2424 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2425 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2426 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2427 txq->ift_pullups = 0; 2428 ifmp_ring_reset_stats(txq->ift_br); 2429 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2430 bzero((void *)di->idi_vaddr, di->idi_size); 2431 } 2432 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2433 /* make sure all transmitters have completed before proceeding XXX */ 2434 2435 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2436 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2437 bzero((void *)di->idi_vaddr, di->idi_size); 2438 /* also resets the free lists pidx/cidx */ 2439 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2440 iflib_fl_bufs_free(fl); 2441 } 2442 } 2443 2444 static inline caddr_t 2445 calc_next_rxd(iflib_fl_t fl, int cidx) 2446 { 2447 qidx_t size; 2448 int nrxd; 2449 caddr_t start, end, cur, next; 2450 2451 nrxd = fl->ifl_size; 2452 size = fl->ifl_rxd_size; 2453 start = fl->ifl_ifdi->idi_vaddr; 2454 2455 if (__predict_false(size == 0)) 2456 return (start); 2457 cur = start + size*cidx; 2458 end = start + size*nrxd; 2459 next = CACHE_PTR_NEXT(cur); 2460 return (next < end ? next : start); 2461 } 2462 2463 static inline void 2464 prefetch_pkts(iflib_fl_t fl, int cidx) 2465 { 2466 int nextptr; 2467 int nrxd = fl->ifl_size; 2468 caddr_t next_rxd; 2469 2470 2471 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2472 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2473 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2474 next_rxd = calc_next_rxd(fl, cidx); 2475 prefetch(next_rxd); 2476 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2477 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2478 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2479 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2480 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2481 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2482 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2483 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2484 } 2485 2486 static void 2487 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2488 { 2489 int flid, cidx; 2490 bus_dmamap_t map; 2491 iflib_fl_t fl; 2492 int next; 2493 2494 map = NULL; 2495 flid = irf->irf_flid; 2496 cidx = irf->irf_idx; 2497 fl = &rxq->ifr_fl[flid]; 2498 sd->ifsd_fl = fl; 2499 sd->ifsd_cidx = cidx; 2500 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2501 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2502 fl->ifl_credits--; 2503 #if MEMORY_LOGGING 2504 fl->ifl_m_dequeued++; 2505 #endif 2506 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2507 prefetch_pkts(fl, cidx); 2508 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2509 prefetch(&fl->ifl_sds.ifsd_map[next]); 2510 map = fl->ifl_sds.ifsd_map[cidx]; 2511 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2512 2513 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2514 MPASS(fl->ifl_cidx == cidx); 2515 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2516 if (unload) 2517 bus_dmamap_unload(fl->ifl_buf_tag, map); 2518 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2519 if (__predict_false(fl->ifl_cidx == 0)) 2520 fl->ifl_gen = 0; 2521 bit_clear(fl->ifl_rx_bitmap, cidx); 2522 } 2523 2524 static struct mbuf * 2525 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2526 { 2527 int i, padlen , flags; 2528 struct mbuf *m, *mh, *mt; 2529 caddr_t cl; 2530 2531 i = 0; 2532 mh = NULL; 2533 do { 2534 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2535 2536 MPASS(*sd->ifsd_cl != NULL); 2537 MPASS(*sd->ifsd_m != NULL); 2538 2539 /* Don't include zero-length frags */ 2540 if (ri->iri_frags[i].irf_len == 0) { 2541 /* XXX we can save the cluster here, but not the mbuf */ 2542 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2543 m_free(*sd->ifsd_m); 2544 *sd->ifsd_m = NULL; 2545 continue; 2546 } 2547 m = *sd->ifsd_m; 2548 *sd->ifsd_m = NULL; 2549 if (mh == NULL) { 2550 flags = M_PKTHDR|M_EXT; 2551 mh = mt = m; 2552 padlen = ri->iri_pad; 2553 } else { 2554 flags = M_EXT; 2555 mt->m_next = m; 2556 mt = m; 2557 /* assuming padding is only on the first fragment */ 2558 padlen = 0; 2559 } 2560 cl = *sd->ifsd_cl; 2561 *sd->ifsd_cl = NULL; 2562 2563 /* Can these two be made one ? */ 2564 m_init(m, M_NOWAIT, MT_DATA, flags); 2565 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2566 /* 2567 * These must follow m_init and m_cljset 2568 */ 2569 m->m_data += padlen; 2570 ri->iri_len -= padlen; 2571 m->m_len = ri->iri_frags[i].irf_len; 2572 } while (++i < ri->iri_nfrags); 2573 2574 return (mh); 2575 } 2576 2577 /* 2578 * Process one software descriptor 2579 */ 2580 static struct mbuf * 2581 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2582 { 2583 struct if_rxsd sd; 2584 struct mbuf *m; 2585 2586 /* should I merge this back in now that the two paths are basically duplicated? */ 2587 if (ri->iri_nfrags == 1 && 2588 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2589 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2590 m = *sd.ifsd_m; 2591 *sd.ifsd_m = NULL; 2592 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2593 #ifndef __NO_STRICT_ALIGNMENT 2594 if (!IP_ALIGNED(m)) 2595 m->m_data += 2; 2596 #endif 2597 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2598 m->m_len = ri->iri_frags[0].irf_len; 2599 } else { 2600 m = assemble_segments(rxq, ri, &sd); 2601 } 2602 m->m_pkthdr.len = ri->iri_len; 2603 m->m_pkthdr.rcvif = ri->iri_ifp; 2604 m->m_flags |= ri->iri_flags; 2605 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2606 m->m_pkthdr.flowid = ri->iri_flowid; 2607 M_HASHTYPE_SET(m, ri->iri_rsstype); 2608 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2609 m->m_pkthdr.csum_data = ri->iri_csum_data; 2610 return (m); 2611 } 2612 2613 #if defined(INET6) || defined(INET) 2614 static void 2615 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2616 { 2617 CURVNET_SET(lc->ifp->if_vnet); 2618 #if defined(INET6) 2619 *v6 = VNET(ip6_forwarding); 2620 #endif 2621 #if defined(INET) 2622 *v4 = VNET(ipforwarding); 2623 #endif 2624 CURVNET_RESTORE(); 2625 } 2626 2627 /* 2628 * Returns true if it's possible this packet could be LROed. 2629 * if it returns false, it is guaranteed that tcp_lro_rx() 2630 * would not return zero. 2631 */ 2632 static bool 2633 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2634 { 2635 struct ether_header *eh; 2636 uint16_t eh_type; 2637 2638 eh = mtod(m, struct ether_header *); 2639 eh_type = ntohs(eh->ether_type); 2640 switch (eh_type) { 2641 #if defined(INET6) 2642 case ETHERTYPE_IPV6: 2643 return !v6_forwarding; 2644 #endif 2645 #if defined (INET) 2646 case ETHERTYPE_IP: 2647 return !v4_forwarding; 2648 #endif 2649 } 2650 2651 return false; 2652 } 2653 #else 2654 static void 2655 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2656 { 2657 } 2658 #endif 2659 2660 static bool 2661 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2662 { 2663 if_ctx_t ctx = rxq->ifr_ctx; 2664 if_shared_ctx_t sctx = ctx->ifc_sctx; 2665 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2666 int avail, i; 2667 qidx_t *cidxp; 2668 struct if_rxd_info ri; 2669 int err, budget_left, rx_bytes, rx_pkts; 2670 iflib_fl_t fl; 2671 struct ifnet *ifp; 2672 int lro_enabled; 2673 bool v4_forwarding, v6_forwarding, lro_possible; 2674 2675 /* 2676 * XXX early demux data packets so that if_input processing only handles 2677 * acks in interrupt context 2678 */ 2679 struct mbuf *m, *mh, *mt, *mf; 2680 2681 lro_possible = v4_forwarding = v6_forwarding = false; 2682 ifp = ctx->ifc_ifp; 2683 mh = mt = NULL; 2684 MPASS(budget > 0); 2685 rx_pkts = rx_bytes = 0; 2686 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2687 cidxp = &rxq->ifr_cq_cidx; 2688 else 2689 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2690 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2691 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2692 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2693 DBG_COUNTER_INC(rx_unavail); 2694 return (false); 2695 } 2696 2697 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2698 if (__predict_false(!CTX_ACTIVE(ctx))) { 2699 DBG_COUNTER_INC(rx_ctx_inactive); 2700 break; 2701 } 2702 /* 2703 * Reset client set fields to their default values 2704 */ 2705 rxd_info_zero(&ri); 2706 ri.iri_qsidx = rxq->ifr_id; 2707 ri.iri_cidx = *cidxp; 2708 ri.iri_ifp = ifp; 2709 ri.iri_frags = rxq->ifr_frags; 2710 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2711 2712 if (err) 2713 goto err; 2714 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2715 *cidxp = ri.iri_cidx; 2716 /* Update our consumer index */ 2717 /* XXX NB: shurd - check if this is still safe */ 2718 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2719 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2720 rxq->ifr_cq_gen = 0; 2721 } 2722 /* was this only a completion queue message? */ 2723 if (__predict_false(ri.iri_nfrags == 0)) 2724 continue; 2725 } 2726 MPASS(ri.iri_nfrags != 0); 2727 MPASS(ri.iri_len != 0); 2728 2729 /* will advance the cidx on the corresponding free lists */ 2730 m = iflib_rxd_pkt_get(rxq, &ri); 2731 avail--; 2732 budget_left--; 2733 if (avail == 0 && budget_left) 2734 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2735 2736 if (__predict_false(m == NULL)) { 2737 DBG_COUNTER_INC(rx_mbuf_null); 2738 continue; 2739 } 2740 /* imm_pkt: -- cxgb */ 2741 if (mh == NULL) 2742 mh = mt = m; 2743 else { 2744 mt->m_nextpkt = m; 2745 mt = m; 2746 } 2747 } 2748 /* make sure that we can refill faster than drain */ 2749 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2750 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2751 2752 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2753 if (lro_enabled) 2754 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2755 mt = mf = NULL; 2756 while (mh != NULL) { 2757 m = mh; 2758 mh = mh->m_nextpkt; 2759 m->m_nextpkt = NULL; 2760 #ifndef __NO_STRICT_ALIGNMENT 2761 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2762 continue; 2763 #endif 2764 rx_bytes += m->m_pkthdr.len; 2765 rx_pkts++; 2766 #if defined(INET6) || defined(INET) 2767 if (lro_enabled) { 2768 if (!lro_possible) { 2769 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2770 if (lro_possible && mf != NULL) { 2771 ifp->if_input(ifp, mf); 2772 DBG_COUNTER_INC(rx_if_input); 2773 mt = mf = NULL; 2774 } 2775 } 2776 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2777 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2778 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2779 continue; 2780 } 2781 } 2782 #endif 2783 if (lro_possible) { 2784 ifp->if_input(ifp, m); 2785 DBG_COUNTER_INC(rx_if_input); 2786 continue; 2787 } 2788 2789 if (mf == NULL) 2790 mf = m; 2791 if (mt != NULL) 2792 mt->m_nextpkt = m; 2793 mt = m; 2794 } 2795 if (mf != NULL) { 2796 ifp->if_input(ifp, mf); 2797 DBG_COUNTER_INC(rx_if_input); 2798 } 2799 2800 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2801 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2802 2803 /* 2804 * Flush any outstanding LRO work 2805 */ 2806 #if defined(INET6) || defined(INET) 2807 tcp_lro_flush_all(&rxq->ifr_lc); 2808 #endif 2809 if (avail) 2810 return true; 2811 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2812 err: 2813 STATE_LOCK(ctx); 2814 ctx->ifc_flags |= IFC_DO_RESET; 2815 iflib_admin_intr_deferred(ctx); 2816 STATE_UNLOCK(ctx); 2817 return (false); 2818 } 2819 2820 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2821 static inline qidx_t 2822 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2823 { 2824 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2825 qidx_t minthresh = txq->ift_size / 8; 2826 if (in_use > 4*minthresh) 2827 return (notify_count); 2828 if (in_use > 2*minthresh) 2829 return (notify_count >> 1); 2830 if (in_use > minthresh) 2831 return (notify_count >> 3); 2832 return (0); 2833 } 2834 2835 static inline qidx_t 2836 txq_max_rs_deferred(iflib_txq_t txq) 2837 { 2838 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2839 qidx_t minthresh = txq->ift_size / 8; 2840 if (txq->ift_in_use > 4*minthresh) 2841 return (notify_count); 2842 if (txq->ift_in_use > 2*minthresh) 2843 return (notify_count >> 1); 2844 if (txq->ift_in_use > minthresh) 2845 return (notify_count >> 2); 2846 return (2); 2847 } 2848 2849 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2850 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2851 2852 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2853 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2854 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2855 2856 /* forward compatibility for cxgb */ 2857 #define FIRST_QSET(ctx) 0 2858 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2859 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2860 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2861 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2862 2863 /* XXX we should be setting this to something other than zero */ 2864 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2865 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 2866 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 2867 2868 static inline bool 2869 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2870 { 2871 qidx_t dbval, max; 2872 bool rang; 2873 2874 rang = false; 2875 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2876 if (ring || txq->ift_db_pending >= max) { 2877 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2878 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 2879 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2880 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2881 txq->ift_db_pending = txq->ift_npending = 0; 2882 rang = true; 2883 } 2884 return (rang); 2885 } 2886 2887 #ifdef PKT_DEBUG 2888 static void 2889 print_pkt(if_pkt_info_t pi) 2890 { 2891 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2892 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2893 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2894 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2895 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2896 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2897 } 2898 #endif 2899 2900 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2901 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 2902 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2903 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 2904 2905 static int 2906 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2907 { 2908 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2909 struct ether_vlan_header *eh; 2910 struct mbuf *m; 2911 2912 m = *mp; 2913 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2914 M_WRITABLE(m) == 0) { 2915 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2916 return (ENOMEM); 2917 } else { 2918 m_freem(*mp); 2919 DBG_COUNTER_INC(tx_frees); 2920 *mp = m; 2921 } 2922 } 2923 2924 /* 2925 * Determine where frame payload starts. 2926 * Jump over vlan headers if already present, 2927 * helpful for QinQ too. 2928 */ 2929 if (__predict_false(m->m_len < sizeof(*eh))) { 2930 txq->ift_pullups++; 2931 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2932 return (ENOMEM); 2933 } 2934 eh = mtod(m, struct ether_vlan_header *); 2935 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2936 pi->ipi_etype = ntohs(eh->evl_proto); 2937 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2938 } else { 2939 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2940 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2941 } 2942 2943 switch (pi->ipi_etype) { 2944 #ifdef INET 2945 case ETHERTYPE_IP: 2946 { 2947 struct mbuf *n; 2948 struct ip *ip = NULL; 2949 struct tcphdr *th = NULL; 2950 int minthlen; 2951 2952 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2953 if (__predict_false(m->m_len < minthlen)) { 2954 /* 2955 * if this code bloat is causing too much of a hit 2956 * move it to a separate function and mark it noinline 2957 */ 2958 if (m->m_len == pi->ipi_ehdrlen) { 2959 n = m->m_next; 2960 MPASS(n); 2961 if (n->m_len >= sizeof(*ip)) { 2962 ip = (struct ip *)n->m_data; 2963 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2964 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2965 } else { 2966 txq->ift_pullups++; 2967 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2968 return (ENOMEM); 2969 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2970 } 2971 } else { 2972 txq->ift_pullups++; 2973 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2974 return (ENOMEM); 2975 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2976 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2977 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2978 } 2979 } else { 2980 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2981 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2982 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2983 } 2984 pi->ipi_ip_hlen = ip->ip_hl << 2; 2985 pi->ipi_ipproto = ip->ip_p; 2986 pi->ipi_flags |= IPI_TX_IPV4; 2987 2988 /* TCP checksum offload may require TCP header length */ 2989 if (IS_TX_OFFLOAD4(pi)) { 2990 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 2991 if (__predict_false(th == NULL)) { 2992 txq->ift_pullups++; 2993 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 2994 return (ENOMEM); 2995 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 2996 } 2997 pi->ipi_tcp_hflags = th->th_flags; 2998 pi->ipi_tcp_hlen = th->th_off << 2; 2999 pi->ipi_tcp_seq = th->th_seq; 3000 } 3001 if (IS_TSO4(pi)) { 3002 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3003 return (ENXIO); 3004 /* 3005 * TSO always requires hardware checksum offload. 3006 */ 3007 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3008 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3009 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3010 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3011 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3012 ip->ip_sum = 0; 3013 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3014 } 3015 } 3016 } 3017 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3018 ip->ip_sum = 0; 3019 3020 break; 3021 } 3022 #endif 3023 #ifdef INET6 3024 case ETHERTYPE_IPV6: 3025 { 3026 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3027 struct tcphdr *th; 3028 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3029 3030 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3031 txq->ift_pullups++; 3032 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3033 return (ENOMEM); 3034 } 3035 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3036 3037 /* XXX-BZ this will go badly in case of ext hdrs. */ 3038 pi->ipi_ipproto = ip6->ip6_nxt; 3039 pi->ipi_flags |= IPI_TX_IPV6; 3040 3041 /* TCP checksum offload may require TCP header length */ 3042 if (IS_TX_OFFLOAD6(pi)) { 3043 if (pi->ipi_ipproto == IPPROTO_TCP) { 3044 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3045 txq->ift_pullups++; 3046 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3047 return (ENOMEM); 3048 } 3049 pi->ipi_tcp_hflags = th->th_flags; 3050 pi->ipi_tcp_hlen = th->th_off << 2; 3051 pi->ipi_tcp_seq = th->th_seq; 3052 } 3053 if (IS_TSO6(pi)) { 3054 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3055 return (ENXIO); 3056 /* 3057 * TSO always requires hardware checksum offload. 3058 */ 3059 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3060 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3061 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3062 } 3063 } 3064 break; 3065 } 3066 #endif 3067 default: 3068 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3069 pi->ipi_ip_hlen = 0; 3070 break; 3071 } 3072 *mp = m; 3073 3074 return (0); 3075 } 3076 3077 /* 3078 * If dodgy hardware rejects the scatter gather chain we've handed it 3079 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3080 * m_defrag'd mbufs 3081 */ 3082 static __noinline struct mbuf * 3083 iflib_remove_mbuf(iflib_txq_t txq) 3084 { 3085 int ntxd, pidx; 3086 struct mbuf *m, **ifsd_m; 3087 3088 ifsd_m = txq->ift_sds.ifsd_m; 3089 ntxd = txq->ift_size; 3090 pidx = txq->ift_pidx & (ntxd - 1); 3091 ifsd_m = txq->ift_sds.ifsd_m; 3092 m = ifsd_m[pidx]; 3093 ifsd_m[pidx] = NULL; 3094 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3095 if (txq->ift_sds.ifsd_tso_map != NULL) 3096 bus_dmamap_unload(txq->ift_tso_buf_tag, 3097 txq->ift_sds.ifsd_tso_map[pidx]); 3098 #if MEMORY_LOGGING 3099 txq->ift_dequeued++; 3100 #endif 3101 return (m); 3102 } 3103 3104 static inline caddr_t 3105 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3106 { 3107 qidx_t size; 3108 int ntxd; 3109 caddr_t start, end, cur, next; 3110 3111 ntxd = txq->ift_size; 3112 size = txq->ift_txd_size[qid]; 3113 start = txq->ift_ifdi[qid].idi_vaddr; 3114 3115 if (__predict_false(size == 0)) 3116 return (start); 3117 cur = start + size*cidx; 3118 end = start + size*ntxd; 3119 next = CACHE_PTR_NEXT(cur); 3120 return (next < end ? next : start); 3121 } 3122 3123 /* 3124 * Pad an mbuf to ensure a minimum ethernet frame size. 3125 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3126 */ 3127 static __noinline int 3128 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3129 { 3130 /* 3131 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3132 * and ARP message is the smallest common payload I can think of 3133 */ 3134 static char pad[18]; /* just zeros */ 3135 int n; 3136 struct mbuf *new_head; 3137 3138 if (!M_WRITABLE(*m_head)) { 3139 new_head = m_dup(*m_head, M_NOWAIT); 3140 if (new_head == NULL) { 3141 m_freem(*m_head); 3142 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3143 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3144 DBG_COUNTER_INC(tx_frees); 3145 return ENOMEM; 3146 } 3147 m_freem(*m_head); 3148 *m_head = new_head; 3149 } 3150 3151 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3152 n > 0; n -= sizeof(pad)) 3153 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3154 break; 3155 3156 if (n > 0) { 3157 m_freem(*m_head); 3158 device_printf(dev, "cannot pad short frame\n"); 3159 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3160 DBG_COUNTER_INC(tx_frees); 3161 return (ENOBUFS); 3162 } 3163 3164 return 0; 3165 } 3166 3167 static int 3168 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3169 { 3170 if_ctx_t ctx; 3171 if_shared_ctx_t sctx; 3172 if_softc_ctx_t scctx; 3173 bus_dma_tag_t buf_tag; 3174 bus_dma_segment_t *segs; 3175 struct mbuf *m_head, **ifsd_m; 3176 void *next_txd; 3177 bus_dmamap_t map; 3178 struct if_pkt_info pi; 3179 int remap = 0; 3180 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3181 3182 ctx = txq->ift_ctx; 3183 sctx = ctx->ifc_sctx; 3184 scctx = &ctx->ifc_softc_ctx; 3185 segs = txq->ift_segs; 3186 ntxd = txq->ift_size; 3187 m_head = *m_headp; 3188 map = NULL; 3189 3190 /* 3191 * If we're doing TSO the next descriptor to clean may be quite far ahead 3192 */ 3193 cidx = txq->ift_cidx; 3194 pidx = txq->ift_pidx; 3195 if (ctx->ifc_flags & IFC_PREFETCH) { 3196 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3197 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3198 next_txd = calc_next_txd(txq, cidx, 0); 3199 prefetch(next_txd); 3200 } 3201 3202 /* prefetch the next cache line of mbuf pointers and flags */ 3203 prefetch(&txq->ift_sds.ifsd_m[next]); 3204 prefetch(&txq->ift_sds.ifsd_map[next]); 3205 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3206 } 3207 map = txq->ift_sds.ifsd_map[pidx]; 3208 ifsd_m = txq->ift_sds.ifsd_m; 3209 3210 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3211 buf_tag = txq->ift_tso_buf_tag; 3212 max_segs = scctx->isc_tx_tso_segments_max; 3213 map = txq->ift_sds.ifsd_tso_map[pidx]; 3214 MPASS(buf_tag != NULL); 3215 MPASS(max_segs > 0); 3216 } else { 3217 buf_tag = txq->ift_buf_tag; 3218 max_segs = scctx->isc_tx_nsegments; 3219 map = txq->ift_sds.ifsd_map[pidx]; 3220 } 3221 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3222 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3223 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3224 if (err) { 3225 DBG_COUNTER_INC(encap_txd_encap_fail); 3226 return err; 3227 } 3228 } 3229 m_head = *m_headp; 3230 3231 pkt_info_zero(&pi); 3232 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3233 pi.ipi_pidx = pidx; 3234 pi.ipi_qsidx = txq->ift_id; 3235 pi.ipi_len = m_head->m_pkthdr.len; 3236 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3237 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3238 3239 /* deliberate bitwise OR to make one condition */ 3240 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3241 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3242 DBG_COUNTER_INC(encap_txd_encap_fail); 3243 return (err); 3244 } 3245 m_head = *m_headp; 3246 } 3247 3248 retry: 3249 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3250 BUS_DMA_NOWAIT); 3251 defrag: 3252 if (__predict_false(err)) { 3253 switch (err) { 3254 case EFBIG: 3255 /* try collapse once and defrag once */ 3256 if (remap == 0) { 3257 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3258 /* try defrag if collapsing fails */ 3259 if (m_head == NULL) 3260 remap++; 3261 } 3262 if (remap == 1) { 3263 txq->ift_mbuf_defrag++; 3264 m_head = m_defrag(*m_headp, M_NOWAIT); 3265 } 3266 /* 3267 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3268 * failed to map an mbuf that was run through m_defrag 3269 */ 3270 MPASS(remap <= 1); 3271 if (__predict_false(m_head == NULL || remap > 1)) 3272 goto defrag_failed; 3273 remap++; 3274 *m_headp = m_head; 3275 goto retry; 3276 break; 3277 case ENOMEM: 3278 txq->ift_no_tx_dma_setup++; 3279 break; 3280 default: 3281 txq->ift_no_tx_dma_setup++; 3282 m_freem(*m_headp); 3283 DBG_COUNTER_INC(tx_frees); 3284 *m_headp = NULL; 3285 break; 3286 } 3287 txq->ift_map_failed++; 3288 DBG_COUNTER_INC(encap_load_mbuf_fail); 3289 DBG_COUNTER_INC(encap_txd_encap_fail); 3290 return (err); 3291 } 3292 ifsd_m[pidx] = m_head; 3293 /* 3294 * XXX assumes a 1 to 1 relationship between segments and 3295 * descriptors - this does not hold true on all drivers, e.g. 3296 * cxgb 3297 */ 3298 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3299 txq->ift_no_desc_avail++; 3300 bus_dmamap_unload(buf_tag, map); 3301 DBG_COUNTER_INC(encap_txq_avail_fail); 3302 DBG_COUNTER_INC(encap_txd_encap_fail); 3303 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3304 GROUPTASK_ENQUEUE(&txq->ift_task); 3305 return (ENOBUFS); 3306 } 3307 /* 3308 * On Intel cards we can greatly reduce the number of TX interrupts 3309 * we see by only setting report status on every Nth descriptor. 3310 * However, this also means that the driver will need to keep track 3311 * of the descriptors that RS was set on to check them for the DD bit. 3312 */ 3313 txq->ift_rs_pending += nsegs + 1; 3314 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3315 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3316 pi.ipi_flags |= IPI_TX_INTR; 3317 txq->ift_rs_pending = 0; 3318 } 3319 3320 pi.ipi_segs = segs; 3321 pi.ipi_nsegs = nsegs; 3322 3323 MPASS(pidx >= 0 && pidx < txq->ift_size); 3324 #ifdef PKT_DEBUG 3325 print_pkt(&pi); 3326 #endif 3327 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3328 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3329 DBG_COUNTER_INC(tx_encap); 3330 MPASS(pi.ipi_new_pidx < txq->ift_size); 3331 3332 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3333 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3334 ndesc += txq->ift_size; 3335 txq->ift_gen = 1; 3336 } 3337 /* 3338 * drivers can need as many as 3339 * two sentinels 3340 */ 3341 MPASS(ndesc <= pi.ipi_nsegs + 2); 3342 MPASS(pi.ipi_new_pidx != pidx); 3343 MPASS(ndesc > 0); 3344 txq->ift_in_use += ndesc; 3345 3346 /* 3347 * We update the last software descriptor again here because there may 3348 * be a sentinel and/or there may be more mbufs than segments 3349 */ 3350 txq->ift_pidx = pi.ipi_new_pidx; 3351 txq->ift_npending += pi.ipi_ndescs; 3352 } else { 3353 *m_headp = m_head = iflib_remove_mbuf(txq); 3354 if (err == EFBIG) { 3355 txq->ift_txd_encap_efbig++; 3356 if (remap < 2) { 3357 remap = 1; 3358 goto defrag; 3359 } 3360 } 3361 goto defrag_failed; 3362 } 3363 /* 3364 * err can't possibly be non-zero here, so we don't neet to test it 3365 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3366 */ 3367 return (err); 3368 3369 defrag_failed: 3370 txq->ift_mbuf_defrag_failed++; 3371 txq->ift_map_failed++; 3372 m_freem(*m_headp); 3373 DBG_COUNTER_INC(tx_frees); 3374 *m_headp = NULL; 3375 DBG_COUNTER_INC(encap_txd_encap_fail); 3376 return (ENOMEM); 3377 } 3378 3379 static void 3380 iflib_tx_desc_free(iflib_txq_t txq, int n) 3381 { 3382 uint32_t qsize, cidx, mask, gen; 3383 struct mbuf *m, **ifsd_m; 3384 bool do_prefetch; 3385 3386 cidx = txq->ift_cidx; 3387 gen = txq->ift_gen; 3388 qsize = txq->ift_size; 3389 mask = qsize-1; 3390 ifsd_m = txq->ift_sds.ifsd_m; 3391 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3392 3393 while (n-- > 0) { 3394 if (do_prefetch) { 3395 prefetch(ifsd_m[(cidx + 3) & mask]); 3396 prefetch(ifsd_m[(cidx + 4) & mask]); 3397 } 3398 if ((m = ifsd_m[cidx]) != NULL) { 3399 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3400 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3401 bus_dmamap_sync(txq->ift_tso_buf_tag, 3402 txq->ift_sds.ifsd_tso_map[cidx], 3403 BUS_DMASYNC_POSTWRITE); 3404 bus_dmamap_unload(txq->ift_tso_buf_tag, 3405 txq->ift_sds.ifsd_tso_map[cidx]); 3406 } else { 3407 bus_dmamap_sync(txq->ift_buf_tag, 3408 txq->ift_sds.ifsd_map[cidx], 3409 BUS_DMASYNC_POSTWRITE); 3410 bus_dmamap_unload(txq->ift_buf_tag, 3411 txq->ift_sds.ifsd_map[cidx]); 3412 } 3413 /* XXX we don't support any drivers that batch packets yet */ 3414 MPASS(m->m_nextpkt == NULL); 3415 m_freem(m); 3416 ifsd_m[cidx] = NULL; 3417 #if MEMORY_LOGGING 3418 txq->ift_dequeued++; 3419 #endif 3420 DBG_COUNTER_INC(tx_frees); 3421 } 3422 if (__predict_false(++cidx == qsize)) { 3423 cidx = 0; 3424 gen = 0; 3425 } 3426 } 3427 txq->ift_cidx = cidx; 3428 txq->ift_gen = gen; 3429 } 3430 3431 static __inline int 3432 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3433 { 3434 int reclaim; 3435 if_ctx_t ctx = txq->ift_ctx; 3436 3437 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3438 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3439 3440 /* 3441 * Need a rate-limiting check so that this isn't called every time 3442 */ 3443 iflib_tx_credits_update(ctx, txq); 3444 reclaim = DESC_RECLAIMABLE(txq); 3445 3446 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3447 #ifdef INVARIANTS 3448 if (iflib_verbose_debug) { 3449 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3450 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3451 reclaim, thresh); 3452 3453 } 3454 #endif 3455 return (0); 3456 } 3457 iflib_tx_desc_free(txq, reclaim); 3458 txq->ift_cleaned += reclaim; 3459 txq->ift_in_use -= reclaim; 3460 3461 return (reclaim); 3462 } 3463 3464 static struct mbuf ** 3465 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3466 { 3467 int next, size; 3468 struct mbuf **items; 3469 3470 size = r->size; 3471 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3472 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3473 3474 prefetch(items[(cidx + offset) & (size-1)]); 3475 if (remaining > 1) { 3476 prefetch2cachelines(&items[next]); 3477 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3478 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3479 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3480 } 3481 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3482 } 3483 3484 static void 3485 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3486 { 3487 3488 ifmp_ring_check_drainage(txq->ift_br, budget); 3489 } 3490 3491 static uint32_t 3492 iflib_txq_can_drain(struct ifmp_ring *r) 3493 { 3494 iflib_txq_t txq = r->cookie; 3495 if_ctx_t ctx = txq->ift_ctx; 3496 3497 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3498 return (1); 3499 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3500 BUS_DMASYNC_POSTREAD); 3501 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3502 false)); 3503 } 3504 3505 static uint32_t 3506 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3507 { 3508 iflib_txq_t txq = r->cookie; 3509 if_ctx_t ctx = txq->ift_ctx; 3510 struct ifnet *ifp = ctx->ifc_ifp; 3511 struct mbuf **mp, *m; 3512 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3513 int reclaimed, err, in_use_prev, desc_used; 3514 bool do_prefetch, ring, rang; 3515 3516 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3517 !LINK_ACTIVE(ctx))) { 3518 DBG_COUNTER_INC(txq_drain_notready); 3519 return (0); 3520 } 3521 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3522 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3523 avail = IDXDIFF(pidx, cidx, r->size); 3524 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3525 DBG_COUNTER_INC(txq_drain_flushing); 3526 for (i = 0; i < avail; i++) { 3527 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3528 m_free(r->items[(cidx + i) & (r->size-1)]); 3529 r->items[(cidx + i) & (r->size-1)] = NULL; 3530 } 3531 return (avail); 3532 } 3533 3534 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3535 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3536 CALLOUT_LOCK(txq); 3537 callout_stop(&txq->ift_timer); 3538 CALLOUT_UNLOCK(txq); 3539 DBG_COUNTER_INC(txq_drain_oactive); 3540 return (0); 3541 } 3542 if (reclaimed) 3543 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3544 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3545 count = MIN(avail, TX_BATCH_SIZE); 3546 #ifdef INVARIANTS 3547 if (iflib_verbose_debug) 3548 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3549 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3550 #endif 3551 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3552 avail = TXQ_AVAIL(txq); 3553 err = 0; 3554 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3555 int rem = do_prefetch ? count - i : 0; 3556 3557 mp = _ring_peek_one(r, cidx, i, rem); 3558 MPASS(mp != NULL && *mp != NULL); 3559 if (__predict_false(*mp == (struct mbuf *)txq)) { 3560 consumed++; 3561 reclaimed++; 3562 continue; 3563 } 3564 in_use_prev = txq->ift_in_use; 3565 err = iflib_encap(txq, mp); 3566 if (__predict_false(err)) { 3567 /* no room - bail out */ 3568 if (err == ENOBUFS) 3569 break; 3570 consumed++; 3571 /* we can't send this packet - skip it */ 3572 continue; 3573 } 3574 consumed++; 3575 pkt_sent++; 3576 m = *mp; 3577 DBG_COUNTER_INC(tx_sent); 3578 bytes_sent += m->m_pkthdr.len; 3579 mcast_sent += !!(m->m_flags & M_MCAST); 3580 avail = TXQ_AVAIL(txq); 3581 3582 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3583 desc_used += (txq->ift_in_use - in_use_prev); 3584 ETHER_BPF_MTAP(ifp, m); 3585 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3586 break; 3587 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3588 } 3589 3590 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3591 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3592 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3593 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3594 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3595 if (mcast_sent) 3596 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3597 #ifdef INVARIANTS 3598 if (iflib_verbose_debug) 3599 printf("consumed=%d\n", consumed); 3600 #endif 3601 return (consumed); 3602 } 3603 3604 static uint32_t 3605 iflib_txq_drain_always(struct ifmp_ring *r) 3606 { 3607 return (1); 3608 } 3609 3610 static uint32_t 3611 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3612 { 3613 int i, avail; 3614 struct mbuf **mp; 3615 iflib_txq_t txq; 3616 3617 txq = r->cookie; 3618 3619 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3620 CALLOUT_LOCK(txq); 3621 callout_stop(&txq->ift_timer); 3622 CALLOUT_UNLOCK(txq); 3623 3624 avail = IDXDIFF(pidx, cidx, r->size); 3625 for (i = 0; i < avail; i++) { 3626 mp = _ring_peek_one(r, cidx, i, avail - i); 3627 if (__predict_false(*mp == (struct mbuf *)txq)) 3628 continue; 3629 m_freem(*mp); 3630 DBG_COUNTER_INC(tx_frees); 3631 } 3632 MPASS(ifmp_ring_is_stalled(r) == 0); 3633 return (avail); 3634 } 3635 3636 static void 3637 iflib_ifmp_purge(iflib_txq_t txq) 3638 { 3639 struct ifmp_ring *r; 3640 3641 r = txq->ift_br; 3642 r->drain = iflib_txq_drain_free; 3643 r->can_drain = iflib_txq_drain_always; 3644 3645 ifmp_ring_check_drainage(r, r->size); 3646 3647 r->drain = iflib_txq_drain; 3648 r->can_drain = iflib_txq_can_drain; 3649 } 3650 3651 static void 3652 _task_fn_tx(void *context) 3653 { 3654 iflib_txq_t txq = context; 3655 if_ctx_t ctx = txq->ift_ctx; 3656 #if defined(ALTQ) || defined(DEV_NETMAP) 3657 if_t ifp = ctx->ifc_ifp; 3658 #endif 3659 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3660 3661 #ifdef IFLIB_DIAGNOSTICS 3662 txq->ift_cpu_exec_count[curcpu]++; 3663 #endif 3664 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3665 return; 3666 #ifdef DEV_NETMAP 3667 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3668 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3669 BUS_DMASYNC_POSTREAD); 3670 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3671 netmap_tx_irq(ifp, txq->ift_id); 3672 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3673 return; 3674 } 3675 #endif 3676 #ifdef ALTQ 3677 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3678 iflib_altq_if_start(ifp); 3679 #endif 3680 if (txq->ift_db_pending) 3681 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3682 else if (!abdicate) 3683 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3684 /* 3685 * When abdicating, we always need to check drainage, not just when we don't enqueue 3686 */ 3687 if (abdicate) 3688 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3689 if (ctx->ifc_flags & IFC_LEGACY) 3690 IFDI_INTR_ENABLE(ctx); 3691 else { 3692 #ifdef INVARIANTS 3693 int rc = 3694 #endif 3695 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3696 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3697 } 3698 } 3699 3700 static void 3701 _task_fn_rx(void *context) 3702 { 3703 iflib_rxq_t rxq = context; 3704 if_ctx_t ctx = rxq->ifr_ctx; 3705 bool more; 3706 uint16_t budget; 3707 3708 #ifdef IFLIB_DIAGNOSTICS 3709 rxq->ifr_cpu_exec_count[curcpu]++; 3710 #endif 3711 DBG_COUNTER_INC(task_fn_rxs); 3712 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3713 return; 3714 more = true; 3715 #ifdef DEV_NETMAP 3716 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3717 u_int work = 0; 3718 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3719 more = false; 3720 } 3721 } 3722 #endif 3723 budget = ctx->ifc_sysctl_rx_budget; 3724 if (budget == 0) 3725 budget = 16; /* XXX */ 3726 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3727 if (ctx->ifc_flags & IFC_LEGACY) 3728 IFDI_INTR_ENABLE(ctx); 3729 else { 3730 #ifdef INVARIANTS 3731 int rc = 3732 #endif 3733 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3734 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3735 DBG_COUNTER_INC(rx_intr_enables); 3736 } 3737 } 3738 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3739 return; 3740 if (more) 3741 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3742 } 3743 3744 static void 3745 _task_fn_admin(void *context) 3746 { 3747 if_ctx_t ctx = context; 3748 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3749 iflib_txq_t txq; 3750 int i; 3751 bool oactive, running, do_reset, do_watchdog, in_detach; 3752 uint32_t reset_on = hz / 2; 3753 3754 STATE_LOCK(ctx); 3755 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3756 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3757 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3758 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3759 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3760 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3761 STATE_UNLOCK(ctx); 3762 3763 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3764 return; 3765 if (in_detach) 3766 return; 3767 3768 CTX_LOCK(ctx); 3769 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3770 CALLOUT_LOCK(txq); 3771 callout_stop(&txq->ift_timer); 3772 CALLOUT_UNLOCK(txq); 3773 } 3774 if (do_watchdog) { 3775 ctx->ifc_watchdog_events++; 3776 IFDI_WATCHDOG_RESET(ctx); 3777 } 3778 IFDI_UPDATE_ADMIN_STATUS(ctx); 3779 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3780 #ifdef DEV_NETMAP 3781 reset_on = hz / 2; 3782 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 3783 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 3784 #endif 3785 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 3786 } 3787 IFDI_LINK_INTR_ENABLE(ctx); 3788 if (do_reset) 3789 iflib_if_init_locked(ctx); 3790 CTX_UNLOCK(ctx); 3791 3792 if (LINK_ACTIVE(ctx) == 0) 3793 return; 3794 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3795 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3796 } 3797 3798 3799 static void 3800 _task_fn_iov(void *context) 3801 { 3802 if_ctx_t ctx = context; 3803 3804 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3805 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3806 return; 3807 3808 CTX_LOCK(ctx); 3809 IFDI_VFLR_HANDLE(ctx); 3810 CTX_UNLOCK(ctx); 3811 } 3812 3813 static int 3814 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3815 { 3816 int err; 3817 if_int_delay_info_t info; 3818 if_ctx_t ctx; 3819 3820 info = (if_int_delay_info_t)arg1; 3821 ctx = info->iidi_ctx; 3822 info->iidi_req = req; 3823 info->iidi_oidp = oidp; 3824 CTX_LOCK(ctx); 3825 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3826 CTX_UNLOCK(ctx); 3827 return (err); 3828 } 3829 3830 /********************************************************************* 3831 * 3832 * IFNET FUNCTIONS 3833 * 3834 **********************************************************************/ 3835 3836 static void 3837 iflib_if_init_locked(if_ctx_t ctx) 3838 { 3839 iflib_stop(ctx); 3840 iflib_init_locked(ctx); 3841 } 3842 3843 3844 static void 3845 iflib_if_init(void *arg) 3846 { 3847 if_ctx_t ctx = arg; 3848 3849 CTX_LOCK(ctx); 3850 iflib_if_init_locked(ctx); 3851 CTX_UNLOCK(ctx); 3852 } 3853 3854 static int 3855 iflib_if_transmit(if_t ifp, struct mbuf *m) 3856 { 3857 if_ctx_t ctx = if_getsoftc(ifp); 3858 3859 iflib_txq_t txq; 3860 int err, qidx; 3861 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3862 3863 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3864 DBG_COUNTER_INC(tx_frees); 3865 m_freem(m); 3866 return (ENETDOWN); 3867 } 3868 3869 MPASS(m->m_nextpkt == NULL); 3870 /* ALTQ-enabled interfaces always use queue 0. */ 3871 qidx = 0; 3872 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 3873 qidx = QIDX(ctx, m); 3874 /* 3875 * XXX calculate buf_ring based on flowid (divvy up bits?) 3876 */ 3877 txq = &ctx->ifc_txqs[qidx]; 3878 3879 #ifdef DRIVER_BACKPRESSURE 3880 if (txq->ift_closed) { 3881 while (m != NULL) { 3882 next = m->m_nextpkt; 3883 m->m_nextpkt = NULL; 3884 m_freem(m); 3885 DBG_COUNTER_INC(tx_frees); 3886 m = next; 3887 } 3888 return (ENOBUFS); 3889 } 3890 #endif 3891 #ifdef notyet 3892 qidx = count = 0; 3893 mp = marr; 3894 next = m; 3895 do { 3896 count++; 3897 next = next->m_nextpkt; 3898 } while (next != NULL); 3899 3900 if (count > nitems(marr)) 3901 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3902 /* XXX check nextpkt */ 3903 m_freem(m); 3904 /* XXX simplify for now */ 3905 DBG_COUNTER_INC(tx_frees); 3906 return (ENOBUFS); 3907 } 3908 for (next = m, i = 0; next != NULL; i++) { 3909 mp[i] = next; 3910 next = next->m_nextpkt; 3911 mp[i]->m_nextpkt = NULL; 3912 } 3913 #endif 3914 DBG_COUNTER_INC(tx_seen); 3915 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 3916 3917 if (abdicate) 3918 GROUPTASK_ENQUEUE(&txq->ift_task); 3919 if (err) { 3920 if (!abdicate) 3921 GROUPTASK_ENQUEUE(&txq->ift_task); 3922 /* support forthcoming later */ 3923 #ifdef DRIVER_BACKPRESSURE 3924 txq->ift_closed = TRUE; 3925 #endif 3926 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3927 m_freem(m); 3928 DBG_COUNTER_INC(tx_frees); 3929 } 3930 3931 return (err); 3932 } 3933 3934 #ifdef ALTQ 3935 /* 3936 * The overall approach to integrating iflib with ALTQ is to continue to use 3937 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 3938 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 3939 * is redundant/unnecessary, but doing so minimizes the amount of 3940 * ALTQ-specific code required in iflib. It is assumed that the overhead of 3941 * redundantly queueing to an intermediate mp_ring is swamped by the 3942 * performance limitations inherent in using ALTQ. 3943 * 3944 * When ALTQ support is compiled in, all iflib drivers will use a transmit 3945 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 3946 * given interface. If ALTQ is enabled for an interface, then all 3947 * transmitted packets for that interface will be submitted to the ALTQ 3948 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 3949 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 3950 * update stats that the iflib machinery handles, and which is sensitve to 3951 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 3952 * will be installed as the start routine for use by ALTQ facilities that 3953 * need to trigger queue drains on a scheduled basis. 3954 * 3955 */ 3956 static void 3957 iflib_altq_if_start(if_t ifp) 3958 { 3959 struct ifaltq *ifq = &ifp->if_snd; 3960 struct mbuf *m; 3961 3962 IFQ_LOCK(ifq); 3963 IFQ_DEQUEUE_NOLOCK(ifq, m); 3964 while (m != NULL) { 3965 iflib_if_transmit(ifp, m); 3966 IFQ_DEQUEUE_NOLOCK(ifq, m); 3967 } 3968 IFQ_UNLOCK(ifq); 3969 } 3970 3971 static int 3972 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 3973 { 3974 int err; 3975 3976 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 3977 IFQ_ENQUEUE(&ifp->if_snd, m, err); 3978 if (err == 0) 3979 iflib_altq_if_start(ifp); 3980 } else 3981 err = iflib_if_transmit(ifp, m); 3982 3983 return (err); 3984 } 3985 #endif /* ALTQ */ 3986 3987 static void 3988 iflib_if_qflush(if_t ifp) 3989 { 3990 if_ctx_t ctx = if_getsoftc(ifp); 3991 iflib_txq_t txq = ctx->ifc_txqs; 3992 int i; 3993 3994 STATE_LOCK(ctx); 3995 ctx->ifc_flags |= IFC_QFLUSH; 3996 STATE_UNLOCK(ctx); 3997 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 3998 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 3999 iflib_txq_check_drain(txq, 0); 4000 STATE_LOCK(ctx); 4001 ctx->ifc_flags &= ~IFC_QFLUSH; 4002 STATE_UNLOCK(ctx); 4003 4004 /* 4005 * When ALTQ is enabled, this will also take care of purging the 4006 * ALTQ queue(s). 4007 */ 4008 if_qflush(ifp); 4009 } 4010 4011 4012 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4013 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4014 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4015 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM) 4016 4017 static int 4018 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4019 { 4020 if_ctx_t ctx = if_getsoftc(ifp); 4021 struct ifreq *ifr = (struct ifreq *)data; 4022 #if defined(INET) || defined(INET6) 4023 struct ifaddr *ifa = (struct ifaddr *)data; 4024 #endif 4025 bool avoid_reset = FALSE; 4026 int err = 0, reinit = 0, bits; 4027 4028 switch (command) { 4029 case SIOCSIFADDR: 4030 #ifdef INET 4031 if (ifa->ifa_addr->sa_family == AF_INET) 4032 avoid_reset = TRUE; 4033 #endif 4034 #ifdef INET6 4035 if (ifa->ifa_addr->sa_family == AF_INET6) 4036 avoid_reset = TRUE; 4037 #endif 4038 /* 4039 ** Calling init results in link renegotiation, 4040 ** so we avoid doing it when possible. 4041 */ 4042 if (avoid_reset) { 4043 if_setflagbits(ifp, IFF_UP,0); 4044 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4045 reinit = 1; 4046 #ifdef INET 4047 if (!(if_getflags(ifp) & IFF_NOARP)) 4048 arp_ifinit(ifp, ifa); 4049 #endif 4050 } else 4051 err = ether_ioctl(ifp, command, data); 4052 break; 4053 case SIOCSIFMTU: 4054 CTX_LOCK(ctx); 4055 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4056 CTX_UNLOCK(ctx); 4057 break; 4058 } 4059 bits = if_getdrvflags(ifp); 4060 /* stop the driver and free any clusters before proceeding */ 4061 iflib_stop(ctx); 4062 4063 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4064 STATE_LOCK(ctx); 4065 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4066 ctx->ifc_flags |= IFC_MULTISEG; 4067 else 4068 ctx->ifc_flags &= ~IFC_MULTISEG; 4069 STATE_UNLOCK(ctx); 4070 err = if_setmtu(ifp, ifr->ifr_mtu); 4071 } 4072 iflib_init_locked(ctx); 4073 STATE_LOCK(ctx); 4074 if_setdrvflags(ifp, bits); 4075 STATE_UNLOCK(ctx); 4076 CTX_UNLOCK(ctx); 4077 break; 4078 case SIOCSIFFLAGS: 4079 CTX_LOCK(ctx); 4080 if (if_getflags(ifp) & IFF_UP) { 4081 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4082 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4083 (IFF_PROMISC | IFF_ALLMULTI)) { 4084 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4085 } 4086 } else 4087 reinit = 1; 4088 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4089 iflib_stop(ctx); 4090 } 4091 ctx->ifc_if_flags = if_getflags(ifp); 4092 CTX_UNLOCK(ctx); 4093 break; 4094 case SIOCADDMULTI: 4095 case SIOCDELMULTI: 4096 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4097 CTX_LOCK(ctx); 4098 IFDI_INTR_DISABLE(ctx); 4099 IFDI_MULTI_SET(ctx); 4100 IFDI_INTR_ENABLE(ctx); 4101 CTX_UNLOCK(ctx); 4102 } 4103 break; 4104 case SIOCSIFMEDIA: 4105 CTX_LOCK(ctx); 4106 IFDI_MEDIA_SET(ctx); 4107 CTX_UNLOCK(ctx); 4108 /* falls thru */ 4109 case SIOCGIFMEDIA: 4110 case SIOCGIFXMEDIA: 4111 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 4112 break; 4113 case SIOCGI2C: 4114 { 4115 struct ifi2creq i2c; 4116 4117 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4118 if (err != 0) 4119 break; 4120 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4121 err = EINVAL; 4122 break; 4123 } 4124 if (i2c.len > sizeof(i2c.data)) { 4125 err = EINVAL; 4126 break; 4127 } 4128 4129 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4130 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4131 sizeof(i2c)); 4132 break; 4133 } 4134 case SIOCSIFCAP: 4135 { 4136 int mask, setmask, oldmask; 4137 4138 oldmask = if_getcapenable(ifp); 4139 mask = ifr->ifr_reqcap ^ oldmask; 4140 mask &= ctx->ifc_softc_ctx.isc_capabilities; 4141 setmask = 0; 4142 #ifdef TCP_OFFLOAD 4143 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4144 #endif 4145 setmask |= (mask & IFCAP_FLAGS); 4146 setmask |= (mask & IFCAP_WOL); 4147 4148 /* 4149 * If any RX csum has changed, change all the ones that 4150 * are supported by the driver. 4151 */ 4152 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4153 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4154 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4155 } 4156 4157 /* 4158 * want to ensure that traffic has stopped before we change any of the flags 4159 */ 4160 if (setmask) { 4161 CTX_LOCK(ctx); 4162 bits = if_getdrvflags(ifp); 4163 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4164 iflib_stop(ctx); 4165 STATE_LOCK(ctx); 4166 if_togglecapenable(ifp, setmask); 4167 STATE_UNLOCK(ctx); 4168 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4169 iflib_init_locked(ctx); 4170 STATE_LOCK(ctx); 4171 if_setdrvflags(ifp, bits); 4172 STATE_UNLOCK(ctx); 4173 CTX_UNLOCK(ctx); 4174 } 4175 if_vlancap(ifp); 4176 break; 4177 } 4178 case SIOCGPRIVATE_0: 4179 case SIOCSDRVSPEC: 4180 case SIOCGDRVSPEC: 4181 CTX_LOCK(ctx); 4182 err = IFDI_PRIV_IOCTL(ctx, command, data); 4183 CTX_UNLOCK(ctx); 4184 break; 4185 default: 4186 err = ether_ioctl(ifp, command, data); 4187 break; 4188 } 4189 if (reinit) 4190 iflib_if_init(ctx); 4191 return (err); 4192 } 4193 4194 static uint64_t 4195 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4196 { 4197 if_ctx_t ctx = if_getsoftc(ifp); 4198 4199 return (IFDI_GET_COUNTER(ctx, cnt)); 4200 } 4201 4202 /********************************************************************* 4203 * 4204 * OTHER FUNCTIONS EXPORTED TO THE STACK 4205 * 4206 **********************************************************************/ 4207 4208 static void 4209 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4210 { 4211 if_ctx_t ctx = if_getsoftc(ifp); 4212 4213 if ((void *)ctx != arg) 4214 return; 4215 4216 if ((vtag == 0) || (vtag > 4095)) 4217 return; 4218 4219 CTX_LOCK(ctx); 4220 IFDI_VLAN_REGISTER(ctx, vtag); 4221 /* Re-init to load the changes */ 4222 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4223 iflib_if_init_locked(ctx); 4224 CTX_UNLOCK(ctx); 4225 } 4226 4227 static void 4228 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4229 { 4230 if_ctx_t ctx = if_getsoftc(ifp); 4231 4232 if ((void *)ctx != arg) 4233 return; 4234 4235 if ((vtag == 0) || (vtag > 4095)) 4236 return; 4237 4238 CTX_LOCK(ctx); 4239 IFDI_VLAN_UNREGISTER(ctx, vtag); 4240 /* Re-init to load the changes */ 4241 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 4242 iflib_if_init_locked(ctx); 4243 CTX_UNLOCK(ctx); 4244 } 4245 4246 static void 4247 iflib_led_func(void *arg, int onoff) 4248 { 4249 if_ctx_t ctx = arg; 4250 4251 CTX_LOCK(ctx); 4252 IFDI_LED_FUNC(ctx, onoff); 4253 CTX_UNLOCK(ctx); 4254 } 4255 4256 /********************************************************************* 4257 * 4258 * BUS FUNCTION DEFINITIONS 4259 * 4260 **********************************************************************/ 4261 4262 int 4263 iflib_device_probe(device_t dev) 4264 { 4265 pci_vendor_info_t *ent; 4266 4267 uint16_t pci_vendor_id, pci_device_id; 4268 uint16_t pci_subvendor_id, pci_subdevice_id; 4269 uint16_t pci_rev_id; 4270 if_shared_ctx_t sctx; 4271 4272 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4273 return (ENOTSUP); 4274 4275 pci_vendor_id = pci_get_vendor(dev); 4276 pci_device_id = pci_get_device(dev); 4277 pci_subvendor_id = pci_get_subvendor(dev); 4278 pci_subdevice_id = pci_get_subdevice(dev); 4279 pci_rev_id = pci_get_revid(dev); 4280 if (sctx->isc_parse_devinfo != NULL) 4281 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4282 4283 ent = sctx->isc_vendor_info; 4284 while (ent->pvi_vendor_id != 0) { 4285 if (pci_vendor_id != ent->pvi_vendor_id) { 4286 ent++; 4287 continue; 4288 } 4289 if ((pci_device_id == ent->pvi_device_id) && 4290 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4291 (ent->pvi_subvendor_id == 0)) && 4292 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4293 (ent->pvi_subdevice_id == 0)) && 4294 ((pci_rev_id == ent->pvi_rev_id) || 4295 (ent->pvi_rev_id == 0))) { 4296 4297 device_set_desc_copy(dev, ent->pvi_name); 4298 /* this needs to be changed to zero if the bus probing code 4299 * ever stops re-probing on best match because the sctx 4300 * may have its values over written by register calls 4301 * in subsequent probes 4302 */ 4303 return (BUS_PROBE_DEFAULT); 4304 } 4305 ent++; 4306 } 4307 return (ENXIO); 4308 } 4309 4310 static void 4311 iflib_reset_qvalues(if_ctx_t ctx) 4312 { 4313 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4314 if_shared_ctx_t sctx = ctx->ifc_sctx; 4315 device_t dev = ctx->ifc_dev; 4316 int i; 4317 4318 scctx->isc_txrx_budget_bytes_max = IFLIB_MAX_TX_BYTES; 4319 scctx->isc_tx_qdepth = IFLIB_DEFAULT_TX_QDEPTH; 4320 /* 4321 * XXX sanity check that ntxd & nrxd are a power of 2 4322 */ 4323 if (ctx->ifc_sysctl_ntxqs != 0) 4324 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4325 if (ctx->ifc_sysctl_nrxqs != 0) 4326 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4327 4328 for (i = 0; i < sctx->isc_ntxqs; i++) { 4329 if (ctx->ifc_sysctl_ntxds[i] != 0) 4330 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4331 else 4332 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4333 } 4334 4335 for (i = 0; i < sctx->isc_nrxqs; i++) { 4336 if (ctx->ifc_sysctl_nrxds[i] != 0) 4337 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4338 else 4339 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4340 } 4341 4342 for (i = 0; i < sctx->isc_nrxqs; i++) { 4343 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4344 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4345 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4346 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4347 } 4348 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4349 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4350 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4351 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4352 } 4353 } 4354 4355 for (i = 0; i < sctx->isc_ntxqs; i++) { 4356 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4357 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4358 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4359 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4360 } 4361 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4362 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4363 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4364 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4365 } 4366 } 4367 } 4368 4369 int 4370 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4371 { 4372 int err, rid, msix; 4373 if_ctx_t ctx; 4374 if_t ifp; 4375 if_softc_ctx_t scctx; 4376 int i; 4377 uint16_t main_txq; 4378 uint16_t main_rxq; 4379 4380 4381 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4382 4383 if (sc == NULL) { 4384 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4385 device_set_softc(dev, ctx); 4386 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4387 } 4388 4389 ctx->ifc_sctx = sctx; 4390 ctx->ifc_dev = dev; 4391 ctx->ifc_softc = sc; 4392 4393 if ((err = iflib_register(ctx)) != 0) { 4394 device_printf(dev, "iflib_register failed %d\n", err); 4395 goto fail_ctx_free; 4396 } 4397 iflib_add_device_sysctl_pre(ctx); 4398 4399 scctx = &ctx->ifc_softc_ctx; 4400 ifp = ctx->ifc_ifp; 4401 4402 iflib_reset_qvalues(ctx); 4403 CTX_LOCK(ctx); 4404 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4405 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4406 goto fail_unlock; 4407 } 4408 _iflib_pre_assert(scctx); 4409 ctx->ifc_txrx = *scctx->isc_txrx; 4410 4411 #ifdef INVARIANTS 4412 MPASS(scctx->isc_capabilities); 4413 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4414 MPASS(scctx->isc_tx_csum_flags); 4415 #endif 4416 4417 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS); 4418 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4419 4420 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4421 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4422 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4423 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4424 4425 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4426 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4427 4428 /* XXX change for per-queue sizes */ 4429 device_printf(dev, "Using %d tx descriptors and %d rx descriptors\n", 4430 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4431 for (i = 0; i < sctx->isc_nrxqs; i++) { 4432 if (!powerof2(scctx->isc_nrxd[i])) { 4433 /* round down instead? */ 4434 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4435 err = EINVAL; 4436 goto fail_iflib_detach; 4437 } 4438 } 4439 for (i = 0; i < sctx->isc_ntxqs; i++) { 4440 if (!powerof2(scctx->isc_ntxd[i])) { 4441 device_printf(dev, 4442 "# tx descriptors must be a power of 2"); 4443 err = EINVAL; 4444 goto fail_iflib_detach; 4445 } 4446 } 4447 4448 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4449 MAX_SINGLE_PACKET_FRACTION) 4450 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4451 MAX_SINGLE_PACKET_FRACTION); 4452 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4453 MAX_SINGLE_PACKET_FRACTION) 4454 scctx->isc_tx_tso_segments_max = max(1, 4455 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4456 4457 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4458 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4459 /* 4460 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4461 * but some MACs do. 4462 */ 4463 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4464 IP_MAXPACKET)); 4465 /* 4466 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4467 * into account. In the worst case, each of these calls will 4468 * add another mbuf and, thus, the requirement for another DMA 4469 * segment. So for best performance, it doesn't make sense to 4470 * advertize a maximum of TSO segments that typically will 4471 * require defragmentation in iflib_encap(). 4472 */ 4473 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4474 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4475 } 4476 if (scctx->isc_rss_table_size == 0) 4477 scctx->isc_rss_table_size = 64; 4478 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4479 4480 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4481 /* XXX format name */ 4482 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4483 NULL, NULL, "admin"); 4484 4485 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4486 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4487 device_printf(dev, "Unable to fetch CPU list\n"); 4488 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4489 } 4490 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4491 4492 /* 4493 ** Now set up MSI or MSI-X, should return us the number of supported 4494 ** vectors (will be 1 for a legacy interrupt and MSI). 4495 */ 4496 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4497 msix = scctx->isc_vectors; 4498 } else if (scctx->isc_msix_bar != 0) 4499 /* 4500 * The simple fact that isc_msix_bar is not 0 does not mean we 4501 * we have a good value there that is known to work. 4502 */ 4503 msix = iflib_msix_init(ctx); 4504 else { 4505 scctx->isc_vectors = 1; 4506 scctx->isc_ntxqsets = 1; 4507 scctx->isc_nrxqsets = 1; 4508 scctx->isc_intr = IFLIB_INTR_LEGACY; 4509 msix = 0; 4510 } 4511 /* Get memory for the station queues */ 4512 if ((err = iflib_queues_alloc(ctx))) { 4513 device_printf(dev, "Unable to allocate queue memory\n"); 4514 goto fail_intr_free; 4515 } 4516 4517 if ((err = iflib_qset_structures_setup(ctx))) 4518 goto fail_queues; 4519 4520 /* 4521 * Group taskqueues aren't properly set up until SMP is started, 4522 * so we disable interrupts until we can handle them post 4523 * SI_SUB_SMP. 4524 * 4525 * XXX: disabling interrupts doesn't actually work, at least for 4526 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4527 * we do null handling and depend on this not causing too large an 4528 * interrupt storm. 4529 */ 4530 IFDI_INTR_DISABLE(ctx); 4531 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4532 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4533 goto fail_queues; 4534 } 4535 if (msix <= 1) { 4536 rid = 0; 4537 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4538 MPASS(msix == 1); 4539 rid = 1; 4540 } 4541 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4542 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4543 goto fail_queues; 4544 } 4545 } 4546 4547 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4548 4549 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4550 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4551 goto fail_detach; 4552 } 4553 4554 /* 4555 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4556 * This must appear after the call to ether_ifattach() because 4557 * ether_ifattach() sets if_hdrlen to the default value. 4558 */ 4559 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4560 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4561 4562 if ((err = iflib_netmap_attach(ctx))) { 4563 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4564 goto fail_detach; 4565 } 4566 *ctxp = ctx; 4567 4568 NETDUMP_SET(ctx->ifc_ifp, iflib); 4569 4570 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4571 iflib_add_device_sysctl_post(ctx); 4572 ctx->ifc_flags |= IFC_INIT_DONE; 4573 CTX_UNLOCK(ctx); 4574 return (0); 4575 4576 fail_detach: 4577 ether_ifdetach(ctx->ifc_ifp); 4578 fail_intr_free: 4579 iflib_free_intr_mem(ctx); 4580 fail_queues: 4581 iflib_tx_structures_free(ctx); 4582 iflib_rx_structures_free(ctx); 4583 fail_iflib_detach: 4584 IFDI_DETACH(ctx); 4585 fail_unlock: 4586 CTX_UNLOCK(ctx); 4587 fail_ctx_free: 4588 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4589 free(ctx->ifc_softc, M_IFLIB); 4590 free(ctx, M_IFLIB); 4591 return (err); 4592 } 4593 4594 int 4595 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4596 struct iflib_cloneattach_ctx *clctx) 4597 { 4598 int err; 4599 if_ctx_t ctx; 4600 if_t ifp; 4601 if_softc_ctx_t scctx; 4602 int i; 4603 void *sc; 4604 uint16_t main_txq; 4605 uint16_t main_rxq; 4606 4607 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4608 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4609 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4610 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4611 ctx->ifc_flags |= IFC_PSEUDO; 4612 4613 ctx->ifc_sctx = sctx; 4614 ctx->ifc_softc = sc; 4615 ctx->ifc_dev = dev; 4616 4617 if ((err = iflib_register(ctx)) != 0) { 4618 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4619 goto fail_ctx_free; 4620 } 4621 iflib_add_device_sysctl_pre(ctx); 4622 4623 scctx = &ctx->ifc_softc_ctx; 4624 ifp = ctx->ifc_ifp; 4625 4626 /* 4627 * XXX sanity check that ntxd & nrxd are a power of 2 4628 */ 4629 iflib_reset_qvalues(ctx); 4630 CTX_LOCK(ctx); 4631 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4632 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4633 goto fail_unlock; 4634 } 4635 if (sctx->isc_flags & IFLIB_GEN_MAC) 4636 ether_gen_addr(ifp, &ctx->ifc_mac); 4637 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4638 clctx->cc_params)) != 0) { 4639 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4640 goto fail_ctx_free; 4641 } 4642 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4643 ifmedia_add(&ctx->ifc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 4644 ifmedia_set(&ctx->ifc_media, IFM_ETHER | IFM_AUTO); 4645 4646 #ifdef INVARIANTS 4647 MPASS(scctx->isc_capabilities); 4648 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4649 MPASS(scctx->isc_tx_csum_flags); 4650 #endif 4651 4652 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4653 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4654 4655 ifp->if_flags |= IFF_NOGROUP; 4656 if (sctx->isc_flags & IFLIB_PSEUDO) { 4657 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4658 4659 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4660 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4661 goto fail_detach; 4662 } 4663 *ctxp = ctx; 4664 4665 /* 4666 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4667 * This must appear after the call to ether_ifattach() because 4668 * ether_ifattach() sets if_hdrlen to the default value. 4669 */ 4670 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4671 if_setifheaderlen(ifp, 4672 sizeof(struct ether_vlan_header)); 4673 4674 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4675 iflib_add_device_sysctl_post(ctx); 4676 ctx->ifc_flags |= IFC_INIT_DONE; 4677 return (0); 4678 } 4679 _iflib_pre_assert(scctx); 4680 ctx->ifc_txrx = *scctx->isc_txrx; 4681 4682 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4683 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4684 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4685 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4686 4687 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4688 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4689 4690 /* XXX change for per-queue sizes */ 4691 device_printf(dev, "Using %d tx descriptors and %d rx descriptors\n", 4692 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4693 for (i = 0; i < sctx->isc_nrxqs; i++) { 4694 if (!powerof2(scctx->isc_nrxd[i])) { 4695 /* round down instead? */ 4696 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4697 err = EINVAL; 4698 goto fail_iflib_detach; 4699 } 4700 } 4701 for (i = 0; i < sctx->isc_ntxqs; i++) { 4702 if (!powerof2(scctx->isc_ntxd[i])) { 4703 device_printf(dev, 4704 "# tx descriptors must be a power of 2"); 4705 err = EINVAL; 4706 goto fail_iflib_detach; 4707 } 4708 } 4709 4710 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4711 MAX_SINGLE_PACKET_FRACTION) 4712 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4713 MAX_SINGLE_PACKET_FRACTION); 4714 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4715 MAX_SINGLE_PACKET_FRACTION) 4716 scctx->isc_tx_tso_segments_max = max(1, 4717 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4718 4719 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4720 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4721 /* 4722 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4723 * but some MACs do. 4724 */ 4725 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4726 IP_MAXPACKET)); 4727 /* 4728 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4729 * into account. In the worst case, each of these calls will 4730 * add another mbuf and, thus, the requirement for another DMA 4731 * segment. So for best performance, it doesn't make sense to 4732 * advertize a maximum of TSO segments that typically will 4733 * require defragmentation in iflib_encap(). 4734 */ 4735 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4736 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4737 } 4738 if (scctx->isc_rss_table_size == 0) 4739 scctx->isc_rss_table_size = 64; 4740 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4741 4742 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4743 /* XXX format name */ 4744 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4745 NULL, NULL, "admin"); 4746 4747 /* XXX --- can support > 1 -- but keep it simple for now */ 4748 scctx->isc_intr = IFLIB_INTR_LEGACY; 4749 4750 /* Get memory for the station queues */ 4751 if ((err = iflib_queues_alloc(ctx))) { 4752 device_printf(dev, "Unable to allocate queue memory\n"); 4753 goto fail_iflib_detach; 4754 } 4755 4756 if ((err = iflib_qset_structures_setup(ctx))) { 4757 device_printf(dev, "qset structure setup failed %d\n", err); 4758 goto fail_queues; 4759 } 4760 4761 /* 4762 * XXX What if anything do we want to do about interrupts? 4763 */ 4764 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4765 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4766 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4767 goto fail_detach; 4768 } 4769 4770 /* 4771 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4772 * This must appear after the call to ether_ifattach() because 4773 * ether_ifattach() sets if_hdrlen to the default value. 4774 */ 4775 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4776 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4777 4778 /* XXX handle more than one queue */ 4779 for (i = 0; i < scctx->isc_nrxqsets; i++) 4780 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 4781 4782 *ctxp = ctx; 4783 4784 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4785 iflib_add_device_sysctl_post(ctx); 4786 ctx->ifc_flags |= IFC_INIT_DONE; 4787 CTX_UNLOCK(ctx); 4788 return (0); 4789 fail_detach: 4790 ether_ifdetach(ctx->ifc_ifp); 4791 fail_queues: 4792 iflib_tx_structures_free(ctx); 4793 iflib_rx_structures_free(ctx); 4794 fail_iflib_detach: 4795 IFDI_DETACH(ctx); 4796 fail_unlock: 4797 CTX_UNLOCK(ctx); 4798 fail_ctx_free: 4799 free(ctx->ifc_softc, M_IFLIB); 4800 free(ctx, M_IFLIB); 4801 return (err); 4802 } 4803 4804 int 4805 iflib_pseudo_deregister(if_ctx_t ctx) 4806 { 4807 if_t ifp = ctx->ifc_ifp; 4808 iflib_txq_t txq; 4809 iflib_rxq_t rxq; 4810 int i, j; 4811 struct taskqgroup *tqg; 4812 iflib_fl_t fl; 4813 4814 /* Unregister VLAN events */ 4815 if (ctx->ifc_vlan_attach_event != NULL) 4816 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4817 if (ctx->ifc_vlan_detach_event != NULL) 4818 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4819 4820 ether_ifdetach(ifp); 4821 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4822 CTX_LOCK_DESTROY(ctx); 4823 /* XXX drain any dependent tasks */ 4824 tqg = qgroup_if_io_tqg; 4825 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4826 callout_drain(&txq->ift_timer); 4827 if (txq->ift_task.gt_uniq != NULL) 4828 taskqgroup_detach(tqg, &txq->ift_task); 4829 } 4830 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4831 if (rxq->ifr_task.gt_uniq != NULL) 4832 taskqgroup_detach(tqg, &rxq->ifr_task); 4833 4834 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4835 free(fl->ifl_rx_bitmap, M_IFLIB); 4836 } 4837 tqg = qgroup_if_config_tqg; 4838 if (ctx->ifc_admin_task.gt_uniq != NULL) 4839 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4840 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4841 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4842 4843 if_free(ifp); 4844 4845 iflib_tx_structures_free(ctx); 4846 iflib_rx_structures_free(ctx); 4847 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4848 free(ctx->ifc_softc, M_IFLIB); 4849 free(ctx, M_IFLIB); 4850 return (0); 4851 } 4852 4853 int 4854 iflib_device_attach(device_t dev) 4855 { 4856 if_ctx_t ctx; 4857 if_shared_ctx_t sctx; 4858 4859 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4860 return (ENOTSUP); 4861 4862 pci_enable_busmaster(dev); 4863 4864 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4865 } 4866 4867 int 4868 iflib_device_deregister(if_ctx_t ctx) 4869 { 4870 if_t ifp = ctx->ifc_ifp; 4871 iflib_txq_t txq; 4872 iflib_rxq_t rxq; 4873 device_t dev = ctx->ifc_dev; 4874 int i, j; 4875 struct taskqgroup *tqg; 4876 iflib_fl_t fl; 4877 4878 /* Make sure VLANS are not using driver */ 4879 if (if_vlantrunkinuse(ifp)) { 4880 device_printf(dev, "Vlan in use, detach first\n"); 4881 return (EBUSY); 4882 } 4883 #ifdef PCI_IOV 4884 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 4885 device_printf(dev, "SR-IOV in use; detach first.\n"); 4886 return (EBUSY); 4887 } 4888 #endif 4889 4890 STATE_LOCK(ctx); 4891 ctx->ifc_flags |= IFC_IN_DETACH; 4892 STATE_UNLOCK(ctx); 4893 4894 CTX_LOCK(ctx); 4895 iflib_stop(ctx); 4896 CTX_UNLOCK(ctx); 4897 4898 /* Unregister VLAN events */ 4899 if (ctx->ifc_vlan_attach_event != NULL) 4900 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4901 if (ctx->ifc_vlan_detach_event != NULL) 4902 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4903 4904 iflib_netmap_detach(ifp); 4905 ether_ifdetach(ifp); 4906 if (ctx->ifc_led_dev != NULL) 4907 led_destroy(ctx->ifc_led_dev); 4908 /* XXX drain any dependent tasks */ 4909 tqg = qgroup_if_io_tqg; 4910 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4911 callout_drain(&txq->ift_timer); 4912 if (txq->ift_task.gt_uniq != NULL) 4913 taskqgroup_detach(tqg, &txq->ift_task); 4914 } 4915 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4916 if (rxq->ifr_task.gt_uniq != NULL) 4917 taskqgroup_detach(tqg, &rxq->ifr_task); 4918 4919 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4920 free(fl->ifl_rx_bitmap, M_IFLIB); 4921 } 4922 tqg = qgroup_if_config_tqg; 4923 if (ctx->ifc_admin_task.gt_uniq != NULL) 4924 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4925 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4926 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4927 CTX_LOCK(ctx); 4928 IFDI_DETACH(ctx); 4929 CTX_UNLOCK(ctx); 4930 4931 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4932 CTX_LOCK_DESTROY(ctx); 4933 device_set_softc(ctx->ifc_dev, NULL); 4934 iflib_free_intr_mem(ctx); 4935 4936 bus_generic_detach(dev); 4937 if_free(ifp); 4938 4939 iflib_tx_structures_free(ctx); 4940 iflib_rx_structures_free(ctx); 4941 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4942 free(ctx->ifc_softc, M_IFLIB); 4943 STATE_LOCK_DESTROY(ctx); 4944 free(ctx, M_IFLIB); 4945 return (0); 4946 } 4947 4948 static void 4949 iflib_free_intr_mem(if_ctx_t ctx) 4950 { 4951 4952 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4953 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4954 } 4955 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4956 pci_release_msi(ctx->ifc_dev); 4957 } 4958 if (ctx->ifc_msix_mem != NULL) { 4959 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4960 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 4961 ctx->ifc_msix_mem = NULL; 4962 } 4963 } 4964 4965 int 4966 iflib_device_detach(device_t dev) 4967 { 4968 if_ctx_t ctx = device_get_softc(dev); 4969 4970 return (iflib_device_deregister(ctx)); 4971 } 4972 4973 int 4974 iflib_device_suspend(device_t dev) 4975 { 4976 if_ctx_t ctx = device_get_softc(dev); 4977 4978 CTX_LOCK(ctx); 4979 IFDI_SUSPEND(ctx); 4980 CTX_UNLOCK(ctx); 4981 4982 return bus_generic_suspend(dev); 4983 } 4984 int 4985 iflib_device_shutdown(device_t dev) 4986 { 4987 if_ctx_t ctx = device_get_softc(dev); 4988 4989 CTX_LOCK(ctx); 4990 IFDI_SHUTDOWN(ctx); 4991 CTX_UNLOCK(ctx); 4992 4993 return bus_generic_suspend(dev); 4994 } 4995 4996 4997 int 4998 iflib_device_resume(device_t dev) 4999 { 5000 if_ctx_t ctx = device_get_softc(dev); 5001 iflib_txq_t txq = ctx->ifc_txqs; 5002 5003 CTX_LOCK(ctx); 5004 IFDI_RESUME(ctx); 5005 iflib_if_init_locked(ctx); 5006 CTX_UNLOCK(ctx); 5007 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5008 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5009 5010 return (bus_generic_resume(dev)); 5011 } 5012 5013 int 5014 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5015 { 5016 int error; 5017 if_ctx_t ctx = device_get_softc(dev); 5018 5019 CTX_LOCK(ctx); 5020 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5021 CTX_UNLOCK(ctx); 5022 5023 return (error); 5024 } 5025 5026 void 5027 iflib_device_iov_uninit(device_t dev) 5028 { 5029 if_ctx_t ctx = device_get_softc(dev); 5030 5031 CTX_LOCK(ctx); 5032 IFDI_IOV_UNINIT(ctx); 5033 CTX_UNLOCK(ctx); 5034 } 5035 5036 int 5037 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5038 { 5039 int error; 5040 if_ctx_t ctx = device_get_softc(dev); 5041 5042 CTX_LOCK(ctx); 5043 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5044 CTX_UNLOCK(ctx); 5045 5046 return (error); 5047 } 5048 5049 /********************************************************************* 5050 * 5051 * MODULE FUNCTION DEFINITIONS 5052 * 5053 **********************************************************************/ 5054 5055 /* 5056 * - Start a fast taskqueue thread for each core 5057 * - Start a taskqueue for control operations 5058 */ 5059 static int 5060 iflib_module_init(void) 5061 { 5062 return (0); 5063 } 5064 5065 static int 5066 iflib_module_event_handler(module_t mod, int what, void *arg) 5067 { 5068 int err; 5069 5070 switch (what) { 5071 case MOD_LOAD: 5072 if ((err = iflib_module_init()) != 0) 5073 return (err); 5074 break; 5075 case MOD_UNLOAD: 5076 return (EBUSY); 5077 default: 5078 return (EOPNOTSUPP); 5079 } 5080 5081 return (0); 5082 } 5083 5084 /********************************************************************* 5085 * 5086 * PUBLIC FUNCTION DEFINITIONS 5087 * ordered as in iflib.h 5088 * 5089 **********************************************************************/ 5090 5091 5092 static void 5093 _iflib_assert(if_shared_ctx_t sctx) 5094 { 5095 MPASS(sctx->isc_tx_maxsize); 5096 MPASS(sctx->isc_tx_maxsegsize); 5097 5098 MPASS(sctx->isc_rx_maxsize); 5099 MPASS(sctx->isc_rx_nsegments); 5100 MPASS(sctx->isc_rx_maxsegsize); 5101 5102 MPASS(sctx->isc_nrxd_min[0]); 5103 MPASS(sctx->isc_nrxd_max[0]); 5104 MPASS(sctx->isc_nrxd_default[0]); 5105 MPASS(sctx->isc_ntxd_min[0]); 5106 MPASS(sctx->isc_ntxd_max[0]); 5107 MPASS(sctx->isc_ntxd_default[0]); 5108 } 5109 5110 static void 5111 _iflib_pre_assert(if_softc_ctx_t scctx) 5112 { 5113 5114 MPASS(scctx->isc_txrx->ift_txd_encap); 5115 MPASS(scctx->isc_txrx->ift_txd_flush); 5116 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5117 MPASS(scctx->isc_txrx->ift_rxd_available); 5118 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5119 MPASS(scctx->isc_txrx->ift_rxd_refill); 5120 MPASS(scctx->isc_txrx->ift_rxd_flush); 5121 } 5122 5123 static int 5124 iflib_register(if_ctx_t ctx) 5125 { 5126 if_shared_ctx_t sctx = ctx->ifc_sctx; 5127 driver_t *driver = sctx->isc_driver; 5128 device_t dev = ctx->ifc_dev; 5129 if_t ifp; 5130 5131 _iflib_assert(sctx); 5132 5133 CTX_LOCK_INIT(ctx); 5134 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5135 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER); 5136 if (ifp == NULL) { 5137 device_printf(dev, "can not allocate ifnet structure\n"); 5138 return (ENOMEM); 5139 } 5140 5141 /* 5142 * Initialize our context's device specific methods 5143 */ 5144 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5145 kobj_class_compile((kobj_class_t) driver); 5146 driver->refs++; 5147 5148 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5149 if_setsoftc(ifp, ctx); 5150 if_setdev(ifp, dev); 5151 if_setinitfn(ifp, iflib_if_init); 5152 if_setioctlfn(ifp, iflib_if_ioctl); 5153 #ifdef ALTQ 5154 if_setstartfn(ifp, iflib_altq_if_start); 5155 if_settransmitfn(ifp, iflib_altq_if_transmit); 5156 if_setsendqready(ifp); 5157 #else 5158 if_settransmitfn(ifp, iflib_if_transmit); 5159 #endif 5160 if_setqflushfn(ifp, iflib_if_qflush); 5161 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 5162 5163 ctx->ifc_vlan_attach_event = 5164 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5165 EVENTHANDLER_PRI_FIRST); 5166 ctx->ifc_vlan_detach_event = 5167 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5168 EVENTHANDLER_PRI_FIRST); 5169 5170 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 5171 iflib_media_change, iflib_media_status); 5172 5173 return (0); 5174 } 5175 5176 5177 static int 5178 iflib_queues_alloc(if_ctx_t ctx) 5179 { 5180 if_shared_ctx_t sctx = ctx->ifc_sctx; 5181 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5182 device_t dev = ctx->ifc_dev; 5183 int nrxqsets = scctx->isc_nrxqsets; 5184 int ntxqsets = scctx->isc_ntxqsets; 5185 iflib_txq_t txq; 5186 iflib_rxq_t rxq; 5187 iflib_fl_t fl = NULL; 5188 int i, j, cpu, err, txconf, rxconf; 5189 iflib_dma_info_t ifdip; 5190 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5191 uint32_t *txqsizes = scctx->isc_txqsizes; 5192 uint8_t nrxqs = sctx->isc_nrxqs; 5193 uint8_t ntxqs = sctx->isc_ntxqs; 5194 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5195 caddr_t *vaddrs; 5196 uint64_t *paddrs; 5197 5198 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5199 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5200 5201 /* Allocate the TX ring struct memory */ 5202 if (!(ctx->ifc_txqs = 5203 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5204 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5205 device_printf(dev, "Unable to allocate TX ring memory\n"); 5206 err = ENOMEM; 5207 goto fail; 5208 } 5209 5210 /* Now allocate the RX */ 5211 if (!(ctx->ifc_rxqs = 5212 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5213 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5214 device_printf(dev, "Unable to allocate RX ring memory\n"); 5215 err = ENOMEM; 5216 goto rx_fail; 5217 } 5218 5219 txq = ctx->ifc_txqs; 5220 rxq = ctx->ifc_rxqs; 5221 5222 /* 5223 * XXX handle allocation failure 5224 */ 5225 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5226 /* Set up some basics */ 5227 5228 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5229 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5230 device_printf(dev, 5231 "Unable to allocate TX DMA info memory\n"); 5232 err = ENOMEM; 5233 goto err_tx_desc; 5234 } 5235 txq->ift_ifdi = ifdip; 5236 for (j = 0; j < ntxqs; j++, ifdip++) { 5237 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5238 device_printf(dev, 5239 "Unable to allocate TX descriptors\n"); 5240 err = ENOMEM; 5241 goto err_tx_desc; 5242 } 5243 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5244 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5245 } 5246 txq->ift_ctx = ctx; 5247 txq->ift_id = i; 5248 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5249 txq->ift_br_offset = 1; 5250 } else { 5251 txq->ift_br_offset = 0; 5252 } 5253 /* XXX fix this */ 5254 txq->ift_timer.c_cpu = cpu; 5255 5256 if (iflib_txsd_alloc(txq)) { 5257 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5258 err = ENOMEM; 5259 goto err_tx_desc; 5260 } 5261 5262 /* Initialize the TX lock */ 5263 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 5264 device_get_nameunit(dev), txq->ift_id); 5265 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5266 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5267 5268 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 5269 device_get_nameunit(dev), txq->ift_id); 5270 5271 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5272 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5273 if (err) { 5274 /* XXX free any allocated rings */ 5275 device_printf(dev, "Unable to allocate buf_ring\n"); 5276 goto err_tx_desc; 5277 } 5278 } 5279 5280 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5281 /* Set up some basics */ 5282 5283 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5284 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5285 device_printf(dev, 5286 "Unable to allocate RX DMA info memory\n"); 5287 err = ENOMEM; 5288 goto err_tx_desc; 5289 } 5290 5291 rxq->ifr_ifdi = ifdip; 5292 /* XXX this needs to be changed if #rx queues != #tx queues */ 5293 rxq->ifr_ntxqirq = 1; 5294 rxq->ifr_txqid[0] = i; 5295 for (j = 0; j < nrxqs; j++, ifdip++) { 5296 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5297 device_printf(dev, 5298 "Unable to allocate RX descriptors\n"); 5299 err = ENOMEM; 5300 goto err_tx_desc; 5301 } 5302 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5303 } 5304 rxq->ifr_ctx = ctx; 5305 rxq->ifr_id = i; 5306 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5307 rxq->ifr_fl_offset = 1; 5308 } else { 5309 rxq->ifr_fl_offset = 0; 5310 } 5311 rxq->ifr_nfl = nfree_lists; 5312 if (!(fl = 5313 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5314 device_printf(dev, "Unable to allocate free list memory\n"); 5315 err = ENOMEM; 5316 goto err_tx_desc; 5317 } 5318 rxq->ifr_fl = fl; 5319 for (j = 0; j < nfree_lists; j++) { 5320 fl[j].ifl_rxq = rxq; 5321 fl[j].ifl_id = j; 5322 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5323 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5324 } 5325 /* Allocate receive buffers for the ring */ 5326 if (iflib_rxsd_alloc(rxq)) { 5327 device_printf(dev, 5328 "Critical Failure setting up receive buffers\n"); 5329 err = ENOMEM; 5330 goto err_rx_desc; 5331 } 5332 5333 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5334 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5335 M_WAITOK); 5336 } 5337 5338 /* TXQs */ 5339 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5340 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5341 for (i = 0; i < ntxqsets; i++) { 5342 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5343 5344 for (j = 0; j < ntxqs; j++, di++) { 5345 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5346 paddrs[i*ntxqs + j] = di->idi_paddr; 5347 } 5348 } 5349 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5350 device_printf(ctx->ifc_dev, 5351 "Unable to allocate device TX queue\n"); 5352 iflib_tx_structures_free(ctx); 5353 free(vaddrs, M_IFLIB); 5354 free(paddrs, M_IFLIB); 5355 goto err_rx_desc; 5356 } 5357 free(vaddrs, M_IFLIB); 5358 free(paddrs, M_IFLIB); 5359 5360 /* RXQs */ 5361 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5362 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5363 for (i = 0; i < nrxqsets; i++) { 5364 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5365 5366 for (j = 0; j < nrxqs; j++, di++) { 5367 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5368 paddrs[i*nrxqs + j] = di->idi_paddr; 5369 } 5370 } 5371 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5372 device_printf(ctx->ifc_dev, 5373 "Unable to allocate device RX queue\n"); 5374 iflib_tx_structures_free(ctx); 5375 free(vaddrs, M_IFLIB); 5376 free(paddrs, M_IFLIB); 5377 goto err_rx_desc; 5378 } 5379 free(vaddrs, M_IFLIB); 5380 free(paddrs, M_IFLIB); 5381 5382 return (0); 5383 5384 /* XXX handle allocation failure changes */ 5385 err_rx_desc: 5386 err_tx_desc: 5387 rx_fail: 5388 if (ctx->ifc_rxqs != NULL) 5389 free(ctx->ifc_rxqs, M_IFLIB); 5390 ctx->ifc_rxqs = NULL; 5391 if (ctx->ifc_txqs != NULL) 5392 free(ctx->ifc_txqs, M_IFLIB); 5393 ctx->ifc_txqs = NULL; 5394 fail: 5395 return (err); 5396 } 5397 5398 static int 5399 iflib_tx_structures_setup(if_ctx_t ctx) 5400 { 5401 iflib_txq_t txq = ctx->ifc_txqs; 5402 int i; 5403 5404 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5405 iflib_txq_setup(txq); 5406 5407 return (0); 5408 } 5409 5410 static void 5411 iflib_tx_structures_free(if_ctx_t ctx) 5412 { 5413 iflib_txq_t txq = ctx->ifc_txqs; 5414 if_shared_ctx_t sctx = ctx->ifc_sctx; 5415 int i, j; 5416 5417 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5418 iflib_txq_destroy(txq); 5419 for (j = 0; j < sctx->isc_ntxqs; j++) 5420 iflib_dma_free(&txq->ift_ifdi[j]); 5421 } 5422 free(ctx->ifc_txqs, M_IFLIB); 5423 ctx->ifc_txqs = NULL; 5424 IFDI_QUEUES_FREE(ctx); 5425 } 5426 5427 /********************************************************************* 5428 * 5429 * Initialize all receive rings. 5430 * 5431 **********************************************************************/ 5432 static int 5433 iflib_rx_structures_setup(if_ctx_t ctx) 5434 { 5435 iflib_rxq_t rxq = ctx->ifc_rxqs; 5436 int q; 5437 #if defined(INET6) || defined(INET) 5438 int i, err; 5439 #endif 5440 5441 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5442 #if defined(INET6) || defined(INET) 5443 tcp_lro_free(&rxq->ifr_lc); 5444 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5445 TCP_LRO_ENTRIES, min(1024, 5446 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 5447 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 5448 goto fail; 5449 } 5450 rxq->ifr_lro_enabled = TRUE; 5451 #endif 5452 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5453 } 5454 return (0); 5455 #if defined(INET6) || defined(INET) 5456 fail: 5457 /* 5458 * Free RX software descriptors allocated so far, we will only handle 5459 * the rings that completed, the failing case will have 5460 * cleaned up for itself. 'q' failed, so its the terminus. 5461 */ 5462 rxq = ctx->ifc_rxqs; 5463 for (i = 0; i < q; ++i, rxq++) { 5464 iflib_rx_sds_free(rxq); 5465 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 5466 } 5467 return (err); 5468 #endif 5469 } 5470 5471 /********************************************************************* 5472 * 5473 * Free all receive rings. 5474 * 5475 **********************************************************************/ 5476 static void 5477 iflib_rx_structures_free(if_ctx_t ctx) 5478 { 5479 iflib_rxq_t rxq = ctx->ifc_rxqs; 5480 5481 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5482 iflib_rx_sds_free(rxq); 5483 } 5484 free(ctx->ifc_rxqs, M_IFLIB); 5485 ctx->ifc_rxqs = NULL; 5486 } 5487 5488 static int 5489 iflib_qset_structures_setup(if_ctx_t ctx) 5490 { 5491 int err; 5492 5493 /* 5494 * It is expected that the caller takes care of freeing queues if this 5495 * fails. 5496 */ 5497 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5498 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5499 return (err); 5500 } 5501 5502 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5503 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5504 5505 return (err); 5506 } 5507 5508 int 5509 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5510 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5511 { 5512 5513 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5514 } 5515 5516 #ifdef SMP 5517 static int 5518 find_nth(if_ctx_t ctx, int qid) 5519 { 5520 cpuset_t cpus; 5521 int i, cpuid, eqid, count; 5522 5523 CPU_COPY(&ctx->ifc_cpus, &cpus); 5524 count = CPU_COUNT(&cpus); 5525 eqid = qid % count; 5526 /* clear up to the qid'th bit */ 5527 for (i = 0; i < eqid; i++) { 5528 cpuid = CPU_FFS(&cpus); 5529 MPASS(cpuid != 0); 5530 CPU_CLR(cpuid-1, &cpus); 5531 } 5532 cpuid = CPU_FFS(&cpus); 5533 MPASS(cpuid != 0); 5534 return (cpuid-1); 5535 } 5536 5537 #ifdef SCHED_ULE 5538 extern struct cpu_group *cpu_top; /* CPU topology */ 5539 5540 static int 5541 find_child_with_core(int cpu, struct cpu_group *grp) 5542 { 5543 int i; 5544 5545 if (grp->cg_children == 0) 5546 return -1; 5547 5548 MPASS(grp->cg_child); 5549 for (i = 0; i < grp->cg_children; i++) { 5550 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5551 return i; 5552 } 5553 5554 return -1; 5555 } 5556 5557 /* 5558 * Find the nth "close" core to the specified core 5559 * "close" is defined as the deepest level that shares 5560 * at least an L2 cache. With threads, this will be 5561 * threads on the same core. If the sahred cache is L3 5562 * or higher, simply returns the same core. 5563 */ 5564 static int 5565 find_close_core(int cpu, int core_offset) 5566 { 5567 struct cpu_group *grp; 5568 int i; 5569 int fcpu; 5570 cpuset_t cs; 5571 5572 grp = cpu_top; 5573 if (grp == NULL) 5574 return cpu; 5575 i = 0; 5576 while ((i = find_child_with_core(cpu, grp)) != -1) { 5577 /* If the child only has one cpu, don't descend */ 5578 if (grp->cg_child[i].cg_count <= 1) 5579 break; 5580 grp = &grp->cg_child[i]; 5581 } 5582 5583 /* If they don't share at least an L2 cache, use the same CPU */ 5584 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5585 return cpu; 5586 5587 /* Now pick one */ 5588 CPU_COPY(&grp->cg_mask, &cs); 5589 5590 /* Add the selected CPU offset to core offset. */ 5591 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5592 if (fcpu - 1 == cpu) 5593 break; 5594 CPU_CLR(fcpu - 1, &cs); 5595 } 5596 MPASS(fcpu); 5597 5598 core_offset += i; 5599 5600 CPU_COPY(&grp->cg_mask, &cs); 5601 for (i = core_offset % grp->cg_count; i > 0; i--) { 5602 MPASS(CPU_FFS(&cs)); 5603 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5604 } 5605 MPASS(CPU_FFS(&cs)); 5606 return CPU_FFS(&cs) - 1; 5607 } 5608 #else 5609 static int 5610 find_close_core(int cpu, int core_offset __unused) 5611 { 5612 return cpu; 5613 } 5614 #endif 5615 5616 static int 5617 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5618 { 5619 switch (type) { 5620 case IFLIB_INTR_TX: 5621 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5622 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5623 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5624 case IFLIB_INTR_RX: 5625 case IFLIB_INTR_RXTX: 5626 /* RX queues get the specified core */ 5627 return qid / CPU_COUNT(&ctx->ifc_cpus); 5628 default: 5629 return -1; 5630 } 5631 } 5632 #else 5633 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5634 #define find_close_core(cpuid, tid) CPU_FIRST() 5635 #define find_nth(ctx, gid) CPU_FIRST() 5636 #endif 5637 5638 /* Just to avoid copy/paste */ 5639 static inline int 5640 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 5641 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 5642 const char *name) 5643 { 5644 device_t dev; 5645 int err, cpuid, tid; 5646 5647 dev = ctx->ifc_dev; 5648 cpuid = find_nth(ctx, qid); 5649 tid = get_core_offset(ctx, type, qid); 5650 MPASS(tid >= 0); 5651 cpuid = find_close_core(cpuid, tid); 5652 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res, 5653 name); 5654 if (err) { 5655 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 5656 return (err); 5657 } 5658 #ifdef notyet 5659 if (cpuid > ctx->ifc_cpuid_highest) 5660 ctx->ifc_cpuid_highest = cpuid; 5661 #endif 5662 return 0; 5663 } 5664 5665 int 5666 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5667 iflib_intr_type_t type, driver_filter_t *filter, 5668 void *filter_arg, int qid, const char *name) 5669 { 5670 device_t dev; 5671 struct grouptask *gtask; 5672 struct taskqgroup *tqg; 5673 iflib_filter_info_t info; 5674 gtask_fn_t *fn; 5675 int tqrid, err; 5676 driver_filter_t *intr_fast; 5677 void *q; 5678 5679 info = &ctx->ifc_filter_info; 5680 tqrid = rid; 5681 5682 switch (type) { 5683 /* XXX merge tx/rx for netmap? */ 5684 case IFLIB_INTR_TX: 5685 q = &ctx->ifc_txqs[qid]; 5686 info = &ctx->ifc_txqs[qid].ift_filter_info; 5687 gtask = &ctx->ifc_txqs[qid].ift_task; 5688 tqg = qgroup_if_io_tqg; 5689 fn = _task_fn_tx; 5690 intr_fast = iflib_fast_intr; 5691 GROUPTASK_INIT(gtask, 0, fn, q); 5692 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 5693 break; 5694 case IFLIB_INTR_RX: 5695 q = &ctx->ifc_rxqs[qid]; 5696 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5697 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5698 tqg = qgroup_if_io_tqg; 5699 fn = _task_fn_rx; 5700 intr_fast = iflib_fast_intr; 5701 GROUPTASK_INIT(gtask, 0, fn, q); 5702 break; 5703 case IFLIB_INTR_RXTX: 5704 q = &ctx->ifc_rxqs[qid]; 5705 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5706 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5707 tqg = qgroup_if_io_tqg; 5708 fn = _task_fn_rx; 5709 intr_fast = iflib_fast_intr_rxtx; 5710 GROUPTASK_INIT(gtask, 0, fn, q); 5711 break; 5712 case IFLIB_INTR_ADMIN: 5713 q = ctx; 5714 tqrid = -1; 5715 info = &ctx->ifc_filter_info; 5716 gtask = &ctx->ifc_admin_task; 5717 tqg = qgroup_if_config_tqg; 5718 fn = _task_fn_admin; 5719 intr_fast = iflib_fast_intr_ctx; 5720 break; 5721 default: 5722 panic("unknown net intr type"); 5723 } 5724 5725 info->ifi_filter = filter; 5726 info->ifi_filter_arg = filter_arg; 5727 info->ifi_task = gtask; 5728 info->ifi_ctx = q; 5729 5730 dev = ctx->ifc_dev; 5731 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 5732 if (err != 0) { 5733 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 5734 return (err); 5735 } 5736 if (type == IFLIB_INTR_ADMIN) 5737 return (0); 5738 5739 if (tqrid != -1) { 5740 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 5741 q, name); 5742 if (err) 5743 return (err); 5744 } else { 5745 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 5746 } 5747 5748 return (0); 5749 } 5750 5751 void 5752 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 5753 { 5754 struct grouptask *gtask; 5755 struct taskqgroup *tqg; 5756 gtask_fn_t *fn; 5757 void *q; 5758 int err; 5759 5760 switch (type) { 5761 case IFLIB_INTR_TX: 5762 q = &ctx->ifc_txqs[qid]; 5763 gtask = &ctx->ifc_txqs[qid].ift_task; 5764 tqg = qgroup_if_io_tqg; 5765 fn = _task_fn_tx; 5766 break; 5767 case IFLIB_INTR_RX: 5768 q = &ctx->ifc_rxqs[qid]; 5769 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5770 tqg = qgroup_if_io_tqg; 5771 fn = _task_fn_rx; 5772 break; 5773 case IFLIB_INTR_IOV: 5774 q = ctx; 5775 gtask = &ctx->ifc_vflr_task; 5776 tqg = qgroup_if_config_tqg; 5777 fn = _task_fn_iov; 5778 break; 5779 default: 5780 panic("unknown net intr type"); 5781 } 5782 GROUPTASK_INIT(gtask, 0, fn, q); 5783 if (irq != NULL) { 5784 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 5785 q, name); 5786 if (err) 5787 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev, 5788 irq->ii_res, name); 5789 } else { 5790 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name); 5791 } 5792 } 5793 5794 void 5795 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5796 { 5797 5798 if (irq->ii_tag) 5799 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5800 5801 if (irq->ii_res) 5802 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 5803 rman_get_rid(irq->ii_res), irq->ii_res); 5804 } 5805 5806 static int 5807 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 5808 { 5809 iflib_txq_t txq = ctx->ifc_txqs; 5810 iflib_rxq_t rxq = ctx->ifc_rxqs; 5811 if_irq_t irq = &ctx->ifc_legacy_irq; 5812 iflib_filter_info_t info; 5813 device_t dev; 5814 struct grouptask *gtask; 5815 struct resource *res; 5816 struct taskqgroup *tqg; 5817 gtask_fn_t *fn; 5818 int tqrid; 5819 void *q; 5820 int err; 5821 5822 q = &ctx->ifc_rxqs[0]; 5823 info = &rxq[0].ifr_filter_info; 5824 gtask = &rxq[0].ifr_task; 5825 tqg = qgroup_if_io_tqg; 5826 tqrid = irq->ii_rid = *rid; 5827 fn = _task_fn_rx; 5828 5829 ctx->ifc_flags |= IFC_LEGACY; 5830 info->ifi_filter = filter; 5831 info->ifi_filter_arg = filter_arg; 5832 info->ifi_task = gtask; 5833 info->ifi_ctx = ctx; 5834 5835 dev = ctx->ifc_dev; 5836 /* We allocate a single interrupt resource */ 5837 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5838 return (err); 5839 GROUPTASK_INIT(gtask, 0, fn, q); 5840 res = irq->ii_res; 5841 taskqgroup_attach(tqg, gtask, q, dev, res, name); 5842 5843 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5844 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 5845 "tx"); 5846 return (0); 5847 } 5848 5849 void 5850 iflib_led_create(if_ctx_t ctx) 5851 { 5852 5853 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5854 device_get_nameunit(ctx->ifc_dev)); 5855 } 5856 5857 void 5858 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5859 { 5860 5861 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5862 } 5863 5864 void 5865 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5866 { 5867 5868 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5869 } 5870 5871 void 5872 iflib_admin_intr_deferred(if_ctx_t ctx) 5873 { 5874 #ifdef INVARIANTS 5875 struct grouptask *gtask; 5876 5877 gtask = &ctx->ifc_admin_task; 5878 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 5879 #endif 5880 5881 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5882 } 5883 5884 void 5885 iflib_iov_intr_deferred(if_ctx_t ctx) 5886 { 5887 5888 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5889 } 5890 5891 void 5892 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5893 { 5894 5895 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 5896 name); 5897 } 5898 5899 void 5900 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 5901 const char *name) 5902 { 5903 5904 GROUPTASK_INIT(gtask, 0, fn, ctx); 5905 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 5906 name); 5907 } 5908 5909 void 5910 iflib_config_gtask_deinit(struct grouptask *gtask) 5911 { 5912 5913 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5914 } 5915 5916 void 5917 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5918 { 5919 if_t ifp = ctx->ifc_ifp; 5920 iflib_txq_t txq = ctx->ifc_txqs; 5921 5922 if_setbaudrate(ifp, baudrate); 5923 if (baudrate >= IF_Gbps(10)) { 5924 STATE_LOCK(ctx); 5925 ctx->ifc_flags |= IFC_PREFETCH; 5926 STATE_UNLOCK(ctx); 5927 } 5928 /* If link down, disable watchdog */ 5929 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5930 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5931 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5932 } 5933 ctx->ifc_link_state = link_state; 5934 if_link_state_change(ifp, link_state); 5935 } 5936 5937 static int 5938 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5939 { 5940 int credits; 5941 #ifdef INVARIANTS 5942 int credits_pre = txq->ift_cidx_processed; 5943 #endif 5944 5945 if (ctx->isc_txd_credits_update == NULL) 5946 return (0); 5947 5948 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 5949 BUS_DMASYNC_POSTREAD); 5950 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5951 return (0); 5952 5953 txq->ift_processed += credits; 5954 txq->ift_cidx_processed += credits; 5955 5956 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5957 if (txq->ift_cidx_processed >= txq->ift_size) 5958 txq->ift_cidx_processed -= txq->ift_size; 5959 return (credits); 5960 } 5961 5962 static int 5963 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5964 { 5965 iflib_fl_t fl; 5966 u_int i; 5967 5968 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 5969 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 5970 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 5971 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 5972 budget)); 5973 } 5974 5975 void 5976 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 5977 const char *description, if_int_delay_info_t info, 5978 int offset, int value) 5979 { 5980 info->iidi_ctx = ctx; 5981 info->iidi_offset = offset; 5982 info->iidi_value = value; 5983 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 5984 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 5985 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5986 info, 0, iflib_sysctl_int_delay, "I", description); 5987 } 5988 5989 struct sx * 5990 iflib_ctx_lock_get(if_ctx_t ctx) 5991 { 5992 5993 return (&ctx->ifc_ctx_sx); 5994 } 5995 5996 static int 5997 iflib_msix_init(if_ctx_t ctx) 5998 { 5999 device_t dev = ctx->ifc_dev; 6000 if_shared_ctx_t sctx = ctx->ifc_sctx; 6001 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6002 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 6003 int iflib_num_tx_queues, iflib_num_rx_queues; 6004 int err, admincnt, bar; 6005 6006 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6007 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6008 6009 if (bootverbose) 6010 device_printf(dev, "msix_init qsets capped at %d\n", 6011 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6012 6013 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6014 admincnt = sctx->isc_admin_intrcnt; 6015 /* Override by tuneable */ 6016 if (scctx->isc_disable_msix) 6017 goto msi; 6018 6019 /* First try MSI-X */ 6020 if ((msgs = pci_msix_count(dev)) == 0) { 6021 if (bootverbose) 6022 device_printf(dev, "MSI-X not supported or disabled\n"); 6023 goto msi; 6024 } 6025 /* 6026 * bar == -1 => "trust me I know what I'm doing" 6027 * Some drivers are for hardware that is so shoddily 6028 * documented that no one knows which bars are which 6029 * so the developer has to map all bars. This hack 6030 * allows shoddy garbage to use MSI-X in this framework. 6031 */ 6032 if (bar != -1) { 6033 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6034 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6035 if (ctx->ifc_msix_mem == NULL) { 6036 device_printf(dev, "Unable to map MSI-X table\n"); 6037 goto msi; 6038 } 6039 } 6040 #if IFLIB_DEBUG 6041 /* use only 1 qset in debug mode */ 6042 queuemsgs = min(msgs - admincnt, 1); 6043 #else 6044 queuemsgs = msgs - admincnt; 6045 #endif 6046 #ifdef RSS 6047 queues = imin(queuemsgs, rss_getnumbuckets()); 6048 #else 6049 queues = queuemsgs; 6050 #endif 6051 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6052 if (bootverbose) 6053 device_printf(dev, 6054 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6055 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6056 #ifdef RSS 6057 /* If we're doing RSS, clamp at the number of RSS buckets */ 6058 if (queues > rss_getnumbuckets()) 6059 queues = rss_getnumbuckets(); 6060 #endif 6061 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6062 rx_queues = iflib_num_rx_queues; 6063 else 6064 rx_queues = queues; 6065 6066 if (rx_queues > scctx->isc_nrxqsets) 6067 rx_queues = scctx->isc_nrxqsets; 6068 6069 /* 6070 * We want this to be all logical CPUs by default 6071 */ 6072 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6073 tx_queues = iflib_num_tx_queues; 6074 else 6075 tx_queues = mp_ncpus; 6076 6077 if (tx_queues > scctx->isc_ntxqsets) 6078 tx_queues = scctx->isc_ntxqsets; 6079 6080 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6081 #ifdef INVARIANTS 6082 if (tx_queues != rx_queues) 6083 device_printf(dev, 6084 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6085 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6086 #endif 6087 tx_queues = min(rx_queues, tx_queues); 6088 rx_queues = min(rx_queues, tx_queues); 6089 } 6090 6091 device_printf(dev, "Using %d rx queues %d tx queues\n", 6092 rx_queues, tx_queues); 6093 6094 vectors = rx_queues + admincnt; 6095 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6096 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6097 vectors); 6098 scctx->isc_vectors = vectors; 6099 scctx->isc_nrxqsets = rx_queues; 6100 scctx->isc_ntxqsets = tx_queues; 6101 scctx->isc_intr = IFLIB_INTR_MSIX; 6102 6103 return (vectors); 6104 } else { 6105 device_printf(dev, 6106 "failed to allocate %d MSI-X vectors, err: %d - using MSI\n", 6107 vectors, err); 6108 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6109 ctx->ifc_msix_mem); 6110 ctx->ifc_msix_mem = NULL; 6111 } 6112 msi: 6113 vectors = pci_msi_count(dev); 6114 scctx->isc_nrxqsets = 1; 6115 scctx->isc_ntxqsets = 1; 6116 scctx->isc_vectors = vectors; 6117 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6118 device_printf(dev,"Using an MSI interrupt\n"); 6119 scctx->isc_intr = IFLIB_INTR_MSI; 6120 } else { 6121 scctx->isc_vectors = 1; 6122 device_printf(dev,"Using a Legacy interrupt\n"); 6123 scctx->isc_intr = IFLIB_INTR_LEGACY; 6124 } 6125 6126 return (vectors); 6127 } 6128 6129 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6130 6131 static int 6132 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6133 { 6134 int rc; 6135 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6136 struct sbuf *sb; 6137 const char *ring_state = "UNKNOWN"; 6138 6139 /* XXX needed ? */ 6140 rc = sysctl_wire_old_buffer(req, 0); 6141 MPASS(rc == 0); 6142 if (rc != 0) 6143 return (rc); 6144 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6145 MPASS(sb != NULL); 6146 if (sb == NULL) 6147 return (ENOMEM); 6148 if (state[3] <= 3) 6149 ring_state = ring_states[state[3]]; 6150 6151 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6152 state[0], state[1], state[2], ring_state); 6153 rc = sbuf_finish(sb); 6154 sbuf_delete(sb); 6155 return(rc); 6156 } 6157 6158 enum iflib_ndesc_handler { 6159 IFLIB_NTXD_HANDLER, 6160 IFLIB_NRXD_HANDLER, 6161 }; 6162 6163 static int 6164 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6165 { 6166 if_ctx_t ctx = (void *)arg1; 6167 enum iflib_ndesc_handler type = arg2; 6168 char buf[256] = {0}; 6169 qidx_t *ndesc; 6170 char *p, *next; 6171 int nqs, rc, i; 6172 6173 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 6174 6175 nqs = 8; 6176 switch(type) { 6177 case IFLIB_NTXD_HANDLER: 6178 ndesc = ctx->ifc_sysctl_ntxds; 6179 if (ctx->ifc_sctx) 6180 nqs = ctx->ifc_sctx->isc_ntxqs; 6181 break; 6182 case IFLIB_NRXD_HANDLER: 6183 ndesc = ctx->ifc_sysctl_nrxds; 6184 if (ctx->ifc_sctx) 6185 nqs = ctx->ifc_sctx->isc_nrxqs; 6186 break; 6187 default: 6188 panic("unhandled type"); 6189 } 6190 if (nqs == 0) 6191 nqs = 8; 6192 6193 for (i=0; i<8; i++) { 6194 if (i >= nqs) 6195 break; 6196 if (i) 6197 strcat(buf, ","); 6198 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6199 } 6200 6201 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6202 if (rc || req->newptr == NULL) 6203 return rc; 6204 6205 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6206 i++, p = strsep(&next, " ,")) { 6207 ndesc[i] = strtoul(p, NULL, 10); 6208 } 6209 6210 return(rc); 6211 } 6212 6213 #define NAME_BUFLEN 32 6214 static void 6215 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6216 { 6217 device_t dev = iflib_get_dev(ctx); 6218 struct sysctl_oid_list *child, *oid_list; 6219 struct sysctl_ctx_list *ctx_list; 6220 struct sysctl_oid *node; 6221 6222 ctx_list = device_get_sysctl_ctx(dev); 6223 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6224 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6225 CTLFLAG_RD, NULL, "IFLIB fields"); 6226 oid_list = SYSCTL_CHILDREN(node); 6227 6228 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6229 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6230 "driver version"); 6231 6232 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6233 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6234 "# of txqs to use, 0 => use default #"); 6235 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6236 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6237 "# of rxqs to use, 0 => use default #"); 6238 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6239 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6240 "permit #txq != #rxq"); 6241 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6242 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6243 "disable MSI-X (default 0)"); 6244 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6245 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6246 "set the rx budget"); 6247 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6248 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6249 "cause tx to abdicate instead of running to completion"); 6250 6251 /* XXX change for per-queue sizes */ 6252 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6253 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 6254 mp_ndesc_handler, "A", 6255 "list of # of tx descriptors to use, 0 = use default #"); 6256 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6257 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 6258 mp_ndesc_handler, "A", 6259 "list of # of rx descriptors to use, 0 = use default #"); 6260 } 6261 6262 static void 6263 iflib_add_device_sysctl_post(if_ctx_t ctx) 6264 { 6265 if_shared_ctx_t sctx = ctx->ifc_sctx; 6266 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6267 device_t dev = iflib_get_dev(ctx); 6268 struct sysctl_oid_list *child; 6269 struct sysctl_ctx_list *ctx_list; 6270 iflib_fl_t fl; 6271 iflib_txq_t txq; 6272 iflib_rxq_t rxq; 6273 int i, j; 6274 char namebuf[NAME_BUFLEN]; 6275 char *qfmt; 6276 struct sysctl_oid *queue_node, *fl_node, *node; 6277 struct sysctl_oid_list *queue_list, *fl_list; 6278 ctx_list = device_get_sysctl_ctx(dev); 6279 6280 node = ctx->ifc_sysctl_node; 6281 child = SYSCTL_CHILDREN(node); 6282 6283 if (scctx->isc_ntxqsets > 100) 6284 qfmt = "txq%03d"; 6285 else if (scctx->isc_ntxqsets > 10) 6286 qfmt = "txq%02d"; 6287 else 6288 qfmt = "txq%d"; 6289 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6290 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6291 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6292 CTLFLAG_RD, NULL, "Queue Name"); 6293 queue_list = SYSCTL_CHILDREN(queue_node); 6294 #if MEMORY_LOGGING 6295 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6296 CTLFLAG_RD, 6297 &txq->ift_dequeued, "total mbufs freed"); 6298 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6299 CTLFLAG_RD, 6300 &txq->ift_enqueued, "total mbufs enqueued"); 6301 #endif 6302 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6303 CTLFLAG_RD, 6304 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6305 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6306 CTLFLAG_RD, 6307 &txq->ift_pullups, "# of times m_pullup was called"); 6308 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6309 CTLFLAG_RD, 6310 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6311 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6312 CTLFLAG_RD, 6313 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6314 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6315 CTLFLAG_RD, 6316 &txq->ift_map_failed, "# of times dma map failed"); 6317 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6318 CTLFLAG_RD, 6319 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6320 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6321 CTLFLAG_RD, 6322 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6323 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6324 CTLFLAG_RD, 6325 &txq->ift_pidx, 1, "Producer Index"); 6326 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6327 CTLFLAG_RD, 6328 &txq->ift_cidx, 1, "Consumer Index"); 6329 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6330 CTLFLAG_RD, 6331 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6332 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6333 CTLFLAG_RD, 6334 &txq->ift_in_use, 1, "descriptors in use"); 6335 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6336 CTLFLAG_RD, 6337 &txq->ift_processed, "descriptors procesed for clean"); 6338 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6339 CTLFLAG_RD, 6340 &txq->ift_cleaned, "total cleaned"); 6341 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6342 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 6343 0, mp_ring_state_handler, "A", "soft ring state"); 6344 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6345 CTLFLAG_RD, &txq->ift_br->enqueues, 6346 "# of enqueues to the mp_ring for this queue"); 6347 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6348 CTLFLAG_RD, &txq->ift_br->drops, 6349 "# of drops in the mp_ring for this queue"); 6350 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6351 CTLFLAG_RD, &txq->ift_br->starts, 6352 "# of normal consumer starts in the mp_ring for this queue"); 6353 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6354 CTLFLAG_RD, &txq->ift_br->stalls, 6355 "# of consumer stalls in the mp_ring for this queue"); 6356 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6357 CTLFLAG_RD, &txq->ift_br->restarts, 6358 "# of consumer restarts in the mp_ring for this queue"); 6359 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6360 CTLFLAG_RD, &txq->ift_br->abdications, 6361 "# of consumer abdications in the mp_ring for this queue"); 6362 } 6363 6364 if (scctx->isc_nrxqsets > 100) 6365 qfmt = "rxq%03d"; 6366 else if (scctx->isc_nrxqsets > 10) 6367 qfmt = "rxq%02d"; 6368 else 6369 qfmt = "rxq%d"; 6370 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6371 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6372 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6373 CTLFLAG_RD, NULL, "Queue Name"); 6374 queue_list = SYSCTL_CHILDREN(queue_node); 6375 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6376 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 6377 CTLFLAG_RD, 6378 &rxq->ifr_cq_pidx, 1, "Producer Index"); 6379 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6380 CTLFLAG_RD, 6381 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6382 } 6383 6384 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6385 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6386 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6387 CTLFLAG_RD, NULL, "freelist Name"); 6388 fl_list = SYSCTL_CHILDREN(fl_node); 6389 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6390 CTLFLAG_RD, 6391 &fl->ifl_pidx, 1, "Producer Index"); 6392 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6393 CTLFLAG_RD, 6394 &fl->ifl_cidx, 1, "Consumer Index"); 6395 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6396 CTLFLAG_RD, 6397 &fl->ifl_credits, 1, "credits available"); 6398 #if MEMORY_LOGGING 6399 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6400 CTLFLAG_RD, 6401 &fl->ifl_m_enqueued, "mbufs allocated"); 6402 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6403 CTLFLAG_RD, 6404 &fl->ifl_m_dequeued, "mbufs freed"); 6405 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6406 CTLFLAG_RD, 6407 &fl->ifl_cl_enqueued, "clusters allocated"); 6408 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6409 CTLFLAG_RD, 6410 &fl->ifl_cl_dequeued, "clusters freed"); 6411 #endif 6412 6413 } 6414 } 6415 6416 } 6417 6418 void 6419 iflib_request_reset(if_ctx_t ctx) 6420 { 6421 6422 STATE_LOCK(ctx); 6423 ctx->ifc_flags |= IFC_DO_RESET; 6424 STATE_UNLOCK(ctx); 6425 } 6426 6427 #ifndef __NO_STRICT_ALIGNMENT 6428 static struct mbuf * 6429 iflib_fixup_rx(struct mbuf *m) 6430 { 6431 struct mbuf *n; 6432 6433 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6434 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6435 m->m_data += ETHER_HDR_LEN; 6436 n = m; 6437 } else { 6438 MGETHDR(n, M_NOWAIT, MT_DATA); 6439 if (n == NULL) { 6440 m_freem(m); 6441 return (NULL); 6442 } 6443 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6444 m->m_data += ETHER_HDR_LEN; 6445 m->m_len -= ETHER_HDR_LEN; 6446 n->m_len = ETHER_HDR_LEN; 6447 M_MOVE_PKTHDR(n, m); 6448 n->m_next = m; 6449 } 6450 return (n); 6451 } 6452 #endif 6453 6454 #ifdef NETDUMP 6455 static void 6456 iflib_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize) 6457 { 6458 if_ctx_t ctx; 6459 6460 ctx = if_getsoftc(ifp); 6461 CTX_LOCK(ctx); 6462 *nrxr = NRXQSETS(ctx); 6463 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6464 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6465 CTX_UNLOCK(ctx); 6466 } 6467 6468 static void 6469 iflib_netdump_event(struct ifnet *ifp, enum netdump_ev event) 6470 { 6471 if_ctx_t ctx; 6472 if_softc_ctx_t scctx; 6473 iflib_fl_t fl; 6474 iflib_rxq_t rxq; 6475 int i, j; 6476 6477 ctx = if_getsoftc(ifp); 6478 scctx = &ctx->ifc_softc_ctx; 6479 6480 switch (event) { 6481 case NETDUMP_START: 6482 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6483 rxq = &ctx->ifc_rxqs[i]; 6484 for (j = 0; j < rxq->ifr_nfl; j++) { 6485 fl = rxq->ifr_fl; 6486 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6487 } 6488 } 6489 iflib_no_tx_batch = 1; 6490 break; 6491 default: 6492 break; 6493 } 6494 } 6495 6496 static int 6497 iflib_netdump_transmit(struct ifnet *ifp, struct mbuf *m) 6498 { 6499 if_ctx_t ctx; 6500 iflib_txq_t txq; 6501 int error; 6502 6503 ctx = if_getsoftc(ifp); 6504 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6505 IFF_DRV_RUNNING) 6506 return (EBUSY); 6507 6508 txq = &ctx->ifc_txqs[0]; 6509 error = iflib_encap(txq, &m); 6510 if (error == 0) 6511 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6512 return (error); 6513 } 6514 6515 static int 6516 iflib_netdump_poll(struct ifnet *ifp, int count) 6517 { 6518 if_ctx_t ctx; 6519 if_softc_ctx_t scctx; 6520 iflib_txq_t txq; 6521 int i; 6522 6523 ctx = if_getsoftc(ifp); 6524 scctx = &ctx->ifc_softc_ctx; 6525 6526 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6527 IFF_DRV_RUNNING) 6528 return (EBUSY); 6529 6530 txq = &ctx->ifc_txqs[0]; 6531 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6532 6533 for (i = 0; i < scctx->isc_nrxqsets; i++) 6534 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6535 return (0); 6536 } 6537 #endif /* NETDUMP */ 6538