1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/debugnet.h> 63 #include <net/pfil.h> 64 #include <net/vnet.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_pcb.h> 68 #include <netinet/tcp_lro.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 #include <netinet/ip6.h> 73 #include <netinet/tcp.h> 74 #include <netinet/ip_var.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 #include <net/iflib_private.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 /* 120 * File organization: 121 * - private structures 122 * - iflib private utility functions 123 * - ifnet functions 124 * - vlan registry and other exported functions 125 * - iflib public core functions 126 * 127 * 128 */ 129 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 130 131 #define IFLIB_RXEOF_MORE (1U << 0) 132 #define IFLIB_RXEOF_EMPTY (2U << 0) 133 134 struct iflib_txq; 135 typedef struct iflib_txq *iflib_txq_t; 136 struct iflib_rxq; 137 typedef struct iflib_rxq *iflib_rxq_t; 138 struct iflib_fl; 139 typedef struct iflib_fl *iflib_fl_t; 140 141 struct iflib_ctx; 142 143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 144 static void iflib_timer(void *arg); 145 static void iflib_tqg_detach(if_ctx_t ctx); 146 147 typedef struct iflib_filter_info { 148 driver_filter_t *ifi_filter; 149 void *ifi_filter_arg; 150 struct grouptask *ifi_task; 151 void *ifi_ctx; 152 } *iflib_filter_info_t; 153 154 struct iflib_ctx { 155 KOBJ_FIELDS; 156 /* 157 * Pointer to hardware driver's softc 158 */ 159 void *ifc_softc; 160 device_t ifc_dev; 161 if_t ifc_ifp; 162 163 cpuset_t ifc_cpus; 164 if_shared_ctx_t ifc_sctx; 165 struct if_softc_ctx ifc_softc_ctx; 166 167 struct sx ifc_ctx_sx; 168 struct mtx ifc_state_mtx; 169 170 iflib_txq_t ifc_txqs; 171 iflib_rxq_t ifc_rxqs; 172 uint32_t ifc_if_flags; 173 uint32_t ifc_flags; 174 uint32_t ifc_max_fl_buf_size; 175 uint32_t ifc_rx_mbuf_sz; 176 177 int ifc_link_state; 178 int ifc_watchdog_events; 179 struct cdev *ifc_led_dev; 180 struct resource *ifc_msix_mem; 181 182 struct if_irq ifc_legacy_irq; 183 struct grouptask ifc_admin_task; 184 struct grouptask ifc_vflr_task; 185 struct iflib_filter_info ifc_filter_info; 186 struct ifmedia ifc_media; 187 struct ifmedia *ifc_mediap; 188 189 struct sysctl_oid *ifc_sysctl_node; 190 uint16_t ifc_sysctl_ntxqs; 191 uint16_t ifc_sysctl_nrxqs; 192 uint16_t ifc_sysctl_qs_eq_override; 193 uint16_t ifc_sysctl_rx_budget; 194 uint16_t ifc_sysctl_tx_abdicate; 195 uint16_t ifc_sysctl_core_offset; 196 #define CORE_OFFSET_UNSPECIFIED 0xffff 197 uint8_t ifc_sysctl_separate_txrx; 198 uint8_t ifc_sysctl_use_logical_cores; 199 bool ifc_cpus_are_physical_cores; 200 201 qidx_t ifc_sysctl_ntxds[8]; 202 qidx_t ifc_sysctl_nrxds[8]; 203 struct if_txrx ifc_txrx; 204 #define isc_txd_encap ifc_txrx.ift_txd_encap 205 #define isc_txd_flush ifc_txrx.ift_txd_flush 206 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 207 #define isc_rxd_available ifc_txrx.ift_rxd_available 208 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 209 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 210 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 211 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 212 #define isc_txq_select ifc_txrx.ift_txq_select 213 eventhandler_tag ifc_vlan_attach_event; 214 eventhandler_tag ifc_vlan_detach_event; 215 struct ether_addr ifc_mac; 216 }; 217 218 void * 219 iflib_get_softc(if_ctx_t ctx) 220 { 221 222 return (ctx->ifc_softc); 223 } 224 225 device_t 226 iflib_get_dev(if_ctx_t ctx) 227 { 228 229 return (ctx->ifc_dev); 230 } 231 232 if_t 233 iflib_get_ifp(if_ctx_t ctx) 234 { 235 236 return (ctx->ifc_ifp); 237 } 238 239 struct ifmedia * 240 iflib_get_media(if_ctx_t ctx) 241 { 242 243 return (ctx->ifc_mediap); 244 } 245 246 uint32_t 247 iflib_get_flags(if_ctx_t ctx) 248 { 249 return (ctx->ifc_flags); 250 } 251 252 void 253 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 254 { 255 256 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 257 } 258 259 if_softc_ctx_t 260 iflib_get_softc_ctx(if_ctx_t ctx) 261 { 262 263 return (&ctx->ifc_softc_ctx); 264 } 265 266 if_shared_ctx_t 267 iflib_get_sctx(if_ctx_t ctx) 268 { 269 270 return (ctx->ifc_sctx); 271 } 272 273 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 274 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 275 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 276 277 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 278 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 279 280 typedef struct iflib_sw_rx_desc_array { 281 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 282 struct mbuf **ifsd_m; /* pkthdr mbufs */ 283 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 284 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 285 } iflib_rxsd_array_t; 286 287 typedef struct iflib_sw_tx_desc_array { 288 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 289 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 290 struct mbuf **ifsd_m; /* pkthdr mbufs */ 291 } if_txsd_vec_t; 292 293 /* magic number that should be high enough for any hardware */ 294 #define IFLIB_MAX_TX_SEGS 128 295 #define IFLIB_RX_COPY_THRESH 128 296 #define IFLIB_MAX_RX_REFRESH 32 297 /* The minimum descriptors per second before we start coalescing */ 298 #define IFLIB_MIN_DESC_SEC 16384 299 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 300 #define IFLIB_QUEUE_IDLE 0 301 #define IFLIB_QUEUE_HUNG 1 302 #define IFLIB_QUEUE_WORKING 2 303 /* maximum number of txqs that can share an rx interrupt */ 304 #define IFLIB_MAX_TX_SHARED_INTR 4 305 306 /* this should really scale with ring size - this is a fairly arbitrary value */ 307 #define TX_BATCH_SIZE 32 308 309 #define IFLIB_RESTART_BUDGET 8 310 311 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 312 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 313 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 314 315 struct iflib_txq { 316 qidx_t ift_in_use; 317 qidx_t ift_cidx; 318 qidx_t ift_cidx_processed; 319 qidx_t ift_pidx; 320 uint8_t ift_gen; 321 uint8_t ift_br_offset; 322 uint16_t ift_npending; 323 uint16_t ift_db_pending; 324 uint16_t ift_rs_pending; 325 /* implicit pad */ 326 uint8_t ift_txd_size[8]; 327 uint64_t ift_processed; 328 uint64_t ift_cleaned; 329 uint64_t ift_cleaned_prev; 330 #if MEMORY_LOGGING 331 uint64_t ift_enqueued; 332 uint64_t ift_dequeued; 333 #endif 334 uint64_t ift_no_tx_dma_setup; 335 uint64_t ift_no_desc_avail; 336 uint64_t ift_mbuf_defrag_failed; 337 uint64_t ift_mbuf_defrag; 338 uint64_t ift_map_failed; 339 uint64_t ift_txd_encap_efbig; 340 uint64_t ift_pullups; 341 uint64_t ift_last_timer_tick; 342 343 struct mtx ift_mtx; 344 struct mtx ift_db_mtx; 345 346 /* constant values */ 347 if_ctx_t ift_ctx; 348 struct ifmp_ring *ift_br; 349 struct grouptask ift_task; 350 qidx_t ift_size; 351 uint16_t ift_id; 352 struct callout ift_timer; 353 #ifdef DEV_NETMAP 354 struct callout ift_netmap_timer; 355 #endif /* DEV_NETMAP */ 356 357 if_txsd_vec_t ift_sds; 358 uint8_t ift_qstatus; 359 uint8_t ift_closed; 360 uint8_t ift_update_freq; 361 struct iflib_filter_info ift_filter_info; 362 bus_dma_tag_t ift_buf_tag; 363 bus_dma_tag_t ift_tso_buf_tag; 364 iflib_dma_info_t ift_ifdi; 365 #define MTX_NAME_LEN 32 366 char ift_mtx_name[MTX_NAME_LEN]; 367 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 368 #ifdef IFLIB_DIAGNOSTICS 369 uint64_t ift_cpu_exec_count[256]; 370 #endif 371 } __aligned(CACHE_LINE_SIZE); 372 373 struct iflib_fl { 374 qidx_t ifl_cidx; 375 qidx_t ifl_pidx; 376 qidx_t ifl_credits; 377 uint8_t ifl_gen; 378 uint8_t ifl_rxd_size; 379 #if MEMORY_LOGGING 380 uint64_t ifl_m_enqueued; 381 uint64_t ifl_m_dequeued; 382 uint64_t ifl_cl_enqueued; 383 uint64_t ifl_cl_dequeued; 384 #endif 385 /* implicit pad */ 386 bitstr_t *ifl_rx_bitmap; 387 qidx_t ifl_fragidx; 388 /* constant */ 389 qidx_t ifl_size; 390 uint16_t ifl_buf_size; 391 uint16_t ifl_cltype; 392 uma_zone_t ifl_zone; 393 iflib_rxsd_array_t ifl_sds; 394 iflib_rxq_t ifl_rxq; 395 uint8_t ifl_id; 396 bus_dma_tag_t ifl_buf_tag; 397 iflib_dma_info_t ifl_ifdi; 398 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 399 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 400 } __aligned(CACHE_LINE_SIZE); 401 402 static inline qidx_t 403 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 404 { 405 qidx_t used; 406 407 if (pidx > cidx) 408 used = pidx - cidx; 409 else if (pidx < cidx) 410 used = size - cidx + pidx; 411 else if (gen == 0 && pidx == cidx) 412 used = 0; 413 else if (gen == 1 && pidx == cidx) 414 used = size; 415 else 416 panic("bad state"); 417 418 return (used); 419 } 420 421 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 422 423 #define IDXDIFF(head, tail, wrap) \ 424 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 425 426 struct iflib_rxq { 427 if_ctx_t ifr_ctx; 428 iflib_fl_t ifr_fl; 429 uint64_t ifr_rx_irq; 430 struct pfil_head *pfil; 431 /* 432 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 433 * the completion queue consumer index. Otherwise it's unused. 434 */ 435 qidx_t ifr_cq_cidx; 436 uint16_t ifr_id; 437 uint8_t ifr_nfl; 438 uint8_t ifr_ntxqirq; 439 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 440 uint8_t ifr_fl_offset; 441 struct lro_ctrl ifr_lc; 442 struct grouptask ifr_task; 443 struct callout ifr_watchdog; 444 struct iflib_filter_info ifr_filter_info; 445 iflib_dma_info_t ifr_ifdi; 446 447 /* dynamically allocate if any drivers need a value substantially larger than this */ 448 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 449 #ifdef IFLIB_DIAGNOSTICS 450 uint64_t ifr_cpu_exec_count[256]; 451 #endif 452 } __aligned(CACHE_LINE_SIZE); 453 454 typedef struct if_rxsd { 455 caddr_t *ifsd_cl; 456 iflib_fl_t ifsd_fl; 457 } *if_rxsd_t; 458 459 /* multiple of word size */ 460 #ifdef __LP64__ 461 #define PKT_INFO_SIZE 6 462 #define RXD_INFO_SIZE 5 463 #define PKT_TYPE uint64_t 464 #else 465 #define PKT_INFO_SIZE 11 466 #define RXD_INFO_SIZE 8 467 #define PKT_TYPE uint32_t 468 #endif 469 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 470 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 471 472 typedef struct if_pkt_info_pad { 473 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 474 } *if_pkt_info_pad_t; 475 typedef struct if_rxd_info_pad { 476 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 477 } *if_rxd_info_pad_t; 478 479 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 480 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 481 482 static inline void 483 pkt_info_zero(if_pkt_info_t pi) 484 { 485 if_pkt_info_pad_t pi_pad; 486 487 pi_pad = (if_pkt_info_pad_t)pi; 488 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 489 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 490 #ifndef __LP64__ 491 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 492 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 493 #endif 494 } 495 496 static device_method_t iflib_pseudo_methods[] = { 497 DEVMETHOD(device_attach, noop_attach), 498 DEVMETHOD(device_detach, iflib_pseudo_detach), 499 DEVMETHOD_END 500 }; 501 502 driver_t iflib_pseudodriver = { 503 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 504 }; 505 506 static inline void 507 rxd_info_zero(if_rxd_info_t ri) 508 { 509 if_rxd_info_pad_t ri_pad; 510 int i; 511 512 ri_pad = (if_rxd_info_pad_t)ri; 513 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 514 ri_pad->rxd_val[i] = 0; 515 ri_pad->rxd_val[i+1] = 0; 516 ri_pad->rxd_val[i+2] = 0; 517 ri_pad->rxd_val[i+3] = 0; 518 } 519 #ifdef __LP64__ 520 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 521 #endif 522 } 523 524 /* 525 * Only allow a single packet to take up most 1/nth of the tx ring 526 */ 527 #define MAX_SINGLE_PACKET_FRACTION 12 528 #define IF_BAD_DMA (bus_addr_t)-1 529 530 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 531 532 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 533 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 534 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 535 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 536 537 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 538 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 539 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 540 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 541 542 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 543 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 544 545 void 546 iflib_set_detach(if_ctx_t ctx) 547 { 548 STATE_LOCK(ctx); 549 ctx->ifc_flags |= IFC_IN_DETACH; 550 STATE_UNLOCK(ctx); 551 } 552 553 /* Our boot-time initialization hook */ 554 static int iflib_module_event_handler(module_t, int, void *); 555 556 static moduledata_t iflib_moduledata = { 557 "iflib", 558 iflib_module_event_handler, 559 NULL 560 }; 561 562 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 563 MODULE_VERSION(iflib, 1); 564 565 MODULE_DEPEND(iflib, pci, 1, 1, 1); 566 MODULE_DEPEND(iflib, ether, 1, 1, 1); 567 568 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 569 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 570 571 #ifndef IFLIB_DEBUG_COUNTERS 572 #ifdef INVARIANTS 573 #define IFLIB_DEBUG_COUNTERS 1 574 #else 575 #define IFLIB_DEBUG_COUNTERS 0 576 #endif /* !INVARIANTS */ 577 #endif 578 579 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 580 "iflib driver parameters"); 581 582 /* 583 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 584 */ 585 static int iflib_min_tx_latency = 0; 586 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 587 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 588 static int iflib_no_tx_batch = 0; 589 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 590 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 591 static int iflib_timer_default = 1000; 592 SYSCTL_INT(_net_iflib, OID_AUTO, timer_default, CTLFLAG_RW, 593 &iflib_timer_default, 0, "number of ticks between iflib_timer calls"); 594 595 596 #if IFLIB_DEBUG_COUNTERS 597 598 static int iflib_tx_seen; 599 static int iflib_tx_sent; 600 static int iflib_tx_encap; 601 static int iflib_rx_allocs; 602 static int iflib_fl_refills; 603 static int iflib_fl_refills_large; 604 static int iflib_tx_frees; 605 606 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 607 &iflib_tx_seen, 0, "# TX mbufs seen"); 608 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 609 &iflib_tx_sent, 0, "# TX mbufs sent"); 610 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 611 &iflib_tx_encap, 0, "# TX mbufs encapped"); 612 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 613 &iflib_tx_frees, 0, "# TX frees"); 614 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 615 &iflib_rx_allocs, 0, "# RX allocations"); 616 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 617 &iflib_fl_refills, 0, "# refills"); 618 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 619 &iflib_fl_refills_large, 0, "# large refills"); 620 621 static int iflib_txq_drain_flushing; 622 static int iflib_txq_drain_oactive; 623 static int iflib_txq_drain_notready; 624 625 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 626 &iflib_txq_drain_flushing, 0, "# drain flushes"); 627 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 628 &iflib_txq_drain_oactive, 0, "# drain oactives"); 629 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 630 &iflib_txq_drain_notready, 0, "# drain notready"); 631 632 static int iflib_encap_load_mbuf_fail; 633 static int iflib_encap_pad_mbuf_fail; 634 static int iflib_encap_txq_avail_fail; 635 static int iflib_encap_txd_encap_fail; 636 637 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 638 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 639 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 640 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 641 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 642 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 643 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 644 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 645 646 static int iflib_task_fn_rxs; 647 static int iflib_rx_intr_enables; 648 static int iflib_fast_intrs; 649 static int iflib_rx_unavail; 650 static int iflib_rx_ctx_inactive; 651 static int iflib_rx_if_input; 652 static int iflib_rxd_flush; 653 654 static int iflib_verbose_debug; 655 656 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 657 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 658 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 659 &iflib_rx_intr_enables, 0, "# RX intr enables"); 660 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 661 &iflib_fast_intrs, 0, "# fast_intr calls"); 662 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 663 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 664 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 665 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 666 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 667 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 668 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 669 &iflib_rxd_flush, 0, "# times rxd_flush called"); 670 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 671 &iflib_verbose_debug, 0, "enable verbose debugging"); 672 673 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 674 static void 675 iflib_debug_reset(void) 676 { 677 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 678 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 679 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 680 iflib_txq_drain_notready = 681 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 682 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 683 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 684 iflib_rx_unavail = 685 iflib_rx_ctx_inactive = iflib_rx_if_input = 686 iflib_rxd_flush = 0; 687 } 688 689 #else 690 #define DBG_COUNTER_INC(name) 691 static void iflib_debug_reset(void) {} 692 #endif 693 694 #define IFLIB_DEBUG 0 695 696 static void iflib_tx_structures_free(if_ctx_t ctx); 697 static void iflib_rx_structures_free(if_ctx_t ctx); 698 static int iflib_queues_alloc(if_ctx_t ctx); 699 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 700 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 701 static int iflib_qset_structures_setup(if_ctx_t ctx); 702 static int iflib_msix_init(if_ctx_t ctx); 703 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 704 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 705 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 706 #ifdef ALTQ 707 static void iflib_altq_if_start(if_t ifp); 708 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 709 #endif 710 static int iflib_register(if_ctx_t); 711 static void iflib_deregister(if_ctx_t); 712 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 713 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 714 static void iflib_init_locked(if_ctx_t ctx); 715 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 716 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 717 static void iflib_ifmp_purge(iflib_txq_t txq); 718 static void _iflib_pre_assert(if_softc_ctx_t scctx); 719 static void iflib_if_init_locked(if_ctx_t ctx); 720 static void iflib_free_intr_mem(if_ctx_t ctx); 721 #ifndef __NO_STRICT_ALIGNMENT 722 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 723 #endif 724 725 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 726 SLIST_HEAD_INITIALIZER(cpu_offsets); 727 struct cpu_offset { 728 SLIST_ENTRY(cpu_offset) entries; 729 cpuset_t set; 730 unsigned int refcount; 731 uint16_t next_cpuid; 732 }; 733 static struct mtx cpu_offset_mtx; 734 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 735 MTX_DEF); 736 737 DEBUGNET_DEFINE(iflib); 738 739 static int 740 iflib_num_rx_descs(if_ctx_t ctx) 741 { 742 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 743 if_shared_ctx_t sctx = ctx->ifc_sctx; 744 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 745 746 return scctx->isc_nrxd[first_rxq]; 747 } 748 749 static int 750 iflib_num_tx_descs(if_ctx_t ctx) 751 { 752 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 753 if_shared_ctx_t sctx = ctx->ifc_sctx; 754 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 755 756 return scctx->isc_ntxd[first_txq]; 757 } 758 759 #ifdef DEV_NETMAP 760 #include <sys/selinfo.h> 761 #include <net/netmap.h> 762 #include <dev/netmap/netmap_kern.h> 763 764 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 765 766 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init); 767 static void iflib_netmap_timer(void *arg); 768 769 /* 770 * device-specific sysctl variables: 771 * 772 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 773 * During regular operations the CRC is stripped, but on some 774 * hardware reception of frames not multiple of 64 is slower, 775 * so using crcstrip=0 helps in benchmarks. 776 * 777 * iflib_rx_miss, iflib_rx_miss_bufs: 778 * count packets that might be missed due to lost interrupts. 779 */ 780 SYSCTL_DECL(_dev_netmap); 781 /* 782 * The xl driver by default strips CRCs and we do not override it. 783 */ 784 785 int iflib_crcstrip = 1; 786 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 787 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 788 789 int iflib_rx_miss, iflib_rx_miss_bufs; 790 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 791 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 792 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 793 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 794 795 /* 796 * Register/unregister. We are already under netmap lock. 797 * Only called on the first register or the last unregister. 798 */ 799 static int 800 iflib_netmap_register(struct netmap_adapter *na, int onoff) 801 { 802 if_t ifp = na->ifp; 803 if_ctx_t ctx = ifp->if_softc; 804 int status; 805 806 CTX_LOCK(ctx); 807 if (!CTX_IS_VF(ctx)) 808 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 809 810 iflib_stop(ctx); 811 812 /* 813 * Enable (or disable) netmap flags, and intercept (or restore) 814 * ifp->if_transmit. This is done once the device has been stopped 815 * to prevent race conditions. Also, this must be done after 816 * calling netmap_disable_all_rings() and before calling 817 * netmap_enable_all_rings(), so that these two functions see the 818 * updated state of the NAF_NETMAP_ON bit. 819 */ 820 if (onoff) { 821 nm_set_native_flags(na); 822 } else { 823 nm_clear_native_flags(na); 824 } 825 826 iflib_init_locked(ctx); 827 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 828 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 829 if (status) 830 nm_clear_native_flags(na); 831 CTX_UNLOCK(ctx); 832 return (status); 833 } 834 835 static int 836 iflib_netmap_config(struct netmap_adapter *na, struct nm_config_info *info) 837 { 838 if_t ifp = na->ifp; 839 if_ctx_t ctx = ifp->if_softc; 840 iflib_rxq_t rxq = &ctx->ifc_rxqs[0]; 841 iflib_fl_t fl = &rxq->ifr_fl[0]; 842 843 info->num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 844 info->num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 845 info->num_tx_descs = iflib_num_tx_descs(ctx); 846 info->num_rx_descs = iflib_num_rx_descs(ctx); 847 info->rx_buf_maxsize = fl->ifl_buf_size; 848 nm_prinf("txr %u rxr %u txd %u rxd %u rbufsz %u", 849 info->num_tx_rings, info->num_rx_rings, info->num_tx_descs, 850 info->num_rx_descs, info->rx_buf_maxsize); 851 852 return 0; 853 } 854 855 static int 856 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init) 857 { 858 struct netmap_adapter *na = kring->na; 859 u_int const lim = kring->nkr_num_slots - 1; 860 struct netmap_ring *ring = kring->ring; 861 bus_dmamap_t *map; 862 struct if_rxd_update iru; 863 if_ctx_t ctx = rxq->ifr_ctx; 864 iflib_fl_t fl = &rxq->ifr_fl[0]; 865 u_int nic_i_first, nic_i; 866 u_int nm_i; 867 int i, n; 868 #if IFLIB_DEBUG_COUNTERS 869 int rf_count = 0; 870 #endif 871 872 /* 873 * This function is used both at initialization and in rxsync. 874 * At initialization we need to prepare (with isc_rxd_refill()) 875 * all the netmap buffers currently owned by the kernel, in 876 * such a way to keep fl->ifl_pidx and kring->nr_hwcur in sync 877 * (except for kring->nkr_hwofs). These may be less than 878 * kring->nkr_num_slots if netmap_reset() was called while 879 * an application using the kring that still owned some 880 * buffers. 881 * At rxsync time, both indexes point to the next buffer to be 882 * refilled. 883 * In any case we publish (with isc_rxd_flush()) up to 884 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod 885 * pointer to overrun the head/cons pointer, although this is 886 * not necessary for some NICs (e.g. vmx). 887 */ 888 if (__predict_false(init)) { 889 n = kring->nkr_num_slots - nm_kr_rxspace(kring); 890 } else { 891 n = kring->rhead - kring->nr_hwcur; 892 if (n == 0) 893 return (0); /* Nothing to do. */ 894 if (n < 0) 895 n += kring->nkr_num_slots; 896 } 897 898 iru_init(&iru, rxq, 0 /* flid */); 899 map = fl->ifl_sds.ifsd_map; 900 nic_i = fl->ifl_pidx; 901 nm_i = netmap_idx_n2k(kring, nic_i); 902 if (__predict_false(init)) { 903 /* 904 * On init/reset, nic_i must be 0, and we must 905 * start to refill from hwtail (see netmap_reset()). 906 */ 907 MPASS(nic_i == 0); 908 MPASS(nm_i == kring->nr_hwtail); 909 } else 910 MPASS(nm_i == kring->nr_hwcur); 911 DBG_COUNTER_INC(fl_refills); 912 while (n > 0) { 913 #if IFLIB_DEBUG_COUNTERS 914 if (++rf_count == 9) 915 DBG_COUNTER_INC(fl_refills_large); 916 #endif 917 nic_i_first = nic_i; 918 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) { 919 struct netmap_slot *slot = &ring->slot[nm_i]; 920 uint64_t paddr; 921 void *addr = PNMB(na, slot, &paddr); 922 923 MPASS(i < IFLIB_MAX_RX_REFRESH); 924 925 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 926 return netmap_ring_reinit(kring); 927 928 fl->ifl_bus_addrs[i] = paddr + 929 nm_get_offset(kring, slot); 930 fl->ifl_rxd_idxs[i] = nic_i; 931 932 if (__predict_false(init)) { 933 netmap_load_map(na, fl->ifl_buf_tag, 934 map[nic_i], addr); 935 } else if (slot->flags & NS_BUF_CHANGED) { 936 /* buffer has changed, reload map */ 937 netmap_reload_map(na, fl->ifl_buf_tag, 938 map[nic_i], addr); 939 } 940 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i], 941 BUS_DMASYNC_PREREAD); 942 slot->flags &= ~NS_BUF_CHANGED; 943 944 nm_i = nm_next(nm_i, lim); 945 nic_i = nm_next(nic_i, lim); 946 } 947 948 iru.iru_pidx = nic_i_first; 949 iru.iru_count = i; 950 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 951 } 952 fl->ifl_pidx = nic_i; 953 /* 954 * At the end of the loop we must have refilled everything 955 * we could possibly refill. 956 */ 957 MPASS(nm_i == kring->rhead); 958 kring->nr_hwcur = nm_i; 959 960 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 961 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 962 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, 963 nm_prev(nic_i, lim)); 964 DBG_COUNTER_INC(rxd_flush); 965 966 return (0); 967 } 968 969 #define NETMAP_TX_TIMER_US 90 970 971 /* 972 * Reconcile kernel and user view of the transmit ring. 973 * 974 * All information is in the kring. 975 * Userspace wants to send packets up to the one before kring->rhead, 976 * kernel knows kring->nr_hwcur is the first unsent packet. 977 * 978 * Here we push packets out (as many as possible), and possibly 979 * reclaim buffers from previously completed transmission. 980 * 981 * The caller (netmap) guarantees that there is only one instance 982 * running at any time. Any interference with other driver 983 * methods should be handled by the individual drivers. 984 */ 985 static int 986 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 987 { 988 struct netmap_adapter *na = kring->na; 989 if_t ifp = na->ifp; 990 struct netmap_ring *ring = kring->ring; 991 u_int nm_i; /* index into the netmap kring */ 992 u_int nic_i; /* index into the NIC ring */ 993 u_int n; 994 u_int const lim = kring->nkr_num_slots - 1; 995 u_int const head = kring->rhead; 996 struct if_pkt_info pi; 997 int tx_pkts = 0, tx_bytes = 0; 998 999 /* 1000 * interrupts on every tx packet are expensive so request 1001 * them every half ring, or where NS_REPORT is set 1002 */ 1003 u_int report_frequency = kring->nkr_num_slots >> 1; 1004 /* device-specific */ 1005 if_ctx_t ctx = ifp->if_softc; 1006 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 1007 1008 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1009 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1010 1011 /* 1012 * First part: process new packets to send. 1013 * nm_i is the current index in the netmap kring, 1014 * nic_i is the corresponding index in the NIC ring. 1015 * 1016 * If we have packets to send (nm_i != head) 1017 * iterate over the netmap ring, fetch length and update 1018 * the corresponding slot in the NIC ring. Some drivers also 1019 * need to update the buffer's physical address in the NIC slot 1020 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 1021 * 1022 * The netmap_reload_map() calls is especially expensive, 1023 * even when (as in this case) the tag is 0, so do only 1024 * when the buffer has actually changed. 1025 * 1026 * If possible do not set the report/intr bit on all slots, 1027 * but only a few times per ring or when NS_REPORT is set. 1028 * 1029 * Finally, on 10G and faster drivers, it might be useful 1030 * to prefetch the next slot and txr entry. 1031 */ 1032 1033 nm_i = kring->nr_hwcur; 1034 if (nm_i != head) { /* we have new packets to send */ 1035 uint32_t pkt_len = 0, seg_idx = 0; 1036 int nic_i_start = -1, flags = 0; 1037 pkt_info_zero(&pi); 1038 pi.ipi_segs = txq->ift_segs; 1039 pi.ipi_qsidx = kring->ring_id; 1040 nic_i = netmap_idx_k2n(kring, nm_i); 1041 1042 __builtin_prefetch(&ring->slot[nm_i]); 1043 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 1044 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 1045 1046 for (n = 0; nm_i != head; n++) { 1047 struct netmap_slot *slot = &ring->slot[nm_i]; 1048 uint64_t offset = nm_get_offset(kring, slot); 1049 u_int len = slot->len; 1050 uint64_t paddr; 1051 void *addr = PNMB(na, slot, &paddr); 1052 1053 flags |= (slot->flags & NS_REPORT || 1054 nic_i == 0 || nic_i == report_frequency) ? 1055 IPI_TX_INTR : 0; 1056 1057 /* 1058 * If this is the first packet fragment, save the 1059 * index of the first NIC slot for later. 1060 */ 1061 if (nic_i_start < 0) 1062 nic_i_start = nic_i; 1063 1064 pi.ipi_segs[seg_idx].ds_addr = paddr + offset; 1065 pi.ipi_segs[seg_idx].ds_len = len; 1066 if (len) { 1067 pkt_len += len; 1068 seg_idx++; 1069 } 1070 1071 if (!(slot->flags & NS_MOREFRAG)) { 1072 pi.ipi_len = pkt_len; 1073 pi.ipi_nsegs = seg_idx; 1074 pi.ipi_pidx = nic_i_start; 1075 pi.ipi_ndescs = 0; 1076 pi.ipi_flags = flags; 1077 1078 /* Prepare the NIC TX ring. */ 1079 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 1080 DBG_COUNTER_INC(tx_encap); 1081 1082 /* Update transmit counters */ 1083 tx_bytes += pi.ipi_len; 1084 tx_pkts++; 1085 1086 /* Reinit per-packet info for the next one. */ 1087 flags = seg_idx = pkt_len = 0; 1088 nic_i_start = -1; 1089 } 1090 1091 /* prefetch for next round */ 1092 __builtin_prefetch(&ring->slot[nm_i + 1]); 1093 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 1094 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1095 1096 NM_CHECK_ADDR_LEN_OFF(na, len, offset); 1097 1098 if (slot->flags & NS_BUF_CHANGED) { 1099 /* buffer has changed, reload map */ 1100 netmap_reload_map(na, txq->ift_buf_tag, 1101 txq->ift_sds.ifsd_map[nic_i], addr); 1102 } 1103 /* make sure changes to the buffer are synced */ 1104 bus_dmamap_sync(txq->ift_buf_tag, 1105 txq->ift_sds.ifsd_map[nic_i], 1106 BUS_DMASYNC_PREWRITE); 1107 1108 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED | NS_MOREFRAG); 1109 nm_i = nm_next(nm_i, lim); 1110 nic_i = nm_next(nic_i, lim); 1111 } 1112 kring->nr_hwcur = nm_i; 1113 1114 /* synchronize the NIC ring */ 1115 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1116 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1117 1118 /* (re)start the tx unit up to slot nic_i (excluded) */ 1119 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1120 } 1121 1122 /* 1123 * Second part: reclaim buffers for completed transmissions. 1124 * 1125 * If there are unclaimed buffers, attempt to reclaim them. 1126 * If we don't manage to reclaim them all, and TX IRQs are not in use, 1127 * trigger a per-tx-queue timer to try again later. 1128 */ 1129 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1130 if (iflib_tx_credits_update(ctx, txq)) { 1131 /* some tx completed, increment avail */ 1132 nic_i = txq->ift_cidx_processed; 1133 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1134 } 1135 } 1136 1137 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1138 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1139 callout_reset_sbt_on(&txq->ift_netmap_timer, 1140 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US, 1141 iflib_netmap_timer, txq, 1142 txq->ift_netmap_timer.c_cpu, 0); 1143 } 1144 1145 if_inc_counter(ifp, IFCOUNTER_OBYTES, tx_bytes); 1146 if_inc_counter(ifp, IFCOUNTER_OPACKETS, tx_pkts); 1147 1148 return (0); 1149 } 1150 1151 /* 1152 * Reconcile kernel and user view of the receive ring. 1153 * Same as for the txsync, this routine must be efficient. 1154 * The caller guarantees a single invocations, but races against 1155 * the rest of the driver should be handled here. 1156 * 1157 * On call, kring->rhead is the first packet that userspace wants 1158 * to keep, and kring->rcur is the wakeup point. 1159 * The kernel has previously reported packets up to kring->rtail. 1160 * 1161 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1162 * of whether or not we received an interrupt. 1163 */ 1164 static int 1165 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1166 { 1167 struct netmap_adapter *na = kring->na; 1168 struct netmap_ring *ring = kring->ring; 1169 if_t ifp = na->ifp; 1170 uint32_t nm_i; /* index into the netmap ring */ 1171 uint32_t nic_i; /* index into the NIC ring */ 1172 u_int n; 1173 u_int const lim = kring->nkr_num_slots - 1; 1174 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1175 int i = 0, rx_bytes = 0, rx_pkts = 0; 1176 1177 if_ctx_t ctx = ifp->if_softc; 1178 if_shared_ctx_t sctx = ctx->ifc_sctx; 1179 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1180 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1181 iflib_fl_t fl = &rxq->ifr_fl[0]; 1182 struct if_rxd_info ri; 1183 qidx_t *cidxp; 1184 1185 /* 1186 * netmap only uses free list 0, to avoid out of order consumption 1187 * of receive buffers 1188 */ 1189 1190 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1191 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1192 1193 /* 1194 * First part: import newly received packets. 1195 * 1196 * nm_i is the index of the next free slot in the netmap ring, 1197 * nic_i is the index of the next received packet in the NIC ring 1198 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may 1199 * differ in case if_init() has been called while 1200 * in netmap mode. For the receive ring we have 1201 * 1202 * nic_i = fl->ifl_cidx; 1203 * nm_i = kring->nr_hwtail (previous) 1204 * and 1205 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1206 * 1207 * fl->ifl_cidx is set to 0 on a ring reinit 1208 */ 1209 if (netmap_no_pendintr || force_update) { 1210 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim); 1211 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ; 1212 int crclen = iflib_crcstrip ? 0 : 4; 1213 int error, avail; 1214 1215 /* 1216 * For the free list consumer index, we use the same 1217 * logic as in iflib_rxeof(). 1218 */ 1219 if (have_rxcq) 1220 cidxp = &rxq->ifr_cq_cidx; 1221 else 1222 cidxp = &fl->ifl_cidx; 1223 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1224 rxq->ifr_id, *cidxp, USHRT_MAX); 1225 1226 nic_i = fl->ifl_cidx; 1227 nm_i = netmap_idx_n2k(kring, nic_i); 1228 MPASS(nm_i == kring->nr_hwtail); 1229 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) { 1230 rxd_info_zero(&ri); 1231 ri.iri_frags = rxq->ifr_frags; 1232 ri.iri_qsidx = kring->ring_id; 1233 ri.iri_ifp = ctx->ifc_ifp; 1234 ri.iri_cidx = *cidxp; 1235 1236 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1237 for (i = 0; i < ri.iri_nfrags; i++) { 1238 if (error) { 1239 ring->slot[nm_i].len = 0; 1240 ring->slot[nm_i].flags = 0; 1241 } else { 1242 ring->slot[nm_i].len = ri.iri_frags[i].irf_len; 1243 if (i == (ri.iri_nfrags - 1)) { 1244 ring->slot[nm_i].len -= crclen; 1245 ring->slot[nm_i].flags = 0; 1246 1247 /* Update receive counters */ 1248 rx_bytes += ri.iri_len; 1249 rx_pkts++; 1250 } else 1251 ring->slot[nm_i].flags = NS_MOREFRAG; 1252 } 1253 1254 bus_dmamap_sync(fl->ifl_buf_tag, 1255 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1256 nm_i = nm_next(nm_i, lim); 1257 fl->ifl_cidx = nic_i = nm_next(nic_i, lim); 1258 } 1259 1260 if (have_rxcq) { 1261 *cidxp = ri.iri_cidx; 1262 while (*cidxp >= scctx->isc_nrxd[0]) 1263 *cidxp -= scctx->isc_nrxd[0]; 1264 } 1265 1266 } 1267 if (n) { /* update the state variables */ 1268 if (netmap_no_pendintr && !force_update) { 1269 /* diagnostics */ 1270 iflib_rx_miss ++; 1271 iflib_rx_miss_bufs += n; 1272 } 1273 kring->nr_hwtail = nm_i; 1274 } 1275 kring->nr_kflags &= ~NKR_PENDINTR; 1276 } 1277 /* 1278 * Second part: skip past packets that userspace has released. 1279 * (kring->nr_hwcur to head excluded), 1280 * and make the buffers available for reception. 1281 * As usual nm_i is the index in the netmap ring, 1282 * nic_i is the index in the NIC ring, and 1283 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1284 */ 1285 netmap_fl_refill(rxq, kring, false); 1286 1287 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 1288 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 1289 1290 return (0); 1291 } 1292 1293 static void 1294 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1295 { 1296 if_ctx_t ctx = na->ifp->if_softc; 1297 1298 CTX_LOCK(ctx); 1299 if (onoff) { 1300 IFDI_INTR_ENABLE(ctx); 1301 } else { 1302 IFDI_INTR_DISABLE(ctx); 1303 } 1304 CTX_UNLOCK(ctx); 1305 } 1306 1307 static int 1308 iflib_netmap_attach(if_ctx_t ctx) 1309 { 1310 struct netmap_adapter na; 1311 1312 bzero(&na, sizeof(na)); 1313 1314 na.ifp = ctx->ifc_ifp; 1315 na.na_flags = NAF_BDG_MAYSLEEP | NAF_MOREFRAG | NAF_OFFSETS; 1316 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1317 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1318 1319 na.num_tx_desc = iflib_num_tx_descs(ctx); 1320 na.num_rx_desc = iflib_num_rx_descs(ctx); 1321 na.nm_txsync = iflib_netmap_txsync; 1322 na.nm_rxsync = iflib_netmap_rxsync; 1323 na.nm_register = iflib_netmap_register; 1324 na.nm_intr = iflib_netmap_intr; 1325 na.nm_config = iflib_netmap_config; 1326 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1327 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1328 return (netmap_attach(&na)); 1329 } 1330 1331 static int 1332 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1333 { 1334 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1335 struct netmap_slot *slot; 1336 1337 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1338 if (slot == NULL) 1339 return (0); 1340 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1341 /* 1342 * In netmap mode, set the map for the packet buffer. 1343 * NOTE: Some drivers (not this one) also need to set 1344 * the physical buffer address in the NIC ring. 1345 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1346 * netmap slot index, si 1347 */ 1348 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1349 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1350 NMB(na, slot + si)); 1351 } 1352 return (1); 1353 } 1354 1355 static int 1356 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1357 { 1358 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1359 struct netmap_kring *kring; 1360 struct netmap_slot *slot; 1361 1362 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1363 if (slot == NULL) 1364 return (0); 1365 kring = na->rx_rings[rxq->ifr_id]; 1366 netmap_fl_refill(rxq, kring, true); 1367 return (1); 1368 } 1369 1370 static void 1371 iflib_netmap_timer(void *arg) 1372 { 1373 iflib_txq_t txq = arg; 1374 if_ctx_t ctx = txq->ift_ctx; 1375 1376 /* 1377 * Wake up the netmap application, to give it a chance to 1378 * call txsync and reclaim more completed TX buffers. 1379 */ 1380 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id); 1381 } 1382 1383 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1384 1385 #else 1386 #define iflib_netmap_txq_init(ctx, txq) (0) 1387 #define iflib_netmap_rxq_init(ctx, rxq) (0) 1388 #define iflib_netmap_detach(ifp) 1389 #define netmap_enable_all_rings(ifp) 1390 #define netmap_disable_all_rings(ifp) 1391 1392 #define iflib_netmap_attach(ctx) (0) 1393 #define netmap_rx_irq(ifp, qid, budget) (0) 1394 #endif 1395 1396 #if defined(__i386__) || defined(__amd64__) 1397 static __inline void 1398 prefetch(void *x) 1399 { 1400 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1401 } 1402 static __inline void 1403 prefetch2cachelines(void *x) 1404 { 1405 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1406 #if (CACHE_LINE_SIZE < 128) 1407 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1408 #endif 1409 } 1410 #else 1411 #define prefetch(x) 1412 #define prefetch2cachelines(x) 1413 #endif 1414 1415 static void 1416 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1417 { 1418 iflib_fl_t fl; 1419 1420 fl = &rxq->ifr_fl[flid]; 1421 iru->iru_paddrs = fl->ifl_bus_addrs; 1422 iru->iru_idxs = fl->ifl_rxd_idxs; 1423 iru->iru_qsidx = rxq->ifr_id; 1424 iru->iru_buf_size = fl->ifl_buf_size; 1425 iru->iru_flidx = fl->ifl_id; 1426 } 1427 1428 static void 1429 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1430 { 1431 if (err) 1432 return; 1433 *(bus_addr_t *) arg = segs[0].ds_addr; 1434 } 1435 1436 #define DMA_WIDTH_TO_BUS_LOWADDR(width) \ 1437 (((width) == 0) || (width) == flsll(BUS_SPACE_MAXADDR) ? \ 1438 BUS_SPACE_MAXADDR : (1ULL << (width)) - 1ULL) 1439 1440 int 1441 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1442 { 1443 int err; 1444 device_t dev = ctx->ifc_dev; 1445 bus_addr_t lowaddr; 1446 1447 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(ctx->ifc_softc_ctx.isc_dma_width); 1448 1449 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1450 align, 0, /* alignment, bounds */ 1451 lowaddr, /* lowaddr */ 1452 BUS_SPACE_MAXADDR, /* highaddr */ 1453 NULL, NULL, /* filter, filterarg */ 1454 size, /* maxsize */ 1455 1, /* nsegments */ 1456 size, /* maxsegsize */ 1457 BUS_DMA_ALLOCNOW, /* flags */ 1458 NULL, /* lockfunc */ 1459 NULL, /* lockarg */ 1460 &dma->idi_tag); 1461 if (err) { 1462 device_printf(dev, 1463 "%s: bus_dma_tag_create failed: %d\n", 1464 __func__, err); 1465 goto fail_0; 1466 } 1467 1468 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1469 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1470 if (err) { 1471 device_printf(dev, 1472 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1473 __func__, (uintmax_t)size, err); 1474 goto fail_1; 1475 } 1476 1477 dma->idi_paddr = IF_BAD_DMA; 1478 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1479 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1480 if (err || dma->idi_paddr == IF_BAD_DMA) { 1481 device_printf(dev, 1482 "%s: bus_dmamap_load failed: %d\n", 1483 __func__, err); 1484 goto fail_2; 1485 } 1486 1487 dma->idi_size = size; 1488 return (0); 1489 1490 fail_2: 1491 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1492 fail_1: 1493 bus_dma_tag_destroy(dma->idi_tag); 1494 fail_0: 1495 dma->idi_tag = NULL; 1496 1497 return (err); 1498 } 1499 1500 int 1501 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1502 { 1503 if_shared_ctx_t sctx = ctx->ifc_sctx; 1504 1505 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1506 1507 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1508 } 1509 1510 int 1511 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1512 { 1513 int i, err; 1514 iflib_dma_info_t *dmaiter; 1515 1516 dmaiter = dmalist; 1517 for (i = 0; i < count; i++, dmaiter++) { 1518 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1519 break; 1520 } 1521 if (err) 1522 iflib_dma_free_multi(dmalist, i); 1523 return (err); 1524 } 1525 1526 void 1527 iflib_dma_free(iflib_dma_info_t dma) 1528 { 1529 if (dma->idi_tag == NULL) 1530 return; 1531 if (dma->idi_paddr != IF_BAD_DMA) { 1532 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1533 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1534 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1535 dma->idi_paddr = IF_BAD_DMA; 1536 } 1537 if (dma->idi_vaddr != NULL) { 1538 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1539 dma->idi_vaddr = NULL; 1540 } 1541 bus_dma_tag_destroy(dma->idi_tag); 1542 dma->idi_tag = NULL; 1543 } 1544 1545 void 1546 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1547 { 1548 int i; 1549 iflib_dma_info_t *dmaiter = dmalist; 1550 1551 for (i = 0; i < count; i++, dmaiter++) 1552 iflib_dma_free(*dmaiter); 1553 } 1554 1555 static int 1556 iflib_fast_intr(void *arg) 1557 { 1558 iflib_filter_info_t info = arg; 1559 struct grouptask *gtask = info->ifi_task; 1560 int result; 1561 1562 DBG_COUNTER_INC(fast_intrs); 1563 if (info->ifi_filter != NULL) { 1564 result = info->ifi_filter(info->ifi_filter_arg); 1565 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1566 return (result); 1567 } 1568 1569 GROUPTASK_ENQUEUE(gtask); 1570 return (FILTER_HANDLED); 1571 } 1572 1573 static int 1574 iflib_fast_intr_rxtx(void *arg) 1575 { 1576 iflib_filter_info_t info = arg; 1577 struct grouptask *gtask = info->ifi_task; 1578 if_ctx_t ctx; 1579 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1580 iflib_txq_t txq; 1581 void *sc; 1582 int i, cidx, result; 1583 qidx_t txqid; 1584 bool intr_enable, intr_legacy; 1585 1586 DBG_COUNTER_INC(fast_intrs); 1587 if (info->ifi_filter != NULL) { 1588 result = info->ifi_filter(info->ifi_filter_arg); 1589 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1590 return (result); 1591 } 1592 1593 ctx = rxq->ifr_ctx; 1594 sc = ctx->ifc_softc; 1595 intr_enable = false; 1596 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1597 MPASS(rxq->ifr_ntxqirq); 1598 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1599 txqid = rxq->ifr_txqid[i]; 1600 txq = &ctx->ifc_txqs[txqid]; 1601 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1602 BUS_DMASYNC_POSTREAD); 1603 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1604 if (intr_legacy) 1605 intr_enable = true; 1606 else 1607 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1608 continue; 1609 } 1610 GROUPTASK_ENQUEUE(&txq->ift_task); 1611 } 1612 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1613 cidx = rxq->ifr_cq_cidx; 1614 else 1615 cidx = rxq->ifr_fl[0].ifl_cidx; 1616 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1617 GROUPTASK_ENQUEUE(gtask); 1618 else { 1619 if (intr_legacy) 1620 intr_enable = true; 1621 else 1622 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1623 DBG_COUNTER_INC(rx_intr_enables); 1624 } 1625 if (intr_enable) 1626 IFDI_INTR_ENABLE(ctx); 1627 return (FILTER_HANDLED); 1628 } 1629 1630 static int 1631 iflib_fast_intr_ctx(void *arg) 1632 { 1633 iflib_filter_info_t info = arg; 1634 struct grouptask *gtask = info->ifi_task; 1635 int result; 1636 1637 DBG_COUNTER_INC(fast_intrs); 1638 if (info->ifi_filter != NULL) { 1639 result = info->ifi_filter(info->ifi_filter_arg); 1640 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1641 return (result); 1642 } 1643 1644 GROUPTASK_ENQUEUE(gtask); 1645 return (FILTER_HANDLED); 1646 } 1647 1648 static int 1649 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1650 driver_filter_t filter, driver_intr_t handler, void *arg, 1651 const char *name) 1652 { 1653 struct resource *res; 1654 void *tag = NULL; 1655 device_t dev = ctx->ifc_dev; 1656 int flags, i, rc; 1657 1658 flags = RF_ACTIVE; 1659 if (ctx->ifc_flags & IFC_LEGACY) 1660 flags |= RF_SHAREABLE; 1661 MPASS(rid < 512); 1662 i = rid; 1663 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1664 if (res == NULL) { 1665 device_printf(dev, 1666 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1667 return (ENOMEM); 1668 } 1669 irq->ii_res = res; 1670 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1671 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1672 filter, handler, arg, &tag); 1673 if (rc != 0) { 1674 device_printf(dev, 1675 "failed to setup interrupt for rid %d, name %s: %d\n", 1676 rid, name ? name : "unknown", rc); 1677 return (rc); 1678 } else if (name) 1679 bus_describe_intr(dev, res, tag, "%s", name); 1680 1681 irq->ii_tag = tag; 1682 return (0); 1683 } 1684 1685 /********************************************************************* 1686 * 1687 * Allocate DMA resources for TX buffers as well as memory for the TX 1688 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1689 * iflib_sw_tx_desc_array structure, storing all the information that 1690 * is needed to transmit a packet on the wire. This is called only 1691 * once at attach, setup is done every reset. 1692 * 1693 **********************************************************************/ 1694 static int 1695 iflib_txsd_alloc(iflib_txq_t txq) 1696 { 1697 if_ctx_t ctx = txq->ift_ctx; 1698 if_shared_ctx_t sctx = ctx->ifc_sctx; 1699 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1700 device_t dev = ctx->ifc_dev; 1701 bus_size_t tsomaxsize; 1702 bus_addr_t lowaddr; 1703 int err, nsegments, ntsosegments; 1704 bool tso; 1705 1706 nsegments = scctx->isc_tx_nsegments; 1707 ntsosegments = scctx->isc_tx_tso_segments_max; 1708 tsomaxsize = scctx->isc_tx_tso_size_max; 1709 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1710 tsomaxsize += sizeof(struct ether_vlan_header); 1711 MPASS(scctx->isc_ntxd[0] > 0); 1712 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1713 MPASS(nsegments > 0); 1714 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1715 MPASS(ntsosegments > 0); 1716 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1717 } 1718 1719 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1720 1721 /* 1722 * Set up DMA tags for TX buffers. 1723 */ 1724 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1725 1, 0, /* alignment, bounds */ 1726 lowaddr, /* lowaddr */ 1727 BUS_SPACE_MAXADDR, /* highaddr */ 1728 NULL, NULL, /* filter, filterarg */ 1729 sctx->isc_tx_maxsize, /* maxsize */ 1730 nsegments, /* nsegments */ 1731 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1732 0, /* flags */ 1733 NULL, /* lockfunc */ 1734 NULL, /* lockfuncarg */ 1735 &txq->ift_buf_tag))) { 1736 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1737 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1738 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1739 goto fail; 1740 } 1741 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1742 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1743 1, 0, /* alignment, bounds */ 1744 lowaddr, /* lowaddr */ 1745 BUS_SPACE_MAXADDR, /* highaddr */ 1746 NULL, NULL, /* filter, filterarg */ 1747 tsomaxsize, /* maxsize */ 1748 ntsosegments, /* nsegments */ 1749 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1750 0, /* flags */ 1751 NULL, /* lockfunc */ 1752 NULL, /* lockfuncarg */ 1753 &txq->ift_tso_buf_tag))) { 1754 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1755 err); 1756 goto fail; 1757 } 1758 1759 /* Allocate memory for the TX mbuf map. */ 1760 if (!(txq->ift_sds.ifsd_m = 1761 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1762 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1763 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1764 err = ENOMEM; 1765 goto fail; 1766 } 1767 1768 /* 1769 * Create the DMA maps for TX buffers. 1770 */ 1771 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1772 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1773 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1774 device_printf(dev, 1775 "Unable to allocate TX buffer DMA map memory\n"); 1776 err = ENOMEM; 1777 goto fail; 1778 } 1779 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1780 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1781 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1782 device_printf(dev, 1783 "Unable to allocate TSO TX buffer map memory\n"); 1784 err = ENOMEM; 1785 goto fail; 1786 } 1787 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1788 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1789 &txq->ift_sds.ifsd_map[i]); 1790 if (err != 0) { 1791 device_printf(dev, "Unable to create TX DMA map\n"); 1792 goto fail; 1793 } 1794 if (!tso) 1795 continue; 1796 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1797 &txq->ift_sds.ifsd_tso_map[i]); 1798 if (err != 0) { 1799 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1800 goto fail; 1801 } 1802 } 1803 return (0); 1804 fail: 1805 /* We free all, it handles case where we are in the middle */ 1806 iflib_tx_structures_free(ctx); 1807 return (err); 1808 } 1809 1810 static void 1811 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1812 { 1813 bus_dmamap_t map; 1814 1815 if (txq->ift_sds.ifsd_map != NULL) { 1816 map = txq->ift_sds.ifsd_map[i]; 1817 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1818 bus_dmamap_unload(txq->ift_buf_tag, map); 1819 bus_dmamap_destroy(txq->ift_buf_tag, map); 1820 txq->ift_sds.ifsd_map[i] = NULL; 1821 } 1822 1823 if (txq->ift_sds.ifsd_tso_map != NULL) { 1824 map = txq->ift_sds.ifsd_tso_map[i]; 1825 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1826 BUS_DMASYNC_POSTWRITE); 1827 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1828 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1829 txq->ift_sds.ifsd_tso_map[i] = NULL; 1830 } 1831 } 1832 1833 static void 1834 iflib_txq_destroy(iflib_txq_t txq) 1835 { 1836 if_ctx_t ctx = txq->ift_ctx; 1837 1838 for (int i = 0; i < txq->ift_size; i++) 1839 iflib_txsd_destroy(ctx, txq, i); 1840 1841 if (txq->ift_br != NULL) { 1842 ifmp_ring_free(txq->ift_br); 1843 txq->ift_br = NULL; 1844 } 1845 1846 mtx_destroy(&txq->ift_mtx); 1847 1848 if (txq->ift_sds.ifsd_map != NULL) { 1849 free(txq->ift_sds.ifsd_map, M_IFLIB); 1850 txq->ift_sds.ifsd_map = NULL; 1851 } 1852 if (txq->ift_sds.ifsd_tso_map != NULL) { 1853 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1854 txq->ift_sds.ifsd_tso_map = NULL; 1855 } 1856 if (txq->ift_sds.ifsd_m != NULL) { 1857 free(txq->ift_sds.ifsd_m, M_IFLIB); 1858 txq->ift_sds.ifsd_m = NULL; 1859 } 1860 if (txq->ift_buf_tag != NULL) { 1861 bus_dma_tag_destroy(txq->ift_buf_tag); 1862 txq->ift_buf_tag = NULL; 1863 } 1864 if (txq->ift_tso_buf_tag != NULL) { 1865 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1866 txq->ift_tso_buf_tag = NULL; 1867 } 1868 if (txq->ift_ifdi != NULL) { 1869 free(txq->ift_ifdi, M_IFLIB); 1870 } 1871 } 1872 1873 static void 1874 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1875 { 1876 struct mbuf **mp; 1877 1878 mp = &txq->ift_sds.ifsd_m[i]; 1879 if (*mp == NULL) 1880 return; 1881 1882 if (txq->ift_sds.ifsd_map != NULL) { 1883 bus_dmamap_sync(txq->ift_buf_tag, 1884 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1885 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1886 } 1887 if (txq->ift_sds.ifsd_tso_map != NULL) { 1888 bus_dmamap_sync(txq->ift_tso_buf_tag, 1889 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1890 bus_dmamap_unload(txq->ift_tso_buf_tag, 1891 txq->ift_sds.ifsd_tso_map[i]); 1892 } 1893 m_freem(*mp); 1894 DBG_COUNTER_INC(tx_frees); 1895 *mp = NULL; 1896 } 1897 1898 static int 1899 iflib_txq_setup(iflib_txq_t txq) 1900 { 1901 if_ctx_t ctx = txq->ift_ctx; 1902 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1903 if_shared_ctx_t sctx = ctx->ifc_sctx; 1904 iflib_dma_info_t di; 1905 int i; 1906 1907 /* Set number of descriptors available */ 1908 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1909 /* XXX make configurable */ 1910 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1911 1912 /* Reset indices */ 1913 txq->ift_cidx_processed = 0; 1914 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1915 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1916 1917 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1918 bzero((void *)di->idi_vaddr, di->idi_size); 1919 1920 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1921 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1922 bus_dmamap_sync(di->idi_tag, di->idi_map, 1923 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1924 return (0); 1925 } 1926 1927 /********************************************************************* 1928 * 1929 * Allocate DMA resources for RX buffers as well as memory for the RX 1930 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1931 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1932 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1933 * Since we use use one entry in iflib_sw_rx_desc_array per received 1934 * packet, the maximum number of entries we'll need is equal to the 1935 * number of hardware receive descriptors that we've allocated. 1936 * 1937 **********************************************************************/ 1938 static int 1939 iflib_rxsd_alloc(iflib_rxq_t rxq) 1940 { 1941 if_ctx_t ctx = rxq->ifr_ctx; 1942 if_shared_ctx_t sctx = ctx->ifc_sctx; 1943 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1944 device_t dev = ctx->ifc_dev; 1945 iflib_fl_t fl; 1946 bus_addr_t lowaddr; 1947 int err; 1948 1949 MPASS(scctx->isc_nrxd[0] > 0); 1950 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1951 1952 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1953 1954 fl = rxq->ifr_fl; 1955 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1956 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1957 /* Set up DMA tag for RX buffers. */ 1958 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1959 1, 0, /* alignment, bounds */ 1960 lowaddr, /* lowaddr */ 1961 BUS_SPACE_MAXADDR, /* highaddr */ 1962 NULL, NULL, /* filter, filterarg */ 1963 sctx->isc_rx_maxsize, /* maxsize */ 1964 sctx->isc_rx_nsegments, /* nsegments */ 1965 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1966 0, /* flags */ 1967 NULL, /* lockfunc */ 1968 NULL, /* lockarg */ 1969 &fl->ifl_buf_tag); 1970 if (err) { 1971 device_printf(dev, 1972 "Unable to allocate RX DMA tag: %d\n", err); 1973 goto fail; 1974 } 1975 1976 /* Allocate memory for the RX mbuf map. */ 1977 if (!(fl->ifl_sds.ifsd_m = 1978 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1979 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1980 device_printf(dev, 1981 "Unable to allocate RX mbuf map memory\n"); 1982 err = ENOMEM; 1983 goto fail; 1984 } 1985 1986 /* Allocate memory for the direct RX cluster pointer map. */ 1987 if (!(fl->ifl_sds.ifsd_cl = 1988 (caddr_t *) malloc(sizeof(caddr_t) * 1989 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1990 device_printf(dev, 1991 "Unable to allocate RX cluster map memory\n"); 1992 err = ENOMEM; 1993 goto fail; 1994 } 1995 1996 /* Allocate memory for the RX cluster bus address map. */ 1997 if (!(fl->ifl_sds.ifsd_ba = 1998 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1999 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2000 device_printf(dev, 2001 "Unable to allocate RX bus address map memory\n"); 2002 err = ENOMEM; 2003 goto fail; 2004 } 2005 2006 /* 2007 * Create the DMA maps for RX buffers. 2008 */ 2009 if (!(fl->ifl_sds.ifsd_map = 2010 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2011 device_printf(dev, 2012 "Unable to allocate RX buffer DMA map memory\n"); 2013 err = ENOMEM; 2014 goto fail; 2015 } 2016 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 2017 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 2018 &fl->ifl_sds.ifsd_map[i]); 2019 if (err != 0) { 2020 device_printf(dev, "Unable to create RX buffer DMA map\n"); 2021 goto fail; 2022 } 2023 } 2024 } 2025 return (0); 2026 2027 fail: 2028 iflib_rx_structures_free(ctx); 2029 return (err); 2030 } 2031 2032 /* 2033 * Internal service routines 2034 */ 2035 2036 struct rxq_refill_cb_arg { 2037 int error; 2038 bus_dma_segment_t seg; 2039 int nseg; 2040 }; 2041 2042 static void 2043 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2044 { 2045 struct rxq_refill_cb_arg *cb_arg = arg; 2046 2047 cb_arg->error = error; 2048 cb_arg->seg = segs[0]; 2049 cb_arg->nseg = nseg; 2050 } 2051 2052 /** 2053 * iflib_fl_refill - refill an rxq free-buffer list 2054 * @ctx: the iflib context 2055 * @fl: the free list to refill 2056 * @count: the number of new buffers to allocate 2057 * 2058 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 2059 * The caller must assure that @count does not exceed the queue's capacity 2060 * minus one (since we always leave a descriptor unavailable). 2061 */ 2062 static uint8_t 2063 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 2064 { 2065 struct if_rxd_update iru; 2066 struct rxq_refill_cb_arg cb_arg; 2067 struct mbuf *m; 2068 caddr_t cl, *sd_cl; 2069 struct mbuf **sd_m; 2070 bus_dmamap_t *sd_map; 2071 bus_addr_t bus_addr, *sd_ba; 2072 int err, frag_idx, i, idx, n, pidx; 2073 qidx_t credits; 2074 2075 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1); 2076 2077 sd_m = fl->ifl_sds.ifsd_m; 2078 sd_map = fl->ifl_sds.ifsd_map; 2079 sd_cl = fl->ifl_sds.ifsd_cl; 2080 sd_ba = fl->ifl_sds.ifsd_ba; 2081 pidx = fl->ifl_pidx; 2082 idx = pidx; 2083 frag_idx = fl->ifl_fragidx; 2084 credits = fl->ifl_credits; 2085 2086 i = 0; 2087 n = count; 2088 MPASS(n > 0); 2089 MPASS(credits + n <= fl->ifl_size); 2090 2091 if (pidx < fl->ifl_cidx) 2092 MPASS(pidx + n <= fl->ifl_cidx); 2093 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 2094 MPASS(fl->ifl_gen == 0); 2095 if (pidx > fl->ifl_cidx) 2096 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 2097 2098 DBG_COUNTER_INC(fl_refills); 2099 if (n > 8) 2100 DBG_COUNTER_INC(fl_refills_large); 2101 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 2102 while (n-- > 0) { 2103 /* 2104 * We allocate an uninitialized mbuf + cluster, mbuf is 2105 * initialized after rx. 2106 * 2107 * If the cluster is still set then we know a minimum sized 2108 * packet was received 2109 */ 2110 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 2111 &frag_idx); 2112 if (frag_idx < 0) 2113 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 2114 MPASS(frag_idx >= 0); 2115 if ((cl = sd_cl[frag_idx]) == NULL) { 2116 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT); 2117 if (__predict_false(cl == NULL)) 2118 break; 2119 2120 cb_arg.error = 0; 2121 MPASS(sd_map != NULL); 2122 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2123 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2124 BUS_DMA_NOWAIT); 2125 if (__predict_false(err != 0 || cb_arg.error)) { 2126 uma_zfree(fl->ifl_zone, cl); 2127 break; 2128 } 2129 2130 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2131 sd_cl[frag_idx] = cl; 2132 #if MEMORY_LOGGING 2133 fl->ifl_cl_enqueued++; 2134 #endif 2135 } else { 2136 bus_addr = sd_ba[frag_idx]; 2137 } 2138 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2139 BUS_DMASYNC_PREREAD); 2140 2141 if (sd_m[frag_idx] == NULL) { 2142 m = m_gethdr_raw(M_NOWAIT, 0); 2143 if (__predict_false(m == NULL)) 2144 break; 2145 sd_m[frag_idx] = m; 2146 } 2147 bit_set(fl->ifl_rx_bitmap, frag_idx); 2148 #if MEMORY_LOGGING 2149 fl->ifl_m_enqueued++; 2150 #endif 2151 2152 DBG_COUNTER_INC(rx_allocs); 2153 fl->ifl_rxd_idxs[i] = frag_idx; 2154 fl->ifl_bus_addrs[i] = bus_addr; 2155 credits++; 2156 i++; 2157 MPASS(credits <= fl->ifl_size); 2158 if (++idx == fl->ifl_size) { 2159 #ifdef INVARIANTS 2160 fl->ifl_gen = 1; 2161 #endif 2162 idx = 0; 2163 } 2164 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2165 iru.iru_pidx = pidx; 2166 iru.iru_count = i; 2167 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2168 fl->ifl_pidx = idx; 2169 fl->ifl_credits = credits; 2170 pidx = idx; 2171 i = 0; 2172 } 2173 } 2174 2175 if (n < count - 1) { 2176 if (i != 0) { 2177 iru.iru_pidx = pidx; 2178 iru.iru_count = i; 2179 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2180 fl->ifl_pidx = idx; 2181 fl->ifl_credits = credits; 2182 } 2183 DBG_COUNTER_INC(rxd_flush); 2184 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2185 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2186 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, 2187 fl->ifl_id, fl->ifl_pidx); 2188 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) { 2189 fl->ifl_fragidx = frag_idx + 1; 2190 if (fl->ifl_fragidx == fl->ifl_size) 2191 fl->ifl_fragidx = 0; 2192 } else { 2193 fl->ifl_fragidx = frag_idx; 2194 } 2195 } 2196 2197 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2198 } 2199 2200 static inline uint8_t 2201 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2202 { 2203 /* 2204 * We leave an unused descriptor to avoid pidx to catch up with cidx. 2205 * This is important as it confuses most NICs. For instance, 2206 * Intel NICs have (per receive ring) RDH and RDT registers, where 2207 * RDH points to the next receive descriptor to be used by the NIC, 2208 * and RDT for the next receive descriptor to be published by the 2209 * driver to the NIC (RDT - 1 is thus the last valid one). 2210 * The condition RDH == RDT means no descriptors are available to 2211 * the NIC, and thus it would be ambiguous if it also meant that 2212 * all the descriptors are available to the NIC. 2213 */ 2214 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2215 #ifdef INVARIANTS 2216 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2217 #endif 2218 2219 MPASS(fl->ifl_credits <= fl->ifl_size); 2220 MPASS(reclaimable == delta); 2221 2222 if (reclaimable > 0) 2223 return (iflib_fl_refill(ctx, fl, reclaimable)); 2224 return (0); 2225 } 2226 2227 uint8_t 2228 iflib_in_detach(if_ctx_t ctx) 2229 { 2230 bool in_detach; 2231 2232 STATE_LOCK(ctx); 2233 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2234 STATE_UNLOCK(ctx); 2235 return (in_detach); 2236 } 2237 2238 static void 2239 iflib_fl_bufs_free(iflib_fl_t fl) 2240 { 2241 iflib_dma_info_t idi = fl->ifl_ifdi; 2242 bus_dmamap_t sd_map; 2243 uint32_t i; 2244 2245 for (i = 0; i < fl->ifl_size; i++) { 2246 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2247 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2248 2249 if (*sd_cl != NULL) { 2250 sd_map = fl->ifl_sds.ifsd_map[i]; 2251 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2252 BUS_DMASYNC_POSTREAD); 2253 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2254 uma_zfree(fl->ifl_zone, *sd_cl); 2255 *sd_cl = NULL; 2256 if (*sd_m != NULL) { 2257 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2258 m_free_raw(*sd_m); 2259 *sd_m = NULL; 2260 } 2261 } else { 2262 MPASS(*sd_m == NULL); 2263 } 2264 #if MEMORY_LOGGING 2265 fl->ifl_m_dequeued++; 2266 fl->ifl_cl_dequeued++; 2267 #endif 2268 } 2269 #ifdef INVARIANTS 2270 for (i = 0; i < fl->ifl_size; i++) { 2271 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2272 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2273 } 2274 #endif 2275 /* 2276 * Reset free list values 2277 */ 2278 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2279 bzero(idi->idi_vaddr, idi->idi_size); 2280 } 2281 2282 /********************************************************************* 2283 * 2284 * Initialize a free list and its buffers. 2285 * 2286 **********************************************************************/ 2287 static int 2288 iflib_fl_setup(iflib_fl_t fl) 2289 { 2290 iflib_rxq_t rxq = fl->ifl_rxq; 2291 if_ctx_t ctx = rxq->ifr_ctx; 2292 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2293 int qidx; 2294 2295 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2296 /* 2297 ** Free current RX buffer structs and their mbufs 2298 */ 2299 iflib_fl_bufs_free(fl); 2300 /* Now replenish the mbufs */ 2301 MPASS(fl->ifl_credits == 0); 2302 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2303 if (scctx->isc_rxd_buf_size[qidx] != 0) 2304 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2305 else 2306 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2307 /* 2308 * ifl_buf_size may be a driver-supplied value, so pull it up 2309 * to the selected mbuf size. 2310 */ 2311 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2312 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2313 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2314 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2315 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2316 2317 /* 2318 * Avoid pre-allocating zillions of clusters to an idle card 2319 * potentially speeding up attach. In any case make sure 2320 * to leave a descriptor unavailable. See the comment in 2321 * iflib_fl_refill_all(). 2322 */ 2323 MPASS(fl->ifl_size > 0); 2324 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1)); 2325 if (min(128, fl->ifl_size - 1) != fl->ifl_credits) 2326 return (ENOBUFS); 2327 /* 2328 * handle failure 2329 */ 2330 MPASS(rxq != NULL); 2331 MPASS(fl->ifl_ifdi != NULL); 2332 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2333 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2334 return (0); 2335 } 2336 2337 /********************************************************************* 2338 * 2339 * Free receive ring data structures 2340 * 2341 **********************************************************************/ 2342 static void 2343 iflib_rx_sds_free(iflib_rxq_t rxq) 2344 { 2345 iflib_fl_t fl; 2346 int i, j; 2347 2348 if (rxq->ifr_fl != NULL) { 2349 for (i = 0; i < rxq->ifr_nfl; i++) { 2350 fl = &rxq->ifr_fl[i]; 2351 if (fl->ifl_buf_tag != NULL) { 2352 if (fl->ifl_sds.ifsd_map != NULL) { 2353 for (j = 0; j < fl->ifl_size; j++) { 2354 bus_dmamap_sync( 2355 fl->ifl_buf_tag, 2356 fl->ifl_sds.ifsd_map[j], 2357 BUS_DMASYNC_POSTREAD); 2358 bus_dmamap_unload( 2359 fl->ifl_buf_tag, 2360 fl->ifl_sds.ifsd_map[j]); 2361 bus_dmamap_destroy( 2362 fl->ifl_buf_tag, 2363 fl->ifl_sds.ifsd_map[j]); 2364 } 2365 } 2366 bus_dma_tag_destroy(fl->ifl_buf_tag); 2367 fl->ifl_buf_tag = NULL; 2368 } 2369 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2370 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2371 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2372 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2373 free(fl->ifl_rx_bitmap, M_IFLIB); 2374 fl->ifl_sds.ifsd_m = NULL; 2375 fl->ifl_sds.ifsd_cl = NULL; 2376 fl->ifl_sds.ifsd_ba = NULL; 2377 fl->ifl_sds.ifsd_map = NULL; 2378 fl->ifl_rx_bitmap = NULL; 2379 } 2380 free(rxq->ifr_fl, M_IFLIB); 2381 rxq->ifr_fl = NULL; 2382 free(rxq->ifr_ifdi, M_IFLIB); 2383 rxq->ifr_ifdi = NULL; 2384 rxq->ifr_cq_cidx = 0; 2385 } 2386 } 2387 2388 /* 2389 * Timer routine 2390 */ 2391 static void 2392 iflib_timer(void *arg) 2393 { 2394 iflib_txq_t txq = arg; 2395 if_ctx_t ctx = txq->ift_ctx; 2396 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2397 uint64_t this_tick = ticks; 2398 2399 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2400 return; 2401 2402 /* 2403 ** Check on the state of the TX queue(s), this 2404 ** can be done without the lock because its RO 2405 ** and the HUNG state will be static if set. 2406 */ 2407 if (this_tick - txq->ift_last_timer_tick >= iflib_timer_default) { 2408 txq->ift_last_timer_tick = this_tick; 2409 IFDI_TIMER(ctx, txq->ift_id); 2410 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2411 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2412 (sctx->isc_pause_frames == 0))) 2413 goto hung; 2414 2415 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE && 2416 ifmp_ring_is_stalled(txq->ift_br)) { 2417 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, 2418 ("queue can't be marked as hung if interface is down")); 2419 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2420 } 2421 txq->ift_cleaned_prev = txq->ift_cleaned; 2422 } 2423 /* handle any laggards */ 2424 if (txq->ift_db_pending) 2425 GROUPTASK_ENQUEUE(&txq->ift_task); 2426 2427 sctx->isc_pause_frames = 0; 2428 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2429 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, 2430 txq, txq->ift_timer.c_cpu); 2431 return; 2432 2433 hung: 2434 device_printf(ctx->ifc_dev, 2435 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2436 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2437 STATE_LOCK(ctx); 2438 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2439 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2440 iflib_admin_intr_deferred(ctx); 2441 STATE_UNLOCK(ctx); 2442 } 2443 2444 static uint16_t 2445 iflib_get_mbuf_size_for(unsigned int size) 2446 { 2447 2448 if (size <= MCLBYTES) 2449 return (MCLBYTES); 2450 else 2451 return (MJUMPAGESIZE); 2452 } 2453 2454 static void 2455 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2456 { 2457 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2458 2459 /* 2460 * XXX don't set the max_frame_size to larger 2461 * than the hardware can handle 2462 */ 2463 ctx->ifc_rx_mbuf_sz = 2464 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2465 } 2466 2467 uint32_t 2468 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2469 { 2470 2471 return (ctx->ifc_rx_mbuf_sz); 2472 } 2473 2474 static void 2475 iflib_init_locked(if_ctx_t ctx) 2476 { 2477 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2478 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2479 if_t ifp = ctx->ifc_ifp; 2480 iflib_fl_t fl; 2481 iflib_txq_t txq; 2482 iflib_rxq_t rxq; 2483 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2484 2485 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2486 IFDI_INTR_DISABLE(ctx); 2487 2488 /* 2489 * See iflib_stop(). Useful in case iflib_init_locked() is 2490 * called without first calling iflib_stop(). 2491 */ 2492 netmap_disable_all_rings(ifp); 2493 2494 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2495 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2496 /* Set hardware offload abilities */ 2497 if_clearhwassist(ifp); 2498 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2499 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2500 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2501 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2502 if (if_getcapenable(ifp) & IFCAP_TSO4) 2503 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2504 if (if_getcapenable(ifp) & IFCAP_TSO6) 2505 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2506 2507 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2508 CALLOUT_LOCK(txq); 2509 callout_stop(&txq->ift_timer); 2510 #ifdef DEV_NETMAP 2511 callout_stop(&txq->ift_netmap_timer); 2512 #endif /* DEV_NETMAP */ 2513 CALLOUT_UNLOCK(txq); 2514 (void)iflib_netmap_txq_init(ctx, txq); 2515 } 2516 2517 /* 2518 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2519 * that drivers can use the value when setting up the hardware receive 2520 * buffers. 2521 */ 2522 iflib_calc_rx_mbuf_sz(ctx); 2523 2524 #ifdef INVARIANTS 2525 i = if_getdrvflags(ifp); 2526 #endif 2527 IFDI_INIT(ctx); 2528 MPASS(if_getdrvflags(ifp) == i); 2529 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2530 if (iflib_netmap_rxq_init(ctx, rxq) > 0) { 2531 /* This rxq is in netmap mode. Skip normal init. */ 2532 continue; 2533 } 2534 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2535 if (iflib_fl_setup(fl)) { 2536 device_printf(ctx->ifc_dev, 2537 "setting up free list %d failed - " 2538 "check cluster settings\n", j); 2539 goto done; 2540 } 2541 } 2542 } 2543 done: 2544 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2545 IFDI_INTR_ENABLE(ctx); 2546 txq = ctx->ifc_txqs; 2547 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2548 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 2549 txq->ift_timer.c_cpu); 2550 2551 /* Re-enable txsync/rxsync. */ 2552 netmap_enable_all_rings(ifp); 2553 } 2554 2555 static int 2556 iflib_media_change(if_t ifp) 2557 { 2558 if_ctx_t ctx = if_getsoftc(ifp); 2559 int err; 2560 2561 CTX_LOCK(ctx); 2562 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2563 iflib_if_init_locked(ctx); 2564 CTX_UNLOCK(ctx); 2565 return (err); 2566 } 2567 2568 static void 2569 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2570 { 2571 if_ctx_t ctx = if_getsoftc(ifp); 2572 2573 CTX_LOCK(ctx); 2574 IFDI_UPDATE_ADMIN_STATUS(ctx); 2575 IFDI_MEDIA_STATUS(ctx, ifmr); 2576 CTX_UNLOCK(ctx); 2577 } 2578 2579 void 2580 iflib_stop(if_ctx_t ctx) 2581 { 2582 iflib_txq_t txq = ctx->ifc_txqs; 2583 iflib_rxq_t rxq = ctx->ifc_rxqs; 2584 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2585 if_shared_ctx_t sctx = ctx->ifc_sctx; 2586 iflib_dma_info_t di; 2587 iflib_fl_t fl; 2588 int i, j; 2589 2590 /* Tell the stack that the interface is no longer active */ 2591 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2592 2593 IFDI_INTR_DISABLE(ctx); 2594 DELAY(1000); 2595 IFDI_STOP(ctx); 2596 DELAY(1000); 2597 2598 /* 2599 * Stop any pending txsync/rxsync and prevent new ones 2600 * form starting. Processes blocked in poll() will get 2601 * POLLERR. 2602 */ 2603 netmap_disable_all_rings(ctx->ifc_ifp); 2604 2605 iflib_debug_reset(); 2606 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2607 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2608 /* make sure all transmitters have completed before proceeding XXX */ 2609 2610 CALLOUT_LOCK(txq); 2611 callout_stop(&txq->ift_timer); 2612 #ifdef DEV_NETMAP 2613 callout_stop(&txq->ift_netmap_timer); 2614 #endif /* DEV_NETMAP */ 2615 CALLOUT_UNLOCK(txq); 2616 2617 /* clean any enqueued buffers */ 2618 iflib_ifmp_purge(txq); 2619 /* Free any existing tx buffers. */ 2620 for (j = 0; j < txq->ift_size; j++) { 2621 iflib_txsd_free(ctx, txq, j); 2622 } 2623 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2624 txq->ift_in_use = txq->ift_gen = txq->ift_no_desc_avail = 0; 2625 if (sctx->isc_flags & IFLIB_PRESERVE_TX_INDICES) 2626 txq->ift_cidx = txq->ift_pidx; 2627 else 2628 txq->ift_cidx = txq->ift_pidx = 0; 2629 2630 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2631 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2632 txq->ift_pullups = 0; 2633 ifmp_ring_reset_stats(txq->ift_br); 2634 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2635 bzero((void *)di->idi_vaddr, di->idi_size); 2636 } 2637 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2638 gtaskqueue_drain(rxq->ifr_task.gt_taskqueue, 2639 &rxq->ifr_task.gt_task); 2640 2641 rxq->ifr_cq_cidx = 0; 2642 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2643 bzero((void *)di->idi_vaddr, di->idi_size); 2644 /* also resets the free lists pidx/cidx */ 2645 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2646 iflib_fl_bufs_free(fl); 2647 } 2648 } 2649 2650 static inline caddr_t 2651 calc_next_rxd(iflib_fl_t fl, int cidx) 2652 { 2653 qidx_t size; 2654 int nrxd; 2655 caddr_t start, end, cur, next; 2656 2657 nrxd = fl->ifl_size; 2658 size = fl->ifl_rxd_size; 2659 start = fl->ifl_ifdi->idi_vaddr; 2660 2661 if (__predict_false(size == 0)) 2662 return (start); 2663 cur = start + size*cidx; 2664 end = start + size*nrxd; 2665 next = CACHE_PTR_NEXT(cur); 2666 return (next < end ? next : start); 2667 } 2668 2669 static inline void 2670 prefetch_pkts(iflib_fl_t fl, int cidx) 2671 { 2672 int nextptr; 2673 int nrxd = fl->ifl_size; 2674 caddr_t next_rxd; 2675 2676 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2677 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2678 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2679 next_rxd = calc_next_rxd(fl, cidx); 2680 prefetch(next_rxd); 2681 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2682 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2683 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2684 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2685 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2686 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2687 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2688 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2689 } 2690 2691 static struct mbuf * 2692 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2693 int *pf_rv, if_rxd_info_t ri) 2694 { 2695 bus_dmamap_t map; 2696 iflib_fl_t fl; 2697 caddr_t payload; 2698 struct mbuf *m; 2699 int flid, cidx, len, next; 2700 2701 map = NULL; 2702 flid = irf->irf_flid; 2703 cidx = irf->irf_idx; 2704 fl = &rxq->ifr_fl[flid]; 2705 sd->ifsd_fl = fl; 2706 m = fl->ifl_sds.ifsd_m[cidx]; 2707 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2708 fl->ifl_credits--; 2709 #if MEMORY_LOGGING 2710 fl->ifl_m_dequeued++; 2711 #endif 2712 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2713 prefetch_pkts(fl, cidx); 2714 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2715 prefetch(&fl->ifl_sds.ifsd_map[next]); 2716 map = fl->ifl_sds.ifsd_map[cidx]; 2717 2718 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2719 2720 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 2721 irf->irf_len != 0) { 2722 payload = *sd->ifsd_cl; 2723 payload += ri->iri_pad; 2724 len = ri->iri_len - ri->iri_pad; 2725 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp, 2726 len | PFIL_MEMPTR | PFIL_IN, NULL); 2727 switch (*pf_rv) { 2728 case PFIL_DROPPED: 2729 case PFIL_CONSUMED: 2730 /* 2731 * The filter ate it. Everything is recycled. 2732 */ 2733 m = NULL; 2734 unload = 0; 2735 break; 2736 case PFIL_REALLOCED: 2737 /* 2738 * The filter copied it. Everything is recycled. 2739 */ 2740 m = pfil_mem2mbuf(payload); 2741 unload = 0; 2742 break; 2743 case PFIL_PASS: 2744 /* 2745 * Filter said it was OK, so receive like 2746 * normal 2747 */ 2748 fl->ifl_sds.ifsd_m[cidx] = NULL; 2749 break; 2750 default: 2751 MPASS(0); 2752 } 2753 } else { 2754 fl->ifl_sds.ifsd_m[cidx] = NULL; 2755 if (pf_rv != NULL) 2756 *pf_rv = PFIL_PASS; 2757 } 2758 2759 if (unload && irf->irf_len != 0) 2760 bus_dmamap_unload(fl->ifl_buf_tag, map); 2761 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2762 if (__predict_false(fl->ifl_cidx == 0)) 2763 fl->ifl_gen = 0; 2764 bit_clear(fl->ifl_rx_bitmap, cidx); 2765 return (m); 2766 } 2767 2768 static struct mbuf * 2769 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2770 { 2771 struct mbuf *m, *mh, *mt; 2772 caddr_t cl; 2773 int *pf_rv_ptr, flags, i, padlen; 2774 bool consumed; 2775 2776 i = 0; 2777 mh = NULL; 2778 consumed = false; 2779 *pf_rv = PFIL_PASS; 2780 pf_rv_ptr = pf_rv; 2781 do { 2782 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2783 pf_rv_ptr, ri); 2784 2785 MPASS(*sd->ifsd_cl != NULL); 2786 2787 /* 2788 * Exclude zero-length frags & frags from 2789 * packets the filter has consumed or dropped 2790 */ 2791 if (ri->iri_frags[i].irf_len == 0 || consumed || 2792 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2793 if (mh == NULL) { 2794 /* everything saved here */ 2795 consumed = true; 2796 pf_rv_ptr = NULL; 2797 continue; 2798 } 2799 /* XXX we can save the cluster here, but not the mbuf */ 2800 m_init(m, M_NOWAIT, MT_DATA, 0); 2801 m_free(m); 2802 continue; 2803 } 2804 if (mh == NULL) { 2805 flags = M_PKTHDR|M_EXT; 2806 mh = mt = m; 2807 padlen = ri->iri_pad; 2808 } else { 2809 flags = M_EXT; 2810 mt->m_next = m; 2811 mt = m; 2812 /* assuming padding is only on the first fragment */ 2813 padlen = 0; 2814 } 2815 cl = *sd->ifsd_cl; 2816 *sd->ifsd_cl = NULL; 2817 2818 /* Can these two be made one ? */ 2819 m_init(m, M_NOWAIT, MT_DATA, flags); 2820 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2821 /* 2822 * These must follow m_init and m_cljset 2823 */ 2824 m->m_data += padlen; 2825 ri->iri_len -= padlen; 2826 m->m_len = ri->iri_frags[i].irf_len; 2827 } while (++i < ri->iri_nfrags); 2828 2829 return (mh); 2830 } 2831 2832 /* 2833 * Process one software descriptor 2834 */ 2835 static struct mbuf * 2836 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2837 { 2838 struct if_rxsd sd; 2839 struct mbuf *m; 2840 int pf_rv; 2841 2842 /* should I merge this back in now that the two paths are basically duplicated? */ 2843 if (ri->iri_nfrags == 1 && 2844 ri->iri_frags[0].irf_len != 0 && 2845 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2846 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2847 &pf_rv, ri); 2848 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2849 return (m); 2850 if (pf_rv == PFIL_PASS) { 2851 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2852 #ifndef __NO_STRICT_ALIGNMENT 2853 if (!IP_ALIGNED(m) && ri->iri_pad == 0) 2854 m->m_data += 2; 2855 #endif 2856 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2857 m->m_len = ri->iri_frags[0].irf_len; 2858 m->m_data += ri->iri_pad; 2859 ri->iri_len -= ri->iri_pad; 2860 } 2861 } else { 2862 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2863 if (m == NULL) 2864 return (NULL); 2865 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2866 return (m); 2867 } 2868 m->m_pkthdr.len = ri->iri_len; 2869 m->m_pkthdr.rcvif = ri->iri_ifp; 2870 m->m_flags |= ri->iri_flags; 2871 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2872 m->m_pkthdr.flowid = ri->iri_flowid; 2873 M_HASHTYPE_SET(m, ri->iri_rsstype); 2874 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2875 m->m_pkthdr.csum_data = ri->iri_csum_data; 2876 return (m); 2877 } 2878 2879 #if defined(INET6) || defined(INET) 2880 static void 2881 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2882 { 2883 CURVNET_SET(lc->ifp->if_vnet); 2884 #if defined(INET6) 2885 *v6 = V_ip6_forwarding; 2886 #endif 2887 #if defined(INET) 2888 *v4 = V_ipforwarding; 2889 #endif 2890 CURVNET_RESTORE(); 2891 } 2892 2893 /* 2894 * Returns true if it's possible this packet could be LROed. 2895 * if it returns false, it is guaranteed that tcp_lro_rx() 2896 * would not return zero. 2897 */ 2898 static bool 2899 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2900 { 2901 struct ether_header *eh; 2902 2903 eh = mtod(m, struct ether_header *); 2904 switch (eh->ether_type) { 2905 #if defined(INET6) 2906 case htons(ETHERTYPE_IPV6): 2907 return (!v6_forwarding); 2908 #endif 2909 #if defined (INET) 2910 case htons(ETHERTYPE_IP): 2911 return (!v4_forwarding); 2912 #endif 2913 } 2914 2915 return false; 2916 } 2917 #else 2918 static void 2919 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2920 { 2921 } 2922 #endif 2923 2924 static void 2925 _task_fn_rx_watchdog(void *context) 2926 { 2927 iflib_rxq_t rxq = context; 2928 2929 GROUPTASK_ENQUEUE(&rxq->ifr_task); 2930 } 2931 2932 static uint8_t 2933 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2934 { 2935 if_t ifp; 2936 if_ctx_t ctx = rxq->ifr_ctx; 2937 if_shared_ctx_t sctx = ctx->ifc_sctx; 2938 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2939 int avail, i; 2940 qidx_t *cidxp; 2941 struct if_rxd_info ri; 2942 int err, budget_left, rx_bytes, rx_pkts; 2943 iflib_fl_t fl; 2944 int lro_enabled; 2945 bool v4_forwarding, v6_forwarding, lro_possible; 2946 uint8_t retval = 0; 2947 2948 /* 2949 * XXX early demux data packets so that if_input processing only handles 2950 * acks in interrupt context 2951 */ 2952 struct mbuf *m, *mh, *mt, *mf; 2953 2954 NET_EPOCH_ASSERT(); 2955 2956 lro_possible = v4_forwarding = v6_forwarding = false; 2957 ifp = ctx->ifc_ifp; 2958 mh = mt = NULL; 2959 MPASS(budget > 0); 2960 rx_pkts = rx_bytes = 0; 2961 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2962 cidxp = &rxq->ifr_cq_cidx; 2963 else 2964 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2965 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2966 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2967 retval |= iflib_fl_refill_all(ctx, fl); 2968 DBG_COUNTER_INC(rx_unavail); 2969 return (retval); 2970 } 2971 2972 /* pfil needs the vnet to be set */ 2973 CURVNET_SET_QUIET(ifp->if_vnet); 2974 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2975 if (__predict_false(!CTX_ACTIVE(ctx))) { 2976 DBG_COUNTER_INC(rx_ctx_inactive); 2977 break; 2978 } 2979 /* 2980 * Reset client set fields to their default values 2981 */ 2982 rxd_info_zero(&ri); 2983 ri.iri_qsidx = rxq->ifr_id; 2984 ri.iri_cidx = *cidxp; 2985 ri.iri_ifp = ifp; 2986 ri.iri_frags = rxq->ifr_frags; 2987 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2988 2989 if (err) 2990 goto err; 2991 rx_pkts += 1; 2992 rx_bytes += ri.iri_len; 2993 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2994 *cidxp = ri.iri_cidx; 2995 /* Update our consumer index */ 2996 /* XXX NB: shurd - check if this is still safe */ 2997 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2998 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2999 /* was this only a completion queue message? */ 3000 if (__predict_false(ri.iri_nfrags == 0)) 3001 continue; 3002 } 3003 MPASS(ri.iri_nfrags != 0); 3004 MPASS(ri.iri_len != 0); 3005 3006 /* will advance the cidx on the corresponding free lists */ 3007 m = iflib_rxd_pkt_get(rxq, &ri); 3008 avail--; 3009 budget_left--; 3010 if (avail == 0 && budget_left) 3011 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 3012 3013 if (__predict_false(m == NULL)) 3014 continue; 3015 3016 /* imm_pkt: -- cxgb */ 3017 if (mh == NULL) 3018 mh = mt = m; 3019 else { 3020 mt->m_nextpkt = m; 3021 mt = m; 3022 } 3023 } 3024 CURVNET_RESTORE(); 3025 /* make sure that we can refill faster than drain */ 3026 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 3027 retval |= iflib_fl_refill_all(ctx, fl); 3028 3029 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 3030 if (lro_enabled) 3031 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 3032 mt = mf = NULL; 3033 while (mh != NULL) { 3034 m = mh; 3035 mh = mh->m_nextpkt; 3036 m->m_nextpkt = NULL; 3037 #ifndef __NO_STRICT_ALIGNMENT 3038 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 3039 continue; 3040 #endif 3041 #if defined(INET6) || defined(INET) 3042 if (lro_enabled) { 3043 if (!lro_possible) { 3044 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 3045 if (lro_possible && mf != NULL) { 3046 ifp->if_input(ifp, mf); 3047 DBG_COUNTER_INC(rx_if_input); 3048 mt = mf = NULL; 3049 } 3050 } 3051 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 3052 (CSUM_L4_CALC|CSUM_L4_VALID)) { 3053 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 3054 continue; 3055 } 3056 } 3057 #endif 3058 if (lro_possible) { 3059 ifp->if_input(ifp, m); 3060 DBG_COUNTER_INC(rx_if_input); 3061 continue; 3062 } 3063 3064 if (mf == NULL) 3065 mf = m; 3066 if (mt != NULL) 3067 mt->m_nextpkt = m; 3068 mt = m; 3069 } 3070 if (mf != NULL) { 3071 ifp->if_input(ifp, mf); 3072 DBG_COUNTER_INC(rx_if_input); 3073 } 3074 3075 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 3076 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 3077 3078 /* 3079 * Flush any outstanding LRO work 3080 */ 3081 #if defined(INET6) || defined(INET) 3082 tcp_lro_flush_all(&rxq->ifr_lc); 3083 #endif 3084 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 3085 retval |= IFLIB_RXEOF_MORE; 3086 return (retval); 3087 err: 3088 STATE_LOCK(ctx); 3089 ctx->ifc_flags |= IFC_DO_RESET; 3090 iflib_admin_intr_deferred(ctx); 3091 STATE_UNLOCK(ctx); 3092 return (0); 3093 } 3094 3095 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 3096 static inline qidx_t 3097 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 3098 { 3099 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3100 qidx_t minthresh = txq->ift_size / 8; 3101 if (in_use > 4*minthresh) 3102 return (notify_count); 3103 if (in_use > 2*minthresh) 3104 return (notify_count >> 1); 3105 if (in_use > minthresh) 3106 return (notify_count >> 3); 3107 return (0); 3108 } 3109 3110 static inline qidx_t 3111 txq_max_rs_deferred(iflib_txq_t txq) 3112 { 3113 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3114 qidx_t minthresh = txq->ift_size / 8; 3115 if (txq->ift_in_use > 4*minthresh) 3116 return (notify_count); 3117 if (txq->ift_in_use > 2*minthresh) 3118 return (notify_count >> 1); 3119 if (txq->ift_in_use > minthresh) 3120 return (notify_count >> 2); 3121 return (2); 3122 } 3123 3124 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 3125 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 3126 3127 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 3128 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 3129 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 3130 3131 /* forward compatibility for cxgb */ 3132 #define FIRST_QSET(ctx) 0 3133 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 3134 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 3135 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 3136 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 3137 3138 /* XXX we should be setting this to something other than zero */ 3139 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 3140 #define MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 3141 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 3142 3143 static inline bool 3144 iflib_txd_db_check(iflib_txq_t txq, int ring) 3145 { 3146 if_ctx_t ctx = txq->ift_ctx; 3147 qidx_t dbval, max; 3148 3149 max = TXQ_MAX_DB_DEFERRED(txq, txq->ift_in_use); 3150 3151 /* force || threshold exceeded || at the edge of the ring */ 3152 if (ring || (txq->ift_db_pending >= max) || (TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx) + 2)) { 3153 3154 /* 3155 * 'npending' is used if the card's doorbell is in terms of the number of descriptors 3156 * pending flush (BRCM). 'pidx' is used in cases where the card's doorbeel uses the 3157 * producer index explicitly (INTC). 3158 */ 3159 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 3160 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3161 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3162 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 3163 3164 /* 3165 * Absent bugs there are zero packets pending so reset pending counts to zero. 3166 */ 3167 txq->ift_db_pending = txq->ift_npending = 0; 3168 return (true); 3169 } 3170 return (false); 3171 } 3172 3173 #ifdef PKT_DEBUG 3174 static void 3175 print_pkt(if_pkt_info_t pi) 3176 { 3177 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 3178 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 3179 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 3180 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 3181 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 3182 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 3183 } 3184 #endif 3185 3186 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 3187 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 3188 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 3189 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3190 3191 static int 3192 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3193 { 3194 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3195 struct ether_vlan_header *eh; 3196 struct mbuf *m; 3197 3198 m = *mp; 3199 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3200 M_WRITABLE(m) == 0) { 3201 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3202 return (ENOMEM); 3203 } else { 3204 m_freem(*mp); 3205 DBG_COUNTER_INC(tx_frees); 3206 *mp = m; 3207 } 3208 } 3209 3210 /* 3211 * Determine where frame payload starts. 3212 * Jump over vlan headers if already present, 3213 * helpful for QinQ too. 3214 */ 3215 if (__predict_false(m->m_len < sizeof(*eh))) { 3216 txq->ift_pullups++; 3217 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3218 return (ENOMEM); 3219 } 3220 eh = mtod(m, struct ether_vlan_header *); 3221 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3222 pi->ipi_etype = ntohs(eh->evl_proto); 3223 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3224 } else { 3225 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3226 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3227 } 3228 3229 switch (pi->ipi_etype) { 3230 #ifdef INET 3231 case ETHERTYPE_IP: 3232 { 3233 struct mbuf *n; 3234 struct ip *ip = NULL; 3235 struct tcphdr *th = NULL; 3236 int minthlen; 3237 3238 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3239 if (__predict_false(m->m_len < minthlen)) { 3240 /* 3241 * if this code bloat is causing too much of a hit 3242 * move it to a separate function and mark it noinline 3243 */ 3244 if (m->m_len == pi->ipi_ehdrlen) { 3245 n = m->m_next; 3246 MPASS(n); 3247 if (n->m_len >= sizeof(*ip)) { 3248 ip = (struct ip *)n->m_data; 3249 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3250 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3251 } else { 3252 txq->ift_pullups++; 3253 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3254 return (ENOMEM); 3255 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3256 } 3257 } else { 3258 txq->ift_pullups++; 3259 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3260 return (ENOMEM); 3261 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3262 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3263 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3264 } 3265 } else { 3266 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3267 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3268 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3269 } 3270 pi->ipi_ip_hlen = ip->ip_hl << 2; 3271 pi->ipi_ipproto = ip->ip_p; 3272 pi->ipi_flags |= IPI_TX_IPV4; 3273 3274 /* TCP checksum offload may require TCP header length */ 3275 if (IS_TX_OFFLOAD4(pi)) { 3276 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3277 if (__predict_false(th == NULL)) { 3278 txq->ift_pullups++; 3279 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3280 return (ENOMEM); 3281 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3282 } 3283 pi->ipi_tcp_hflags = th->th_flags; 3284 pi->ipi_tcp_hlen = th->th_off << 2; 3285 pi->ipi_tcp_seq = th->th_seq; 3286 } 3287 if (IS_TSO4(pi)) { 3288 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3289 return (ENXIO); 3290 /* 3291 * TSO always requires hardware checksum offload. 3292 */ 3293 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3294 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3295 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3296 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3297 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3298 ip->ip_sum = 0; 3299 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3300 } 3301 } 3302 } 3303 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3304 ip->ip_sum = 0; 3305 3306 break; 3307 } 3308 #endif 3309 #ifdef INET6 3310 case ETHERTYPE_IPV6: 3311 { 3312 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3313 struct tcphdr *th; 3314 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3315 3316 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3317 txq->ift_pullups++; 3318 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3319 return (ENOMEM); 3320 } 3321 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3322 3323 /* XXX-BZ this will go badly in case of ext hdrs. */ 3324 pi->ipi_ipproto = ip6->ip6_nxt; 3325 pi->ipi_flags |= IPI_TX_IPV6; 3326 3327 /* TCP checksum offload may require TCP header length */ 3328 if (IS_TX_OFFLOAD6(pi)) { 3329 if (pi->ipi_ipproto == IPPROTO_TCP) { 3330 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3331 txq->ift_pullups++; 3332 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3333 return (ENOMEM); 3334 } 3335 pi->ipi_tcp_hflags = th->th_flags; 3336 pi->ipi_tcp_hlen = th->th_off << 2; 3337 pi->ipi_tcp_seq = th->th_seq; 3338 } 3339 if (IS_TSO6(pi)) { 3340 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3341 return (ENXIO); 3342 /* 3343 * TSO always requires hardware checksum offload. 3344 */ 3345 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3346 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3347 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3348 } 3349 } 3350 break; 3351 } 3352 #endif 3353 default: 3354 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3355 pi->ipi_ip_hlen = 0; 3356 break; 3357 } 3358 *mp = m; 3359 3360 return (0); 3361 } 3362 3363 /* 3364 * If dodgy hardware rejects the scatter gather chain we've handed it 3365 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3366 * m_defrag'd mbufs 3367 */ 3368 static __noinline struct mbuf * 3369 iflib_remove_mbuf(iflib_txq_t txq) 3370 { 3371 int ntxd, pidx; 3372 struct mbuf *m, **ifsd_m; 3373 3374 ifsd_m = txq->ift_sds.ifsd_m; 3375 ntxd = txq->ift_size; 3376 pidx = txq->ift_pidx & (ntxd - 1); 3377 ifsd_m = txq->ift_sds.ifsd_m; 3378 m = ifsd_m[pidx]; 3379 ifsd_m[pidx] = NULL; 3380 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3381 if (txq->ift_sds.ifsd_tso_map != NULL) 3382 bus_dmamap_unload(txq->ift_tso_buf_tag, 3383 txq->ift_sds.ifsd_tso_map[pidx]); 3384 #if MEMORY_LOGGING 3385 txq->ift_dequeued++; 3386 #endif 3387 return (m); 3388 } 3389 3390 static inline caddr_t 3391 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3392 { 3393 qidx_t size; 3394 int ntxd; 3395 caddr_t start, end, cur, next; 3396 3397 ntxd = txq->ift_size; 3398 size = txq->ift_txd_size[qid]; 3399 start = txq->ift_ifdi[qid].idi_vaddr; 3400 3401 if (__predict_false(size == 0)) 3402 return (start); 3403 cur = start + size*cidx; 3404 end = start + size*ntxd; 3405 next = CACHE_PTR_NEXT(cur); 3406 return (next < end ? next : start); 3407 } 3408 3409 /* 3410 * Pad an mbuf to ensure a minimum ethernet frame size. 3411 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3412 */ 3413 static __noinline int 3414 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3415 { 3416 /* 3417 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3418 * and ARP message is the smallest common payload I can think of 3419 */ 3420 static char pad[18]; /* just zeros */ 3421 int n; 3422 struct mbuf *new_head; 3423 3424 if (!M_WRITABLE(*m_head)) { 3425 new_head = m_dup(*m_head, M_NOWAIT); 3426 if (new_head == NULL) { 3427 m_freem(*m_head); 3428 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3429 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3430 DBG_COUNTER_INC(tx_frees); 3431 return ENOMEM; 3432 } 3433 m_freem(*m_head); 3434 *m_head = new_head; 3435 } 3436 3437 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3438 n > 0; n -= sizeof(pad)) 3439 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3440 break; 3441 3442 if (n > 0) { 3443 m_freem(*m_head); 3444 device_printf(dev, "cannot pad short frame\n"); 3445 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3446 DBG_COUNTER_INC(tx_frees); 3447 return (ENOBUFS); 3448 } 3449 3450 return 0; 3451 } 3452 3453 static int 3454 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3455 { 3456 if_ctx_t ctx; 3457 if_shared_ctx_t sctx; 3458 if_softc_ctx_t scctx; 3459 bus_dma_tag_t buf_tag; 3460 bus_dma_segment_t *segs; 3461 struct mbuf *m_head, **ifsd_m; 3462 void *next_txd; 3463 bus_dmamap_t map; 3464 struct if_pkt_info pi; 3465 int remap = 0; 3466 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3467 3468 ctx = txq->ift_ctx; 3469 sctx = ctx->ifc_sctx; 3470 scctx = &ctx->ifc_softc_ctx; 3471 segs = txq->ift_segs; 3472 ntxd = txq->ift_size; 3473 m_head = *m_headp; 3474 map = NULL; 3475 3476 /* 3477 * If we're doing TSO the next descriptor to clean may be quite far ahead 3478 */ 3479 cidx = txq->ift_cidx; 3480 pidx = txq->ift_pidx; 3481 if (ctx->ifc_flags & IFC_PREFETCH) { 3482 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3483 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3484 next_txd = calc_next_txd(txq, cidx, 0); 3485 prefetch(next_txd); 3486 } 3487 3488 /* prefetch the next cache line of mbuf pointers and flags */ 3489 prefetch(&txq->ift_sds.ifsd_m[next]); 3490 prefetch(&txq->ift_sds.ifsd_map[next]); 3491 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3492 } 3493 map = txq->ift_sds.ifsd_map[pidx]; 3494 ifsd_m = txq->ift_sds.ifsd_m; 3495 3496 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3497 buf_tag = txq->ift_tso_buf_tag; 3498 max_segs = scctx->isc_tx_tso_segments_max; 3499 map = txq->ift_sds.ifsd_tso_map[pidx]; 3500 MPASS(buf_tag != NULL); 3501 MPASS(max_segs > 0); 3502 } else { 3503 buf_tag = txq->ift_buf_tag; 3504 max_segs = scctx->isc_tx_nsegments; 3505 map = txq->ift_sds.ifsd_map[pidx]; 3506 } 3507 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3508 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3509 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3510 if (err) { 3511 DBG_COUNTER_INC(encap_txd_encap_fail); 3512 return err; 3513 } 3514 } 3515 m_head = *m_headp; 3516 3517 pkt_info_zero(&pi); 3518 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3519 pi.ipi_pidx = pidx; 3520 pi.ipi_qsidx = txq->ift_id; 3521 pi.ipi_len = m_head->m_pkthdr.len; 3522 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3523 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3524 3525 /* deliberate bitwise OR to make one condition */ 3526 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3527 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3528 DBG_COUNTER_INC(encap_txd_encap_fail); 3529 return (err); 3530 } 3531 m_head = *m_headp; 3532 } 3533 3534 retry: 3535 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3536 BUS_DMA_NOWAIT); 3537 defrag: 3538 if (__predict_false(err)) { 3539 switch (err) { 3540 case EFBIG: 3541 /* try collapse once and defrag once */ 3542 if (remap == 0) { 3543 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3544 /* try defrag if collapsing fails */ 3545 if (m_head == NULL) 3546 remap++; 3547 } 3548 if (remap == 1) { 3549 txq->ift_mbuf_defrag++; 3550 m_head = m_defrag(*m_headp, M_NOWAIT); 3551 } 3552 /* 3553 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3554 * failed to map an mbuf that was run through m_defrag 3555 */ 3556 MPASS(remap <= 1); 3557 if (__predict_false(m_head == NULL || remap > 1)) 3558 goto defrag_failed; 3559 remap++; 3560 *m_headp = m_head; 3561 goto retry; 3562 break; 3563 case ENOMEM: 3564 txq->ift_no_tx_dma_setup++; 3565 break; 3566 default: 3567 txq->ift_no_tx_dma_setup++; 3568 m_freem(*m_headp); 3569 DBG_COUNTER_INC(tx_frees); 3570 *m_headp = NULL; 3571 break; 3572 } 3573 txq->ift_map_failed++; 3574 DBG_COUNTER_INC(encap_load_mbuf_fail); 3575 DBG_COUNTER_INC(encap_txd_encap_fail); 3576 return (err); 3577 } 3578 ifsd_m[pidx] = m_head; 3579 /* 3580 * XXX assumes a 1 to 1 relationship between segments and 3581 * descriptors - this does not hold true on all drivers, e.g. 3582 * cxgb 3583 */ 3584 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3585 txq->ift_no_desc_avail++; 3586 bus_dmamap_unload(buf_tag, map); 3587 DBG_COUNTER_INC(encap_txq_avail_fail); 3588 DBG_COUNTER_INC(encap_txd_encap_fail); 3589 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3590 GROUPTASK_ENQUEUE(&txq->ift_task); 3591 return (ENOBUFS); 3592 } 3593 /* 3594 * On Intel cards we can greatly reduce the number of TX interrupts 3595 * we see by only setting report status on every Nth descriptor. 3596 * However, this also means that the driver will need to keep track 3597 * of the descriptors that RS was set on to check them for the DD bit. 3598 */ 3599 txq->ift_rs_pending += nsegs + 1; 3600 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3601 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3602 pi.ipi_flags |= IPI_TX_INTR; 3603 txq->ift_rs_pending = 0; 3604 } 3605 3606 pi.ipi_segs = segs; 3607 pi.ipi_nsegs = nsegs; 3608 3609 MPASS(pidx >= 0 && pidx < txq->ift_size); 3610 #ifdef PKT_DEBUG 3611 print_pkt(&pi); 3612 #endif 3613 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3614 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3615 DBG_COUNTER_INC(tx_encap); 3616 MPASS(pi.ipi_new_pidx < txq->ift_size); 3617 3618 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3619 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3620 ndesc += txq->ift_size; 3621 txq->ift_gen = 1; 3622 } 3623 /* 3624 * drivers can need as many as 3625 * two sentinels 3626 */ 3627 MPASS(ndesc <= pi.ipi_nsegs + 2); 3628 MPASS(pi.ipi_new_pidx != pidx); 3629 MPASS(ndesc > 0); 3630 txq->ift_in_use += ndesc; 3631 txq->ift_db_pending += ndesc; 3632 3633 /* 3634 * We update the last software descriptor again here because there may 3635 * be a sentinel and/or there may be more mbufs than segments 3636 */ 3637 txq->ift_pidx = pi.ipi_new_pidx; 3638 txq->ift_npending += pi.ipi_ndescs; 3639 } else { 3640 *m_headp = m_head = iflib_remove_mbuf(txq); 3641 if (err == EFBIG) { 3642 txq->ift_txd_encap_efbig++; 3643 if (remap < 2) { 3644 remap = 1; 3645 goto defrag; 3646 } 3647 } 3648 goto defrag_failed; 3649 } 3650 /* 3651 * err can't possibly be non-zero here, so we don't neet to test it 3652 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3653 */ 3654 return (err); 3655 3656 defrag_failed: 3657 txq->ift_mbuf_defrag_failed++; 3658 txq->ift_map_failed++; 3659 m_freem(*m_headp); 3660 DBG_COUNTER_INC(tx_frees); 3661 *m_headp = NULL; 3662 DBG_COUNTER_INC(encap_txd_encap_fail); 3663 return (ENOMEM); 3664 } 3665 3666 static void 3667 iflib_tx_desc_free(iflib_txq_t txq, int n) 3668 { 3669 uint32_t qsize, cidx, mask, gen; 3670 struct mbuf *m, **ifsd_m; 3671 bool do_prefetch; 3672 3673 cidx = txq->ift_cidx; 3674 gen = txq->ift_gen; 3675 qsize = txq->ift_size; 3676 mask = qsize-1; 3677 ifsd_m = txq->ift_sds.ifsd_m; 3678 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3679 3680 while (n-- > 0) { 3681 if (do_prefetch) { 3682 prefetch(ifsd_m[(cidx + 3) & mask]); 3683 prefetch(ifsd_m[(cidx + 4) & mask]); 3684 } 3685 if ((m = ifsd_m[cidx]) != NULL) { 3686 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3687 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3688 bus_dmamap_sync(txq->ift_tso_buf_tag, 3689 txq->ift_sds.ifsd_tso_map[cidx], 3690 BUS_DMASYNC_POSTWRITE); 3691 bus_dmamap_unload(txq->ift_tso_buf_tag, 3692 txq->ift_sds.ifsd_tso_map[cidx]); 3693 } else { 3694 bus_dmamap_sync(txq->ift_buf_tag, 3695 txq->ift_sds.ifsd_map[cidx], 3696 BUS_DMASYNC_POSTWRITE); 3697 bus_dmamap_unload(txq->ift_buf_tag, 3698 txq->ift_sds.ifsd_map[cidx]); 3699 } 3700 /* XXX we don't support any drivers that batch packets yet */ 3701 MPASS(m->m_nextpkt == NULL); 3702 m_freem(m); 3703 ifsd_m[cidx] = NULL; 3704 #if MEMORY_LOGGING 3705 txq->ift_dequeued++; 3706 #endif 3707 DBG_COUNTER_INC(tx_frees); 3708 } 3709 if (__predict_false(++cidx == qsize)) { 3710 cidx = 0; 3711 gen = 0; 3712 } 3713 } 3714 txq->ift_cidx = cidx; 3715 txq->ift_gen = gen; 3716 } 3717 3718 static __inline int 3719 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3720 { 3721 int reclaim; 3722 if_ctx_t ctx = txq->ift_ctx; 3723 3724 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3725 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3726 3727 /* 3728 * Need a rate-limiting check so that this isn't called every time 3729 */ 3730 iflib_tx_credits_update(ctx, txq); 3731 reclaim = DESC_RECLAIMABLE(txq); 3732 3733 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3734 #ifdef INVARIANTS 3735 if (iflib_verbose_debug) { 3736 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3737 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3738 reclaim, thresh); 3739 } 3740 #endif 3741 return (0); 3742 } 3743 iflib_tx_desc_free(txq, reclaim); 3744 txq->ift_cleaned += reclaim; 3745 txq->ift_in_use -= reclaim; 3746 3747 return (reclaim); 3748 } 3749 3750 static struct mbuf ** 3751 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3752 { 3753 int next, size; 3754 struct mbuf **items; 3755 3756 size = r->size; 3757 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3758 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3759 3760 prefetch(items[(cidx + offset) & (size-1)]); 3761 if (remaining > 1) { 3762 prefetch2cachelines(&items[next]); 3763 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3764 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3765 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3766 } 3767 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3768 } 3769 3770 static void 3771 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3772 { 3773 3774 ifmp_ring_check_drainage(txq->ift_br, budget); 3775 } 3776 3777 static uint32_t 3778 iflib_txq_can_drain(struct ifmp_ring *r) 3779 { 3780 iflib_txq_t txq = r->cookie; 3781 if_ctx_t ctx = txq->ift_ctx; 3782 3783 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3784 return (1); 3785 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3786 BUS_DMASYNC_POSTREAD); 3787 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3788 false)); 3789 } 3790 3791 static uint32_t 3792 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3793 { 3794 iflib_txq_t txq = r->cookie; 3795 if_ctx_t ctx = txq->ift_ctx; 3796 if_t ifp = ctx->ifc_ifp; 3797 struct mbuf *m, **mp; 3798 int avail, bytes_sent, skipped, count, err, i; 3799 int mcast_sent, pkt_sent, reclaimed; 3800 bool do_prefetch, rang, ring; 3801 3802 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3803 !LINK_ACTIVE(ctx))) { 3804 DBG_COUNTER_INC(txq_drain_notready); 3805 return (0); 3806 } 3807 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3808 rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending); 3809 avail = IDXDIFF(pidx, cidx, r->size); 3810 3811 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3812 /* 3813 * The driver is unloading so we need to free all pending packets. 3814 */ 3815 DBG_COUNTER_INC(txq_drain_flushing); 3816 for (i = 0; i < avail; i++) { 3817 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3818 m_freem(r->items[(cidx + i) & (r->size-1)]); 3819 r->items[(cidx + i) & (r->size-1)] = NULL; 3820 } 3821 return (avail); 3822 } 3823 3824 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3825 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3826 CALLOUT_LOCK(txq); 3827 callout_stop(&txq->ift_timer); 3828 CALLOUT_UNLOCK(txq); 3829 DBG_COUNTER_INC(txq_drain_oactive); 3830 return (0); 3831 } 3832 3833 /* 3834 * If we've reclaimed any packets this queue cannot be hung. 3835 */ 3836 if (reclaimed) 3837 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3838 skipped = mcast_sent = bytes_sent = pkt_sent = 0; 3839 count = MIN(avail, TX_BATCH_SIZE); 3840 #ifdef INVARIANTS 3841 if (iflib_verbose_debug) 3842 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3843 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3844 #endif 3845 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3846 err = 0; 3847 for (i = 0; i < count && TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx) + 2; i++) { 3848 int rem = do_prefetch ? count - i : 0; 3849 3850 mp = _ring_peek_one(r, cidx, i, rem); 3851 MPASS(mp != NULL && *mp != NULL); 3852 3853 /* 3854 * Completion interrupts will use the address of the txq 3855 * as a sentinel to enqueue _something_ in order to acquire 3856 * the lock on the mp_ring (there's no direct lock call). 3857 * We obviously whave to check for these sentinel cases 3858 * and skip them. 3859 */ 3860 if (__predict_false(*mp == (struct mbuf *)txq)) { 3861 skipped++; 3862 continue; 3863 } 3864 err = iflib_encap(txq, mp); 3865 if (__predict_false(err)) { 3866 /* no room - bail out */ 3867 if (err == ENOBUFS) 3868 break; 3869 skipped++; 3870 /* we can't send this packet - skip it */ 3871 continue; 3872 } 3873 pkt_sent++; 3874 m = *mp; 3875 DBG_COUNTER_INC(tx_sent); 3876 bytes_sent += m->m_pkthdr.len; 3877 mcast_sent += !!(m->m_flags & M_MCAST); 3878 3879 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3880 break; 3881 ETHER_BPF_MTAP(ifp, m); 3882 rang = iflib_txd_db_check(txq, false); 3883 } 3884 3885 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3886 ring = rang ? false : (iflib_min_tx_latency | err); 3887 iflib_txd_db_check(txq, ring); 3888 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3889 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3890 if (mcast_sent) 3891 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3892 #ifdef INVARIANTS 3893 if (iflib_verbose_debug) 3894 printf("consumed=%d\n", skipped + pkt_sent); 3895 #endif 3896 return (skipped + pkt_sent); 3897 } 3898 3899 static uint32_t 3900 iflib_txq_drain_always(struct ifmp_ring *r) 3901 { 3902 return (1); 3903 } 3904 3905 static uint32_t 3906 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3907 { 3908 int i, avail; 3909 struct mbuf **mp; 3910 iflib_txq_t txq; 3911 3912 txq = r->cookie; 3913 3914 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3915 CALLOUT_LOCK(txq); 3916 callout_stop(&txq->ift_timer); 3917 CALLOUT_UNLOCK(txq); 3918 3919 avail = IDXDIFF(pidx, cidx, r->size); 3920 for (i = 0; i < avail; i++) { 3921 mp = _ring_peek_one(r, cidx, i, avail - i); 3922 if (__predict_false(*mp == (struct mbuf *)txq)) 3923 continue; 3924 m_freem(*mp); 3925 DBG_COUNTER_INC(tx_frees); 3926 } 3927 MPASS(ifmp_ring_is_stalled(r) == 0); 3928 return (avail); 3929 } 3930 3931 static void 3932 iflib_ifmp_purge(iflib_txq_t txq) 3933 { 3934 struct ifmp_ring *r; 3935 3936 r = txq->ift_br; 3937 r->drain = iflib_txq_drain_free; 3938 r->can_drain = iflib_txq_drain_always; 3939 3940 ifmp_ring_check_drainage(r, r->size); 3941 3942 r->drain = iflib_txq_drain; 3943 r->can_drain = iflib_txq_can_drain; 3944 } 3945 3946 static void 3947 _task_fn_tx(void *context) 3948 { 3949 iflib_txq_t txq = context; 3950 if_ctx_t ctx = txq->ift_ctx; 3951 if_t ifp = ctx->ifc_ifp; 3952 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3953 3954 #ifdef IFLIB_DIAGNOSTICS 3955 txq->ift_cpu_exec_count[curcpu]++; 3956 #endif 3957 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 3958 return; 3959 #ifdef DEV_NETMAP 3960 if ((if_getcapenable(ifp) & IFCAP_NETMAP) && 3961 netmap_tx_irq(ifp, txq->ift_id)) 3962 goto skip_ifmp; 3963 #endif 3964 #ifdef ALTQ 3965 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3966 iflib_altq_if_start(ifp); 3967 #endif 3968 if (txq->ift_db_pending) 3969 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3970 else if (!abdicate) 3971 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3972 /* 3973 * When abdicating, we always need to check drainage, not just when we don't enqueue 3974 */ 3975 if (abdicate) 3976 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3977 #ifdef DEV_NETMAP 3978 skip_ifmp: 3979 #endif 3980 if (ctx->ifc_flags & IFC_LEGACY) 3981 IFDI_INTR_ENABLE(ctx); 3982 else 3983 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3984 } 3985 3986 static void 3987 _task_fn_rx(void *context) 3988 { 3989 iflib_rxq_t rxq = context; 3990 if_ctx_t ctx = rxq->ifr_ctx; 3991 uint8_t more; 3992 uint16_t budget; 3993 #ifdef DEV_NETMAP 3994 u_int work = 0; 3995 int nmirq; 3996 #endif 3997 3998 #ifdef IFLIB_DIAGNOSTICS 3999 rxq->ifr_cpu_exec_count[curcpu]++; 4000 #endif 4001 DBG_COUNTER_INC(task_fn_rxs); 4002 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4003 return; 4004 #ifdef DEV_NETMAP 4005 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work); 4006 if (nmirq != NM_IRQ_PASS) { 4007 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0; 4008 goto skip_rxeof; 4009 } 4010 #endif 4011 budget = ctx->ifc_sysctl_rx_budget; 4012 if (budget == 0) 4013 budget = 16; /* XXX */ 4014 more = iflib_rxeof(rxq, budget); 4015 #ifdef DEV_NETMAP 4016 skip_rxeof: 4017 #endif 4018 if ((more & IFLIB_RXEOF_MORE) == 0) { 4019 if (ctx->ifc_flags & IFC_LEGACY) 4020 IFDI_INTR_ENABLE(ctx); 4021 else 4022 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 4023 DBG_COUNTER_INC(rx_intr_enables); 4024 } 4025 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4026 return; 4027 4028 if (more & IFLIB_RXEOF_MORE) 4029 GROUPTASK_ENQUEUE(&rxq->ifr_task); 4030 else if (more & IFLIB_RXEOF_EMPTY) 4031 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 4032 } 4033 4034 static void 4035 _task_fn_admin(void *context) 4036 { 4037 if_ctx_t ctx = context; 4038 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 4039 iflib_txq_t txq; 4040 int i; 4041 bool oactive, running, do_reset, do_watchdog, in_detach; 4042 4043 STATE_LOCK(ctx); 4044 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 4045 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 4046 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 4047 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 4048 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 4049 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 4050 STATE_UNLOCK(ctx); 4051 4052 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4053 return; 4054 if (in_detach) 4055 return; 4056 4057 CTX_LOCK(ctx); 4058 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4059 CALLOUT_LOCK(txq); 4060 callout_stop(&txq->ift_timer); 4061 CALLOUT_UNLOCK(txq); 4062 } 4063 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_ADMINCQ) 4064 IFDI_ADMIN_COMPLETION_HANDLE(ctx); 4065 if (do_watchdog) { 4066 ctx->ifc_watchdog_events++; 4067 IFDI_WATCHDOG_RESET(ctx); 4068 } 4069 IFDI_UPDATE_ADMIN_STATUS(ctx); 4070 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4071 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 4072 txq->ift_timer.c_cpu); 4073 } 4074 IFDI_LINK_INTR_ENABLE(ctx); 4075 if (do_reset) 4076 iflib_if_init_locked(ctx); 4077 CTX_UNLOCK(ctx); 4078 4079 if (LINK_ACTIVE(ctx) == 0) 4080 return; 4081 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 4082 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4083 } 4084 4085 static void 4086 _task_fn_iov(void *context) 4087 { 4088 if_ctx_t ctx = context; 4089 4090 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 4091 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4092 return; 4093 4094 CTX_LOCK(ctx); 4095 IFDI_VFLR_HANDLE(ctx); 4096 CTX_UNLOCK(ctx); 4097 } 4098 4099 static int 4100 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4101 { 4102 int err; 4103 if_int_delay_info_t info; 4104 if_ctx_t ctx; 4105 4106 info = (if_int_delay_info_t)arg1; 4107 ctx = info->iidi_ctx; 4108 info->iidi_req = req; 4109 info->iidi_oidp = oidp; 4110 CTX_LOCK(ctx); 4111 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 4112 CTX_UNLOCK(ctx); 4113 return (err); 4114 } 4115 4116 /********************************************************************* 4117 * 4118 * IFNET FUNCTIONS 4119 * 4120 **********************************************************************/ 4121 4122 static void 4123 iflib_if_init_locked(if_ctx_t ctx) 4124 { 4125 iflib_stop(ctx); 4126 iflib_init_locked(ctx); 4127 } 4128 4129 static void 4130 iflib_if_init(void *arg) 4131 { 4132 if_ctx_t ctx = arg; 4133 4134 CTX_LOCK(ctx); 4135 iflib_if_init_locked(ctx); 4136 CTX_UNLOCK(ctx); 4137 } 4138 4139 static int 4140 iflib_if_transmit(if_t ifp, struct mbuf *m) 4141 { 4142 if_ctx_t ctx = if_getsoftc(ifp); 4143 4144 iflib_txq_t txq; 4145 int err, qidx; 4146 int abdicate = ctx->ifc_sysctl_tx_abdicate; 4147 4148 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 4149 DBG_COUNTER_INC(tx_frees); 4150 m_freem(m); 4151 return (ENETDOWN); 4152 } 4153 4154 MPASS(m->m_nextpkt == NULL); 4155 /* ALTQ-enabled interfaces always use queue 0. */ 4156 qidx = 0; 4157 /* Use driver-supplied queue selection method if it exists */ 4158 if (ctx->isc_txq_select) 4159 qidx = ctx->isc_txq_select(ctx->ifc_softc, m); 4160 /* If not, use iflib's standard method */ 4161 else if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 4162 qidx = QIDX(ctx, m); 4163 4164 /* Set TX queue */ 4165 txq = &ctx->ifc_txqs[qidx]; 4166 4167 #ifdef DRIVER_BACKPRESSURE 4168 if (txq->ift_closed) { 4169 while (m != NULL) { 4170 next = m->m_nextpkt; 4171 m->m_nextpkt = NULL; 4172 m_freem(m); 4173 DBG_COUNTER_INC(tx_frees); 4174 m = next; 4175 } 4176 return (ENOBUFS); 4177 } 4178 #endif 4179 #ifdef notyet 4180 qidx = count = 0; 4181 mp = marr; 4182 next = m; 4183 do { 4184 count++; 4185 next = next->m_nextpkt; 4186 } while (next != NULL); 4187 4188 if (count > nitems(marr)) 4189 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 4190 /* XXX check nextpkt */ 4191 m_freem(m); 4192 /* XXX simplify for now */ 4193 DBG_COUNTER_INC(tx_frees); 4194 return (ENOBUFS); 4195 } 4196 for (next = m, i = 0; next != NULL; i++) { 4197 mp[i] = next; 4198 next = next->m_nextpkt; 4199 mp[i]->m_nextpkt = NULL; 4200 } 4201 #endif 4202 DBG_COUNTER_INC(tx_seen); 4203 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4204 4205 if (abdicate) 4206 GROUPTASK_ENQUEUE(&txq->ift_task); 4207 if (err) { 4208 if (!abdicate) 4209 GROUPTASK_ENQUEUE(&txq->ift_task); 4210 /* support forthcoming later */ 4211 #ifdef DRIVER_BACKPRESSURE 4212 txq->ift_closed = TRUE; 4213 #endif 4214 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4215 m_freem(m); 4216 DBG_COUNTER_INC(tx_frees); 4217 } 4218 4219 return (err); 4220 } 4221 4222 #ifdef ALTQ 4223 /* 4224 * The overall approach to integrating iflib with ALTQ is to continue to use 4225 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4226 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4227 * is redundant/unnecessary, but doing so minimizes the amount of 4228 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4229 * redundantly queueing to an intermediate mp_ring is swamped by the 4230 * performance limitations inherent in using ALTQ. 4231 * 4232 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4233 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4234 * given interface. If ALTQ is enabled for an interface, then all 4235 * transmitted packets for that interface will be submitted to the ALTQ 4236 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4237 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4238 * update stats that the iflib machinery handles, and which is sensitve to 4239 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4240 * will be installed as the start routine for use by ALTQ facilities that 4241 * need to trigger queue drains on a scheduled basis. 4242 * 4243 */ 4244 static void 4245 iflib_altq_if_start(if_t ifp) 4246 { 4247 struct ifaltq *ifq = &ifp->if_snd; 4248 struct mbuf *m; 4249 4250 IFQ_LOCK(ifq); 4251 IFQ_DEQUEUE_NOLOCK(ifq, m); 4252 while (m != NULL) { 4253 iflib_if_transmit(ifp, m); 4254 IFQ_DEQUEUE_NOLOCK(ifq, m); 4255 } 4256 IFQ_UNLOCK(ifq); 4257 } 4258 4259 static int 4260 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4261 { 4262 int err; 4263 4264 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4265 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4266 if (err == 0) 4267 iflib_altq_if_start(ifp); 4268 } else 4269 err = iflib_if_transmit(ifp, m); 4270 4271 return (err); 4272 } 4273 #endif /* ALTQ */ 4274 4275 static void 4276 iflib_if_qflush(if_t ifp) 4277 { 4278 if_ctx_t ctx = if_getsoftc(ifp); 4279 iflib_txq_t txq = ctx->ifc_txqs; 4280 int i; 4281 4282 STATE_LOCK(ctx); 4283 ctx->ifc_flags |= IFC_QFLUSH; 4284 STATE_UNLOCK(ctx); 4285 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4286 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4287 iflib_txq_check_drain(txq, 0); 4288 STATE_LOCK(ctx); 4289 ctx->ifc_flags &= ~IFC_QFLUSH; 4290 STATE_UNLOCK(ctx); 4291 4292 /* 4293 * When ALTQ is enabled, this will also take care of purging the 4294 * ALTQ queue(s). 4295 */ 4296 if_qflush(ifp); 4297 } 4298 4299 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4300 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4301 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4302 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_MEXTPG) 4303 4304 static int 4305 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4306 { 4307 if_ctx_t ctx = if_getsoftc(ifp); 4308 struct ifreq *ifr = (struct ifreq *)data; 4309 #if defined(INET) || defined(INET6) 4310 struct ifaddr *ifa = (struct ifaddr *)data; 4311 #endif 4312 bool avoid_reset = false; 4313 int err = 0, reinit = 0, bits; 4314 4315 switch (command) { 4316 case SIOCSIFADDR: 4317 #ifdef INET 4318 if (ifa->ifa_addr->sa_family == AF_INET) 4319 avoid_reset = true; 4320 #endif 4321 #ifdef INET6 4322 if (ifa->ifa_addr->sa_family == AF_INET6) 4323 avoid_reset = true; 4324 #endif 4325 /* 4326 ** Calling init results in link renegotiation, 4327 ** so we avoid doing it when possible. 4328 */ 4329 if (avoid_reset) { 4330 if_setflagbits(ifp, IFF_UP,0); 4331 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4332 reinit = 1; 4333 #ifdef INET 4334 if (!(if_getflags(ifp) & IFF_NOARP)) 4335 arp_ifinit(ifp, ifa); 4336 #endif 4337 } else 4338 err = ether_ioctl(ifp, command, data); 4339 break; 4340 case SIOCSIFMTU: 4341 CTX_LOCK(ctx); 4342 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4343 CTX_UNLOCK(ctx); 4344 break; 4345 } 4346 bits = if_getdrvflags(ifp); 4347 /* stop the driver and free any clusters before proceeding */ 4348 iflib_stop(ctx); 4349 4350 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4351 STATE_LOCK(ctx); 4352 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4353 ctx->ifc_flags |= IFC_MULTISEG; 4354 else 4355 ctx->ifc_flags &= ~IFC_MULTISEG; 4356 STATE_UNLOCK(ctx); 4357 err = if_setmtu(ifp, ifr->ifr_mtu); 4358 } 4359 iflib_init_locked(ctx); 4360 STATE_LOCK(ctx); 4361 if_setdrvflags(ifp, bits); 4362 STATE_UNLOCK(ctx); 4363 CTX_UNLOCK(ctx); 4364 break; 4365 case SIOCSIFFLAGS: 4366 CTX_LOCK(ctx); 4367 if (if_getflags(ifp) & IFF_UP) { 4368 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4369 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4370 (IFF_PROMISC | IFF_ALLMULTI)) { 4371 CTX_UNLOCK(ctx); 4372 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4373 CTX_LOCK(ctx); 4374 } 4375 } else 4376 reinit = 1; 4377 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4378 iflib_stop(ctx); 4379 } 4380 ctx->ifc_if_flags = if_getflags(ifp); 4381 CTX_UNLOCK(ctx); 4382 break; 4383 case SIOCADDMULTI: 4384 case SIOCDELMULTI: 4385 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4386 CTX_LOCK(ctx); 4387 IFDI_INTR_DISABLE(ctx); 4388 IFDI_MULTI_SET(ctx); 4389 IFDI_INTR_ENABLE(ctx); 4390 CTX_UNLOCK(ctx); 4391 } 4392 break; 4393 case SIOCSIFMEDIA: 4394 CTX_LOCK(ctx); 4395 IFDI_MEDIA_SET(ctx); 4396 CTX_UNLOCK(ctx); 4397 /* FALLTHROUGH */ 4398 case SIOCGIFMEDIA: 4399 case SIOCGIFXMEDIA: 4400 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4401 break; 4402 case SIOCGI2C: 4403 { 4404 struct ifi2creq i2c; 4405 4406 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4407 if (err != 0) 4408 break; 4409 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4410 err = EINVAL; 4411 break; 4412 } 4413 if (i2c.len > sizeof(i2c.data)) { 4414 err = EINVAL; 4415 break; 4416 } 4417 4418 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4419 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4420 sizeof(i2c)); 4421 break; 4422 } 4423 case SIOCSIFCAP: 4424 { 4425 int mask, setmask, oldmask; 4426 4427 oldmask = if_getcapenable(ifp); 4428 mask = ifr->ifr_reqcap ^ oldmask; 4429 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_MEXTPG; 4430 setmask = 0; 4431 #ifdef TCP_OFFLOAD 4432 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4433 #endif 4434 setmask |= (mask & IFCAP_FLAGS); 4435 setmask |= (mask & IFCAP_WOL); 4436 4437 /* 4438 * If any RX csum has changed, change all the ones that 4439 * are supported by the driver. 4440 */ 4441 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4442 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4443 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4444 } 4445 4446 /* 4447 * want to ensure that traffic has stopped before we change any of the flags 4448 */ 4449 if (setmask) { 4450 CTX_LOCK(ctx); 4451 bits = if_getdrvflags(ifp); 4452 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4453 iflib_stop(ctx); 4454 STATE_LOCK(ctx); 4455 if_togglecapenable(ifp, setmask); 4456 ctx->ifc_softc_ctx.isc_capenable ^= setmask; 4457 STATE_UNLOCK(ctx); 4458 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4459 iflib_init_locked(ctx); 4460 STATE_LOCK(ctx); 4461 if_setdrvflags(ifp, bits); 4462 STATE_UNLOCK(ctx); 4463 CTX_UNLOCK(ctx); 4464 } 4465 if_vlancap(ifp); 4466 break; 4467 } 4468 case SIOCGPRIVATE_0: 4469 case SIOCSDRVSPEC: 4470 case SIOCGDRVSPEC: 4471 CTX_LOCK(ctx); 4472 err = IFDI_PRIV_IOCTL(ctx, command, data); 4473 CTX_UNLOCK(ctx); 4474 break; 4475 default: 4476 err = ether_ioctl(ifp, command, data); 4477 break; 4478 } 4479 if (reinit) 4480 iflib_if_init(ctx); 4481 return (err); 4482 } 4483 4484 static uint64_t 4485 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4486 { 4487 if_ctx_t ctx = if_getsoftc(ifp); 4488 4489 return (IFDI_GET_COUNTER(ctx, cnt)); 4490 } 4491 4492 /********************************************************************* 4493 * 4494 * OTHER FUNCTIONS EXPORTED TO THE STACK 4495 * 4496 **********************************************************************/ 4497 4498 static void 4499 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4500 { 4501 if_ctx_t ctx = if_getsoftc(ifp); 4502 4503 if ((void *)ctx != arg) 4504 return; 4505 4506 if ((vtag == 0) || (vtag > 4095)) 4507 return; 4508 4509 if (iflib_in_detach(ctx)) 4510 return; 4511 4512 CTX_LOCK(ctx); 4513 /* Driver may need all untagged packets to be flushed */ 4514 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4515 iflib_stop(ctx); 4516 IFDI_VLAN_REGISTER(ctx, vtag); 4517 /* Re-init to load the changes, if required */ 4518 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4519 iflib_init_locked(ctx); 4520 CTX_UNLOCK(ctx); 4521 } 4522 4523 static void 4524 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4525 { 4526 if_ctx_t ctx = if_getsoftc(ifp); 4527 4528 if ((void *)ctx != arg) 4529 return; 4530 4531 if ((vtag == 0) || (vtag > 4095)) 4532 return; 4533 4534 CTX_LOCK(ctx); 4535 /* Driver may need all tagged packets to be flushed */ 4536 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4537 iflib_stop(ctx); 4538 IFDI_VLAN_UNREGISTER(ctx, vtag); 4539 /* Re-init to load the changes, if required */ 4540 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4541 iflib_init_locked(ctx); 4542 CTX_UNLOCK(ctx); 4543 } 4544 4545 static void 4546 iflib_led_func(void *arg, int onoff) 4547 { 4548 if_ctx_t ctx = arg; 4549 4550 CTX_LOCK(ctx); 4551 IFDI_LED_FUNC(ctx, onoff); 4552 CTX_UNLOCK(ctx); 4553 } 4554 4555 /********************************************************************* 4556 * 4557 * BUS FUNCTION DEFINITIONS 4558 * 4559 **********************************************************************/ 4560 4561 int 4562 iflib_device_probe(device_t dev) 4563 { 4564 const pci_vendor_info_t *ent; 4565 if_shared_ctx_t sctx; 4566 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4567 uint16_t pci_vendor_id; 4568 4569 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4570 return (ENOTSUP); 4571 4572 pci_vendor_id = pci_get_vendor(dev); 4573 pci_device_id = pci_get_device(dev); 4574 pci_subvendor_id = pci_get_subvendor(dev); 4575 pci_subdevice_id = pci_get_subdevice(dev); 4576 pci_rev_id = pci_get_revid(dev); 4577 if (sctx->isc_parse_devinfo != NULL) 4578 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4579 4580 ent = sctx->isc_vendor_info; 4581 while (ent->pvi_vendor_id != 0) { 4582 if (pci_vendor_id != ent->pvi_vendor_id) { 4583 ent++; 4584 continue; 4585 } 4586 if ((pci_device_id == ent->pvi_device_id) && 4587 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4588 (ent->pvi_subvendor_id == 0)) && 4589 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4590 (ent->pvi_subdevice_id == 0)) && 4591 ((pci_rev_id == ent->pvi_rev_id) || 4592 (ent->pvi_rev_id == 0))) { 4593 device_set_desc_copy(dev, ent->pvi_name); 4594 /* this needs to be changed to zero if the bus probing code 4595 * ever stops re-probing on best match because the sctx 4596 * may have its values over written by register calls 4597 * in subsequent probes 4598 */ 4599 return (BUS_PROBE_DEFAULT); 4600 } 4601 ent++; 4602 } 4603 return (ENXIO); 4604 } 4605 4606 int 4607 iflib_device_probe_vendor(device_t dev) 4608 { 4609 int probe; 4610 4611 probe = iflib_device_probe(dev); 4612 if (probe == BUS_PROBE_DEFAULT) 4613 return (BUS_PROBE_VENDOR); 4614 else 4615 return (probe); 4616 } 4617 4618 static void 4619 iflib_reset_qvalues(if_ctx_t ctx) 4620 { 4621 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4622 if_shared_ctx_t sctx = ctx->ifc_sctx; 4623 device_t dev = ctx->ifc_dev; 4624 int i; 4625 4626 if (ctx->ifc_sysctl_ntxqs != 0) 4627 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4628 if (ctx->ifc_sysctl_nrxqs != 0) 4629 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4630 4631 for (i = 0; i < sctx->isc_ntxqs; i++) { 4632 if (ctx->ifc_sysctl_ntxds[i] != 0) 4633 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4634 else 4635 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4636 } 4637 4638 for (i = 0; i < sctx->isc_nrxqs; i++) { 4639 if (ctx->ifc_sysctl_nrxds[i] != 0) 4640 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4641 else 4642 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4643 } 4644 4645 for (i = 0; i < sctx->isc_nrxqs; i++) { 4646 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4647 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4648 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4649 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4650 } 4651 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4652 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4653 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4654 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4655 } 4656 if (!powerof2(scctx->isc_nrxd[i])) { 4657 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4658 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4659 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4660 } 4661 } 4662 4663 for (i = 0; i < sctx->isc_ntxqs; i++) { 4664 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4665 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4666 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4667 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4668 } 4669 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4670 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4671 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4672 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4673 } 4674 if (!powerof2(scctx->isc_ntxd[i])) { 4675 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4676 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4677 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4678 } 4679 } 4680 } 4681 4682 static void 4683 iflib_add_pfil(if_ctx_t ctx) 4684 { 4685 struct pfil_head *pfil; 4686 struct pfil_head_args pa; 4687 iflib_rxq_t rxq; 4688 int i; 4689 4690 pa.pa_version = PFIL_VERSION; 4691 pa.pa_flags = PFIL_IN; 4692 pa.pa_type = PFIL_TYPE_ETHERNET; 4693 pa.pa_headname = ctx->ifc_ifp->if_xname; 4694 pfil = pfil_head_register(&pa); 4695 4696 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4697 rxq->pfil = pfil; 4698 } 4699 } 4700 4701 static void 4702 iflib_rem_pfil(if_ctx_t ctx) 4703 { 4704 struct pfil_head *pfil; 4705 iflib_rxq_t rxq; 4706 int i; 4707 4708 rxq = ctx->ifc_rxqs; 4709 pfil = rxq->pfil; 4710 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4711 rxq->pfil = NULL; 4712 } 4713 pfil_head_unregister(pfil); 4714 } 4715 4716 4717 /* 4718 * Advance forward by n members of the cpuset ctx->ifc_cpus starting from 4719 * cpuid and wrapping as necessary. 4720 */ 4721 static unsigned int 4722 cpuid_advance(if_ctx_t ctx, unsigned int cpuid, unsigned int n) 4723 { 4724 unsigned int first_valid; 4725 unsigned int last_valid; 4726 4727 /* cpuid should always be in the valid set */ 4728 MPASS(CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4729 4730 /* valid set should never be empty */ 4731 MPASS(!CPU_EMPTY(&ctx->ifc_cpus)); 4732 4733 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 4734 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 4735 n = n % CPU_COUNT(&ctx->ifc_cpus); 4736 while (n > 0) { 4737 do { 4738 cpuid++; 4739 if (cpuid > last_valid) 4740 cpuid = first_valid; 4741 } while (!CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4742 n--; 4743 } 4744 4745 return (cpuid); 4746 } 4747 4748 #if defined(SMP) && defined(SCHED_ULE) 4749 extern struct cpu_group *cpu_top; /* CPU topology */ 4750 4751 static int 4752 find_child_with_core(int cpu, struct cpu_group *grp) 4753 { 4754 int i; 4755 4756 if (grp->cg_children == 0) 4757 return -1; 4758 4759 MPASS(grp->cg_child); 4760 for (i = 0; i < grp->cg_children; i++) { 4761 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 4762 return i; 4763 } 4764 4765 return -1; 4766 } 4767 4768 4769 /* 4770 * Find an L2 neighbor of the given CPU or return -1 if none found. This 4771 * does not distinguish among multiple L2 neighbors if the given CPU has 4772 * more than one (it will always return the same result in that case). 4773 */ 4774 static int 4775 find_l2_neighbor(int cpu) 4776 { 4777 struct cpu_group *grp; 4778 int i; 4779 4780 grp = cpu_top; 4781 if (grp == NULL) 4782 return -1; 4783 4784 /* 4785 * Find the smallest CPU group that contains the given core. 4786 */ 4787 i = 0; 4788 while ((i = find_child_with_core(cpu, grp)) != -1) { 4789 /* 4790 * If the smallest group containing the given CPU has less 4791 * than two members, we conclude the given CPU has no 4792 * L2 neighbor. 4793 */ 4794 if (grp->cg_child[i].cg_count <= 1) 4795 return (-1); 4796 grp = &grp->cg_child[i]; 4797 } 4798 4799 /* Must share L2. */ 4800 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 4801 return -1; 4802 4803 /* 4804 * Select the first member of the set that isn't the reference 4805 * CPU, which at this point is guaranteed to exist. 4806 */ 4807 for (i = 0; i < CPU_SETSIZE; i++) { 4808 if (CPU_ISSET(i, &grp->cg_mask) && i != cpu) 4809 return (i); 4810 } 4811 4812 /* Should never be reached */ 4813 return (-1); 4814 } 4815 4816 #else 4817 static int 4818 find_l2_neighbor(int cpu) 4819 { 4820 4821 return (-1); 4822 } 4823 #endif 4824 4825 /* 4826 * CPU mapping behaviors 4827 * --------------------- 4828 * 'separate txrx' refers to the separate_txrx sysctl 4829 * 'use logical' refers to the use_logical_cores sysctl 4830 * 'INTR CPUS' indicates whether bus_get_cpus(INTR_CPUS) succeeded 4831 * 4832 * separate use INTR 4833 * txrx logical CPUS result 4834 * ---------- --------- ------ ------------------------------------------------ 4835 * - - X RX and TX queues mapped to consecutive physical 4836 * cores with RX/TX pairs on same core and excess 4837 * of either following 4838 * - X X RX and TX queues mapped to consecutive cores 4839 * of any type with RX/TX pairs on same core and 4840 * excess of either following 4841 * X - X RX and TX queues mapped to consecutive physical 4842 * cores; all RX then all TX 4843 * X X X RX queues mapped to consecutive physical cores 4844 * first, then TX queues mapped to L2 neighbor of 4845 * the corresponding RX queue if one exists, 4846 * otherwise to consecutive physical cores 4847 * - n/a - RX and TX queues mapped to consecutive cores of 4848 * any type with RX/TX pairs on same core and excess 4849 * of either following 4850 * X n/a - RX and TX queues mapped to consecutive cores of 4851 * any type; all RX then all TX 4852 */ 4853 static unsigned int 4854 get_cpuid_for_queue(if_ctx_t ctx, unsigned int base_cpuid, unsigned int qid, 4855 bool is_tx) 4856 { 4857 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4858 unsigned int core_index; 4859 4860 if (ctx->ifc_sysctl_separate_txrx) { 4861 /* 4862 * When using separate CPUs for TX and RX, the assignment 4863 * will always be of a consecutive CPU out of the set of 4864 * context CPUs, except for the specific case where the 4865 * context CPUs are phsyical cores, the use of logical cores 4866 * has been enabled, the assignment is for TX, the TX qid 4867 * corresponds to an RX qid, and the CPU assigned to the 4868 * corresponding RX queue has an L2 neighbor. 4869 */ 4870 if (ctx->ifc_sysctl_use_logical_cores && 4871 ctx->ifc_cpus_are_physical_cores && 4872 is_tx && qid < scctx->isc_nrxqsets) { 4873 int l2_neighbor; 4874 unsigned int rx_cpuid; 4875 4876 rx_cpuid = cpuid_advance(ctx, base_cpuid, qid); 4877 l2_neighbor = find_l2_neighbor(rx_cpuid); 4878 if (l2_neighbor != -1) { 4879 return (l2_neighbor); 4880 } 4881 /* 4882 * ... else fall through to the normal 4883 * consecutive-after-RX assignment scheme. 4884 * 4885 * Note that we are assuming that all RX queue CPUs 4886 * have an L2 neighbor, or all do not. If a mixed 4887 * scenario is possible, we will have to keep track 4888 * separately of how many queues prior to this one 4889 * were not able to be assigned to an L2 neighbor. 4890 */ 4891 } 4892 if (is_tx) 4893 core_index = scctx->isc_nrxqsets + qid; 4894 else 4895 core_index = qid; 4896 } else { 4897 core_index = qid; 4898 } 4899 4900 return (cpuid_advance(ctx, base_cpuid, core_index)); 4901 } 4902 4903 static uint16_t 4904 get_ctx_core_offset(if_ctx_t ctx) 4905 { 4906 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4907 struct cpu_offset *op; 4908 cpuset_t assigned_cpus; 4909 unsigned int cores_consumed; 4910 unsigned int base_cpuid = ctx->ifc_sysctl_core_offset; 4911 unsigned int first_valid; 4912 unsigned int last_valid; 4913 unsigned int i; 4914 4915 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 4916 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 4917 4918 if (base_cpuid != CORE_OFFSET_UNSPECIFIED) { 4919 /* 4920 * Align the user-chosen base CPU ID to the next valid CPU 4921 * for this device. If the chosen base CPU ID is smaller 4922 * than the first valid CPU or larger than the last valid 4923 * CPU, we assume the user does not know what the valid 4924 * range is for this device and is thinking in terms of a 4925 * zero-based reference frame, and so we shift the given 4926 * value into the valid range (and wrap accordingly) so the 4927 * intent is translated to the proper frame of reference. 4928 * If the base CPU ID is within the valid first/last, but 4929 * does not correspond to a valid CPU, it is advanced to the 4930 * next valid CPU (wrapping if necessary). 4931 */ 4932 if (base_cpuid < first_valid || base_cpuid > last_valid) { 4933 /* shift from zero-based to first_valid-based */ 4934 base_cpuid += first_valid; 4935 /* wrap to range [first_valid, last_valid] */ 4936 base_cpuid = (base_cpuid - first_valid) % 4937 (last_valid - first_valid + 1); 4938 } 4939 if (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) { 4940 /* 4941 * base_cpuid is in [first_valid, last_valid], but 4942 * not a member of the valid set. In this case, 4943 * there will always be a member of the valid set 4944 * with a CPU ID that is greater than base_cpuid, 4945 * and we simply advance to it. 4946 */ 4947 while (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) 4948 base_cpuid++; 4949 } 4950 return (base_cpuid); 4951 } 4952 4953 /* 4954 * Determine how many cores will be consumed by performing the CPU 4955 * assignments and counting how many of the assigned CPUs correspond 4956 * to CPUs in the set of context CPUs. This is done using the CPU 4957 * ID first_valid as the base CPU ID, as the base CPU must be within 4958 * the set of context CPUs. 4959 * 4960 * Note not all assigned CPUs will be in the set of context CPUs 4961 * when separate CPUs are being allocated to TX and RX queues, 4962 * assignment to logical cores has been enabled, the set of context 4963 * CPUs contains only physical CPUs, and TX queues are mapped to L2 4964 * neighbors of CPUs that RX queues have been mapped to - in this 4965 * case we do only want to count how many CPUs in the set of context 4966 * CPUs have been consumed, as that determines the next CPU in that 4967 * set to start allocating at for the next device for which 4968 * core_offset is not set. 4969 */ 4970 CPU_ZERO(&assigned_cpus); 4971 for (i = 0; i < scctx->isc_ntxqsets; i++) 4972 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, true), 4973 &assigned_cpus); 4974 for (i = 0; i < scctx->isc_nrxqsets; i++) 4975 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, false), 4976 &assigned_cpus); 4977 CPU_AND(&assigned_cpus, &assigned_cpus, &ctx->ifc_cpus); 4978 cores_consumed = CPU_COUNT(&assigned_cpus); 4979 4980 mtx_lock(&cpu_offset_mtx); 4981 SLIST_FOREACH(op, &cpu_offsets, entries) { 4982 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4983 base_cpuid = op->next_cpuid; 4984 op->next_cpuid = cpuid_advance(ctx, op->next_cpuid, 4985 cores_consumed); 4986 MPASS(op->refcount < UINT_MAX); 4987 op->refcount++; 4988 break; 4989 } 4990 } 4991 if (base_cpuid == CORE_OFFSET_UNSPECIFIED) { 4992 base_cpuid = first_valid; 4993 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 4994 M_NOWAIT | M_ZERO); 4995 if (op == NULL) { 4996 device_printf(ctx->ifc_dev, 4997 "allocation for cpu offset failed.\n"); 4998 } else { 4999 op->next_cpuid = cpuid_advance(ctx, base_cpuid, 5000 cores_consumed); 5001 op->refcount = 1; 5002 CPU_COPY(&ctx->ifc_cpus, &op->set); 5003 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 5004 } 5005 } 5006 mtx_unlock(&cpu_offset_mtx); 5007 5008 return (base_cpuid); 5009 } 5010 5011 static void 5012 unref_ctx_core_offset(if_ctx_t ctx) 5013 { 5014 struct cpu_offset *op, *top; 5015 5016 mtx_lock(&cpu_offset_mtx); 5017 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 5018 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 5019 MPASS(op->refcount > 0); 5020 op->refcount--; 5021 if (op->refcount == 0) { 5022 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 5023 free(op, M_IFLIB); 5024 } 5025 break; 5026 } 5027 } 5028 mtx_unlock(&cpu_offset_mtx); 5029 } 5030 5031 int 5032 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 5033 { 5034 if_ctx_t ctx; 5035 if_t ifp; 5036 if_softc_ctx_t scctx; 5037 kobjop_desc_t kobj_desc; 5038 kobj_method_t *kobj_method; 5039 int err, msix, rid; 5040 int num_txd, num_rxd; 5041 5042 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 5043 5044 if (sc == NULL) { 5045 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 5046 device_set_softc(dev, ctx); 5047 ctx->ifc_flags |= IFC_SC_ALLOCATED; 5048 } 5049 5050 ctx->ifc_sctx = sctx; 5051 ctx->ifc_dev = dev; 5052 ctx->ifc_softc = sc; 5053 5054 if ((err = iflib_register(ctx)) != 0) { 5055 device_printf(dev, "iflib_register failed %d\n", err); 5056 goto fail_ctx_free; 5057 } 5058 iflib_add_device_sysctl_pre(ctx); 5059 5060 scctx = &ctx->ifc_softc_ctx; 5061 ifp = ctx->ifc_ifp; 5062 5063 iflib_reset_qvalues(ctx); 5064 IFNET_WLOCK(); 5065 CTX_LOCK(ctx); 5066 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 5067 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 5068 goto fail_unlock; 5069 } 5070 _iflib_pre_assert(scctx); 5071 ctx->ifc_txrx = *scctx->isc_txrx; 5072 5073 MPASS(scctx->isc_dma_width <= flsll(BUS_SPACE_MAXADDR)); 5074 5075 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 5076 ctx->ifc_mediap = scctx->isc_media; 5077 5078 #ifdef INVARIANTS 5079 if (scctx->isc_capabilities & IFCAP_TXCSUM) 5080 MPASS(scctx->isc_tx_csum_flags); 5081 #endif 5082 5083 if_setcapabilities(ifp, 5084 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_MEXTPG); 5085 if_setcapenable(ifp, 5086 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_MEXTPG); 5087 5088 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 5089 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 5090 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 5091 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 5092 5093 num_txd = iflib_num_tx_descs(ctx); 5094 num_rxd = iflib_num_rx_descs(ctx); 5095 5096 /* XXX change for per-queue sizes */ 5097 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 5098 num_txd, num_rxd); 5099 5100 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 5101 scctx->isc_tx_nsegments = max(1, num_txd / 5102 MAX_SINGLE_PACKET_FRACTION); 5103 if (scctx->isc_tx_tso_segments_max > num_txd / 5104 MAX_SINGLE_PACKET_FRACTION) 5105 scctx->isc_tx_tso_segments_max = max(1, 5106 num_txd / MAX_SINGLE_PACKET_FRACTION); 5107 5108 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5109 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5110 /* 5111 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5112 * but some MACs do. 5113 */ 5114 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5115 IP_MAXPACKET)); 5116 /* 5117 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5118 * into account. In the worst case, each of these calls will 5119 * add another mbuf and, thus, the requirement for another DMA 5120 * segment. So for best performance, it doesn't make sense to 5121 * advertize a maximum of TSO segments that typically will 5122 * require defragmentation in iflib_encap(). 5123 */ 5124 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5125 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5126 } 5127 if (scctx->isc_rss_table_size == 0) 5128 scctx->isc_rss_table_size = 64; 5129 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 5130 5131 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5132 /* XXX format name */ 5133 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 5134 NULL, NULL, "admin"); 5135 5136 /* Set up cpu set. If it fails, use the set of all CPUs. */ 5137 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 5138 device_printf(dev, "Unable to fetch CPU list\n"); 5139 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 5140 ctx->ifc_cpus_are_physical_cores = false; 5141 } else 5142 ctx->ifc_cpus_are_physical_cores = true; 5143 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 5144 5145 /* 5146 ** Now set up MSI or MSI-X, should return us the number of supported 5147 ** vectors (will be 1 for a legacy interrupt and MSI). 5148 */ 5149 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 5150 msix = scctx->isc_vectors; 5151 } else if (scctx->isc_msix_bar != 0) 5152 /* 5153 * The simple fact that isc_msix_bar is not 0 does not mean we 5154 * we have a good value there that is known to work. 5155 */ 5156 msix = iflib_msix_init(ctx); 5157 else { 5158 scctx->isc_vectors = 1; 5159 scctx->isc_ntxqsets = 1; 5160 scctx->isc_nrxqsets = 1; 5161 scctx->isc_intr = IFLIB_INTR_LEGACY; 5162 msix = 0; 5163 } 5164 /* Get memory for the station queues */ 5165 if ((err = iflib_queues_alloc(ctx))) { 5166 device_printf(dev, "Unable to allocate queue memory\n"); 5167 goto fail_intr_free; 5168 } 5169 5170 if ((err = iflib_qset_structures_setup(ctx))) 5171 goto fail_queues; 5172 5173 /* 5174 * Now that we know how many queues there are, get the core offset. 5175 */ 5176 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 5177 5178 if (msix > 1) { 5179 /* 5180 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 5181 * aren't the default NULL implementation. 5182 */ 5183 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 5184 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5185 kobj_desc); 5186 if (kobj_method == &kobj_desc->deflt) { 5187 device_printf(dev, 5188 "MSI-X requires ifdi_rx_queue_intr_enable method"); 5189 err = EOPNOTSUPP; 5190 goto fail_queues; 5191 } 5192 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 5193 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5194 kobj_desc); 5195 if (kobj_method == &kobj_desc->deflt) { 5196 device_printf(dev, 5197 "MSI-X requires ifdi_tx_queue_intr_enable method"); 5198 err = EOPNOTSUPP; 5199 goto fail_queues; 5200 } 5201 5202 /* 5203 * Assign the MSI-X vectors. 5204 * Note that the default NULL ifdi_msix_intr_assign method will 5205 * fail here, too. 5206 */ 5207 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 5208 if (err != 0) { 5209 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 5210 err); 5211 goto fail_queues; 5212 } 5213 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 5214 rid = 0; 5215 if (scctx->isc_intr == IFLIB_INTR_MSI) { 5216 MPASS(msix == 1); 5217 rid = 1; 5218 } 5219 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 5220 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 5221 goto fail_queues; 5222 } 5223 } else { 5224 device_printf(dev, 5225 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 5226 err = ENODEV; 5227 goto fail_queues; 5228 } 5229 5230 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5231 5232 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5233 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5234 goto fail_detach; 5235 } 5236 5237 /* 5238 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5239 * This must appear after the call to ether_ifattach() because 5240 * ether_ifattach() sets if_hdrlen to the default value. 5241 */ 5242 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5243 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5244 5245 if ((err = iflib_netmap_attach(ctx))) { 5246 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 5247 goto fail_detach; 5248 } 5249 *ctxp = ctx; 5250 5251 DEBUGNET_SET(ctx->ifc_ifp, iflib); 5252 5253 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5254 iflib_add_device_sysctl_post(ctx); 5255 iflib_add_pfil(ctx); 5256 ctx->ifc_flags |= IFC_INIT_DONE; 5257 CTX_UNLOCK(ctx); 5258 IFNET_WUNLOCK(); 5259 5260 return (0); 5261 5262 fail_detach: 5263 ether_ifdetach(ctx->ifc_ifp); 5264 fail_queues: 5265 iflib_tqg_detach(ctx); 5266 iflib_tx_structures_free(ctx); 5267 iflib_rx_structures_free(ctx); 5268 IFDI_DETACH(ctx); 5269 IFDI_QUEUES_FREE(ctx); 5270 fail_intr_free: 5271 iflib_free_intr_mem(ctx); 5272 fail_unlock: 5273 CTX_UNLOCK(ctx); 5274 IFNET_WUNLOCK(); 5275 iflib_deregister(ctx); 5276 fail_ctx_free: 5277 device_set_softc(ctx->ifc_dev, NULL); 5278 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5279 free(ctx->ifc_softc, M_IFLIB); 5280 free(ctx, M_IFLIB); 5281 return (err); 5282 } 5283 5284 int 5285 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 5286 struct iflib_cloneattach_ctx *clctx) 5287 { 5288 int num_txd, num_rxd; 5289 int err; 5290 if_ctx_t ctx; 5291 if_t ifp; 5292 if_softc_ctx_t scctx; 5293 int i; 5294 void *sc; 5295 5296 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 5297 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 5298 ctx->ifc_flags |= IFC_SC_ALLOCATED; 5299 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 5300 ctx->ifc_flags |= IFC_PSEUDO; 5301 5302 ctx->ifc_sctx = sctx; 5303 ctx->ifc_softc = sc; 5304 ctx->ifc_dev = dev; 5305 5306 if ((err = iflib_register(ctx)) != 0) { 5307 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 5308 goto fail_ctx_free; 5309 } 5310 iflib_add_device_sysctl_pre(ctx); 5311 5312 scctx = &ctx->ifc_softc_ctx; 5313 ifp = ctx->ifc_ifp; 5314 5315 iflib_reset_qvalues(ctx); 5316 CTX_LOCK(ctx); 5317 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 5318 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 5319 goto fail_unlock; 5320 } 5321 if (sctx->isc_flags & IFLIB_GEN_MAC) 5322 ether_gen_addr(ifp, &ctx->ifc_mac); 5323 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 5324 clctx->cc_params)) != 0) { 5325 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 5326 goto fail_unlock; 5327 } 5328 #ifdef INVARIANTS 5329 if (scctx->isc_capabilities & IFCAP_TXCSUM) 5330 MPASS(scctx->isc_tx_csum_flags); 5331 #endif 5332 5333 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 5334 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 5335 5336 ifp->if_flags |= IFF_NOGROUP; 5337 if (sctx->isc_flags & IFLIB_PSEUDO) { 5338 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 5339 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 5340 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) { 5341 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5342 } else { 5343 if_attach(ctx->ifc_ifp); 5344 bpfattach(ctx->ifc_ifp, DLT_NULL, sizeof(u_int32_t)); 5345 } 5346 5347 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5348 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5349 goto fail_detach; 5350 } 5351 *ctxp = ctx; 5352 5353 /* 5354 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5355 * This must appear after the call to ether_ifattach() because 5356 * ether_ifattach() sets if_hdrlen to the default value. 5357 */ 5358 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5359 if_setifheaderlen(ifp, 5360 sizeof(struct ether_vlan_header)); 5361 5362 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5363 iflib_add_device_sysctl_post(ctx); 5364 ctx->ifc_flags |= IFC_INIT_DONE; 5365 CTX_UNLOCK(ctx); 5366 return (0); 5367 } 5368 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 5369 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 5370 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 5371 5372 _iflib_pre_assert(scctx); 5373 ctx->ifc_txrx = *scctx->isc_txrx; 5374 5375 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 5376 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 5377 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 5378 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 5379 5380 num_txd = iflib_num_tx_descs(ctx); 5381 num_rxd = iflib_num_rx_descs(ctx); 5382 5383 /* XXX change for per-queue sizes */ 5384 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 5385 num_txd, num_rxd); 5386 5387 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 5388 scctx->isc_tx_nsegments = max(1, num_txd / 5389 MAX_SINGLE_PACKET_FRACTION); 5390 if (scctx->isc_tx_tso_segments_max > num_txd / 5391 MAX_SINGLE_PACKET_FRACTION) 5392 scctx->isc_tx_tso_segments_max = max(1, 5393 num_txd / MAX_SINGLE_PACKET_FRACTION); 5394 5395 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5396 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5397 /* 5398 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5399 * but some MACs do. 5400 */ 5401 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5402 IP_MAXPACKET)); 5403 /* 5404 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5405 * into account. In the worst case, each of these calls will 5406 * add another mbuf and, thus, the requirement for another DMA 5407 * segment. So for best performance, it doesn't make sense to 5408 * advertize a maximum of TSO segments that typically will 5409 * require defragmentation in iflib_encap(). 5410 */ 5411 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5412 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5413 } 5414 if (scctx->isc_rss_table_size == 0) 5415 scctx->isc_rss_table_size = 64; 5416 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 5417 5418 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5419 /* XXX format name */ 5420 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 5421 NULL, NULL, "admin"); 5422 5423 /* XXX --- can support > 1 -- but keep it simple for now */ 5424 scctx->isc_intr = IFLIB_INTR_LEGACY; 5425 5426 /* Get memory for the station queues */ 5427 if ((err = iflib_queues_alloc(ctx))) { 5428 device_printf(dev, "Unable to allocate queue memory\n"); 5429 goto fail_iflib_detach; 5430 } 5431 5432 if ((err = iflib_qset_structures_setup(ctx))) { 5433 device_printf(dev, "qset structure setup failed %d\n", err); 5434 goto fail_queues; 5435 } 5436 5437 /* 5438 * XXX What if anything do we want to do about interrupts? 5439 */ 5440 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5441 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5442 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5443 goto fail_detach; 5444 } 5445 5446 /* 5447 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5448 * This must appear after the call to ether_ifattach() because 5449 * ether_ifattach() sets if_hdrlen to the default value. 5450 */ 5451 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5452 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5453 5454 /* XXX handle more than one queue */ 5455 for (i = 0; i < scctx->isc_nrxqsets; i++) 5456 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 5457 5458 *ctxp = ctx; 5459 5460 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5461 iflib_add_device_sysctl_post(ctx); 5462 ctx->ifc_flags |= IFC_INIT_DONE; 5463 CTX_UNLOCK(ctx); 5464 5465 return (0); 5466 fail_detach: 5467 ether_ifdetach(ctx->ifc_ifp); 5468 fail_queues: 5469 iflib_tqg_detach(ctx); 5470 iflib_tx_structures_free(ctx); 5471 iflib_rx_structures_free(ctx); 5472 fail_iflib_detach: 5473 IFDI_DETACH(ctx); 5474 IFDI_QUEUES_FREE(ctx); 5475 fail_unlock: 5476 CTX_UNLOCK(ctx); 5477 iflib_deregister(ctx); 5478 fail_ctx_free: 5479 free(ctx->ifc_softc, M_IFLIB); 5480 free(ctx, M_IFLIB); 5481 return (err); 5482 } 5483 5484 int 5485 iflib_pseudo_deregister(if_ctx_t ctx) 5486 { 5487 if_t ifp = ctx->ifc_ifp; 5488 if_shared_ctx_t sctx = ctx->ifc_sctx; 5489 5490 /* Unregister VLAN event handlers early */ 5491 iflib_unregister_vlan_handlers(ctx); 5492 5493 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5494 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) { 5495 bpfdetach(ifp); 5496 if_detach(ifp); 5497 } else { 5498 ether_ifdetach(ifp); 5499 } 5500 5501 iflib_tqg_detach(ctx); 5502 iflib_tx_structures_free(ctx); 5503 iflib_rx_structures_free(ctx); 5504 IFDI_DETACH(ctx); 5505 IFDI_QUEUES_FREE(ctx); 5506 5507 iflib_deregister(ctx); 5508 5509 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5510 free(ctx->ifc_softc, M_IFLIB); 5511 free(ctx, M_IFLIB); 5512 return (0); 5513 } 5514 5515 int 5516 iflib_device_attach(device_t dev) 5517 { 5518 if_ctx_t ctx; 5519 if_shared_ctx_t sctx; 5520 5521 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5522 return (ENOTSUP); 5523 5524 pci_enable_busmaster(dev); 5525 5526 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5527 } 5528 5529 int 5530 iflib_device_deregister(if_ctx_t ctx) 5531 { 5532 if_t ifp = ctx->ifc_ifp; 5533 device_t dev = ctx->ifc_dev; 5534 5535 /* Make sure VLANS are not using driver */ 5536 if (if_vlantrunkinuse(ifp)) { 5537 device_printf(dev, "Vlan in use, detach first\n"); 5538 return (EBUSY); 5539 } 5540 #ifdef PCI_IOV 5541 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5542 device_printf(dev, "SR-IOV in use; detach first.\n"); 5543 return (EBUSY); 5544 } 5545 #endif 5546 5547 STATE_LOCK(ctx); 5548 ctx->ifc_flags |= IFC_IN_DETACH; 5549 STATE_UNLOCK(ctx); 5550 5551 /* Unregister VLAN handlers before calling iflib_stop() */ 5552 iflib_unregister_vlan_handlers(ctx); 5553 5554 iflib_netmap_detach(ifp); 5555 ether_ifdetach(ifp); 5556 5557 CTX_LOCK(ctx); 5558 iflib_stop(ctx); 5559 CTX_UNLOCK(ctx); 5560 5561 iflib_rem_pfil(ctx); 5562 if (ctx->ifc_led_dev != NULL) 5563 led_destroy(ctx->ifc_led_dev); 5564 5565 iflib_tqg_detach(ctx); 5566 iflib_tx_structures_free(ctx); 5567 iflib_rx_structures_free(ctx); 5568 5569 CTX_LOCK(ctx); 5570 IFDI_DETACH(ctx); 5571 IFDI_QUEUES_FREE(ctx); 5572 CTX_UNLOCK(ctx); 5573 5574 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5575 iflib_free_intr_mem(ctx); 5576 5577 bus_generic_detach(dev); 5578 5579 iflib_deregister(ctx); 5580 5581 device_set_softc(ctx->ifc_dev, NULL); 5582 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5583 free(ctx->ifc_softc, M_IFLIB); 5584 unref_ctx_core_offset(ctx); 5585 free(ctx, M_IFLIB); 5586 return (0); 5587 } 5588 5589 static void 5590 iflib_tqg_detach(if_ctx_t ctx) 5591 { 5592 iflib_txq_t txq; 5593 iflib_rxq_t rxq; 5594 int i; 5595 struct taskqgroup *tqg; 5596 5597 /* XXX drain any dependent tasks */ 5598 tqg = qgroup_if_io_tqg; 5599 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5600 callout_drain(&txq->ift_timer); 5601 #ifdef DEV_NETMAP 5602 callout_drain(&txq->ift_netmap_timer); 5603 #endif /* DEV_NETMAP */ 5604 if (txq->ift_task.gt_uniq != NULL) 5605 taskqgroup_detach(tqg, &txq->ift_task); 5606 } 5607 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5608 if (rxq->ifr_task.gt_uniq != NULL) 5609 taskqgroup_detach(tqg, &rxq->ifr_task); 5610 } 5611 tqg = qgroup_if_config_tqg; 5612 if (ctx->ifc_admin_task.gt_uniq != NULL) 5613 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5614 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5615 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5616 } 5617 5618 static void 5619 iflib_free_intr_mem(if_ctx_t ctx) 5620 { 5621 5622 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5623 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5624 } 5625 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5626 pci_release_msi(ctx->ifc_dev); 5627 } 5628 if (ctx->ifc_msix_mem != NULL) { 5629 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5630 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5631 ctx->ifc_msix_mem = NULL; 5632 } 5633 } 5634 5635 int 5636 iflib_device_detach(device_t dev) 5637 { 5638 if_ctx_t ctx = device_get_softc(dev); 5639 5640 return (iflib_device_deregister(ctx)); 5641 } 5642 5643 int 5644 iflib_device_suspend(device_t dev) 5645 { 5646 if_ctx_t ctx = device_get_softc(dev); 5647 5648 CTX_LOCK(ctx); 5649 IFDI_SUSPEND(ctx); 5650 CTX_UNLOCK(ctx); 5651 5652 return bus_generic_suspend(dev); 5653 } 5654 int 5655 iflib_device_shutdown(device_t dev) 5656 { 5657 if_ctx_t ctx = device_get_softc(dev); 5658 5659 CTX_LOCK(ctx); 5660 IFDI_SHUTDOWN(ctx); 5661 CTX_UNLOCK(ctx); 5662 5663 return bus_generic_suspend(dev); 5664 } 5665 5666 int 5667 iflib_device_resume(device_t dev) 5668 { 5669 if_ctx_t ctx = device_get_softc(dev); 5670 iflib_txq_t txq = ctx->ifc_txqs; 5671 5672 CTX_LOCK(ctx); 5673 IFDI_RESUME(ctx); 5674 iflib_if_init_locked(ctx); 5675 CTX_UNLOCK(ctx); 5676 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5677 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5678 5679 return (bus_generic_resume(dev)); 5680 } 5681 5682 int 5683 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5684 { 5685 int error; 5686 if_ctx_t ctx = device_get_softc(dev); 5687 5688 CTX_LOCK(ctx); 5689 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5690 CTX_UNLOCK(ctx); 5691 5692 return (error); 5693 } 5694 5695 void 5696 iflib_device_iov_uninit(device_t dev) 5697 { 5698 if_ctx_t ctx = device_get_softc(dev); 5699 5700 CTX_LOCK(ctx); 5701 IFDI_IOV_UNINIT(ctx); 5702 CTX_UNLOCK(ctx); 5703 } 5704 5705 int 5706 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5707 { 5708 int error; 5709 if_ctx_t ctx = device_get_softc(dev); 5710 5711 CTX_LOCK(ctx); 5712 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5713 CTX_UNLOCK(ctx); 5714 5715 return (error); 5716 } 5717 5718 /********************************************************************* 5719 * 5720 * MODULE FUNCTION DEFINITIONS 5721 * 5722 **********************************************************************/ 5723 5724 /* 5725 * - Start a fast taskqueue thread for each core 5726 * - Start a taskqueue for control operations 5727 */ 5728 static int 5729 iflib_module_init(void) 5730 { 5731 iflib_timer_default = hz / 2; 5732 return (0); 5733 } 5734 5735 static int 5736 iflib_module_event_handler(module_t mod, int what, void *arg) 5737 { 5738 int err; 5739 5740 switch (what) { 5741 case MOD_LOAD: 5742 if ((err = iflib_module_init()) != 0) 5743 return (err); 5744 break; 5745 case MOD_UNLOAD: 5746 return (EBUSY); 5747 default: 5748 return (EOPNOTSUPP); 5749 } 5750 5751 return (0); 5752 } 5753 5754 /********************************************************************* 5755 * 5756 * PUBLIC FUNCTION DEFINITIONS 5757 * ordered as in iflib.h 5758 * 5759 **********************************************************************/ 5760 5761 static void 5762 _iflib_assert(if_shared_ctx_t sctx) 5763 { 5764 int i; 5765 5766 MPASS(sctx->isc_tx_maxsize); 5767 MPASS(sctx->isc_tx_maxsegsize); 5768 5769 MPASS(sctx->isc_rx_maxsize); 5770 MPASS(sctx->isc_rx_nsegments); 5771 MPASS(sctx->isc_rx_maxsegsize); 5772 5773 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5774 for (i = 0; i < sctx->isc_nrxqs; i++) { 5775 MPASS(sctx->isc_nrxd_min[i]); 5776 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5777 MPASS(sctx->isc_nrxd_max[i]); 5778 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5779 MPASS(sctx->isc_nrxd_default[i]); 5780 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5781 } 5782 5783 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5784 for (i = 0; i < sctx->isc_ntxqs; i++) { 5785 MPASS(sctx->isc_ntxd_min[i]); 5786 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5787 MPASS(sctx->isc_ntxd_max[i]); 5788 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5789 MPASS(sctx->isc_ntxd_default[i]); 5790 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5791 } 5792 } 5793 5794 static void 5795 _iflib_pre_assert(if_softc_ctx_t scctx) 5796 { 5797 5798 MPASS(scctx->isc_txrx->ift_txd_encap); 5799 MPASS(scctx->isc_txrx->ift_txd_flush); 5800 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5801 MPASS(scctx->isc_txrx->ift_rxd_available); 5802 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5803 MPASS(scctx->isc_txrx->ift_rxd_refill); 5804 MPASS(scctx->isc_txrx->ift_rxd_flush); 5805 } 5806 5807 static int 5808 iflib_register(if_ctx_t ctx) 5809 { 5810 if_shared_ctx_t sctx = ctx->ifc_sctx; 5811 driver_t *driver = sctx->isc_driver; 5812 device_t dev = ctx->ifc_dev; 5813 if_t ifp; 5814 u_char type; 5815 int iflags; 5816 5817 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0) 5818 _iflib_assert(sctx); 5819 5820 CTX_LOCK_INIT(ctx); 5821 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5822 if (sctx->isc_flags & IFLIB_PSEUDO) { 5823 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) 5824 type = IFT_ETHER; 5825 else 5826 type = IFT_PPP; 5827 } else 5828 type = IFT_ETHER; 5829 ifp = ctx->ifc_ifp = if_alloc(type); 5830 if (ifp == NULL) { 5831 device_printf(dev, "can not allocate ifnet structure\n"); 5832 return (ENOMEM); 5833 } 5834 5835 /* 5836 * Initialize our context's device specific methods 5837 */ 5838 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5839 kobj_class_compile((kobj_class_t) driver); 5840 5841 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5842 if_setsoftc(ifp, ctx); 5843 if_setdev(ifp, dev); 5844 if_setinitfn(ifp, iflib_if_init); 5845 if_setioctlfn(ifp, iflib_if_ioctl); 5846 #ifdef ALTQ 5847 if_setstartfn(ifp, iflib_altq_if_start); 5848 if_settransmitfn(ifp, iflib_altq_if_transmit); 5849 if_setsendqready(ifp); 5850 #else 5851 if_settransmitfn(ifp, iflib_if_transmit); 5852 #endif 5853 if_setqflushfn(ifp, iflib_if_qflush); 5854 iflags = IFF_MULTICAST | IFF_KNOWSEPOCH; 5855 5856 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5857 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) 5858 iflags |= IFF_POINTOPOINT; 5859 else 5860 iflags |= IFF_BROADCAST | IFF_SIMPLEX; 5861 if_setflags(ifp, iflags); 5862 ctx->ifc_vlan_attach_event = 5863 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5864 EVENTHANDLER_PRI_FIRST); 5865 ctx->ifc_vlan_detach_event = 5866 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5867 EVENTHANDLER_PRI_FIRST); 5868 5869 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5870 ctx->ifc_mediap = &ctx->ifc_media; 5871 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5872 iflib_media_change, iflib_media_status); 5873 } 5874 return (0); 5875 } 5876 5877 static void 5878 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5879 { 5880 /* Unregister VLAN events */ 5881 if (ctx->ifc_vlan_attach_event != NULL) { 5882 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5883 ctx->ifc_vlan_attach_event = NULL; 5884 } 5885 if (ctx->ifc_vlan_detach_event != NULL) { 5886 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5887 ctx->ifc_vlan_detach_event = NULL; 5888 } 5889 5890 } 5891 5892 static void 5893 iflib_deregister(if_ctx_t ctx) 5894 { 5895 if_t ifp = ctx->ifc_ifp; 5896 5897 /* Remove all media */ 5898 ifmedia_removeall(&ctx->ifc_media); 5899 5900 /* Ensure that VLAN event handlers are unregistered */ 5901 iflib_unregister_vlan_handlers(ctx); 5902 5903 /* Release kobject reference */ 5904 kobj_delete((kobj_t) ctx, NULL); 5905 5906 /* Free the ifnet structure */ 5907 if_free(ifp); 5908 5909 STATE_LOCK_DESTROY(ctx); 5910 5911 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5912 CTX_LOCK_DESTROY(ctx); 5913 } 5914 5915 static int 5916 iflib_queues_alloc(if_ctx_t ctx) 5917 { 5918 if_shared_ctx_t sctx = ctx->ifc_sctx; 5919 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5920 device_t dev = ctx->ifc_dev; 5921 int nrxqsets = scctx->isc_nrxqsets; 5922 int ntxqsets = scctx->isc_ntxqsets; 5923 iflib_txq_t txq; 5924 iflib_rxq_t rxq; 5925 iflib_fl_t fl = NULL; 5926 int i, j, cpu, err, txconf, rxconf; 5927 iflib_dma_info_t ifdip; 5928 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5929 uint32_t *txqsizes = scctx->isc_txqsizes; 5930 uint8_t nrxqs = sctx->isc_nrxqs; 5931 uint8_t ntxqs = sctx->isc_ntxqs; 5932 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5933 int fl_offset = (sctx->isc_flags & IFLIB_HAS_RXCQ ? 1 : 0); 5934 caddr_t *vaddrs; 5935 uint64_t *paddrs; 5936 5937 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5938 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5939 KASSERT(nrxqs >= fl_offset + nfree_lists, 5940 ("there must be at least a rxq for each free list")); 5941 5942 /* Allocate the TX ring struct memory */ 5943 if (!(ctx->ifc_txqs = 5944 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5945 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5946 device_printf(dev, "Unable to allocate TX ring memory\n"); 5947 err = ENOMEM; 5948 goto fail; 5949 } 5950 5951 /* Now allocate the RX */ 5952 if (!(ctx->ifc_rxqs = 5953 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5954 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5955 device_printf(dev, "Unable to allocate RX ring memory\n"); 5956 err = ENOMEM; 5957 goto rx_fail; 5958 } 5959 5960 txq = ctx->ifc_txqs; 5961 rxq = ctx->ifc_rxqs; 5962 5963 /* 5964 * XXX handle allocation failure 5965 */ 5966 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5967 /* Set up some basics */ 5968 5969 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5970 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5971 device_printf(dev, 5972 "Unable to allocate TX DMA info memory\n"); 5973 err = ENOMEM; 5974 goto err_tx_desc; 5975 } 5976 txq->ift_ifdi = ifdip; 5977 for (j = 0; j < ntxqs; j++, ifdip++) { 5978 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5979 device_printf(dev, 5980 "Unable to allocate TX descriptors\n"); 5981 err = ENOMEM; 5982 goto err_tx_desc; 5983 } 5984 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5985 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5986 } 5987 txq->ift_ctx = ctx; 5988 txq->ift_id = i; 5989 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5990 txq->ift_br_offset = 1; 5991 } else { 5992 txq->ift_br_offset = 0; 5993 } 5994 5995 if (iflib_txsd_alloc(txq)) { 5996 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5997 err = ENOMEM; 5998 goto err_tx_desc; 5999 } 6000 6001 /* Initialize the TX lock */ 6002 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 6003 device_get_nameunit(dev), txq->ift_id); 6004 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 6005 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 6006 txq->ift_timer.c_cpu = cpu; 6007 #ifdef DEV_NETMAP 6008 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0); 6009 txq->ift_netmap_timer.c_cpu = cpu; 6010 #endif /* DEV_NETMAP */ 6011 6012 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 6013 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 6014 if (err) { 6015 /* XXX free any allocated rings */ 6016 device_printf(dev, "Unable to allocate buf_ring\n"); 6017 goto err_tx_desc; 6018 } 6019 } 6020 6021 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 6022 /* Set up some basics */ 6023 callout_init(&rxq->ifr_watchdog, 1); 6024 6025 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 6026 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 6027 device_printf(dev, 6028 "Unable to allocate RX DMA info memory\n"); 6029 err = ENOMEM; 6030 goto err_tx_desc; 6031 } 6032 6033 rxq->ifr_ifdi = ifdip; 6034 /* XXX this needs to be changed if #rx queues != #tx queues */ 6035 rxq->ifr_ntxqirq = 1; 6036 rxq->ifr_txqid[0] = i; 6037 for (j = 0; j < nrxqs; j++, ifdip++) { 6038 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 6039 device_printf(dev, 6040 "Unable to allocate RX descriptors\n"); 6041 err = ENOMEM; 6042 goto err_tx_desc; 6043 } 6044 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 6045 } 6046 rxq->ifr_ctx = ctx; 6047 rxq->ifr_id = i; 6048 rxq->ifr_fl_offset = fl_offset; 6049 rxq->ifr_nfl = nfree_lists; 6050 if (!(fl = 6051 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 6052 device_printf(dev, "Unable to allocate free list memory\n"); 6053 err = ENOMEM; 6054 goto err_tx_desc; 6055 } 6056 rxq->ifr_fl = fl; 6057 for (j = 0; j < nfree_lists; j++) { 6058 fl[j].ifl_rxq = rxq; 6059 fl[j].ifl_id = j; 6060 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 6061 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 6062 } 6063 /* Allocate receive buffers for the ring */ 6064 if (iflib_rxsd_alloc(rxq)) { 6065 device_printf(dev, 6066 "Critical Failure setting up receive buffers\n"); 6067 err = ENOMEM; 6068 goto err_rx_desc; 6069 } 6070 6071 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 6072 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 6073 M_WAITOK); 6074 } 6075 6076 /* TXQs */ 6077 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 6078 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 6079 for (i = 0; i < ntxqsets; i++) { 6080 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 6081 6082 for (j = 0; j < ntxqs; j++, di++) { 6083 vaddrs[i*ntxqs + j] = di->idi_vaddr; 6084 paddrs[i*ntxqs + j] = di->idi_paddr; 6085 } 6086 } 6087 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 6088 device_printf(ctx->ifc_dev, 6089 "Unable to allocate device TX queue\n"); 6090 iflib_tx_structures_free(ctx); 6091 free(vaddrs, M_IFLIB); 6092 free(paddrs, M_IFLIB); 6093 goto err_rx_desc; 6094 } 6095 free(vaddrs, M_IFLIB); 6096 free(paddrs, M_IFLIB); 6097 6098 /* RXQs */ 6099 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 6100 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 6101 for (i = 0; i < nrxqsets; i++) { 6102 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 6103 6104 for (j = 0; j < nrxqs; j++, di++) { 6105 vaddrs[i*nrxqs + j] = di->idi_vaddr; 6106 paddrs[i*nrxqs + j] = di->idi_paddr; 6107 } 6108 } 6109 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 6110 device_printf(ctx->ifc_dev, 6111 "Unable to allocate device RX queue\n"); 6112 iflib_tx_structures_free(ctx); 6113 free(vaddrs, M_IFLIB); 6114 free(paddrs, M_IFLIB); 6115 goto err_rx_desc; 6116 } 6117 free(vaddrs, M_IFLIB); 6118 free(paddrs, M_IFLIB); 6119 6120 return (0); 6121 6122 /* XXX handle allocation failure changes */ 6123 err_rx_desc: 6124 err_tx_desc: 6125 rx_fail: 6126 if (ctx->ifc_rxqs != NULL) 6127 free(ctx->ifc_rxqs, M_IFLIB); 6128 ctx->ifc_rxqs = NULL; 6129 if (ctx->ifc_txqs != NULL) 6130 free(ctx->ifc_txqs, M_IFLIB); 6131 ctx->ifc_txqs = NULL; 6132 fail: 6133 return (err); 6134 } 6135 6136 static int 6137 iflib_tx_structures_setup(if_ctx_t ctx) 6138 { 6139 iflib_txq_t txq = ctx->ifc_txqs; 6140 int i; 6141 6142 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 6143 iflib_txq_setup(txq); 6144 6145 return (0); 6146 } 6147 6148 static void 6149 iflib_tx_structures_free(if_ctx_t ctx) 6150 { 6151 iflib_txq_t txq = ctx->ifc_txqs; 6152 if_shared_ctx_t sctx = ctx->ifc_sctx; 6153 int i, j; 6154 6155 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 6156 for (j = 0; j < sctx->isc_ntxqs; j++) 6157 iflib_dma_free(&txq->ift_ifdi[j]); 6158 iflib_txq_destroy(txq); 6159 } 6160 free(ctx->ifc_txqs, M_IFLIB); 6161 ctx->ifc_txqs = NULL; 6162 } 6163 6164 /********************************************************************* 6165 * 6166 * Initialize all receive rings. 6167 * 6168 **********************************************************************/ 6169 static int 6170 iflib_rx_structures_setup(if_ctx_t ctx) 6171 { 6172 iflib_rxq_t rxq = ctx->ifc_rxqs; 6173 int q; 6174 #if defined(INET6) || defined(INET) 6175 int err, i; 6176 #endif 6177 6178 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 6179 #if defined(INET6) || defined(INET) 6180 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 6181 TCP_LRO_ENTRIES, min(1024, 6182 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 6183 if (err != 0) { 6184 device_printf(ctx->ifc_dev, 6185 "LRO Initialization failed!\n"); 6186 goto fail; 6187 } 6188 #endif 6189 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 6190 } 6191 return (0); 6192 #if defined(INET6) || defined(INET) 6193 fail: 6194 /* 6195 * Free LRO resources allocated so far, we will only handle 6196 * the rings that completed, the failing case will have 6197 * cleaned up for itself. 'q' failed, so its the terminus. 6198 */ 6199 rxq = ctx->ifc_rxqs; 6200 for (i = 0; i < q; ++i, rxq++) { 6201 tcp_lro_free(&rxq->ifr_lc); 6202 } 6203 return (err); 6204 #endif 6205 } 6206 6207 /********************************************************************* 6208 * 6209 * Free all receive rings. 6210 * 6211 **********************************************************************/ 6212 static void 6213 iflib_rx_structures_free(if_ctx_t ctx) 6214 { 6215 iflib_rxq_t rxq = ctx->ifc_rxqs; 6216 if_shared_ctx_t sctx = ctx->ifc_sctx; 6217 int i, j; 6218 6219 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 6220 for (j = 0; j < sctx->isc_nrxqs; j++) 6221 iflib_dma_free(&rxq->ifr_ifdi[j]); 6222 iflib_rx_sds_free(rxq); 6223 #if defined(INET6) || defined(INET) 6224 tcp_lro_free(&rxq->ifr_lc); 6225 #endif 6226 } 6227 free(ctx->ifc_rxqs, M_IFLIB); 6228 ctx->ifc_rxqs = NULL; 6229 } 6230 6231 static int 6232 iflib_qset_structures_setup(if_ctx_t ctx) 6233 { 6234 int err; 6235 6236 /* 6237 * It is expected that the caller takes care of freeing queues if this 6238 * fails. 6239 */ 6240 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 6241 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 6242 return (err); 6243 } 6244 6245 if ((err = iflib_rx_structures_setup(ctx)) != 0) 6246 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 6247 6248 return (err); 6249 } 6250 6251 int 6252 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 6253 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 6254 { 6255 6256 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 6257 } 6258 6259 /* Just to avoid copy/paste */ 6260 static inline int 6261 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6262 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 6263 const char *name) 6264 { 6265 device_t dev; 6266 unsigned int base_cpuid, cpuid; 6267 int err; 6268 6269 dev = ctx->ifc_dev; 6270 base_cpuid = ctx->ifc_sysctl_core_offset; 6271 cpuid = get_cpuid_for_queue(ctx, base_cpuid, qid, type == IFLIB_INTR_TX); 6272 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, 6273 irq ? irq->ii_res : NULL, name); 6274 if (err) { 6275 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 6276 return (err); 6277 } 6278 #ifdef notyet 6279 if (cpuid > ctx->ifc_cpuid_highest) 6280 ctx->ifc_cpuid_highest = cpuid; 6281 #endif 6282 return (0); 6283 } 6284 6285 int 6286 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 6287 iflib_intr_type_t type, driver_filter_t *filter, 6288 void *filter_arg, int qid, const char *name) 6289 { 6290 device_t dev; 6291 struct grouptask *gtask; 6292 struct taskqgroup *tqg; 6293 iflib_filter_info_t info; 6294 gtask_fn_t *fn; 6295 int tqrid, err; 6296 driver_filter_t *intr_fast; 6297 void *q; 6298 6299 info = &ctx->ifc_filter_info; 6300 tqrid = rid; 6301 6302 switch (type) { 6303 /* XXX merge tx/rx for netmap? */ 6304 case IFLIB_INTR_TX: 6305 q = &ctx->ifc_txqs[qid]; 6306 info = &ctx->ifc_txqs[qid].ift_filter_info; 6307 gtask = &ctx->ifc_txqs[qid].ift_task; 6308 tqg = qgroup_if_io_tqg; 6309 fn = _task_fn_tx; 6310 intr_fast = iflib_fast_intr; 6311 GROUPTASK_INIT(gtask, 0, fn, q); 6312 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 6313 break; 6314 case IFLIB_INTR_RX: 6315 q = &ctx->ifc_rxqs[qid]; 6316 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6317 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6318 tqg = qgroup_if_io_tqg; 6319 fn = _task_fn_rx; 6320 intr_fast = iflib_fast_intr; 6321 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6322 break; 6323 case IFLIB_INTR_RXTX: 6324 q = &ctx->ifc_rxqs[qid]; 6325 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6326 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6327 tqg = qgroup_if_io_tqg; 6328 fn = _task_fn_rx; 6329 intr_fast = iflib_fast_intr_rxtx; 6330 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6331 break; 6332 case IFLIB_INTR_ADMIN: 6333 q = ctx; 6334 tqrid = -1; 6335 info = &ctx->ifc_filter_info; 6336 gtask = &ctx->ifc_admin_task; 6337 tqg = qgroup_if_config_tqg; 6338 fn = _task_fn_admin; 6339 intr_fast = iflib_fast_intr_ctx; 6340 break; 6341 default: 6342 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6343 __func__); 6344 return (EINVAL); 6345 } 6346 6347 info->ifi_filter = filter; 6348 info->ifi_filter_arg = filter_arg; 6349 info->ifi_task = gtask; 6350 info->ifi_ctx = q; 6351 6352 dev = ctx->ifc_dev; 6353 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6354 if (err != 0) { 6355 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6356 return (err); 6357 } 6358 if (type == IFLIB_INTR_ADMIN) 6359 return (0); 6360 6361 if (tqrid != -1) { 6362 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, 6363 name); 6364 if (err) 6365 return (err); 6366 } else { 6367 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6368 } 6369 6370 return (0); 6371 } 6372 6373 void 6374 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 6375 { 6376 device_t dev; 6377 struct grouptask *gtask; 6378 struct taskqgroup *tqg; 6379 gtask_fn_t *fn; 6380 void *q; 6381 int err; 6382 6383 switch (type) { 6384 case IFLIB_INTR_TX: 6385 q = &ctx->ifc_txqs[qid]; 6386 gtask = &ctx->ifc_txqs[qid].ift_task; 6387 tqg = qgroup_if_io_tqg; 6388 fn = _task_fn_tx; 6389 GROUPTASK_INIT(gtask, 0, fn, q); 6390 break; 6391 case IFLIB_INTR_RX: 6392 q = &ctx->ifc_rxqs[qid]; 6393 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6394 tqg = qgroup_if_io_tqg; 6395 fn = _task_fn_rx; 6396 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6397 break; 6398 case IFLIB_INTR_IOV: 6399 q = ctx; 6400 gtask = &ctx->ifc_vflr_task; 6401 tqg = qgroup_if_config_tqg; 6402 fn = _task_fn_iov; 6403 GROUPTASK_INIT(gtask, 0, fn, q); 6404 break; 6405 default: 6406 panic("unknown net intr type"); 6407 } 6408 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, name); 6409 if (err) { 6410 dev = ctx->ifc_dev; 6411 taskqgroup_attach(tqg, gtask, q, dev, irq ? irq->ii_res : NULL, 6412 name); 6413 } 6414 } 6415 6416 void 6417 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6418 { 6419 6420 if (irq->ii_tag) 6421 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6422 6423 if (irq->ii_res) 6424 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6425 rman_get_rid(irq->ii_res), irq->ii_res); 6426 } 6427 6428 static int 6429 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6430 { 6431 iflib_txq_t txq = ctx->ifc_txqs; 6432 iflib_rxq_t rxq = ctx->ifc_rxqs; 6433 if_irq_t irq = &ctx->ifc_legacy_irq; 6434 iflib_filter_info_t info; 6435 device_t dev; 6436 struct grouptask *gtask; 6437 struct resource *res; 6438 struct taskqgroup *tqg; 6439 void *q; 6440 int err, tqrid; 6441 bool rx_only; 6442 6443 q = &ctx->ifc_rxqs[0]; 6444 info = &rxq[0].ifr_filter_info; 6445 gtask = &rxq[0].ifr_task; 6446 tqg = qgroup_if_io_tqg; 6447 tqrid = *rid; 6448 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6449 6450 ctx->ifc_flags |= IFC_LEGACY; 6451 info->ifi_filter = filter; 6452 info->ifi_filter_arg = filter_arg; 6453 info->ifi_task = gtask; 6454 info->ifi_ctx = rx_only ? ctx : q; 6455 6456 dev = ctx->ifc_dev; 6457 /* We allocate a single interrupt resource */ 6458 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx : 6459 iflib_fast_intr_rxtx, NULL, info, name); 6460 if (err != 0) 6461 return (err); 6462 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q); 6463 res = irq->ii_res; 6464 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6465 6466 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6467 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6468 "tx"); 6469 return (0); 6470 } 6471 6472 void 6473 iflib_led_create(if_ctx_t ctx) 6474 { 6475 6476 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6477 device_get_nameunit(ctx->ifc_dev)); 6478 } 6479 6480 void 6481 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6482 { 6483 6484 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6485 } 6486 6487 void 6488 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6489 { 6490 6491 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6492 } 6493 6494 void 6495 iflib_admin_intr_deferred(if_ctx_t ctx) 6496 { 6497 6498 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL); 6499 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6500 } 6501 6502 void 6503 iflib_iov_intr_deferred(if_ctx_t ctx) 6504 { 6505 6506 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6507 } 6508 6509 void 6510 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6511 { 6512 6513 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6514 name); 6515 } 6516 6517 void 6518 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6519 const char *name) 6520 { 6521 6522 GROUPTASK_INIT(gtask, 0, fn, ctx); 6523 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6524 name); 6525 } 6526 6527 void 6528 iflib_config_gtask_deinit(struct grouptask *gtask) 6529 { 6530 6531 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6532 } 6533 6534 void 6535 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6536 { 6537 if_t ifp = ctx->ifc_ifp; 6538 iflib_txq_t txq = ctx->ifc_txqs; 6539 6540 if_setbaudrate(ifp, baudrate); 6541 if (baudrate >= IF_Gbps(10)) { 6542 STATE_LOCK(ctx); 6543 ctx->ifc_flags |= IFC_PREFETCH; 6544 STATE_UNLOCK(ctx); 6545 } 6546 /* If link down, disable watchdog */ 6547 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6548 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6549 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6550 } 6551 ctx->ifc_link_state = link_state; 6552 if_link_state_change(ifp, link_state); 6553 } 6554 6555 static int 6556 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6557 { 6558 int credits; 6559 #ifdef INVARIANTS 6560 int credits_pre = txq->ift_cidx_processed; 6561 #endif 6562 6563 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6564 BUS_DMASYNC_POSTREAD); 6565 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6566 return (0); 6567 6568 txq->ift_processed += credits; 6569 txq->ift_cidx_processed += credits; 6570 6571 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6572 if (txq->ift_cidx_processed >= txq->ift_size) 6573 txq->ift_cidx_processed -= txq->ift_size; 6574 return (credits); 6575 } 6576 6577 static int 6578 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6579 { 6580 iflib_fl_t fl; 6581 u_int i; 6582 6583 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6584 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6585 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6586 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6587 budget)); 6588 } 6589 6590 void 6591 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6592 const char *description, if_int_delay_info_t info, 6593 int offset, int value) 6594 { 6595 info->iidi_ctx = ctx; 6596 info->iidi_offset = offset; 6597 info->iidi_value = value; 6598 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6599 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6600 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 6601 info, 0, iflib_sysctl_int_delay, "I", description); 6602 } 6603 6604 struct sx * 6605 iflib_ctx_lock_get(if_ctx_t ctx) 6606 { 6607 6608 return (&ctx->ifc_ctx_sx); 6609 } 6610 6611 static int 6612 iflib_msix_init(if_ctx_t ctx) 6613 { 6614 device_t dev = ctx->ifc_dev; 6615 if_shared_ctx_t sctx = ctx->ifc_sctx; 6616 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6617 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6618 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6619 6620 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6621 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6622 6623 if (bootverbose) 6624 device_printf(dev, "msix_init qsets capped at %d\n", 6625 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6626 6627 /* Override by tuneable */ 6628 if (scctx->isc_disable_msix) 6629 goto msi; 6630 6631 /* First try MSI-X */ 6632 if ((msgs = pci_msix_count(dev)) == 0) { 6633 if (bootverbose) 6634 device_printf(dev, "MSI-X not supported or disabled\n"); 6635 goto msi; 6636 } 6637 6638 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6639 /* 6640 * bar == -1 => "trust me I know what I'm doing" 6641 * Some drivers are for hardware that is so shoddily 6642 * documented that no one knows which bars are which 6643 * so the developer has to map all bars. This hack 6644 * allows shoddy garbage to use MSI-X in this framework. 6645 */ 6646 if (bar != -1) { 6647 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6648 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6649 if (ctx->ifc_msix_mem == NULL) { 6650 device_printf(dev, "Unable to map MSI-X table\n"); 6651 goto msi; 6652 } 6653 } 6654 6655 admincnt = sctx->isc_admin_intrcnt; 6656 #if IFLIB_DEBUG 6657 /* use only 1 qset in debug mode */ 6658 queuemsgs = min(msgs - admincnt, 1); 6659 #else 6660 queuemsgs = msgs - admincnt; 6661 #endif 6662 #ifdef RSS 6663 queues = imin(queuemsgs, rss_getnumbuckets()); 6664 #else 6665 queues = queuemsgs; 6666 #endif 6667 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6668 if (bootverbose) 6669 device_printf(dev, 6670 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6671 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6672 #ifdef RSS 6673 /* If we're doing RSS, clamp at the number of RSS buckets */ 6674 if (queues > rss_getnumbuckets()) 6675 queues = rss_getnumbuckets(); 6676 #endif 6677 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6678 rx_queues = iflib_num_rx_queues; 6679 else 6680 rx_queues = queues; 6681 6682 if (rx_queues > scctx->isc_nrxqsets) 6683 rx_queues = scctx->isc_nrxqsets; 6684 6685 /* 6686 * We want this to be all logical CPUs by default 6687 */ 6688 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6689 tx_queues = iflib_num_tx_queues; 6690 else 6691 tx_queues = mp_ncpus; 6692 6693 if (tx_queues > scctx->isc_ntxqsets) 6694 tx_queues = scctx->isc_ntxqsets; 6695 6696 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6697 #ifdef INVARIANTS 6698 if (tx_queues != rx_queues) 6699 device_printf(dev, 6700 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6701 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6702 #endif 6703 tx_queues = min(rx_queues, tx_queues); 6704 rx_queues = min(rx_queues, tx_queues); 6705 } 6706 6707 vectors = rx_queues + admincnt; 6708 if (msgs < vectors) { 6709 device_printf(dev, 6710 "insufficient number of MSI-X vectors " 6711 "(supported %d, need %d)\n", msgs, vectors); 6712 goto msi; 6713 } 6714 6715 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6716 tx_queues); 6717 msgs = vectors; 6718 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6719 if (vectors != msgs) { 6720 device_printf(dev, 6721 "Unable to allocate sufficient MSI-X vectors " 6722 "(got %d, need %d)\n", vectors, msgs); 6723 pci_release_msi(dev); 6724 if (bar != -1) { 6725 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6726 ctx->ifc_msix_mem); 6727 ctx->ifc_msix_mem = NULL; 6728 } 6729 goto msi; 6730 } 6731 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6732 vectors); 6733 scctx->isc_vectors = vectors; 6734 scctx->isc_nrxqsets = rx_queues; 6735 scctx->isc_ntxqsets = tx_queues; 6736 scctx->isc_intr = IFLIB_INTR_MSIX; 6737 6738 return (vectors); 6739 } else { 6740 device_printf(dev, 6741 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6742 err); 6743 if (bar != -1) { 6744 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6745 ctx->ifc_msix_mem); 6746 ctx->ifc_msix_mem = NULL; 6747 } 6748 } 6749 6750 msi: 6751 vectors = pci_msi_count(dev); 6752 scctx->isc_nrxqsets = 1; 6753 scctx->isc_ntxqsets = 1; 6754 scctx->isc_vectors = vectors; 6755 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6756 device_printf(dev,"Using an MSI interrupt\n"); 6757 scctx->isc_intr = IFLIB_INTR_MSI; 6758 } else { 6759 scctx->isc_vectors = 1; 6760 device_printf(dev,"Using a Legacy interrupt\n"); 6761 scctx->isc_intr = IFLIB_INTR_LEGACY; 6762 } 6763 6764 return (vectors); 6765 } 6766 6767 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6768 6769 static int 6770 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6771 { 6772 int rc; 6773 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6774 struct sbuf *sb; 6775 const char *ring_state = "UNKNOWN"; 6776 6777 /* XXX needed ? */ 6778 rc = sysctl_wire_old_buffer(req, 0); 6779 MPASS(rc == 0); 6780 if (rc != 0) 6781 return (rc); 6782 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6783 MPASS(sb != NULL); 6784 if (sb == NULL) 6785 return (ENOMEM); 6786 if (state[3] <= 3) 6787 ring_state = ring_states[state[3]]; 6788 6789 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6790 state[0], state[1], state[2], ring_state); 6791 rc = sbuf_finish(sb); 6792 sbuf_delete(sb); 6793 return(rc); 6794 } 6795 6796 enum iflib_ndesc_handler { 6797 IFLIB_NTXD_HANDLER, 6798 IFLIB_NRXD_HANDLER, 6799 }; 6800 6801 static int 6802 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6803 { 6804 if_ctx_t ctx = (void *)arg1; 6805 enum iflib_ndesc_handler type = arg2; 6806 char buf[256] = {0}; 6807 qidx_t *ndesc; 6808 char *p, *next; 6809 int nqs, rc, i; 6810 6811 nqs = 8; 6812 switch(type) { 6813 case IFLIB_NTXD_HANDLER: 6814 ndesc = ctx->ifc_sysctl_ntxds; 6815 if (ctx->ifc_sctx) 6816 nqs = ctx->ifc_sctx->isc_ntxqs; 6817 break; 6818 case IFLIB_NRXD_HANDLER: 6819 ndesc = ctx->ifc_sysctl_nrxds; 6820 if (ctx->ifc_sctx) 6821 nqs = ctx->ifc_sctx->isc_nrxqs; 6822 break; 6823 default: 6824 printf("%s: unhandled type\n", __func__); 6825 return (EINVAL); 6826 } 6827 if (nqs == 0) 6828 nqs = 8; 6829 6830 for (i=0; i<8; i++) { 6831 if (i >= nqs) 6832 break; 6833 if (i) 6834 strcat(buf, ","); 6835 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6836 } 6837 6838 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6839 if (rc || req->newptr == NULL) 6840 return rc; 6841 6842 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6843 i++, p = strsep(&next, " ,")) { 6844 ndesc[i] = strtoul(p, NULL, 10); 6845 } 6846 6847 return(rc); 6848 } 6849 6850 #define NAME_BUFLEN 32 6851 static void 6852 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6853 { 6854 device_t dev = iflib_get_dev(ctx); 6855 struct sysctl_oid_list *child, *oid_list; 6856 struct sysctl_ctx_list *ctx_list; 6857 struct sysctl_oid *node; 6858 6859 ctx_list = device_get_sysctl_ctx(dev); 6860 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6861 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6862 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields"); 6863 oid_list = SYSCTL_CHILDREN(node); 6864 6865 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6866 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6867 "driver version"); 6868 6869 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6870 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6871 "# of txqs to use, 0 => use default #"); 6872 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6873 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6874 "# of rxqs to use, 0 => use default #"); 6875 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6876 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6877 "permit #txq != #rxq"); 6878 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6879 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6880 "disable MSI-X (default 0)"); 6881 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6882 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6883 "set the RX budget"); 6884 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6885 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6886 "cause TX to abdicate instead of running to completion"); 6887 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6888 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6889 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6890 "offset to start using cores at"); 6891 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6892 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6893 "use separate cores for TX and RX"); 6894 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "use_logical_cores", 6895 CTLFLAG_RDTUN, &ctx->ifc_sysctl_use_logical_cores, 0, 6896 "try to make use of logical cores for TX and RX"); 6897 6898 /* XXX change for per-queue sizes */ 6899 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6900 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6901 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 6902 "list of # of TX descriptors to use, 0 = use default #"); 6903 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6904 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6905 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 6906 "list of # of RX descriptors to use, 0 = use default #"); 6907 } 6908 6909 static void 6910 iflib_add_device_sysctl_post(if_ctx_t ctx) 6911 { 6912 if_shared_ctx_t sctx = ctx->ifc_sctx; 6913 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6914 device_t dev = iflib_get_dev(ctx); 6915 struct sysctl_oid_list *child; 6916 struct sysctl_ctx_list *ctx_list; 6917 iflib_fl_t fl; 6918 iflib_txq_t txq; 6919 iflib_rxq_t rxq; 6920 int i, j; 6921 char namebuf[NAME_BUFLEN]; 6922 char *qfmt; 6923 struct sysctl_oid *queue_node, *fl_node, *node; 6924 struct sysctl_oid_list *queue_list, *fl_list; 6925 ctx_list = device_get_sysctl_ctx(dev); 6926 6927 node = ctx->ifc_sysctl_node; 6928 child = SYSCTL_CHILDREN(node); 6929 6930 if (scctx->isc_ntxqsets > 100) 6931 qfmt = "txq%03d"; 6932 else if (scctx->isc_ntxqsets > 10) 6933 qfmt = "txq%02d"; 6934 else 6935 qfmt = "txq%d"; 6936 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6937 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6938 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6939 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6940 queue_list = SYSCTL_CHILDREN(queue_node); 6941 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 6942 CTLFLAG_RD, 6943 &txq->ift_task.gt_cpu, 0, "cpu this queue is bound to"); 6944 #if MEMORY_LOGGING 6945 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6946 CTLFLAG_RD, 6947 &txq->ift_dequeued, "total mbufs freed"); 6948 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6949 CTLFLAG_RD, 6950 &txq->ift_enqueued, "total mbufs enqueued"); 6951 #endif 6952 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6953 CTLFLAG_RD, 6954 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6955 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6956 CTLFLAG_RD, 6957 &txq->ift_pullups, "# of times m_pullup was called"); 6958 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6959 CTLFLAG_RD, 6960 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6961 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6962 CTLFLAG_RD, 6963 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6964 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6965 CTLFLAG_RD, 6966 &txq->ift_map_failed, "# of times DMA map failed"); 6967 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6968 CTLFLAG_RD, 6969 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6970 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6971 CTLFLAG_RD, 6972 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6973 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6974 CTLFLAG_RD, 6975 &txq->ift_pidx, 1, "Producer Index"); 6976 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6977 CTLFLAG_RD, 6978 &txq->ift_cidx, 1, "Consumer Index"); 6979 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6980 CTLFLAG_RD, 6981 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6982 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6983 CTLFLAG_RD, 6984 &txq->ift_in_use, 1, "descriptors in use"); 6985 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6986 CTLFLAG_RD, 6987 &txq->ift_processed, "descriptors procesed for clean"); 6988 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6989 CTLFLAG_RD, 6990 &txq->ift_cleaned, "total cleaned"); 6991 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6992 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 6993 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 6994 mp_ring_state_handler, "A", "soft ring state"); 6995 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6996 CTLFLAG_RD, &txq->ift_br->enqueues, 6997 "# of enqueues to the mp_ring for this queue"); 6998 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6999 CTLFLAG_RD, &txq->ift_br->drops, 7000 "# of drops in the mp_ring for this queue"); 7001 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 7002 CTLFLAG_RD, &txq->ift_br->starts, 7003 "# of normal consumer starts in the mp_ring for this queue"); 7004 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 7005 CTLFLAG_RD, &txq->ift_br->stalls, 7006 "# of consumer stalls in the mp_ring for this queue"); 7007 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 7008 CTLFLAG_RD, &txq->ift_br->restarts, 7009 "# of consumer restarts in the mp_ring for this queue"); 7010 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 7011 CTLFLAG_RD, &txq->ift_br->abdications, 7012 "# of consumer abdications in the mp_ring for this queue"); 7013 } 7014 7015 if (scctx->isc_nrxqsets > 100) 7016 qfmt = "rxq%03d"; 7017 else if (scctx->isc_nrxqsets > 10) 7018 qfmt = "rxq%02d"; 7019 else 7020 qfmt = "rxq%d"; 7021 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 7022 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 7023 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 7024 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 7025 queue_list = SYSCTL_CHILDREN(queue_node); 7026 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 7027 CTLFLAG_RD, 7028 &rxq->ifr_task.gt_cpu, 0, "cpu this queue is bound to"); 7029 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 7030 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 7031 CTLFLAG_RD, 7032 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 7033 } 7034 7035 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 7036 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 7037 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 7038 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name"); 7039 fl_list = SYSCTL_CHILDREN(fl_node); 7040 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 7041 CTLFLAG_RD, 7042 &fl->ifl_pidx, 1, "Producer Index"); 7043 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 7044 CTLFLAG_RD, 7045 &fl->ifl_cidx, 1, "Consumer Index"); 7046 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 7047 CTLFLAG_RD, 7048 &fl->ifl_credits, 1, "credits available"); 7049 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 7050 CTLFLAG_RD, 7051 &fl->ifl_buf_size, 1, "buffer size"); 7052 #if MEMORY_LOGGING 7053 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 7054 CTLFLAG_RD, 7055 &fl->ifl_m_enqueued, "mbufs allocated"); 7056 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 7057 CTLFLAG_RD, 7058 &fl->ifl_m_dequeued, "mbufs freed"); 7059 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 7060 CTLFLAG_RD, 7061 &fl->ifl_cl_enqueued, "clusters allocated"); 7062 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 7063 CTLFLAG_RD, 7064 &fl->ifl_cl_dequeued, "clusters freed"); 7065 #endif 7066 } 7067 } 7068 7069 } 7070 7071 void 7072 iflib_request_reset(if_ctx_t ctx) 7073 { 7074 7075 STATE_LOCK(ctx); 7076 ctx->ifc_flags |= IFC_DO_RESET; 7077 STATE_UNLOCK(ctx); 7078 } 7079 7080 #ifndef __NO_STRICT_ALIGNMENT 7081 static struct mbuf * 7082 iflib_fixup_rx(struct mbuf *m) 7083 { 7084 struct mbuf *n; 7085 7086 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 7087 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 7088 m->m_data += ETHER_HDR_LEN; 7089 n = m; 7090 } else { 7091 MGETHDR(n, M_NOWAIT, MT_DATA); 7092 if (n == NULL) { 7093 m_freem(m); 7094 return (NULL); 7095 } 7096 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 7097 m->m_data += ETHER_HDR_LEN; 7098 m->m_len -= ETHER_HDR_LEN; 7099 n->m_len = ETHER_HDR_LEN; 7100 M_MOVE_PKTHDR(n, m); 7101 n->m_next = m; 7102 } 7103 return (n); 7104 } 7105 #endif 7106 7107 #ifdef DEBUGNET 7108 static void 7109 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 7110 { 7111 if_ctx_t ctx; 7112 7113 ctx = if_getsoftc(ifp); 7114 CTX_LOCK(ctx); 7115 *nrxr = NRXQSETS(ctx); 7116 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 7117 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 7118 CTX_UNLOCK(ctx); 7119 } 7120 7121 static void 7122 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 7123 { 7124 if_ctx_t ctx; 7125 if_softc_ctx_t scctx; 7126 iflib_fl_t fl; 7127 iflib_rxq_t rxq; 7128 int i, j; 7129 7130 ctx = if_getsoftc(ifp); 7131 scctx = &ctx->ifc_softc_ctx; 7132 7133 switch (event) { 7134 case DEBUGNET_START: 7135 for (i = 0; i < scctx->isc_nrxqsets; i++) { 7136 rxq = &ctx->ifc_rxqs[i]; 7137 for (j = 0; j < rxq->ifr_nfl; j++) { 7138 fl = rxq->ifr_fl; 7139 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 7140 } 7141 } 7142 iflib_no_tx_batch = 1; 7143 break; 7144 default: 7145 break; 7146 } 7147 } 7148 7149 static int 7150 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 7151 { 7152 if_ctx_t ctx; 7153 iflib_txq_t txq; 7154 int error; 7155 7156 ctx = if_getsoftc(ifp); 7157 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7158 IFF_DRV_RUNNING) 7159 return (EBUSY); 7160 7161 txq = &ctx->ifc_txqs[0]; 7162 error = iflib_encap(txq, &m); 7163 if (error == 0) 7164 (void)iflib_txd_db_check(txq, true); 7165 return (error); 7166 } 7167 7168 static int 7169 iflib_debugnet_poll(if_t ifp, int count) 7170 { 7171 struct epoch_tracker et; 7172 if_ctx_t ctx; 7173 if_softc_ctx_t scctx; 7174 iflib_txq_t txq; 7175 int i; 7176 7177 ctx = if_getsoftc(ifp); 7178 scctx = &ctx->ifc_softc_ctx; 7179 7180 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7181 IFF_DRV_RUNNING) 7182 return (EBUSY); 7183 7184 txq = &ctx->ifc_txqs[0]; 7185 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 7186 7187 NET_EPOCH_ENTER(et); 7188 for (i = 0; i < scctx->isc_nrxqsets; i++) 7189 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 7190 NET_EPOCH_EXIT(et); 7191 return (0); 7192 } 7193 #endif /* DEBUGNET */ 7194