1 /* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $Id: mp_machdep.c,v 1.56 1997/10/06 02:11:32 dyson Exp $ 26 */ 27 28 #include "opt_smp.h" 29 #include "opt_vm86.h" 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/proc.h> 35 #include <sys/sysctl.h> 36 37 #include <vm/vm.h> 38 #include <vm/vm_param.h> 39 #include <vm/pmap.h> 40 #include <vm/vm_kern.h> 41 #include <vm/vm_extern.h> 42 43 #include <machine/smp.h> 44 #include <machine/apic.h> 45 #include <machine/mpapic.h> 46 #include <machine/segments.h> 47 #include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */ 48 #include <machine/tss.h> 49 #include <machine/specialreg.h> 50 #include <machine/cpu.h> 51 #include <machine/cputypes.h> 52 53 #include <i386/i386/cons.h> /* cngetc() */ 54 55 #if defined(APIC_IO) 56 #include <machine/md_var.h> /* setidt() */ 57 #include <i386/isa/icu.h> /* IPIs */ 58 #include <i386/isa/intr_machdep.h> /* IPIs */ 59 #endif /* APIC_IO */ 60 61 #if defined(TEST_DEFAULT_CONFIG) 62 #define MPFPS_MPFB1 TEST_DEFAULT_CONFIG 63 #else 64 #define MPFPS_MPFB1 mpfps->mpfb1 65 #endif /* TEST_DEFAULT_CONFIG */ 66 67 #define WARMBOOT_TARGET 0 68 #define WARMBOOT_OFF (KERNBASE + 0x0467) 69 #define WARMBOOT_SEG (KERNBASE + 0x0469) 70 71 #define BIOS_BASE (0xf0000) 72 #define BIOS_SIZE (0x10000) 73 #define BIOS_COUNT (BIOS_SIZE/4) 74 75 #define CMOS_REG (0x70) 76 #define CMOS_DATA (0x71) 77 #define BIOS_RESET (0x0f) 78 #define BIOS_WARM (0x0a) 79 80 #define PROCENTRY_FLAG_EN 0x01 81 #define PROCENTRY_FLAG_BP 0x02 82 #define IOAPICENTRY_FLAG_EN 0x01 83 84 85 /* MP Floating Pointer Structure */ 86 typedef struct MPFPS { 87 char signature[4]; 88 void *pap; 89 u_char length; 90 u_char spec_rev; 91 u_char checksum; 92 u_char mpfb1; 93 u_char mpfb2; 94 u_char mpfb3; 95 u_char mpfb4; 96 u_char mpfb5; 97 } *mpfps_t; 98 99 /* MP Configuration Table Header */ 100 typedef struct MPCTH { 101 char signature[4]; 102 u_short base_table_length; 103 u_char spec_rev; 104 u_char checksum; 105 u_char oem_id[8]; 106 u_char product_id[12]; 107 void *oem_table_pointer; 108 u_short oem_table_size; 109 u_short entry_count; 110 void *apic_address; 111 u_short extended_table_length; 112 u_char extended_table_checksum; 113 u_char reserved; 114 } *mpcth_t; 115 116 117 typedef struct PROCENTRY { 118 u_char type; 119 u_char apic_id; 120 u_char apic_version; 121 u_char cpu_flags; 122 u_long cpu_signature; 123 u_long feature_flags; 124 u_long reserved1; 125 u_long reserved2; 126 } *proc_entry_ptr; 127 128 typedef struct BUSENTRY { 129 u_char type; 130 u_char bus_id; 131 char bus_type[6]; 132 } *bus_entry_ptr; 133 134 typedef struct IOAPICENTRY { 135 u_char type; 136 u_char apic_id; 137 u_char apic_version; 138 u_char apic_flags; 139 void *apic_address; 140 } *io_apic_entry_ptr; 141 142 typedef struct INTENTRY { 143 u_char type; 144 u_char int_type; 145 u_short int_flags; 146 u_char src_bus_id; 147 u_char src_bus_irq; 148 u_char dst_apic_id; 149 u_char dst_apic_int; 150 } *int_entry_ptr; 151 152 /* descriptions of MP basetable entries */ 153 typedef struct BASETABLE_ENTRY { 154 u_char type; 155 u_char length; 156 char name[16]; 157 } basetable_entry; 158 159 /* 160 * this code MUST be enabled here and in mpboot.s. 161 * it follows the very early stages of AP boot by placing values in CMOS ram. 162 * it NORMALLY will never be needed and thus the primitive method for enabling. 163 * 164 #define CHECK_POINTS 165 */ 166 167 #if defined(CHECK_POINTS) 168 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 169 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 170 171 #define CHECK_INIT(D); \ 172 CHECK_WRITE(0x34, (D)); \ 173 CHECK_WRITE(0x35, (D)); \ 174 CHECK_WRITE(0x36, (D)); \ 175 CHECK_WRITE(0x37, (D)); \ 176 CHECK_WRITE(0x38, (D)); \ 177 CHECK_WRITE(0x39, (D)); 178 179 #define CHECK_PRINT(S); \ 180 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 181 (S), \ 182 CHECK_READ(0x34), \ 183 CHECK_READ(0x35), \ 184 CHECK_READ(0x36), \ 185 CHECK_READ(0x37), \ 186 CHECK_READ(0x38), \ 187 CHECK_READ(0x39)); 188 189 #else /* CHECK_POINTS */ 190 191 #define CHECK_INIT(D) 192 #define CHECK_PRINT(S) 193 194 #endif /* CHECK_POINTS */ 195 196 /* 197 * Values to send to the POST hardware. 198 */ 199 #define MP_BOOTADDRESS_POST 0x10 200 #define MP_PROBE_POST 0x11 201 #define MPTABLE_PASS1_POST 0x12 202 203 #define MP_START_POST 0x13 204 #define MP_ENABLE_POST 0x14 205 #define MPTABLE_PASS2_POST 0x15 206 207 #define START_ALL_APS_POST 0x16 208 #define INSTALL_AP_TRAMP_POST 0x17 209 #define START_AP_POST 0x18 210 211 #define MP_ANNOUNCE_POST 0x19 212 213 214 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ 215 int current_postcode; 216 217 /** XXX FIXME: what system files declare these??? */ 218 extern struct region_descriptor r_gdt, r_idt; 219 220 int bsp_apic_ready = 0; /* flags useability of BSP apic */ 221 int mp_ncpus; /* # of CPUs, including BSP */ 222 int mp_naps; /* # of Applications processors */ 223 int mp_nbusses; /* # of busses */ 224 int mp_napics; /* # of IO APICs */ 225 int boot_cpu_id; /* designated BSP */ 226 vm_offset_t cpu_apic_address; 227 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ 228 extern int nkpt; 229 230 u_int32_t cpu_apic_versions[NCPU]; 231 u_int32_t io_apic_versions[NAPIC]; 232 233 /* 234 * APIC ID logical/physical mapping structures. 235 * We oversize these to simplify boot-time config. 236 */ 237 int cpu_num_to_apic_id[NAPICID]; 238 int io_num_to_apic_id[NAPICID]; 239 int apic_id_to_logical[NAPICID]; 240 241 242 #define NPPROVMTRR 8 243 #define PPRO_VMTRRphysBase0 0x200 244 #define PPRO_VMTRRphysMask0 0x201 245 static struct { 246 u_int64_t base, 247 mask; 248 } PPro_vmtrr[NPPROVMTRR]; 249 250 /* Bitmap of all available CPUs */ 251 u_int all_cpus; 252 253 /* AP uses this PTD during bootstrap */ 254 pd_entry_t *bootPTD; 255 256 /* Hotwire a 0->4MB V==P mapping */ 257 extern pt_entry_t *KPTphys; 258 259 /* Virtual address of per-cpu common_tss */ 260 extern struct i386tss common_tss; 261 #ifdef VM86 262 extern struct segment_descriptor common_tssd; 263 extern u_int private_tss; /* flag indicating private tss */ 264 extern u_int my_tr; 265 #endif /* VM86 */ 266 267 /* IdlePTD per cpu */ 268 pd_entry_t *IdlePTDS[NCPU]; 269 270 /* "my" private page table page, for BSP init */ 271 extern pt_entry_t SMP_prvpt[]; 272 273 /* Private page pointer to curcpu's PTD, used during BSP init */ 274 extern pd_entry_t *my_idlePTD; 275 276 static int smp_started; /* has the system started? */ 277 278 /* 279 * Local data and functions. 280 */ 281 282 static int mp_capable; 283 static u_int boot_address; 284 static u_int base_memory; 285 286 static int picmode; /* 0: virtual wire mode, 1: PIC mode */ 287 static mpfps_t mpfps; 288 static int search_for_sig(u_int32_t target, int count); 289 static void mp_enable(u_int boot_addr); 290 291 static int mptable_pass1(void); 292 static int mptable_pass2(void); 293 static void default_mp_table(int type); 294 static void fix_mp_table(void); 295 static void init_locks(void); 296 static int start_all_aps(u_int boot_addr); 297 static void install_ap_tramp(u_int boot_addr); 298 static int start_ap(int logicalCpu, u_int boot_addr); 299 static void getmtrr(void) ; 300 static void putmtrr(void) ; 301 static void putfmtrr(void) ; 302 303 304 /* 305 * Calculate usable address in base memory for AP trampoline code. 306 */ 307 u_int 308 mp_bootaddress(u_int basemem) 309 { 310 POSTCODE(MP_BOOTADDRESS_POST); 311 312 base_memory = basemem * 1024; /* convert to bytes */ 313 314 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ 315 if ((base_memory - boot_address) < bootMP_size) 316 boot_address -= 4096; /* not enough, lower by 4k */ 317 318 return boot_address; 319 } 320 321 322 /* 323 * Look for an Intel MP spec table (ie, SMP capable hardware). 324 */ 325 int 326 mp_probe(void) 327 { 328 int x; 329 u_long segment; 330 u_int32_t target; 331 332 POSTCODE(MP_PROBE_POST); 333 334 /* see if EBDA exists */ 335 if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) { 336 /* search first 1K of EBDA */ 337 target = (u_int32_t) (segment << 4); 338 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 339 goto found; 340 } else { 341 /* last 1K of base memory, effective 'top of base' passed in */ 342 target = (u_int32_t) (base_memory - 0x400); 343 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 344 goto found; 345 } 346 347 /* search the BIOS */ 348 target = (u_int32_t) BIOS_BASE; 349 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 350 goto found; 351 352 /* nothing found */ 353 mpfps = (mpfps_t)0; 354 mp_capable = 0; 355 return 0; 356 357 found: 358 /* calculate needed resources */ 359 mpfps = (mpfps_t)x; 360 if (mptable_pass1()) 361 panic("you must reconfigure your kernel"); 362 363 /* flag fact that we are running multiple processors */ 364 mp_capable = 1; 365 return 1; 366 } 367 368 369 /* 370 * Startup the SMP processors. 371 */ 372 void 373 mp_start(void) 374 { 375 POSTCODE(MP_START_POST); 376 377 /* look for MP capable motherboard */ 378 if (mp_capable) 379 mp_enable(boot_address); 380 else 381 panic("MP hardware not found!"); 382 } 383 384 385 /* 386 * Print various information about the SMP system hardware and setup. 387 */ 388 void 389 mp_announce(void) 390 { 391 int x; 392 393 POSTCODE(MP_ANNOUNCE_POST); 394 395 printf("FreeBSD/SMP: Multiprocessor motherboard\n"); 396 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0)); 397 printf(", version: 0x%08x", cpu_apic_versions[0]); 398 printf(", at 0x%08x\n", cpu_apic_address); 399 for (x = 1; x <= mp_naps; ++x) { 400 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x)); 401 printf(", version: 0x%08x", cpu_apic_versions[x]); 402 printf(", at 0x%08x\n", cpu_apic_address); 403 } 404 405 #if defined(APIC_IO) 406 for (x = 0; x < mp_napics; ++x) { 407 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x)); 408 printf(", version: 0x%08x", io_apic_versions[x]); 409 printf(", at 0x%08x\n", io_apic_address[x]); 410 } 411 #else 412 printf(" Warning: APIC I/O disabled\n"); 413 #endif /* APIC_IO */ 414 } 415 416 /* 417 * AP cpu's call this to sync up protected mode. 418 */ 419 void 420 init_secondary(void) 421 { 422 int gsel_tss; 423 #ifndef VM86 424 u_int my_tr; 425 #endif 426 427 r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1; 428 r_gdt.rd_base = (int) gdt; 429 lgdt(&r_gdt); /* does magic intra-segment return */ 430 lidt(&r_idt); 431 lldt(_default_ldt); 432 433 my_tr = NGDT + cpuid; 434 gsel_tss = GSEL(my_tr, SEL_KPL); 435 gdt[my_tr].sd.sd_type = SDT_SYS386TSS; 436 common_tss.tss_esp0 = 0; /* not used until after switch */ 437 common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 438 common_tss.tss_ioopt = (sizeof common_tss) << 16; 439 #ifdef VM86 440 common_tssd = gdt[my_tr].sd; 441 private_tss = 0; 442 #endif /* VM86 */ 443 ltr(gsel_tss); 444 445 load_cr0(0x8005003b); /* XXX! */ 446 447 PTD[0] = 0; 448 pmap_set_opt((unsigned *)PTD); 449 450 putmtrr(); 451 putfmtrr(); 452 453 invltlb(); 454 } 455 456 457 #if defined(APIC_IO) 458 /* 459 * Final configuration of the BSP's local APIC: 460 * - disable 'pic mode'. 461 * - disable 'virtual wire mode'. 462 * - enable NMI. 463 */ 464 void 465 bsp_apic_configure(void) 466 { 467 u_char byte; 468 u_int32_t temp; 469 470 /* leave 'pic mode' if necessary */ 471 if (picmode) { 472 outb(0x22, 0x70); /* select IMCR */ 473 byte = inb(0x23); /* current contents */ 474 byte |= 0x01; /* mask external INTR */ 475 outb(0x23, byte); /* disconnect 8259s/NMI */ 476 } 477 478 /* mask lint0 (the 8259 'virtual wire' connection) */ 479 temp = lapic.lvt_lint0; 480 temp |= APIC_LVT_M; /* set the mask */ 481 lapic.lvt_lint0 = temp; 482 483 /* setup lint1 to handle NMI */ 484 temp = lapic.lvt_lint1; 485 temp &= ~APIC_LVT_M; /* clear the mask */ 486 lapic.lvt_lint1 = temp; 487 488 if (bootverbose) 489 apic_dump("bsp_apic_configure()"); 490 } 491 #endif /* APIC_IO */ 492 493 494 /******************************************************************* 495 * local functions and data 496 */ 497 498 /* 499 * start the SMP system 500 */ 501 static void 502 mp_enable(u_int boot_addr) 503 { 504 int x; 505 #if defined(APIC_IO) 506 int apic; 507 u_int ux; 508 #endif /* APIC_IO */ 509 510 getmtrr(); 511 putfmtrr(); 512 513 POSTCODE(MP_ENABLE_POST); 514 515 /* turn on 4MB of V == P addressing so we can get to MP table */ 516 *(int *)PTD = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); 517 invltlb(); 518 519 /* examine the MP table for needed info, uses physical addresses */ 520 x = mptable_pass2(); 521 522 *(int *)PTD = 0; 523 invltlb(); 524 525 /* can't process default configs till the CPU APIC is pmapped */ 526 if (x) 527 default_mp_table(x); 528 529 /* post scan cleanup */ 530 fix_mp_table(); 531 532 #if defined(APIC_IO) 533 534 /* fill the LOGICAL io_apic_versions table */ 535 for (apic = 0; apic < mp_napics; ++apic) { 536 ux = io_apic_read(apic, IOAPIC_VER); 537 io_apic_versions[apic] = ux; 538 } 539 540 /* program each IO APIC in the system */ 541 for (apic = 0; apic < mp_napics; ++apic) 542 if (io_apic_setup(apic) < 0) 543 panic("IO APIC setup failure"); 544 545 /* install a 'Spurious INTerrupt' vector */ 546 setidt(XSPURIOUSINT_OFFSET, Xspuriousint, 547 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 548 549 /* install an inter-CPU IPI for TLB invalidation */ 550 setidt(XINVLTLB_OFFSET, Xinvltlb, 551 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 552 553 /* install an inter-CPU IPI for CPU stop/restart */ 554 setidt(XCPUSTOP_OFFSET, Xcpustop, 555 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 556 557 #if defined(TEST_TEST1) 558 /* install a "fake hardware INTerrupt" vector */ 559 setidt(XTEST1_OFFSET, Xtest1, 560 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 561 #endif /** TEST_TEST1 */ 562 563 #endif /* APIC_IO */ 564 565 /* initialize all SMP locks */ 566 init_locks(); 567 568 /* start each Application Processor */ 569 start_all_aps(boot_addr); 570 571 /* 572 * The init process might be started on a different CPU now, 573 * and the boot CPU might not call prepare_usermode to get 574 * cr0 correctly configured. Thus we initialize cr0 here. 575 */ 576 load_cr0(rcr0() | CR0_WP | CR0_AM); 577 } 578 579 580 /* 581 * look for the MP spec signature 582 */ 583 584 /* string defined by the Intel MP Spec as identifying the MP table */ 585 #define MP_SIG 0x5f504d5f /* _MP_ */ 586 #define NEXT(X) ((X) += 4) 587 static int 588 search_for_sig(u_int32_t target, int count) 589 { 590 int x; 591 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 592 593 for (x = 0; x < count; NEXT(x)) 594 if (addr[x] == MP_SIG) 595 /* make array index a byte index */ 596 return (target + (x * sizeof(u_int32_t))); 597 598 return -1; 599 } 600 601 602 static basetable_entry basetable_entry_types[] = 603 { 604 {0, 20, "Processor"}, 605 {1, 8, "Bus"}, 606 {2, 8, "I/O APIC"}, 607 {3, 8, "I/O INT"}, 608 {4, 8, "Local INT"} 609 }; 610 611 typedef struct BUSDATA { 612 u_char bus_id; 613 enum busTypes bus_type; 614 } bus_datum; 615 616 typedef struct INTDATA { 617 u_char int_type; 618 u_short int_flags; 619 u_char src_bus_id; 620 u_char src_bus_irq; 621 u_char dst_apic_id; 622 u_char dst_apic_int; 623 } io_int, local_int; 624 625 typedef struct BUSTYPENAME { 626 u_char type; 627 char name[7]; 628 } bus_type_name; 629 630 static bus_type_name bus_type_table[] = 631 { 632 {CBUS, "CBUS"}, 633 {CBUSII, "CBUSII"}, 634 {EISA, "EISA"}, 635 {UNKNOWN_BUSTYPE, "---"}, 636 {UNKNOWN_BUSTYPE, "---"}, 637 {ISA, "ISA"}, 638 {UNKNOWN_BUSTYPE, "---"}, 639 {UNKNOWN_BUSTYPE, "---"}, 640 {UNKNOWN_BUSTYPE, "---"}, 641 {UNKNOWN_BUSTYPE, "---"}, 642 {UNKNOWN_BUSTYPE, "---"}, 643 {UNKNOWN_BUSTYPE, "---"}, 644 {PCI, "PCI"}, 645 {UNKNOWN_BUSTYPE, "---"}, 646 {UNKNOWN_BUSTYPE, "---"}, 647 {UNKNOWN_BUSTYPE, "---"}, 648 {UNKNOWN_BUSTYPE, "---"}, 649 {XPRESS, "XPRESS"}, 650 {UNKNOWN_BUSTYPE, "---"} 651 }; 652 /* from MP spec v1.4, table 5-1 */ 653 static int default_data[7][5] = 654 { 655 /* nbus, id0, type0, id1, type1 */ 656 {1, 0, ISA, 255, 255}, 657 {1, 0, EISA, 255, 255}, 658 {1, 0, EISA, 255, 255}, 659 {0, 255, 255, 255, 255},/* MCA not supported */ 660 {2, 0, ISA, 1, PCI}, 661 {2, 0, EISA, 1, PCI}, 662 {0, 255, 255, 255, 255} /* MCA not supported */ 663 }; 664 665 666 /* the bus data */ 667 bus_datum bus_data[NBUS]; 668 669 /* the IO INT data, one entry per possible APIC INTerrupt */ 670 io_int io_apic_ints[NINTR]; 671 672 static int nintrs; 673 674 static int processor_entry __P((proc_entry_ptr entry, int cpu)); 675 static int bus_entry __P((bus_entry_ptr entry, int bus)); 676 static int io_apic_entry __P((io_apic_entry_ptr entry, int apic)); 677 static int int_entry __P((int_entry_ptr entry, int intr)); 678 static int lookup_bus_type __P((char *name)); 679 680 681 /* 682 * 1st pass on motherboard's Intel MP specification table. 683 * 684 * initializes: 685 * mp_ncpus = 1 686 * 687 * determines: 688 * cpu_apic_address (common to all CPUs) 689 * io_apic_address[N] 690 * mp_naps 691 * mp_nbusses 692 * mp_napics 693 * nintrs 694 */ 695 static int 696 mptable_pass1(void) 697 { 698 int x; 699 mpcth_t cth; 700 int totalSize; 701 void* position; 702 int count; 703 int type; 704 int mustpanic; 705 706 POSTCODE(MPTABLE_PASS1_POST); 707 708 mustpanic = 0; 709 710 /* clear various tables */ 711 for (x = 0; x < NAPICID; ++x) { 712 io_apic_address[x] = ~0; /* IO APIC address table */ 713 } 714 715 /* init everything to empty */ 716 mp_naps = 0; 717 mp_nbusses = 0; 718 mp_napics = 0; 719 nintrs = 0; 720 721 /* check for use of 'default' configuration */ 722 if (MPFPS_MPFB1 != 0) { 723 /* use default addresses */ 724 cpu_apic_address = DEFAULT_APIC_BASE; 725 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 726 727 /* fill in with defaults */ 728 mp_naps = 2; /* includes BSP */ 729 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0]; 730 #if defined(APIC_IO) 731 mp_napics = 1; 732 nintrs = 16; 733 #endif /* APIC_IO */ 734 } 735 else { 736 if ((cth = mpfps->pap) == 0) 737 panic("MP Configuration Table Header MISSING!"); 738 739 cpu_apic_address = (vm_offset_t) cth->apic_address; 740 741 /* walk the table, recording info of interest */ 742 totalSize = cth->base_table_length - sizeof(struct MPCTH); 743 position = (u_char *) cth + sizeof(struct MPCTH); 744 count = cth->entry_count; 745 746 while (count--) { 747 switch (type = *(u_char *) position) { 748 case 0: /* processor_entry */ 749 if (((proc_entry_ptr)position)->cpu_flags 750 & PROCENTRY_FLAG_EN) 751 ++mp_naps; 752 break; 753 case 1: /* bus_entry */ 754 ++mp_nbusses; 755 break; 756 case 2: /* io_apic_entry */ 757 if (((io_apic_entry_ptr)position)->apic_flags 758 & IOAPICENTRY_FLAG_EN) 759 io_apic_address[mp_napics++] = 760 (vm_offset_t)((io_apic_entry_ptr) 761 position)->apic_address; 762 break; 763 case 3: /* int_entry */ 764 ++nintrs; 765 break; 766 case 4: /* int_entry */ 767 break; 768 default: 769 panic("mpfps Base Table HOSED!"); 770 /* NOTREACHED */ 771 } 772 773 totalSize -= basetable_entry_types[type].length; 774 (u_char*)position += basetable_entry_types[type].length; 775 } 776 } 777 778 /* qualify the numbers */ 779 if (mp_naps > NCPU) 780 #if 0 /* XXX FIXME: kern/4255 */ 781 printf("Warning: only using %d of %d available CPUs!\n", 782 NCPU, mp_naps); 783 #else 784 { 785 printf("NCPU cannot be different than actual CPU count.\n"); 786 printf(" add 'options NCPU=%d' to your kernel config file,\n", 787 mp_naps); 788 printf(" then rerun config & rebuild your SMP kernel\n"); 789 mustpanic = 1; 790 } 791 #endif /* XXX FIXME: kern/4255 */ 792 if (mp_nbusses > NBUS) { 793 printf("found %d busses, increase NBUS\n", mp_nbusses); 794 mustpanic = 1; 795 } 796 if (mp_napics > NAPIC) { 797 printf("found %d apics, increase NAPIC\n", mp_napics); 798 mustpanic = 1; 799 } 800 if (nintrs > NINTR) { 801 printf("found %d intrs, increase NINTR\n", nintrs); 802 mustpanic = 1; 803 } 804 805 /* 806 * Count the BSP. 807 * This is also used as a counter while starting the APs. 808 */ 809 mp_ncpus = 1; 810 811 --mp_naps; /* subtract the BSP */ 812 813 return mustpanic; 814 } 815 816 817 /* 818 * 2nd pass on motherboard's Intel MP specification table. 819 * 820 * sets: 821 * boot_cpu_id 822 * ID_TO_IO(N), phy APIC ID to log CPU/IO table 823 * CPU_TO_ID(N), logical CPU to APIC ID table 824 * IO_TO_ID(N), logical IO to APIC ID table 825 * bus_data[N] 826 * io_apic_ints[N] 827 */ 828 static int 829 mptable_pass2(void) 830 { 831 int x; 832 mpcth_t cth; 833 int totalSize; 834 void* position; 835 int count; 836 int type; 837 int apic, bus, cpu, intr; 838 839 POSTCODE(MPTABLE_PASS2_POST); 840 841 /* clear various tables */ 842 for (x = 0; x < NAPICID; ++x) { 843 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ 844 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ 845 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ 846 } 847 848 /* clear bus data table */ 849 for (x = 0; x < NBUS; ++x) 850 bus_data[x].bus_id = 0xff; 851 852 /* clear IO APIC INT table */ 853 for (x = 0; x < NINTR; ++x) 854 io_apic_ints[x].int_type = 0xff; 855 856 /* setup the cpu/apic mapping arrays */ 857 boot_cpu_id = -1; 858 859 /* record whether PIC or virtual-wire mode */ 860 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; 861 862 /* check for use of 'default' configuration */ 863 if (MPFPS_MPFB1 != 0) 864 return MPFPS_MPFB1; /* return default configuration type */ 865 866 if ((cth = mpfps->pap) == 0) 867 panic("MP Configuration Table Header MISSING!"); 868 869 /* walk the table, recording info of interest */ 870 totalSize = cth->base_table_length - sizeof(struct MPCTH); 871 position = (u_char *) cth + sizeof(struct MPCTH); 872 count = cth->entry_count; 873 apic = bus = intr = 0; 874 cpu = 1; /* pre-count the BSP */ 875 876 while (count--) { 877 switch (type = *(u_char *) position) { 878 case 0: 879 if (processor_entry(position, cpu)) 880 ++cpu; 881 break; 882 case 1: 883 if (bus_entry(position, bus)) 884 ++bus; 885 break; 886 case 2: 887 if (io_apic_entry(position, apic)) 888 ++apic; 889 break; 890 case 3: 891 if (int_entry(position, intr)) 892 ++intr; 893 break; 894 case 4: 895 /* int_entry(position); */ 896 break; 897 default: 898 panic("mpfps Base Table HOSED!"); 899 /* NOTREACHED */ 900 } 901 902 totalSize -= basetable_entry_types[type].length; 903 (u_char *) position += basetable_entry_types[type].length; 904 } 905 906 if (boot_cpu_id == -1) 907 panic("NO BSP found!"); 908 909 /* report fact that its NOT a default configuration */ 910 return 0; 911 } 912 913 914 /* 915 * parse an Intel MP specification table 916 */ 917 static void 918 fix_mp_table(void) 919 { 920 int x; 921 int id; 922 int bus_0; 923 int bus_pci; 924 int num_pci_bus; 925 926 /* 927 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS 928 * did it wrong. The MP spec says that when more than 1 PCI bus 929 * exists the BIOS must begin with bus entries for the PCI bus and use 930 * actual PCI bus numbering. This implies that when only 1 PCI bus 931 * exists the BIOS can choose to ignore this ordering, and indeed many 932 * MP motherboards do ignore it. This causes a problem when the PCI 933 * sub-system makes requests of the MP sub-system based on PCI bus 934 * numbers. So here we look for the situation and renumber the 935 * busses and associated INTs in an effort to "make it right". 936 */ 937 938 /* find bus 0, PCI bus, count the number of PCI busses */ 939 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { 940 if (bus_data[x].bus_id == 0) { 941 bus_0 = x; 942 } 943 if (bus_data[x].bus_type == PCI) { 944 ++num_pci_bus; 945 bus_pci = x; 946 } 947 } 948 /* 949 * bus_0 == slot of bus with ID of 0 950 * bus_pci == slot of last PCI bus encountered 951 */ 952 953 /* check the 1 PCI bus case for sanity */ 954 if (num_pci_bus == 1) { 955 956 /* if it is number 0 all is well */ 957 if (bus_data[bus_pci].bus_id == 0) 958 return; 959 960 /* mis-numbered, swap with whichever bus uses slot 0 */ 961 962 /* swap the bus entry types */ 963 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; 964 bus_data[bus_0].bus_type = PCI; 965 966 /* swap each relavant INTerrupt entry */ 967 id = bus_data[bus_pci].bus_id; 968 for (x = 0; x < nintrs; ++x) { 969 if (io_apic_ints[x].src_bus_id == id) { 970 io_apic_ints[x].src_bus_id = 0; 971 } 972 else if (io_apic_ints[x].src_bus_id == 0) { 973 io_apic_ints[x].src_bus_id = id; 974 } 975 } 976 } 977 /* sanity check if more than 1 PCI bus */ 978 else if (num_pci_bus > 1) { 979 for (x = 0; x < mp_nbusses; ++x) { 980 if (bus_data[x].bus_type != PCI) 981 continue; 982 if (bus_data[x].bus_id >= num_pci_bus) 983 panic("bad PCI bus numbering"); 984 } 985 } 986 } 987 988 989 static int 990 processor_entry(proc_entry_ptr entry, int cpu) 991 { 992 /* check for usability */ 993 if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN)) 994 return 0; 995 996 /* check for BSP flag */ 997 if (entry->cpu_flags & PROCENTRY_FLAG_BP) { 998 boot_cpu_id = entry->apic_id; 999 CPU_TO_ID(0) = entry->apic_id; 1000 ID_TO_CPU(entry->apic_id) = 0; 1001 return 0; /* its already been counted */ 1002 } 1003 1004 /* add another AP to list, if less than max number of CPUs */ 1005 else { 1006 CPU_TO_ID(cpu) = entry->apic_id; 1007 ID_TO_CPU(entry->apic_id) = cpu; 1008 return 1; 1009 } 1010 } 1011 1012 1013 static int 1014 bus_entry(bus_entry_ptr entry, int bus) 1015 { 1016 int x; 1017 char c, name[8]; 1018 1019 /* encode the name into an index */ 1020 for (x = 0; x < 6; ++x) { 1021 if ((c = entry->bus_type[x]) == ' ') 1022 break; 1023 name[x] = c; 1024 } 1025 name[x] = '\0'; 1026 1027 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) 1028 panic("unknown bus type: '%s'", name); 1029 1030 bus_data[bus].bus_id = entry->bus_id; 1031 bus_data[bus].bus_type = x; 1032 1033 return 1; 1034 } 1035 1036 1037 static int 1038 io_apic_entry(io_apic_entry_ptr entry, int apic) 1039 { 1040 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) 1041 return 0; 1042 1043 IO_TO_ID(apic) = entry->apic_id; 1044 ID_TO_IO(entry->apic_id) = apic; 1045 1046 return 1; 1047 } 1048 1049 1050 static int 1051 lookup_bus_type(char *name) 1052 { 1053 int x; 1054 1055 for (x = 0; x < MAX_BUSTYPE; ++x) 1056 if (strcmp(bus_type_table[x].name, name) == 0) 1057 return bus_type_table[x].type; 1058 1059 return UNKNOWN_BUSTYPE; 1060 } 1061 1062 1063 static int 1064 int_entry(int_entry_ptr entry, int intr) 1065 { 1066 io_apic_ints[intr].int_type = entry->int_type; 1067 io_apic_ints[intr].int_flags = entry->int_flags; 1068 io_apic_ints[intr].src_bus_id = entry->src_bus_id; 1069 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; 1070 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; 1071 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; 1072 1073 return 1; 1074 } 1075 1076 1077 static int 1078 apic_int_is_bus_type(int intr, int bus_type) 1079 { 1080 int bus; 1081 1082 for (bus = 0; bus < mp_nbusses; ++bus) 1083 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) 1084 && ((int) bus_data[bus].bus_type == bus_type)) 1085 return 1; 1086 1087 return 0; 1088 } 1089 1090 1091 /* 1092 * Given a traditional ISA INT mask, return an APIC mask. 1093 */ 1094 u_int 1095 isa_apic_mask(u_int isa_mask) 1096 { 1097 int isa_irq; 1098 int apic_pin; 1099 1100 #if defined(SKIP_IRQ15_REDIRECT) 1101 if (isa_mask == (1 << 15)) { 1102 printf("skipping ISA IRQ15 redirect\n"); 1103 return isa_mask; 1104 } 1105 #endif /* SKIP_IRQ15_REDIRECT */ 1106 1107 isa_irq = ffs(isa_mask); /* find its bit position */ 1108 if (isa_irq == 0) /* doesn't exist */ 1109 return 0; 1110 --isa_irq; /* make it zero based */ 1111 1112 apic_pin = isa_apic_pin(isa_irq); /* look for APIC connection */ 1113 if (apic_pin == -1) 1114 return 0; 1115 1116 return (1 << apic_pin); /* convert pin# to a mask */ 1117 } 1118 1119 1120 /* 1121 * Determine which APIC pin an ISA/EISA INT is attached to. 1122 */ 1123 #define INTTYPE(I) (io_apic_ints[(I)].int_type) 1124 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) 1125 1126 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 1127 int 1128 isa_apic_pin(int isa_irq) 1129 { 1130 int intr; 1131 1132 for (intr = 0; intr < nintrs; ++intr) { /* check each record */ 1133 if (INTTYPE(intr) == 0) { /* standard INT */ 1134 if (SRCBUSIRQ(intr) == isa_irq) { 1135 if (apic_int_is_bus_type(intr, ISA) || 1136 apic_int_is_bus_type(intr, EISA)) 1137 return INTPIN(intr); /* found */ 1138 } 1139 } 1140 } 1141 return -1; /* NOT found */ 1142 } 1143 #undef SRCBUSIRQ 1144 1145 1146 /* 1147 * Determine which APIC pin a PCI INT is attached to. 1148 */ 1149 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) 1150 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) 1151 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) 1152 int 1153 pci_apic_pin(int pciBus, int pciDevice, int pciInt) 1154 { 1155 int intr; 1156 1157 --pciInt; /* zero based */ 1158 1159 for (intr = 0; intr < nintrs; ++intr) /* check each record */ 1160 if ((INTTYPE(intr) == 0) /* standard INT */ 1161 && (SRCBUSID(intr) == pciBus) 1162 && (SRCBUSDEVICE(intr) == pciDevice) 1163 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ 1164 if (apic_int_is_bus_type(intr, PCI)) 1165 return INTPIN(intr); /* exact match */ 1166 1167 return -1; /* NOT found */ 1168 } 1169 #undef SRCBUSLINE 1170 #undef SRCBUSDEVICE 1171 #undef SRCBUSID 1172 1173 #undef INTPIN 1174 #undef INTTYPE 1175 1176 1177 /* 1178 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. 1179 * 1180 * XXX FIXME: 1181 * Exactly what this means is unclear at this point. It is a solution 1182 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard 1183 * could route any of the ISA INTs to upper (>15) IRQ values. But most would 1184 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an 1185 * option. 1186 */ 1187 int 1188 undirect_isa_irq(int rirq) 1189 { 1190 #if defined(READY) 1191 printf("Freeing redirected ISA irq %d.\n", rirq); 1192 /** FIXME: tickle the MB redirector chip */ 1193 return ???; 1194 #else 1195 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); 1196 return 0; 1197 #endif /* READY */ 1198 } 1199 1200 1201 /* 1202 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt 1203 */ 1204 int 1205 undirect_pci_irq(int rirq) 1206 { 1207 #if defined(READY) 1208 if (bootverbose) 1209 printf("Freeing redirected PCI irq %d.\n", rirq); 1210 1211 /** FIXME: tickle the MB redirector chip */ 1212 return ???; 1213 #else 1214 if (bootverbose) 1215 printf("Freeing (NOT implemented) redirected PCI irq %d.\n", 1216 rirq); 1217 return 0; 1218 #endif /* READY */ 1219 } 1220 1221 1222 /* 1223 * given a bus ID, return: 1224 * the bus type if found 1225 * -1 if NOT found 1226 */ 1227 int 1228 apic_bus_type(int id) 1229 { 1230 int x; 1231 1232 for (x = 0; x < mp_nbusses; ++x) 1233 if (bus_data[x].bus_id == id) 1234 return bus_data[x].bus_type; 1235 1236 return -1; 1237 } 1238 1239 1240 /* 1241 * given a LOGICAL APIC# and pin#, return: 1242 * the associated src bus ID if found 1243 * -1 if NOT found 1244 */ 1245 int 1246 apic_src_bus_id(int apic, int pin) 1247 { 1248 int x; 1249 1250 /* search each of the possible INTerrupt sources */ 1251 for (x = 0; x < nintrs; ++x) 1252 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1253 (pin == io_apic_ints[x].dst_apic_int)) 1254 return (io_apic_ints[x].src_bus_id); 1255 1256 return -1; /* NOT found */ 1257 } 1258 1259 1260 /* 1261 * given a LOGICAL APIC# and pin#, return: 1262 * the associated src bus IRQ if found 1263 * -1 if NOT found 1264 */ 1265 int 1266 apic_src_bus_irq(int apic, int pin) 1267 { 1268 int x; 1269 1270 for (x = 0; x < nintrs; x++) 1271 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1272 (pin == io_apic_ints[x].dst_apic_int)) 1273 return (io_apic_ints[x].src_bus_irq); 1274 1275 return -1; /* NOT found */ 1276 } 1277 1278 1279 /* 1280 * given a LOGICAL APIC# and pin#, return: 1281 * the associated INTerrupt type if found 1282 * -1 if NOT found 1283 */ 1284 int 1285 apic_int_type(int apic, int pin) 1286 { 1287 int x; 1288 1289 /* search each of the possible INTerrupt sources */ 1290 for (x = 0; x < nintrs; ++x) 1291 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1292 (pin == io_apic_ints[x].dst_apic_int)) 1293 return (io_apic_ints[x].int_type); 1294 1295 return -1; /* NOT found */ 1296 } 1297 1298 1299 /* 1300 * given a LOGICAL APIC# and pin#, return: 1301 * the associated trigger mode if found 1302 * -1 if NOT found 1303 */ 1304 int 1305 apic_trigger(int apic, int pin) 1306 { 1307 int x; 1308 1309 /* search each of the possible INTerrupt sources */ 1310 for (x = 0; x < nintrs; ++x) 1311 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1312 (pin == io_apic_ints[x].dst_apic_int)) 1313 return ((io_apic_ints[x].int_flags >> 2) & 0x03); 1314 1315 return -1; /* NOT found */ 1316 } 1317 1318 1319 /* 1320 * given a LOGICAL APIC# and pin#, return: 1321 * the associated 'active' level if found 1322 * -1 if NOT found 1323 */ 1324 int 1325 apic_polarity(int apic, int pin) 1326 { 1327 int x; 1328 1329 /* search each of the possible INTerrupt sources */ 1330 for (x = 0; x < nintrs; ++x) 1331 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1332 (pin == io_apic_ints[x].dst_apic_int)) 1333 return (io_apic_ints[x].int_flags & 0x03); 1334 1335 return -1; /* NOT found */ 1336 } 1337 1338 1339 /* 1340 * set data according to MP defaults 1341 * FIXME: probably not complete yet... 1342 */ 1343 static void 1344 default_mp_table(int type) 1345 { 1346 int ap_cpu_id; 1347 #if defined(APIC_IO) 1348 u_int32_t ux; 1349 int io_apic_id; 1350 int pin; 1351 #endif /* APIC_IO */ 1352 1353 #if 0 1354 printf(" MP default config type: %d\n", type); 1355 switch (type) { 1356 case 1: 1357 printf(" bus: ISA, APIC: 82489DX\n"); 1358 break; 1359 case 2: 1360 printf(" bus: EISA, APIC: 82489DX\n"); 1361 break; 1362 case 3: 1363 printf(" bus: EISA, APIC: 82489DX\n"); 1364 break; 1365 case 4: 1366 printf(" bus: MCA, APIC: 82489DX\n"); 1367 break; 1368 case 5: 1369 printf(" bus: ISA+PCI, APIC: Integrated\n"); 1370 break; 1371 case 6: 1372 printf(" bus: EISA+PCI, APIC: Integrated\n"); 1373 break; 1374 case 7: 1375 printf(" bus: MCA+PCI, APIC: Integrated\n"); 1376 break; 1377 default: 1378 printf(" future type\n"); 1379 break; 1380 /* NOTREACHED */ 1381 } 1382 #endif /* 0 */ 1383 1384 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; 1385 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; 1386 1387 /* BSP */ 1388 CPU_TO_ID(0) = boot_cpu_id; 1389 ID_TO_CPU(boot_cpu_id) = 0; 1390 1391 /* one and only AP */ 1392 CPU_TO_ID(1) = ap_cpu_id; 1393 ID_TO_CPU(ap_cpu_id) = 1; 1394 1395 #if defined(APIC_IO) 1396 /* one and only IO APIC */ 1397 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; 1398 1399 /* 1400 * sanity check, refer to MP spec section 3.6.6, last paragraph 1401 * necessary as some hardware isn't properly setting up the IO APIC 1402 */ 1403 #if defined(REALLY_ANAL_IOAPICID_VALUE) 1404 if (io_apic_id != 2) { 1405 #else 1406 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { 1407 #endif /* REALLY_ANAL_IOAPICID_VALUE */ 1408 ux = io_apic_read(0, IOAPIC_ID); /* get current contents */ 1409 ux &= ~APIC_ID_MASK; /* clear the ID field */ 1410 ux |= 0x02000000; /* set it to '2' */ 1411 io_apic_write(0, IOAPIC_ID, ux); /* write new value */ 1412 ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */ 1413 if ((ux & APIC_ID_MASK) != 0x02000000) 1414 panic("can't control IO APIC ID, reg: 0x%08x", ux); 1415 io_apic_id = 2; 1416 } 1417 IO_TO_ID(0) = io_apic_id; 1418 ID_TO_IO(io_apic_id) = 0; 1419 #endif /* APIC_IO */ 1420 1421 /* fill out bus entries */ 1422 switch (type) { 1423 case 1: 1424 case 2: 1425 case 3: 1426 case 5: 1427 case 6: 1428 bus_data[0].bus_id = default_data[type - 1][1]; 1429 bus_data[0].bus_type = default_data[type - 1][2]; 1430 bus_data[1].bus_id = default_data[type - 1][3]; 1431 bus_data[1].bus_type = default_data[type - 1][4]; 1432 break; 1433 1434 /* case 4: case 7: MCA NOT supported */ 1435 default: /* illegal/reserved */ 1436 panic("BAD default MP config: %d", type); 1437 /* NOTREACHED */ 1438 } 1439 1440 #if defined(APIC_IO) 1441 /* general cases from MP v1.4, table 5-2 */ 1442 for (pin = 0; pin < 16; ++pin) { 1443 io_apic_ints[pin].int_type = 0; 1444 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */ 1445 io_apic_ints[pin].src_bus_id = 0; 1446 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */ 1447 io_apic_ints[pin].dst_apic_id = io_apic_id; 1448 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */ 1449 } 1450 1451 /* special cases from MP v1.4, table 5-2 */ 1452 if (type == 2) { 1453 io_apic_ints[2].int_type = 0xff; /* N/C */ 1454 io_apic_ints[13].int_type = 0xff; /* N/C */ 1455 #if !defined(APIC_MIXED_MODE) 1456 /** FIXME: ??? */ 1457 panic("sorry, can't support type 2 default yet"); 1458 #endif /* APIC_MIXED_MODE */ 1459 } 1460 else 1461 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ 1462 1463 if (type == 7) 1464 io_apic_ints[0].int_type = 0xff; /* N/C */ 1465 else 1466 io_apic_ints[0].int_type = 3; /* vectored 8259 */ 1467 #endif /* APIC_IO */ 1468 } 1469 1470 1471 /* 1472 * initialize all the SMP locks 1473 */ 1474 1475 /* critical region around IO APIC, apic_imen */ 1476 struct simplelock imen_lock; 1477 1478 /* critical region around splxx(), cpl, cml, cil, ipending */ 1479 struct simplelock cpl_lock; 1480 1481 /* Make FAST_INTR() routines sequential */ 1482 struct simplelock fast_intr_lock; 1483 1484 /* critical region around INTR() routines */ 1485 struct simplelock intr_lock; 1486 1487 /* lock regions protected in UP kernel via cli/sti */ 1488 struct simplelock mpintr_lock; 1489 1490 #ifdef USE_COMLOCK 1491 /* locks com (tty) data/hardware accesses: a FASTINTR() */ 1492 struct simplelock com_lock; 1493 #endif /* USE_COMLOCK */ 1494 1495 #ifdef USE_CLOCKLOCK 1496 /* lock regions around the clock hardware */ 1497 struct simplelock clock_lock; 1498 #endif /* USE_CLOCKLOCK */ 1499 1500 static void 1501 init_locks(void) 1502 { 1503 /* 1504 * Get the initial mp_lock with a count of 1 for the BSP. 1505 * This uses a LOGICAL cpu ID, ie BSP == 0. 1506 */ 1507 mp_lock = 0x00000001; 1508 1509 /* ISR uses its own "giant lock" */ 1510 isr_lock = FREE_LOCK; 1511 1512 s_lock_init((struct simplelock*)&mpintr_lock); 1513 1514 s_lock_init((struct simplelock*)&fast_intr_lock); 1515 s_lock_init((struct simplelock*)&intr_lock); 1516 s_lock_init((struct simplelock*)&imen_lock); 1517 s_lock_init((struct simplelock*)&cpl_lock); 1518 1519 #ifdef USE_COMLOCK 1520 s_lock_init((struct simplelock*)&com_lock); 1521 #endif /* USE_COMLOCK */ 1522 #ifdef USE_CLOCKLOCK 1523 s_lock_init((struct simplelock*)&clock_lock); 1524 #endif /* USE_CLOCKLOCK */ 1525 } 1526 1527 1528 /* 1529 * start each AP in our list 1530 */ 1531 static int 1532 start_all_aps(u_int boot_addr) 1533 { 1534 int x, i; 1535 u_char mpbiosreason; 1536 u_long mpbioswarmvec; 1537 pd_entry_t *newptd; 1538 pt_entry_t *newpt; 1539 int *newpp; 1540 char *stack; 1541 pd_entry_t *myPTD; 1542 1543 POSTCODE(START_ALL_APS_POST); 1544 1545 /* initialize BSP's local APIC */ 1546 apic_initialize(); 1547 bsp_apic_ready = 1; 1548 1549 /* install the AP 1st level boot code */ 1550 install_ap_tramp(boot_addr); 1551 1552 1553 /* save the current value of the warm-start vector */ 1554 mpbioswarmvec = *((u_long *) WARMBOOT_OFF); 1555 outb(CMOS_REG, BIOS_RESET); 1556 mpbiosreason = inb(CMOS_DATA); 1557 1558 /* record BSP in CPU map */ 1559 all_cpus = 1; 1560 1561 /* start each AP */ 1562 for (x = 1; x <= mp_naps; ++x) { 1563 1564 /* This is a bit verbose, it will go away soon. */ 1565 1566 /* alloc new page table directory */ 1567 newptd = (pd_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE)); 1568 1569 /* Store the virtual PTD address for this CPU */ 1570 IdlePTDS[x] = newptd; 1571 1572 /* clone currently active one (ie: IdlePTD) */ 1573 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ 1574 1575 /* set up 0 -> 4MB P==V mapping for AP boot */ 1576 newptd[0] = (pd_entry_t) (PG_V | PG_RW | 1577 ((u_long)KPTphys & PG_FRAME)); 1578 1579 /* store PTD for this AP's boot sequence */ 1580 myPTD = (pd_entry_t *)vtophys(newptd); 1581 1582 /* alloc new page table page */ 1583 newpt = (pt_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE)); 1584 1585 /* set the new PTD's private page to point there */ 1586 newptd[MPPTDI] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpt)); 1587 1588 /* install self referential entry */ 1589 newptd[PTDPTDI] = (pd_entry_t)(PG_V | PG_RW | vtophys(newptd)); 1590 1591 /* allocate a new private data page */ 1592 newpp = (int *)kmem_alloc(kernel_map, PAGE_SIZE); 1593 1594 /* wire it into the private page table page */ 1595 newpt[0] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpp)); 1596 1597 /* wire the ptp into itself for access */ 1598 newpt[1] = (pt_entry_t)(PG_V | PG_RW | vtophys(newpt)); 1599 1600 /* copy in the pointer to the local apic */ 1601 newpt[2] = SMP_prvpt[2]; 1602 1603 /* and the IO apic mapping[s] */ 1604 for (i = 16; i < 32; i++) 1605 newpt[i] = SMP_prvpt[i]; 1606 1607 /* allocate and set up an idle stack data page */ 1608 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE); 1609 for (i = 0; i < UPAGES; i++) 1610 newpt[i + 3] = (pt_entry_t)(PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 1611 1612 newpt[5] = 0; /* *prv_CMAP1 */ 1613 newpt[6] = 0; /* *prv_CMAP2 */ 1614 newpt[7] = 0; /* *prv_CMAP3 */ 1615 1616 /* prime data page for it to use */ 1617 newpp[0] = x; /* cpuid */ 1618 newpp[1] = 0; /* curproc */ 1619 newpp[2] = 0; /* curpcb */ 1620 newpp[3] = 0; /* npxproc */ 1621 newpp[4] = 0; /* runtime.tv_sec */ 1622 newpp[5] = 0; /* runtime.tv_usec */ 1623 newpp[6] = x << 24; /* cpu_lockid */ 1624 newpp[7] = 0; /* other_cpus */ 1625 newpp[8] = (int)myPTD; /* my_idlePTD */ 1626 newpp[9] = 0; /* ss_tpr */ 1627 newpp[10] = (int)&newpt[5]; /* prv_CMAP1 */ 1628 newpp[11] = (int)&newpt[6]; /* prv_CMAP2 */ 1629 newpp[12] = (int)&newpt[7]; /* prv_CMAP3 */ 1630 1631 /* setup a vector to our boot code */ 1632 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 1633 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 1634 outb(CMOS_REG, BIOS_RESET); 1635 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 1636 1637 bootPTD = myPTD; 1638 /* attempt to start the Application Processor */ 1639 CHECK_INIT(99); /* setup checkpoints */ 1640 if (!start_ap(x, boot_addr)) { 1641 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); 1642 CHECK_PRINT("trace"); /* show checkpoints */ 1643 /* better panic as the AP may be running loose */ 1644 printf("panic y/n? [y] "); 1645 if (cngetc() != 'n') 1646 panic("bye-bye"); 1647 } 1648 CHECK_PRINT("trace"); /* show checkpoints */ 1649 1650 /* record its version info */ 1651 cpu_apic_versions[x] = cpu_apic_versions[0]; 1652 1653 all_cpus |= (1 << x); /* record AP in CPU map */ 1654 } 1655 1656 /* build our map of 'other' CPUs */ 1657 other_cpus = all_cpus & ~(1 << cpuid); 1658 1659 /* fill in our (BSP) APIC version */ 1660 cpu_apic_versions[0] = lapic.version; 1661 1662 /* restore the warmstart vector */ 1663 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 1664 outb(CMOS_REG, BIOS_RESET); 1665 outb(CMOS_DATA, mpbiosreason); 1666 1667 /* 1668 * Set up the idle context for the BSP. Similar to above except 1669 * that some was done by locore, some by pmap.c and some is implicit 1670 * because the BSP is cpu#0 and the page is initially zero, and also 1671 * because we can refer to variables by name on the BSP.. 1672 */ 1673 newptd = (pd_entry_t *)(kmem_alloc(kernel_map, PAGE_SIZE)); 1674 1675 bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ 1676 IdlePTDS[0] = newptd; 1677 1678 /* Point PTD[] to this page instead of IdlePTD's physical page */ 1679 newptd[PTDPTDI] = (pd_entry_t)(PG_V | PG_RW | vtophys(newptd)); 1680 1681 my_idlePTD = (pd_entry_t *)vtophys(newptd); 1682 1683 /* Allocate and setup BSP idle stack */ 1684 stack = (char *)kmem_alloc(kernel_map, UPAGES * PAGE_SIZE); 1685 for (i = 0; i < UPAGES; i++) 1686 SMP_prvpt[i + 3] = (pt_entry_t)(PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack)); 1687 1688 pmap_set_opt_bsp(); 1689 1690 for (i = 0; i < mp_ncpus; i++) { 1691 bcopy( (int *) PTD + KPTDI, (int *) IdlePTDS[i] + KPTDI, NKPDE * sizeof (int)); 1692 } 1693 1694 /* number of APs actually started */ 1695 return mp_ncpus - 1; 1696 } 1697 1698 1699 /* 1700 * load the 1st level AP boot code into base memory. 1701 */ 1702 1703 /* targets for relocation */ 1704 extern void bigJump(void); 1705 extern void bootCodeSeg(void); 1706 extern void bootDataSeg(void); 1707 extern void MPentry(void); 1708 extern u_int MP_GDT; 1709 extern u_int mp_gdtbase; 1710 1711 static void 1712 install_ap_tramp(u_int boot_addr) 1713 { 1714 int x; 1715 int size = *(int *) ((u_long) & bootMP_size); 1716 u_char *src = (u_char *) ((u_long) bootMP); 1717 u_char *dst = (u_char *) boot_addr + KERNBASE; 1718 u_int boot_base = (u_int) bootMP; 1719 u_int8_t *dst8; 1720 u_int16_t *dst16; 1721 u_int32_t *dst32; 1722 1723 POSTCODE(INSTALL_AP_TRAMP_POST); 1724 1725 for (x = 0; x < size; ++x) 1726 *dst++ = *src++; 1727 1728 /* 1729 * modify addresses in code we just moved to basemem. unfortunately we 1730 * need fairly detailed info about mpboot.s for this to work. changes 1731 * to mpboot.s might require changes here. 1732 */ 1733 1734 /* boot code is located in KERNEL space */ 1735 dst = (u_char *) boot_addr + KERNBASE; 1736 1737 /* modify the lgdt arg */ 1738 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 1739 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 1740 1741 /* modify the ljmp target for MPentry() */ 1742 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 1743 *dst32 = ((u_int) MPentry - KERNBASE); 1744 1745 /* modify the target for boot code segment */ 1746 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 1747 dst8 = (u_int8_t *) (dst16 + 1); 1748 *dst16 = (u_int) boot_addr & 0xffff; 1749 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1750 1751 /* modify the target for boot data segment */ 1752 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 1753 dst8 = (u_int8_t *) (dst16 + 1); 1754 *dst16 = (u_int) boot_addr & 0xffff; 1755 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1756 } 1757 1758 1759 /* 1760 * this function starts the AP (application processor) identified 1761 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 1762 * to accomplish this. This is necessary because of the nuances 1763 * of the different hardware we might encounter. It ain't pretty, 1764 * but it seems to work. 1765 */ 1766 static int 1767 start_ap(int logical_cpu, u_int boot_addr) 1768 { 1769 int physical_cpu; 1770 int vector; 1771 int cpus; 1772 u_long icr_lo, icr_hi; 1773 1774 POSTCODE(START_AP_POST); 1775 1776 /* get the PHYSICAL APIC ID# */ 1777 physical_cpu = CPU_TO_ID(logical_cpu); 1778 1779 /* calculate the vector */ 1780 vector = (boot_addr >> 12) & 0xff; 1781 1782 /* used as a watchpoint to signal AP startup */ 1783 cpus = mp_ncpus; 1784 1785 /* 1786 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 1787 * and running the target CPU. OR this INIT IPI might be latched (P5 1788 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 1789 * ignored. 1790 */ 1791 1792 /* setup the address for the target AP */ 1793 icr_hi = lapic.icr_hi & ~APIC_ID_MASK; 1794 icr_hi |= (physical_cpu << 24); 1795 lapic.icr_hi = icr_hi; 1796 1797 /* do an INIT IPI: assert RESET */ 1798 icr_lo = lapic.icr_lo & 0xfff00000; 1799 lapic.icr_lo = icr_lo | 0x0000c500; 1800 1801 /* wait for pending status end */ 1802 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1803 /* spin */ ; 1804 1805 /* do an INIT IPI: deassert RESET */ 1806 lapic.icr_lo = icr_lo | 0x00008500; 1807 1808 /* wait for pending status end */ 1809 u_sleep(10000); /* wait ~10mS */ 1810 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1811 /* spin */ ; 1812 1813 /* 1814 * next we do a STARTUP IPI: the previous INIT IPI might still be 1815 * latched, (P5 bug) this 1st STARTUP would then terminate 1816 * immediately, and the previously started INIT IPI would continue. OR 1817 * the previous INIT IPI has already run. and this STARTUP IPI will 1818 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 1819 * will run. 1820 */ 1821 1822 /* do a STARTUP IPI */ 1823 lapic.icr_lo = icr_lo | 0x00000600 | vector; 1824 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1825 /* spin */ ; 1826 u_sleep(200); /* wait ~200uS */ 1827 1828 /* 1829 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 1830 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 1831 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 1832 * recognized after hardware RESET or INIT IPI. 1833 */ 1834 1835 lapic.icr_lo = icr_lo | 0x00000600 | vector; 1836 while (lapic.icr_lo & APIC_DELSTAT_MASK) 1837 /* spin */ ; 1838 u_sleep(200); /* wait ~200uS */ 1839 1840 /* wait for it to start */ 1841 set_apic_timer(5000000);/* == 5 seconds */ 1842 while (read_apic_timer()) 1843 if (mp_ncpus > cpus) 1844 return 1; /* return SUCCESS */ 1845 1846 return 0; /* return FAILURE */ 1847 } 1848 1849 1850 /* 1851 * Flush the TLB on all other CPU's 1852 * 1853 * XXX: Needs to handshake and wait for completion before proceding. 1854 */ 1855 void 1856 smp_invltlb(void) 1857 { 1858 #if defined(APIC_IO) 1859 if (smp_started && invltlb_ok) 1860 all_but_self_ipi(XINVLTLB_OFFSET); 1861 #endif /* APIC_IO */ 1862 } 1863 1864 void 1865 invlpg(u_int addr) 1866 { 1867 __asm __volatile("invlpg (%0)"::"r"(addr):"memory"); 1868 1869 /* send a message to the other CPUs */ 1870 smp_invltlb(); 1871 } 1872 1873 void 1874 invltlb(void) 1875 { 1876 u_long temp; 1877 1878 /* 1879 * This should be implemented as load_cr3(rcr3()) when load_cr3() is 1880 * inlined. 1881 */ 1882 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory"); 1883 1884 /* send a message to the other CPUs */ 1885 smp_invltlb(); 1886 } 1887 1888 1889 /* 1890 * When called the executing CPU will send an IPI to all other CPUs 1891 * requesting that they halt execution. 1892 * 1893 * Usually (but not necessarily) called with 'other_cpus' as its arg. 1894 * 1895 * - Signals all CPUs in map to stop. 1896 * - Waits for each to stop. 1897 * 1898 * Returns: 1899 * -1: error 1900 * 0: NA 1901 * 1: ok 1902 * 1903 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs 1904 * from executing at same time. 1905 */ 1906 int 1907 stop_cpus(u_int map) 1908 { 1909 if (!smp_started) 1910 return 0; 1911 1912 /* send IPI to all CPUs in map */ 1913 stopped_cpus = 0; 1914 1915 /* send the Xcpustop IPI to all CPUs in map */ 1916 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED); 1917 1918 while (stopped_cpus != map) 1919 /* spin */ ; 1920 1921 return 1; 1922 } 1923 1924 1925 /* 1926 * Called by a CPU to restart stopped CPUs. 1927 * 1928 * Usually (but not necessarily) called with 'stopped_cpus' as its arg. 1929 * 1930 * - Signals all CPUs in map to restart. 1931 * - Waits for each to restart. 1932 * 1933 * Returns: 1934 * -1: error 1935 * 0: NA 1936 * 1: ok 1937 */ 1938 int 1939 restart_cpus(u_int map) 1940 { 1941 if (!smp_started) 1942 return 0; 1943 1944 started_cpus = map; /* signal other cpus to restart */ 1945 1946 while (started_cpus) /* wait for each to clear its bit */ 1947 /* spin */ ; 1948 1949 return 1; 1950 } 1951 1952 int smp_active = 0; /* are the APs allowed to run? */ 1953 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RW, &smp_active, 0, ""); 1954 1955 /* XXX maybe should be hw.ncpu */ 1956 int smp_cpus = 1; /* how many cpu's running */ 1957 SYSCTL_INT(_machdep, OID_AUTO, smp_cpus, CTLFLAG_RD, &smp_cpus, 0, ""); 1958 1959 int invltlb_ok = 0; /* throttle smp_invltlb() till safe */ 1960 SYSCTL_INT(_machdep, OID_AUTO, invltlb_ok, CTLFLAG_RW, &invltlb_ok, 0, ""); 1961 1962 int do_page_zero_idle = 0; /* bzero pages for fun and profit in idleloop */ 1963 SYSCTL_INT(_machdep, OID_AUTO, do_page_zero_idle, CTLFLAG_RW, 1964 &do_page_zero_idle, 0, ""); 1965 1966 1967 /* 1968 * This is called once the rest of the system is up and running and we're 1969 * ready to let the AP's out of the pen. 1970 */ 1971 void ap_init(void); 1972 1973 void 1974 ap_init() 1975 { 1976 u_int temp; 1977 u_int apic_id; 1978 1979 smp_cpus++; 1980 1981 /* Build our map of 'other' CPUs. */ 1982 other_cpus = all_cpus & ~(1 << cpuid); 1983 1984 printf("SMP: AP CPU #%d Launched!\n", cpuid); 1985 1986 /* XXX FIXME: i386 specific, and redundant: Setup the FPU. */ 1987 load_cr0((rcr0() & ~CR0_EM) | CR0_MP | CR0_NE | CR0_TS); 1988 1989 /* A quick check from sanity claus */ 1990 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]); 1991 if (cpuid != apic_id) { 1992 printf("SMP: cpuid = %d\n", cpuid); 1993 printf("SMP: apic_id = %d\n", apic_id); 1994 printf("PTD[MPPTDI] = %08x\n", PTD[MPPTDI]); 1995 panic("cpuid mismatch! boom!!"); 1996 } 1997 1998 /* Init local apic for irq's */ 1999 apic_initialize(); 2000 2001 /* 2002 * Activate smp_invltlb, although strictly speaking, this isn't 2003 * quite correct yet. We should have a bitfield for cpus willing 2004 * to accept TLB flush IPI's or something and sync them. 2005 */ 2006 invltlb_ok = 1; 2007 smp_started = 1; /* enable IPI's, tlb shootdown, freezes etc */ 2008 smp_active = 1; /* historic */ 2009 2010 curproc = NULL; /* make sure */ 2011 } 2012 2013 void 2014 getmtrr() { 2015 int i; 2016 if (cpu_class == CPUCLASS_686) { 2017 for(i=0;i<NPPROVMTRR;i++) { 2018 PPro_vmtrr[i].base = rdmsr(PPRO_VMTRRphysBase0 + i * 2); 2019 PPro_vmtrr[i].mask = rdmsr(PPRO_VMTRRphysMask0 + i * 2); 2020 } 2021 } 2022 } 2023 2024 void 2025 putmtrr() { 2026 int i; 2027 if (cpu_class == CPUCLASS_686) { 2028 wbinvd(); 2029 for(i=0;i<NPPROVMTRR;i++) { 2030 wrmsr(PPRO_VMTRRphysBase0 + i * 2, PPro_vmtrr[i].base); 2031 wrmsr(PPRO_VMTRRphysMask0 + i * 2, PPro_vmtrr[i].mask); 2032 } 2033 } 2034 } 2035 2036 void 2037 putfmtrr() { 2038 if (cpu_class == CPUCLASS_686) { 2039 wbinvd(); 2040 /* 2041 * Set memory between 0-640K to be WB 2042 */ 2043 wrmsr(0x250, 0x0606060606060606LL); 2044 wrmsr(0x258, 0x0606060606060606LL); 2045 /* 2046 * Set normal, PC video memory to be WC 2047 */ 2048 wrmsr(0x259, 0x0101010101010101LL); 2049 } 2050 } 2051 2052