1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1996, Sujal M. Patel 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Sujal M. Patel 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * from: pnp.h,v 1.7 1998/09/13 22:15:44 eivind Exp 34 */ 35 36 #ifndef _ISA_PNPREG_H_ 37 #define _ISA_PNPREG_H_ 38 39 /* Maximum Number of PnP Devices. 8 should be plenty */ 40 #define PNP_MAX_CARDS 8 41 42 /* Static ports to access PnP state machine */ 43 #define _PNP_ADDRESS 0x279 44 #define _PNP_WRITE_DATA 0xa79 45 46 /* PnP Registers. Write to ADDRESS and then use WRITE/READ_DATA */ 47 #define PNP_SET_RD_DATA 0x00 48 /*** 49 Writing to this location modifies the address of the port used for 50 reading from the Plug and Play ISA cards. Bits[7:0] become I/O 51 read port address bits[9:2]. Reads from this register are ignored. 52 ***/ 53 54 #define PNP_SERIAL_ISOLATION 0x01 55 /*** 56 A read to this register causes a Plug and Play cards in the Isolation 57 state to compare one bit of the boards ID. 58 This register is read only. 59 ***/ 60 61 #define PNP_CONFIG_CONTROL 0x02 62 #define PNP_CONFIG_CONTROL_RESET_CSN 0x04 63 #define PNP_CONFIG_CONTROL_WAIT_FOR_KEY 0x02 64 #define PNP_CONFIG_CONTROL_RESET 0x01 65 /*** 66 Bit[2] Reset CSN to 0 67 Bit[1] Return to the Wait for Key state 68 Bit[0] Reset all logical devices and restore configuration 69 registers to their power-up values. 70 71 A write to bit[0] of this register performs a reset function on 72 all logical devices. This resets the contents of configuration 73 registers to their default state. All card's logical devices 74 enter their default state and the CSN is preserved. 75 76 A write to bit[1] of this register causes all cards to enter the 77 Wait for Key state but all CSNs are preserved and logical devices 78 are not affected. 79 80 A write to bit[2] of this register causes all cards to reset their 81 CSN to zero . 82 83 This register is write-only. The values are not sticky, that is, 84 hardware will automatically clear them and there is no need for 85 software to clear the bits. 86 ***/ 87 88 #define PNP_WAKE 0x03 89 /*** 90 A write to this port will cause all cards that have a CSN that 91 matches the write data[7:0] to go from the Sleep state to the either 92 the Isolation state if the write data for this command is zero or 93 the Config state if the write data is not zero. Additionally, the 94 pointer to the byte-serial device is reset. This register is 95 writeonly. 96 ***/ 97 98 #define PNP_RESOURCE_DATA 0x04 99 /*** 100 A read from this address reads the next byte of resource information. 101 The Status register must be polled until bit[0] is set before this 102 register may be read. This register is read only. 103 ***/ 104 105 #define PNP_STATUS 0x05 106 /*** 107 Bit[0] when set indicates it is okay to read the next data byte 108 from the Resource Data register. This register is readonly. 109 ***/ 110 111 #define PNP_SET_CSN 0x06 112 /*** 113 A write to this port sets a card's CSN. The CSN is a value uniquely 114 assigned to each ISA card after the serial identification process 115 so that each card may be individually selected during a Wake[CSN] 116 command. This register is read/write. 117 ***/ 118 119 #define PNP_SET_LDN 0x07 120 /*** 121 Selects the current logical device. All reads and writes of memory, 122 I/O, interrupt and DMA configuration information access the registers 123 of the logical device written here. In addition, the I/O Range 124 Check and Activate commands operate only on the selected logical 125 device. This register is read/write. If a card has only 1 logical 126 device, this location should be a read-only value of 0x00. 127 ***/ 128 129 /*** addresses 0x08 - 0x1F Card Level Reserved for future use ***/ 130 /*** addresses 0x20 - 0x2F Card Level, Vendor Defined ***/ 131 132 #define PNP_ACTIVATE 0x30 133 /*** 134 For each logical device there is one activate register that controls 135 whether or not the logical device is active on the ISA bus. Bit[0], 136 if set, activates the logical device. Bits[7:1] are reserved and 137 must return 0 on reads. This is a read/write register. Before a 138 logical device is activated, I/O range check must be disabled. 139 ***/ 140 141 #define PNP_IO_RANGE_CHECK 0x31 142 #define PNP_IO_RANGE_CHECK_ENABLE 0x02 143 #define PNP_IO_RANGE_CHECK_READ_AS_55 0x01 144 /*** 145 This register is used to perform a conflict check on the I/O port 146 range programmed for use by a logical device. 147 148 Bit[7:2] Reserved and must return 0 on reads 149 Bit[1] Enable I/O Range check, if set then I/O Range Check 150 is enabled. I/O range check is only valid when the logical 151 device is inactive. 152 153 Bit[0], if set, forces the logical device to respond to I/O reads 154 of the logical device's assigned I/O range with a 0x55 when I/O 155 range check is in operation. If clear, the logical device drives 156 0xAA. This register is read/write. 157 ***/ 158 159 /*** addr 0x32 - 0x37 Logical Device Control Reserved for future use ***/ 160 /*** addr 0x38 - 0x3F Logical Device Control Vendor Define ***/ 161 162 #define PNP_MEM_BASE_HIGH(i) (0x40 + 8*(i)) 163 #define PNP_MEM_BASE_LOW(i) (0x41 + 8*(i)) 164 #define PNP_MEM_CONTROL(i) (0x42 * 8*(i)) 165 #define PNP_MEM_CONTROL_16BIT 0x2 166 #define PNP_MEM_CONTROL_LIMIT 0x1 167 #define PNP_MEM_RANGE_HIGH(i) (0x43 + 8*(i)) 168 #define PNP_MEM_RANGE_LOW(i) (0x44 + 8*(i)) 169 /*** 170 Four memory resource registers per range, four ranges. 171 Fill with 0 if no ranges are enabled. 172 173 Offset 0: RW Memory base address bits[23:16] 174 Offset 1: RW Memory base address bits[15:8] 175 Offset 2: Memory control 176 Bit[1] specifies 8/16-bit control. This bit is set to indicate 177 16-bit memory, and cleared to indicate 8-bit memory. 178 Bit[0], if cleared, indicates the next field can be used as a range 179 length for decode (implies range length and base alignment of memory 180 descriptor are equal). 181 Bit[0], if set, indicates the next field is the upper limit for 182 the address. - - Bit[0] is read-only. 183 Offset 3: RW upper limit or range len, bits[23:16] 184 Offset 4: RW upper limit or range len, bits[15:8] 185 Offset 5-Offset 7: filler, unused. 186 ***/ 187 188 #define PNP_IO_BASE_HIGH(i) (0x60 + 2*(i)) 189 #define PNP_IO_BASE_LOW(i) (0x61 + 2*(i)) 190 /*** 191 Eight ranges, two bytes per range. 192 Offset 0: I/O port base address bits[15:8] 193 Offset 1: I/O port base address bits[7:0] 194 ***/ 195 196 #define PNP_IRQ_LEVEL(i) (0x70 + 2*(i)) 197 #define PNP_IRQ_TYPE(i) (0x71 + 2*(i)) 198 /*** 199 Two entries, two bytes per entry. 200 Offset 0: RW interrupt level (1..15, 0=unused). 201 Offset 1: Bit[1]: level(1:hi, 0:low), 202 Bit[0]: type (1:level, 0:edge) 203 byte 1 can be readonly if 1 type of int is used. 204 ***/ 205 206 #define PNP_DMA_CHANNEL(i) (0x74 + 1*(i)) 207 /*** 208 Two entries, one byte per entry. Bits[2:0] select 209 which DMA channel is in use for DMA 0. Zero selects DMA channel 210 0, seven selects DMA channel 7. DMA channel 4, the cascade channel 211 is used to indicate no DMA channel is active. 212 ***/ 213 214 /*** 32-bit memory accesses are at 0x76 ***/ 215 216 /* Macros to parse Resource IDs */ 217 #define PNP_RES_TYPE(a) (a >> 7) 218 #define PNP_SRES_NUM(a) (a >> 3) 219 #define PNP_SRES_LEN(a) (a & 0x07) 220 #define PNP_LRES_NUM(a) (a & 0x7f) 221 222 /* Small Resource Item names */ 223 #define PNP_TAG_VERSION 0x1 224 #define PNP_TAG_LOGICAL_DEVICE 0x2 225 #define PNP_TAG_COMPAT_DEVICE 0x3 226 #define PNP_TAG_IRQ_FORMAT 0x4 227 #define PNP_TAG_DMA_FORMAT 0x5 228 #define PNP_TAG_START_DEPENDANT 0x6 229 #define PNP_TAG_END_DEPENDANT 0x7 230 #define PNP_TAG_IO_RANGE 0x8 231 #define PNP_TAG_IO_FIXED 0x9 232 #define PNP_TAG_RESERVED 0xa-0xd 233 #define PNP_TAG_VENDOR 0xe 234 #define PNP_TAG_END 0xf 235 236 /* Large Resource Item names */ 237 #define PNP_TAG_MEMORY_RANGE 0x1 238 #define PNP_TAG_ID_ANSI 0x2 239 #define PNP_TAG_ID_UNICODE 0x3 240 #define PNP_TAG_LARGE_VENDOR 0x4 241 #define PNP_TAG_MEMORY32_RANGE 0x5 242 #define PNP_TAG_MEMORY32_FIXED 0x6 243 #define PNP_TAG_LARGE_RESERVED 0x7-0x7f 244 245 #endif /* !_ISA_PNPREG_H_ */ 246