1/* 2 * P3041 Silicon Device Tree Source 3 * 4 * Copyright 2010-2011 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34/* $FreeBSD$ */ 35 36/dts-v1/; 37 38/ { 39 compatible = "fsl,P3041"; 40 #address-cells = <2>; 41 #size-cells = <2>; 42 interrupt-parent = <&mpic>; 43 44 aliases { 45 ccsr = &soc; 46 dcsr = &dcsr; 47 48 ethernet0 = &enet0; 49 ethernet1 = &enet1; 50 ethernet2 = &enet2; 51 ethernet3 = &enet3; 52 ethernet4 = &enet4; 53 ethernet5 = &enet5; 54 serial0 = &serial0; 55 serial1 = &serial1; 56 serial2 = &serial2; 57 serial3 = &serial3; 58 pci0 = &pci0; 59 pci1 = &pci1; 60 pci2 = &pci2; 61 pci3 = &pci3; 62 usb0 = &usb0; 63 usb1 = &usb1; 64 dma0 = &dma0; 65 dma1 = &dma1; 66 bman = &bman; 67 qman = &qman; 68 pme = &pme; 69 rman = &rman; 70 sdhc = &sdhc; 71 msi0 = &msi0; 72 msi1 = &msi1; 73 msi2 = &msi2; 74 75 crypto = &crypto; 76 sec_jr0 = &sec_jr0; 77 sec_jr1 = &sec_jr1; 78 sec_jr2 = &sec_jr2; 79 sec_jr3 = &sec_jr3; 80 rtic_a = &rtic_a; 81 rtic_b = &rtic_b; 82 rtic_c = &rtic_c; 83 rtic_d = &rtic_d; 84 sec_mon = &sec_mon; 85 86 fman0 = &fman0; 87 fman0_oh0 = &fman0_oh0; 88 fman0_oh1 = &fman0_oh1; 89 fman0_oh2 = &fman0_oh2; 90 fman0_oh3 = &fman0_oh3; 91 fman0_oh4 = &fman0_oh4; 92 fman0_oh5 = &fman0_oh5; 93 fman0_oh6 = &fman0_oh6; 94 fman0_rx0 = &fman0_rx0; 95 fman0_rx1 = &fman0_rx1; 96 fman0_rx2 = &fman0_rx2; 97 fman0_rx3 = &fman0_rx3; 98 fman0_rx4 = &fman0_rx4; 99 fman0_rx5 = &fman0_rx5; 100 }; 101 102 cpus { 103 #address-cells = <1>; 104 #size-cells = <0>; 105 106 cpu0: PowerPC,e500mc@0 { 107 device_type = "cpu"; 108 reg = <0>; 109 bus-frequency = <749999996>; 110 next-level-cache = <&L2_0>; 111 L2_0: l2-cache { 112 next-level-cache = <&cpc>; 113 }; 114 }; 115 cpu1: PowerPC,e500mc@1 { 116 device_type = "cpu"; 117 reg = <1>; 118 next-level-cache = <&L2_1>; 119 L2_1: l2-cache { 120 next-level-cache = <&cpc>; 121 }; 122 }; 123 cpu2: PowerPC,e500mc@2 { 124 device_type = "cpu"; 125 reg = <2>; 126 next-level-cache = <&L2_2>; 127 L2_2: l2-cache { 128 next-level-cache = <&cpc>; 129 }; 130 }; 131 cpu3: PowerPC,e500mc@3 { 132 device_type = "cpu"; 133 reg = <3>; 134 next-level-cache = <&L2_3>; 135 L2_3: l2-cache { 136 next-level-cache = <&cpc>; 137 }; 138 }; 139 }; 140 141 dcsr: dcsr@f00000000 { 142 #address-cells = <1>; 143 #size-cells = <1>; 144 compatible = "fsl,dcsr", "simple-bus"; 145 146 dcsr-epu@0 { 147 compatible = "fsl,dcsr-epu"; 148 interrupts = <52 2 0 0 149 84 2 0 0 150 85 2 0 0>; 151 interrupt-parent = <&mpic>; 152 reg = <0x0 0x1000>; 153 }; 154 dcsr-npc { 155 compatible = "fsl,dcsr-npc"; 156 reg = <0x1000 0x1000 0x1000000 0x8000>; 157 }; 158 dcsr-nxc@2000 { 159 compatible = "fsl,dcsr-nxc"; 160 reg = <0x2000 0x1000>; 161 }; 162 dcsr-corenet { 163 compatible = "fsl,dcsr-corenet"; 164 reg = <0x8000 0x1000 0xB0000 0x1000>; 165 }; 166 dcsr-dpaa@9000 { 167 compatible = "fsl,p43041-dcsr-dpaa", "fsl,dcsr-dpaa"; 168 reg = <0x9000 0x1000>; 169 }; 170 dcsr-ocn@11000 { 171 compatible = "fsl,p43041-dcsr-ocn", "fsl,dcsr-ocn"; 172 reg = <0x11000 0x1000>; 173 }; 174 dcsr-ddr@12000 { 175 compatible = "fsl,dcsr-ddr"; 176 dev-handle = <&ddr>; 177 reg = <0x12000 0x1000>; 178 }; 179 dcsr-nal@18000 { 180 compatible = "fsl,p43041-dcsr-nal", "fsl,dcsr-nal"; 181 reg = <0x18000 0x1000>; 182 }; 183 dcsr-rcpm@22000 { 184 compatible = "fsl,p43041-dcsr-rcpm", "fsl,dcsr-rcpm"; 185 reg = <0x22000 0x1000>; 186 }; 187 dcsr-cpu-sb-proxy@40000 { 188 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 189 cpu-handle = <&cpu0>; 190 reg = <0x40000 0x1000>; 191 }; 192 dcsr-cpu-sb-proxy@41000 { 193 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 194 cpu-handle = <&cpu1>; 195 reg = <0x41000 0x1000>; 196 }; 197 dcsr-cpu-sb-proxy@42000 { 198 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 199 cpu-handle = <&cpu2>; 200 reg = <0x42000 0x1000>; 201 }; 202 dcsr-cpu-sb-proxy@43000 { 203 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy"; 204 cpu-handle = <&cpu3>; 205 reg = <0x43000 0x1000>; 206 }; 207 }; 208 209 bman-portals@ff4000000 { 210 #address-cells = <0x1>; 211 #size-cells = <0x1>; 212 compatible = "fsl,bman-portals"; 213 ranges = <0x0 0xf 0xfde00000 0x200000>; 214 bman-portal@0 { 215 cell-index = <0x0>; 216 compatible = "fsl,p3041-bman-portal", "fsl,bman-portal"; 217 reg = <0x0 0x4000 0x100000 0x1000>; 218 interrupts = <105 2 0 0>; 219 }; 220 bman-portal@4000 { 221 cell-index = <0x1>; 222 compatible = "fsl,p3041-bman-portal", "fsl,bman-portal"; 223 reg = <0x4000 0x4000 0x101000 0x1000>; 224 interrupts = <107 2 0 0>; 225 }; 226 bman-portal@8000 { 227 cell-index = <2>; 228 compatible = "fsl,p3041-bman-portal", "fsl,bman-portal"; 229 reg = <0x8000 0x4000 0x102000 0x1000>; 230 interrupts = <109 2 0 0>; 231 }; 232 bman-portal@c000 { 233 cell-index = <0x3>; 234 compatible = "fsl,p3041-bman-portal", "fsl,bman-portal"; 235 reg = <0xc000 0x4000 0x103000 0x1000>; 236 interrupts = <111 2 0 0>; 237 }; 238 bman-portal@10000 { 239 cell-index = <0x4>; 240 compatible = "fsl,p3041-bman-portal", "fsl,bman-portal"; 241 reg = <0x10000 0x4000 0x104000 0x1000>; 242 interrupts = <113 2 0 0>; 243 }; 244 bman-portal@14000 { 245 cell-index = <0x5>; 246 compatible = "fsl,p3041-bman-portal", "fsl,bman-portal"; 247 reg = <0x14000 0x4000 0x105000 0x1000>; 248 interrupts = <115 2 0 0>; 249 }; 250 bman-portal@18000 { 251 cell-index = <0x6>; 252 compatible = "fsl,p3041-bman-portal", "fsl,bman-portal"; 253 reg = <0x18000 0x4000 0x106000 0x1000>; 254 interrupts = <117 2 0 0>; 255 }; 256 bman-portal@1c000 { 257 cell-index = <0x7>; 258 compatible = "fsl,p3041-bman-portal", "fsl,bman-portal"; 259 reg = <0x1c000 0x4000 0x107000 0x1000>; 260 interrupts = <119 2 0 0>; 261 }; 262 bman-portal@20000 { 263 cell-index = <0x8>; 264 compatible = "fsl,p3041-bman-portal", "fsl,bman-portal"; 265 reg = <0x20000 0x4000 0x108000 0x1000>; 266 interrupts = <121 2 0 0>; 267 }; 268 bman-portal@24000 { 269 cell-index = <0x9>; 270 compatible = "fsl,p3041-bman-portal", "fsl,bman-portal"; 271 reg = <0x24000 0x4000 0x109000 0x1000>; 272 interrupts = <123 2 0 0>; 273 }; 274 275 buffer-pool@0 { 276 compatible = "fsl,p3041-bpool", "fsl,bpool"; 277 fsl,bpid = <0>; 278 fsl,bpool-cfg = <0 0x100 0 1 0 0x100>; 279 }; 280 }; 281 282 qman-portals@ff4200000 { 283 #address-cells = <0x1>; 284 #size-cells = <0x1>; 285 compatible = "fsl,qman-portals"; 286 ranges = <0x0 0xf 0xfdc00000 0x200000>; 287 qportal0: qman-portal@0 { 288 cell-index = <0x0>; 289 compatible = "fsl,p3041-qman-portal", "fsl,qman-portal"; 290 reg = <0x0 0x4000 0x100000 0x1000>; 291 interrupts = <104 0x2 0 0>; 292 fsl,qman-channel-id = <0x0>; 293 }; 294 295 qportal1: qman-portal@4000 { 296 cell-index = <0x1>; 297 compatible = "fsl,p3041-qman-portal", "fsl,qman-portal"; 298 reg = <0x4000 0x4000 0x101000 0x1000>; 299 interrupts = <106 0x2 0 0>; 300 fsl,qman-channel-id = <0x1>; 301 }; 302 303 qportal2: qman-portal@8000 { 304 cell-index = <0x2>; 305 compatible = "fsl,p3041-qman-portal", "fsl,qman-portal"; 306 reg = <0x8000 0x4000 0x102000 0x1000>; 307 interrupts = <108 0x2 0 0>; 308 fsl,qman-channel-id = <0x2>; 309 }; 310 311 qportal3: qman-portal@c000 { 312 cell-index = <0x3>; 313 compatible = "fsl,p3041-qman-portal", "fsl,qman-portal"; 314 reg = <0xc000 0x4000 0x103000 0x1000>; 315 interrupts = <110 0x2 0 0>; 316 fsl,qman-channel-id = <0x3>; 317 }; 318 319 qportal4: qman-portal@10000 { 320 cell-index = <0x4>; 321 compatible = "fsl,p3041-qman-portal", "fsl,qman-portal"; 322 reg = <0x10000 0x4000 0x104000 0x1000>; 323 interrupts = <112 0x2 0 0>; 324 fsl,qman-channel-id = <0x4>; 325 }; 326 327 qportal5: qman-portal@14000 { 328 cell-index = <0x5>; 329 compatible = "fsl,p3041-qman-portal", "fsl,qman-portal"; 330 reg = <0x14000 0x4000 0x105000 0x1000>; 331 interrupts = <114 0x2 0 0>; 332 fsl,qman-channel-id = <0x5>; 333 }; 334 335 qportal6: qman-portal@18000 { 336 cell-index = <0x6>; 337 compatible = "fsl,p3041-qman-portal", "fsl,qman-portal"; 338 reg = <0x18000 0x4000 0x106000 0x1000>; 339 interrupts = <116 0x2 0 0>; 340 fsl,qman-channel-id = <0x6>; 341 }; 342 343 qportal7: qman-portal@1c000 { 344 cell-index = <0x7>; 345 compatible = "fsl,p3041-qman-portal", "fsl,qman-portal"; 346 reg = <0x1c000 0x4000 0x107000 0x1000>; 347 interrupts = <118 0x2 0 0>; 348 fsl,qman-channel-id = <0x7>; 349 }; 350 351 qportal8: qman-portal@20000 { 352 cell-index = <0x8>; 353 compatible = "fsl,p3041-qman-portal", "fsl,qman-portal"; 354 reg = <0x20000 0x4000 0x108000 0x1000>; 355 interrupts = <120 0x2 0 0>; 356 fsl,qman-channel-id = <0x8>; 357 }; 358 359 qportal9: qman-portal@24000 { 360 cell-index = <0x9>; 361 compatible = "fsl,p3041-qman-portal", "fsl,qman-portal"; 362 reg = <0x24000 0x4000 0x109000 0x1000>; 363 interrupts = <122 0x2 0 0>; 364 fsl,qman-channel-id = <0x9>; 365 }; 366 367 qpool1: qman-pool@1 { 368 cell-index = <1>; 369 compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel"; 370 fsl,qman-channel-id = <0x21>; 371 }; 372 373 qpool2: qman-pool@2 { 374 cell-index = <2>; 375 compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel"; 376 fsl,qman-channel-id = <0x22>; 377 }; 378 379 qpool3: qman-pool@3 { 380 cell-index = <3>; 381 compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel"; 382 fsl,qman-channel-id = <0x23>; 383 }; 384 385 qpool4: qman-pool@4 { 386 cell-index = <4>; 387 compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel"; 388 fsl,qman-channel-id = <0x24>; 389 }; 390 391 qpool5: qman-pool@5 { 392 cell-index = <5>; 393 compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel"; 394 fsl,qman-channel-id = <0x25>; 395 }; 396 397 qpool6: qman-pool@6 { 398 cell-index = <6>; 399 compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel"; 400 fsl,qman-channel-id = <0x26>; 401 }; 402 403 qpool7: qman-pool@7 { 404 cell-index = <7>; 405 compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel"; 406 fsl,qman-channel-id = <0x27>; 407 }; 408 409 qpool8: qman-pool@8 { 410 cell-index = <8>; 411 compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel"; 412 fsl,qman-channel-id = <0x28>; 413 }; 414 415 qpool9: qman-pool@9 { 416 cell-index = <9>; 417 compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel"; 418 fsl,qman-channel-id = <0x29>; 419 }; 420 421 qpool10: qman-pool@10 { 422 cell-index = <10>; 423 compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel"; 424 fsl,qman-channel-id = <0x2a>; 425 }; 426 427 qpool11: qman-pool@11 { 428 cell-index = <11>; 429 compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel"; 430 fsl,qman-channel-id = <0x2b>; 431 }; 432 433 qpool12: qman-pool@12 { 434 cell-index = <12>; 435 compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel"; 436 fsl,qman-channel-id = <0x2c>; 437 }; 438 439 qpool13: qman-pool@13 { 440 cell-index = <13>; 441 compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel"; 442 fsl,qman-channel-id = <0x2d>; 443 }; 444 445 qpool14: qman-pool@14 { 446 cell-index = <14>; 447 compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel"; 448 fsl,qman-channel-id = <0x2e>; 449 }; 450 451 qpool15: qman-pool@15 { 452 cell-index = <15>; 453 compatible = "fsl,p3041-qman-pool-channel", "fsl,qman-pool-channel"; 454 fsl,qman-channel-id = <0x2f>; 455 }; 456 }; 457 458 soc: soc@ffe000000 { 459 #address-cells = <1>; 460 #size-cells = <1>; 461 device_type = "soc"; 462 compatible = "simple-bus"; 463 464 bus-frequency = <0>; // Filled out by kernel. 465 466 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; 467 reg = <0xf 0xfe000000 0 0x00001000>; 468 469 soc-sram-error { 470 compatible = "fsl,soc-sram-error"; 471 interrupts = <16 2 1 29>; 472 }; 473 474 corenet-law@0 { 475 compatible = "fsl,corenet-law"; 476 reg = <0x0 0x1000>; 477 fsl,num-laws = <32>; 478 }; 479 480 ddr: memory-controller@8000 { 481 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller"; 482 reg = <0x8000 0x1000>; 483 interrupts = <16 2 1 23>; 484 }; 485 486 cpc: l3-cache-controller@10000 { 487 compatible = "fsl,p3041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache"; 488 reg = <0x10000 0x1000>; 489 interrupts = <16 2 1 27>; 490 }; 491 492 corenet-cf@18000 { 493 compatible = "fsl,corenet-cf"; 494 reg = <0x18000 0x1000>; 495 interrupts = <16 2 1 31>; 496 fsl,ccf-num-csdids = <32>; 497 fsl,ccf-num-snoopids = <32>; 498 }; 499 500 iommu@20000 { 501 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 502 reg = <0x20000 0x4000>; 503 interrupts = < 504 24 2 0 0 505 16 2 1 30>; 506 }; 507 508 mpic: pic@40000 { 509 clock-frequency = <0>; 510 interrupt-controller; 511 #address-cells = <0>; 512 #interrupt-cells = <4>; 513 reg = <0x40000 0x40000>; 514 compatible = "fsl,mpic", "chrp,open-pic"; 515 device_type = "open-pic"; 516 }; 517 518 msi0: msi@41600 { 519 compatible = "fsl,mpic-msi"; 520 reg = <0x41600 0x200>; 521 msi-available-ranges = <0 0x100>; 522 interrupts = < 523 0xe0 0 0 0 524 0xe1 0 0 0 525 0xe2 0 0 0 526 0xe3 0 0 0 527 0xe4 0 0 0 528 0xe5 0 0 0 529 0xe6 0 0 0 530 0xe7 0 0 0>; 531 }; 532 533 msi1: msi@41800 { 534 compatible = "fsl,mpic-msi"; 535 reg = <0x41800 0x200>; 536 msi-available-ranges = <0 0x100>; 537 interrupts = < 538 0xe8 0 0 0 539 0xe9 0 0 0 540 0xea 0 0 0 541 0xeb 0 0 0 542 0xec 0 0 0 543 0xed 0 0 0 544 0xee 0 0 0 545 0xef 0 0 0>; 546 }; 547 548 msi2: msi@41a00 { 549 compatible = "fsl,mpic-msi"; 550 reg = <0x41a00 0x200>; 551 msi-available-ranges = <0 0x100>; 552 interrupts = < 553 0xf0 0 0 0 554 0xf1 0 0 0 555 0xf2 0 0 0 556 0xf3 0 0 0 557 0xf4 0 0 0 558 0xf5 0 0 0 559 0xf6 0 0 0 560 0xf7 0 0 0>; 561 }; 562 563 guts: global-utilities@e0000 { 564 compatible = "fsl,qoriq-device-config-1.0"; 565 reg = <0xe0000 0xe00>; 566 fsl,has-rstcr; 567 #sleep-cells = <1>; 568 fsl,liodn-bits = <12>; 569 }; 570 571 pins: global-utilities@e0e00 { 572 compatible = "fsl,qoriq-pin-control-1.0"; 573 reg = <0xe0e00 0x200>; 574 #sleep-cells = <2>; 575 }; 576 577 clockgen: global-utilities@e1000 { 578 compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0"; 579 reg = <0xe1000 0x1000>; 580 clock-frequency = <0>; 581 }; 582 583 rcpm: global-utilities@e2000 { 584 compatible = "fsl,qoriq-rcpm-1.0"; 585 reg = <0xe2000 0x1000>; 586 #sleep-cells = <1>; 587 }; 588 589 sfp: sfp@e8000 { 590 compatible = "fsl,p3041-sfp", "fsl,qoriq-sfp-1.0"; 591 reg = <0xe8000 0x1000>; 592 }; 593 594 serdes: serdes@ea000 { 595 compatible = "fsl,p3041-serdes"; 596 reg = <0xea000 0x1000>; 597 }; 598 599 dma0: dma@100300 { 600 #address-cells = <1>; 601 #size-cells = <1>; 602 compatible = "fsl,p3041-dma", "fsl,eloplus-dma"; 603 reg = <0x100300 0x4>; 604 ranges = <0x0 0x100100 0x200>; 605 cell-index = <0>; 606 dma-channel@0 { 607 compatible = "fsl,p3041-dma-channel", 608 "fsl,eloplus-dma-channel"; 609 reg = <0x0 0x80>; 610 cell-index = <0>; 611 interrupts = <28 2 0 0>; 612 }; 613 dma-channel@80 { 614 compatible = "fsl,p3041-dma-channel", 615 "fsl,eloplus-dma-channel"; 616 reg = <0x80 0x80>; 617 cell-index = <1>; 618 interrupts = <29 2 0 0>; 619 }; 620 dma-channel@100 { 621 compatible = "fsl,p3041-dma-channel", 622 "fsl,eloplus-dma-channel"; 623 reg = <0x100 0x80>; 624 cell-index = <2>; 625 interrupts = <30 2 0 0>; 626 }; 627 dma-channel@180 { 628 compatible = "fsl,p3041-dma-channel", 629 "fsl,eloplus-dma-channel"; 630 reg = <0x180 0x80>; 631 cell-index = <3>; 632 interrupts = <31 2 0 0>; 633 }; 634 }; 635 636 dma1: dma@101300 { 637 #address-cells = <1>; 638 #size-cells = <1>; 639 compatible = "fsl,p3041-dma", "fsl,eloplus-dma"; 640 reg = <0x101300 0x4>; 641 ranges = <0x0 0x101100 0x200>; 642 cell-index = <1>; 643 dma-channel@0 { 644 compatible = "fsl,p3041-dma-channel", 645 "fsl,eloplus-dma-channel"; 646 reg = <0x0 0x80>; 647 cell-index = <0>; 648 interrupts = <32 2 0 0>; 649 }; 650 dma-channel@80 { 651 compatible = "fsl,p3041-dma-channel", 652 "fsl,eloplus-dma-channel"; 653 reg = <0x80 0x80>; 654 cell-index = <1>; 655 interrupts = <33 2 0 0>; 656 }; 657 dma-channel@100 { 658 compatible = "fsl,p3041-dma-channel", 659 "fsl,eloplus-dma-channel"; 660 reg = <0x100 0x80>; 661 cell-index = <2>; 662 interrupts = <34 2 0 0>; 663 }; 664 dma-channel@180 { 665 compatible = "fsl,p3041-dma-channel", 666 "fsl,eloplus-dma-channel"; 667 reg = <0x180 0x80>; 668 cell-index = <3>; 669 interrupts = <35 2 0 0>; 670 }; 671 }; 672 673 spi@110000 { 674 #address-cells = <1>; 675 #size-cells = <0>; 676 compatible = "fsl,p3041-espi", "fsl,mpc8536-espi"; 677 reg = <0x110000 0x1000>; 678 interrupts = <53 0x2 0 0>; 679 fsl,espi-num-chipselects = <4>; 680 }; 681 682 sdhc: sdhc@114000 { 683 compatible = "fsl,p3041-esdhc", "fsl,esdhc"; 684 reg = <0x114000 0x1000>; 685 interrupts = <48 2 0 0>; 686 sdhci,auto-cmd12; 687 clock-frequency = <0>; 688 }; 689 690 i2c@118000 { 691 #address-cells = <1>; 692 #size-cells = <0>; 693 cell-index = <0>; 694 compatible = "fsl-i2c"; 695 reg = <0x118000 0x100>; 696 interrupts = <38 2 0 0>; 697 dfsrr; 698 }; 699 700 i2c@118100 { 701 #address-cells = <1>; 702 #size-cells = <0>; 703 cell-index = <1>; 704 compatible = "fsl-i2c"; 705 reg = <0x118100 0x100>; 706 interrupts = <38 2 0 0>; 707 dfsrr; 708 }; 709 710 i2c@119000 { 711 #address-cells = <1>; 712 #size-cells = <0>; 713 cell-index = <2>; 714 compatible = "fsl-i2c"; 715 reg = <0x119000 0x100>; 716 interrupts = <39 2 0 0>; 717 dfsrr; 718 }; 719 720 i2c@119100 { 721 #address-cells = <1>; 722 #size-cells = <0>; 723 cell-index = <3>; 724 compatible = "fsl-i2c"; 725 reg = <0x119100 0x100>; 726 interrupts = <39 2 0 0>; 727 dfsrr; 728 }; 729 730 serial0: serial@11c500 { 731 cell-index = <0>; 732 device_type = "serial"; 733 compatible = "ns16550"; 734 reg = <0x11c500 0x100>; 735 clock-frequency = <0>; 736 interrupts = <36 2 0 0>; 737 }; 738 739 serial1: serial@11c600 { 740 cell-index = <1>; 741 device_type = "serial"; 742 compatible = "ns16550"; 743 reg = <0x11c600 0x100>; 744 clock-frequency = <0>; 745 interrupts = <36 2 0 0>; 746 }; 747 748 serial2: serial@11d500 { 749 cell-index = <2>; 750 device_type = "serial"; 751 compatible = "ns16550"; 752 reg = <0x11d500 0x100>; 753 clock-frequency = <0>; 754 interrupts = <37 2 0 0>; 755 }; 756 757 serial3: serial@11d600 { 758 cell-index = <3>; 759 device_type = "serial"; 760 compatible = "ns16550"; 761 reg = <0x11d600 0x100>; 762 clock-frequency = <0>; 763 interrupts = <37 2 0 0>; 764 }; 765 766 gpio0: gpio@130000 { 767 compatible = "fsl,p3041-gpio", "fsl,qoriq-gpio"; 768 reg = <0x130000 0x1000>; 769 interrupts = <55 2 0 0>; 770 #gpio-cells = <2>; 771 gpio-controller; 772 }; 773 774 rman: rman@1e0000 { 775 compatible = "fsl,rman"; 776 #address-cells = <1>; 777 #size-cells = <1>; 778 ranges = <0x0 0x1e0000 0x20000>; 779 reg = <0x1e0000 0x20000>; 780 interrupts = <16 2 1 11>; /* err_irq */ 781 fsl,qman-channels-id = <0x62 0x63>; 782 783 inbound-block@0 { 784 compatible = "fsl,rman-inbound-block"; 785 reg = <0x0 0x800>; 786 }; 787 global-cfg@b00 { 788 compatible = "fsl,rman-global-cfg"; 789 reg = <0xb00 0x500>; 790 }; 791 inbound-block@1000 { 792 compatible = "fsl,rman-inbound-block"; 793 reg = <0x1000 0x800>; 794 }; 795 inbound-block@2000 { 796 compatible = "fsl,rman-inbound-block"; 797 reg = <0x2000 0x800>; 798 }; 799 inbound-block@3000 { 800 compatible = "fsl,rman-inbound-block"; 801 reg = <0x3000 0x800>; 802 }; 803 }; 804 805 usb0: usb@210000 { 806 compatible = "fsl,p3041-usb2-mph", 807 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; 808 reg = <0x210000 0x1000>; 809 #address-cells = <1>; 810 #size-cells = <0>; 811 interrupts = <44 0x2 0 0>; 812 phy_type = "utmi"; 813 port0; 814 }; 815 816 usb1: usb@211000 { 817 compatible = "fsl,p3041-usb2-dr", 818 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; 819 reg = <0x211000 0x1000>; 820 #address-cells = <1>; 821 #size-cells = <0>; 822 interrupts = <45 0x2 0 0>; 823 dr_mode = "host"; 824 phy_type = "utmi"; 825 }; 826 827 sata@220000 { 828 compatible = "fsl,p3041-sata", "fsl,pq-sata-v2"; 829 reg = <0x220000 0x1000>; 830 interrupts = <68 0x2 0 0>; 831 }; 832 833 sata@221000 { 834 compatible = "fsl,p3041-sata", "fsl,pq-sata-v2"; 835 reg = <0x221000 0x1000>; 836 interrupts = <69 0x2 0 0>; 837 }; 838 839 crypto: crypto@300000 { 840 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0"; 841 #address-cells = <1>; 842 #size-cells = <1>; 843 reg = <0x300000 0x10000>; 844 ranges = <0 0x300000 0x10000>; 845 interrupts = <92 2 0 0>; 846 847 sec_jr0: jr@1000 { 848 compatible = "fsl,sec-v4.2-job-ring", 849 "fsl,sec-v4.0-job-ring"; 850 reg = <0x1000 0x1000>; 851 interrupts = <88 2 0 0>; 852 }; 853 854 sec_jr1: jr@2000 { 855 compatible = "fsl,sec-v4.2-job-ring", 856 "fsl,sec-v4.0-job-ring"; 857 reg = <0x2000 0x1000>; 858 interrupts = <89 2 0 0>; 859 }; 860 861 sec_jr2: jr@3000 { 862 compatible = "fsl,sec-v4.2-job-ring", 863 "fsl,sec-v4.0-job-ring"; 864 reg = <0x3000 0x1000>; 865 interrupts = <90 2 0 0>; 866 }; 867 868 sec_jr3: jr@4000 { 869 compatible = "fsl,sec-v4.2-job-ring", 870 "fsl,sec-v4.0-job-ring"; 871 reg = <0x4000 0x1000>; 872 interrupts = <91 2 0 0>; 873 }; 874 875 rtic@6000 { 876 compatible = "fsl,sec-v4.2-rtic", 877 "fsl,sec-v4.0-rtic"; 878 #address-cells = <1>; 879 #size-cells = <1>; 880 reg = <0x6000 0x100>; 881 ranges = <0x0 0x6100 0xe00>; 882 883 rtic_a: rtic-a@0 { 884 compatible = "fsl,sec-v4.2-rtic-memory", 885 "fsl,sec-v4.0-rtic-memory"; 886 reg = <0x00 0x20 0x100 0x80>; 887 }; 888 889 rtic_b: rtic-b@20 { 890 compatible = "fsl,sec-v4.2-rtic-memory", 891 "fsl,sec-v4.0-rtic-memory"; 892 reg = <0x20 0x20 0x200 0x80>; 893 }; 894 895 rtic_c: rtic-c@40 { 896 compatible = "fsl,sec-v4.2-rtic-memory", 897 "fsl,sec-v4.0-rtic-memory"; 898 reg = <0x40 0x20 0x300 0x80>; 899 }; 900 901 rtic_d: rtic-d@60 { 902 compatible = "fsl,sec-v4.2-rtic-memory", 903 "fsl,sec-v4.0-rtic-memory"; 904 reg = <0x60 0x20 0x500 0x80>; 905 }; 906 }; 907 }; 908 909 sec_mon: sec_mon@314000 { 910 compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon"; 911 reg = <0x314000 0x1000>; 912 interrupts = <93 2 0 0>; 913 }; 914 915 pme: pme@316000 { 916 compatible = "fsl,pme"; 917 reg = <0x316000 0x10000>; 918 /* "fsl,pme-pdsr = <0x0 0x23000000 0x0 0x01000000>; */ 919 /* "fsl,pme-sre = <0x0 0x24000000 0x0 0x00a00000>; */ 920 interrupts = <16 2 1 5>; 921 }; 922 923 qman: qman@318000 { 924 compatible = "fsl,p3041-qman", "fsl,qman"; 925 reg = <0x318000 0x1000>; 926 interrupts = <16 2 1 3>; 927 /* Commented out, use default allocation */ 928 /* "fsl,qman-fqd = <0x0 0x20000000 0x0 0x01000000>; */ 929 /* "fsl,qman-pfdr = <0x0 0x21000000 0x0 0x01000000>; */ 930 }; 931 932 bman: bman@31a000 { 933 compatible = "fsl,p3041-bman", "fsl,bman"; 934 reg = <0x31a000 0x1000>; 935 interrupts = <16 2 1 2>; 936 /* Same as "fsl,qman-*, use default allocation */ 937 /* "fsl,bman-fbpr = <0x0 0x22000000 0x0 0x01000000>; */ 938 }; 939 940 fman0: fman@400000 { 941 #address-cells = <1>; 942 #size-cells = <1>; 943 cell-index = <0>; 944 compatible = "fsl,p3041-fman", "fsl,fman", "simple-bus"; 945 ranges = <0 0x400000 0x100000>; 946 reg = <0x400000 0x100000>; 947 clock-frequency = <0>; 948 interrupts = < 949 96 2 0 0 950 16 2 1 1>; 951 952 cc@0 { 953 compatible = "fsl,p3041-fman-cc", "fsl,fman-cc"; 954 }; 955 956 parser@c7000 { 957 compatible = "fsl,p3041-fman-parser", "fsl,fman-parser"; 958 reg = <0xc7000 0x1000>; 959 }; 960 961 keygen@c1000 { 962 compatible = "fsl,p3041-fman-keygen", "fsl,fman-keygen"; 963 reg = <0xc1000 0x1000>; 964 }; 965 966 policer@c0000 { 967 compatible = "fsl,p3041-fman-policer", "fsl,fman-policer"; 968 reg = <0xc0000 0x1000>; 969 }; 970 971 muram@0 { 972 compatible = "fsl,p3041-fman-muram", "fsl,fman-muram"; 973 reg = <0x0 0x28000>; 974 }; 975 976 bmi@80000 { 977 compatible = "fsl,p3041-fman-bmi", "fsl,fman-bmi"; 978 reg = <0x80000 0x400>; 979 }; 980 981 qmi@80400 { 982 compatible = "fsl,p3041-fman-qmi", "fsl,fman-qmi"; 983 reg = <0x80400 0x400>; 984 }; 985 986 fman0_rx0: port@88000 { 987 cell-index = <0>; 988 compatible = "fsl,p3041-fman-port-1g-rx", "fsl,fman-port-1g-rx", "fsl,fman-v2-port-rx"; 989 reg = <0x88000 0x1000>; 990 }; 991 fman0_rx1: port@89000 { 992 cell-index = <1>; 993 compatible = "fsl,p3041-fman-port-1g-rx", "fsl,fman-port-1g-rx", "fsl,fman-v2-port-rx"; 994 reg = <0x89000 0x1000>; 995 }; 996 fman0_rx2: port@8a000 { 997 cell-index = <2>; 998 compatible = "fsl,p3041-fman-port-1g-rx", "fsl,fman-port-1g-rx", "fsl,fman-v2-port-rx"; 999 reg = <0x8a000 0x1000>; 1000 }; 1001 fman0_rx3: port@8b000 { 1002 cell-index = <3>; 1003 compatible = "fsl,p3041-fman-port-1g-rx", "fsl,fman-port-1g-rx", "fsl,fman-v2-port-rx"; 1004 reg = <0x8b000 0x1000>; 1005 }; 1006 fman0_rx4: port@8c000 { 1007 cell-index = <4>; 1008 compatible = "fsl,p3041-fman-port-1g-rx", "fsl,fman-port-1g-rx", "fsl,fman-v2-port-rx"; 1009 reg = <0x8c000 0x1000>; 1010 }; 1011 fman0_rx5: port@90000 { 1012 cell-index = <0>; 1013 compatible = "fsl,p3041-fman-port-10g-rx", "fsl,fman-port-10g-rx"; 1014 reg = <0x90000 0x1000>; 1015 }; 1016 1017 fman0_tx5: port@b0000 { 1018 cell-index = <0>; 1019 compatible = "fsl,p3041-fman-port-10g-tx", "fsl,fman-port-10g-tx"; 1020 reg = <0xb0000 0x1000>; 1021 fsl,qman-channel-id = <0x40>; 1022 }; 1023 fman0_tx0: port@a8000 { 1024 cell-index = <0>; 1025 compatible = "fsl,p3041-fman-port-1g-tx", "fsl,fman-port-1g-tx", "fsl,fman-v2-port-tx"; 1026 reg = <0xa8000 0x1000>; 1027 fsl,qman-channel-id = <0x41>; 1028 }; 1029 fman0_tx1: port@a9000 { 1030 cell-index = <1>; 1031 compatible = "fsl,p3041-fman-port-1g-tx", "fsl,fman-port-1g-tx", "fsl,fman-v2-port-tx"; 1032 reg = <0xa9000 0x1000>; 1033 fsl,qman-channel-id = <0x42>; 1034 }; 1035 fman0_tx2: port@aa000 { 1036 cell-index = <2>; 1037 compatible = "fsl,p3041-fman-port-1g-tx", "fsl,fman-port-1g-tx", "fsl,fman-v2-port-tx"; 1038 reg = <0xaa000 0x1000>; 1039 fsl,qman-channel-id = <0x43>; 1040 }; 1041 fman0_tx3: port@ab000 { 1042 cell-index = <3>; 1043 compatible = "fsl,p3041-fman-port-1g-tx", "fsl,fman-port-1g-tx", "fsl,fman-v2-port-tx"; 1044 reg = <0xab000 0x1000>; 1045 fsl,qman-channel-id = <0x44>; 1046 }; 1047 fman0_tx4: port@ac000 { 1048 cell-index = <4>; 1049 compatible = "fsl,p3041-fman-port-1g-tx", "fsl,fman-port-1g-tx", "fsl,fman-v2-port-tx"; 1050 reg = <0xac000 0x1000>; 1051 fsl,qman-channel-id = <0x45>; 1052 }; 1053 1054 fman0_oh0: port@81000 { 1055 cell-index = <0>; 1056 compatible = "fsl,p3041-fman-port-oh", "fsl,fman-port-oh"; 1057 reg = <0x81000 0x1000>; 1058 fsl,qman-channel-id = <0x46>; 1059 }; 1060 fman0_oh1: port@82000 { 1061 cell-index = <1>; 1062 compatible = "fsl,p3041-fman-port-oh", "fsl,fman-port-oh"; 1063 reg = <0x82000 0x1000>; 1064 fsl,qman-channel-id = <0x47>; 1065 }; 1066 fman0_oh2: port@83000 { 1067 cell-index = <2>; 1068 compatible = "fsl,p3041-fman-port-oh", "fsl,fman-port-oh"; 1069 reg = <0x83000 0x1000>; 1070 fsl,qman-channel-id = <0x48>; 1071 }; 1072 fman0_oh3: port@84000 { 1073 cell-index = <3>; 1074 compatible = "fsl,p3041-fman-port-oh", "fsl,fman-port-oh"; 1075 reg = <0x84000 0x1000>; 1076 fsl,qman-channel-id = <0x49>; 1077 }; 1078 fman0_oh4: port@85000 { 1079 cell-index = <4>; 1080 compatible = "fsl,p3041-fman-port-oh", "fsl,fman-port-oh"; 1081 reg = <0x85000 0x1000>; 1082 fsl,qman-channel-id = <0x4a>; 1083 }; 1084 fman0_oh5: port@86000 { 1085 cell-index = <5>; 1086 compatible = "fsl,p3041-fman-port-oh", "fsl,fman-port-oh"; 1087 reg = <0x86000 0x1000>; 1088 fsl,qman-channel-id = <0x4b>; 1089 }; 1090 fman0_oh6: port@87000 { 1091 cell-index = <6>; 1092 compatible = "fsl,p3041-fman-port-oh", "fsl,fman-port-oh"; 1093 reg = <0x87000 0x1000>; 1094 }; 1095 1096 enet0: ethernet@e0000 { 1097 cell-index = <0>; 1098 compatible = "fsl,p3041-fman-1g-mac", 1099 "fsl,fman-1g-mac", "fsl,fman-dtsec"; 1100 reg = <0xe0000 0x1000>; 1101 fsl,port-handles = <&fman0_rx0 &fman0_tx0>; 1102 ptimer-handle = <&ptp_timer0>; 1103 }; 1104 1105 mdio0: mdio@e1120 { 1106 #address-cells = <1>; 1107 #size-cells = <0>; 1108 compatible = "fsl,fman-mdio"; 1109 reg = <0xe1120 0xee0>; 1110 interrupts = <100 1 0 0>; 1111 }; 1112 1113 enet1: ethernet@e2000 { 1114 cell-index = <1>; 1115 compatible = "fsl,p3041-fman-1g-mac", 1116 "fsl,fman-1g-mac", "fsl,fman-dtsec"; 1117 reg = <0xe2000 0x1000>; 1118 fsl,port-handles = <&fman0_rx1 &fman0_tx1>; 1119 ptimer-handle = <&ptp_timer0>; 1120 }; 1121 1122 mdio@e3120 { 1123 #address-cells = <1>; 1124 #size-cells = <0>; 1125 compatible = "fsl,fman-tbi"; 1126 reg = <0xe3120 0xee0>; 1127 interrupts = <100 1 0 0>; 1128 }; 1129 1130 enet2: ethernet@e4000 { 1131 cell-index = <2>; 1132 compatible = "fsl,p3041-fman-1g-mac", 1133 "fsl,fman-1g-mac", "fsl,fman-dtsec"; 1134 reg = <0xe4000 0x1000>; 1135 fsl,port-handles = <&fman0_rx2 &fman0_tx2>; 1136 ptimer-handle = <&ptp_timer0>; 1137 }; 1138 1139 mdio@e5120 { 1140 #address-cells = <1>; 1141 #size-cells = <0>; 1142 compatible = "fsl,fman-tbi"; 1143 reg = <0xe5120 0xee0>; 1144 interrupts = <100 1 0 0>; 1145 }; 1146 1147 enet3: ethernet@e6000 { 1148 cell-index = <3>; 1149 compatible = "fsl,p3041-fman-1g-mac", 1150 "fsl,fman-1g-mac", "fsl,fman-dtsec"; 1151 reg = <0xe6000 0x1000>; 1152 fsl,port-handles = <&fman0_rx3 &fman0_tx3>; 1153 }; 1154 1155 mdio@e7120 { 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 compatible = "fsl,fman-tbi"; 1159 reg = <0xe7120 0xee0>; 1160 interrupts = <100 1 0 0>; 1161 }; 1162 1163 enet4: ethernet@e8000 { 1164 cell-index = <4>; 1165 compatible = "fsl,p3041-fman-1g-mac", 1166 "fsl,fman-1g-mac", "fsl,fman-dtsec"; 1167 reg = <0xe8000 0x1000>; 1168 fsl,port-handles = <&fman0_rx4 &fman0_tx4>; 1169 ptimer-handle = <&ptp_timer0>; 1170 }; 1171 1172 mdio@e9120 { 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 compatible = "fsl,fman-tbi"; 1176 reg = <0xe9120 0xee0>; 1177 interrupts = <100 1 0 0>; 1178 }; 1179 1180 enet5: ethernet@f0000 { 1181 cell-index = <0>; 1182 compatible = "fsl,p3041-fman-10g-mac", 1183 "fsl,fman-10g-mac", "fsl,fman-xgec"; 1184 reg = <0xf0000 0x1000>; 1185 fsl,port-handles = <&fman0_rx5 &fman0_tx5>; 1186 }; 1187 1188 mdio@f1000 { 1189 #address-cells = <1>; 1190 #size-cells = <0>; 1191 compatible = "fsl,fman-xmdio"; 1192 reg = <0xf1000 0x1000>; 1193 interrupts = <100 1 0 0>; 1194 }; 1195 1196 ptp_timer0: rtc@fe000 { 1197 compatible = "fsl,fman-rtc"; 1198 reg = <0xfe000 0x1000>; 1199 }; 1200 }; 1201 }; 1202 1203 rapidio@ffe0c0000 { 1204 compatible = "fsl,srio"; 1205 interrupts = <16 2 1 11>; 1206 #address-cells = <2>; 1207 #size-cells = <2>; 1208 ranges; 1209 1210 port1 { 1211 #address-cells = <2>; 1212 #size-cells = <2>; 1213 cell-index = <1>; 1214 }; 1215 1216 port2 { 1217 #address-cells = <2>; 1218 #size-cells = <2>; 1219 cell-index = <2>; 1220 }; 1221 }; 1222 1223 localbus@ffe124000 { 1224 compatible = "fsl,p3041-rev1.0-elbc", "simple-bus", "fsl,elbc"; 1225 interrupts = < 1226 25 2 0 0 1227 16 2 1 19 1228 >; 1229 #address-cells = <2>; 1230 #size-cells = <1>; 1231 }; 1232 1233 pci0: pcie@ffe200000 { 1234 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2"; 1235 device_type = "pci"; 1236 status = "okay"; 1237 #size-cells = <2>; 1238 #address-cells = <3>; 1239 bus-range = <0x0 0xff>; 1240 clock-frequency = <0x1fca055>; 1241 fsl,msi = <&msi0>; 1242 interrupts = <16 2 1 15>; 1243 1244 pcie@0 { 1245 reg = <0 0 0 0 0>; 1246 #interrupt-cells = <1>; 1247 #size-cells = <2>; 1248 #address-cells = <3>; 1249 device_type = "pci"; 1250 interrupts = <16 2 1 15>; 1251 interrupt-map-mask = <0xf800 0 0 7>; 1252 interrupt-map = < 1253 /* IDSEL 0x0 */ 1254 0000 0 0 1 &mpic 40 1 0 0 1255 0000 0 0 2 &mpic 1 1 0 0 1256 0000 0 0 3 &mpic 2 1 0 0 1257 0000 0 0 4 &mpic 3 1 0 0 1258 >; 1259 }; 1260 }; 1261 1262 pci1: pcie@ffe201000 { 1263 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2"; 1264 device_type = "pci"; 1265 status = "disabled"; 1266 #size-cells = <2>; 1267 #address-cells = <3>; 1268 bus-range = <0 0xff>; 1269 clock-frequency = <0x1fca055>; 1270 fsl,msi = <&msi1>; 1271 interrupts = <16 2 1 14>; 1272 pcie@0 { 1273 reg = <0 0 0 0 0>; 1274 #interrupt-cells = <1>; 1275 #size-cells = <2>; 1276 #address-cells = <3>; 1277 device_type = "pci"; 1278 interrupts = <16 2 1 14>; 1279 interrupt-map-mask = <0xf800 0 0 7>; 1280 interrupt-map = < 1281 /* IDSEL 0x0 */ 1282 0000 0 0 1 &mpic 41 1 0 0 1283 0000 0 0 2 &mpic 5 1 0 0 1284 0000 0 0 3 &mpic 6 1 0 0 1285 0000 0 0 4 &mpic 7 1 0 0 1286 >; 1287 }; 1288 }; 1289 1290 pci2: pcie@ffe202000 { 1291 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2"; 1292 device_type = "pci"; 1293 status = "okay"; 1294 #size-cells = <2>; 1295 #address-cells = <3>; 1296 bus-range = <0x0 0xff>; 1297 clock-frequency = <0x1fca055>; 1298 fsl,msi = <&msi2>; 1299 interrupts = <16 2 1 13>; 1300 pcie@0 { 1301 reg = <0 0 0 0 0>; 1302 #interrupt-cells = <1>; 1303 #size-cells = <2>; 1304 #address-cells = <3>; 1305 device_type = "pci"; 1306 interrupts = <16 2 1 13>; 1307 interrupt-map-mask = <0xf800 0 0 7>; 1308 interrupt-map = < 1309 /* IDSEL 0x0 */ 1310 0000 0 0 1 &mpic 42 1 0 0 1311 0000 0 0 2 &mpic 9 1 0 0 1312 0000 0 0 3 &mpic 10 1 0 0 1313 0000 0 0 4 &mpic 11 1 0 0 1314 >; 1315 }; 1316 }; 1317 1318 pci3: pcie@ffe203000 { 1319 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2"; 1320 device_type = "pci"; 1321 status = "disabled"; 1322 #size-cells = <2>; 1323 #address-cells = <3>; 1324 bus-range = <0x0 0xff>; 1325 clock-frequency = <0x1fca055>; 1326 fsl,msi = <&msi2>; 1327 interrupts = <16 2 1 12>; 1328 pcie@0 { 1329 reg = <0 0 0 0 0>; 1330 #interrupt-cells = <1>; 1331 #size-cells = <2>; 1332 #address-cells = <3>; 1333 device_type = "pci"; 1334 interrupts = <16 2 1 12>; 1335 interrupt-map-mask = <0xf800 0 0 7>; 1336 interrupt-map = < 1337 /* IDSEL 0x0 */ 1338 0000 0 0 1 &mpic 43 1 0 0 1339 0000 0 0 2 &mpic 0 1 0 0 1340 0000 0 0 3 &mpic 4 1 0 0 1341 0000 0 0 4 &mpic 8 1 0 0 1342 >; 1343 }; 1344 }; 1345}; 1346