1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 /* 37 * 3Com 3c90x Etherlink XL PCI NIC driver 38 * 39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 40 * bus-master chips (3c90x cards and embedded controllers) including 41 * the following: 42 * 43 * 3Com 3c900-TPO 10Mbps/RJ-45 44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 45 * 3Com 3c905-TX 10/100Mbps/RJ-45 46 * 3Com 3c905-T4 10/100Mbps/RJ-45 47 * 3Com 3c900B-TPO 10Mbps/RJ-45 48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 50 * 3Com 3c900B-FL 10Mbps/Fiber-optic 51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 52 * 3Com 3c905B-TX 10/100Mbps/RJ-45 53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 69 * Dell on-board 3c920 10/100Mbps/RJ-45 70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 71 * Dell Latitude laptop docking station embedded 3c905-TX 72 * 73 * Written by Bill Paul <wpaul@ctr.columbia.edu> 74 * Electrical Engineering Department 75 * Columbia University, New York City 76 */ 77 /* 78 * The 3c90x series chips use a bus-master DMA interface for transferring 79 * packets to and from the controller chip. Some of the "vortex" cards 80 * (3c59x) also supported a bus master mode, however for those chips 81 * you could only DMA packets to/from a contiguous memory buffer. For 82 * transmission this would mean copying the contents of the queued mbuf 83 * chain into an mbuf cluster and then DMAing the cluster. This extra 84 * copy would sort of defeat the purpose of the bus master support for 85 * any packet that doesn't fit into a single mbuf. 86 * 87 * By contrast, the 3c90x cards support a fragment-based bus master 88 * mode where mbuf chains can be encapsulated using TX descriptors. 89 * This is similar to other PCI chips such as the Texas Instruments 90 * ThunderLAN and the Intel 82557/82558. 91 * 92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 93 * bus master chips because they maintain the old PIO interface for 94 * backwards compatibility, but starting with the 3c905B and the 95 * "cyclone" chips, the compatibility interface has been dropped. 96 * Since using bus master DMA is a big win, we use this driver to 97 * support the PCI "boomerang" chips even though they work with the 98 * "vortex" driver in order to obtain better performance. 99 */ 100 101 #ifdef HAVE_KERNEL_OPTION_HEADERS 102 #include "opt_device_polling.h" 103 #endif 104 105 #include <sys/param.h> 106 #include <sys/systm.h> 107 #include <sys/sockio.h> 108 #include <sys/endian.h> 109 #include <sys/kernel.h> 110 #include <sys/malloc.h> 111 #include <sys/mbuf.h> 112 #include <sys/module.h> 113 #include <sys/socket.h> 114 #include <sys/taskqueue.h> 115 116 #include <net/if.h> 117 #include <net/if_var.h> 118 #include <net/if_arp.h> 119 #include <net/ethernet.h> 120 #include <net/if_dl.h> 121 #include <net/if_media.h> 122 #include <net/if_types.h> 123 124 #include <net/bpf.h> 125 126 #include <machine/bus.h> 127 #include <machine/resource.h> 128 #include <sys/bus.h> 129 #include <sys/rman.h> 130 131 #include <dev/mii/mii.h> 132 #include <dev/mii/mii_bitbang.h> 133 #include <dev/mii/miivar.h> 134 135 #include <dev/pci/pcireg.h> 136 #include <dev/pci/pcivar.h> 137 138 MODULE_DEPEND(xl, pci, 1, 1, 1); 139 MODULE_DEPEND(xl, ether, 1, 1, 1); 140 MODULE_DEPEND(xl, miibus, 1, 1, 1); 141 142 /* "device miibus" required. See GENERIC if you get errors here. */ 143 #include "miibus_if.h" 144 145 #include <dev/xl/if_xlreg.h> 146 147 /* 148 * TX Checksumming is disabled by default for two reasons: 149 * - TX Checksumming will occasionally produce corrupt packets 150 * - TX Checksumming seems to reduce performance 151 * 152 * Only 905B/C cards were reported to have this problem, it is possible 153 * that later chips _may_ be immune. 154 */ 155 #define XL905B_TXCSUM_BROKEN 1 156 157 #ifdef XL905B_TXCSUM_BROKEN 158 #define XL905B_CSUM_FEATURES 0 159 #else 160 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 161 #endif 162 163 /* 164 * Various supported device vendors/types and their names. 165 */ 166 static const struct xl_type xl_devs[] = { 167 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 168 "3Com 3c900-TPO Etherlink XL" }, 169 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 170 "3Com 3c900-COMBO Etherlink XL" }, 171 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 172 "3Com 3c905-TX Fast Etherlink XL" }, 173 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 174 "3Com 3c905-T4 Fast Etherlink XL" }, 175 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 176 "3Com 3c900B-TPO Etherlink XL" }, 177 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 178 "3Com 3c900B-COMBO Etherlink XL" }, 179 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 180 "3Com 3c900B-TPC Etherlink XL" }, 181 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 182 "3Com 3c900B-FL Etherlink XL" }, 183 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 184 "3Com 3c905B-TX Fast Etherlink XL" }, 185 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 186 "3Com 3c905B-T4 Fast Etherlink XL" }, 187 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 188 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 189 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 190 "3Com 3c905B-COMBO Fast Etherlink XL" }, 191 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 192 "3Com 3c905C-TX Fast Etherlink XL" }, 193 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 194 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 195 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM, 196 "3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" }, 197 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 198 "3Com 3c980 Fast Etherlink XL" }, 199 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 200 "3Com 3c980C Fast Etherlink XL" }, 201 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 202 "3Com 3cSOHO100-TX OfficeConnect" }, 203 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 204 "3Com 3c450-TX HomeConnect" }, 205 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 206 "3Com 3c555 Fast Etherlink XL" }, 207 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 208 "3Com 3c556 Fast Etherlink XL" }, 209 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 210 "3Com 3c556B Fast Etherlink XL" }, 211 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 212 "3Com 3c575TX Fast Etherlink XL" }, 213 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 214 "3Com 3c575B Fast Etherlink XL" }, 215 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 216 "3Com 3c575C Fast Etherlink XL" }, 217 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 218 "3Com 3c656 Fast Etherlink XL" }, 219 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 220 "3Com 3c656B Fast Etherlink XL" }, 221 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 222 "3Com 3c656C Fast Etherlink XL" }, 223 { 0, 0, NULL } 224 }; 225 226 static int xl_probe(device_t); 227 static int xl_attach(device_t); 228 static int xl_detach(device_t); 229 230 static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *); 231 static void xl_tick(void *); 232 static void xl_stats_update(struct xl_softc *); 233 static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf **); 234 static int xl_rxeof(struct xl_softc *); 235 static void xl_rxeof_task(void *, int); 236 static int xl_rx_resync(struct xl_softc *); 237 static void xl_txeof(struct xl_softc *); 238 static void xl_txeof_90xB(struct xl_softc *); 239 static void xl_txeoc(struct xl_softc *); 240 static void xl_intr(void *); 241 static void xl_start(if_t); 242 static void xl_start_locked(if_t); 243 static void xl_start_90xB_locked(if_t); 244 static int xl_ioctl(if_t, u_long, caddr_t); 245 static void xl_init(void *); 246 static void xl_init_locked(struct xl_softc *); 247 static void xl_stop(struct xl_softc *); 248 static int xl_watchdog(struct xl_softc *); 249 static int xl_shutdown(device_t); 250 static int xl_suspend(device_t); 251 static int xl_resume(device_t); 252 static void xl_setwol(struct xl_softc *); 253 254 #ifdef DEVICE_POLLING 255 static int xl_poll(if_t ifp, enum poll_cmd cmd, int count); 256 static int xl_poll_locked(if_t ifp, enum poll_cmd cmd, int count); 257 #endif 258 259 static int xl_ifmedia_upd(if_t); 260 static void xl_ifmedia_sts(if_t, struct ifmediareq *); 261 262 static int xl_eeprom_wait(struct xl_softc *); 263 static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int); 264 265 static void xl_rxfilter(struct xl_softc *); 266 static void xl_rxfilter_90x(struct xl_softc *); 267 static void xl_rxfilter_90xB(struct xl_softc *); 268 static void xl_setcfg(struct xl_softc *); 269 static void xl_setmode(struct xl_softc *, int); 270 static void xl_reset(struct xl_softc *); 271 static int xl_list_rx_init(struct xl_softc *); 272 static int xl_list_tx_init(struct xl_softc *); 273 static int xl_list_tx_init_90xB(struct xl_softc *); 274 static void xl_wait(struct xl_softc *); 275 static void xl_mediacheck(struct xl_softc *); 276 static void xl_choose_media(struct xl_softc *sc, int *media); 277 static void xl_choose_xcvr(struct xl_softc *, int); 278 static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int); 279 #ifdef notdef 280 static void xl_testpacket(struct xl_softc *); 281 #endif 282 283 static int xl_miibus_readreg(device_t, int, int); 284 static int xl_miibus_writereg(device_t, int, int, int); 285 static void xl_miibus_statchg(device_t); 286 static void xl_miibus_mediainit(device_t); 287 288 /* 289 * MII bit-bang glue 290 */ 291 static uint32_t xl_mii_bitbang_read(device_t); 292 static void xl_mii_bitbang_write(device_t, uint32_t); 293 294 static const struct mii_bitbang_ops xl_mii_bitbang_ops = { 295 xl_mii_bitbang_read, 296 xl_mii_bitbang_write, 297 { 298 XL_MII_DATA, /* MII_BIT_MDO */ 299 XL_MII_DATA, /* MII_BIT_MDI */ 300 XL_MII_CLK, /* MII_BIT_MDC */ 301 XL_MII_DIR, /* MII_BIT_DIR_HOST_PHY */ 302 0, /* MII_BIT_DIR_PHY_HOST */ 303 } 304 }; 305 306 static device_method_t xl_methods[] = { 307 /* Device interface */ 308 DEVMETHOD(device_probe, xl_probe), 309 DEVMETHOD(device_attach, xl_attach), 310 DEVMETHOD(device_detach, xl_detach), 311 DEVMETHOD(device_shutdown, xl_shutdown), 312 DEVMETHOD(device_suspend, xl_suspend), 313 DEVMETHOD(device_resume, xl_resume), 314 315 /* MII interface */ 316 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 317 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 318 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 319 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 320 321 DEVMETHOD_END 322 }; 323 324 static driver_t xl_driver = { 325 "xl", 326 xl_methods, 327 sizeof(struct xl_softc) 328 }; 329 330 DRIVER_MODULE_ORDERED(xl, pci, xl_driver, NULL, NULL, SI_ORDER_ANY); 331 DRIVER_MODULE(miibus, xl, miibus_driver, NULL, NULL); 332 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, xl, xl_devs, 333 nitems(xl_devs) - 1); 334 335 static void 336 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 337 { 338 u_int32_t *paddr; 339 340 paddr = arg; 341 *paddr = segs->ds_addr; 342 } 343 344 /* 345 * Murphy's law says that it's possible the chip can wedge and 346 * the 'command in progress' bit may never clear. Hence, we wait 347 * only a finite amount of time to avoid getting caught in an 348 * infinite loop. Normally this delay routine would be a macro, 349 * but it isn't called during normal operation so we can afford 350 * to make it a function. Suppress warning when card gone. 351 */ 352 static void 353 xl_wait(struct xl_softc *sc) 354 { 355 int i; 356 357 for (i = 0; i < XL_TIMEOUT; i++) { 358 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0) 359 break; 360 } 361 362 if (i == XL_TIMEOUT && bus_child_present(sc->xl_dev)) 363 device_printf(sc->xl_dev, "command never completed!\n"); 364 } 365 366 /* 367 * MII access routines are provided for adapters with external 368 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 369 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 370 * Note: if you don't perform the MDIO operations just right, 371 * it's possible to end up with code that works correctly with 372 * some chips/CPUs/processor speeds/bus speeds/etc but not 373 * with others. 374 */ 375 376 /* 377 * Read the MII serial port for the MII bit-bang module. 378 */ 379 static uint32_t 380 xl_mii_bitbang_read(device_t dev) 381 { 382 struct xl_softc *sc; 383 uint32_t val; 384 385 sc = device_get_softc(dev); 386 387 /* We're already in window 4. */ 388 val = CSR_READ_2(sc, XL_W4_PHY_MGMT); 389 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2, 390 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 391 392 return (val); 393 } 394 395 /* 396 * Write the MII serial port for the MII bit-bang module. 397 */ 398 static void 399 xl_mii_bitbang_write(device_t dev, uint32_t val) 400 { 401 struct xl_softc *sc; 402 403 sc = device_get_softc(dev); 404 405 /* We're already in window 4. */ 406 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, val); 407 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2, 408 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 409 } 410 411 static int 412 xl_miibus_readreg(device_t dev, int phy, int reg) 413 { 414 struct xl_softc *sc; 415 416 sc = device_get_softc(dev); 417 418 /* Select the window 4. */ 419 XL_SEL_WIN(4); 420 421 return (mii_bitbang_readreg(dev, &xl_mii_bitbang_ops, phy, reg)); 422 } 423 424 static int 425 xl_miibus_writereg(device_t dev, int phy, int reg, int data) 426 { 427 struct xl_softc *sc; 428 429 sc = device_get_softc(dev); 430 431 /* Select the window 4. */ 432 XL_SEL_WIN(4); 433 434 mii_bitbang_writereg(dev, &xl_mii_bitbang_ops, phy, reg, data); 435 436 return (0); 437 } 438 439 static void 440 xl_miibus_statchg(device_t dev) 441 { 442 struct xl_softc *sc; 443 struct mii_data *mii; 444 uint8_t macctl; 445 446 sc = device_get_softc(dev); 447 mii = device_get_softc(sc->xl_miibus); 448 449 xl_setcfg(sc); 450 451 /* Set ASIC's duplex mode to match the PHY. */ 452 XL_SEL_WIN(3); 453 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 454 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 455 macctl |= XL_MACCTRL_DUPLEX; 456 if (sc->xl_type == XL_TYPE_905B) { 457 if ((IFM_OPTIONS(mii->mii_media_active) & 458 IFM_ETH_RXPAUSE) != 0) 459 macctl |= XL_MACCTRL_FLOW_CONTROL_ENB; 460 else 461 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB; 462 } 463 } else { 464 macctl &= ~XL_MACCTRL_DUPLEX; 465 if (sc->xl_type == XL_TYPE_905B) 466 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB; 467 } 468 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 469 } 470 471 /* 472 * Special support for the 3c905B-COMBO. This card has 10/100 support 473 * plus BNC and AUI ports. This means we will have both an miibus attached 474 * plus some non-MII media settings. In order to allow this, we have to 475 * add the extra media to the miibus's ifmedia struct, but we can't do 476 * that during xl_attach() because the miibus hasn't been attached yet. 477 * So instead, we wait until the miibus probe/attach is done, at which 478 * point we will get a callback telling is that it's safe to add our 479 * extra media. 480 */ 481 static void 482 xl_miibus_mediainit(device_t dev) 483 { 484 struct xl_softc *sc; 485 struct mii_data *mii; 486 struct ifmedia *ifm; 487 488 sc = device_get_softc(dev); 489 mii = device_get_softc(sc->xl_miibus); 490 ifm = &mii->mii_media; 491 492 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) { 493 /* 494 * Check for a 10baseFL board in disguise. 495 */ 496 if (sc->xl_type == XL_TYPE_905B && 497 sc->xl_media == XL_MEDIAOPT_10FL) { 498 if (bootverbose) 499 device_printf(sc->xl_dev, "found 10baseFL\n"); 500 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL); 501 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0, 502 NULL); 503 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 504 ifmedia_add(ifm, 505 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL); 506 } else { 507 if (bootverbose) 508 device_printf(sc->xl_dev, "found AUI\n"); 509 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL); 510 } 511 } 512 513 if (sc->xl_media & XL_MEDIAOPT_BNC) { 514 if (bootverbose) 515 device_printf(sc->xl_dev, "found BNC\n"); 516 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL); 517 } 518 } 519 520 /* 521 * The EEPROM is slow: give it time to come ready after issuing 522 * it a command. 523 */ 524 static int 525 xl_eeprom_wait(struct xl_softc *sc) 526 { 527 int i; 528 529 for (i = 0; i < 100; i++) { 530 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 531 DELAY(162); 532 else 533 break; 534 } 535 536 if (i == 100) { 537 device_printf(sc->xl_dev, "eeprom failed to come ready\n"); 538 return (1); 539 } 540 541 return (0); 542 } 543 544 /* 545 * Read a sequence of words from the EEPROM. Note that ethernet address 546 * data is stored in the EEPROM in network byte order. 547 */ 548 static int 549 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap) 550 { 551 int err = 0, i; 552 u_int16_t word = 0, *ptr; 553 554 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 555 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 556 /* 557 * XXX: WARNING! DANGER! 558 * It's easy to accidentally overwrite the rom content! 559 * Note: the 3c575 uses 8bit EEPROM offsets. 560 */ 561 XL_SEL_WIN(0); 562 563 if (xl_eeprom_wait(sc)) 564 return (1); 565 566 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 567 off += 0x30; 568 569 for (i = 0; i < cnt; i++) { 570 if (sc->xl_flags & XL_FLAG_8BITROM) 571 CSR_WRITE_2(sc, XL_W0_EE_CMD, 572 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 573 else 574 CSR_WRITE_2(sc, XL_W0_EE_CMD, 575 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 576 err = xl_eeprom_wait(sc); 577 if (err) 578 break; 579 word = CSR_READ_2(sc, XL_W0_EE_DATA); 580 ptr = (u_int16_t *)(dest + (i * 2)); 581 if (swap) 582 *ptr = ntohs(word); 583 else 584 *ptr = word; 585 } 586 587 return (err ? 1 : 0); 588 } 589 590 static void 591 xl_rxfilter(struct xl_softc *sc) 592 { 593 594 if (sc->xl_type == XL_TYPE_905B) 595 xl_rxfilter_90xB(sc); 596 else 597 xl_rxfilter_90x(sc); 598 } 599 600 /* 601 * NICs older than the 3c905B have only one multicast option, which 602 * is to enable reception of all multicast frames. 603 */ 604 static u_int 605 xl_check_maddr_90x(void *arg, struct sockaddr_dl *sdl, u_int cnt) 606 { 607 uint8_t *rxfilt = arg; 608 609 *rxfilt |= XL_RXFILTER_ALLMULTI; 610 611 return (1); 612 } 613 614 static void 615 xl_rxfilter_90x(struct xl_softc *sc) 616 { 617 if_t ifp; 618 u_int8_t rxfilt; 619 620 XL_LOCK_ASSERT(sc); 621 622 ifp = sc->xl_ifp; 623 624 XL_SEL_WIN(5); 625 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 626 rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI | 627 XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL); 628 629 /* Set the individual bit to receive frames for this host only. */ 630 rxfilt |= XL_RXFILTER_INDIVIDUAL; 631 /* Set capture broadcast bit to capture broadcast frames. */ 632 if (if_getflags(ifp) & IFF_BROADCAST) 633 rxfilt |= XL_RXFILTER_BROADCAST; 634 635 /* If we want promiscuous mode, set the allframes bit. */ 636 if (if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) { 637 if (if_getflags(ifp) & IFF_PROMISC) 638 rxfilt |= XL_RXFILTER_ALLFRAMES; 639 if (if_getflags(ifp) & IFF_ALLMULTI) 640 rxfilt |= XL_RXFILTER_ALLMULTI; 641 } else 642 if_foreach_llmaddr(sc->xl_ifp, xl_check_maddr_90x, &rxfilt); 643 644 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); 645 XL_SEL_WIN(7); 646 } 647 648 /* 649 * 3c905B adapters have a hash filter that we can program. 650 * Note: the 3c905B currently only supports a 64-bit 651 * hash table, which means we really only need 6 bits, 652 * but the manual indicates that future chip revisions 653 * will have a 256-bit hash table, hence the routine 654 * is set up to calculate 8 bits of position info in 655 * case we need it some day. 656 * Note II, The Sequel: _CURRENT_ versions of the 657 * 3c905B have a 256 bit hash table. This means we have 658 * to use all 8 bits regardless. On older cards, the 659 * upper 2 bits will be ignored. Grrrr.... 660 */ 661 static u_int 662 xl_check_maddr_90xB(void *arg, struct sockaddr_dl *sdl, u_int count) 663 { 664 struct xl_softc *sc = arg; 665 uint16_t h; 666 667 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) & 0xFF; 668 CSR_WRITE_2(sc, XL_COMMAND, h | XL_CMD_RX_SET_HASH | XL_HASH_SET); 669 670 return (1); 671 } 672 673 static void 674 xl_rxfilter_90xB(struct xl_softc *sc) 675 { 676 if_t ifp; 677 int i; 678 u_int8_t rxfilt; 679 680 XL_LOCK_ASSERT(sc); 681 682 ifp = sc->xl_ifp; 683 684 XL_SEL_WIN(5); 685 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 686 rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI | 687 XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL | 688 XL_RXFILTER_MULTIHASH); 689 690 /* Set the individual bit to receive frames for this host only. */ 691 rxfilt |= XL_RXFILTER_INDIVIDUAL; 692 /* Set capture broadcast bit to capture broadcast frames. */ 693 if (if_getflags(ifp) & IFF_BROADCAST) 694 rxfilt |= XL_RXFILTER_BROADCAST; 695 696 /* If we want promiscuous mode, set the allframes bit. */ 697 if (if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) { 698 if (if_getflags(ifp) & IFF_PROMISC) 699 rxfilt |= XL_RXFILTER_ALLFRAMES; 700 if (if_getflags(ifp) & IFF_ALLMULTI) 701 rxfilt |= XL_RXFILTER_ALLMULTI; 702 } else { 703 /* First, zot all the existing hash bits. */ 704 for (i = 0; i < XL_HASHFILT_SIZE; i++) 705 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH | i); 706 707 /* Now program new ones. */ 708 if (if_foreach_llmaddr(sc->xl_ifp, xl_check_maddr_90xB, sc) > 0) 709 rxfilt |= XL_RXFILTER_MULTIHASH; 710 } 711 712 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); 713 XL_SEL_WIN(7); 714 } 715 716 static void 717 xl_setcfg(struct xl_softc *sc) 718 { 719 u_int32_t icfg; 720 721 /*XL_LOCK_ASSERT(sc);*/ 722 723 XL_SEL_WIN(3); 724 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 725 icfg &= ~XL_ICFG_CONNECTOR_MASK; 726 if (sc->xl_media & XL_MEDIAOPT_MII || 727 sc->xl_media & XL_MEDIAOPT_BT4) 728 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 729 if (sc->xl_media & XL_MEDIAOPT_BTX) 730 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 731 732 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 733 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 734 } 735 736 static void 737 xl_setmode(struct xl_softc *sc, int media) 738 { 739 u_int32_t icfg; 740 u_int16_t mediastat; 741 char *pmsg = "", *dmsg = ""; 742 743 XL_LOCK_ASSERT(sc); 744 745 XL_SEL_WIN(4); 746 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 747 XL_SEL_WIN(3); 748 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 749 750 if (sc->xl_media & XL_MEDIAOPT_BT) { 751 if (IFM_SUBTYPE(media) == IFM_10_T) { 752 pmsg = "10baseT transceiver"; 753 sc->xl_xcvr = XL_XCVR_10BT; 754 icfg &= ~XL_ICFG_CONNECTOR_MASK; 755 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 756 mediastat |= XL_MEDIASTAT_LINKBEAT | 757 XL_MEDIASTAT_JABGUARD; 758 mediastat &= ~XL_MEDIASTAT_SQEENB; 759 } 760 } 761 762 if (sc->xl_media & XL_MEDIAOPT_BFX) { 763 if (IFM_SUBTYPE(media) == IFM_100_FX) { 764 pmsg = "100baseFX port"; 765 sc->xl_xcvr = XL_XCVR_100BFX; 766 icfg &= ~XL_ICFG_CONNECTOR_MASK; 767 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 768 mediastat |= XL_MEDIASTAT_LINKBEAT; 769 mediastat &= ~XL_MEDIASTAT_SQEENB; 770 } 771 } 772 773 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 774 if (IFM_SUBTYPE(media) == IFM_10_5) { 775 pmsg = "AUI port"; 776 sc->xl_xcvr = XL_XCVR_AUI; 777 icfg &= ~XL_ICFG_CONNECTOR_MASK; 778 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 779 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 780 XL_MEDIASTAT_JABGUARD); 781 mediastat |= ~XL_MEDIASTAT_SQEENB; 782 } 783 if (IFM_SUBTYPE(media) == IFM_10_FL) { 784 pmsg = "10baseFL transceiver"; 785 sc->xl_xcvr = XL_XCVR_AUI; 786 icfg &= ~XL_ICFG_CONNECTOR_MASK; 787 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 788 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 789 XL_MEDIASTAT_JABGUARD); 790 mediastat |= ~XL_MEDIASTAT_SQEENB; 791 } 792 } 793 794 if (sc->xl_media & XL_MEDIAOPT_BNC) { 795 if (IFM_SUBTYPE(media) == IFM_10_2) { 796 pmsg = "AUI port"; 797 sc->xl_xcvr = XL_XCVR_COAX; 798 icfg &= ~XL_ICFG_CONNECTOR_MASK; 799 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 800 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 801 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB); 802 } 803 } 804 805 if ((media & IFM_GMASK) == IFM_FDX || 806 IFM_SUBTYPE(media) == IFM_100_FX) { 807 dmsg = "full"; 808 XL_SEL_WIN(3); 809 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 810 } else { 811 dmsg = "half"; 812 XL_SEL_WIN(3); 813 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 814 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 815 } 816 817 if (IFM_SUBTYPE(media) == IFM_10_2) 818 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 819 else 820 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 821 822 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 823 XL_SEL_WIN(4); 824 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 825 826 DELAY(800); 827 XL_SEL_WIN(7); 828 829 device_printf(sc->xl_dev, "selecting %s, %s duplex\n", pmsg, dmsg); 830 } 831 832 static void 833 xl_reset(struct xl_softc *sc) 834 { 835 int i; 836 837 XL_LOCK_ASSERT(sc); 838 839 XL_SEL_WIN(0); 840 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 841 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 842 XL_RESETOPT_DISADVFD:0)); 843 844 /* 845 * If we're using memory mapped register mode, pause briefly 846 * after issuing the reset command before trying to access any 847 * other registers. With my 3c575C CardBus card, failing to do 848 * this results in the system locking up while trying to poll 849 * the command busy bit in the status register. 850 */ 851 if (sc->xl_flags & XL_FLAG_USE_MMIO) 852 DELAY(100000); 853 854 for (i = 0; i < XL_TIMEOUT; i++) { 855 DELAY(10); 856 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 857 break; 858 } 859 860 if (i == XL_TIMEOUT) 861 device_printf(sc->xl_dev, "reset didn't complete\n"); 862 863 /* Reset TX and RX. */ 864 /* Note: the RX reset takes an absurd amount of time 865 * on newer versions of the Tornado chips such as those 866 * on the 3c905CX and newer 3c908C cards. We wait an 867 * extra amount of time so that xl_wait() doesn't complain 868 * and annoy the users. 869 */ 870 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 871 DELAY(100000); 872 xl_wait(sc); 873 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 874 xl_wait(sc); 875 876 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 877 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 878 XL_SEL_WIN(2); 879 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, 880 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) | 881 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ? 882 XL_RESETOPT_INVERT_LED : 0) | 883 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ? 884 XL_RESETOPT_INVERT_MII : 0)); 885 } 886 887 /* Wait a little while for the chip to get its brains in order. */ 888 DELAY(100000); 889 } 890 891 /* 892 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 893 * IDs against our list and return a device name if we find a match. 894 */ 895 static int 896 xl_probe(device_t dev) 897 { 898 const struct xl_type *t; 899 900 t = xl_devs; 901 902 while (t->xl_name != NULL) { 903 if ((pci_get_vendor(dev) == t->xl_vid) && 904 (pci_get_device(dev) == t->xl_did)) { 905 device_set_desc(dev, t->xl_name); 906 return (BUS_PROBE_DEFAULT); 907 } 908 t++; 909 } 910 911 return (ENXIO); 912 } 913 914 /* 915 * This routine is a kludge to work around possible hardware faults 916 * or manufacturing defects that can cause the media options register 917 * (or reset options register, as it's called for the first generation 918 * 3c90x adapters) to return an incorrect result. I have encountered 919 * one Dell Latitude laptop docking station with an integrated 3c905-TX 920 * which doesn't have any of the 'mediaopt' bits set. This screws up 921 * the attach routine pretty badly because it doesn't know what media 922 * to look for. If we find ourselves in this predicament, this routine 923 * will try to guess the media options values and warn the user of a 924 * possible manufacturing defect with his adapter/system/whatever. 925 */ 926 static void 927 xl_mediacheck(struct xl_softc *sc) 928 { 929 930 /* 931 * If some of the media options bits are set, assume they are 932 * correct. If not, try to figure it out down below. 933 * XXX I should check for 10baseFL, but I don't have an adapter 934 * to test with. 935 */ 936 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 937 /* 938 * Check the XCVR value. If it's not in the normal range 939 * of values, we need to fake it up here. 940 */ 941 if (sc->xl_xcvr <= XL_XCVR_AUTO) 942 return; 943 else { 944 device_printf(sc->xl_dev, 945 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr); 946 device_printf(sc->xl_dev, 947 "choosing new default based on card type\n"); 948 } 949 } else { 950 if (sc->xl_type == XL_TYPE_905B && 951 sc->xl_media & XL_MEDIAOPT_10FL) 952 return; 953 device_printf(sc->xl_dev, 954 "WARNING: no media options bits set in the media options register!!\n"); 955 device_printf(sc->xl_dev, 956 "this could be a manufacturing defect in your adapter or system\n"); 957 device_printf(sc->xl_dev, 958 "attempting to guess media type; you should probably consult your vendor\n"); 959 } 960 961 xl_choose_xcvr(sc, 1); 962 } 963 964 static void 965 xl_choose_xcvr(struct xl_softc *sc, int verbose) 966 { 967 u_int16_t devid; 968 969 /* 970 * Read the device ID from the EEPROM. 971 * This is what's loaded into the PCI device ID register, so it has 972 * to be correct otherwise we wouldn't have gotten this far. 973 */ 974 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 975 976 switch (devid) { 977 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 978 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 979 sc->xl_media = XL_MEDIAOPT_BT; 980 sc->xl_xcvr = XL_XCVR_10BT; 981 if (verbose) 982 device_printf(sc->xl_dev, 983 "guessing 10BaseT transceiver\n"); 984 break; 985 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 986 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 987 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 988 sc->xl_xcvr = XL_XCVR_10BT; 989 if (verbose) 990 device_printf(sc->xl_dev, 991 "guessing COMBO (AUI/BNC/TP)\n"); 992 break; 993 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 994 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 995 sc->xl_xcvr = XL_XCVR_10BT; 996 if (verbose) 997 device_printf(sc->xl_dev, "guessing TPC (BNC/TP)\n"); 998 break; 999 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1000 sc->xl_media = XL_MEDIAOPT_10FL; 1001 sc->xl_xcvr = XL_XCVR_AUI; 1002 if (verbose) 1003 device_printf(sc->xl_dev, "guessing 10baseFL\n"); 1004 break; 1005 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1006 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1007 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1008 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1009 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1010 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1011 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1012 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1013 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1014 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1015 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1016 case TC_DEVICEID_TORNADO_10_100BT_920B_WNM: /* 3c920B-EMB-WNM */ 1017 sc->xl_media = XL_MEDIAOPT_MII; 1018 sc->xl_xcvr = XL_XCVR_MII; 1019 if (verbose) 1020 device_printf(sc->xl_dev, "guessing MII\n"); 1021 break; 1022 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1023 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1024 sc->xl_media = XL_MEDIAOPT_BT4; 1025 sc->xl_xcvr = XL_XCVR_MII; 1026 if (verbose) 1027 device_printf(sc->xl_dev, "guessing 100baseT4/MII\n"); 1028 break; 1029 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1030 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1031 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1032 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1033 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1034 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1035 sc->xl_media = XL_MEDIAOPT_BTX; 1036 sc->xl_xcvr = XL_XCVR_AUTO; 1037 if (verbose) 1038 device_printf(sc->xl_dev, "guessing 10/100 internal\n"); 1039 break; 1040 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1041 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1042 sc->xl_xcvr = XL_XCVR_AUTO; 1043 if (verbose) 1044 device_printf(sc->xl_dev, 1045 "guessing 10/100 plus BNC/AUI\n"); 1046 break; 1047 default: 1048 device_printf(sc->xl_dev, 1049 "unknown device ID: %x -- defaulting to 10baseT\n", devid); 1050 sc->xl_media = XL_MEDIAOPT_BT; 1051 break; 1052 } 1053 } 1054 1055 /* 1056 * Attach the interface. Allocate softc structures, do ifmedia 1057 * setup and ethernet/BPF attach. 1058 */ 1059 static int 1060 xl_attach(device_t dev) 1061 { 1062 u_char eaddr[ETHER_ADDR_LEN]; 1063 u_int16_t sinfo2, xcvr[2]; 1064 struct xl_softc *sc; 1065 if_t ifp; 1066 int media, pmcap; 1067 int error = 0, phy, rid, res; 1068 uint16_t did; 1069 1070 sc = device_get_softc(dev); 1071 sc->xl_dev = dev; 1072 1073 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1074 MTX_DEF); 1075 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1076 1077 did = pci_get_device(dev); 1078 1079 sc->xl_flags = 0; 1080 if (did == TC_DEVICEID_HURRICANE_555) 1081 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1082 if (did == TC_DEVICEID_HURRICANE_556 || 1083 did == TC_DEVICEID_HURRICANE_556B) 1084 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1085 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1086 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1087 if (did == TC_DEVICEID_HURRICANE_555 || 1088 did == TC_DEVICEID_HURRICANE_556) 1089 sc->xl_flags |= XL_FLAG_8BITROM; 1090 if (did == TC_DEVICEID_HURRICANE_556B) 1091 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1092 1093 if (did == TC_DEVICEID_HURRICANE_575B || 1094 did == TC_DEVICEID_HURRICANE_575C || 1095 did == TC_DEVICEID_HURRICANE_656B || 1096 did == TC_DEVICEID_TORNADO_656C) 1097 sc->xl_flags |= XL_FLAG_FUNCREG; 1098 if (did == TC_DEVICEID_HURRICANE_575A || 1099 did == TC_DEVICEID_HURRICANE_575B || 1100 did == TC_DEVICEID_HURRICANE_575C || 1101 did == TC_DEVICEID_HURRICANE_656B || 1102 did == TC_DEVICEID_TORNADO_656C) 1103 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 1104 XL_FLAG_8BITROM; 1105 if (did == TC_DEVICEID_HURRICANE_656) 1106 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1107 if (did == TC_DEVICEID_HURRICANE_575B) 1108 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1109 if (did == TC_DEVICEID_HURRICANE_575C) 1110 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1111 if (did == TC_DEVICEID_TORNADO_656C) 1112 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1113 if (did == TC_DEVICEID_HURRICANE_656 || 1114 did == TC_DEVICEID_HURRICANE_656B) 1115 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1116 XL_FLAG_INVERT_LED_PWR; 1117 if (did == TC_DEVICEID_TORNADO_10_100BT_920B || 1118 did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM) 1119 sc->xl_flags |= XL_FLAG_PHYOK; 1120 1121 switch (did) { 1122 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1123 case TC_DEVICEID_HURRICANE_575A: 1124 case TC_DEVICEID_HURRICANE_575B: 1125 case TC_DEVICEID_HURRICANE_575C: 1126 sc->xl_flags |= XL_FLAG_NO_MMIO; 1127 break; 1128 default: 1129 break; 1130 } 1131 1132 /* 1133 * Map control/status registers. 1134 */ 1135 pci_enable_busmaster(dev); 1136 1137 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) { 1138 rid = XL_PCI_LOMEM; 1139 res = SYS_RES_MEMORY; 1140 1141 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1142 } 1143 1144 if (sc->xl_res != NULL) { 1145 sc->xl_flags |= XL_FLAG_USE_MMIO; 1146 if (bootverbose) 1147 device_printf(dev, "using memory mapped I/O\n"); 1148 } else { 1149 rid = XL_PCI_LOIO; 1150 res = SYS_RES_IOPORT; 1151 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1152 if (sc->xl_res == NULL) { 1153 device_printf(dev, "couldn't map ports/memory\n"); 1154 error = ENXIO; 1155 goto fail; 1156 } 1157 if (bootverbose) 1158 device_printf(dev, "using port I/O\n"); 1159 } 1160 1161 sc->xl_btag = rman_get_bustag(sc->xl_res); 1162 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1163 1164 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1165 rid = XL_PCI_FUNCMEM; 1166 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1167 RF_ACTIVE); 1168 1169 if (sc->xl_fres == NULL) { 1170 device_printf(dev, "couldn't map funcreg memory\n"); 1171 error = ENXIO; 1172 goto fail; 1173 } 1174 1175 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1176 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1177 } 1178 1179 /* Allocate interrupt */ 1180 rid = 0; 1181 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1182 RF_SHAREABLE | RF_ACTIVE); 1183 if (sc->xl_irq == NULL) { 1184 device_printf(dev, "couldn't map interrupt\n"); 1185 error = ENXIO; 1186 goto fail; 1187 } 1188 1189 /* Initialize interface name. */ 1190 ifp = sc->xl_ifp = if_alloc(IFT_ETHER); 1191 if_setsoftc(ifp, sc); 1192 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1193 1194 /* Reset the adapter. */ 1195 XL_LOCK(sc); 1196 xl_reset(sc); 1197 XL_UNLOCK(sc); 1198 1199 /* 1200 * Get station address from the EEPROM. 1201 */ 1202 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1203 device_printf(dev, "failed to read station address\n"); 1204 error = ENXIO; 1205 goto fail; 1206 } 1207 1208 callout_init_mtx(&sc->xl_tick_callout, &sc->xl_mtx, 0); 1209 NET_TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc); 1210 1211 /* 1212 * Now allocate a tag for the DMA descriptor lists and a chunk 1213 * of DMA-able memory based on the tag. Also obtain the DMA 1214 * addresses of the RX and TX ring, which we'll need later. 1215 * All of our lists are allocated as a contiguous block 1216 * of memory. 1217 */ 1218 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1219 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1220 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL, 1221 &sc->xl_ldata.xl_rx_tag); 1222 if (error) { 1223 device_printf(dev, "failed to allocate rx dma tag\n"); 1224 goto fail; 1225 } 1226 1227 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag, 1228 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT | 1229 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_rx_dmamap); 1230 if (error) { 1231 device_printf(dev, "no memory for rx list buffers!\n"); 1232 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1233 sc->xl_ldata.xl_rx_tag = NULL; 1234 goto fail; 1235 } 1236 1237 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag, 1238 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list, 1239 XL_RX_LIST_SZ, xl_dma_map_addr, 1240 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT); 1241 if (error) { 1242 device_printf(dev, "cannot get dma address of the rx ring!\n"); 1243 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1244 sc->xl_ldata.xl_rx_dmamap); 1245 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1246 sc->xl_ldata.xl_rx_tag = NULL; 1247 goto fail; 1248 } 1249 1250 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1251 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1252 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL, 1253 &sc->xl_ldata.xl_tx_tag); 1254 if (error) { 1255 device_printf(dev, "failed to allocate tx dma tag\n"); 1256 goto fail; 1257 } 1258 1259 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag, 1260 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT | 1261 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_tx_dmamap); 1262 if (error) { 1263 device_printf(dev, "no memory for list buffers!\n"); 1264 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1265 sc->xl_ldata.xl_tx_tag = NULL; 1266 goto fail; 1267 } 1268 1269 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag, 1270 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list, 1271 XL_TX_LIST_SZ, xl_dma_map_addr, 1272 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT); 1273 if (error) { 1274 device_printf(dev, "cannot get dma address of the tx ring!\n"); 1275 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1276 sc->xl_ldata.xl_tx_dmamap); 1277 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1278 sc->xl_ldata.xl_tx_tag = NULL; 1279 goto fail; 1280 } 1281 1282 /* 1283 * Allocate a DMA tag for the mapping of mbufs. 1284 */ 1285 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 1286 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1287 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL, 1288 NULL, &sc->xl_mtag); 1289 if (error) { 1290 device_printf(dev, "failed to allocate mbuf dma tag\n"); 1291 goto fail; 1292 } 1293 1294 /* We need a spare DMA map for the RX ring. */ 1295 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap); 1296 if (error) 1297 goto fail; 1298 1299 /* 1300 * Figure out the card type. 3c905B adapters have the 1301 * 'supportsNoTxLength' bit set in the capabilities 1302 * word in the EEPROM. 1303 * Note: my 3c575C CardBus card lies. It returns a value 1304 * of 0x1578 for its capabilities word, which is somewhat 1305 * nonsensical. Another way to distinguish a 3c90x chip 1306 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1307 * bit. This will only be set for 3c90x boomerage chips. 1308 */ 1309 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1310 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1311 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1312 sc->xl_type = XL_TYPE_905B; 1313 else 1314 sc->xl_type = XL_TYPE_90X; 1315 1316 /* Check availability of WOL. */ 1317 if ((sc->xl_caps & XL_CAPS_PWRMGMT) != 0 && 1318 pci_find_cap(dev, PCIY_PMG, &pmcap) == 0) { 1319 sc->xl_pmcap = pmcap; 1320 sc->xl_flags |= XL_FLAG_WOL; 1321 sinfo2 = 0; 1322 xl_read_eeprom(sc, (caddr_t)&sinfo2, XL_EE_SOFTINFO2, 1, 0); 1323 if ((sinfo2 & XL_SINFO2_AUX_WOL_CON) == 0 && bootverbose) 1324 device_printf(dev, 1325 "No auxiliary remote wakeup connector!\n"); 1326 } 1327 1328 /* Set the TX start threshold for best performance. */ 1329 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 1330 1331 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1332 if_setioctlfn(ifp, xl_ioctl); 1333 if_setcapabilities(ifp, IFCAP_VLAN_MTU); 1334 if (sc->xl_type == XL_TYPE_905B) { 1335 if_sethwassist(ifp, XL905B_CSUM_FEATURES); 1336 #ifdef XL905B_TXCSUM_BROKEN 1337 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0); 1338 #else 1339 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM, 0); 1340 #endif 1341 } 1342 if ((sc->xl_flags & XL_FLAG_WOL) != 0) 1343 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0); 1344 if_setcapenable(ifp, if_getcapabilities(ifp)); 1345 #ifdef DEVICE_POLLING 1346 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 1347 #endif 1348 if_setstartfn(ifp, xl_start); 1349 if_setinitfn(ifp, xl_init); 1350 if_setsendqlen(ifp, XL_TX_LIST_CNT - 1); 1351 if_setsendqready(ifp); 1352 1353 /* 1354 * Now we have to see what sort of media we have. 1355 * This includes probing for an MII interace and a 1356 * possible PHY. 1357 */ 1358 XL_SEL_WIN(3); 1359 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1360 if (bootverbose) 1361 device_printf(dev, "media options word: %x\n", sc->xl_media); 1362 1363 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1364 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1365 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1366 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1367 1368 xl_mediacheck(sc); 1369 1370 if (sc->xl_media & XL_MEDIAOPT_MII || 1371 sc->xl_media & XL_MEDIAOPT_BTX || 1372 sc->xl_media & XL_MEDIAOPT_BT4) { 1373 if (bootverbose) 1374 device_printf(dev, "found MII/AUTO\n"); 1375 xl_setcfg(sc); 1376 /* 1377 * Attach PHYs only at MII address 24 if !XL_FLAG_PHYOK. 1378 * This is to guard against problems with certain 3Com ASIC 1379 * revisions that incorrectly map the internal transceiver 1380 * control registers at all MII addresses. 1381 */ 1382 phy = MII_PHY_ANY; 1383 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0) 1384 phy = 24; 1385 error = mii_attach(dev, &sc->xl_miibus, ifp, xl_ifmedia_upd, 1386 xl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 1387 sc->xl_type == XL_TYPE_905B ? MIIF_DOPAUSE : 0); 1388 if (error != 0) { 1389 device_printf(dev, "attaching PHYs failed\n"); 1390 goto fail; 1391 } 1392 goto done; 1393 } 1394 1395 /* 1396 * Sanity check. If the user has selected "auto" and this isn't 1397 * a 10/100 card of some kind, we need to force the transceiver 1398 * type to something sane. 1399 */ 1400 if (sc->xl_xcvr == XL_XCVR_AUTO) 1401 xl_choose_xcvr(sc, bootverbose); 1402 1403 /* 1404 * Do ifmedia setup. 1405 */ 1406 if (sc->xl_media & XL_MEDIAOPT_BT) { 1407 if (bootverbose) 1408 device_printf(dev, "found 10baseT\n"); 1409 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1410 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1411 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1412 ifmedia_add(&sc->ifmedia, 1413 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1414 } 1415 1416 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1417 /* 1418 * Check for a 10baseFL board in disguise. 1419 */ 1420 if (sc->xl_type == XL_TYPE_905B && 1421 sc->xl_media == XL_MEDIAOPT_10FL) { 1422 if (bootverbose) 1423 device_printf(dev, "found 10baseFL\n"); 1424 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1425 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1426 0, NULL); 1427 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1428 ifmedia_add(&sc->ifmedia, 1429 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1430 } else { 1431 if (bootverbose) 1432 device_printf(dev, "found AUI\n"); 1433 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1434 } 1435 } 1436 1437 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1438 if (bootverbose) 1439 device_printf(dev, "found BNC\n"); 1440 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1441 } 1442 1443 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1444 if (bootverbose) 1445 device_printf(dev, "found 100baseFX\n"); 1446 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1447 } 1448 1449 media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1450 xl_choose_media(sc, &media); 1451 1452 if (sc->xl_miibus == NULL) 1453 ifmedia_set(&sc->ifmedia, media); 1454 1455 done: 1456 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1457 XL_SEL_WIN(0); 1458 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1459 } 1460 1461 /* 1462 * Call MI attach routine. 1463 */ 1464 ether_ifattach(ifp, eaddr); 1465 1466 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1467 NULL, xl_intr, sc, &sc->xl_intrhand); 1468 if (error) { 1469 device_printf(dev, "couldn't set up irq\n"); 1470 ether_ifdetach(ifp); 1471 goto fail; 1472 } 1473 1474 fail: 1475 if (error) 1476 xl_detach(dev); 1477 1478 return (error); 1479 } 1480 1481 /* 1482 * Choose a default media. 1483 * XXX This is a leaf function only called by xl_attach() and 1484 * acquires/releases the non-recursible driver mutex to 1485 * satisfy lock assertions. 1486 */ 1487 static void 1488 xl_choose_media(struct xl_softc *sc, int *media) 1489 { 1490 1491 XL_LOCK(sc); 1492 1493 switch (sc->xl_xcvr) { 1494 case XL_XCVR_10BT: 1495 *media = IFM_ETHER|IFM_10_T; 1496 xl_setmode(sc, *media); 1497 break; 1498 case XL_XCVR_AUI: 1499 if (sc->xl_type == XL_TYPE_905B && 1500 sc->xl_media == XL_MEDIAOPT_10FL) { 1501 *media = IFM_ETHER|IFM_10_FL; 1502 xl_setmode(sc, *media); 1503 } else { 1504 *media = IFM_ETHER|IFM_10_5; 1505 xl_setmode(sc, *media); 1506 } 1507 break; 1508 case XL_XCVR_COAX: 1509 *media = IFM_ETHER|IFM_10_2; 1510 xl_setmode(sc, *media); 1511 break; 1512 case XL_XCVR_AUTO: 1513 case XL_XCVR_100BTX: 1514 case XL_XCVR_MII: 1515 /* Chosen by miibus */ 1516 break; 1517 case XL_XCVR_100BFX: 1518 *media = IFM_ETHER|IFM_100_FX; 1519 break; 1520 default: 1521 device_printf(sc->xl_dev, "unknown XCVR type: %d\n", 1522 sc->xl_xcvr); 1523 /* 1524 * This will probably be wrong, but it prevents 1525 * the ifmedia code from panicking. 1526 */ 1527 *media = IFM_ETHER|IFM_10_T; 1528 break; 1529 } 1530 1531 XL_UNLOCK(sc); 1532 } 1533 1534 /* 1535 * Shutdown hardware and free up resources. This can be called any 1536 * time after the mutex has been initialized. It is called in both 1537 * the error case in attach and the normal detach case so it needs 1538 * to be careful about only freeing resources that have actually been 1539 * allocated. 1540 */ 1541 static int 1542 xl_detach(device_t dev) 1543 { 1544 struct xl_softc *sc; 1545 if_t ifp; 1546 int rid, res; 1547 1548 sc = device_get_softc(dev); 1549 ifp = sc->xl_ifp; 1550 1551 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized")); 1552 1553 #ifdef DEVICE_POLLING 1554 if (ifp && if_getcapenable(ifp) & IFCAP_POLLING) 1555 ether_poll_deregister(ifp); 1556 #endif 1557 1558 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1559 rid = XL_PCI_LOMEM; 1560 res = SYS_RES_MEMORY; 1561 } else { 1562 rid = XL_PCI_LOIO; 1563 res = SYS_RES_IOPORT; 1564 } 1565 1566 /* These should only be active if attach succeeded */ 1567 if (device_is_attached(dev)) { 1568 XL_LOCK(sc); 1569 xl_stop(sc); 1570 XL_UNLOCK(sc); 1571 taskqueue_drain(taskqueue_swi, &sc->xl_task); 1572 callout_drain(&sc->xl_tick_callout); 1573 ether_ifdetach(ifp); 1574 } 1575 if (sc->xl_miibus) 1576 device_delete_child(dev, sc->xl_miibus); 1577 bus_generic_detach(dev); 1578 ifmedia_removeall(&sc->ifmedia); 1579 1580 if (sc->xl_intrhand) 1581 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1582 if (sc->xl_irq) 1583 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1584 if (sc->xl_fres != NULL) 1585 bus_release_resource(dev, SYS_RES_MEMORY, 1586 XL_PCI_FUNCMEM, sc->xl_fres); 1587 if (sc->xl_res) 1588 bus_release_resource(dev, res, rid, sc->xl_res); 1589 1590 if (ifp) 1591 if_free(ifp); 1592 1593 if (sc->xl_mtag) { 1594 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap); 1595 bus_dma_tag_destroy(sc->xl_mtag); 1596 } 1597 if (sc->xl_ldata.xl_rx_tag) { 1598 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag, 1599 sc->xl_ldata.xl_rx_dmamap); 1600 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1601 sc->xl_ldata.xl_rx_dmamap); 1602 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1603 } 1604 if (sc->xl_ldata.xl_tx_tag) { 1605 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag, 1606 sc->xl_ldata.xl_tx_dmamap); 1607 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1608 sc->xl_ldata.xl_tx_dmamap); 1609 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1610 } 1611 1612 mtx_destroy(&sc->xl_mtx); 1613 1614 return (0); 1615 } 1616 1617 /* 1618 * Initialize the transmit descriptors. 1619 */ 1620 static int 1621 xl_list_tx_init(struct xl_softc *sc) 1622 { 1623 struct xl_chain_data *cd; 1624 struct xl_list_data *ld; 1625 int error, i; 1626 1627 XL_LOCK_ASSERT(sc); 1628 1629 cd = &sc->xl_cdata; 1630 ld = &sc->xl_ldata; 1631 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1632 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1633 error = bus_dmamap_create(sc->xl_mtag, 0, 1634 &cd->xl_tx_chain[i].xl_map); 1635 if (error) 1636 return (error); 1637 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1638 i * sizeof(struct xl_list); 1639 if (i == (XL_TX_LIST_CNT - 1)) 1640 cd->xl_tx_chain[i].xl_next = NULL; 1641 else 1642 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1643 } 1644 1645 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1646 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1647 1648 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1649 return (0); 1650 } 1651 1652 /* 1653 * Initialize the transmit descriptors. 1654 */ 1655 static int 1656 xl_list_tx_init_90xB(struct xl_softc *sc) 1657 { 1658 struct xl_chain_data *cd; 1659 struct xl_list_data *ld; 1660 int error, i; 1661 1662 XL_LOCK_ASSERT(sc); 1663 1664 cd = &sc->xl_cdata; 1665 ld = &sc->xl_ldata; 1666 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1667 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1668 error = bus_dmamap_create(sc->xl_mtag, 0, 1669 &cd->xl_tx_chain[i].xl_map); 1670 if (error) 1671 return (error); 1672 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1673 i * sizeof(struct xl_list); 1674 if (i == (XL_TX_LIST_CNT - 1)) 1675 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1676 else 1677 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1678 if (i == 0) 1679 cd->xl_tx_chain[i].xl_prev = 1680 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1681 else 1682 cd->xl_tx_chain[i].xl_prev = 1683 &cd->xl_tx_chain[i - 1]; 1684 } 1685 1686 bzero(ld->xl_tx_list, XL_TX_LIST_SZ); 1687 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1688 1689 cd->xl_tx_prod = 1; 1690 cd->xl_tx_cons = 1; 1691 cd->xl_tx_cnt = 0; 1692 1693 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1694 return (0); 1695 } 1696 1697 /* 1698 * Initialize the RX descriptors and allocate mbufs for them. Note that 1699 * we arrange the descriptors in a closed ring, so that the last descriptor 1700 * points back to the first. 1701 */ 1702 static int 1703 xl_list_rx_init(struct xl_softc *sc) 1704 { 1705 struct xl_chain_data *cd; 1706 struct xl_list_data *ld; 1707 int error, i, next; 1708 u_int32_t nextptr; 1709 1710 XL_LOCK_ASSERT(sc); 1711 1712 cd = &sc->xl_cdata; 1713 ld = &sc->xl_ldata; 1714 1715 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1716 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1717 error = bus_dmamap_create(sc->xl_mtag, 0, 1718 &cd->xl_rx_chain[i].xl_map); 1719 if (error) 1720 return (error); 1721 error = xl_newbuf(sc, &cd->xl_rx_chain[i]); 1722 if (error) 1723 return (error); 1724 if (i == (XL_RX_LIST_CNT - 1)) 1725 next = 0; 1726 else 1727 next = i + 1; 1728 nextptr = ld->xl_rx_dmaaddr + 1729 next * sizeof(struct xl_list_onefrag); 1730 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1731 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1732 } 1733 1734 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1735 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1736 1737 return (0); 1738 } 1739 1740 /* 1741 * Initialize an RX descriptor and attach an MBUF cluster. 1742 * If we fail to do so, we need to leave the old mbuf and 1743 * the old DMA map untouched so that it can be reused. 1744 */ 1745 static int 1746 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c) 1747 { 1748 struct mbuf *m_new = NULL; 1749 bus_dmamap_t map; 1750 bus_dma_segment_t segs[1]; 1751 int error, nseg; 1752 1753 XL_LOCK_ASSERT(sc); 1754 1755 m_new = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1756 if (m_new == NULL) 1757 return (ENOBUFS); 1758 1759 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1760 1761 /* Force longword alignment for packet payload. */ 1762 m_adj(m_new, ETHER_ALIGN); 1763 1764 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, sc->xl_tmpmap, m_new, 1765 segs, &nseg, BUS_DMA_NOWAIT); 1766 if (error) { 1767 m_freem(m_new); 1768 device_printf(sc->xl_dev, "can't map mbuf (error %d)\n", 1769 error); 1770 return (error); 1771 } 1772 KASSERT(nseg == 1, 1773 ("%s: too many DMA segments (%d)", __func__, nseg)); 1774 1775 bus_dmamap_unload(sc->xl_mtag, c->xl_map); 1776 map = c->xl_map; 1777 c->xl_map = sc->xl_tmpmap; 1778 sc->xl_tmpmap = map; 1779 c->xl_mbuf = m_new; 1780 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG); 1781 c->xl_ptr->xl_frag.xl_addr = htole32(segs->ds_addr); 1782 c->xl_ptr->xl_status = 0; 1783 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); 1784 return (0); 1785 } 1786 1787 static int 1788 xl_rx_resync(struct xl_softc *sc) 1789 { 1790 struct xl_chain_onefrag *pos; 1791 int i; 1792 1793 XL_LOCK_ASSERT(sc); 1794 1795 pos = sc->xl_cdata.xl_rx_head; 1796 1797 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1798 if (pos->xl_ptr->xl_status) 1799 break; 1800 pos = pos->xl_next; 1801 } 1802 1803 if (i == XL_RX_LIST_CNT) 1804 return (0); 1805 1806 sc->xl_cdata.xl_rx_head = pos; 1807 1808 return (EAGAIN); 1809 } 1810 1811 /* 1812 * A frame has been uploaded: pass the resulting mbuf chain up to 1813 * the higher level protocols. 1814 */ 1815 static int 1816 xl_rxeof(struct xl_softc *sc) 1817 { 1818 struct mbuf *m; 1819 if_t ifp = sc->xl_ifp; 1820 struct xl_chain_onefrag *cur_rx; 1821 int total_len; 1822 int rx_npkts = 0; 1823 u_int32_t rxstat; 1824 1825 XL_LOCK_ASSERT(sc); 1826 again: 1827 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap, 1828 BUS_DMASYNC_POSTREAD); 1829 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 1830 #ifdef DEVICE_POLLING 1831 if (if_getcapenable(ifp) & IFCAP_POLLING) { 1832 if (sc->rxcycles <= 0) 1833 break; 1834 sc->rxcycles--; 1835 } 1836 #endif 1837 cur_rx = sc->xl_cdata.xl_rx_head; 1838 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 1839 total_len = rxstat & XL_RXSTAT_LENMASK; 1840 rx_npkts++; 1841 1842 /* 1843 * Since we have told the chip to allow large frames, 1844 * we need to trap giant frame errors in software. We allow 1845 * a little more than the normal frame size to account for 1846 * frames with VLAN tags. 1847 */ 1848 if (total_len > XL_MAX_FRAMELEN) 1849 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 1850 1851 /* 1852 * If an error occurs, update stats, clear the 1853 * status word and leave the mbuf cluster in place: 1854 * it should simply get re-used next time this descriptor 1855 * comes up in the ring. 1856 */ 1857 if (rxstat & XL_RXSTAT_UP_ERROR) { 1858 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1859 cur_rx->xl_ptr->xl_status = 0; 1860 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1861 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1862 continue; 1863 } 1864 1865 /* 1866 * If the error bit was not set, the upload complete 1867 * bit should be set which means we have a valid packet. 1868 * If not, something truly strange has happened. 1869 */ 1870 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 1871 device_printf(sc->xl_dev, 1872 "bad receive status -- packet dropped\n"); 1873 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1874 cur_rx->xl_ptr->xl_status = 0; 1875 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1876 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1877 continue; 1878 } 1879 1880 /* No errors; receive the packet. */ 1881 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map, 1882 BUS_DMASYNC_POSTREAD); 1883 m = cur_rx->xl_mbuf; 1884 1885 /* 1886 * Try to conjure up a new mbuf cluster. If that 1887 * fails, it means we have an out of memory condition and 1888 * should leave the buffer in place and continue. This will 1889 * result in a lost packet, but there's little else we 1890 * can do in this situation. 1891 */ 1892 if (xl_newbuf(sc, cur_rx)) { 1893 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1894 cur_rx->xl_ptr->xl_status = 0; 1895 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1896 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1897 continue; 1898 } 1899 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1900 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1901 1902 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1903 m->m_pkthdr.rcvif = ifp; 1904 m->m_pkthdr.len = m->m_len = total_len; 1905 1906 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 1907 /* Do IP checksum checking. */ 1908 if (rxstat & XL_RXSTAT_IPCKOK) 1909 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1910 if (!(rxstat & XL_RXSTAT_IPCKERR)) 1911 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1912 if ((rxstat & XL_RXSTAT_TCPCOK && 1913 !(rxstat & XL_RXSTAT_TCPCKERR)) || 1914 (rxstat & XL_RXSTAT_UDPCKOK && 1915 !(rxstat & XL_RXSTAT_UDPCKERR))) { 1916 m->m_pkthdr.csum_flags |= 1917 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1918 m->m_pkthdr.csum_data = 0xffff; 1919 } 1920 } 1921 1922 XL_UNLOCK(sc); 1923 if_input(ifp, m); 1924 XL_LOCK(sc); 1925 1926 /* 1927 * If we are running from the taskqueue, the interface 1928 * might have been stopped while we were passing the last 1929 * packet up the network stack. 1930 */ 1931 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 1932 return (rx_npkts); 1933 } 1934 1935 /* 1936 * Handle the 'end of channel' condition. When the upload 1937 * engine hits the end of the RX ring, it will stall. This 1938 * is our cue to flush the RX ring, reload the uplist pointer 1939 * register and unstall the engine. 1940 * XXX This is actually a little goofy. With the ThunderLAN 1941 * chip, you get an interrupt when the receiver hits the end 1942 * of the receive ring, which tells you exactly when you 1943 * you need to reload the ring pointer. Here we have to 1944 * fake it. I'm mad at myself for not being clever enough 1945 * to avoid the use of a goto here. 1946 */ 1947 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 1948 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 1949 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 1950 xl_wait(sc); 1951 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 1952 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 1953 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 1954 goto again; 1955 } 1956 return (rx_npkts); 1957 } 1958 1959 /* 1960 * Taskqueue wrapper for xl_rxeof(). 1961 */ 1962 static void 1963 xl_rxeof_task(void *arg, int pending) 1964 { 1965 struct xl_softc *sc = (struct xl_softc *)arg; 1966 1967 XL_LOCK(sc); 1968 if (if_getdrvflags(sc->xl_ifp) & IFF_DRV_RUNNING) 1969 xl_rxeof(sc); 1970 XL_UNLOCK(sc); 1971 } 1972 1973 /* 1974 * A frame was downloaded to the chip. It's safe for us to clean up 1975 * the list buffers. 1976 */ 1977 static void 1978 xl_txeof(struct xl_softc *sc) 1979 { 1980 struct xl_chain *cur_tx; 1981 if_t ifp = sc->xl_ifp; 1982 1983 XL_LOCK_ASSERT(sc); 1984 1985 /* 1986 * Go through our tx list and free mbufs for those 1987 * frames that have been uploaded. Note: the 3c905B 1988 * sets a special bit in the status word to let us 1989 * know that a frame has been downloaded, but the 1990 * original 3c900/3c905 adapters don't do that. 1991 * Consequently, we have to use a different test if 1992 * xl_type != XL_TYPE_905B. 1993 */ 1994 while (sc->xl_cdata.xl_tx_head != NULL) { 1995 cur_tx = sc->xl_cdata.xl_tx_head; 1996 1997 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 1998 break; 1999 2000 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2001 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2002 BUS_DMASYNC_POSTWRITE); 2003 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2004 m_freem(cur_tx->xl_mbuf); 2005 cur_tx->xl_mbuf = NULL; 2006 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2007 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2008 2009 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2010 sc->xl_cdata.xl_tx_free = cur_tx; 2011 } 2012 2013 if (sc->xl_cdata.xl_tx_head == NULL) { 2014 sc->xl_wdog_timer = 0; 2015 sc->xl_cdata.xl_tx_tail = NULL; 2016 } else { 2017 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2018 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2019 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2020 sc->xl_cdata.xl_tx_head->xl_phys); 2021 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2022 } 2023 } 2024 } 2025 2026 static void 2027 xl_txeof_90xB(struct xl_softc *sc) 2028 { 2029 struct xl_chain *cur_tx = NULL; 2030 if_t ifp = sc->xl_ifp; 2031 int idx; 2032 2033 XL_LOCK_ASSERT(sc); 2034 2035 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2036 BUS_DMASYNC_POSTREAD); 2037 idx = sc->xl_cdata.xl_tx_cons; 2038 while (idx != sc->xl_cdata.xl_tx_prod) { 2039 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2040 2041 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2042 XL_TXSTAT_DL_COMPLETE)) 2043 break; 2044 2045 if (cur_tx->xl_mbuf != NULL) { 2046 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2047 BUS_DMASYNC_POSTWRITE); 2048 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2049 m_freem(cur_tx->xl_mbuf); 2050 cur_tx->xl_mbuf = NULL; 2051 } 2052 2053 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2054 2055 sc->xl_cdata.xl_tx_cnt--; 2056 XL_INC(idx, XL_TX_LIST_CNT); 2057 } 2058 2059 if (sc->xl_cdata.xl_tx_cnt == 0) 2060 sc->xl_wdog_timer = 0; 2061 sc->xl_cdata.xl_tx_cons = idx; 2062 2063 if (cur_tx != NULL) 2064 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2065 } 2066 2067 /* 2068 * TX 'end of channel' interrupt handler. Actually, we should 2069 * only get a 'TX complete' interrupt if there's a transmit error, 2070 * so this is really TX error handler. 2071 */ 2072 static void 2073 xl_txeoc(struct xl_softc *sc) 2074 { 2075 u_int8_t txstat; 2076 2077 XL_LOCK_ASSERT(sc); 2078 2079 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2080 if (txstat & XL_TXSTATUS_UNDERRUN || 2081 txstat & XL_TXSTATUS_JABBER || 2082 txstat & XL_TXSTATUS_RECLAIM) { 2083 device_printf(sc->xl_dev, 2084 "transmission error: 0x%02x\n", txstat); 2085 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2086 xl_wait(sc); 2087 if (sc->xl_type == XL_TYPE_905B) { 2088 if (sc->xl_cdata.xl_tx_cnt) { 2089 int i; 2090 struct xl_chain *c; 2091 2092 i = sc->xl_cdata.xl_tx_cons; 2093 c = &sc->xl_cdata.xl_tx_chain[i]; 2094 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2095 c->xl_phys); 2096 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2097 sc->xl_wdog_timer = 5; 2098 } 2099 } else { 2100 if (sc->xl_cdata.xl_tx_head != NULL) { 2101 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2102 sc->xl_cdata.xl_tx_head->xl_phys); 2103 sc->xl_wdog_timer = 5; 2104 } 2105 } 2106 /* 2107 * Remember to set this for the 2108 * first generation 3c90X chips. 2109 */ 2110 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2111 if (txstat & XL_TXSTATUS_UNDERRUN && 2112 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2113 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2114 device_printf(sc->xl_dev, 2115 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh); 2116 } 2117 CSR_WRITE_2(sc, XL_COMMAND, 2118 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2119 if (sc->xl_type == XL_TYPE_905B) { 2120 CSR_WRITE_2(sc, XL_COMMAND, 2121 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2122 } 2123 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2124 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2125 } else { 2126 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2127 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2128 } 2129 /* 2130 * Write an arbitrary byte to the TX_STATUS register 2131 * to clear this interrupt/error and advance to the next. 2132 */ 2133 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2134 } 2135 } 2136 2137 static void 2138 xl_intr(void *arg) 2139 { 2140 struct xl_softc *sc = arg; 2141 if_t ifp = sc->xl_ifp; 2142 u_int16_t status; 2143 2144 XL_LOCK(sc); 2145 2146 #ifdef DEVICE_POLLING 2147 if (if_getcapenable(ifp) & IFCAP_POLLING) { 2148 XL_UNLOCK(sc); 2149 return; 2150 } 2151 #endif 2152 2153 for (;;) { 2154 status = CSR_READ_2(sc, XL_STATUS); 2155 if ((status & XL_INTRS) == 0 || status == 0xFFFF) 2156 break; 2157 CSR_WRITE_2(sc, XL_COMMAND, 2158 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2159 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 2160 break; 2161 2162 if (status & XL_STAT_UP_COMPLETE) { 2163 if (xl_rxeof(sc) == 0) { 2164 while (xl_rx_resync(sc)) 2165 xl_rxeof(sc); 2166 } 2167 } 2168 2169 if (status & XL_STAT_DOWN_COMPLETE) { 2170 if (sc->xl_type == XL_TYPE_905B) 2171 xl_txeof_90xB(sc); 2172 else 2173 xl_txeof(sc); 2174 } 2175 2176 if (status & XL_STAT_TX_COMPLETE) { 2177 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2178 xl_txeoc(sc); 2179 } 2180 2181 if (status & XL_STAT_ADFAIL) { 2182 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2183 xl_init_locked(sc); 2184 break; 2185 } 2186 2187 if (status & XL_STAT_STATSOFLOW) 2188 xl_stats_update(sc); 2189 } 2190 2191 if (!if_sendq_empty(ifp) && 2192 if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 2193 if (sc->xl_type == XL_TYPE_905B) 2194 xl_start_90xB_locked(ifp); 2195 else 2196 xl_start_locked(ifp); 2197 } 2198 2199 XL_UNLOCK(sc); 2200 } 2201 2202 #ifdef DEVICE_POLLING 2203 static int 2204 xl_poll(if_t ifp, enum poll_cmd cmd, int count) 2205 { 2206 struct xl_softc *sc = if_getsoftc(ifp); 2207 int rx_npkts = 0; 2208 2209 XL_LOCK(sc); 2210 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2211 rx_npkts = xl_poll_locked(ifp, cmd, count); 2212 XL_UNLOCK(sc); 2213 return (rx_npkts); 2214 } 2215 2216 static int 2217 xl_poll_locked(if_t ifp, enum poll_cmd cmd, int count) 2218 { 2219 struct xl_softc *sc = if_getsoftc(ifp); 2220 int rx_npkts; 2221 2222 XL_LOCK_ASSERT(sc); 2223 2224 sc->rxcycles = count; 2225 rx_npkts = xl_rxeof(sc); 2226 if (sc->xl_type == XL_TYPE_905B) 2227 xl_txeof_90xB(sc); 2228 else 2229 xl_txeof(sc); 2230 2231 if (!if_sendq_empty(ifp)) { 2232 if (sc->xl_type == XL_TYPE_905B) 2233 xl_start_90xB_locked(ifp); 2234 else 2235 xl_start_locked(ifp); 2236 } 2237 2238 if (cmd == POLL_AND_CHECK_STATUS) { 2239 u_int16_t status; 2240 2241 status = CSR_READ_2(sc, XL_STATUS); 2242 if (status & XL_INTRS && status != 0xFFFF) { 2243 CSR_WRITE_2(sc, XL_COMMAND, 2244 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2245 2246 if (status & XL_STAT_TX_COMPLETE) { 2247 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2248 xl_txeoc(sc); 2249 } 2250 2251 if (status & XL_STAT_ADFAIL) { 2252 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2253 xl_init_locked(sc); 2254 } 2255 2256 if (status & XL_STAT_STATSOFLOW) 2257 xl_stats_update(sc); 2258 } 2259 } 2260 return (rx_npkts); 2261 } 2262 #endif /* DEVICE_POLLING */ 2263 2264 static void 2265 xl_tick(void *xsc) 2266 { 2267 struct xl_softc *sc = xsc; 2268 struct mii_data *mii; 2269 2270 XL_LOCK_ASSERT(sc); 2271 2272 if (sc->xl_miibus != NULL) { 2273 mii = device_get_softc(sc->xl_miibus); 2274 mii_tick(mii); 2275 } 2276 2277 xl_stats_update(sc); 2278 if (xl_watchdog(sc) == EJUSTRETURN) 2279 return; 2280 2281 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc); 2282 } 2283 2284 static void 2285 xl_stats_update(struct xl_softc *sc) 2286 { 2287 if_t ifp = sc->xl_ifp; 2288 struct xl_stats xl_stats; 2289 u_int8_t *p; 2290 int i; 2291 2292 XL_LOCK_ASSERT(sc); 2293 2294 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2295 2296 p = (u_int8_t *)&xl_stats; 2297 2298 /* Read all the stats registers. */ 2299 XL_SEL_WIN(6); 2300 2301 for (i = 0; i < 16; i++) 2302 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2303 2304 if_inc_counter(ifp, IFCOUNTER_IERRORS, xl_stats.xl_rx_overrun); 2305 2306 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 2307 xl_stats.xl_tx_multi_collision + 2308 xl_stats.xl_tx_single_collision + 2309 xl_stats.xl_tx_late_collision); 2310 2311 /* 2312 * Boomerang and cyclone chips have an extra stats counter 2313 * in window 4 (BadSSD). We have to read this too in order 2314 * to clear out all the stats registers and avoid a statsoflow 2315 * interrupt. 2316 */ 2317 XL_SEL_WIN(4); 2318 CSR_READ_1(sc, XL_W4_BADSSD); 2319 XL_SEL_WIN(7); 2320 } 2321 2322 /* 2323 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2324 * pointers to the fragment pointers. 2325 */ 2326 static int 2327 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head) 2328 { 2329 struct mbuf *m_new; 2330 if_t ifp = sc->xl_ifp; 2331 int error, i, nseg, total_len; 2332 u_int32_t status; 2333 2334 XL_LOCK_ASSERT(sc); 2335 2336 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, *m_head, 2337 sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); 2338 2339 if (error && error != EFBIG) { 2340 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2341 return (error); 2342 } 2343 2344 /* 2345 * Handle special case: we used up all 63 fragments, 2346 * but we have more mbufs left in the chain. Copy the 2347 * data into an mbuf cluster. Note that we don't 2348 * bother clearing the values in the other fragment 2349 * pointers/counters; it wouldn't gain us anything, 2350 * and would waste cycles. 2351 */ 2352 if (error) { 2353 m_new = m_collapse(*m_head, M_NOWAIT, XL_MAXFRAGS); 2354 if (m_new == NULL) { 2355 m_freem(*m_head); 2356 *m_head = NULL; 2357 return (ENOBUFS); 2358 } 2359 *m_head = m_new; 2360 2361 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, 2362 *m_head, sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); 2363 if (error) { 2364 m_freem(*m_head); 2365 *m_head = NULL; 2366 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2367 return (error); 2368 } 2369 } 2370 2371 KASSERT(nseg <= XL_MAXFRAGS, 2372 ("%s: too many DMA segments (%d)", __func__, nseg)); 2373 if (nseg == 0) { 2374 m_freem(*m_head); 2375 *m_head = NULL; 2376 return (EIO); 2377 } 2378 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2379 2380 total_len = 0; 2381 for (i = 0; i < nseg; i++) { 2382 KASSERT(sc->xl_cdata.xl_tx_segs[i].ds_len <= MCLBYTES, 2383 ("segment size too large")); 2384 c->xl_ptr->xl_frag[i].xl_addr = 2385 htole32(sc->xl_cdata.xl_tx_segs[i].ds_addr); 2386 c->xl_ptr->xl_frag[i].xl_len = 2387 htole32(sc->xl_cdata.xl_tx_segs[i].ds_len); 2388 total_len += sc->xl_cdata.xl_tx_segs[i].ds_len; 2389 } 2390 c->xl_ptr->xl_frag[nseg - 1].xl_len |= htole32(XL_LAST_FRAG); 2391 2392 if (sc->xl_type == XL_TYPE_905B) { 2393 status = XL_TXSTAT_RND_DEFEAT; 2394 2395 #ifndef XL905B_TXCSUM_BROKEN 2396 if ((*m_head)->m_pkthdr.csum_flags) { 2397 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 2398 status |= XL_TXSTAT_IPCKSUM; 2399 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 2400 status |= XL_TXSTAT_TCPCKSUM; 2401 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 2402 status |= XL_TXSTAT_UDPCKSUM; 2403 } 2404 #endif 2405 } else 2406 status = total_len; 2407 c->xl_ptr->xl_status = htole32(status); 2408 c->xl_ptr->xl_next = 0; 2409 2410 c->xl_mbuf = *m_head; 2411 return (0); 2412 } 2413 2414 /* 2415 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2416 * to the mbuf data regions directly in the transmit lists. We also save a 2417 * copy of the pointers since the transmit list fragment pointers are 2418 * physical addresses. 2419 */ 2420 2421 static void 2422 xl_start(if_t ifp) 2423 { 2424 struct xl_softc *sc = if_getsoftc(ifp); 2425 2426 XL_LOCK(sc); 2427 2428 if (sc->xl_type == XL_TYPE_905B) 2429 xl_start_90xB_locked(ifp); 2430 else 2431 xl_start_locked(ifp); 2432 2433 XL_UNLOCK(sc); 2434 } 2435 2436 static void 2437 xl_start_locked(if_t ifp) 2438 { 2439 struct xl_softc *sc = if_getsoftc(ifp); 2440 struct mbuf *m_head; 2441 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2442 struct xl_chain *prev_tx; 2443 int error; 2444 2445 XL_LOCK_ASSERT(sc); 2446 2447 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2448 IFF_DRV_RUNNING) 2449 return; 2450 /* 2451 * Check for an available queue slot. If there are none, 2452 * punt. 2453 */ 2454 if (sc->xl_cdata.xl_tx_free == NULL) { 2455 xl_txeoc(sc); 2456 xl_txeof(sc); 2457 if (sc->xl_cdata.xl_tx_free == NULL) { 2458 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2459 return; 2460 } 2461 } 2462 2463 start_tx = sc->xl_cdata.xl_tx_free; 2464 2465 for (; !if_sendq_empty(ifp) && 2466 sc->xl_cdata.xl_tx_free != NULL;) { 2467 m_head = if_dequeue(ifp); 2468 if (m_head == NULL) 2469 break; 2470 2471 /* Pick a descriptor off the free list. */ 2472 prev_tx = cur_tx; 2473 cur_tx = sc->xl_cdata.xl_tx_free; 2474 2475 /* Pack the data into the descriptor. */ 2476 error = xl_encap(sc, cur_tx, &m_head); 2477 if (error) { 2478 cur_tx = prev_tx; 2479 if (m_head == NULL) 2480 break; 2481 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2482 if_sendq_prepend(ifp, m_head); 2483 break; 2484 } 2485 2486 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2487 cur_tx->xl_next = NULL; 2488 2489 /* Chain it together. */ 2490 if (prev != NULL) { 2491 prev->xl_next = cur_tx; 2492 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2493 } 2494 prev = cur_tx; 2495 2496 /* 2497 * If there's a BPF listener, bounce a copy of this frame 2498 * to him. 2499 */ 2500 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2501 } 2502 2503 /* 2504 * If there are no packets queued, bail. 2505 */ 2506 if (cur_tx == NULL) 2507 return; 2508 2509 /* 2510 * Place the request for the upload interrupt 2511 * in the last descriptor in the chain. This way, if 2512 * we're chaining several packets at once, we'll only 2513 * get an interrupt once for the whole chain rather than 2514 * once for each packet. 2515 */ 2516 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR); 2517 2518 /* 2519 * Queue the packets. If the TX channel is clear, update 2520 * the downlist pointer register. 2521 */ 2522 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2523 xl_wait(sc); 2524 2525 if (sc->xl_cdata.xl_tx_head != NULL) { 2526 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2527 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2528 htole32(start_tx->xl_phys); 2529 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &= 2530 htole32(~XL_TXSTAT_DL_INTR); 2531 sc->xl_cdata.xl_tx_tail = cur_tx; 2532 } else { 2533 sc->xl_cdata.xl_tx_head = start_tx; 2534 sc->xl_cdata.xl_tx_tail = cur_tx; 2535 } 2536 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2537 BUS_DMASYNC_PREWRITE); 2538 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2539 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2540 2541 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2542 2543 XL_SEL_WIN(7); 2544 2545 /* 2546 * Set a timeout in case the chip goes out to lunch. 2547 */ 2548 sc->xl_wdog_timer = 5; 2549 2550 /* 2551 * XXX Under certain conditions, usually on slower machines 2552 * where interrupts may be dropped, it's possible for the 2553 * adapter to chew up all the buffers in the receive ring 2554 * and stall, without us being able to do anything about it. 2555 * To guard against this, we need to make a pass over the 2556 * RX queue to make sure there aren't any packets pending. 2557 * Doing it here means we can flush the receive ring at the 2558 * same time the chip is DMAing the transmit descriptors we 2559 * just gave it. 2560 * 2561 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm) 2562 * nature of their chips in all their marketing literature; 2563 * we may as well take advantage of it. :) 2564 */ 2565 taskqueue_enqueue(taskqueue_swi, &sc->xl_task); 2566 } 2567 2568 static void 2569 xl_start_90xB_locked(if_t ifp) 2570 { 2571 struct xl_softc *sc = if_getsoftc(ifp); 2572 struct mbuf *m_head; 2573 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2574 struct xl_chain *prev_tx; 2575 int error, idx; 2576 2577 XL_LOCK_ASSERT(sc); 2578 2579 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2580 IFF_DRV_RUNNING) 2581 return; 2582 2583 idx = sc->xl_cdata.xl_tx_prod; 2584 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2585 2586 for (; !if_sendq_empty(ifp) && 2587 sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL;) { 2588 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2589 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2590 break; 2591 } 2592 2593 m_head = if_dequeue(ifp); 2594 if (m_head == NULL) 2595 break; 2596 2597 prev_tx = cur_tx; 2598 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2599 2600 /* Pack the data into the descriptor. */ 2601 error = xl_encap(sc, cur_tx, &m_head); 2602 if (error) { 2603 cur_tx = prev_tx; 2604 if (m_head == NULL) 2605 break; 2606 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2607 if_sendq_prepend(ifp, m_head); 2608 break; 2609 } 2610 2611 /* Chain it together. */ 2612 if (prev != NULL) 2613 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2614 prev = cur_tx; 2615 2616 /* 2617 * If there's a BPF listener, bounce a copy of this frame 2618 * to him. 2619 */ 2620 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2621 2622 XL_INC(idx, XL_TX_LIST_CNT); 2623 sc->xl_cdata.xl_tx_cnt++; 2624 } 2625 2626 /* 2627 * If there are no packets queued, bail. 2628 */ 2629 if (cur_tx == NULL) 2630 return; 2631 2632 /* 2633 * Place the request for the upload interrupt 2634 * in the last descriptor in the chain. This way, if 2635 * we're chaining several packets at once, we'll only 2636 * get an interrupt once for the whole chain rather than 2637 * once for each packet. 2638 */ 2639 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR); 2640 2641 /* Start transmission */ 2642 sc->xl_cdata.xl_tx_prod = idx; 2643 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2644 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2645 BUS_DMASYNC_PREWRITE); 2646 2647 /* 2648 * Set a timeout in case the chip goes out to lunch. 2649 */ 2650 sc->xl_wdog_timer = 5; 2651 } 2652 2653 static void 2654 xl_init(void *xsc) 2655 { 2656 struct xl_softc *sc = xsc; 2657 2658 XL_LOCK(sc); 2659 xl_init_locked(sc); 2660 XL_UNLOCK(sc); 2661 } 2662 2663 static void 2664 xl_init_locked(struct xl_softc *sc) 2665 { 2666 if_t ifp = sc->xl_ifp; 2667 int error, i; 2668 struct mii_data *mii = NULL; 2669 2670 XL_LOCK_ASSERT(sc); 2671 2672 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2673 return; 2674 /* 2675 * Cancel pending I/O and free all RX/TX buffers. 2676 */ 2677 xl_stop(sc); 2678 2679 /* Reset the chip to a known state. */ 2680 xl_reset(sc); 2681 2682 if (sc->xl_miibus == NULL) { 2683 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2684 xl_wait(sc); 2685 } 2686 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2687 xl_wait(sc); 2688 DELAY(10000); 2689 2690 if (sc->xl_miibus != NULL) 2691 mii = device_get_softc(sc->xl_miibus); 2692 2693 /* 2694 * Clear WOL status and disable all WOL feature as WOL 2695 * would interfere Rx operation under normal environments. 2696 */ 2697 if ((sc->xl_flags & XL_FLAG_WOL) != 0) { 2698 XL_SEL_WIN(7); 2699 CSR_READ_2(sc, XL_W7_BM_PME); 2700 CSR_WRITE_2(sc, XL_W7_BM_PME, 0); 2701 } 2702 /* Init our MAC address */ 2703 XL_SEL_WIN(2); 2704 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2705 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2706 if_getlladdr(sc->xl_ifp)[i]); 2707 } 2708 2709 /* Clear the station mask. */ 2710 for (i = 0; i < 3; i++) 2711 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2712 #ifdef notdef 2713 /* Reset TX and RX. */ 2714 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2715 xl_wait(sc); 2716 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2717 xl_wait(sc); 2718 #endif 2719 /* Init circular RX list. */ 2720 error = xl_list_rx_init(sc); 2721 if (error) { 2722 device_printf(sc->xl_dev, "initialization of the rx ring failed (%d)\n", 2723 error); 2724 xl_stop(sc); 2725 return; 2726 } 2727 2728 /* Init TX descriptors. */ 2729 if (sc->xl_type == XL_TYPE_905B) 2730 error = xl_list_tx_init_90xB(sc); 2731 else 2732 error = xl_list_tx_init(sc); 2733 if (error) { 2734 device_printf(sc->xl_dev, "initialization of the tx ring failed (%d)\n", 2735 error); 2736 xl_stop(sc); 2737 return; 2738 } 2739 2740 /* 2741 * Set the TX freethresh value. 2742 * Note that this has no effect on 3c905B "cyclone" 2743 * cards but is required for 3c900/3c905 "boomerang" 2744 * cards in order to enable the download engine. 2745 */ 2746 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2747 2748 /* Set the TX start threshold for best performance. */ 2749 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2750 2751 /* 2752 * If this is a 3c905B, also set the tx reclaim threshold. 2753 * This helps cut down on the number of tx reclaim errors 2754 * that could happen on a busy network. The chip multiplies 2755 * the register value by 16 to obtain the actual threshold 2756 * in bytes, so we divide by 16 when setting the value here. 2757 * The existing threshold value can be examined by reading 2758 * the register at offset 9 in window 5. 2759 */ 2760 if (sc->xl_type == XL_TYPE_905B) { 2761 CSR_WRITE_2(sc, XL_COMMAND, 2762 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2763 } 2764 2765 /* Set RX filter bits. */ 2766 xl_rxfilter(sc); 2767 2768 /* 2769 * Load the address of the RX list. We have to 2770 * stall the upload engine before we can manipulate 2771 * the uplist pointer register, then unstall it when 2772 * we're finished. We also have to wait for the 2773 * stall command to complete before proceeding. 2774 * Note that we have to do this after any RX resets 2775 * have completed since the uplist register is cleared 2776 * by a reset. 2777 */ 2778 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2779 xl_wait(sc); 2780 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2781 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2782 xl_wait(sc); 2783 2784 if (sc->xl_type == XL_TYPE_905B) { 2785 /* Set polling interval */ 2786 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2787 /* Load the address of the TX list */ 2788 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2789 xl_wait(sc); 2790 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2791 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2792 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2793 xl_wait(sc); 2794 } 2795 2796 /* 2797 * If the coax transceiver is on, make sure to enable 2798 * the DC-DC converter. 2799 */ 2800 XL_SEL_WIN(3); 2801 if (sc->xl_xcvr == XL_XCVR_COAX) 2802 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2803 else 2804 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2805 2806 /* 2807 * increase packet size to allow reception of 802.1q or ISL packets. 2808 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2809 * control register. For 3c90xB/C chips, use the RX packet size 2810 * register. 2811 */ 2812 2813 if (sc->xl_type == XL_TYPE_905B) 2814 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2815 else { 2816 u_int8_t macctl; 2817 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2818 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2819 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2820 } 2821 2822 /* Clear out the stats counters. */ 2823 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2824 xl_stats_update(sc); 2825 XL_SEL_WIN(4); 2826 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2827 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2828 2829 /* 2830 * Enable interrupts. 2831 */ 2832 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 2833 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); 2834 #ifdef DEVICE_POLLING 2835 /* Disable interrupts if we are polling. */ 2836 if (if_getcapenable(ifp) & IFCAP_POLLING) 2837 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 2838 else 2839 #endif 2840 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 2841 if (sc->xl_flags & XL_FLAG_FUNCREG) 2842 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2843 2844 /* Set the RX early threshold */ 2845 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2846 CSR_WRITE_4(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2847 2848 /* Enable receiver and transmitter. */ 2849 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2850 xl_wait(sc); 2851 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2852 xl_wait(sc); 2853 2854 /* XXX Downcall to miibus. */ 2855 if (mii != NULL) 2856 mii_mediachg(mii); 2857 2858 /* Select window 7 for normal operations. */ 2859 XL_SEL_WIN(7); 2860 2861 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 2862 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2863 2864 sc->xl_wdog_timer = 0; 2865 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc); 2866 } 2867 2868 /* 2869 * Set media options. 2870 */ 2871 static int 2872 xl_ifmedia_upd(if_t ifp) 2873 { 2874 struct xl_softc *sc = if_getsoftc(ifp); 2875 struct ifmedia *ifm = NULL; 2876 struct mii_data *mii = NULL; 2877 2878 XL_LOCK(sc); 2879 2880 if (sc->xl_miibus != NULL) 2881 mii = device_get_softc(sc->xl_miibus); 2882 if (mii == NULL) 2883 ifm = &sc->ifmedia; 2884 else 2885 ifm = &mii->mii_media; 2886 2887 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2888 case IFM_100_FX: 2889 case IFM_10_FL: 2890 case IFM_10_2: 2891 case IFM_10_5: 2892 xl_setmode(sc, ifm->ifm_media); 2893 XL_UNLOCK(sc); 2894 return (0); 2895 } 2896 2897 if (sc->xl_media & XL_MEDIAOPT_MII || 2898 sc->xl_media & XL_MEDIAOPT_BTX || 2899 sc->xl_media & XL_MEDIAOPT_BT4) { 2900 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2901 xl_init_locked(sc); 2902 } else { 2903 xl_setmode(sc, ifm->ifm_media); 2904 } 2905 2906 XL_UNLOCK(sc); 2907 2908 return (0); 2909 } 2910 2911 /* 2912 * Report current media status. 2913 */ 2914 static void 2915 xl_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 2916 { 2917 struct xl_softc *sc = if_getsoftc(ifp); 2918 u_int32_t icfg; 2919 u_int16_t status = 0; 2920 struct mii_data *mii = NULL; 2921 2922 XL_LOCK(sc); 2923 2924 if (sc->xl_miibus != NULL) 2925 mii = device_get_softc(sc->xl_miibus); 2926 2927 XL_SEL_WIN(4); 2928 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 2929 2930 XL_SEL_WIN(3); 2931 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 2932 icfg >>= XL_ICFG_CONNECTOR_BITS; 2933 2934 ifmr->ifm_active = IFM_ETHER; 2935 ifmr->ifm_status = IFM_AVALID; 2936 2937 if ((status & XL_MEDIASTAT_CARRIER) == 0) 2938 ifmr->ifm_status |= IFM_ACTIVE; 2939 2940 switch (icfg) { 2941 case XL_XCVR_10BT: 2942 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2943 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2944 ifmr->ifm_active |= IFM_FDX; 2945 else 2946 ifmr->ifm_active |= IFM_HDX; 2947 break; 2948 case XL_XCVR_AUI: 2949 if (sc->xl_type == XL_TYPE_905B && 2950 sc->xl_media == XL_MEDIAOPT_10FL) { 2951 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 2952 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2953 ifmr->ifm_active |= IFM_FDX; 2954 else 2955 ifmr->ifm_active |= IFM_HDX; 2956 } else 2957 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 2958 break; 2959 case XL_XCVR_COAX: 2960 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 2961 break; 2962 /* 2963 * XXX MII and BTX/AUTO should be separate cases. 2964 */ 2965 2966 case XL_XCVR_100BTX: 2967 case XL_XCVR_AUTO: 2968 case XL_XCVR_MII: 2969 if (mii != NULL) { 2970 mii_pollstat(mii); 2971 ifmr->ifm_active = mii->mii_media_active; 2972 ifmr->ifm_status = mii->mii_media_status; 2973 } 2974 break; 2975 case XL_XCVR_100BFX: 2976 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 2977 break; 2978 default: 2979 if_printf(ifp, "unknown XCVR type: %d\n", icfg); 2980 break; 2981 } 2982 2983 XL_UNLOCK(sc); 2984 } 2985 2986 static int 2987 xl_ioctl(if_t ifp, u_long command, caddr_t data) 2988 { 2989 struct xl_softc *sc = if_getsoftc(ifp); 2990 struct ifreq *ifr = (struct ifreq *) data; 2991 int error = 0, mask; 2992 struct mii_data *mii = NULL; 2993 2994 switch (command) { 2995 case SIOCSIFFLAGS: 2996 XL_LOCK(sc); 2997 if (if_getflags(ifp) & IFF_UP) { 2998 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING && 2999 (if_getflags(ifp) ^ sc->xl_if_flags) & 3000 (IFF_PROMISC | IFF_ALLMULTI)) 3001 xl_rxfilter(sc); 3002 else 3003 xl_init_locked(sc); 3004 } else { 3005 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 3006 xl_stop(sc); 3007 } 3008 sc->xl_if_flags = if_getflags(ifp); 3009 XL_UNLOCK(sc); 3010 break; 3011 case SIOCADDMULTI: 3012 case SIOCDELMULTI: 3013 /* XXX Downcall from if_addmulti() possibly with locks held. */ 3014 XL_LOCK(sc); 3015 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 3016 xl_rxfilter(sc); 3017 XL_UNLOCK(sc); 3018 break; 3019 case SIOCGIFMEDIA: 3020 case SIOCSIFMEDIA: 3021 if (sc->xl_miibus != NULL) 3022 mii = device_get_softc(sc->xl_miibus); 3023 if (mii == NULL) 3024 error = ifmedia_ioctl(ifp, ifr, 3025 &sc->ifmedia, command); 3026 else 3027 error = ifmedia_ioctl(ifp, ifr, 3028 &mii->mii_media, command); 3029 break; 3030 case SIOCSIFCAP: 3031 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 3032 #ifdef DEVICE_POLLING 3033 if ((mask & IFCAP_POLLING) != 0 && 3034 (if_getcapabilities(ifp) & IFCAP_POLLING) != 0) { 3035 if_togglecapenable(ifp, IFCAP_POLLING); 3036 if ((if_getcapenable(ifp) & IFCAP_POLLING) != 0) { 3037 error = ether_poll_register(xl_poll, ifp); 3038 if (error) 3039 break; 3040 XL_LOCK(sc); 3041 /* Disable interrupts */ 3042 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3043 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 3044 XL_UNLOCK(sc); 3045 } else { 3046 error = ether_poll_deregister(ifp); 3047 /* Enable interrupts. */ 3048 XL_LOCK(sc); 3049 CSR_WRITE_2(sc, XL_COMMAND, 3050 XL_CMD_INTR_ACK | 0xFF); 3051 CSR_WRITE_2(sc, XL_COMMAND, 3052 XL_CMD_INTR_ENB | XL_INTRS); 3053 if (sc->xl_flags & XL_FLAG_FUNCREG) 3054 bus_space_write_4(sc->xl_ftag, 3055 sc->xl_fhandle, 4, 0x8000); 3056 XL_UNLOCK(sc); 3057 } 3058 } 3059 #endif /* DEVICE_POLLING */ 3060 XL_LOCK(sc); 3061 if ((mask & IFCAP_TXCSUM) != 0 && 3062 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 3063 if_togglecapenable(ifp, IFCAP_TXCSUM); 3064 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 3065 if_sethwassistbits(ifp, XL905B_CSUM_FEATURES, 0); 3066 else 3067 if_sethwassistbits(ifp, 0, XL905B_CSUM_FEATURES); 3068 } 3069 if ((mask & IFCAP_RXCSUM) != 0 && 3070 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) 3071 if_togglecapenable(ifp, IFCAP_RXCSUM); 3072 if ((mask & IFCAP_WOL_MAGIC) != 0 && 3073 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 3074 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 3075 XL_UNLOCK(sc); 3076 break; 3077 default: 3078 error = ether_ioctl(ifp, command, data); 3079 break; 3080 } 3081 3082 return (error); 3083 } 3084 3085 static int 3086 xl_watchdog(struct xl_softc *sc) 3087 { 3088 if_t ifp = sc->xl_ifp; 3089 u_int16_t status = 0; 3090 int misintr; 3091 3092 XL_LOCK_ASSERT(sc); 3093 3094 if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0) 3095 return (0); 3096 3097 xl_rxeof(sc); 3098 xl_txeoc(sc); 3099 misintr = 0; 3100 if (sc->xl_type == XL_TYPE_905B) { 3101 xl_txeof_90xB(sc); 3102 if (sc->xl_cdata.xl_tx_cnt == 0) 3103 misintr++; 3104 } else { 3105 xl_txeof(sc); 3106 if (sc->xl_cdata.xl_tx_head == NULL) 3107 misintr++; 3108 } 3109 if (misintr != 0) { 3110 device_printf(sc->xl_dev, 3111 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 3112 return (0); 3113 } 3114 3115 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3116 XL_SEL_WIN(4); 3117 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3118 device_printf(sc->xl_dev, "watchdog timeout\n"); 3119 3120 if (status & XL_MEDIASTAT_CARRIER) 3121 device_printf(sc->xl_dev, 3122 "no carrier - transceiver cable problem?\n"); 3123 3124 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3125 xl_init_locked(sc); 3126 3127 if (!if_sendq_empty(ifp)) { 3128 if (sc->xl_type == XL_TYPE_905B) 3129 xl_start_90xB_locked(ifp); 3130 else 3131 xl_start_locked(ifp); 3132 } 3133 3134 return (EJUSTRETURN); 3135 } 3136 3137 /* 3138 * Stop the adapter and free any mbufs allocated to the 3139 * RX and TX lists. 3140 */ 3141 static void 3142 xl_stop(struct xl_softc *sc) 3143 { 3144 int i; 3145 if_t ifp = sc->xl_ifp; 3146 3147 XL_LOCK_ASSERT(sc); 3148 3149 sc->xl_wdog_timer = 0; 3150 3151 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3152 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3153 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3154 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3155 xl_wait(sc); 3156 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3157 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3158 DELAY(800); 3159 3160 #ifdef foo 3161 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3162 xl_wait(sc); 3163 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3164 xl_wait(sc); 3165 #endif 3166 3167 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3168 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3169 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3170 if (sc->xl_flags & XL_FLAG_FUNCREG) 3171 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3172 3173 /* Stop the stats updater. */ 3174 callout_stop(&sc->xl_tick_callout); 3175 3176 /* 3177 * Free data in the RX lists. 3178 */ 3179 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3180 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3181 bus_dmamap_unload(sc->xl_mtag, 3182 sc->xl_cdata.xl_rx_chain[i].xl_map); 3183 bus_dmamap_destroy(sc->xl_mtag, 3184 sc->xl_cdata.xl_rx_chain[i].xl_map); 3185 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3186 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3187 } 3188 } 3189 if (sc->xl_ldata.xl_rx_list != NULL) 3190 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3191 /* 3192 * Free the TX list buffers. 3193 */ 3194 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3195 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3196 bus_dmamap_unload(sc->xl_mtag, 3197 sc->xl_cdata.xl_tx_chain[i].xl_map); 3198 bus_dmamap_destroy(sc->xl_mtag, 3199 sc->xl_cdata.xl_tx_chain[i].xl_map); 3200 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3201 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3202 } 3203 } 3204 if (sc->xl_ldata.xl_tx_list != NULL) 3205 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3206 3207 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 3208 } 3209 3210 /* 3211 * Stop all chip I/O so that the kernel's probe routines don't 3212 * get confused by errant DMAs when rebooting. 3213 */ 3214 static int 3215 xl_shutdown(device_t dev) 3216 { 3217 3218 return (xl_suspend(dev)); 3219 } 3220 3221 static int 3222 xl_suspend(device_t dev) 3223 { 3224 struct xl_softc *sc; 3225 3226 sc = device_get_softc(dev); 3227 3228 XL_LOCK(sc); 3229 xl_stop(sc); 3230 xl_setwol(sc); 3231 XL_UNLOCK(sc); 3232 3233 return (0); 3234 } 3235 3236 static int 3237 xl_resume(device_t dev) 3238 { 3239 struct xl_softc *sc; 3240 if_t ifp; 3241 3242 sc = device_get_softc(dev); 3243 ifp = sc->xl_ifp; 3244 3245 XL_LOCK(sc); 3246 3247 if (if_getflags(ifp) & IFF_UP) { 3248 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3249 xl_init_locked(sc); 3250 } 3251 3252 XL_UNLOCK(sc); 3253 3254 return (0); 3255 } 3256 3257 static void 3258 xl_setwol(struct xl_softc *sc) 3259 { 3260 if_t ifp; 3261 u_int16_t cfg, pmstat; 3262 3263 if ((sc->xl_flags & XL_FLAG_WOL) == 0) 3264 return; 3265 3266 ifp = sc->xl_ifp; 3267 XL_SEL_WIN(7); 3268 /* Clear any pending PME events. */ 3269 CSR_READ_2(sc, XL_W7_BM_PME); 3270 cfg = 0; 3271 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 3272 cfg |= XL_BM_PME_MAGIC; 3273 CSR_WRITE_2(sc, XL_W7_BM_PME, cfg); 3274 /* Enable RX. */ 3275 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 3276 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 3277 /* Request PME. */ 3278 pmstat = pci_read_config(sc->xl_dev, 3279 sc->xl_pmcap + PCIR_POWER_STATUS, 2); 3280 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 3281 pmstat |= PCIM_PSTAT_PMEENABLE; 3282 else 3283 pmstat &= ~PCIM_PSTAT_PMEENABLE; 3284 pci_write_config(sc->xl_dev, 3285 sc->xl_pmcap + PCIR_POWER_STATUS, pmstat, 2); 3286 } 3287