1 /*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 2004 Lennart Augustsson. All rights reserved. 5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 31 * 32 * The EHCI 0.96 spec can be found at 33 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf 34 * The EHCI 1.0 spec can be found at 35 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 36 * and the USB 2.0 spec at 37 * http://www.usb.org/developers/docs/usb_20.zip 38 * 39 */ 40 41 /* 42 * TODO: 43 * 1) command failures are not recovered correctly 44 */ 45 46 #include <sys/cdefs.h> 47 __FBSDID("$FreeBSD$"); 48 49 #include <sys/stdint.h> 50 #include <sys/stddef.h> 51 #include <sys/param.h> 52 #include <sys/queue.h> 53 #include <sys/types.h> 54 #include <sys/systm.h> 55 #include <sys/kernel.h> 56 #include <sys/bus.h> 57 #include <sys/module.h> 58 #include <sys/lock.h> 59 #include <sys/mutex.h> 60 #include <sys/condvar.h> 61 #include <sys/sysctl.h> 62 #include <sys/sx.h> 63 #include <sys/unistd.h> 64 #include <sys/callout.h> 65 #include <sys/malloc.h> 66 #include <sys/priv.h> 67 68 #include <dev/usb/usb.h> 69 #include <dev/usb/usbdi.h> 70 71 #define USB_DEBUG_VAR ehcidebug 72 73 #include <dev/usb/usb_core.h> 74 #include <dev/usb/usb_debug.h> 75 #include <dev/usb/usb_busdma.h> 76 #include <dev/usb/usb_process.h> 77 #include <dev/usb/usb_transfer.h> 78 #include <dev/usb/usb_device.h> 79 #include <dev/usb/usb_hub.h> 80 #include <dev/usb/usb_util.h> 81 82 #include <dev/usb/usb_controller.h> 83 #include <dev/usb/usb_bus.h> 84 #include <dev/usb/controller/ehci.h> 85 #include <dev/usb/controller/ehcireg.h> 86 87 #define EHCI_BUS2SC(bus) \ 88 ((ehci_softc_t *)(((uint8_t *)(bus)) - \ 89 ((uint8_t *)&(((ehci_softc_t *)0)->sc_bus)))) 90 91 #ifdef USB_DEBUG 92 static int ehcidebug = 0; 93 static int ehcinohighspeed = 0; 94 static int ehciiaadbug = 0; 95 static int ehcilostintrbug = 0; 96 97 SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci"); 98 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RW, 99 &ehcidebug, 0, "Debug level"); 100 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, no_hs, CTLFLAG_RW, 101 &ehcinohighspeed, 0, "Disable High Speed USB"); 102 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, iaadbug, CTLFLAG_RW, 103 &ehciiaadbug, 0, "Enable doorbell bug workaround"); 104 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, lostintrbug, CTLFLAG_RW, 105 &ehcilostintrbug, 0, "Enable lost interrupt bug workaround"); 106 107 TUNABLE_INT("hw.usb.ehci.debug", &ehcidebug); 108 TUNABLE_INT("hw.usb.ehci.no_hs", &ehcinohighspeed); 109 TUNABLE_INT("hw.usb.ehci.iaadbug", &ehciiaadbug); 110 TUNABLE_INT("hw.usb.ehci.lostintrbug", &ehcilostintrbug); 111 112 static void ehci_dump_regs(ehci_softc_t *sc); 113 static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh); 114 115 #endif 116 117 #define EHCI_INTR_ENDPT 1 118 119 extern struct usb_bus_methods ehci_bus_methods; 120 extern struct usb_pipe_methods ehci_device_bulk_methods; 121 extern struct usb_pipe_methods ehci_device_ctrl_methods; 122 extern struct usb_pipe_methods ehci_device_intr_methods; 123 extern struct usb_pipe_methods ehci_device_isoc_fs_methods; 124 extern struct usb_pipe_methods ehci_device_isoc_hs_methods; 125 126 static void ehci_do_poll(struct usb_bus *); 127 static void ehci_device_done(struct usb_xfer *, usb_error_t); 128 static uint8_t ehci_check_transfer(struct usb_xfer *); 129 static void ehci_timeout(void *); 130 static void ehci_poll_timeout(void *); 131 132 static void ehci_root_intr(ehci_softc_t *sc); 133 134 struct ehci_std_temp { 135 ehci_softc_t *sc; 136 struct usb_page_cache *pc; 137 ehci_qtd_t *td; 138 ehci_qtd_t *td_next; 139 uint32_t average; 140 uint32_t qtd_status; 141 uint32_t len; 142 uint16_t max_frame_size; 143 uint8_t shortpkt; 144 uint8_t auto_data_toggle; 145 uint8_t setup_alt_next; 146 uint8_t last_frame; 147 }; 148 149 void 150 ehci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 151 { 152 ehci_softc_t *sc = EHCI_BUS2SC(bus); 153 uint32_t i; 154 155 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 156 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN); 157 158 cb(bus, &sc->sc_hw.terminate_pc, &sc->sc_hw.terminate_pg, 159 sizeof(struct ehci_qh_sub), EHCI_QH_ALIGN); 160 161 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg, 162 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 163 164 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 165 cb(bus, sc->sc_hw.intr_start_pc + i, 166 sc->sc_hw.intr_start_pg + i, 167 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 168 } 169 170 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 171 cb(bus, sc->sc_hw.isoc_hs_start_pc + i, 172 sc->sc_hw.isoc_hs_start_pg + i, 173 sizeof(ehci_itd_t), EHCI_ITD_ALIGN); 174 } 175 176 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 177 cb(bus, sc->sc_hw.isoc_fs_start_pc + i, 178 sc->sc_hw.isoc_fs_start_pg + i, 179 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN); 180 } 181 } 182 183 usb_error_t 184 ehci_reset(ehci_softc_t *sc) 185 { 186 uint32_t hcr; 187 int i; 188 189 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 190 for (i = 0; i < 100; i++) { 191 usb_pause_mtx(NULL, hz / 1000); 192 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 193 if (!hcr) { 194 if (sc->sc_flags & (EHCI_SCFLG_SETMODE | EHCI_SCFLG_BIGEMMIO)) { 195 /* 196 * Force USBMODE as requested. Controllers 197 * may have multiple operating modes. 198 */ 199 uint32_t usbmode = EOREAD4(sc, EHCI_USBMODE); 200 if (sc->sc_flags & EHCI_SCFLG_SETMODE) { 201 usbmode = (usbmode &~ EHCI_UM_CM) | EHCI_UM_CM_HOST; 202 device_printf(sc->sc_bus.bdev, 203 "set host controller mode\n"); 204 } 205 if (sc->sc_flags & EHCI_SCFLG_BIGEMMIO) { 206 usbmode = (usbmode &~ EHCI_UM_ES) | EHCI_UM_ES_BE; 207 device_printf(sc->sc_bus.bdev, 208 "set big-endian mode\n"); 209 } 210 EOWRITE4(sc, EHCI_USBMODE, usbmode); 211 } 212 return (0); 213 } 214 } 215 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 216 return (USB_ERR_IOERROR); 217 } 218 219 static usb_error_t 220 ehci_hcreset(ehci_softc_t *sc) 221 { 222 uint32_t hcr; 223 int i; 224 225 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 226 for (i = 0; i < 100; i++) { 227 usb_pause_mtx(NULL, hz / 1000); 228 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 229 if (hcr) 230 break; 231 } 232 if (!hcr) 233 /* 234 * Fall through and try reset anyway even though 235 * Table 2-9 in the EHCI spec says this will result 236 * in undefined behavior. 237 */ 238 device_printf(sc->sc_bus.bdev, "stop timeout\n"); 239 240 return ehci_reset(sc); 241 } 242 243 usb_error_t 244 ehci_init(ehci_softc_t *sc) 245 { 246 struct usb_page_search buf_res; 247 uint32_t version; 248 uint32_t sparams; 249 uint32_t cparams; 250 uint32_t hcr; 251 uint16_t i; 252 uint16_t x; 253 uint16_t y; 254 uint16_t bit; 255 usb_error_t err = 0; 256 257 DPRINTF("start\n"); 258 259 usb_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0); 260 usb_callout_init_mtx(&sc->sc_tmo_poll, &sc->sc_bus.bus_mtx, 0); 261 262 #ifdef USB_DEBUG 263 if (ehciiaadbug) 264 sc->sc_flags |= EHCI_SCFLG_IAADBUG; 265 if (ehcilostintrbug) 266 sc->sc_flags |= EHCI_SCFLG_LOSTINTRBUG; 267 if (ehcidebug > 2) { 268 ehci_dump_regs(sc); 269 } 270 #endif 271 272 sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 273 274 version = EHCI_HCIVERSION(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 275 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n", 276 version >> 8, version & 0xff); 277 278 sparams = EREAD4(sc, EHCI_HCSPARAMS); 279 DPRINTF("sparams=0x%x\n", sparams); 280 281 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 282 cparams = EREAD4(sc, EHCI_HCCPARAMS); 283 DPRINTF("cparams=0x%x\n", cparams); 284 285 if (EHCI_HCC_64BIT(cparams)) { 286 DPRINTF("HCC uses 64-bit structures\n"); 287 288 /* MUST clear segment register if 64 bit capable */ 289 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 290 } 291 sc->sc_bus.usbrev = USB_REV_2_0; 292 293 /* Reset the controller */ 294 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev)); 295 296 err = ehci_hcreset(sc); 297 if (err) { 298 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 299 return (err); 300 } 301 /* 302 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4 303 * bytes 2: 256*4 bytes 3: unknown 304 */ 305 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) { 306 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n"); 307 return (USB_ERR_IOERROR); 308 } 309 /* set up the bus struct */ 310 sc->sc_bus.methods = &ehci_bus_methods; 311 312 sc->sc_eintrs = EHCI_NORMAL_INTRS; 313 314 if (1) { 315 struct ehci_qh_sub *qh; 316 317 usbd_get_page(&sc->sc_hw.terminate_pc, 0, &buf_res); 318 319 qh = buf_res.buffer; 320 321 sc->sc_terminate_self = htohc32(sc, buf_res.physaddr); 322 323 /* init terminate TD */ 324 qh->qtd_next = 325 htohc32(sc, EHCI_LINK_TERMINATE); 326 qh->qtd_altnext = 327 htohc32(sc, EHCI_LINK_TERMINATE); 328 qh->qtd_status = 329 htohc32(sc, EHCI_QTD_HALTED); 330 } 331 332 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 333 ehci_qh_t *qh; 334 335 usbd_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res); 336 337 qh = buf_res.buffer; 338 339 /* initialize page cache pointer */ 340 341 qh->page_cache = sc->sc_hw.intr_start_pc + i; 342 343 /* store a pointer to queue head */ 344 345 sc->sc_intr_p_last[i] = qh; 346 347 qh->qh_self = 348 htohc32(sc, buf_res.physaddr) | 349 htohc32(sc, EHCI_LINK_QH); 350 351 qh->qh_endp = 352 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 353 qh->qh_endphub = 354 htohc32(sc, EHCI_QH_SET_MULT(1)); 355 qh->qh_curqtd = 0; 356 357 qh->qh_qtd.qtd_next = 358 htohc32(sc, EHCI_LINK_TERMINATE); 359 qh->qh_qtd.qtd_altnext = 360 htohc32(sc, EHCI_LINK_TERMINATE); 361 qh->qh_qtd.qtd_status = 362 htohc32(sc, EHCI_QTD_HALTED); 363 } 364 365 /* 366 * the QHs are arranged to give poll intervals that are 367 * powers of 2 times 1ms 368 */ 369 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 370 while (bit) { 371 x = bit; 372 while (x & bit) { 373 ehci_qh_t *qh_x; 374 ehci_qh_t *qh_y; 375 376 y = (x ^ bit) | (bit / 2); 377 378 qh_x = sc->sc_intr_p_last[x]; 379 qh_y = sc->sc_intr_p_last[y]; 380 381 /* 382 * the next QH has half the poll interval 383 */ 384 qh_x->qh_link = qh_y->qh_self; 385 386 x++; 387 } 388 bit >>= 1; 389 } 390 391 if (1) { 392 ehci_qh_t *qh; 393 394 qh = sc->sc_intr_p_last[0]; 395 396 /* the last (1ms) QH terminates */ 397 qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE); 398 } 399 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 400 ehci_sitd_t *sitd; 401 ehci_itd_t *itd; 402 403 usbd_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res); 404 405 sitd = buf_res.buffer; 406 407 /* initialize page cache pointer */ 408 409 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i; 410 411 /* store a pointer to the transfer descriptor */ 412 413 sc->sc_isoc_fs_p_last[i] = sitd; 414 415 /* initialize full speed isochronous */ 416 417 sitd->sitd_self = 418 htohc32(sc, buf_res.physaddr) | 419 htohc32(sc, EHCI_LINK_SITD); 420 421 sitd->sitd_back = 422 htohc32(sc, EHCI_LINK_TERMINATE); 423 424 sitd->sitd_next = 425 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self; 426 427 428 usbd_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res); 429 430 itd = buf_res.buffer; 431 432 /* initialize page cache pointer */ 433 434 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i; 435 436 /* store a pointer to the transfer descriptor */ 437 438 sc->sc_isoc_hs_p_last[i] = itd; 439 440 /* initialize high speed isochronous */ 441 442 itd->itd_self = 443 htohc32(sc, buf_res.physaddr) | 444 htohc32(sc, EHCI_LINK_ITD); 445 446 itd->itd_next = 447 sitd->sitd_self; 448 } 449 450 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 451 452 if (1) { 453 uint32_t *pframes; 454 455 pframes = buf_res.buffer; 456 457 /* 458 * execution order: 459 * pframes -> high speed isochronous -> 460 * full speed isochronous -> interrupt QH's 461 */ 462 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) { 463 pframes[i] = sc->sc_isoc_hs_p_last 464 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self; 465 } 466 } 467 /* setup sync list pointer */ 468 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 469 470 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 471 472 if (1) { 473 474 ehci_qh_t *qh; 475 476 qh = buf_res.buffer; 477 478 /* initialize page cache pointer */ 479 480 qh->page_cache = &sc->sc_hw.async_start_pc; 481 482 /* store a pointer to the queue head */ 483 484 sc->sc_async_p_last = qh; 485 486 /* init dummy QH that starts the async list */ 487 488 qh->qh_self = 489 htohc32(sc, buf_res.physaddr) | 490 htohc32(sc, EHCI_LINK_QH); 491 492 /* fill the QH */ 493 qh->qh_endp = 494 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 495 qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1)); 496 qh->qh_link = qh->qh_self; 497 qh->qh_curqtd = 0; 498 499 /* fill the overlay qTD */ 500 qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE); 501 qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE); 502 qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED); 503 } 504 /* flush all cache into memory */ 505 506 usb_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc); 507 508 #ifdef USB_DEBUG 509 if (ehcidebug) { 510 ehci_dump_sqh(sc, sc->sc_async_p_last); 511 } 512 #endif 513 514 /* setup async list pointer */ 515 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 516 517 518 /* enable interrupts */ 519 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 520 521 /* turn on controller */ 522 EOWRITE4(sc, EHCI_USBCMD, 523 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */ 524 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 525 EHCI_CMD_ASE | 526 EHCI_CMD_PSE | 527 EHCI_CMD_RS); 528 529 /* Take over port ownership */ 530 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 531 532 for (i = 0; i < 100; i++) { 533 usb_pause_mtx(NULL, hz / 1000); 534 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 535 if (!hcr) { 536 break; 537 } 538 } 539 if (hcr) { 540 device_printf(sc->sc_bus.bdev, "run timeout\n"); 541 return (USB_ERR_IOERROR); 542 } 543 544 if (!err) { 545 /* catch any lost interrupts */ 546 ehci_do_poll(&sc->sc_bus); 547 } 548 return (err); 549 } 550 551 /* 552 * shut down the controller when the system is going down 553 */ 554 void 555 ehci_detach(ehci_softc_t *sc) 556 { 557 USB_BUS_LOCK(&sc->sc_bus); 558 559 usb_callout_stop(&sc->sc_tmo_pcd); 560 usb_callout_stop(&sc->sc_tmo_poll); 561 562 EOWRITE4(sc, EHCI_USBINTR, 0); 563 USB_BUS_UNLOCK(&sc->sc_bus); 564 565 if (ehci_hcreset(sc)) { 566 DPRINTF("reset failed!\n"); 567 } 568 569 /* XXX let stray task complete */ 570 usb_pause_mtx(NULL, hz / 20); 571 572 usb_callout_drain(&sc->sc_tmo_pcd); 573 usb_callout_drain(&sc->sc_tmo_poll); 574 } 575 576 void 577 ehci_suspend(ehci_softc_t *sc) 578 { 579 uint32_t cmd; 580 uint32_t hcr; 581 uint8_t i; 582 583 USB_BUS_LOCK(&sc->sc_bus); 584 585 for (i = 1; i <= sc->sc_noport; i++) { 586 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 587 if (((cmd & EHCI_PS_PO) == 0) && 588 ((cmd & EHCI_PS_PE) == EHCI_PS_PE)) { 589 EOWRITE4(sc, EHCI_PORTSC(i), 590 cmd | EHCI_PS_SUSP); 591 } 592 } 593 594 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 595 596 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 597 EOWRITE4(sc, EHCI_USBCMD, cmd); 598 599 for (i = 0; i < 100; i++) { 600 hcr = EOREAD4(sc, EHCI_USBSTS) & 601 (EHCI_STS_ASS | EHCI_STS_PSS); 602 603 if (hcr == 0) { 604 break; 605 } 606 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 607 } 608 609 if (hcr != 0) { 610 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 611 } 612 cmd &= ~EHCI_CMD_RS; 613 EOWRITE4(sc, EHCI_USBCMD, cmd); 614 615 for (i = 0; i < 100; i++) { 616 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 617 if (hcr == EHCI_STS_HCH) { 618 break; 619 } 620 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 621 } 622 623 if (hcr != EHCI_STS_HCH) { 624 device_printf(sc->sc_bus.bdev, 625 "config timeout\n"); 626 } 627 USB_BUS_UNLOCK(&sc->sc_bus); 628 } 629 630 void 631 ehci_resume(ehci_softc_t *sc) 632 { 633 struct usb_page_search buf_res; 634 uint32_t cmd; 635 uint32_t hcr; 636 uint8_t i; 637 638 USB_BUS_LOCK(&sc->sc_bus); 639 640 /* restore things in case the bios doesn't */ 641 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 642 643 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 644 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 645 646 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 647 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 648 649 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 650 651 hcr = 0; 652 for (i = 1; i <= sc->sc_noport; i++) { 653 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 654 if (((cmd & EHCI_PS_PO) == 0) && 655 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) { 656 EOWRITE4(sc, EHCI_PORTSC(i), 657 cmd | EHCI_PS_FPR); 658 hcr = 1; 659 } 660 } 661 662 if (hcr) { 663 usb_pause_mtx(&sc->sc_bus.bus_mtx, 664 USB_MS_TO_TICKS(USB_RESUME_WAIT)); 665 666 for (i = 1; i <= sc->sc_noport; i++) { 667 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 668 if (((cmd & EHCI_PS_PO) == 0) && 669 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) { 670 EOWRITE4(sc, EHCI_PORTSC(i), 671 cmd & ~EHCI_PS_FPR); 672 } 673 } 674 } 675 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 676 677 for (i = 0; i < 100; i++) { 678 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 679 if (hcr != EHCI_STS_HCH) { 680 break; 681 } 682 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 683 } 684 if (hcr == EHCI_STS_HCH) { 685 device_printf(sc->sc_bus.bdev, "config timeout\n"); 686 } 687 688 USB_BUS_UNLOCK(&sc->sc_bus); 689 690 usb_pause_mtx(NULL, 691 USB_MS_TO_TICKS(USB_RESUME_WAIT)); 692 693 /* catch any lost interrupts */ 694 ehci_do_poll(&sc->sc_bus); 695 } 696 697 void 698 ehci_shutdown(ehci_softc_t *sc) 699 { 700 DPRINTF("stopping the HC\n"); 701 702 if (ehci_hcreset(sc)) { 703 DPRINTF("reset failed!\n"); 704 } 705 } 706 707 #ifdef USB_DEBUG 708 static void 709 ehci_dump_regs(ehci_softc_t *sc) 710 { 711 uint32_t i; 712 713 i = EOREAD4(sc, EHCI_USBCMD); 714 printf("cmd=0x%08x\n", i); 715 716 if (i & EHCI_CMD_ITC_1) 717 printf(" EHCI_CMD_ITC_1\n"); 718 if (i & EHCI_CMD_ITC_2) 719 printf(" EHCI_CMD_ITC_2\n"); 720 if (i & EHCI_CMD_ITC_4) 721 printf(" EHCI_CMD_ITC_4\n"); 722 if (i & EHCI_CMD_ITC_8) 723 printf(" EHCI_CMD_ITC_8\n"); 724 if (i & EHCI_CMD_ITC_16) 725 printf(" EHCI_CMD_ITC_16\n"); 726 if (i & EHCI_CMD_ITC_32) 727 printf(" EHCI_CMD_ITC_32\n"); 728 if (i & EHCI_CMD_ITC_64) 729 printf(" EHCI_CMD_ITC_64\n"); 730 if (i & EHCI_CMD_ASPME) 731 printf(" EHCI_CMD_ASPME\n"); 732 if (i & EHCI_CMD_ASPMC) 733 printf(" EHCI_CMD_ASPMC\n"); 734 if (i & EHCI_CMD_LHCR) 735 printf(" EHCI_CMD_LHCR\n"); 736 if (i & EHCI_CMD_IAAD) 737 printf(" EHCI_CMD_IAAD\n"); 738 if (i & EHCI_CMD_ASE) 739 printf(" EHCI_CMD_ASE\n"); 740 if (i & EHCI_CMD_PSE) 741 printf(" EHCI_CMD_PSE\n"); 742 if (i & EHCI_CMD_FLS_M) 743 printf(" EHCI_CMD_FLS_M\n"); 744 if (i & EHCI_CMD_HCRESET) 745 printf(" EHCI_CMD_HCRESET\n"); 746 if (i & EHCI_CMD_RS) 747 printf(" EHCI_CMD_RS\n"); 748 749 i = EOREAD4(sc, EHCI_USBSTS); 750 751 printf("sts=0x%08x\n", i); 752 753 if (i & EHCI_STS_ASS) 754 printf(" EHCI_STS_ASS\n"); 755 if (i & EHCI_STS_PSS) 756 printf(" EHCI_STS_PSS\n"); 757 if (i & EHCI_STS_REC) 758 printf(" EHCI_STS_REC\n"); 759 if (i & EHCI_STS_HCH) 760 printf(" EHCI_STS_HCH\n"); 761 if (i & EHCI_STS_IAA) 762 printf(" EHCI_STS_IAA\n"); 763 if (i & EHCI_STS_HSE) 764 printf(" EHCI_STS_HSE\n"); 765 if (i & EHCI_STS_FLR) 766 printf(" EHCI_STS_FLR\n"); 767 if (i & EHCI_STS_PCD) 768 printf(" EHCI_STS_PCD\n"); 769 if (i & EHCI_STS_ERRINT) 770 printf(" EHCI_STS_ERRINT\n"); 771 if (i & EHCI_STS_INT) 772 printf(" EHCI_STS_INT\n"); 773 774 printf("ien=0x%08x\n", 775 EOREAD4(sc, EHCI_USBINTR)); 776 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 777 EOREAD4(sc, EHCI_FRINDEX), 778 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 779 EOREAD4(sc, EHCI_PERIODICLISTBASE), 780 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 781 for (i = 1; i <= sc->sc_noport; i++) { 782 printf("port %d status=0x%08x\n", i, 783 EOREAD4(sc, EHCI_PORTSC(i))); 784 } 785 } 786 787 static void 788 ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type) 789 { 790 link = hc32toh(sc, link); 791 printf("0x%08x", link); 792 if (link & EHCI_LINK_TERMINATE) 793 printf("<T>"); 794 else { 795 printf("<"); 796 if (type) { 797 switch (EHCI_LINK_TYPE(link)) { 798 case EHCI_LINK_ITD: 799 printf("ITD"); 800 break; 801 case EHCI_LINK_QH: 802 printf("QH"); 803 break; 804 case EHCI_LINK_SITD: 805 printf("SITD"); 806 break; 807 case EHCI_LINK_FSTN: 808 printf("FSTN"); 809 break; 810 } 811 } 812 printf(">"); 813 } 814 } 815 816 static void 817 ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd) 818 { 819 uint32_t s; 820 821 printf(" next="); 822 ehci_dump_link(sc, qtd->qtd_next, 0); 823 printf(" altnext="); 824 ehci_dump_link(sc, qtd->qtd_altnext, 0); 825 printf("\n"); 826 s = hc32toh(sc, qtd->qtd_status); 827 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 828 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 829 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 830 printf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n", 831 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), 832 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE", 833 (s & EHCI_QTD_HALTED) ? "-HALTED" : "", 834 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "", 835 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "", 836 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "", 837 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "", 838 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "", 839 (s & EHCI_QTD_PINGSTATE) ? "-PING" : ""); 840 841 for (s = 0; s < 5; s++) { 842 printf(" buffer[%d]=0x%08x\n", s, 843 hc32toh(sc, qtd->qtd_buffer[s])); 844 } 845 for (s = 0; s < 5; s++) { 846 printf(" buffer_hi[%d]=0x%08x\n", s, 847 hc32toh(sc, qtd->qtd_buffer_hi[s])); 848 } 849 } 850 851 static uint8_t 852 ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd) 853 { 854 uint8_t temp; 855 856 usb_pc_cpu_invalidate(sqtd->page_cache); 857 printf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self)); 858 ehci_dump_qtd(sc, sqtd); 859 temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0; 860 return (temp); 861 } 862 863 static void 864 ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd) 865 { 866 uint16_t i; 867 uint8_t stop; 868 869 stop = 0; 870 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) { 871 stop = ehci_dump_sqtd(sc, sqtd); 872 } 873 if (sqtd) { 874 printf("dump aborted, too many TDs\n"); 875 } 876 } 877 878 static void 879 ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh) 880 { 881 uint32_t endp; 882 uint32_t endphub; 883 884 usb_pc_cpu_invalidate(qh->page_cache); 885 printf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F); 886 printf(" link="); 887 ehci_dump_link(sc, qh->qh_link, 1); 888 printf("\n"); 889 endp = hc32toh(sc, qh->qh_endp); 890 printf(" endp=0x%08x\n", endp); 891 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 892 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 893 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 894 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 895 printf(" mpl=0x%x ctl=%d nrl=%d\n", 896 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 897 EHCI_QH_GET_NRL(endp)); 898 endphub = hc32toh(sc, qh->qh_endphub); 899 printf(" endphub=0x%08x\n", endphub); 900 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 901 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 902 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 903 EHCI_QH_GET_MULT(endphub)); 904 printf(" curqtd="); 905 ehci_dump_link(sc, qh->qh_curqtd, 0); 906 printf("\n"); 907 printf("Overlay qTD:\n"); 908 ehci_dump_qtd(sc, (void *)&qh->qh_qtd); 909 } 910 911 static void 912 ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd) 913 { 914 usb_pc_cpu_invalidate(sitd->page_cache); 915 printf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F); 916 printf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next)); 917 printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n", 918 hc32toh(sc, sitd->sitd_portaddr), 919 (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN)) 920 ? "in" : "out", 921 EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)), 922 EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)), 923 EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)), 924 EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr))); 925 printf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask)); 926 printf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status), 927 (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "", 928 EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status))); 929 printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n", 930 hc32toh(sc, sitd->sitd_back), 931 hc32toh(sc, sitd->sitd_bp[0]), 932 hc32toh(sc, sitd->sitd_bp[1]), 933 hc32toh(sc, sitd->sitd_bp_hi[0]), 934 hc32toh(sc, sitd->sitd_bp_hi[1])); 935 } 936 937 static void 938 ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd) 939 { 940 usb_pc_cpu_invalidate(itd->page_cache); 941 printf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F); 942 printf(" next=0x%08x\n", hc32toh(sc, itd->itd_next)); 943 printf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]), 944 (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 945 printf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]), 946 (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 947 printf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]), 948 (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 949 printf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]), 950 (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 951 printf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]), 952 (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 953 printf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]), 954 (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 955 printf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]), 956 (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 957 printf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]), 958 (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 959 printf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0])); 960 printf(" addr=0x%02x; endpt=0x%01x\n", 961 EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])), 962 EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0]))); 963 printf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1])); 964 printf(" dir=%s; mpl=0x%02x\n", 965 (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out", 966 EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1]))); 967 printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n", 968 hc32toh(sc, itd->itd_bp[2]), 969 hc32toh(sc, itd->itd_bp[3]), 970 hc32toh(sc, itd->itd_bp[4]), 971 hc32toh(sc, itd->itd_bp[5]), 972 hc32toh(sc, itd->itd_bp[6])); 973 printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n" 974 " 0x%08x,0x%08x,0x%08x\n", 975 hc32toh(sc, itd->itd_bp_hi[0]), 976 hc32toh(sc, itd->itd_bp_hi[1]), 977 hc32toh(sc, itd->itd_bp_hi[2]), 978 hc32toh(sc, itd->itd_bp_hi[3]), 979 hc32toh(sc, itd->itd_bp_hi[4]), 980 hc32toh(sc, itd->itd_bp_hi[5]), 981 hc32toh(sc, itd->itd_bp_hi[6])); 982 } 983 984 static void 985 ehci_dump_isoc(ehci_softc_t *sc) 986 { 987 ehci_itd_t *itd; 988 ehci_sitd_t *sitd; 989 uint16_t max = 1000; 990 uint16_t pos; 991 992 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) & 993 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 994 995 printf("%s: isochronous dump from frame 0x%03x:\n", 996 __FUNCTION__, pos); 997 998 itd = sc->sc_isoc_hs_p_last[pos]; 999 sitd = sc->sc_isoc_fs_p_last[pos]; 1000 1001 while (itd && max && max--) { 1002 ehci_dump_itd(sc, itd); 1003 itd = itd->prev; 1004 } 1005 1006 while (sitd && max && max--) { 1007 ehci_dump_sitd(sc, sitd); 1008 sitd = sitd->prev; 1009 } 1010 } 1011 1012 #endif 1013 1014 static void 1015 ehci_transfer_intr_enqueue(struct usb_xfer *xfer) 1016 { 1017 /* check for early completion */ 1018 if (ehci_check_transfer(xfer)) { 1019 return; 1020 } 1021 /* put transfer on interrupt queue */ 1022 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 1023 1024 /* start timeout, if any */ 1025 if (xfer->timeout != 0) { 1026 usbd_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout); 1027 } 1028 } 1029 1030 #define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last) 1031 static ehci_sitd_t * 1032 _ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 1033 { 1034 DPRINTFN(11, "%p to %p\n", std, last); 1035 1036 /* (sc->sc_bus.mtx) must be locked */ 1037 1038 std->next = last->next; 1039 std->sitd_next = last->sitd_next; 1040 1041 std->prev = last; 1042 1043 usb_pc_cpu_flush(std->page_cache); 1044 1045 /* 1046 * the last->next->prev is never followed: std->next->prev = std; 1047 */ 1048 last->next = std; 1049 last->sitd_next = std->sitd_self; 1050 1051 usb_pc_cpu_flush(last->page_cache); 1052 1053 return (std); 1054 } 1055 1056 #define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last) 1057 static ehci_itd_t * 1058 _ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1059 { 1060 DPRINTFN(11, "%p to %p\n", std, last); 1061 1062 /* (sc->sc_bus.mtx) must be locked */ 1063 1064 std->next = last->next; 1065 std->itd_next = last->itd_next; 1066 1067 std->prev = last; 1068 1069 usb_pc_cpu_flush(std->page_cache); 1070 1071 /* 1072 * the last->next->prev is never followed: std->next->prev = std; 1073 */ 1074 last->next = std; 1075 last->itd_next = std->itd_self; 1076 1077 usb_pc_cpu_flush(last->page_cache); 1078 1079 return (std); 1080 } 1081 1082 #define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last) 1083 static ehci_qh_t * 1084 _ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1085 { 1086 DPRINTFN(11, "%p to %p\n", sqh, last); 1087 1088 if (sqh->prev != NULL) { 1089 /* should not happen */ 1090 DPRINTFN(0, "QH already linked!\n"); 1091 return (last); 1092 } 1093 /* (sc->sc_bus.mtx) must be locked */ 1094 1095 sqh->next = last->next; 1096 sqh->qh_link = last->qh_link; 1097 1098 sqh->prev = last; 1099 1100 usb_pc_cpu_flush(sqh->page_cache); 1101 1102 /* 1103 * the last->next->prev is never followed: sqh->next->prev = sqh; 1104 */ 1105 1106 last->next = sqh; 1107 last->qh_link = sqh->qh_self; 1108 1109 usb_pc_cpu_flush(last->page_cache); 1110 1111 return (sqh); 1112 } 1113 1114 #define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last) 1115 static ehci_sitd_t * 1116 _ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 1117 { 1118 DPRINTFN(11, "%p from %p\n", std, last); 1119 1120 /* (sc->sc_bus.mtx) must be locked */ 1121 1122 std->prev->next = std->next; 1123 std->prev->sitd_next = std->sitd_next; 1124 1125 usb_pc_cpu_flush(std->prev->page_cache); 1126 1127 if (std->next) { 1128 std->next->prev = std->prev; 1129 usb_pc_cpu_flush(std->next->page_cache); 1130 } 1131 return ((last == std) ? std->prev : last); 1132 } 1133 1134 #define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last) 1135 static ehci_itd_t * 1136 _ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1137 { 1138 DPRINTFN(11, "%p from %p\n", std, last); 1139 1140 /* (sc->sc_bus.mtx) must be locked */ 1141 1142 std->prev->next = std->next; 1143 std->prev->itd_next = std->itd_next; 1144 1145 usb_pc_cpu_flush(std->prev->page_cache); 1146 1147 if (std->next) { 1148 std->next->prev = std->prev; 1149 usb_pc_cpu_flush(std->next->page_cache); 1150 } 1151 return ((last == std) ? std->prev : last); 1152 } 1153 1154 #define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last) 1155 static ehci_qh_t * 1156 _ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1157 { 1158 DPRINTFN(11, "%p from %p\n", sqh, last); 1159 1160 /* (sc->sc_bus.mtx) must be locked */ 1161 1162 /* only remove if not removed from a queue */ 1163 if (sqh->prev) { 1164 1165 sqh->prev->next = sqh->next; 1166 sqh->prev->qh_link = sqh->qh_link; 1167 1168 usb_pc_cpu_flush(sqh->prev->page_cache); 1169 1170 if (sqh->next) { 1171 sqh->next->prev = sqh->prev; 1172 usb_pc_cpu_flush(sqh->next->page_cache); 1173 } 1174 last = ((last == sqh) ? sqh->prev : last); 1175 1176 sqh->prev = 0; 1177 1178 usb_pc_cpu_flush(sqh->page_cache); 1179 } 1180 return (last); 1181 } 1182 1183 static usb_error_t 1184 ehci_non_isoc_done_sub(struct usb_xfer *xfer) 1185 { 1186 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1187 ehci_qtd_t *td; 1188 ehci_qtd_t *td_alt_next; 1189 uint32_t status; 1190 uint16_t len; 1191 1192 td = xfer->td_transfer_cache; 1193 td_alt_next = td->alt_next; 1194 1195 if (xfer->aframes != xfer->nframes) { 1196 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 1197 } 1198 while (1) { 1199 1200 usb_pc_cpu_invalidate(td->page_cache); 1201 status = hc32toh(sc, td->qtd_status); 1202 1203 len = EHCI_QTD_GET_BYTES(status); 1204 1205 /* 1206 * Verify the status length and 1207 * add the length to "frlengths[]": 1208 */ 1209 if (len > td->len) { 1210 /* should not happen */ 1211 DPRINTF("Invalid status length, " 1212 "0x%04x/0x%04x bytes\n", len, td->len); 1213 status |= EHCI_QTD_HALTED; 1214 } else if (xfer->aframes != xfer->nframes) { 1215 xfer->frlengths[xfer->aframes] += td->len - len; 1216 } 1217 /* Check for last transfer */ 1218 if (((void *)td) == xfer->td_transfer_last) { 1219 td = NULL; 1220 break; 1221 } 1222 /* Check for transfer error */ 1223 if (status & EHCI_QTD_HALTED) { 1224 /* the transfer is finished */ 1225 td = NULL; 1226 break; 1227 } 1228 /* Check for short transfer */ 1229 if (len > 0) { 1230 if (xfer->flags_int.short_frames_ok) { 1231 /* follow alt next */ 1232 td = td->alt_next; 1233 } else { 1234 /* the transfer is finished */ 1235 td = NULL; 1236 } 1237 break; 1238 } 1239 td = td->obj_next; 1240 1241 if (td->alt_next != td_alt_next) { 1242 /* this USB frame is complete */ 1243 break; 1244 } 1245 } 1246 1247 /* update transfer cache */ 1248 1249 xfer->td_transfer_cache = td; 1250 1251 #ifdef USB_DEBUG 1252 if (status & EHCI_QTD_STATERRS) { 1253 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x" 1254 "status=%s%s%s%s%s%s%s%s\n", 1255 xfer->address, xfer->endpointno, xfer->aframes, 1256 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1257 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "", 1258 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "", 1259 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "", 1260 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "", 1261 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "", 1262 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "", 1263 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : ""); 1264 } 1265 #endif 1266 1267 return ((status & EHCI_QTD_HALTED) ? 1268 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1269 } 1270 1271 static void 1272 ehci_non_isoc_done(struct usb_xfer *xfer) 1273 { 1274 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1275 ehci_qh_t *qh; 1276 uint32_t status; 1277 usb_error_t err = 0; 1278 1279 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1280 xfer, xfer->endpoint); 1281 1282 #ifdef USB_DEBUG 1283 if (ehcidebug > 10) { 1284 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1285 1286 ehci_dump_sqtds(sc, xfer->td_transfer_first); 1287 } 1288 #endif 1289 1290 /* extract data toggle directly from the QH's overlay area */ 1291 1292 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1293 1294 usb_pc_cpu_invalidate(qh->page_cache); 1295 1296 status = hc32toh(sc, qh->qh_qtd.qtd_status); 1297 1298 xfer->endpoint->toggle_next = 1299 (status & EHCI_QTD_TOGGLE_MASK) ? 1 : 0; 1300 1301 /* reset scanner */ 1302 1303 xfer->td_transfer_cache = xfer->td_transfer_first; 1304 1305 if (xfer->flags_int.control_xfr) { 1306 1307 if (xfer->flags_int.control_hdr) { 1308 1309 err = ehci_non_isoc_done_sub(xfer); 1310 } 1311 xfer->aframes = 1; 1312 1313 if (xfer->td_transfer_cache == NULL) { 1314 goto done; 1315 } 1316 } 1317 while (xfer->aframes != xfer->nframes) { 1318 1319 err = ehci_non_isoc_done_sub(xfer); 1320 xfer->aframes++; 1321 1322 if (xfer->td_transfer_cache == NULL) { 1323 goto done; 1324 } 1325 } 1326 1327 if (xfer->flags_int.control_xfr && 1328 !xfer->flags_int.control_act) { 1329 1330 err = ehci_non_isoc_done_sub(xfer); 1331 } 1332 done: 1333 ehci_device_done(xfer, err); 1334 } 1335 1336 /*------------------------------------------------------------------------* 1337 * ehci_check_transfer 1338 * 1339 * Return values: 1340 * 0: USB transfer is not finished 1341 * Else: USB transfer is finished 1342 *------------------------------------------------------------------------*/ 1343 static uint8_t 1344 ehci_check_transfer(struct usb_xfer *xfer) 1345 { 1346 struct usb_pipe_methods *methods = xfer->endpoint->methods; 1347 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1348 1349 uint32_t status; 1350 1351 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1352 1353 if (methods == &ehci_device_isoc_fs_methods) { 1354 ehci_sitd_t *td; 1355 1356 /* isochronous full speed transfer */ 1357 1358 td = xfer->td_transfer_last; 1359 usb_pc_cpu_invalidate(td->page_cache); 1360 status = hc32toh(sc, td->sitd_status); 1361 1362 /* also check if first is complete */ 1363 1364 td = xfer->td_transfer_first; 1365 usb_pc_cpu_invalidate(td->page_cache); 1366 status |= hc32toh(sc, td->sitd_status); 1367 1368 if (!(status & EHCI_SITD_ACTIVE)) { 1369 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1370 goto transferred; 1371 } 1372 } else if (methods == &ehci_device_isoc_hs_methods) { 1373 ehci_itd_t *td; 1374 1375 /* isochronous high speed transfer */ 1376 1377 /* check last transfer */ 1378 td = xfer->td_transfer_last; 1379 usb_pc_cpu_invalidate(td->page_cache); 1380 status = td->itd_status[0]; 1381 status |= td->itd_status[1]; 1382 status |= td->itd_status[2]; 1383 status |= td->itd_status[3]; 1384 status |= td->itd_status[4]; 1385 status |= td->itd_status[5]; 1386 status |= td->itd_status[6]; 1387 status |= td->itd_status[7]; 1388 1389 /* also check first transfer */ 1390 td = xfer->td_transfer_first; 1391 usb_pc_cpu_invalidate(td->page_cache); 1392 status |= td->itd_status[0]; 1393 status |= td->itd_status[1]; 1394 status |= td->itd_status[2]; 1395 status |= td->itd_status[3]; 1396 status |= td->itd_status[4]; 1397 status |= td->itd_status[5]; 1398 status |= td->itd_status[6]; 1399 status |= td->itd_status[7]; 1400 1401 /* if no transactions are active we continue */ 1402 if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) { 1403 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1404 goto transferred; 1405 } 1406 } else { 1407 ehci_qtd_t *td; 1408 ehci_qh_t *qh; 1409 1410 /* non-isochronous transfer */ 1411 1412 /* 1413 * check whether there is an error somewhere in the middle, 1414 * or whether there was a short packet (SPD and not ACTIVE) 1415 */ 1416 td = xfer->td_transfer_cache; 1417 1418 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1419 1420 usb_pc_cpu_invalidate(qh->page_cache); 1421 1422 status = hc32toh(sc, qh->qh_qtd.qtd_status); 1423 if (status & EHCI_QTD_ACTIVE) { 1424 /* transfer is pending */ 1425 goto done; 1426 } 1427 1428 while (1) { 1429 usb_pc_cpu_invalidate(td->page_cache); 1430 status = hc32toh(sc, td->qtd_status); 1431 1432 /* 1433 * Check if there is an active TD which 1434 * indicates that the transfer isn't done. 1435 */ 1436 if (status & EHCI_QTD_ACTIVE) { 1437 /* update cache */ 1438 xfer->td_transfer_cache = td; 1439 goto done; 1440 } 1441 /* 1442 * last transfer descriptor makes the transfer done 1443 */ 1444 if (((void *)td) == xfer->td_transfer_last) { 1445 break; 1446 } 1447 /* 1448 * any kind of error makes the transfer done 1449 */ 1450 if (status & EHCI_QTD_HALTED) { 1451 break; 1452 } 1453 /* 1454 * if there is no alternate next transfer, a short 1455 * packet also makes the transfer done 1456 */ 1457 if (EHCI_QTD_GET_BYTES(status)) { 1458 if (xfer->flags_int.short_frames_ok) { 1459 /* follow alt next */ 1460 if (td->alt_next) { 1461 td = td->alt_next; 1462 continue; 1463 } 1464 } 1465 /* transfer is done */ 1466 break; 1467 } 1468 td = td->obj_next; 1469 } 1470 ehci_non_isoc_done(xfer); 1471 goto transferred; 1472 } 1473 1474 done: 1475 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1476 return (0); 1477 1478 transferred: 1479 return (1); 1480 } 1481 1482 static void 1483 ehci_pcd_enable(ehci_softc_t *sc) 1484 { 1485 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1486 1487 sc->sc_eintrs |= EHCI_STS_PCD; 1488 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1489 1490 /* acknowledge any PCD interrupt */ 1491 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD); 1492 1493 ehci_root_intr(sc); 1494 } 1495 1496 static void 1497 ehci_interrupt_poll(ehci_softc_t *sc) 1498 { 1499 struct usb_xfer *xfer; 1500 1501 repeat: 1502 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1503 /* 1504 * check if transfer is transferred 1505 */ 1506 if (ehci_check_transfer(xfer)) { 1507 /* queue has been modified */ 1508 goto repeat; 1509 } 1510 } 1511 } 1512 1513 /* 1514 * Some EHCI chips from VIA / ATI seem to trigger interrupts before 1515 * writing back the qTD status, or miss signalling occasionally under 1516 * heavy load. If the host machine is too fast, we can miss 1517 * transaction completion - when we scan the active list the 1518 * transaction still seems to be active. This generally exhibits 1519 * itself as a umass stall that never recovers. 1520 * 1521 * We work around this behaviour by setting up this callback after any 1522 * softintr that completes with transactions still pending, giving us 1523 * another chance to check for completion after the writeback has 1524 * taken place. 1525 */ 1526 static void 1527 ehci_poll_timeout(void *arg) 1528 { 1529 ehci_softc_t *sc = arg; 1530 1531 DPRINTFN(3, "\n"); 1532 ehci_interrupt_poll(sc); 1533 } 1534 1535 /*------------------------------------------------------------------------* 1536 * ehci_interrupt - EHCI interrupt handler 1537 * 1538 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1539 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1540 * is present ! 1541 *------------------------------------------------------------------------*/ 1542 void 1543 ehci_interrupt(ehci_softc_t *sc) 1544 { 1545 uint32_t status; 1546 1547 USB_BUS_LOCK(&sc->sc_bus); 1548 1549 DPRINTFN(16, "real interrupt\n"); 1550 1551 #ifdef USB_DEBUG 1552 if (ehcidebug > 15) { 1553 ehci_dump_regs(sc); 1554 } 1555 #endif 1556 1557 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1558 if (status == 0) { 1559 /* the interrupt was not for us */ 1560 goto done; 1561 } 1562 if (!(status & sc->sc_eintrs)) { 1563 goto done; 1564 } 1565 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */ 1566 1567 status &= sc->sc_eintrs; 1568 1569 if (status & EHCI_STS_HSE) { 1570 printf("%s: unrecoverable error, " 1571 "controller halted\n", __FUNCTION__); 1572 #ifdef USB_DEBUG 1573 ehci_dump_regs(sc); 1574 ehci_dump_isoc(sc); 1575 #endif 1576 } 1577 if (status & EHCI_STS_PCD) { 1578 /* 1579 * Disable PCD interrupt for now, because it will be 1580 * on until the port has been reset. 1581 */ 1582 sc->sc_eintrs &= ~EHCI_STS_PCD; 1583 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1584 1585 ehci_root_intr(sc); 1586 1587 /* do not allow RHSC interrupts > 1 per second */ 1588 usb_callout_reset(&sc->sc_tmo_pcd, hz, 1589 (void *)&ehci_pcd_enable, sc); 1590 } 1591 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA); 1592 1593 if (status != 0) { 1594 /* block unprocessed interrupts */ 1595 sc->sc_eintrs &= ~status; 1596 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1597 printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status); 1598 } 1599 /* poll all the USB transfers */ 1600 ehci_interrupt_poll(sc); 1601 1602 if (sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) { 1603 usb_callout_reset(&sc->sc_tmo_poll, hz / 128, 1604 (void *)&ehci_poll_timeout, sc); 1605 } 1606 1607 done: 1608 USB_BUS_UNLOCK(&sc->sc_bus); 1609 } 1610 1611 /* 1612 * called when a request does not complete 1613 */ 1614 static void 1615 ehci_timeout(void *arg) 1616 { 1617 struct usb_xfer *xfer = arg; 1618 1619 DPRINTF("xfer=%p\n", xfer); 1620 1621 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1622 1623 /* transfer is transferred */ 1624 ehci_device_done(xfer, USB_ERR_TIMEOUT); 1625 } 1626 1627 static void 1628 ehci_do_poll(struct usb_bus *bus) 1629 { 1630 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1631 1632 USB_BUS_LOCK(&sc->sc_bus); 1633 ehci_interrupt_poll(sc); 1634 USB_BUS_UNLOCK(&sc->sc_bus); 1635 } 1636 1637 static void 1638 ehci_setup_standard_chain_sub(struct ehci_std_temp *temp) 1639 { 1640 struct usb_page_search buf_res; 1641 ehci_qtd_t *td; 1642 ehci_qtd_t *td_next; 1643 ehci_qtd_t *td_alt_next; 1644 uint32_t buf_offset; 1645 uint32_t average; 1646 uint32_t len_old; 1647 uint32_t terminate; 1648 uint32_t qtd_altnext; 1649 uint8_t shortpkt_old; 1650 uint8_t precompute; 1651 1652 terminate = temp->sc->sc_terminate_self; 1653 qtd_altnext = temp->sc->sc_terminate_self; 1654 td_alt_next = NULL; 1655 buf_offset = 0; 1656 shortpkt_old = temp->shortpkt; 1657 len_old = temp->len; 1658 precompute = 1; 1659 1660 restart: 1661 1662 td = temp->td; 1663 td_next = temp->td_next; 1664 1665 while (1) { 1666 1667 if (temp->len == 0) { 1668 1669 if (temp->shortpkt) { 1670 break; 1671 } 1672 /* send a Zero Length Packet, ZLP, last */ 1673 1674 temp->shortpkt = 1; 1675 average = 0; 1676 1677 } else { 1678 1679 average = temp->average; 1680 1681 if (temp->len < average) { 1682 if (temp->len % temp->max_frame_size) { 1683 temp->shortpkt = 1; 1684 } 1685 average = temp->len; 1686 } 1687 } 1688 1689 if (td_next == NULL) { 1690 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__); 1691 } 1692 /* get next TD */ 1693 1694 td = td_next; 1695 td_next = td->obj_next; 1696 1697 /* check if we are pre-computing */ 1698 1699 if (precompute) { 1700 1701 /* update remaining length */ 1702 1703 temp->len -= average; 1704 1705 continue; 1706 } 1707 /* fill out current TD */ 1708 1709 td->qtd_status = 1710 temp->qtd_status | 1711 htohc32(temp->sc, EHCI_QTD_IOC | 1712 EHCI_QTD_SET_BYTES(average)); 1713 1714 if (average == 0) { 1715 1716 if (temp->auto_data_toggle == 0) { 1717 1718 /* update data toggle, ZLP case */ 1719 1720 temp->qtd_status ^= 1721 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1722 } 1723 td->len = 0; 1724 1725 td->qtd_buffer[0] = 0; 1726 td->qtd_buffer_hi[0] = 0; 1727 1728 td->qtd_buffer[1] = 0; 1729 td->qtd_buffer_hi[1] = 0; 1730 1731 } else { 1732 1733 uint8_t x; 1734 1735 if (temp->auto_data_toggle == 0) { 1736 1737 /* update data toggle */ 1738 1739 if (((average + temp->max_frame_size - 1) / 1740 temp->max_frame_size) & 1) { 1741 temp->qtd_status ^= 1742 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1743 } 1744 } 1745 td->len = average; 1746 1747 /* update remaining length */ 1748 1749 temp->len -= average; 1750 1751 /* fill out buffer pointers */ 1752 1753 usbd_get_page(temp->pc, buf_offset, &buf_res); 1754 td->qtd_buffer[0] = 1755 htohc32(temp->sc, buf_res.physaddr); 1756 td->qtd_buffer_hi[0] = 0; 1757 1758 x = 1; 1759 1760 while (average > EHCI_PAGE_SIZE) { 1761 average -= EHCI_PAGE_SIZE; 1762 buf_offset += EHCI_PAGE_SIZE; 1763 usbd_get_page(temp->pc, buf_offset, &buf_res); 1764 td->qtd_buffer[x] = 1765 htohc32(temp->sc, 1766 buf_res.physaddr & (~0xFFF)); 1767 td->qtd_buffer_hi[x] = 0; 1768 x++; 1769 } 1770 1771 /* 1772 * NOTE: The "average" variable is never zero after 1773 * exiting the loop above ! 1774 * 1775 * NOTE: We have to subtract one from the offset to 1776 * ensure that we are computing the physical address 1777 * of a valid page ! 1778 */ 1779 buf_offset += average; 1780 usbd_get_page(temp->pc, buf_offset - 1, &buf_res); 1781 td->qtd_buffer[x] = 1782 htohc32(temp->sc, 1783 buf_res.physaddr & (~0xFFF)); 1784 td->qtd_buffer_hi[x] = 0; 1785 } 1786 1787 if (td_next) { 1788 /* link the current TD with the next one */ 1789 td->qtd_next = td_next->qtd_self; 1790 } 1791 td->qtd_altnext = qtd_altnext; 1792 td->alt_next = td_alt_next; 1793 1794 usb_pc_cpu_flush(td->page_cache); 1795 } 1796 1797 if (precompute) { 1798 precompute = 0; 1799 1800 /* setup alt next pointer, if any */ 1801 if (temp->last_frame) { 1802 td_alt_next = NULL; 1803 qtd_altnext = terminate; 1804 } else { 1805 /* we use this field internally */ 1806 td_alt_next = td_next; 1807 if (temp->setup_alt_next) { 1808 qtd_altnext = td_next->qtd_self; 1809 } else { 1810 qtd_altnext = terminate; 1811 } 1812 } 1813 1814 /* restore */ 1815 temp->shortpkt = shortpkt_old; 1816 temp->len = len_old; 1817 goto restart; 1818 } 1819 temp->td = td; 1820 temp->td_next = td_next; 1821 } 1822 1823 static void 1824 ehci_setup_standard_chain(struct usb_xfer *xfer, ehci_qh_t **qh_last) 1825 { 1826 struct ehci_std_temp temp; 1827 struct usb_pipe_methods *methods; 1828 ehci_qh_t *qh; 1829 ehci_qtd_t *td; 1830 uint32_t qh_endp; 1831 uint32_t qh_endphub; 1832 uint32_t x; 1833 1834 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1835 xfer->address, UE_GET_ADDR(xfer->endpointno), 1836 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1837 1838 temp.average = xfer->max_hc_frame_size; 1839 temp.max_frame_size = xfer->max_frame_size; 1840 temp.sc = EHCI_BUS2SC(xfer->xroot->bus); 1841 1842 /* toggle the DMA set we are using */ 1843 xfer->flags_int.curr_dma_set ^= 1; 1844 1845 /* get next DMA set */ 1846 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1847 1848 xfer->td_transfer_first = td; 1849 xfer->td_transfer_cache = td; 1850 1851 temp.td = NULL; 1852 temp.td_next = td; 1853 temp.qtd_status = 0; 1854 temp.last_frame = 0; 1855 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1856 1857 if (xfer->flags_int.control_xfr) { 1858 if (xfer->endpoint->toggle_next) { 1859 /* DATA1 is next */ 1860 temp.qtd_status |= 1861 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1862 } 1863 temp.auto_data_toggle = 0; 1864 } else { 1865 temp.auto_data_toggle = 1; 1866 } 1867 1868 if ((xfer->xroot->udev->parent_hs_hub != NULL) || 1869 (xfer->xroot->udev->address != 0)) { 1870 /* max 3 retries */ 1871 temp.qtd_status |= 1872 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1873 } 1874 /* check if we should prepend a setup message */ 1875 1876 if (xfer->flags_int.control_xfr) { 1877 if (xfer->flags_int.control_hdr) { 1878 1879 temp.qtd_status &= 1880 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1881 temp.qtd_status |= htohc32(temp.sc, 1882 EHCI_QTD_ACTIVE | 1883 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 1884 EHCI_QTD_SET_TOGGLE(0)); 1885 1886 temp.len = xfer->frlengths[0]; 1887 temp.pc = xfer->frbuffers + 0; 1888 temp.shortpkt = temp.len ? 1 : 0; 1889 /* check for last frame */ 1890 if (xfer->nframes == 1) { 1891 /* no STATUS stage yet, SETUP is last */ 1892 if (xfer->flags_int.control_act) { 1893 temp.last_frame = 1; 1894 temp.setup_alt_next = 0; 1895 } 1896 } 1897 ehci_setup_standard_chain_sub(&temp); 1898 } 1899 x = 1; 1900 } else { 1901 x = 0; 1902 } 1903 1904 while (x != xfer->nframes) { 1905 1906 /* DATA0 / DATA1 message */ 1907 1908 temp.len = xfer->frlengths[x]; 1909 temp.pc = xfer->frbuffers + x; 1910 1911 x++; 1912 1913 if (x == xfer->nframes) { 1914 if (xfer->flags_int.control_xfr) { 1915 /* no STATUS stage yet, DATA is last */ 1916 if (xfer->flags_int.control_act) { 1917 temp.last_frame = 1; 1918 temp.setup_alt_next = 0; 1919 } 1920 } else { 1921 temp.last_frame = 1; 1922 temp.setup_alt_next = 0; 1923 } 1924 } 1925 /* keep previous data toggle and error count */ 1926 1927 temp.qtd_status &= 1928 htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1929 EHCI_QTD_SET_TOGGLE(1)); 1930 1931 if (temp.len == 0) { 1932 1933 /* make sure that we send an USB packet */ 1934 1935 temp.shortpkt = 0; 1936 1937 } else { 1938 1939 /* regular data transfer */ 1940 1941 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1942 } 1943 1944 /* set endpoint direction */ 1945 1946 temp.qtd_status |= 1947 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 1948 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1949 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) : 1950 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1951 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT)); 1952 1953 ehci_setup_standard_chain_sub(&temp); 1954 } 1955 1956 /* check if we should append a status stage */ 1957 1958 if (xfer->flags_int.control_xfr && 1959 !xfer->flags_int.control_act) { 1960 1961 /* 1962 * Send a DATA1 message and invert the current endpoint 1963 * direction. 1964 */ 1965 1966 temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1967 EHCI_QTD_SET_TOGGLE(1)); 1968 temp.qtd_status |= 1969 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ? 1970 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1971 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) | 1972 EHCI_QTD_SET_TOGGLE(1)) : 1973 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1974 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) | 1975 EHCI_QTD_SET_TOGGLE(1)); 1976 1977 temp.len = 0; 1978 temp.pc = NULL; 1979 temp.shortpkt = 0; 1980 temp.last_frame = 1; 1981 temp.setup_alt_next = 0; 1982 1983 ehci_setup_standard_chain_sub(&temp); 1984 } 1985 td = temp.td; 1986 1987 /* the last TD terminates the transfer: */ 1988 td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1989 td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1990 1991 usb_pc_cpu_flush(td->page_cache); 1992 1993 /* must have at least one frame! */ 1994 1995 xfer->td_transfer_last = td; 1996 1997 #ifdef USB_DEBUG 1998 if (ehcidebug > 8) { 1999 DPRINTF("nexttog=%d; data before transfer:\n", 2000 xfer->endpoint->toggle_next); 2001 ehci_dump_sqtds(temp.sc, 2002 xfer->td_transfer_first); 2003 } 2004 #endif 2005 2006 methods = xfer->endpoint->methods; 2007 2008 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2009 2010 /* the "qh_link" field is filled when the QH is added */ 2011 2012 qh_endp = 2013 (EHCI_QH_SET_ADDR(xfer->address) | 2014 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 2015 EHCI_QH_SET_MPL(xfer->max_packet_size)); 2016 2017 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 2018 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH); 2019 if (methods != &ehci_device_intr_methods) 2020 qh_endp |= EHCI_QH_SET_NRL(8); 2021 } else { 2022 2023 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) { 2024 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL); 2025 } else { 2026 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW); 2027 } 2028 2029 if (methods == &ehci_device_ctrl_methods) { 2030 qh_endp |= EHCI_QH_CTL; 2031 } 2032 if (methods != &ehci_device_intr_methods) { 2033 /* Only try one time per microframe! */ 2034 qh_endp |= EHCI_QH_SET_NRL(1); 2035 } 2036 } 2037 2038 if (temp.auto_data_toggle == 0) { 2039 /* software computes the data toggle */ 2040 qh_endp |= EHCI_QH_DTC; 2041 } 2042 2043 qh->qh_endp = htohc32(temp.sc, qh_endp); 2044 2045 qh_endphub = 2046 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) | 2047 EHCI_QH_SET_CMASK(xfer->endpoint->usb_cmask) | 2048 EHCI_QH_SET_SMASK(xfer->endpoint->usb_smask) | 2049 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 2050 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no)); 2051 2052 qh->qh_endphub = htohc32(temp.sc, qh_endphub); 2053 qh->qh_curqtd = 0; 2054 2055 /* fill the overlay qTD */ 2056 2057 if (temp.auto_data_toggle && xfer->endpoint->toggle_next) { 2058 /* DATA1 is next */ 2059 qh->qh_qtd.qtd_status = htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 2060 } else { 2061 qh->qh_qtd.qtd_status = 0; 2062 } 2063 2064 td = xfer->td_transfer_first; 2065 2066 qh->qh_qtd.qtd_next = td->qtd_self; 2067 qh->qh_qtd.qtd_altnext = 2068 htohc32(temp.sc, EHCI_LINK_TERMINATE); 2069 2070 usb_pc_cpu_flush(qh->page_cache); 2071 2072 if (xfer->xroot->udev->flags.self_suspended == 0) { 2073 EHCI_APPEND_QH(qh, *qh_last); 2074 } 2075 } 2076 2077 static void 2078 ehci_root_intr(ehci_softc_t *sc) 2079 { 2080 uint16_t i; 2081 uint16_t m; 2082 2083 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2084 2085 /* clear any old interrupt data */ 2086 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2087 2088 /* set bits */ 2089 m = (sc->sc_noport + 1); 2090 if (m > (8 * sizeof(sc->sc_hub_idata))) { 2091 m = (8 * sizeof(sc->sc_hub_idata)); 2092 } 2093 for (i = 1; i < m; i++) { 2094 /* pick out CHANGE bits from the status register */ 2095 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) { 2096 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2097 DPRINTF("port %d changed\n", i); 2098 } 2099 } 2100 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2101 sizeof(sc->sc_hub_idata)); 2102 } 2103 2104 static void 2105 ehci_isoc_fs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2106 { 2107 uint32_t nframes = xfer->nframes; 2108 uint32_t status; 2109 uint32_t *plen = xfer->frlengths; 2110 uint16_t len = 0; 2111 ehci_sitd_t *td = xfer->td_transfer_first; 2112 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos]; 2113 2114 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2115 xfer, xfer->endpoint); 2116 2117 while (nframes--) { 2118 if (td == NULL) { 2119 panic("%s:%d: out of TD's\n", 2120 __FUNCTION__, __LINE__); 2121 } 2122 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2123 pp_last = &sc->sc_isoc_fs_p_last[0]; 2124 } 2125 #ifdef USB_DEBUG 2126 if (ehcidebug > 15) { 2127 DPRINTF("isoc FS-TD\n"); 2128 ehci_dump_sitd(sc, td); 2129 } 2130 #endif 2131 usb_pc_cpu_invalidate(td->page_cache); 2132 status = hc32toh(sc, td->sitd_status); 2133 2134 len = EHCI_SITD_GET_LEN(status); 2135 2136 DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len); 2137 2138 if (*plen >= len) { 2139 len = *plen - len; 2140 } else { 2141 len = 0; 2142 } 2143 2144 *plen = len; 2145 2146 /* remove FS-TD from schedule */ 2147 EHCI_REMOVE_FS_TD(td, *pp_last); 2148 2149 pp_last++; 2150 plen++; 2151 td = td->obj_next; 2152 } 2153 2154 xfer->aframes = xfer->nframes; 2155 } 2156 2157 static void 2158 ehci_isoc_hs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2159 { 2160 uint32_t nframes = xfer->nframes; 2161 uint32_t status; 2162 uint32_t *plen = xfer->frlengths; 2163 uint16_t len = 0; 2164 uint8_t td_no = 0; 2165 ehci_itd_t *td = xfer->td_transfer_first; 2166 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos]; 2167 2168 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2169 xfer, xfer->endpoint); 2170 2171 while (nframes) { 2172 if (td == NULL) { 2173 panic("%s:%d: out of TD's\n", 2174 __FUNCTION__, __LINE__); 2175 } 2176 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2177 pp_last = &sc->sc_isoc_hs_p_last[0]; 2178 } 2179 #ifdef USB_DEBUG 2180 if (ehcidebug > 15) { 2181 DPRINTF("isoc HS-TD\n"); 2182 ehci_dump_itd(sc, td); 2183 } 2184 #endif 2185 2186 usb_pc_cpu_invalidate(td->page_cache); 2187 status = hc32toh(sc, td->itd_status[td_no]); 2188 2189 len = EHCI_ITD_GET_LEN(status); 2190 2191 DPRINTFN(2, "status=0x%08x, len=%u\n", status, len); 2192 2193 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2194 2195 if (*plen >= len) { 2196 /* 2197 * The length is valid. NOTE: The 2198 * complete length is written back 2199 * into the status field, and not the 2200 * remainder like with other transfer 2201 * descriptor types. 2202 */ 2203 } else { 2204 /* Invalid length - truncate */ 2205 len = 0; 2206 } 2207 2208 *plen = len; 2209 plen++; 2210 nframes--; 2211 } 2212 2213 td_no++; 2214 2215 if ((td_no == 8) || (nframes == 0)) { 2216 /* remove HS-TD from schedule */ 2217 EHCI_REMOVE_HS_TD(td, *pp_last); 2218 pp_last++; 2219 2220 td_no = 0; 2221 td = td->obj_next; 2222 } 2223 } 2224 xfer->aframes = xfer->nframes; 2225 } 2226 2227 /* NOTE: "done" can be run two times in a row, 2228 * from close and from interrupt 2229 */ 2230 static void 2231 ehci_device_done(struct usb_xfer *xfer, usb_error_t error) 2232 { 2233 struct usb_pipe_methods *methods = xfer->endpoint->methods; 2234 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2235 2236 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2237 2238 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2239 xfer, xfer->endpoint, error); 2240 2241 if ((methods == &ehci_device_bulk_methods) || 2242 (methods == &ehci_device_ctrl_methods)) { 2243 #ifdef USB_DEBUG 2244 if (ehcidebug > 8) { 2245 DPRINTF("nexttog=%d; data after transfer:\n", 2246 xfer->endpoint->toggle_next); 2247 ehci_dump_sqtds(sc, 2248 xfer->td_transfer_first); 2249 } 2250 #endif 2251 2252 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2253 sc->sc_async_p_last); 2254 } 2255 if (methods == &ehci_device_intr_methods) { 2256 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2257 sc->sc_intr_p_last[xfer->qh_pos]); 2258 } 2259 /* 2260 * Only finish isochronous transfers once which will update 2261 * "xfer->frlengths". 2262 */ 2263 if (xfer->td_transfer_first && 2264 xfer->td_transfer_last) { 2265 if (methods == &ehci_device_isoc_fs_methods) { 2266 ehci_isoc_fs_done(sc, xfer); 2267 } 2268 if (methods == &ehci_device_isoc_hs_methods) { 2269 ehci_isoc_hs_done(sc, xfer); 2270 } 2271 xfer->td_transfer_first = NULL; 2272 xfer->td_transfer_last = NULL; 2273 } 2274 /* dequeue transfer and start next transfer */ 2275 usbd_transfer_done(xfer, error); 2276 } 2277 2278 /*------------------------------------------------------------------------* 2279 * ehci bulk support 2280 *------------------------------------------------------------------------*/ 2281 static void 2282 ehci_device_bulk_open(struct usb_xfer *xfer) 2283 { 2284 return; 2285 } 2286 2287 static void 2288 ehci_device_bulk_close(struct usb_xfer *xfer) 2289 { 2290 ehci_device_done(xfer, USB_ERR_CANCELLED); 2291 } 2292 2293 static void 2294 ehci_device_bulk_enter(struct usb_xfer *xfer) 2295 { 2296 return; 2297 } 2298 2299 static void 2300 ehci_device_bulk_start(struct usb_xfer *xfer) 2301 { 2302 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2303 uint32_t temp; 2304 2305 /* setup TD's and QH */ 2306 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2307 2308 /* put transfer on interrupt queue */ 2309 ehci_transfer_intr_enqueue(xfer); 2310 2311 /* 2312 * XXX Certain nVidia chipsets choke when using the IAAD 2313 * feature too frequently. 2314 */ 2315 if (sc->sc_flags & EHCI_SCFLG_IAADBUG) 2316 return; 2317 2318 /* XXX Performance quirk: Some Host Controllers have a too low 2319 * interrupt rate. Issue an IAAD to stimulate the Host 2320 * Controller after queueing the BULK transfer. 2321 */ 2322 temp = EOREAD4(sc, EHCI_USBCMD); 2323 if (!(temp & EHCI_CMD_IAAD)) 2324 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD); 2325 } 2326 2327 struct usb_pipe_methods ehci_device_bulk_methods = 2328 { 2329 .open = ehci_device_bulk_open, 2330 .close = ehci_device_bulk_close, 2331 .enter = ehci_device_bulk_enter, 2332 .start = ehci_device_bulk_start, 2333 }; 2334 2335 /*------------------------------------------------------------------------* 2336 * ehci control support 2337 *------------------------------------------------------------------------*/ 2338 static void 2339 ehci_device_ctrl_open(struct usb_xfer *xfer) 2340 { 2341 return; 2342 } 2343 2344 static void 2345 ehci_device_ctrl_close(struct usb_xfer *xfer) 2346 { 2347 ehci_device_done(xfer, USB_ERR_CANCELLED); 2348 } 2349 2350 static void 2351 ehci_device_ctrl_enter(struct usb_xfer *xfer) 2352 { 2353 return; 2354 } 2355 2356 static void 2357 ehci_device_ctrl_start(struct usb_xfer *xfer) 2358 { 2359 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2360 2361 /* setup TD's and QH */ 2362 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2363 2364 /* put transfer on interrupt queue */ 2365 ehci_transfer_intr_enqueue(xfer); 2366 } 2367 2368 struct usb_pipe_methods ehci_device_ctrl_methods = 2369 { 2370 .open = ehci_device_ctrl_open, 2371 .close = ehci_device_ctrl_close, 2372 .enter = ehci_device_ctrl_enter, 2373 .start = ehci_device_ctrl_start, 2374 }; 2375 2376 /*------------------------------------------------------------------------* 2377 * ehci interrupt support 2378 *------------------------------------------------------------------------*/ 2379 static void 2380 ehci_device_intr_open(struct usb_xfer *xfer) 2381 { 2382 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2383 uint16_t best; 2384 uint16_t bit; 2385 uint16_t x; 2386 2387 usb_hs_bandwidth_alloc(xfer); 2388 2389 /* 2390 * Find the best QH position corresponding to the given interval: 2391 */ 2392 2393 best = 0; 2394 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 2395 while (bit) { 2396 if (xfer->interval >= bit) { 2397 x = bit; 2398 best = bit; 2399 while (x & bit) { 2400 if (sc->sc_intr_stat[x] < 2401 sc->sc_intr_stat[best]) { 2402 best = x; 2403 } 2404 x++; 2405 } 2406 break; 2407 } 2408 bit >>= 1; 2409 } 2410 2411 sc->sc_intr_stat[best]++; 2412 xfer->qh_pos = best; 2413 2414 DPRINTFN(3, "best=%d interval=%d\n", 2415 best, xfer->interval); 2416 } 2417 2418 static void 2419 ehci_device_intr_close(struct usb_xfer *xfer) 2420 { 2421 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2422 2423 sc->sc_intr_stat[xfer->qh_pos]--; 2424 2425 ehci_device_done(xfer, USB_ERR_CANCELLED); 2426 2427 /* bandwidth must be freed after device done */ 2428 usb_hs_bandwidth_free(xfer); 2429 } 2430 2431 static void 2432 ehci_device_intr_enter(struct usb_xfer *xfer) 2433 { 2434 return; 2435 } 2436 2437 static void 2438 ehci_device_intr_start(struct usb_xfer *xfer) 2439 { 2440 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2441 2442 /* setup TD's and QH */ 2443 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 2444 2445 /* put transfer on interrupt queue */ 2446 ehci_transfer_intr_enqueue(xfer); 2447 } 2448 2449 struct usb_pipe_methods ehci_device_intr_methods = 2450 { 2451 .open = ehci_device_intr_open, 2452 .close = ehci_device_intr_close, 2453 .enter = ehci_device_intr_enter, 2454 .start = ehci_device_intr_start, 2455 }; 2456 2457 /*------------------------------------------------------------------------* 2458 * ehci full speed isochronous support 2459 *------------------------------------------------------------------------*/ 2460 static void 2461 ehci_device_isoc_fs_open(struct usb_xfer *xfer) 2462 { 2463 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2464 ehci_sitd_t *td; 2465 uint32_t sitd_portaddr; 2466 uint8_t ds; 2467 2468 sitd_portaddr = 2469 EHCI_SITD_SET_ADDR(xfer->address) | 2470 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 2471 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 2472 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no); 2473 2474 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 2475 sitd_portaddr |= EHCI_SITD_SET_DIR_IN; 2476 } 2477 sitd_portaddr = htohc32(sc, sitd_portaddr); 2478 2479 /* initialize all TD's */ 2480 2481 for (ds = 0; ds != 2; ds++) { 2482 2483 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2484 2485 td->sitd_portaddr = sitd_portaddr; 2486 2487 /* 2488 * TODO: make some kind of automatic 2489 * SMASK/CMASK selection based on micro-frame 2490 * usage 2491 * 2492 * micro-frame usage (8 microframes per 1ms) 2493 */ 2494 td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE); 2495 2496 usb_pc_cpu_flush(td->page_cache); 2497 } 2498 } 2499 } 2500 2501 static void 2502 ehci_device_isoc_fs_close(struct usb_xfer *xfer) 2503 { 2504 ehci_device_done(xfer, USB_ERR_CANCELLED); 2505 } 2506 2507 static void 2508 ehci_device_isoc_fs_enter(struct usb_xfer *xfer) 2509 { 2510 struct usb_page_search buf_res; 2511 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2512 struct usb_fs_isoc_schedule *fss_start; 2513 struct usb_fs_isoc_schedule *fss_end; 2514 struct usb_fs_isoc_schedule *fss; 2515 ehci_sitd_t *td; 2516 ehci_sitd_t *td_last = NULL; 2517 ehci_sitd_t **pp_last; 2518 uint32_t *plen; 2519 uint32_t buf_offset; 2520 uint32_t nframes; 2521 uint32_t temp; 2522 uint32_t sitd_mask; 2523 uint16_t tlen; 2524 uint8_t sa; 2525 uint8_t sb; 2526 uint8_t error; 2527 2528 #ifdef USB_DEBUG 2529 uint8_t once = 1; 2530 2531 #endif 2532 2533 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2534 xfer, xfer->endpoint->isoc_next, xfer->nframes); 2535 2536 /* get the current frame index */ 2537 2538 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2539 2540 /* 2541 * check if the frame index is within the window where the frames 2542 * will be inserted 2543 */ 2544 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2545 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2546 2547 if ((xfer->endpoint->is_synced == 0) || 2548 (buf_offset < xfer->nframes)) { 2549 /* 2550 * If there is data underflow or the pipe queue is empty we 2551 * schedule the transfer a few frames ahead of the current 2552 * frame position. Else two isochronous transfers might 2553 * overlap. 2554 */ 2555 xfer->endpoint->isoc_next = (nframes + 3) & 2556 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2557 xfer->endpoint->is_synced = 1; 2558 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2559 } 2560 /* 2561 * compute how many milliseconds the insertion is ahead of the 2562 * current frame position: 2563 */ 2564 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2565 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2566 2567 /* 2568 * pre-compute when the isochronous transfer will be finished: 2569 */ 2570 xfer->isoc_time_complete = 2571 usbd_fs_isoc_schedule_isoc_time_expand 2572 (xfer->xroot->udev, &fss_start, &fss_end, nframes) + buf_offset + 2573 xfer->nframes; 2574 2575 /* get the real number of frames */ 2576 2577 nframes = xfer->nframes; 2578 2579 buf_offset = 0; 2580 2581 plen = xfer->frlengths; 2582 2583 /* toggle the DMA set we are using */ 2584 xfer->flags_int.curr_dma_set ^= 1; 2585 2586 /* get next DMA set */ 2587 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2588 xfer->td_transfer_first = td; 2589 2590 pp_last = &sc->sc_isoc_fs_p_last[xfer->endpoint->isoc_next]; 2591 2592 /* store starting position */ 2593 2594 xfer->qh_pos = xfer->endpoint->isoc_next; 2595 2596 fss = fss_start + (xfer->qh_pos % USB_ISOC_TIME_MAX); 2597 2598 while (nframes--) { 2599 if (td == NULL) { 2600 panic("%s:%d: out of TD's\n", 2601 __FUNCTION__, __LINE__); 2602 } 2603 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2604 pp_last = &sc->sc_isoc_fs_p_last[0]; 2605 } 2606 if (fss >= fss_end) { 2607 fss = fss_start; 2608 } 2609 /* reuse sitd_portaddr and sitd_back from last transfer */ 2610 2611 if (*plen > xfer->max_frame_size) { 2612 #ifdef USB_DEBUG 2613 if (once) { 2614 once = 0; 2615 printf("%s: frame length(%d) exceeds %d " 2616 "bytes (frame truncated)\n", 2617 __FUNCTION__, *plen, 2618 xfer->max_frame_size); 2619 } 2620 #endif 2621 *plen = xfer->max_frame_size; 2622 } 2623 /* 2624 * We currently don't care if the ISOCHRONOUS schedule is 2625 * full! 2626 */ 2627 error = usbd_fs_isoc_schedule_alloc(fss, &sa, *plen); 2628 if (error) { 2629 /* 2630 * The FULL speed schedule is FULL! Set length 2631 * to zero. 2632 */ 2633 *plen = 0; 2634 } 2635 if (*plen) { 2636 /* 2637 * only call "usbd_get_page()" when we have a 2638 * non-zero length 2639 */ 2640 usbd_get_page(xfer->frbuffers, buf_offset, &buf_res); 2641 td->sitd_bp[0] = htohc32(sc, buf_res.physaddr); 2642 buf_offset += *plen; 2643 /* 2644 * NOTE: We need to subtract one from the offset so 2645 * that we are on a valid page! 2646 */ 2647 usbd_get_page(xfer->frbuffers, buf_offset - 1, 2648 &buf_res); 2649 temp = buf_res.physaddr & ~0xFFF; 2650 } else { 2651 td->sitd_bp[0] = 0; 2652 temp = 0; 2653 } 2654 2655 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) { 2656 tlen = *plen; 2657 if (tlen <= 188) { 2658 temp |= 1; /* T-count = 1, TP = ALL */ 2659 tlen = 1; 2660 } else { 2661 tlen += 187; 2662 tlen /= 188; 2663 temp |= tlen; /* T-count = [1..6] */ 2664 temp |= 8; /* TP = Begin */ 2665 } 2666 2667 tlen += sa; 2668 2669 if (tlen >= 8) { 2670 sb = 0; 2671 } else { 2672 sb = (1 << tlen); 2673 } 2674 2675 sa = (1 << sa); 2676 sa = (sb - sa) & 0x3F; 2677 sb = 0; 2678 } else { 2679 sb = (-(4 << sa)) & 0xFE; 2680 sa = (1 << sa) & 0x3F; 2681 } 2682 2683 sitd_mask = (EHCI_SITD_SET_SMASK(sa) | 2684 EHCI_SITD_SET_CMASK(sb)); 2685 2686 td->sitd_bp[1] = htohc32(sc, temp); 2687 2688 td->sitd_mask = htohc32(sc, sitd_mask); 2689 2690 if (nframes == 0) { 2691 td->sitd_status = htohc32(sc, 2692 EHCI_SITD_IOC | 2693 EHCI_SITD_ACTIVE | 2694 EHCI_SITD_SET_LEN(*plen)); 2695 } else { 2696 td->sitd_status = htohc32(sc, 2697 EHCI_SITD_ACTIVE | 2698 EHCI_SITD_SET_LEN(*plen)); 2699 } 2700 usb_pc_cpu_flush(td->page_cache); 2701 2702 #ifdef USB_DEBUG 2703 if (ehcidebug > 15) { 2704 DPRINTF("FS-TD %d\n", nframes); 2705 ehci_dump_sitd(sc, td); 2706 } 2707 #endif 2708 /* insert TD into schedule */ 2709 EHCI_APPEND_FS_TD(td, *pp_last); 2710 pp_last++; 2711 2712 plen++; 2713 fss++; 2714 td_last = td; 2715 td = td->obj_next; 2716 } 2717 2718 xfer->td_transfer_last = td_last; 2719 2720 /* update isoc_next */ 2721 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) & 2722 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2723 } 2724 2725 static void 2726 ehci_device_isoc_fs_start(struct usb_xfer *xfer) 2727 { 2728 /* put transfer on interrupt queue */ 2729 ehci_transfer_intr_enqueue(xfer); 2730 } 2731 2732 struct usb_pipe_methods ehci_device_isoc_fs_methods = 2733 { 2734 .open = ehci_device_isoc_fs_open, 2735 .close = ehci_device_isoc_fs_close, 2736 .enter = ehci_device_isoc_fs_enter, 2737 .start = ehci_device_isoc_fs_start, 2738 }; 2739 2740 /*------------------------------------------------------------------------* 2741 * ehci high speed isochronous support 2742 *------------------------------------------------------------------------*/ 2743 static void 2744 ehci_device_isoc_hs_open(struct usb_xfer *xfer) 2745 { 2746 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2747 ehci_itd_t *td; 2748 uint32_t temp; 2749 uint8_t ds; 2750 2751 usb_hs_bandwidth_alloc(xfer); 2752 2753 /* initialize all TD's */ 2754 2755 for (ds = 0; ds != 2; ds++) { 2756 2757 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2758 2759 /* set TD inactive */ 2760 td->itd_status[0] = 0; 2761 td->itd_status[1] = 0; 2762 td->itd_status[2] = 0; 2763 td->itd_status[3] = 0; 2764 td->itd_status[4] = 0; 2765 td->itd_status[5] = 0; 2766 td->itd_status[6] = 0; 2767 td->itd_status[7] = 0; 2768 2769 /* set endpoint and address */ 2770 td->itd_bp[0] = htohc32(sc, 2771 EHCI_ITD_SET_ADDR(xfer->address) | 2772 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno))); 2773 2774 temp = 2775 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF); 2776 2777 /* set direction */ 2778 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 2779 temp |= EHCI_ITD_SET_DIR_IN; 2780 } 2781 /* set maximum packet size */ 2782 td->itd_bp[1] = htohc32(sc, temp); 2783 2784 /* set transfer multiplier */ 2785 td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3); 2786 2787 usb_pc_cpu_flush(td->page_cache); 2788 } 2789 } 2790 } 2791 2792 static void 2793 ehci_device_isoc_hs_close(struct usb_xfer *xfer) 2794 { 2795 ehci_device_done(xfer, USB_ERR_CANCELLED); 2796 2797 /* bandwidth must be freed after device done */ 2798 usb_hs_bandwidth_free(xfer); 2799 } 2800 2801 static void 2802 ehci_device_isoc_hs_enter(struct usb_xfer *xfer) 2803 { 2804 struct usb_page_search buf_res; 2805 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2806 ehci_itd_t *td; 2807 ehci_itd_t *td_last = NULL; 2808 ehci_itd_t **pp_last; 2809 bus_size_t page_addr; 2810 uint32_t *plen; 2811 uint32_t status; 2812 uint32_t buf_offset; 2813 uint32_t nframes; 2814 uint32_t itd_offset[8 + 1]; 2815 uint8_t x; 2816 uint8_t td_no; 2817 uint8_t page_no; 2818 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 2819 2820 #ifdef USB_DEBUG 2821 uint8_t once = 1; 2822 2823 #endif 2824 2825 DPRINTFN(6, "xfer=%p next=%d nframes=%d shift=%d\n", 2826 xfer, xfer->endpoint->isoc_next, xfer->nframes, (int)shift); 2827 2828 /* get the current frame index */ 2829 2830 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2831 2832 /* 2833 * check if the frame index is within the window where the frames 2834 * will be inserted 2835 */ 2836 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2837 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2838 2839 if ((xfer->endpoint->is_synced == 0) || 2840 (buf_offset < (((xfer->nframes << shift) + 7) / 8))) { 2841 /* 2842 * If there is data underflow or the pipe queue is empty we 2843 * schedule the transfer a few frames ahead of the current 2844 * frame position. Else two isochronous transfers might 2845 * overlap. 2846 */ 2847 xfer->endpoint->isoc_next = (nframes + 3) & 2848 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2849 xfer->endpoint->is_synced = 1; 2850 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2851 } 2852 /* 2853 * compute how many milliseconds the insertion is ahead of the 2854 * current frame position: 2855 */ 2856 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2857 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2858 2859 /* 2860 * pre-compute when the isochronous transfer will be finished: 2861 */ 2862 xfer->isoc_time_complete = 2863 usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 2864 (((xfer->nframes << shift) + 7) / 8); 2865 2866 /* get the real number of frames */ 2867 2868 nframes = xfer->nframes; 2869 2870 buf_offset = 0; 2871 td_no = 0; 2872 2873 plen = xfer->frlengths; 2874 2875 /* toggle the DMA set we are using */ 2876 xfer->flags_int.curr_dma_set ^= 1; 2877 2878 /* get next DMA set */ 2879 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2880 xfer->td_transfer_first = td; 2881 2882 pp_last = &sc->sc_isoc_hs_p_last[xfer->endpoint->isoc_next]; 2883 2884 /* store starting position */ 2885 2886 xfer->qh_pos = xfer->endpoint->isoc_next; 2887 2888 while (nframes) { 2889 if (td == NULL) { 2890 panic("%s:%d: out of TD's\n", 2891 __FUNCTION__, __LINE__); 2892 } 2893 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2894 pp_last = &sc->sc_isoc_hs_p_last[0]; 2895 } 2896 /* range check */ 2897 if (*plen > xfer->max_frame_size) { 2898 #ifdef USB_DEBUG 2899 if (once) { 2900 once = 0; 2901 printf("%s: frame length(%d) exceeds %d bytes " 2902 "(frame truncated)\n", 2903 __FUNCTION__, *plen, xfer->max_frame_size); 2904 } 2905 #endif 2906 *plen = xfer->max_frame_size; 2907 } 2908 2909 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2910 status = (EHCI_ITD_SET_LEN(*plen) | 2911 EHCI_ITD_ACTIVE | 2912 EHCI_ITD_SET_PG(0)); 2913 td->itd_status[td_no] = htohc32(sc, status); 2914 itd_offset[td_no] = buf_offset; 2915 buf_offset += *plen; 2916 plen++; 2917 nframes --; 2918 } else { 2919 td->itd_status[td_no] = 0; /* not active */ 2920 itd_offset[td_no] = buf_offset; 2921 } 2922 2923 td_no++; 2924 2925 if ((td_no == 8) || (nframes == 0)) { 2926 2927 /* the rest of the transfers are not active, if any */ 2928 for (x = td_no; x != 8; x++) { 2929 td->itd_status[x] = 0; /* not active */ 2930 } 2931 2932 /* check if there is any data to be transferred */ 2933 if (itd_offset[0] != buf_offset) { 2934 page_no = 0; 2935 itd_offset[td_no] = buf_offset; 2936 2937 /* get first page offset */ 2938 usbd_get_page(xfer->frbuffers, itd_offset[0], &buf_res); 2939 /* get page address */ 2940 page_addr = buf_res.physaddr & ~0xFFF; 2941 /* update page address */ 2942 td->itd_bp[0] &= htohc32(sc, 0xFFF); 2943 td->itd_bp[0] |= htohc32(sc, page_addr); 2944 2945 for (x = 0; x != td_no; x++) { 2946 /* set page number and page offset */ 2947 status = (EHCI_ITD_SET_PG(page_no) | 2948 (buf_res.physaddr & 0xFFF)); 2949 td->itd_status[x] |= htohc32(sc, status); 2950 2951 /* get next page offset */ 2952 if (itd_offset[x + 1] == buf_offset) { 2953 /* 2954 * We subtract one so that 2955 * we don't go off the last 2956 * page! 2957 */ 2958 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 2959 } else { 2960 usbd_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res); 2961 } 2962 2963 /* check if we need a new page */ 2964 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) { 2965 /* new page needed */ 2966 page_addr = buf_res.physaddr & ~0xFFF; 2967 if (page_no == 6) { 2968 panic("%s: too many pages\n", __FUNCTION__); 2969 } 2970 page_no++; 2971 /* update page address */ 2972 td->itd_bp[page_no] &= htohc32(sc, 0xFFF); 2973 td->itd_bp[page_no] |= htohc32(sc, page_addr); 2974 } 2975 } 2976 } 2977 /* set IOC bit if we are complete */ 2978 if (nframes == 0) { 2979 td->itd_status[td_no - 1] |= htohc32(sc, EHCI_ITD_IOC); 2980 } 2981 usb_pc_cpu_flush(td->page_cache); 2982 #ifdef USB_DEBUG 2983 if (ehcidebug > 15) { 2984 DPRINTF("HS-TD %d\n", nframes); 2985 ehci_dump_itd(sc, td); 2986 } 2987 #endif 2988 /* insert TD into schedule */ 2989 EHCI_APPEND_HS_TD(td, *pp_last); 2990 pp_last++; 2991 2992 td_no = 0; 2993 td_last = td; 2994 td = td->obj_next; 2995 } 2996 } 2997 2998 xfer->td_transfer_last = td_last; 2999 3000 /* update isoc_next */ 3001 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) & 3002 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 3003 } 3004 3005 static void 3006 ehci_device_isoc_hs_start(struct usb_xfer *xfer) 3007 { 3008 /* put transfer on interrupt queue */ 3009 ehci_transfer_intr_enqueue(xfer); 3010 } 3011 3012 struct usb_pipe_methods ehci_device_isoc_hs_methods = 3013 { 3014 .open = ehci_device_isoc_hs_open, 3015 .close = ehci_device_isoc_hs_close, 3016 .enter = ehci_device_isoc_hs_enter, 3017 .start = ehci_device_isoc_hs_start, 3018 }; 3019 3020 /*------------------------------------------------------------------------* 3021 * ehci root control support 3022 *------------------------------------------------------------------------* 3023 * Simulate a hardware hub by handling all the necessary requests. 3024 *------------------------------------------------------------------------*/ 3025 3026 static const 3027 struct usb_device_descriptor ehci_devd = 3028 { 3029 sizeof(struct usb_device_descriptor), 3030 UDESC_DEVICE, /* type */ 3031 {0x00, 0x02}, /* USB version */ 3032 UDCLASS_HUB, /* class */ 3033 UDSUBCLASS_HUB, /* subclass */ 3034 UDPROTO_HSHUBSTT, /* protocol */ 3035 64, /* max packet */ 3036 {0}, {0}, {0x00, 0x01}, /* device id */ 3037 1, 2, 0, /* string indicies */ 3038 1 /* # of configurations */ 3039 }; 3040 3041 static const 3042 struct usb_device_qualifier ehci_odevd = 3043 { 3044 sizeof(struct usb_device_qualifier), 3045 UDESC_DEVICE_QUALIFIER, /* type */ 3046 {0x00, 0x02}, /* USB version */ 3047 UDCLASS_HUB, /* class */ 3048 UDSUBCLASS_HUB, /* subclass */ 3049 UDPROTO_FSHUB, /* protocol */ 3050 0, /* max packet */ 3051 0, /* # of configurations */ 3052 0 3053 }; 3054 3055 static const struct ehci_config_desc ehci_confd = { 3056 .confd = { 3057 .bLength = sizeof(struct usb_config_descriptor), 3058 .bDescriptorType = UDESC_CONFIG, 3059 .wTotalLength[0] = sizeof(ehci_confd), 3060 .bNumInterface = 1, 3061 .bConfigurationValue = 1, 3062 .iConfiguration = 0, 3063 .bmAttributes = UC_SELF_POWERED, 3064 .bMaxPower = 0 /* max power */ 3065 }, 3066 .ifcd = { 3067 .bLength = sizeof(struct usb_interface_descriptor), 3068 .bDescriptorType = UDESC_INTERFACE, 3069 .bNumEndpoints = 1, 3070 .bInterfaceClass = UICLASS_HUB, 3071 .bInterfaceSubClass = UISUBCLASS_HUB, 3072 .bInterfaceProtocol = 0, 3073 }, 3074 .endpd = { 3075 .bLength = sizeof(struct usb_endpoint_descriptor), 3076 .bDescriptorType = UDESC_ENDPOINT, 3077 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT, 3078 .bmAttributes = UE_INTERRUPT, 3079 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 3080 .bInterval = 255, 3081 }, 3082 }; 3083 3084 static const 3085 struct usb_hub_descriptor ehci_hubd = 3086 { 3087 0, /* dynamic length */ 3088 UDESC_HUB, 3089 0, 3090 {0, 0}, 3091 0, 3092 0, 3093 {0}, 3094 }; 3095 3096 static void 3097 ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed) 3098 { 3099 uint32_t port; 3100 uint32_t v; 3101 3102 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed); 3103 3104 port = EHCI_PORTSC(index); 3105 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3106 EOWRITE4(sc, port, v | EHCI_PS_PO); 3107 } 3108 3109 static usb_error_t 3110 ehci_roothub_exec(struct usb_device *udev, 3111 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3112 { 3113 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3114 const char *str_ptr; 3115 const void *ptr; 3116 uint32_t port; 3117 uint32_t v; 3118 uint16_t len; 3119 uint16_t i; 3120 uint16_t value; 3121 uint16_t index; 3122 usb_error_t err; 3123 3124 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3125 3126 /* buffer reset */ 3127 ptr = (const void *)&sc->sc_hub_desc; 3128 len = 0; 3129 err = 0; 3130 3131 value = UGETW(req->wValue); 3132 index = UGETW(req->wIndex); 3133 3134 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3135 "wValue=0x%04x wIndex=0x%04x\n", 3136 req->bmRequestType, req->bRequest, 3137 UGETW(req->wLength), value, index); 3138 3139 #define C(x,y) ((x) | ((y) << 8)) 3140 switch (C(req->bRequest, req->bmRequestType)) { 3141 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3142 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3143 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3144 /* 3145 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3146 * for the integrated root hub. 3147 */ 3148 break; 3149 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3150 len = 1; 3151 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3152 break; 3153 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3154 switch (value >> 8) { 3155 case UDESC_DEVICE: 3156 if ((value & 0xff) != 0) { 3157 err = USB_ERR_IOERROR; 3158 goto done; 3159 } 3160 len = sizeof(ehci_devd); 3161 ptr = (const void *)&ehci_devd; 3162 break; 3163 /* 3164 * We can't really operate at another speed, 3165 * but the specification says we need this 3166 * descriptor: 3167 */ 3168 case UDESC_DEVICE_QUALIFIER: 3169 if ((value & 0xff) != 0) { 3170 err = USB_ERR_IOERROR; 3171 goto done; 3172 } 3173 len = sizeof(ehci_odevd); 3174 ptr = (const void *)&ehci_odevd; 3175 break; 3176 3177 case UDESC_CONFIG: 3178 if ((value & 0xff) != 0) { 3179 err = USB_ERR_IOERROR; 3180 goto done; 3181 } 3182 len = sizeof(ehci_confd); 3183 ptr = (const void *)&ehci_confd; 3184 break; 3185 3186 case UDESC_STRING: 3187 switch (value & 0xff) { 3188 case 0: /* Language table */ 3189 str_ptr = "\001"; 3190 break; 3191 3192 case 1: /* Vendor */ 3193 str_ptr = sc->sc_vendor; 3194 break; 3195 3196 case 2: /* Product */ 3197 str_ptr = "EHCI root HUB"; 3198 break; 3199 3200 default: 3201 str_ptr = ""; 3202 break; 3203 } 3204 3205 len = usb_make_str_desc( 3206 sc->sc_hub_desc.temp, 3207 sizeof(sc->sc_hub_desc.temp), 3208 str_ptr); 3209 break; 3210 default: 3211 err = USB_ERR_IOERROR; 3212 goto done; 3213 } 3214 break; 3215 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3216 len = 1; 3217 sc->sc_hub_desc.temp[0] = 0; 3218 break; 3219 case C(UR_GET_STATUS, UT_READ_DEVICE): 3220 len = 2; 3221 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3222 break; 3223 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3224 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3225 len = 2; 3226 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3227 break; 3228 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3229 if (value >= EHCI_MAX_DEVICES) { 3230 err = USB_ERR_IOERROR; 3231 goto done; 3232 } 3233 sc->sc_addr = value; 3234 break; 3235 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3236 if ((value != 0) && (value != 1)) { 3237 err = USB_ERR_IOERROR; 3238 goto done; 3239 } 3240 sc->sc_conf = value; 3241 break; 3242 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3243 break; 3244 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3245 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3246 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3247 err = USB_ERR_IOERROR; 3248 goto done; 3249 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3250 break; 3251 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3252 break; 3253 /* Hub requests */ 3254 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3255 break; 3256 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3257 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3258 3259 if ((index < 1) || 3260 (index > sc->sc_noport)) { 3261 err = USB_ERR_IOERROR; 3262 goto done; 3263 } 3264 port = EHCI_PORTSC(index); 3265 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3266 switch (value) { 3267 case UHF_PORT_ENABLE: 3268 EOWRITE4(sc, port, v & ~EHCI_PS_PE); 3269 break; 3270 case UHF_PORT_SUSPEND: 3271 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) { 3272 3273 /* 3274 * waking up a High Speed device is rather 3275 * complicated if 3276 */ 3277 EOWRITE4(sc, port, v | EHCI_PS_FPR); 3278 } 3279 /* wait 20ms for resume sequence to complete */ 3280 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3281 3282 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP | 3283 EHCI_PS_FPR | (3 << 10) /* High Speed */ )); 3284 3285 /* 4ms settle time */ 3286 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3287 break; 3288 case UHF_PORT_POWER: 3289 EOWRITE4(sc, port, v & ~EHCI_PS_PP); 3290 break; 3291 case UHF_PORT_TEST: 3292 DPRINTFN(3, "clear port test " 3293 "%d\n", index); 3294 break; 3295 case UHF_PORT_INDICATOR: 3296 DPRINTFN(3, "clear port ind " 3297 "%d\n", index); 3298 EOWRITE4(sc, port, v & ~EHCI_PS_PIC); 3299 break; 3300 case UHF_C_PORT_CONNECTION: 3301 EOWRITE4(sc, port, v | EHCI_PS_CSC); 3302 break; 3303 case UHF_C_PORT_ENABLE: 3304 EOWRITE4(sc, port, v | EHCI_PS_PEC); 3305 break; 3306 case UHF_C_PORT_SUSPEND: 3307 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3308 break; 3309 case UHF_C_PORT_OVER_CURRENT: 3310 EOWRITE4(sc, port, v | EHCI_PS_OCC); 3311 break; 3312 case UHF_C_PORT_RESET: 3313 sc->sc_isreset = 0; 3314 break; 3315 default: 3316 err = USB_ERR_IOERROR; 3317 goto done; 3318 } 3319 break; 3320 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3321 if ((value & 0xff) != 0) { 3322 err = USB_ERR_IOERROR; 3323 goto done; 3324 } 3325 v = EREAD4(sc, EHCI_HCSPARAMS); 3326 3327 sc->sc_hub_desc.hubd = ehci_hubd; 3328 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3329 3330 if (EHCI_HCS_PPC(v)) 3331 i = UHD_PWR_INDIVIDUAL; 3332 else 3333 i = UHD_PWR_NO_SWITCH; 3334 3335 if (EHCI_HCS_P_INDICATOR(v)) 3336 i |= UHD_PORT_IND; 3337 3338 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3339 /* XXX can't find out? */ 3340 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200; 3341 /* XXX don't know if ports are removable or not */ 3342 sc->sc_hub_desc.hubd.bDescLength = 3343 8 + ((sc->sc_noport + 7) / 8); 3344 len = sc->sc_hub_desc.hubd.bDescLength; 3345 break; 3346 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3347 len = 16; 3348 bzero(sc->sc_hub_desc.temp, 16); 3349 break; 3350 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3351 DPRINTFN(9, "get port status i=%d\n", 3352 index); 3353 if ((index < 1) || 3354 (index > sc->sc_noport)) { 3355 err = USB_ERR_IOERROR; 3356 goto done; 3357 } 3358 v = EOREAD4(sc, EHCI_PORTSC(index)); 3359 DPRINTFN(9, "port status=0x%04x\n", v); 3360 if (sc->sc_flags & (EHCI_SCFLG_FORCESPEED | EHCI_SCFLG_TT)) { 3361 if ((v & 0xc000000) == 0x8000000) 3362 i = UPS_HIGH_SPEED; 3363 else if ((v & 0xc000000) == 0x4000000) 3364 i = UPS_LOW_SPEED; 3365 else 3366 i = 0; 3367 } else { 3368 i = UPS_HIGH_SPEED; 3369 } 3370 if (v & EHCI_PS_CS) 3371 i |= UPS_CURRENT_CONNECT_STATUS; 3372 if (v & EHCI_PS_PE) 3373 i |= UPS_PORT_ENABLED; 3374 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR)) 3375 i |= UPS_SUSPEND; 3376 if (v & EHCI_PS_OCA) 3377 i |= UPS_OVERCURRENT_INDICATOR; 3378 if (v & EHCI_PS_PR) 3379 i |= UPS_RESET; 3380 if (v & EHCI_PS_PP) 3381 i |= UPS_PORT_POWER; 3382 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3383 i = 0; 3384 if (v & EHCI_PS_CSC) 3385 i |= UPS_C_CONNECT_STATUS; 3386 if (v & EHCI_PS_PEC) 3387 i |= UPS_C_PORT_ENABLED; 3388 if (v & EHCI_PS_OCC) 3389 i |= UPS_C_OVERCURRENT_INDICATOR; 3390 if (v & EHCI_PS_FPR) 3391 i |= UPS_C_SUSPEND; 3392 if (sc->sc_isreset) 3393 i |= UPS_C_PORT_RESET; 3394 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3395 len = sizeof(sc->sc_hub_desc.ps); 3396 break; 3397 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3398 err = USB_ERR_IOERROR; 3399 goto done; 3400 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3401 break; 3402 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3403 if ((index < 1) || 3404 (index > sc->sc_noport)) { 3405 err = USB_ERR_IOERROR; 3406 goto done; 3407 } 3408 port = EHCI_PORTSC(index); 3409 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3410 switch (value) { 3411 case UHF_PORT_ENABLE: 3412 EOWRITE4(sc, port, v | EHCI_PS_PE); 3413 break; 3414 case UHF_PORT_SUSPEND: 3415 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3416 break; 3417 case UHF_PORT_RESET: 3418 DPRINTFN(6, "reset port %d\n", index); 3419 #ifdef USB_DEBUG 3420 if (ehcinohighspeed) { 3421 /* 3422 * Connect USB device to companion 3423 * controller. 3424 */ 3425 ehci_disown(sc, index, 1); 3426 break; 3427 } 3428 #endif 3429 if (EHCI_PS_IS_LOWSPEED(v) && 3430 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3431 /* Low speed device, give up ownership. */ 3432 ehci_disown(sc, index, 1); 3433 break; 3434 } 3435 /* Start reset sequence. */ 3436 v &= ~(EHCI_PS_PE | EHCI_PS_PR); 3437 EOWRITE4(sc, port, v | EHCI_PS_PR); 3438 3439 /* Wait for reset to complete. */ 3440 usb_pause_mtx(&sc->sc_bus.bus_mtx, 3441 USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY)); 3442 3443 /* Terminate reset sequence. */ 3444 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM)) 3445 EOWRITE4(sc, port, v); 3446 3447 /* Wait for HC to complete reset. */ 3448 usb_pause_mtx(&sc->sc_bus.bus_mtx, 3449 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE)); 3450 3451 v = EOREAD4(sc, port); 3452 DPRINTF("ehci after reset, status=0x%08x\n", v); 3453 if (v & EHCI_PS_PR) { 3454 device_printf(sc->sc_bus.bdev, 3455 "port reset timeout\n"); 3456 err = USB_ERR_TIMEOUT; 3457 goto done; 3458 } 3459 if (!(v & EHCI_PS_PE) && 3460 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3461 /* Not a high speed device, give up ownership.*/ 3462 ehci_disown(sc, index, 0); 3463 break; 3464 } 3465 sc->sc_isreset = 1; 3466 DPRINTF("ehci port %d reset, status = 0x%08x\n", 3467 index, v); 3468 break; 3469 3470 case UHF_PORT_POWER: 3471 DPRINTFN(3, "set port power %d\n", index); 3472 EOWRITE4(sc, port, v | EHCI_PS_PP); 3473 break; 3474 3475 case UHF_PORT_TEST: 3476 DPRINTFN(3, "set port test %d\n", index); 3477 break; 3478 3479 case UHF_PORT_INDICATOR: 3480 DPRINTFN(3, "set port ind %d\n", index); 3481 EOWRITE4(sc, port, v | EHCI_PS_PIC); 3482 break; 3483 3484 default: 3485 err = USB_ERR_IOERROR; 3486 goto done; 3487 } 3488 break; 3489 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3490 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3491 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3492 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3493 break; 3494 default: 3495 err = USB_ERR_IOERROR; 3496 goto done; 3497 } 3498 done: 3499 *plength = len; 3500 *pptr = ptr; 3501 return (err); 3502 } 3503 3504 static void 3505 ehci_xfer_setup(struct usb_setup_params *parm) 3506 { 3507 struct usb_page_search page_info; 3508 struct usb_page_cache *pc; 3509 ehci_softc_t *sc; 3510 struct usb_xfer *xfer; 3511 void *last_obj; 3512 uint32_t nqtd; 3513 uint32_t nqh; 3514 uint32_t nsitd; 3515 uint32_t nitd; 3516 uint32_t n; 3517 3518 sc = EHCI_BUS2SC(parm->udev->bus); 3519 xfer = parm->curr_xfer; 3520 3521 nqtd = 0; 3522 nqh = 0; 3523 nsitd = 0; 3524 nitd = 0; 3525 3526 /* 3527 * compute maximum number of some structures 3528 */ 3529 if (parm->methods == &ehci_device_ctrl_methods) { 3530 3531 /* 3532 * The proof for the "nqtd" formula is illustrated like 3533 * this: 3534 * 3535 * +------------------------------------+ 3536 * | | 3537 * | |remainder -> | 3538 * | +-----+---+ | 3539 * | | xxx | x | frm 0 | 3540 * | +-----+---++ | 3541 * | | xxx | xx | frm 1 | 3542 * | +-----+----+ | 3543 * | ... | 3544 * +------------------------------------+ 3545 * 3546 * "xxx" means a completely full USB transfer descriptor 3547 * 3548 * "x" and "xx" means a short USB packet 3549 * 3550 * For the remainder of an USB transfer modulo 3551 * "max_data_length" we need two USB transfer descriptors. 3552 * One to transfer the remaining data and one to finalise 3553 * with a zero length packet in case the "force_short_xfer" 3554 * flag is set. We only need two USB transfer descriptors in 3555 * the case where the transfer length of the first one is a 3556 * factor of "max_frame_size". The rest of the needed USB 3557 * transfer descriptors is given by the buffer size divided 3558 * by the maximum data payload. 3559 */ 3560 parm->hc_max_packet_size = 0x400; 3561 parm->hc_max_packet_count = 1; 3562 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3563 xfer->flags_int.bdma_enable = 1; 3564 3565 usbd_transfer_setup_sub(parm); 3566 3567 nqh = 1; 3568 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */ 3569 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3570 3571 } else if (parm->methods == &ehci_device_bulk_methods) { 3572 3573 parm->hc_max_packet_size = 0x400; 3574 parm->hc_max_packet_count = 1; 3575 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3576 xfer->flags_int.bdma_enable = 1; 3577 3578 usbd_transfer_setup_sub(parm); 3579 3580 nqh = 1; 3581 nqtd = ((2 * xfer->nframes) 3582 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3583 3584 } else if (parm->methods == &ehci_device_intr_methods) { 3585 3586 if (parm->speed == USB_SPEED_HIGH) { 3587 parm->hc_max_packet_size = 0x400; 3588 parm->hc_max_packet_count = 3; 3589 } else if (parm->speed == USB_SPEED_FULL) { 3590 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME; 3591 parm->hc_max_packet_count = 1; 3592 } else { 3593 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8; 3594 parm->hc_max_packet_count = 1; 3595 } 3596 3597 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3598 xfer->flags_int.bdma_enable = 1; 3599 3600 usbd_transfer_setup_sub(parm); 3601 3602 nqh = 1; 3603 nqtd = ((2 * xfer->nframes) 3604 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3605 3606 } else if (parm->methods == &ehci_device_isoc_fs_methods) { 3607 3608 parm->hc_max_packet_size = 0x3FF; 3609 parm->hc_max_packet_count = 1; 3610 parm->hc_max_frame_size = 0x3FF; 3611 xfer->flags_int.bdma_enable = 1; 3612 3613 usbd_transfer_setup_sub(parm); 3614 3615 nsitd = xfer->nframes; 3616 3617 } else if (parm->methods == &ehci_device_isoc_hs_methods) { 3618 3619 parm->hc_max_packet_size = 0x400; 3620 parm->hc_max_packet_count = 3; 3621 parm->hc_max_frame_size = 0xC00; 3622 xfer->flags_int.bdma_enable = 1; 3623 3624 usbd_transfer_setup_sub(parm); 3625 3626 nitd = ((xfer->nframes + 7) / 8) << 3627 usbd_xfer_get_fps_shift(xfer); 3628 3629 } else { 3630 3631 parm->hc_max_packet_size = 0x400; 3632 parm->hc_max_packet_count = 1; 3633 parm->hc_max_frame_size = 0x400; 3634 3635 usbd_transfer_setup_sub(parm); 3636 } 3637 3638 alloc_dma_set: 3639 3640 if (parm->err) { 3641 return; 3642 } 3643 /* 3644 * Allocate queue heads and transfer descriptors 3645 */ 3646 last_obj = NULL; 3647 3648 if (usbd_transfer_setup_sub_malloc( 3649 parm, &pc, sizeof(ehci_itd_t), 3650 EHCI_ITD_ALIGN, nitd)) { 3651 parm->err = USB_ERR_NOMEM; 3652 return; 3653 } 3654 if (parm->buf) { 3655 for (n = 0; n != nitd; n++) { 3656 ehci_itd_t *td; 3657 3658 usbd_get_page(pc + n, 0, &page_info); 3659 3660 td = page_info.buffer; 3661 3662 /* init TD */ 3663 td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD); 3664 td->obj_next = last_obj; 3665 td->page_cache = pc + n; 3666 3667 last_obj = td; 3668 3669 usb_pc_cpu_flush(pc + n); 3670 } 3671 } 3672 if (usbd_transfer_setup_sub_malloc( 3673 parm, &pc, sizeof(ehci_sitd_t), 3674 EHCI_SITD_ALIGN, nsitd)) { 3675 parm->err = USB_ERR_NOMEM; 3676 return; 3677 } 3678 if (parm->buf) { 3679 for (n = 0; n != nsitd; n++) { 3680 ehci_sitd_t *td; 3681 3682 usbd_get_page(pc + n, 0, &page_info); 3683 3684 td = page_info.buffer; 3685 3686 /* init TD */ 3687 td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD); 3688 td->obj_next = last_obj; 3689 td->page_cache = pc + n; 3690 3691 last_obj = td; 3692 3693 usb_pc_cpu_flush(pc + n); 3694 } 3695 } 3696 if (usbd_transfer_setup_sub_malloc( 3697 parm, &pc, sizeof(ehci_qtd_t), 3698 EHCI_QTD_ALIGN, nqtd)) { 3699 parm->err = USB_ERR_NOMEM; 3700 return; 3701 } 3702 if (parm->buf) { 3703 for (n = 0; n != nqtd; n++) { 3704 ehci_qtd_t *qtd; 3705 3706 usbd_get_page(pc + n, 0, &page_info); 3707 3708 qtd = page_info.buffer; 3709 3710 /* init TD */ 3711 qtd->qtd_self = htohc32(sc, page_info.physaddr); 3712 qtd->obj_next = last_obj; 3713 qtd->page_cache = pc + n; 3714 3715 last_obj = qtd; 3716 3717 usb_pc_cpu_flush(pc + n); 3718 } 3719 } 3720 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3721 3722 last_obj = NULL; 3723 3724 if (usbd_transfer_setup_sub_malloc( 3725 parm, &pc, sizeof(ehci_qh_t), 3726 EHCI_QH_ALIGN, nqh)) { 3727 parm->err = USB_ERR_NOMEM; 3728 return; 3729 } 3730 if (parm->buf) { 3731 for (n = 0; n != nqh; n++) { 3732 ehci_qh_t *qh; 3733 3734 usbd_get_page(pc + n, 0, &page_info); 3735 3736 qh = page_info.buffer; 3737 3738 /* init QH */ 3739 qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH); 3740 qh->obj_next = last_obj; 3741 qh->page_cache = pc + n; 3742 3743 last_obj = qh; 3744 3745 usb_pc_cpu_flush(pc + n); 3746 } 3747 } 3748 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3749 3750 if (!xfer->flags_int.curr_dma_set) { 3751 xfer->flags_int.curr_dma_set = 1; 3752 goto alloc_dma_set; 3753 } 3754 } 3755 3756 static void 3757 ehci_xfer_unsetup(struct usb_xfer *xfer) 3758 { 3759 return; 3760 } 3761 3762 static void 3763 ehci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3764 struct usb_endpoint *ep) 3765 { 3766 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3767 3768 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3769 ep, udev->address, 3770 edesc->bEndpointAddress, udev->flags.usb_mode, 3771 sc->sc_addr); 3772 3773 if (udev->flags.usb_mode != USB_MODE_HOST) { 3774 /* not supported */ 3775 return; 3776 } 3777 if (udev->device_index != sc->sc_addr) { 3778 3779 if ((udev->speed != USB_SPEED_HIGH) && 3780 ((udev->hs_hub_addr == 0) || 3781 (udev->hs_port_no == 0) || 3782 (udev->parent_hs_hub == NULL) || 3783 (udev->parent_hs_hub->hub == NULL))) { 3784 /* We need a transaction translator */ 3785 goto done; 3786 } 3787 switch (edesc->bmAttributes & UE_XFERTYPE) { 3788 case UE_CONTROL: 3789 ep->methods = &ehci_device_ctrl_methods; 3790 break; 3791 case UE_INTERRUPT: 3792 ep->methods = &ehci_device_intr_methods; 3793 break; 3794 case UE_ISOCHRONOUS: 3795 if (udev->speed == USB_SPEED_HIGH) { 3796 ep->methods = &ehci_device_isoc_hs_methods; 3797 } else if (udev->speed == USB_SPEED_FULL) { 3798 ep->methods = &ehci_device_isoc_fs_methods; 3799 } 3800 break; 3801 case UE_BULK: 3802 ep->methods = &ehci_device_bulk_methods; 3803 break; 3804 default: 3805 /* do nothing */ 3806 break; 3807 } 3808 } 3809 done: 3810 return; 3811 } 3812 3813 static void 3814 ehci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3815 { 3816 /* 3817 * Wait until the hardware has finished any possible use of 3818 * the transfer descriptor(s) and QH 3819 */ 3820 *pus = (188); /* microseconds */ 3821 } 3822 3823 static void 3824 ehci_device_resume(struct usb_device *udev) 3825 { 3826 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3827 struct usb_xfer *xfer; 3828 struct usb_pipe_methods *methods; 3829 3830 DPRINTF("\n"); 3831 3832 USB_BUS_LOCK(udev->bus); 3833 3834 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3835 3836 if (xfer->xroot->udev == udev) { 3837 3838 methods = xfer->endpoint->methods; 3839 3840 if ((methods == &ehci_device_bulk_methods) || 3841 (methods == &ehci_device_ctrl_methods)) { 3842 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3843 sc->sc_async_p_last); 3844 } 3845 if (methods == &ehci_device_intr_methods) { 3846 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3847 sc->sc_intr_p_last[xfer->qh_pos]); 3848 } 3849 } 3850 } 3851 3852 USB_BUS_UNLOCK(udev->bus); 3853 3854 return; 3855 } 3856 3857 static void 3858 ehci_device_suspend(struct usb_device *udev) 3859 { 3860 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3861 struct usb_xfer *xfer; 3862 struct usb_pipe_methods *methods; 3863 3864 DPRINTF("\n"); 3865 3866 USB_BUS_LOCK(udev->bus); 3867 3868 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3869 3870 if (xfer->xroot->udev == udev) { 3871 3872 methods = xfer->endpoint->methods; 3873 3874 if ((methods == &ehci_device_bulk_methods) || 3875 (methods == &ehci_device_ctrl_methods)) { 3876 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3877 sc->sc_async_p_last); 3878 } 3879 if (methods == &ehci_device_intr_methods) { 3880 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3881 sc->sc_intr_p_last[xfer->qh_pos]); 3882 } 3883 } 3884 } 3885 3886 USB_BUS_UNLOCK(udev->bus); 3887 3888 return; 3889 } 3890 3891 static void 3892 ehci_set_hw_power(struct usb_bus *bus) 3893 { 3894 ehci_softc_t *sc = EHCI_BUS2SC(bus); 3895 uint32_t temp; 3896 uint32_t flags; 3897 3898 DPRINTF("\n"); 3899 3900 USB_BUS_LOCK(bus); 3901 3902 flags = bus->hw_power_state; 3903 3904 temp = EOREAD4(sc, EHCI_USBCMD); 3905 3906 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 3907 3908 if (flags & (USB_HW_POWER_CONTROL | 3909 USB_HW_POWER_BULK)) { 3910 DPRINTF("Async is active\n"); 3911 temp |= EHCI_CMD_ASE; 3912 } 3913 if (flags & (USB_HW_POWER_INTERRUPT | 3914 USB_HW_POWER_ISOC)) { 3915 DPRINTF("Periodic is active\n"); 3916 temp |= EHCI_CMD_PSE; 3917 } 3918 EOWRITE4(sc, EHCI_USBCMD, temp); 3919 3920 USB_BUS_UNLOCK(bus); 3921 3922 return; 3923 } 3924 3925 struct usb_bus_methods ehci_bus_methods = 3926 { 3927 .endpoint_init = ehci_ep_init, 3928 .xfer_setup = ehci_xfer_setup, 3929 .xfer_unsetup = ehci_xfer_unsetup, 3930 .get_dma_delay = ehci_get_dma_delay, 3931 .device_resume = ehci_device_resume, 3932 .device_suspend = ehci_device_suspend, 3933 .set_hw_power = ehci_set_hw_power, 3934 .roothub_exec = ehci_roothub_exec, 3935 .xfer_poll = ehci_do_poll, 3936 }; 3937