1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains the driver for the ATMEGA series USB OTG Controller. This 31 * driver currently only supports the DCI mode of the USB hardware. 32 */ 33 34 /* 35 * NOTE: When the chip detects BUS-reset it will also reset the 36 * endpoints, Function-address and more. 37 */ 38 39 #ifdef USB_GLOBAL_INCLUDE_FILE 40 #include USB_GLOBAL_INCLUDE_FILE 41 #else 42 #include <sys/stdint.h> 43 #include <sys/stddef.h> 44 #include <sys/param.h> 45 #include <sys/queue.h> 46 #include <sys/types.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/bus.h> 50 #include <sys/module.h> 51 #include <sys/lock.h> 52 #include <sys/mutex.h> 53 #include <sys/condvar.h> 54 #include <sys/sysctl.h> 55 #include <sys/sx.h> 56 #include <sys/unistd.h> 57 #include <sys/callout.h> 58 #include <sys/malloc.h> 59 #include <sys/priv.h> 60 61 #include <dev/usb/usb.h> 62 #include <dev/usb/usbdi.h> 63 64 #define USB_DEBUG_VAR atmegadci_debug 65 66 #include <dev/usb/usb_core.h> 67 #include <dev/usb/usb_debug.h> 68 #include <dev/usb/usb_busdma.h> 69 #include <dev/usb/usb_process.h> 70 #include <dev/usb/usb_transfer.h> 71 #include <dev/usb/usb_device.h> 72 #include <dev/usb/usb_hub.h> 73 #include <dev/usb/usb_util.h> 74 75 #include <dev/usb/usb_controller.h> 76 #include <dev/usb/usb_bus.h> 77 #endif /* USB_GLOBAL_INCLUDE_FILE */ 78 79 #include <dev/usb/controller/atmegadci.h> 80 81 #define ATMEGA_BUS2SC(bus) \ 82 ((struct atmegadci_softc *)(((uint8_t *)(bus)) - \ 83 ((uint8_t *)&(((struct atmegadci_softc *)0)->sc_bus)))) 84 85 #define ATMEGA_PC2SC(pc) \ 86 ATMEGA_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 87 88 #ifdef USB_DEBUG 89 static int atmegadci_debug = 0; 90 91 static SYSCTL_NODE(_hw_usb, OID_AUTO, atmegadci, CTLFLAG_RW, 0, 92 "USB ATMEGA DCI"); 93 SYSCTL_INT(_hw_usb_atmegadci, OID_AUTO, debug, CTLFLAG_RWTUN, 94 &atmegadci_debug, 0, "ATMEGA DCI debug level"); 95 #endif 96 97 #define ATMEGA_INTR_ENDPT 1 98 99 /* prototypes */ 100 101 static const struct usb_bus_methods atmegadci_bus_methods; 102 static const struct usb_pipe_methods atmegadci_device_non_isoc_methods; 103 static const struct usb_pipe_methods atmegadci_device_isoc_fs_methods; 104 105 static atmegadci_cmd_t atmegadci_setup_rx; 106 static atmegadci_cmd_t atmegadci_data_rx; 107 static atmegadci_cmd_t atmegadci_data_tx; 108 static atmegadci_cmd_t atmegadci_data_tx_sync; 109 static void atmegadci_device_done(struct usb_xfer *, usb_error_t); 110 static void atmegadci_do_poll(struct usb_bus *); 111 static void atmegadci_standard_done(struct usb_xfer *); 112 static void atmegadci_root_intr(struct atmegadci_softc *sc); 113 114 /* 115 * Here is a list of what the chip supports: 116 */ 117 static const struct usb_hw_ep_profile 118 atmegadci_ep_profile[2] = { 119 120 [0] = { 121 .max_in_frame_size = 64, 122 .max_out_frame_size = 64, 123 .is_simplex = 1, 124 .support_control = 1, 125 }, 126 [1] = { 127 .max_in_frame_size = 64, 128 .max_out_frame_size = 64, 129 .is_simplex = 1, 130 .support_bulk = 1, 131 .support_interrupt = 1, 132 .support_isochronous = 1, 133 .support_in = 1, 134 .support_out = 1, 135 }, 136 }; 137 138 static void 139 atmegadci_get_hw_ep_profile(struct usb_device *udev, 140 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 141 { 142 if (ep_addr == 0) 143 *ppf = atmegadci_ep_profile; 144 else if (ep_addr < ATMEGA_EP_MAX) 145 *ppf = atmegadci_ep_profile + 1; 146 else 147 *ppf = NULL; 148 } 149 150 static void 151 atmegadci_clocks_on(struct atmegadci_softc *sc) 152 { 153 if (sc->sc_flags.clocks_off && 154 sc->sc_flags.port_powered) { 155 156 DPRINTFN(5, "\n"); 157 158 /* turn on clocks */ 159 (sc->sc_clocks_on) (&sc->sc_bus); 160 161 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 162 ATMEGA_USBCON_USBE | 163 ATMEGA_USBCON_OTGPADE | 164 ATMEGA_USBCON_VBUSTE); 165 166 sc->sc_flags.clocks_off = 0; 167 168 /* enable transceiver ? */ 169 } 170 } 171 172 static void 173 atmegadci_clocks_off(struct atmegadci_softc *sc) 174 { 175 if (!sc->sc_flags.clocks_off) { 176 177 DPRINTFN(5, "\n"); 178 179 /* disable Transceiver ? */ 180 181 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 182 ATMEGA_USBCON_USBE | 183 ATMEGA_USBCON_OTGPADE | 184 ATMEGA_USBCON_FRZCLK | 185 ATMEGA_USBCON_VBUSTE); 186 187 /* turn clocks off */ 188 (sc->sc_clocks_off) (&sc->sc_bus); 189 190 sc->sc_flags.clocks_off = 1; 191 } 192 } 193 194 static void 195 atmegadci_pull_up(struct atmegadci_softc *sc) 196 { 197 /* pullup D+, if possible */ 198 199 if (!sc->sc_flags.d_pulled_up && 200 sc->sc_flags.port_powered) { 201 sc->sc_flags.d_pulled_up = 1; 202 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, 0); 203 } 204 } 205 206 static void 207 atmegadci_pull_down(struct atmegadci_softc *sc) 208 { 209 /* pulldown D+, if possible */ 210 211 if (sc->sc_flags.d_pulled_up) { 212 sc->sc_flags.d_pulled_up = 0; 213 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH); 214 } 215 } 216 217 static void 218 atmegadci_wakeup_peer(struct atmegadci_softc *sc) 219 { 220 uint8_t temp; 221 222 if (!sc->sc_flags.status_suspend) { 223 return; 224 } 225 226 temp = ATMEGA_READ_1(sc, ATMEGA_UDCON); 227 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, temp | ATMEGA_UDCON_RMWKUP); 228 229 /* wait 8 milliseconds */ 230 /* Wait for reset to complete. */ 231 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 232 233 /* hardware should have cleared RMWKUP bit */ 234 } 235 236 static void 237 atmegadci_set_address(struct atmegadci_softc *sc, uint8_t addr) 238 { 239 DPRINTFN(5, "addr=%d\n", addr); 240 241 addr |= ATMEGA_UDADDR_ADDEN; 242 243 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, addr); 244 } 245 246 static uint8_t 247 atmegadci_setup_rx(struct atmegadci_td *td) 248 { 249 struct atmegadci_softc *sc; 250 struct usb_device_request req; 251 uint16_t count; 252 uint8_t temp; 253 254 /* get pointer to softc */ 255 sc = ATMEGA_PC2SC(td->pc); 256 257 /* select endpoint number */ 258 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 259 260 /* check endpoint status */ 261 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 262 263 DPRINTFN(5, "UEINTX=0x%02x\n", temp); 264 265 if (!(temp & ATMEGA_UEINTX_RXSTPI)) { 266 goto not_complete; 267 } 268 /* clear did stall */ 269 td->did_stall = 0; 270 /* get the packet byte count */ 271 count = 272 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) | 273 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX)); 274 275 /* mask away undefined bits */ 276 count &= 0x7FF; 277 278 /* verify data length */ 279 if (count != td->remainder) { 280 DPRINTFN(0, "Invalid SETUP packet " 281 "length, %d bytes\n", count); 282 goto not_complete; 283 } 284 if (count != sizeof(req)) { 285 DPRINTFN(0, "Unsupported SETUP packet " 286 "length, %d bytes\n", count); 287 goto not_complete; 288 } 289 /* receive data */ 290 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX, 291 (void *)&req, sizeof(req)); 292 293 /* copy data into real buffer */ 294 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 295 296 td->offset = sizeof(req); 297 td->remainder = 0; 298 299 /* sneak peek the set address */ 300 if ((req.bmRequestType == UT_WRITE_DEVICE) && 301 (req.bRequest == UR_SET_ADDRESS)) { 302 sc->sc_dv_addr = req.wValue[0] & 0x7F; 303 /* must write address before ZLP */ 304 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, sc->sc_dv_addr); 305 } else { 306 sc->sc_dv_addr = 0xFF; 307 } 308 309 /* Clear SETUP packet interrupt and all other previous interrupts */ 310 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0); 311 return (0); /* complete */ 312 313 not_complete: 314 /* abort any ongoing transfer */ 315 if (!td->did_stall) { 316 DPRINTFN(5, "stalling\n"); 317 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 318 ATMEGA_UECONX_EPEN | 319 ATMEGA_UECONX_STALLRQ); 320 td->did_stall = 1; 321 } 322 if (temp & ATMEGA_UEINTX_RXSTPI) { 323 /* clear SETUP packet interrupt */ 324 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ~ATMEGA_UEINTX_RXSTPI); 325 } 326 /* we only want to know if there is a SETUP packet */ 327 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, ATMEGA_UEIENX_RXSTPE); 328 return (1); /* not complete */ 329 } 330 331 static uint8_t 332 atmegadci_data_rx(struct atmegadci_td *td) 333 { 334 struct atmegadci_softc *sc; 335 struct usb_page_search buf_res; 336 uint16_t count; 337 uint8_t temp; 338 uint8_t to; 339 uint8_t got_short; 340 341 to = 3; /* don't loop forever! */ 342 got_short = 0; 343 344 /* get pointer to softc */ 345 sc = ATMEGA_PC2SC(td->pc); 346 347 /* select endpoint number */ 348 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 349 350 repeat: 351 /* check if any of the FIFO banks have data */ 352 /* check endpoint status */ 353 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 354 355 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder); 356 357 if (temp & ATMEGA_UEINTX_RXSTPI) { 358 if (td->remainder == 0) { 359 /* 360 * We are actually complete and have 361 * received the next SETUP 362 */ 363 DPRINTFN(5, "faking complete\n"); 364 return (0); /* complete */ 365 } 366 /* 367 * USB Host Aborted the transfer. 368 */ 369 td->error = 1; 370 return (0); /* complete */ 371 } 372 /* check status */ 373 if (!(temp & (ATMEGA_UEINTX_FIFOCON | 374 ATMEGA_UEINTX_RXOUTI))) { 375 /* no data */ 376 goto not_complete; 377 } 378 /* get the packet byte count */ 379 count = 380 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) | 381 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX)); 382 383 /* mask away undefined bits */ 384 count &= 0x7FF; 385 386 /* verify the packet byte count */ 387 if (count != td->max_packet_size) { 388 if (count < td->max_packet_size) { 389 /* we have a short packet */ 390 td->short_pkt = 1; 391 got_short = 1; 392 } else { 393 /* invalid USB packet */ 394 td->error = 1; 395 return (0); /* we are complete */ 396 } 397 } 398 /* verify the packet byte count */ 399 if (count > td->remainder) { 400 /* invalid USB packet */ 401 td->error = 1; 402 return (0); /* we are complete */ 403 } 404 while (count > 0) { 405 usbd_get_page(td->pc, td->offset, &buf_res); 406 407 /* get correct length */ 408 if (buf_res.length > count) { 409 buf_res.length = count; 410 } 411 /* receive data */ 412 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX, 413 buf_res.buffer, buf_res.length); 414 415 /* update counters */ 416 count -= buf_res.length; 417 td->offset += buf_res.length; 418 td->remainder -= buf_res.length; 419 } 420 421 /* clear OUT packet interrupt */ 422 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_RXOUTI ^ 0xFF); 423 424 /* release FIFO bank */ 425 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_FIFOCON ^ 0xFF); 426 427 /* check if we are complete */ 428 if ((td->remainder == 0) || got_short) { 429 if (td->short_pkt) { 430 /* we are complete */ 431 return (0); 432 } 433 /* else need to receive a zero length packet */ 434 } 435 if (--to) { 436 goto repeat; 437 } 438 not_complete: 439 /* we only want to know if there is a SETUP packet or OUT packet */ 440 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 441 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_RXOUTE); 442 return (1); /* not complete */ 443 } 444 445 static uint8_t 446 atmegadci_data_tx(struct atmegadci_td *td) 447 { 448 struct atmegadci_softc *sc; 449 struct usb_page_search buf_res; 450 uint16_t count; 451 uint8_t to; 452 uint8_t temp; 453 454 to = 3; /* don't loop forever! */ 455 456 /* get pointer to softc */ 457 sc = ATMEGA_PC2SC(td->pc); 458 459 /* select endpoint number */ 460 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 461 462 repeat: 463 464 /* check endpoint status */ 465 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 466 467 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder); 468 469 if (temp & ATMEGA_UEINTX_RXSTPI) { 470 /* 471 * The current transfer was aborted 472 * by the USB Host 473 */ 474 td->error = 1; 475 return (0); /* complete */ 476 } 477 478 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 479 if (temp & 3) { 480 /* cannot write any data - a bank is busy */ 481 goto not_complete; 482 } 483 484 count = td->max_packet_size; 485 if (td->remainder < count) { 486 /* we have a short packet */ 487 td->short_pkt = 1; 488 count = td->remainder; 489 } 490 while (count > 0) { 491 492 usbd_get_page(td->pc, td->offset, &buf_res); 493 494 /* get correct length */ 495 if (buf_res.length > count) { 496 buf_res.length = count; 497 } 498 /* transmit data */ 499 ATMEGA_WRITE_MULTI_1(sc, ATMEGA_UEDATX, 500 buf_res.buffer, buf_res.length); 501 502 /* update counters */ 503 count -= buf_res.length; 504 td->offset += buf_res.length; 505 td->remainder -= buf_res.length; 506 } 507 508 /* clear IN packet interrupt */ 509 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_TXINI); 510 511 /* allocate FIFO bank */ 512 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_FIFOCON); 513 514 /* check remainder */ 515 if (td->remainder == 0) { 516 if (td->short_pkt) { 517 return (0); /* complete */ 518 } 519 /* else we need to transmit a short packet */ 520 } 521 if (--to) { 522 goto repeat; 523 } 524 not_complete: 525 /* we only want to know if there is a SETUP packet or free IN packet */ 526 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 527 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE); 528 return (1); /* not complete */ 529 } 530 531 static uint8_t 532 atmegadci_data_tx_sync(struct atmegadci_td *td) 533 { 534 struct atmegadci_softc *sc; 535 uint8_t temp; 536 537 /* get pointer to softc */ 538 sc = ATMEGA_PC2SC(td->pc); 539 540 /* select endpoint number */ 541 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 542 543 /* check endpoint status */ 544 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 545 546 DPRINTFN(5, "temp=0x%02x\n", temp); 547 548 if (temp & ATMEGA_UEINTX_RXSTPI) { 549 DPRINTFN(5, "faking complete\n"); 550 /* Race condition */ 551 return (0); /* complete */ 552 } 553 /* 554 * The control endpoint has only got one bank, so if that bank 555 * is free the packet has been transferred! 556 */ 557 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 558 if (temp & 3) { 559 /* cannot write any data - a bank is busy */ 560 goto not_complete; 561 } 562 if (sc->sc_dv_addr != 0xFF) { 563 /* set new address */ 564 atmegadci_set_address(sc, sc->sc_dv_addr); 565 } 566 return (0); /* complete */ 567 568 not_complete: 569 /* we only want to know if there is a SETUP packet or free IN packet */ 570 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 571 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE); 572 return (1); /* not complete */ 573 } 574 575 static uint8_t 576 atmegadci_xfer_do_fifo(struct usb_xfer *xfer) 577 { 578 struct atmegadci_td *td; 579 580 DPRINTFN(9, "\n"); 581 582 td = xfer->td_transfer_cache; 583 while (1) { 584 if ((td->func) (td)) { 585 /* operation in progress */ 586 break; 587 } 588 if (((void *)td) == xfer->td_transfer_last) { 589 goto done; 590 } 591 if (td->error) { 592 goto done; 593 } else if (td->remainder > 0) { 594 /* 595 * We had a short transfer. If there is no alternate 596 * next, stop processing ! 597 */ 598 if (!td->alt_next) { 599 goto done; 600 } 601 } 602 /* 603 * Fetch the next transfer descriptor and transfer 604 * some flags to the next transfer descriptor 605 */ 606 td = td->obj_next; 607 xfer->td_transfer_cache = td; 608 } 609 return (1); /* not complete */ 610 611 done: 612 /* compute all actual lengths */ 613 614 atmegadci_standard_done(xfer); 615 return (0); /* complete */ 616 } 617 618 static void 619 atmegadci_interrupt_poll(struct atmegadci_softc *sc) 620 { 621 struct usb_xfer *xfer; 622 623 repeat: 624 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 625 if (!atmegadci_xfer_do_fifo(xfer)) { 626 /* queue has been modified */ 627 goto repeat; 628 } 629 } 630 } 631 632 static void 633 atmegadci_vbus_interrupt(struct atmegadci_softc *sc, uint8_t is_on) 634 { 635 DPRINTFN(5, "vbus = %u\n", is_on); 636 637 if (is_on) { 638 if (!sc->sc_flags.status_vbus) { 639 sc->sc_flags.status_vbus = 1; 640 641 /* complete root HUB interrupt endpoint */ 642 643 atmegadci_root_intr(sc); 644 } 645 } else { 646 if (sc->sc_flags.status_vbus) { 647 sc->sc_flags.status_vbus = 0; 648 sc->sc_flags.status_bus_reset = 0; 649 sc->sc_flags.status_suspend = 0; 650 sc->sc_flags.change_suspend = 0; 651 sc->sc_flags.change_connect = 1; 652 653 /* complete root HUB interrupt endpoint */ 654 655 atmegadci_root_intr(sc); 656 } 657 } 658 } 659 660 void 661 atmegadci_interrupt(struct atmegadci_softc *sc) 662 { 663 uint8_t status; 664 665 USB_BUS_LOCK(&sc->sc_bus); 666 667 /* read interrupt status */ 668 status = ATMEGA_READ_1(sc, ATMEGA_UDINT); 669 670 /* clear all set interrupts */ 671 ATMEGA_WRITE_1(sc, ATMEGA_UDINT, (~status) & 0x7D); 672 673 DPRINTFN(14, "UDINT=0x%02x\n", status); 674 675 /* check for any bus state change interrupts */ 676 if (status & ATMEGA_UDINT_EORSTI) { 677 678 DPRINTFN(5, "end of reset\n"); 679 680 /* set correct state */ 681 sc->sc_flags.status_bus_reset = 1; 682 sc->sc_flags.status_suspend = 0; 683 sc->sc_flags.change_suspend = 0; 684 sc->sc_flags.change_connect = 1; 685 686 /* disable resume interrupt */ 687 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 688 ATMEGA_UDINT_SUSPE | 689 ATMEGA_UDINT_EORSTE); 690 691 /* complete root HUB interrupt endpoint */ 692 atmegadci_root_intr(sc); 693 } 694 /* 695 * If resume and suspend is set at the same time we interpret 696 * that like RESUME. Resume is set when there is at least 3 697 * milliseconds of inactivity on the USB BUS. 698 */ 699 if (status & ATMEGA_UDINT_WAKEUPI) { 700 701 DPRINTFN(5, "resume interrupt\n"); 702 703 if (sc->sc_flags.status_suspend) { 704 /* update status bits */ 705 sc->sc_flags.status_suspend = 0; 706 sc->sc_flags.change_suspend = 1; 707 708 /* disable resume interrupt */ 709 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 710 ATMEGA_UDINT_SUSPE | 711 ATMEGA_UDINT_EORSTE); 712 713 /* complete root HUB interrupt endpoint */ 714 atmegadci_root_intr(sc); 715 } 716 } else if (status & ATMEGA_UDINT_SUSPI) { 717 718 DPRINTFN(5, "suspend interrupt\n"); 719 720 if (!sc->sc_flags.status_suspend) { 721 /* update status bits */ 722 sc->sc_flags.status_suspend = 1; 723 sc->sc_flags.change_suspend = 1; 724 725 /* disable suspend interrupt */ 726 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 727 ATMEGA_UDINT_WAKEUPE | 728 ATMEGA_UDINT_EORSTE); 729 730 /* complete root HUB interrupt endpoint */ 731 atmegadci_root_intr(sc); 732 } 733 } 734 /* check VBUS */ 735 status = ATMEGA_READ_1(sc, ATMEGA_USBINT); 736 737 /* clear all set interrupts */ 738 ATMEGA_WRITE_1(sc, ATMEGA_USBINT, (~status) & 0x03); 739 740 if (status & ATMEGA_USBINT_VBUSTI) { 741 uint8_t temp; 742 743 DPRINTFN(5, "USBINT=0x%02x\n", status); 744 745 temp = ATMEGA_READ_1(sc, ATMEGA_USBSTA); 746 atmegadci_vbus_interrupt(sc, temp & ATMEGA_USBSTA_VBUS); 747 } 748 /* check for any endpoint interrupts */ 749 status = ATMEGA_READ_1(sc, ATMEGA_UEINT); 750 /* the hardware will clear the UEINT bits automatically */ 751 if (status) { 752 753 DPRINTFN(5, "real endpoint interrupt UEINT=0x%02x\n", status); 754 755 atmegadci_interrupt_poll(sc); 756 } 757 USB_BUS_UNLOCK(&sc->sc_bus); 758 } 759 760 static void 761 atmegadci_setup_standard_chain_sub(struct atmegadci_std_temp *temp) 762 { 763 struct atmegadci_td *td; 764 765 /* get current Transfer Descriptor */ 766 td = temp->td_next; 767 temp->td = td; 768 769 /* prepare for next TD */ 770 temp->td_next = td->obj_next; 771 772 /* fill out the Transfer Descriptor */ 773 td->func = temp->func; 774 td->pc = temp->pc; 775 td->offset = temp->offset; 776 td->remainder = temp->len; 777 td->error = 0; 778 td->did_stall = temp->did_stall; 779 td->short_pkt = temp->short_pkt; 780 td->alt_next = temp->setup_alt_next; 781 } 782 783 static void 784 atmegadci_setup_standard_chain(struct usb_xfer *xfer) 785 { 786 struct atmegadci_std_temp temp; 787 struct atmegadci_softc *sc; 788 struct atmegadci_td *td; 789 uint32_t x; 790 uint8_t ep_no; 791 uint8_t need_sync; 792 793 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 794 xfer->address, UE_GET_ADDR(xfer->endpointno), 795 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 796 797 temp.max_frame_size = xfer->max_frame_size; 798 799 td = xfer->td_start[0]; 800 xfer->td_transfer_first = td; 801 xfer->td_transfer_cache = td; 802 803 /* setup temp */ 804 805 temp.pc = NULL; 806 temp.td = NULL; 807 temp.td_next = xfer->td_start[0]; 808 temp.offset = 0; 809 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 810 xfer->flags_int.isochronous_xfr; 811 temp.did_stall = !xfer->flags_int.control_stall; 812 813 sc = ATMEGA_BUS2SC(xfer->xroot->bus); 814 ep_no = (xfer->endpointno & UE_ADDR); 815 816 /* check if we should prepend a setup message */ 817 818 if (xfer->flags_int.control_xfr) { 819 if (xfer->flags_int.control_hdr) { 820 821 temp.func = &atmegadci_setup_rx; 822 temp.len = xfer->frlengths[0]; 823 temp.pc = xfer->frbuffers + 0; 824 temp.short_pkt = temp.len ? 1 : 0; 825 /* check for last frame */ 826 if (xfer->nframes == 1) { 827 /* no STATUS stage yet, SETUP is last */ 828 if (xfer->flags_int.control_act) 829 temp.setup_alt_next = 0; 830 } 831 832 atmegadci_setup_standard_chain_sub(&temp); 833 } 834 x = 1; 835 } else { 836 x = 0; 837 } 838 839 if (x != xfer->nframes) { 840 if (xfer->endpointno & UE_DIR_IN) { 841 temp.func = &atmegadci_data_tx; 842 need_sync = 1; 843 } else { 844 temp.func = &atmegadci_data_rx; 845 need_sync = 0; 846 } 847 848 /* setup "pc" pointer */ 849 temp.pc = xfer->frbuffers + x; 850 } else { 851 need_sync = 0; 852 } 853 while (x != xfer->nframes) { 854 855 /* DATA0 / DATA1 message */ 856 857 temp.len = xfer->frlengths[x]; 858 859 x++; 860 861 if (x == xfer->nframes) { 862 if (xfer->flags_int.control_xfr) { 863 if (xfer->flags_int.control_act) { 864 temp.setup_alt_next = 0; 865 } 866 } else { 867 temp.setup_alt_next = 0; 868 } 869 } 870 if (temp.len == 0) { 871 872 /* make sure that we send an USB packet */ 873 874 temp.short_pkt = 0; 875 876 } else { 877 878 /* regular data transfer */ 879 880 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 881 } 882 883 atmegadci_setup_standard_chain_sub(&temp); 884 885 if (xfer->flags_int.isochronous_xfr) { 886 temp.offset += temp.len; 887 } else { 888 /* get next Page Cache pointer */ 889 temp.pc = xfer->frbuffers + x; 890 } 891 } 892 893 if (xfer->flags_int.control_xfr) { 894 895 /* always setup a valid "pc" pointer for status and sync */ 896 temp.pc = xfer->frbuffers + 0; 897 temp.len = 0; 898 temp.short_pkt = 0; 899 temp.setup_alt_next = 0; 900 901 /* check if we need to sync */ 902 if (need_sync) { 903 /* we need a SYNC point after TX */ 904 temp.func = &atmegadci_data_tx_sync; 905 atmegadci_setup_standard_chain_sub(&temp); 906 } 907 908 /* check if we should append a status stage */ 909 if (!xfer->flags_int.control_act) { 910 911 /* 912 * Send a DATA1 message and invert the current 913 * endpoint direction. 914 */ 915 if (xfer->endpointno & UE_DIR_IN) { 916 temp.func = &atmegadci_data_rx; 917 need_sync = 0; 918 } else { 919 temp.func = &atmegadci_data_tx; 920 need_sync = 1; 921 } 922 923 atmegadci_setup_standard_chain_sub(&temp); 924 if (need_sync) { 925 /* we need a SYNC point after TX */ 926 temp.func = &atmegadci_data_tx_sync; 927 atmegadci_setup_standard_chain_sub(&temp); 928 } 929 } 930 } 931 /* must have at least one frame! */ 932 td = temp.td; 933 xfer->td_transfer_last = td; 934 } 935 936 static void 937 atmegadci_timeout(void *arg) 938 { 939 struct usb_xfer *xfer = arg; 940 941 DPRINTF("xfer=%p\n", xfer); 942 943 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 944 945 /* transfer is transferred */ 946 atmegadci_device_done(xfer, USB_ERR_TIMEOUT); 947 } 948 949 static void 950 atmegadci_start_standard_chain(struct usb_xfer *xfer) 951 { 952 DPRINTFN(9, "\n"); 953 954 /* poll one time - will turn on interrupts */ 955 if (atmegadci_xfer_do_fifo(xfer)) { 956 957 /* put transfer on interrupt queue */ 958 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 959 960 /* start timeout, if any */ 961 if (xfer->timeout != 0) { 962 usbd_transfer_timeout_ms(xfer, 963 &atmegadci_timeout, xfer->timeout); 964 } 965 } 966 } 967 968 static void 969 atmegadci_root_intr(struct atmegadci_softc *sc) 970 { 971 DPRINTFN(9, "\n"); 972 973 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 974 975 /* set port bit */ 976 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 977 978 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 979 sizeof(sc->sc_hub_idata)); 980 } 981 982 static usb_error_t 983 atmegadci_standard_done_sub(struct usb_xfer *xfer) 984 { 985 struct atmegadci_td *td; 986 uint32_t len; 987 uint8_t error; 988 989 DPRINTFN(9, "\n"); 990 991 td = xfer->td_transfer_cache; 992 993 do { 994 len = td->remainder; 995 996 if (xfer->aframes != xfer->nframes) { 997 /* 998 * Verify the length and subtract 999 * the remainder from "frlengths[]": 1000 */ 1001 if (len > xfer->frlengths[xfer->aframes]) { 1002 td->error = 1; 1003 } else { 1004 xfer->frlengths[xfer->aframes] -= len; 1005 } 1006 } 1007 /* Check for transfer error */ 1008 if (td->error) { 1009 /* the transfer is finished */ 1010 error = 1; 1011 td = NULL; 1012 break; 1013 } 1014 /* Check for short transfer */ 1015 if (len > 0) { 1016 if (xfer->flags_int.short_frames_ok || 1017 xfer->flags_int.isochronous_xfr) { 1018 /* follow alt next */ 1019 if (td->alt_next) { 1020 td = td->obj_next; 1021 } else { 1022 td = NULL; 1023 } 1024 } else { 1025 /* the transfer is finished */ 1026 td = NULL; 1027 } 1028 error = 0; 1029 break; 1030 } 1031 td = td->obj_next; 1032 1033 /* this USB frame is complete */ 1034 error = 0; 1035 break; 1036 1037 } while (0); 1038 1039 /* update transfer cache */ 1040 1041 xfer->td_transfer_cache = td; 1042 1043 return (error ? 1044 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1045 } 1046 1047 static void 1048 atmegadci_standard_done(struct usb_xfer *xfer) 1049 { 1050 usb_error_t err = 0; 1051 1052 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1053 xfer, xfer->endpoint); 1054 1055 /* reset scanner */ 1056 1057 xfer->td_transfer_cache = xfer->td_transfer_first; 1058 1059 if (xfer->flags_int.control_xfr) { 1060 1061 if (xfer->flags_int.control_hdr) { 1062 1063 err = atmegadci_standard_done_sub(xfer); 1064 } 1065 xfer->aframes = 1; 1066 1067 if (xfer->td_transfer_cache == NULL) { 1068 goto done; 1069 } 1070 } 1071 while (xfer->aframes != xfer->nframes) { 1072 1073 err = atmegadci_standard_done_sub(xfer); 1074 xfer->aframes++; 1075 1076 if (xfer->td_transfer_cache == NULL) { 1077 goto done; 1078 } 1079 } 1080 1081 if (xfer->flags_int.control_xfr && 1082 !xfer->flags_int.control_act) { 1083 1084 err = atmegadci_standard_done_sub(xfer); 1085 } 1086 done: 1087 atmegadci_device_done(xfer, err); 1088 } 1089 1090 /*------------------------------------------------------------------------* 1091 * atmegadci_device_done 1092 * 1093 * NOTE: this function can be called more than one time on the 1094 * same USB transfer! 1095 *------------------------------------------------------------------------*/ 1096 static void 1097 atmegadci_device_done(struct usb_xfer *xfer, usb_error_t error) 1098 { 1099 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1100 uint8_t ep_no; 1101 1102 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1103 1104 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 1105 xfer, xfer->endpoint, error); 1106 1107 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 1108 ep_no = (xfer->endpointno & UE_ADDR); 1109 1110 /* select endpoint number */ 1111 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1112 1113 /* disable endpoint interrupt */ 1114 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0); 1115 1116 DPRINTFN(15, "disabled interrupts!\n"); 1117 } 1118 /* dequeue transfer and start next transfer */ 1119 usbd_transfer_done(xfer, error); 1120 } 1121 1122 static void 1123 atmegadci_xfer_stall(struct usb_xfer *xfer) 1124 { 1125 atmegadci_device_done(xfer, USB_ERR_STALLED); 1126 } 1127 1128 static void 1129 atmegadci_set_stall(struct usb_device *udev, 1130 struct usb_endpoint *ep, uint8_t *did_stall) 1131 { 1132 struct atmegadci_softc *sc; 1133 uint8_t ep_no; 1134 1135 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1136 1137 DPRINTFN(5, "endpoint=%p\n", ep); 1138 1139 sc = ATMEGA_BUS2SC(udev->bus); 1140 /* get endpoint number */ 1141 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR); 1142 /* select endpoint number */ 1143 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1144 /* set stall */ 1145 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1146 ATMEGA_UECONX_EPEN | 1147 ATMEGA_UECONX_STALLRQ); 1148 } 1149 1150 static void 1151 atmegadci_clear_stall_sub(struct atmegadci_softc *sc, uint8_t ep_no, 1152 uint8_t ep_type, uint8_t ep_dir) 1153 { 1154 uint8_t temp; 1155 1156 if (ep_type == UE_CONTROL) { 1157 /* clearing stall is not needed */ 1158 return; 1159 } 1160 /* select endpoint number */ 1161 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1162 1163 /* set endpoint reset */ 1164 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(ep_no)); 1165 1166 /* clear endpoint reset */ 1167 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1168 1169 /* set stall */ 1170 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1171 ATMEGA_UECONX_EPEN | 1172 ATMEGA_UECONX_STALLRQ); 1173 1174 /* reset data toggle */ 1175 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1176 ATMEGA_UECONX_EPEN | 1177 ATMEGA_UECONX_RSTDT); 1178 1179 /* clear stall */ 1180 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1181 ATMEGA_UECONX_EPEN | 1182 ATMEGA_UECONX_STALLRQC); 1183 1184 do { 1185 if (ep_type == UE_BULK) { 1186 temp = ATMEGA_UECFG0X_EPTYPE2; 1187 } else if (ep_type == UE_INTERRUPT) { 1188 temp = ATMEGA_UECFG0X_EPTYPE3; 1189 } else { 1190 temp = ATMEGA_UECFG0X_EPTYPE1; 1191 } 1192 if (ep_dir & UE_DIR_IN) { 1193 temp |= ATMEGA_UECFG0X_EPDIR; 1194 } 1195 /* two banks, 64-bytes wMaxPacket */ 1196 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, temp); 1197 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X, 1198 ATMEGA_UECFG1X_ALLOC | 1199 ATMEGA_UECFG1X_EPBK0 | /* one bank */ 1200 ATMEGA_UECFG1X_EPSIZE(3)); 1201 1202 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 1203 if (!(temp & ATMEGA_UESTA0X_CFGOK)) { 1204 device_printf(sc->sc_bus.bdev, 1205 "Chip rejected configuration\n"); 1206 } 1207 } while (0); 1208 } 1209 1210 static void 1211 atmegadci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 1212 { 1213 struct atmegadci_softc *sc; 1214 struct usb_endpoint_descriptor *ed; 1215 1216 DPRINTFN(5, "endpoint=%p\n", ep); 1217 1218 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1219 1220 /* check mode */ 1221 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 1222 /* not supported */ 1223 return; 1224 } 1225 /* get softc */ 1226 sc = ATMEGA_BUS2SC(udev->bus); 1227 1228 /* get endpoint descriptor */ 1229 ed = ep->edesc; 1230 1231 /* reset endpoint */ 1232 atmegadci_clear_stall_sub(sc, 1233 (ed->bEndpointAddress & UE_ADDR), 1234 (ed->bmAttributes & UE_XFERTYPE), 1235 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1236 } 1237 1238 usb_error_t 1239 atmegadci_init(struct atmegadci_softc *sc) 1240 { 1241 uint8_t n; 1242 1243 DPRINTF("start\n"); 1244 1245 /* set up the bus structure */ 1246 sc->sc_bus.usbrev = USB_REV_1_1; 1247 sc->sc_bus.methods = &atmegadci_bus_methods; 1248 1249 USB_BUS_LOCK(&sc->sc_bus); 1250 1251 /* make sure USB is enabled */ 1252 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 1253 ATMEGA_USBCON_USBE | 1254 ATMEGA_USBCON_FRZCLK); 1255 1256 /* enable USB PAD regulator */ 1257 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 1258 ATMEGA_UHWCON_UVREGE | 1259 ATMEGA_UHWCON_UIMOD); 1260 1261 /* the following register sets up the USB PLL, assuming 16MHz X-tal */ 1262 ATMEGA_WRITE_1(sc, 0x49 /* PLLCSR */, 0x14 | 0x02); 1263 1264 /* wait for PLL to lock */ 1265 for (n = 0; n != 20; n++) { 1266 if (ATMEGA_READ_1(sc, 0x49) & 0x01) 1267 break; 1268 /* wait a little bit for PLL to start */ 1269 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 1270 } 1271 1272 /* make sure USB is enabled */ 1273 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 1274 ATMEGA_USBCON_USBE | 1275 ATMEGA_USBCON_OTGPADE | 1276 ATMEGA_USBCON_VBUSTE); 1277 1278 /* turn on clocks */ 1279 (sc->sc_clocks_on) (&sc->sc_bus); 1280 1281 /* make sure device is re-enumerated */ 1282 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH); 1283 1284 /* wait a little for things to stabilise */ 1285 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20); 1286 1287 /* enable interrupts */ 1288 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 1289 ATMEGA_UDINT_SUSPE | 1290 ATMEGA_UDINT_EORSTE); 1291 1292 /* reset all endpoints */ 1293 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 1294 (1 << ATMEGA_EP_MAX) - 1); 1295 1296 /* disable reset */ 1297 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1298 1299 /* disable all endpoints */ 1300 for (n = 0; n != ATMEGA_EP_MAX; n++) { 1301 1302 /* select endpoint */ 1303 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, n); 1304 1305 /* disable endpoint interrupt */ 1306 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0); 1307 1308 /* disable endpoint */ 1309 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 0); 1310 } 1311 1312 /* turn off clocks */ 1313 1314 atmegadci_clocks_off(sc); 1315 1316 /* read initial VBUS state */ 1317 1318 n = ATMEGA_READ_1(sc, ATMEGA_USBSTA); 1319 atmegadci_vbus_interrupt(sc, n & ATMEGA_USBSTA_VBUS); 1320 1321 USB_BUS_UNLOCK(&sc->sc_bus); 1322 1323 /* catch any lost interrupts */ 1324 1325 atmegadci_do_poll(&sc->sc_bus); 1326 1327 return (0); /* success */ 1328 } 1329 1330 void 1331 atmegadci_uninit(struct atmegadci_softc *sc) 1332 { 1333 USB_BUS_LOCK(&sc->sc_bus); 1334 1335 /* turn on clocks */ 1336 (sc->sc_clocks_on) (&sc->sc_bus); 1337 1338 /* disable interrupts */ 1339 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 0); 1340 1341 /* reset all endpoints */ 1342 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 1343 (1 << ATMEGA_EP_MAX) - 1); 1344 1345 /* disable reset */ 1346 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1347 1348 sc->sc_flags.port_powered = 0; 1349 sc->sc_flags.status_vbus = 0; 1350 sc->sc_flags.status_bus_reset = 0; 1351 sc->sc_flags.status_suspend = 0; 1352 sc->sc_flags.change_suspend = 0; 1353 sc->sc_flags.change_connect = 1; 1354 1355 atmegadci_pull_down(sc); 1356 atmegadci_clocks_off(sc); 1357 1358 /* disable USB PAD regulator */ 1359 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 0); 1360 1361 USB_BUS_UNLOCK(&sc->sc_bus); 1362 } 1363 1364 static void 1365 atmegadci_suspend(struct atmegadci_softc *sc) 1366 { 1367 /* TODO */ 1368 } 1369 1370 static void 1371 atmegadci_resume(struct atmegadci_softc *sc) 1372 { 1373 /* TODO */ 1374 } 1375 1376 static void 1377 atmegadci_do_poll(struct usb_bus *bus) 1378 { 1379 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus); 1380 1381 USB_BUS_LOCK(&sc->sc_bus); 1382 atmegadci_interrupt_poll(sc); 1383 USB_BUS_UNLOCK(&sc->sc_bus); 1384 } 1385 1386 /*------------------------------------------------------------------------* 1387 * atmegadci bulk support 1388 * atmegadci control support 1389 * atmegadci interrupt support 1390 *------------------------------------------------------------------------*/ 1391 static void 1392 atmegadci_device_non_isoc_open(struct usb_xfer *xfer) 1393 { 1394 return; 1395 } 1396 1397 static void 1398 atmegadci_device_non_isoc_close(struct usb_xfer *xfer) 1399 { 1400 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1401 } 1402 1403 static void 1404 atmegadci_device_non_isoc_enter(struct usb_xfer *xfer) 1405 { 1406 return; 1407 } 1408 1409 static void 1410 atmegadci_device_non_isoc_start(struct usb_xfer *xfer) 1411 { 1412 /* setup TDs */ 1413 atmegadci_setup_standard_chain(xfer); 1414 atmegadci_start_standard_chain(xfer); 1415 } 1416 1417 static const struct usb_pipe_methods atmegadci_device_non_isoc_methods = 1418 { 1419 .open = atmegadci_device_non_isoc_open, 1420 .close = atmegadci_device_non_isoc_close, 1421 .enter = atmegadci_device_non_isoc_enter, 1422 .start = atmegadci_device_non_isoc_start, 1423 }; 1424 1425 /*------------------------------------------------------------------------* 1426 * atmegadci full speed isochronous support 1427 *------------------------------------------------------------------------*/ 1428 static void 1429 atmegadci_device_isoc_fs_open(struct usb_xfer *xfer) 1430 { 1431 return; 1432 } 1433 1434 static void 1435 atmegadci_device_isoc_fs_close(struct usb_xfer *xfer) 1436 { 1437 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1438 } 1439 1440 static void 1441 atmegadci_device_isoc_fs_enter(struct usb_xfer *xfer) 1442 { 1443 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1444 uint32_t temp; 1445 uint32_t nframes; 1446 1447 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1448 xfer, xfer->endpoint->isoc_next, xfer->nframes); 1449 1450 /* get the current frame index */ 1451 1452 nframes = 1453 (ATMEGA_READ_1(sc, ATMEGA_UDFNUMH) << 8) | 1454 (ATMEGA_READ_1(sc, ATMEGA_UDFNUML)); 1455 1456 nframes &= ATMEGA_FRAME_MASK; 1457 1458 /* 1459 * check if the frame index is within the window where the frames 1460 * will be inserted 1461 */ 1462 temp = (nframes - xfer->endpoint->isoc_next) & ATMEGA_FRAME_MASK; 1463 1464 if ((xfer->endpoint->is_synced == 0) || 1465 (temp < xfer->nframes)) { 1466 /* 1467 * If there is data underflow or the pipe queue is 1468 * empty we schedule the transfer a few frames ahead 1469 * of the current frame position. Else two isochronous 1470 * transfers might overlap. 1471 */ 1472 xfer->endpoint->isoc_next = (nframes + 3) & ATMEGA_FRAME_MASK; 1473 xfer->endpoint->is_synced = 1; 1474 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1475 } 1476 /* 1477 * compute how many milliseconds the insertion is ahead of the 1478 * current frame position: 1479 */ 1480 temp = (xfer->endpoint->isoc_next - nframes) & ATMEGA_FRAME_MASK; 1481 1482 /* 1483 * pre-compute when the isochronous transfer will be finished: 1484 */ 1485 xfer->isoc_time_complete = 1486 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1487 xfer->nframes; 1488 1489 /* compute frame number for next insertion */ 1490 xfer->endpoint->isoc_next += xfer->nframes; 1491 1492 /* setup TDs */ 1493 atmegadci_setup_standard_chain(xfer); 1494 } 1495 1496 static void 1497 atmegadci_device_isoc_fs_start(struct usb_xfer *xfer) 1498 { 1499 /* start TD chain */ 1500 atmegadci_start_standard_chain(xfer); 1501 } 1502 1503 static const struct usb_pipe_methods atmegadci_device_isoc_fs_methods = 1504 { 1505 .open = atmegadci_device_isoc_fs_open, 1506 .close = atmegadci_device_isoc_fs_close, 1507 .enter = atmegadci_device_isoc_fs_enter, 1508 .start = atmegadci_device_isoc_fs_start, 1509 }; 1510 1511 /*------------------------------------------------------------------------* 1512 * atmegadci root control support 1513 *------------------------------------------------------------------------* 1514 * Simulate a hardware HUB by handling all the necessary requests. 1515 *------------------------------------------------------------------------*/ 1516 1517 static const struct usb_device_descriptor atmegadci_devd = { 1518 .bLength = sizeof(struct usb_device_descriptor), 1519 .bDescriptorType = UDESC_DEVICE, 1520 .bcdUSB = {0x00, 0x02}, 1521 .bDeviceClass = UDCLASS_HUB, 1522 .bDeviceSubClass = UDSUBCLASS_HUB, 1523 .bDeviceProtocol = UDPROTO_FSHUB, 1524 .bMaxPacketSize = 64, 1525 .bcdDevice = {0x00, 0x01}, 1526 .iManufacturer = 1, 1527 .iProduct = 2, 1528 .bNumConfigurations = 1, 1529 }; 1530 1531 static const struct atmegadci_config_desc atmegadci_confd = { 1532 .confd = { 1533 .bLength = sizeof(struct usb_config_descriptor), 1534 .bDescriptorType = UDESC_CONFIG, 1535 .wTotalLength[0] = sizeof(atmegadci_confd), 1536 .bNumInterface = 1, 1537 .bConfigurationValue = 1, 1538 .iConfiguration = 0, 1539 .bmAttributes = UC_SELF_POWERED, 1540 .bMaxPower = 0, 1541 }, 1542 .ifcd = { 1543 .bLength = sizeof(struct usb_interface_descriptor), 1544 .bDescriptorType = UDESC_INTERFACE, 1545 .bNumEndpoints = 1, 1546 .bInterfaceClass = UICLASS_HUB, 1547 .bInterfaceSubClass = UISUBCLASS_HUB, 1548 .bInterfaceProtocol = 0, 1549 }, 1550 .endpd = { 1551 .bLength = sizeof(struct usb_endpoint_descriptor), 1552 .bDescriptorType = UDESC_ENDPOINT, 1553 .bEndpointAddress = (UE_DIR_IN | ATMEGA_INTR_ENDPT), 1554 .bmAttributes = UE_INTERRUPT, 1555 .wMaxPacketSize[0] = 8, 1556 .bInterval = 255, 1557 }, 1558 }; 1559 1560 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 1561 1562 static const struct usb_hub_descriptor_min atmegadci_hubd = { 1563 .bDescLength = sizeof(atmegadci_hubd), 1564 .bDescriptorType = UDESC_HUB, 1565 .bNbrPorts = 1, 1566 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 1567 .bPwrOn2PwrGood = 50, 1568 .bHubContrCurrent = 0, 1569 .DeviceRemovable = {0}, /* port is removable */ 1570 }; 1571 1572 #define STRING_VENDOR \ 1573 "A\0T\0M\0E\0G\0A" 1574 1575 #define STRING_PRODUCT \ 1576 "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B" 1577 1578 USB_MAKE_STRING_DESC(STRING_VENDOR, atmegadci_vendor); 1579 USB_MAKE_STRING_DESC(STRING_PRODUCT, atmegadci_product); 1580 1581 static usb_error_t 1582 atmegadci_roothub_exec(struct usb_device *udev, 1583 struct usb_device_request *req, const void **pptr, uint16_t *plength) 1584 { 1585 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus); 1586 const void *ptr; 1587 uint16_t len; 1588 uint16_t value; 1589 uint16_t index; 1590 uint8_t temp; 1591 usb_error_t err; 1592 1593 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1594 1595 /* buffer reset */ 1596 ptr = (const void *)&sc->sc_hub_temp; 1597 len = 0; 1598 err = 0; 1599 1600 value = UGETW(req->wValue); 1601 index = UGETW(req->wIndex); 1602 1603 /* demultiplex the control request */ 1604 1605 switch (req->bmRequestType) { 1606 case UT_READ_DEVICE: 1607 switch (req->bRequest) { 1608 case UR_GET_DESCRIPTOR: 1609 goto tr_handle_get_descriptor; 1610 case UR_GET_CONFIG: 1611 goto tr_handle_get_config; 1612 case UR_GET_STATUS: 1613 goto tr_handle_get_status; 1614 default: 1615 goto tr_stalled; 1616 } 1617 break; 1618 1619 case UT_WRITE_DEVICE: 1620 switch (req->bRequest) { 1621 case UR_SET_ADDRESS: 1622 goto tr_handle_set_address; 1623 case UR_SET_CONFIG: 1624 goto tr_handle_set_config; 1625 case UR_CLEAR_FEATURE: 1626 goto tr_valid; /* nop */ 1627 case UR_SET_DESCRIPTOR: 1628 goto tr_valid; /* nop */ 1629 case UR_SET_FEATURE: 1630 default: 1631 goto tr_stalled; 1632 } 1633 break; 1634 1635 case UT_WRITE_ENDPOINT: 1636 switch (req->bRequest) { 1637 case UR_CLEAR_FEATURE: 1638 switch (UGETW(req->wValue)) { 1639 case UF_ENDPOINT_HALT: 1640 goto tr_handle_clear_halt; 1641 case UF_DEVICE_REMOTE_WAKEUP: 1642 goto tr_handle_clear_wakeup; 1643 default: 1644 goto tr_stalled; 1645 } 1646 break; 1647 case UR_SET_FEATURE: 1648 switch (UGETW(req->wValue)) { 1649 case UF_ENDPOINT_HALT: 1650 goto tr_handle_set_halt; 1651 case UF_DEVICE_REMOTE_WAKEUP: 1652 goto tr_handle_set_wakeup; 1653 default: 1654 goto tr_stalled; 1655 } 1656 break; 1657 case UR_SYNCH_FRAME: 1658 goto tr_valid; /* nop */ 1659 default: 1660 goto tr_stalled; 1661 } 1662 break; 1663 1664 case UT_READ_ENDPOINT: 1665 switch (req->bRequest) { 1666 case UR_GET_STATUS: 1667 goto tr_handle_get_ep_status; 1668 default: 1669 goto tr_stalled; 1670 } 1671 break; 1672 1673 case UT_WRITE_INTERFACE: 1674 switch (req->bRequest) { 1675 case UR_SET_INTERFACE: 1676 goto tr_handle_set_interface; 1677 case UR_CLEAR_FEATURE: 1678 goto tr_valid; /* nop */ 1679 case UR_SET_FEATURE: 1680 default: 1681 goto tr_stalled; 1682 } 1683 break; 1684 1685 case UT_READ_INTERFACE: 1686 switch (req->bRequest) { 1687 case UR_GET_INTERFACE: 1688 goto tr_handle_get_interface; 1689 case UR_GET_STATUS: 1690 goto tr_handle_get_iface_status; 1691 default: 1692 goto tr_stalled; 1693 } 1694 break; 1695 1696 case UT_WRITE_CLASS_INTERFACE: 1697 case UT_WRITE_VENDOR_INTERFACE: 1698 /* XXX forward */ 1699 break; 1700 1701 case UT_READ_CLASS_INTERFACE: 1702 case UT_READ_VENDOR_INTERFACE: 1703 /* XXX forward */ 1704 break; 1705 1706 case UT_WRITE_CLASS_DEVICE: 1707 switch (req->bRequest) { 1708 case UR_CLEAR_FEATURE: 1709 goto tr_valid; 1710 case UR_SET_DESCRIPTOR: 1711 case UR_SET_FEATURE: 1712 break; 1713 default: 1714 goto tr_stalled; 1715 } 1716 break; 1717 1718 case UT_WRITE_CLASS_OTHER: 1719 switch (req->bRequest) { 1720 case UR_CLEAR_FEATURE: 1721 goto tr_handle_clear_port_feature; 1722 case UR_SET_FEATURE: 1723 goto tr_handle_set_port_feature; 1724 case UR_CLEAR_TT_BUFFER: 1725 case UR_RESET_TT: 1726 case UR_STOP_TT: 1727 goto tr_valid; 1728 1729 default: 1730 goto tr_stalled; 1731 } 1732 break; 1733 1734 case UT_READ_CLASS_OTHER: 1735 switch (req->bRequest) { 1736 case UR_GET_TT_STATE: 1737 goto tr_handle_get_tt_state; 1738 case UR_GET_STATUS: 1739 goto tr_handle_get_port_status; 1740 default: 1741 goto tr_stalled; 1742 } 1743 break; 1744 1745 case UT_READ_CLASS_DEVICE: 1746 switch (req->bRequest) { 1747 case UR_GET_DESCRIPTOR: 1748 goto tr_handle_get_class_descriptor; 1749 case UR_GET_STATUS: 1750 goto tr_handle_get_class_status; 1751 1752 default: 1753 goto tr_stalled; 1754 } 1755 break; 1756 default: 1757 goto tr_stalled; 1758 } 1759 goto tr_valid; 1760 1761 tr_handle_get_descriptor: 1762 switch (value >> 8) { 1763 case UDESC_DEVICE: 1764 if (value & 0xff) { 1765 goto tr_stalled; 1766 } 1767 len = sizeof(atmegadci_devd); 1768 ptr = (const void *)&atmegadci_devd; 1769 goto tr_valid; 1770 case UDESC_CONFIG: 1771 if (value & 0xff) { 1772 goto tr_stalled; 1773 } 1774 len = sizeof(atmegadci_confd); 1775 ptr = (const void *)&atmegadci_confd; 1776 goto tr_valid; 1777 case UDESC_STRING: 1778 switch (value & 0xff) { 1779 case 0: /* Language table */ 1780 len = sizeof(usb_string_lang_en); 1781 ptr = (const void *)&usb_string_lang_en; 1782 goto tr_valid; 1783 1784 case 1: /* Vendor */ 1785 len = sizeof(atmegadci_vendor); 1786 ptr = (const void *)&atmegadci_vendor; 1787 goto tr_valid; 1788 1789 case 2: /* Product */ 1790 len = sizeof(atmegadci_product); 1791 ptr = (const void *)&atmegadci_product; 1792 goto tr_valid; 1793 default: 1794 break; 1795 } 1796 break; 1797 default: 1798 goto tr_stalled; 1799 } 1800 goto tr_stalled; 1801 1802 tr_handle_get_config: 1803 len = 1; 1804 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 1805 goto tr_valid; 1806 1807 tr_handle_get_status: 1808 len = 2; 1809 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 1810 goto tr_valid; 1811 1812 tr_handle_set_address: 1813 if (value & 0xFF00) { 1814 goto tr_stalled; 1815 } 1816 sc->sc_rt_addr = value; 1817 goto tr_valid; 1818 1819 tr_handle_set_config: 1820 if (value >= 2) { 1821 goto tr_stalled; 1822 } 1823 sc->sc_conf = value; 1824 goto tr_valid; 1825 1826 tr_handle_get_interface: 1827 len = 1; 1828 sc->sc_hub_temp.wValue[0] = 0; 1829 goto tr_valid; 1830 1831 tr_handle_get_tt_state: 1832 tr_handle_get_class_status: 1833 tr_handle_get_iface_status: 1834 tr_handle_get_ep_status: 1835 len = 2; 1836 USETW(sc->sc_hub_temp.wValue, 0); 1837 goto tr_valid; 1838 1839 tr_handle_set_halt: 1840 tr_handle_set_interface: 1841 tr_handle_set_wakeup: 1842 tr_handle_clear_wakeup: 1843 tr_handle_clear_halt: 1844 goto tr_valid; 1845 1846 tr_handle_clear_port_feature: 1847 if (index != 1) { 1848 goto tr_stalled; 1849 } 1850 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 1851 1852 switch (value) { 1853 case UHF_PORT_SUSPEND: 1854 atmegadci_wakeup_peer(sc); 1855 break; 1856 1857 case UHF_PORT_ENABLE: 1858 sc->sc_flags.port_enabled = 0; 1859 break; 1860 1861 case UHF_PORT_TEST: 1862 case UHF_PORT_INDICATOR: 1863 case UHF_C_PORT_ENABLE: 1864 case UHF_C_PORT_OVER_CURRENT: 1865 case UHF_C_PORT_RESET: 1866 /* nops */ 1867 break; 1868 case UHF_PORT_POWER: 1869 sc->sc_flags.port_powered = 0; 1870 atmegadci_pull_down(sc); 1871 atmegadci_clocks_off(sc); 1872 break; 1873 case UHF_C_PORT_CONNECTION: 1874 /* clear connect change flag */ 1875 sc->sc_flags.change_connect = 0; 1876 1877 if (!sc->sc_flags.status_bus_reset) { 1878 /* we are not connected */ 1879 break; 1880 } 1881 1882 /* configure the control endpoint */ 1883 1884 /* select endpoint number */ 1885 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, 0); 1886 1887 /* set endpoint reset */ 1888 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(0)); 1889 1890 /* clear endpoint reset */ 1891 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1892 1893 /* enable and stall endpoint */ 1894 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1895 ATMEGA_UECONX_EPEN | 1896 ATMEGA_UECONX_STALLRQ); 1897 1898 /* one bank, 64-bytes wMaxPacket */ 1899 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, 1900 ATMEGA_UECFG0X_EPTYPE0); 1901 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X, 1902 ATMEGA_UECFG1X_ALLOC | 1903 ATMEGA_UECFG1X_EPBK0 | 1904 ATMEGA_UECFG1X_EPSIZE(3)); 1905 1906 /* check valid config */ 1907 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 1908 if (!(temp & ATMEGA_UESTA0X_CFGOK)) { 1909 device_printf(sc->sc_bus.bdev, 1910 "Chip rejected EP0 configuration\n"); 1911 } 1912 break; 1913 case UHF_C_PORT_SUSPEND: 1914 sc->sc_flags.change_suspend = 0; 1915 break; 1916 default: 1917 err = USB_ERR_IOERROR; 1918 goto done; 1919 } 1920 goto tr_valid; 1921 1922 tr_handle_set_port_feature: 1923 if (index != 1) { 1924 goto tr_stalled; 1925 } 1926 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 1927 1928 switch (value) { 1929 case UHF_PORT_ENABLE: 1930 sc->sc_flags.port_enabled = 1; 1931 break; 1932 case UHF_PORT_SUSPEND: 1933 case UHF_PORT_RESET: 1934 case UHF_PORT_TEST: 1935 case UHF_PORT_INDICATOR: 1936 /* nops */ 1937 break; 1938 case UHF_PORT_POWER: 1939 sc->sc_flags.port_powered = 1; 1940 break; 1941 default: 1942 err = USB_ERR_IOERROR; 1943 goto done; 1944 } 1945 goto tr_valid; 1946 1947 tr_handle_get_port_status: 1948 1949 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 1950 1951 if (index != 1) { 1952 goto tr_stalled; 1953 } 1954 if (sc->sc_flags.status_vbus) { 1955 atmegadci_clocks_on(sc); 1956 atmegadci_pull_up(sc); 1957 } else { 1958 atmegadci_pull_down(sc); 1959 atmegadci_clocks_off(sc); 1960 } 1961 1962 /* Select FULL-speed and Device Side Mode */ 1963 1964 value = UPS_PORT_MODE_DEVICE; 1965 1966 if (sc->sc_flags.port_powered) { 1967 value |= UPS_PORT_POWER; 1968 } 1969 if (sc->sc_flags.port_enabled) { 1970 value |= UPS_PORT_ENABLED; 1971 } 1972 if (sc->sc_flags.status_vbus && 1973 sc->sc_flags.status_bus_reset) { 1974 value |= UPS_CURRENT_CONNECT_STATUS; 1975 } 1976 if (sc->sc_flags.status_suspend) { 1977 value |= UPS_SUSPEND; 1978 } 1979 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 1980 1981 value = 0; 1982 1983 if (sc->sc_flags.change_connect) { 1984 value |= UPS_C_CONNECT_STATUS; 1985 } 1986 if (sc->sc_flags.change_suspend) { 1987 value |= UPS_C_SUSPEND; 1988 } 1989 USETW(sc->sc_hub_temp.ps.wPortChange, value); 1990 len = sizeof(sc->sc_hub_temp.ps); 1991 goto tr_valid; 1992 1993 tr_handle_get_class_descriptor: 1994 if (value & 0xFF) { 1995 goto tr_stalled; 1996 } 1997 ptr = (const void *)&atmegadci_hubd; 1998 len = sizeof(atmegadci_hubd); 1999 goto tr_valid; 2000 2001 tr_stalled: 2002 err = USB_ERR_STALLED; 2003 tr_valid: 2004 done: 2005 *plength = len; 2006 *pptr = ptr; 2007 return (err); 2008 } 2009 2010 static void 2011 atmegadci_xfer_setup(struct usb_setup_params *parm) 2012 { 2013 const struct usb_hw_ep_profile *pf; 2014 struct atmegadci_softc *sc; 2015 struct usb_xfer *xfer; 2016 void *last_obj; 2017 uint32_t ntd; 2018 uint32_t n; 2019 uint8_t ep_no; 2020 2021 sc = ATMEGA_BUS2SC(parm->udev->bus); 2022 xfer = parm->curr_xfer; 2023 2024 /* 2025 * NOTE: This driver does not use any of the parameters that 2026 * are computed from the following values. Just set some 2027 * reasonable dummies: 2028 */ 2029 parm->hc_max_packet_size = 0x500; 2030 parm->hc_max_packet_count = 1; 2031 parm->hc_max_frame_size = 0x500; 2032 2033 usbd_transfer_setup_sub(parm); 2034 2035 /* 2036 * compute maximum number of TDs 2037 */ 2038 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) { 2039 2040 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 2041 + 1 /* SYNC 2 */ ; 2042 } else { 2043 2044 ntd = xfer->nframes + 1 /* SYNC */ ; 2045 } 2046 2047 /* 2048 * check if "usbd_transfer_setup_sub" set an error 2049 */ 2050 if (parm->err) 2051 return; 2052 2053 /* 2054 * allocate transfer descriptors 2055 */ 2056 last_obj = NULL; 2057 2058 /* 2059 * get profile stuff 2060 */ 2061 ep_no = xfer->endpointno & UE_ADDR; 2062 atmegadci_get_hw_ep_profile(parm->udev, &pf, ep_no); 2063 2064 if (pf == NULL) { 2065 /* should not happen */ 2066 parm->err = USB_ERR_INVAL; 2067 return; 2068 } 2069 2070 /* align data */ 2071 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2072 2073 for (n = 0; n != ntd; n++) { 2074 2075 struct atmegadci_td *td; 2076 2077 if (parm->buf) { 2078 2079 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2080 2081 /* init TD */ 2082 td->max_packet_size = xfer->max_packet_size; 2083 td->ep_no = ep_no; 2084 if (pf->support_multi_buffer) { 2085 td->support_multi_buffer = 1; 2086 } 2087 td->obj_next = last_obj; 2088 2089 last_obj = td; 2090 } 2091 parm->size[0] += sizeof(*td); 2092 } 2093 2094 xfer->td_start[0] = last_obj; 2095 } 2096 2097 static void 2098 atmegadci_xfer_unsetup(struct usb_xfer *xfer) 2099 { 2100 return; 2101 } 2102 2103 static void 2104 atmegadci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2105 struct usb_endpoint *ep) 2106 { 2107 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus); 2108 2109 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 2110 ep, udev->address, 2111 edesc->bEndpointAddress, udev->flags.usb_mode, 2112 sc->sc_rt_addr, udev->device_index); 2113 2114 if (udev->device_index != sc->sc_rt_addr) { 2115 2116 if (udev->speed != USB_SPEED_FULL) { 2117 /* not supported */ 2118 return; 2119 } 2120 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 2121 ep->methods = &atmegadci_device_isoc_fs_methods; 2122 else 2123 ep->methods = &atmegadci_device_non_isoc_methods; 2124 } 2125 } 2126 2127 static void 2128 atmegadci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 2129 { 2130 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus); 2131 2132 switch (state) { 2133 case USB_HW_POWER_SUSPEND: 2134 atmegadci_suspend(sc); 2135 break; 2136 case USB_HW_POWER_SHUTDOWN: 2137 atmegadci_uninit(sc); 2138 break; 2139 case USB_HW_POWER_RESUME: 2140 atmegadci_resume(sc); 2141 break; 2142 default: 2143 break; 2144 } 2145 } 2146 2147 static const struct usb_bus_methods atmegadci_bus_methods = 2148 { 2149 .endpoint_init = &atmegadci_ep_init, 2150 .xfer_setup = &atmegadci_xfer_setup, 2151 .xfer_unsetup = &atmegadci_xfer_unsetup, 2152 .get_hw_ep_profile = &atmegadci_get_hw_ep_profile, 2153 .xfer_stall = &atmegadci_xfer_stall, 2154 .set_stall = &atmegadci_set_stall, 2155 .clear_stall = &atmegadci_clear_stall, 2156 .roothub_exec = &atmegadci_roothub_exec, 2157 .xfer_poll = &atmegadci_do_poll, 2158 .set_hw_power_sleep = &atmegadci_set_hw_power_sleep, 2159 }; 2160