1 /*- 2 * Copyright (c) 2012 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Oleksandr Rybalko under sponsorship 6 * from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_ddb.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/conf.h> 39 #include <sys/kdb.h> 40 #include <machine/bus.h> 41 #include <machine/fdt.h> 42 43 #include <dev/uart/uart.h> 44 #include <dev/uart/uart_cpu.h> 45 #include <dev/uart/uart_bus.h> 46 #include <dev/uart/uart_dev_imx.h> 47 #include "uart_if.h" 48 49 #include <arm/freescale/imx/imx_ccmvar.h> 50 51 /* 52 * The hardare FIFOs are 32 bytes. We want an interrupt when there are 24 bytes 53 * available to read or space for 24 more bytes to write. While 8 bytes of 54 * slack before over/underrun might seem excessive, the hardware can run at 55 * 5mbps, which means 2uS per char, so at full speed 8 bytes provides only 16uS 56 * to get into the interrupt handler and service the fifo. 57 */ 58 #define IMX_FIFOSZ 32 59 #define IMX_RXFIFO_LEVEL 24 60 #define IMX_TXFIFO_LEVEL 24 61 62 /* 63 * Low-level UART interface. 64 */ 65 static int imx_uart_probe(struct uart_bas *bas); 66 static void imx_uart_init(struct uart_bas *bas, int, int, int, int); 67 static void imx_uart_term(struct uart_bas *bas); 68 static void imx_uart_putc(struct uart_bas *bas, int); 69 static int imx_uart_rxready(struct uart_bas *bas); 70 static int imx_uart_getc(struct uart_bas *bas, struct mtx *); 71 72 static struct uart_ops uart_imx_uart_ops = { 73 .probe = imx_uart_probe, 74 .init = imx_uart_init, 75 .term = imx_uart_term, 76 .putc = imx_uart_putc, 77 .rxready = imx_uart_rxready, 78 .getc = imx_uart_getc, 79 }; 80 81 #if 0 /* Handy when debugging. */ 82 static void 83 dumpregs(struct uart_bas *bas, const char * msg) 84 { 85 86 if (!bootverbose) 87 return; 88 printf("%s bsh 0x%08lx UCR1 0x%08x UCR2 0x%08x " 89 "UCR3 0x%08x UCR4 0x%08x USR1 0x%08x USR2 0x%08x\n", 90 msg, bas->bsh, 91 GETREG(bas, REG(UCR1)), GETREG(bas, REG(UCR2)), 92 GETREG(bas, REG(UCR3)), GETREG(bas, REG(UCR4)), 93 GETREG(bas, REG(USR1)), GETREG(bas, REG(USR2))); 94 } 95 #endif 96 97 static int 98 imx_uart_probe(struct uart_bas *bas) 99 { 100 101 return (0); 102 } 103 104 static u_int 105 imx_uart_getbaud(struct uart_bas *bas) 106 { 107 uint32_t rate, ubir, ubmr; 108 u_int baud, blo, bhi, i; 109 static const u_int predivs[] = {6, 5, 4, 3, 2, 1, 7, 1}; 110 static const u_int std_rates[] = { 111 9600, 14400, 19200, 38400, 57600, 115200, 230400, 460800, 921600 112 }; 113 114 /* 115 * Get the baud rate the hardware is programmed for, then search the 116 * table of standard baud rates for a number that's within 3% of the 117 * actual rate the hardware is programmed for. It's more comforting to 118 * see that your console is running at 115200 than 114942. Note that 119 * here we cannot make a simplifying assumption that the predivider and 120 * numerator are 1 (like we do when setting the baud rate), because we 121 * don't know what u-boot might have set up. 122 */ 123 i = (GETREG(bas, REG(UFCR)) & IMXUART_UFCR_RFDIV_MASK) >> 124 IMXUART_UFCR_RFDIV_SHIFT; 125 rate = imx_ccm_uart_hz() / predivs[i]; 126 ubir = GETREG(bas, REG(UBIR)) + 1; 127 ubmr = GETREG(bas, REG(UBMR)) + 1; 128 baud = ((rate / 16 ) * ubir) / ubmr; 129 130 blo = (baud * 100) / 103; 131 bhi = (baud * 100) / 97; 132 for (i = 0; i < nitems(std_rates); i++) { 133 rate = std_rates[i]; 134 if (rate >= blo && rate <= bhi) { 135 baud = rate; 136 break; 137 } 138 } 139 140 return (baud); 141 } 142 143 static void 144 imx_uart_init(struct uart_bas *bas, int baudrate, int databits, 145 int stopbits, int parity) 146 { 147 uint32_t baseclk, reg; 148 149 /* Enable the device and the RX/TX channels. */ 150 SET(bas, REG(UCR1), FLD(UCR1, UARTEN)); 151 SET(bas, REG(UCR2), FLD(UCR2, RXEN) | FLD(UCR2, TXEN)); 152 153 if (databits == 7) 154 DIS(bas, UCR2, WS); 155 else 156 ENA(bas, UCR2, WS); 157 158 if (stopbits == 2) 159 ENA(bas, UCR2, STPB); 160 else 161 DIS(bas, UCR2, STPB); 162 163 switch (parity) { 164 case UART_PARITY_ODD: 165 DIS(bas, UCR2, PROE); 166 ENA(bas, UCR2, PREN); 167 break; 168 case UART_PARITY_EVEN: 169 ENA(bas, UCR2, PROE); 170 ENA(bas, UCR2, PREN); 171 break; 172 case UART_PARITY_MARK: 173 case UART_PARITY_SPACE: 174 /* FALLTHROUGH: Hardware doesn't support mark/space. */ 175 case UART_PARITY_NONE: 176 default: 177 DIS(bas, UCR2, PREN); 178 break; 179 } 180 181 /* 182 * The hardware has an extremely flexible baud clock: it allows setting 183 * both the numerator and denominator of the divider, as well as a 184 * separate pre-divider. We simplify the problem of coming up with a 185 * workable pair of numbers by assuming a pre-divider and numerator of 186 * one because our base clock is so fast we can reach virtually any 187 * reasonable speed with a simple divisor. The numerator value actually 188 * includes the 16x over-sampling (so a value of 16 means divide by 1); 189 * the register value is the numerator-1, so we have a hard-coded 15. 190 * Note that a quirk of the hardware requires that both UBIR and UBMR be 191 * set back to back in order for the change to take effect. 192 */ 193 if (baudrate > 0) { 194 baseclk = imx_ccm_uart_hz(); 195 reg = GETREG(bas, REG(UFCR)); 196 reg = (reg & ~IMXUART_UFCR_RFDIV_MASK) | IMXUART_UFCR_RFDIV_DIV1; 197 SETREG(bas, REG(UFCR), reg); 198 SETREG(bas, REG(UBIR), 15); 199 SETREG(bas, REG(UBMR), (baseclk / baudrate) - 1); 200 } 201 202 /* 203 * Program the tx lowater and rx hiwater levels at which fifo-service 204 * interrupts are signaled. The tx value is interpetted as "when there 205 * are only this many bytes remaining" (not "this many free"). 206 */ 207 reg = GETREG(bas, REG(UFCR)); 208 reg &= ~(IMXUART_UFCR_TXTL_MASK | IMXUART_UFCR_RXTL_MASK); 209 reg |= (IMX_FIFOSZ - IMX_TXFIFO_LEVEL) << IMXUART_UFCR_TXTL_SHIFT; 210 reg |= IMX_RXFIFO_LEVEL << IMXUART_UFCR_RXTL_SHIFT; 211 SETREG(bas, REG(UFCR), reg); 212 } 213 214 static void 215 imx_uart_term(struct uart_bas *bas) 216 { 217 218 } 219 220 static void 221 imx_uart_putc(struct uart_bas *bas, int c) 222 { 223 224 while (!(IS(bas, USR1, TRDY))) 225 ; 226 SETREG(bas, REG(UTXD), c); 227 } 228 229 static int 230 imx_uart_rxready(struct uart_bas *bas) 231 { 232 233 return ((IS(bas, USR2, RDR)) ? 1 : 0); 234 } 235 236 static int 237 imx_uart_getc(struct uart_bas *bas, struct mtx *hwmtx) 238 { 239 int c; 240 241 uart_lock(hwmtx); 242 while (!(IS(bas, USR2, RDR))) 243 ; 244 245 c = GETREG(bas, REG(URXD)); 246 uart_unlock(hwmtx); 247 #if defined(KDB) 248 if (c & FLD(URXD, BRK)) { 249 if (kdb_break()) 250 return (0); 251 } 252 #endif 253 return (c & 0xff); 254 } 255 256 /* 257 * High-level UART interface. 258 */ 259 struct imx_uart_softc { 260 struct uart_softc base; 261 }; 262 263 static int imx_uart_bus_attach(struct uart_softc *); 264 static int imx_uart_bus_detach(struct uart_softc *); 265 static int imx_uart_bus_flush(struct uart_softc *, int); 266 static int imx_uart_bus_getsig(struct uart_softc *); 267 static int imx_uart_bus_ioctl(struct uart_softc *, int, intptr_t); 268 static int imx_uart_bus_ipend(struct uart_softc *); 269 static int imx_uart_bus_param(struct uart_softc *, int, int, int, int); 270 static int imx_uart_bus_probe(struct uart_softc *); 271 static int imx_uart_bus_receive(struct uart_softc *); 272 static int imx_uart_bus_setsig(struct uart_softc *, int); 273 static int imx_uart_bus_transmit(struct uart_softc *); 274 static void imx_uart_bus_grab(struct uart_softc *); 275 static void imx_uart_bus_ungrab(struct uart_softc *); 276 277 static kobj_method_t imx_uart_methods[] = { 278 KOBJMETHOD(uart_attach, imx_uart_bus_attach), 279 KOBJMETHOD(uart_detach, imx_uart_bus_detach), 280 KOBJMETHOD(uart_flush, imx_uart_bus_flush), 281 KOBJMETHOD(uart_getsig, imx_uart_bus_getsig), 282 KOBJMETHOD(uart_ioctl, imx_uart_bus_ioctl), 283 KOBJMETHOD(uart_ipend, imx_uart_bus_ipend), 284 KOBJMETHOD(uart_param, imx_uart_bus_param), 285 KOBJMETHOD(uart_probe, imx_uart_bus_probe), 286 KOBJMETHOD(uart_receive, imx_uart_bus_receive), 287 KOBJMETHOD(uart_setsig, imx_uart_bus_setsig), 288 KOBJMETHOD(uart_transmit, imx_uart_bus_transmit), 289 KOBJMETHOD(uart_grab, imx_uart_bus_grab), 290 KOBJMETHOD(uart_ungrab, imx_uart_bus_ungrab), 291 { 0, 0 } 292 }; 293 294 struct uart_class uart_imx_class = { 295 "imx", 296 imx_uart_methods, 297 sizeof(struct imx_uart_softc), 298 .uc_ops = &uart_imx_uart_ops, 299 .uc_range = 0x100, 300 .uc_rclk = 24000000 /* TODO: get value from CCM */ 301 }; 302 303 #define SIGCHG(c, i, s, d) \ 304 if (c) { \ 305 i |= (i & s) ? s : s | d; \ 306 } else { \ 307 i = (i & s) ? (i & ~s) | d : i; \ 308 } 309 310 static int 311 imx_uart_bus_attach(struct uart_softc *sc) 312 { 313 struct uart_bas *bas; 314 struct uart_devinfo *di; 315 316 bas = &sc->sc_bas; 317 if (sc->sc_sysdev != NULL) { 318 di = sc->sc_sysdev; 319 imx_uart_init(bas, di->baudrate, di->databits, di->stopbits, 320 di->parity); 321 } else { 322 imx_uart_init(bas, 115200, 8, 1, 0); 323 } 324 325 (void)imx_uart_bus_getsig(sc); 326 327 /* Clear all pending interrupts. */ 328 SETREG(bas, REG(USR1), 0xffff); 329 SETREG(bas, REG(USR2), 0xffff); 330 331 DIS(bas, UCR4, DREN); 332 ENA(bas, UCR1, RRDYEN); 333 DIS(bas, UCR1, IDEN); 334 DIS(bas, UCR3, RXDSEN); 335 ENA(bas, UCR2, ATEN); 336 DIS(bas, UCR1, TXMPTYEN); 337 DIS(bas, UCR1, TRDYEN); 338 DIS(bas, UCR4, TCEN); 339 DIS(bas, UCR4, OREN); 340 ENA(bas, UCR4, BKEN); 341 DIS(bas, UCR4, WKEN); 342 DIS(bas, UCR1, ADEN); 343 DIS(bas, UCR3, ACIEN); 344 DIS(bas, UCR2, ESCI); 345 DIS(bas, UCR4, ENIRI); 346 DIS(bas, UCR3, AIRINTEN); 347 DIS(bas, UCR3, AWAKEN); 348 DIS(bas, UCR3, FRAERREN); 349 DIS(bas, UCR3, PARERREN); 350 DIS(bas, UCR1, RTSDEN); 351 DIS(bas, UCR2, RTSEN); 352 DIS(bas, UCR3, DTREN); 353 DIS(bas, UCR3, RI); 354 DIS(bas, UCR3, DCD); 355 DIS(bas, UCR3, DTRDEN); 356 ENA(bas, UCR2, IRTS); 357 ENA(bas, UCR3, RXDMUXSEL); 358 359 return (0); 360 } 361 362 static int 363 imx_uart_bus_detach(struct uart_softc *sc) 364 { 365 366 SETREG(&sc->sc_bas, REG(UCR4), 0); 367 368 return (0); 369 } 370 371 static int 372 imx_uart_bus_flush(struct uart_softc *sc, int what) 373 { 374 375 /* TODO */ 376 return (0); 377 } 378 379 static int 380 imx_uart_bus_getsig(struct uart_softc *sc) 381 { 382 uint32_t new, old, sig; 383 uint8_t bes; 384 385 do { 386 old = sc->sc_hwsig; 387 sig = old; 388 uart_lock(sc->sc_hwmtx); 389 bes = GETREG(&sc->sc_bas, REG(USR2)); 390 uart_unlock(sc->sc_hwmtx); 391 /* XXX: chip can show delta */ 392 SIGCHG(bes & FLD(USR2, DCDIN), sig, SER_DCD, SER_DDCD); 393 new = sig & ~SER_MASK_DELTA; 394 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 395 396 return (sig); 397 } 398 399 static int 400 imx_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 401 { 402 struct uart_bas *bas; 403 int error; 404 405 bas = &sc->sc_bas; 406 error = 0; 407 uart_lock(sc->sc_hwmtx); 408 switch (request) { 409 case UART_IOCTL_BREAK: 410 /* TODO */ 411 break; 412 case UART_IOCTL_BAUD: 413 *(u_int*)data = imx_uart_getbaud(bas); 414 break; 415 default: 416 error = EINVAL; 417 break; 418 } 419 uart_unlock(sc->sc_hwmtx); 420 421 return (error); 422 } 423 424 static int 425 imx_uart_bus_ipend(struct uart_softc *sc) 426 { 427 struct uart_bas *bas; 428 int ipend; 429 uint32_t usr1, usr2; 430 uint32_t ucr1, ucr2, ucr4; 431 432 bas = &sc->sc_bas; 433 ipend = 0; 434 435 uart_lock(sc->sc_hwmtx); 436 437 /* Read pending interrupts */ 438 usr1 = GETREG(bas, REG(USR1)); 439 usr2 = GETREG(bas, REG(USR2)); 440 /* ACK interrupts */ 441 SETREG(bas, REG(USR1), usr1); 442 SETREG(bas, REG(USR2), usr2); 443 444 ucr1 = GETREG(bas, REG(UCR1)); 445 ucr2 = GETREG(bas, REG(UCR2)); 446 ucr4 = GETREG(bas, REG(UCR4)); 447 448 /* If we have reached tx low-water, we can tx some more now. */ 449 if ((usr1 & FLD(USR1, TRDY)) && (ucr1 & FLD(UCR1, TRDYEN))) { 450 DIS(bas, UCR1, TRDYEN); 451 ipend |= SER_INT_TXIDLE; 452 } 453 454 /* 455 * If we have reached the rx high-water, or if there are bytes in the rx 456 * fifo and no new data has arrived for 8 character periods (aging 457 * timer), we have input data to process. 458 */ 459 if (((usr1 & FLD(USR1, RRDY)) && (ucr1 & FLD(UCR1, RRDYEN))) || 460 ((usr1 & FLD(USR1, AGTIM)) && (ucr2 & FLD(UCR2, ATEN)))) { 461 DIS(bas, UCR1, RRDYEN); 462 DIS(bas, UCR2, ATEN); 463 ipend |= SER_INT_RXREADY; 464 } 465 466 /* A break can come in at any time, it never gets disabled. */ 467 if ((usr2 & FLD(USR2, BRCD)) && (ucr4 & FLD(UCR4, BKEN))) 468 ipend |= SER_INT_BREAK; 469 470 uart_unlock(sc->sc_hwmtx); 471 472 return (ipend); 473 } 474 475 static int 476 imx_uart_bus_param(struct uart_softc *sc, int baudrate, int databits, 477 int stopbits, int parity) 478 { 479 480 uart_lock(sc->sc_hwmtx); 481 imx_uart_init(&sc->sc_bas, baudrate, databits, stopbits, parity); 482 uart_unlock(sc->sc_hwmtx); 483 return (0); 484 } 485 486 static int 487 imx_uart_bus_probe(struct uart_softc *sc) 488 { 489 int error; 490 491 error = imx_uart_probe(&sc->sc_bas); 492 if (error) 493 return (error); 494 495 /* 496 * On input we can read up to the full fifo size at once. On output, we 497 * want to write only as much as the programmed tx low water level, 498 * because that's all we can be certain we have room for in the fifo 499 * when we get a tx-ready interrupt. 500 */ 501 sc->sc_rxfifosz = IMX_FIFOSZ; 502 sc->sc_txfifosz = IMX_TXFIFO_LEVEL; 503 504 device_set_desc(sc->sc_dev, "Freescale i.MX UART"); 505 return (0); 506 } 507 508 static int 509 imx_uart_bus_receive(struct uart_softc *sc) 510 { 511 struct uart_bas *bas; 512 int xc, out; 513 514 bas = &sc->sc_bas; 515 uart_lock(sc->sc_hwmtx); 516 517 /* 518 * Empty the rx fifo. We get the RRDY interrupt when IMX_RXFIFO_LEVEL 519 * (the rx high-water level) is reached, but we set sc_rxfifosz to the 520 * full hardware fifo size, so we can safely process however much is 521 * there, not just the highwater size. 522 */ 523 while (IS(bas, USR2, RDR)) { 524 if (uart_rx_full(sc)) { 525 /* No space left in input buffer */ 526 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 527 break; 528 } 529 xc = GETREG(bas, REG(URXD)); 530 out = xc & 0x000000ff; 531 if (xc & FLD(URXD, FRMERR)) 532 out |= UART_STAT_FRAMERR; 533 if (xc & FLD(URXD, PRERR)) 534 out |= UART_STAT_PARERR; 535 if (xc & FLD(URXD, OVRRUN)) 536 out |= UART_STAT_OVERRUN; 537 if (xc & FLD(URXD, BRK)) 538 out |= UART_STAT_BREAK; 539 540 uart_rx_put(sc, out); 541 } 542 ENA(bas, UCR1, RRDYEN); 543 ENA(bas, UCR2, ATEN); 544 545 uart_unlock(sc->sc_hwmtx); 546 return (0); 547 } 548 549 static int 550 imx_uart_bus_setsig(struct uart_softc *sc, int sig) 551 { 552 553 return (0); 554 } 555 556 static int 557 imx_uart_bus_transmit(struct uart_softc *sc) 558 { 559 struct uart_bas *bas = &sc->sc_bas; 560 int i; 561 562 bas = &sc->sc_bas; 563 uart_lock(sc->sc_hwmtx); 564 565 /* 566 * Fill the tx fifo. The uart core puts at most IMX_TXFIFO_LEVEL bytes 567 * into the txbuf (because that's what sc_txfifosz is set to), and 568 * because we got the TRDY (low-water reached) interrupt we know at 569 * least that much space is available in the fifo. 570 */ 571 for (i = 0; i < sc->sc_txdatasz; i++) { 572 SETREG(bas, REG(UTXD), sc->sc_txbuf[i] & 0xff); 573 } 574 sc->sc_txbusy = 1; 575 ENA(bas, UCR1, TRDYEN); 576 577 uart_unlock(sc->sc_hwmtx); 578 579 return (0); 580 } 581 582 static void 583 imx_uart_bus_grab(struct uart_softc *sc) 584 { 585 struct uart_bas *bas = &sc->sc_bas; 586 587 bas = &sc->sc_bas; 588 uart_lock(sc->sc_hwmtx); 589 DIS(bas, UCR1, RRDYEN); 590 DIS(bas, UCR2, ATEN); 591 uart_unlock(sc->sc_hwmtx); 592 } 593 594 static void 595 imx_uart_bus_ungrab(struct uart_softc *sc) 596 { 597 struct uart_bas *bas = &sc->sc_bas; 598 599 bas = &sc->sc_bas; 600 uart_lock(sc->sc_hwmtx); 601 ENA(bas, UCR1, RRDYEN); 602 ENA(bas, UCR2, ATEN); 603 uart_unlock(sc->sc_hwmtx); 604 } 605