1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 #ifdef HAVE_KERNEL_OPTION_HEADERS 39 #include "opt_device_polling.h" 40 #endif 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/bus.h> 45 #include <sys/endian.h> 46 #include <sys/kernel.h> 47 #include <sys/lock.h> 48 #include <sys/malloc.h> 49 #include <sys/mbuf.h> 50 #include <sys/module.h> 51 #include <sys/rman.h> 52 #include <sys/socket.h> 53 #include <sys/sockio.h> 54 #include <sys/sysctl.h> 55 56 #include <net/bpf.h> 57 #include <net/if.h> 58 #include <net/if_var.h> 59 #include <net/if_arp.h> 60 #include <net/ethernet.h> 61 #include <net/if_dl.h> 62 #include <net/if_media.h> 63 #include <net/if_types.h> 64 #include <net/if_vlan_var.h> 65 66 #include <machine/bus.h> 67 #include <machine/resource.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/mii_bitbang.h> 71 #include <dev/mii/miivar.h> 72 73 #include <dev/pci/pcireg.h> 74 #include <dev/pci/pcivar.h> 75 76 #include <dev/ste/if_stereg.h> 77 78 /* "device miibus" required. See GENERIC if you get errors here. */ 79 #include "miibus_if.h" 80 81 MODULE_DEPEND(ste, pci, 1, 1, 1); 82 MODULE_DEPEND(ste, ether, 1, 1, 1); 83 MODULE_DEPEND(ste, miibus, 1, 1, 1); 84 85 /* Define to show Tx error status. */ 86 #define STE_SHOW_TXERRORS 87 88 /* 89 * Various supported device vendors/types and their names. 90 */ 91 static const struct ste_type ste_devs[] = { 92 { ST_VENDORID, ST_DEVICEID_ST201_1, "Sundance ST201 10/100BaseTX" }, 93 { ST_VENDORID, ST_DEVICEID_ST201_2, "Sundance ST201 10/100BaseTX" }, 94 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 95 { 0, 0, NULL } 96 }; 97 98 static int ste_attach(device_t); 99 static int ste_detach(device_t); 100 static int ste_probe(device_t); 101 static int ste_resume(device_t); 102 static int ste_shutdown(device_t); 103 static int ste_suspend(device_t); 104 105 static int ste_dma_alloc(struct ste_softc *); 106 static void ste_dma_free(struct ste_softc *); 107 static void ste_dmamap_cb(void *, bus_dma_segment_t *, int, int); 108 static int ste_eeprom_wait(struct ste_softc *); 109 static int ste_encap(struct ste_softc *, struct mbuf **, 110 struct ste_chain *); 111 static int ste_ifmedia_upd(if_t); 112 static void ste_ifmedia_sts(if_t, struct ifmediareq *); 113 static void ste_init(void *); 114 static void ste_init_locked(struct ste_softc *); 115 static int ste_init_rx_list(struct ste_softc *); 116 static void ste_init_tx_list(struct ste_softc *); 117 static void ste_intr(void *); 118 static int ste_ioctl(if_t, u_long, caddr_t); 119 static uint32_t ste_mii_bitbang_read(device_t); 120 static void ste_mii_bitbang_write(device_t, uint32_t); 121 static int ste_miibus_readreg(device_t, int, int); 122 static void ste_miibus_statchg(device_t); 123 static int ste_miibus_writereg(device_t, int, int, int); 124 static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *); 125 static int ste_read_eeprom(struct ste_softc *, uint16_t *, int, int); 126 static void ste_reset(struct ste_softc *); 127 static void ste_restart_tx(struct ste_softc *); 128 static int ste_rxeof(struct ste_softc *, int); 129 static void ste_rxfilter(struct ste_softc *); 130 static void ste_setwol(struct ste_softc *); 131 static void ste_start(if_t); 132 static void ste_start_locked(if_t); 133 static void ste_stats_clear(struct ste_softc *); 134 static void ste_stats_update(struct ste_softc *); 135 static void ste_stop(struct ste_softc *); 136 static void ste_sysctl_node(struct ste_softc *); 137 static void ste_tick(void *); 138 static void ste_txeoc(struct ste_softc *); 139 static void ste_txeof(struct ste_softc *); 140 static void ste_wait(struct ste_softc *); 141 static void ste_watchdog(struct ste_softc *); 142 143 /* 144 * MII bit-bang glue 145 */ 146 static const struct mii_bitbang_ops ste_mii_bitbang_ops = { 147 ste_mii_bitbang_read, 148 ste_mii_bitbang_write, 149 { 150 STE_PHYCTL_MDATA, /* MII_BIT_MDO */ 151 STE_PHYCTL_MDATA, /* MII_BIT_MDI */ 152 STE_PHYCTL_MCLK, /* MII_BIT_MDC */ 153 STE_PHYCTL_MDIR, /* MII_BIT_DIR_HOST_PHY */ 154 0, /* MII_BIT_DIR_PHY_HOST */ 155 } 156 }; 157 158 static device_method_t ste_methods[] = { 159 /* Device interface */ 160 DEVMETHOD(device_probe, ste_probe), 161 DEVMETHOD(device_attach, ste_attach), 162 DEVMETHOD(device_detach, ste_detach), 163 DEVMETHOD(device_shutdown, ste_shutdown), 164 DEVMETHOD(device_suspend, ste_suspend), 165 DEVMETHOD(device_resume, ste_resume), 166 167 /* MII interface */ 168 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 169 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 170 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 171 172 DEVMETHOD_END 173 }; 174 175 static driver_t ste_driver = { 176 "ste", 177 ste_methods, 178 sizeof(struct ste_softc) 179 }; 180 181 DRIVER_MODULE(ste, pci, ste_driver, 0, 0); 182 DRIVER_MODULE(miibus, ste, miibus_driver, 0, 0); 183 184 #define STE_SETBIT4(sc, reg, x) \ 185 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 186 187 #define STE_CLRBIT4(sc, reg, x) \ 188 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 189 190 #define STE_SETBIT2(sc, reg, x) \ 191 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 192 193 #define STE_CLRBIT2(sc, reg, x) \ 194 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 195 196 #define STE_SETBIT1(sc, reg, x) \ 197 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 198 199 #define STE_CLRBIT1(sc, reg, x) \ 200 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 201 202 /* 203 * Read the MII serial port for the MII bit-bang module. 204 */ 205 static uint32_t 206 ste_mii_bitbang_read(device_t dev) 207 { 208 struct ste_softc *sc; 209 uint32_t val; 210 211 sc = device_get_softc(dev); 212 213 val = CSR_READ_1(sc, STE_PHYCTL); 214 CSR_BARRIER(sc, STE_PHYCTL, 1, 215 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 216 217 return (val); 218 } 219 220 /* 221 * Write the MII serial port for the MII bit-bang module. 222 */ 223 static void 224 ste_mii_bitbang_write(device_t dev, uint32_t val) 225 { 226 struct ste_softc *sc; 227 228 sc = device_get_softc(dev); 229 230 CSR_WRITE_1(sc, STE_PHYCTL, val); 231 CSR_BARRIER(sc, STE_PHYCTL, 1, 232 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 233 } 234 235 static int 236 ste_miibus_readreg(device_t dev, int phy, int reg) 237 { 238 239 return (mii_bitbang_readreg(dev, &ste_mii_bitbang_ops, phy, reg)); 240 } 241 242 static int 243 ste_miibus_writereg(device_t dev, int phy, int reg, int data) 244 { 245 246 mii_bitbang_writereg(dev, &ste_mii_bitbang_ops, phy, reg, data); 247 248 return (0); 249 } 250 251 static void 252 ste_miibus_statchg(device_t dev) 253 { 254 struct ste_softc *sc; 255 struct mii_data *mii; 256 if_t ifp; 257 uint16_t cfg; 258 259 sc = device_get_softc(dev); 260 261 mii = device_get_softc(sc->ste_miibus); 262 ifp = sc->ste_ifp; 263 if (mii == NULL || ifp == NULL || 264 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 265 return; 266 267 sc->ste_flags &= ~STE_FLAG_LINK; 268 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 269 (IFM_ACTIVE | IFM_AVALID)) { 270 switch (IFM_SUBTYPE(mii->mii_media_active)) { 271 case IFM_10_T: 272 case IFM_100_TX: 273 case IFM_100_FX: 274 case IFM_100_T4: 275 sc->ste_flags |= STE_FLAG_LINK; 276 default: 277 break; 278 } 279 } 280 281 /* Program MACs with resolved speed/duplex/flow-control. */ 282 if ((sc->ste_flags & STE_FLAG_LINK) != 0) { 283 cfg = CSR_READ_2(sc, STE_MACCTL0); 284 cfg &= ~(STE_MACCTL0_FLOWCTL_ENABLE | STE_MACCTL0_FULLDUPLEX); 285 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 286 /* 287 * ST201 data sheet says driver should enable receiving 288 * MAC control frames bit of receive mode register to 289 * receive flow-control frames but the register has no 290 * such bits. In addition the controller has no ability 291 * to send pause frames so it should be handled in 292 * driver. Implementing pause timer handling in driver 293 * layer is not trivial, so don't enable flow-control 294 * here. 295 */ 296 cfg |= STE_MACCTL0_FULLDUPLEX; 297 } 298 CSR_WRITE_2(sc, STE_MACCTL0, cfg); 299 } 300 } 301 302 static int 303 ste_ifmedia_upd(if_t ifp) 304 { 305 struct ste_softc *sc; 306 struct mii_data *mii; 307 struct mii_softc *miisc; 308 int error; 309 310 sc = if_getsoftc(ifp); 311 STE_LOCK(sc); 312 mii = device_get_softc(sc->ste_miibus); 313 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 314 PHY_RESET(miisc); 315 error = mii_mediachg(mii); 316 STE_UNLOCK(sc); 317 318 return (error); 319 } 320 321 static void 322 ste_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 323 { 324 struct ste_softc *sc; 325 struct mii_data *mii; 326 327 sc = if_getsoftc(ifp); 328 mii = device_get_softc(sc->ste_miibus); 329 330 STE_LOCK(sc); 331 if ((if_getflags(ifp) & IFF_UP) == 0) { 332 STE_UNLOCK(sc); 333 return; 334 } 335 mii_pollstat(mii); 336 ifmr->ifm_active = mii->mii_media_active; 337 ifmr->ifm_status = mii->mii_media_status; 338 STE_UNLOCK(sc); 339 } 340 341 static void 342 ste_wait(struct ste_softc *sc) 343 { 344 int i; 345 346 for (i = 0; i < STE_TIMEOUT; i++) { 347 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 348 break; 349 DELAY(1); 350 } 351 352 if (i == STE_TIMEOUT) 353 device_printf(sc->ste_dev, "command never completed!\n"); 354 } 355 356 /* 357 * The EEPROM is slow: give it time to come ready after issuing 358 * it a command. 359 */ 360 static int 361 ste_eeprom_wait(struct ste_softc *sc) 362 { 363 int i; 364 365 DELAY(1000); 366 367 for (i = 0; i < 100; i++) { 368 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 369 DELAY(1000); 370 else 371 break; 372 } 373 374 if (i == 100) { 375 device_printf(sc->ste_dev, "eeprom failed to come ready\n"); 376 return (1); 377 } 378 379 return (0); 380 } 381 382 /* 383 * Read a sequence of words from the EEPROM. Note that ethernet address 384 * data is stored in the EEPROM in network byte order. 385 */ 386 static int 387 ste_read_eeprom(struct ste_softc *sc, uint16_t *dest, int off, int cnt) 388 { 389 int err = 0, i; 390 391 if (ste_eeprom_wait(sc)) 392 return (1); 393 394 for (i = 0; i < cnt; i++) { 395 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 396 err = ste_eeprom_wait(sc); 397 if (err) 398 break; 399 *dest = le16toh(CSR_READ_2(sc, STE_EEPROM_DATA)); 400 dest++; 401 } 402 403 return (err ? 1 : 0); 404 } 405 406 static u_int 407 ste_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 408 { 409 uint32_t *hashes = arg; 410 int h; 411 412 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) & 0x3F; 413 if (h < 32) 414 hashes[0] |= (1 << h); 415 else 416 hashes[1] |= (1 << (h - 32)); 417 418 return (1); 419 } 420 421 static void 422 ste_rxfilter(struct ste_softc *sc) 423 { 424 if_t ifp; 425 uint32_t hashes[2] = { 0, 0 }; 426 uint8_t rxcfg; 427 428 STE_LOCK_ASSERT(sc); 429 430 ifp = sc->ste_ifp; 431 rxcfg = CSR_READ_1(sc, STE_RX_MODE); 432 rxcfg |= STE_RXMODE_UNICAST; 433 rxcfg &= ~(STE_RXMODE_ALLMULTI | STE_RXMODE_MULTIHASH | 434 STE_RXMODE_BROADCAST | STE_RXMODE_PROMISC); 435 if (if_getflags(ifp) & IFF_BROADCAST) 436 rxcfg |= STE_RXMODE_BROADCAST; 437 if ((if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 438 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 439 rxcfg |= STE_RXMODE_ALLMULTI; 440 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 441 rxcfg |= STE_RXMODE_PROMISC; 442 goto chipit; 443 } 444 445 rxcfg |= STE_RXMODE_MULTIHASH; 446 /* Now program new ones. */ 447 if_foreach_llmaddr(ifp, ste_hash_maddr, hashes); 448 449 chipit: 450 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 451 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 452 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 453 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 454 CSR_WRITE_1(sc, STE_RX_MODE, rxcfg); 455 CSR_READ_1(sc, STE_RX_MODE); 456 } 457 458 #ifdef DEVICE_POLLING 459 static poll_handler_t ste_poll, ste_poll_locked; 460 461 static int 462 ste_poll(if_t ifp, enum poll_cmd cmd, int count) 463 { 464 struct ste_softc *sc = if_getsoftc(ifp); 465 int rx_npkts = 0; 466 467 STE_LOCK(sc); 468 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 469 rx_npkts = ste_poll_locked(ifp, cmd, count); 470 STE_UNLOCK(sc); 471 return (rx_npkts); 472 } 473 474 static int 475 ste_poll_locked(if_t ifp, enum poll_cmd cmd, int count) 476 { 477 struct ste_softc *sc = if_getsoftc(ifp); 478 int rx_npkts; 479 480 STE_LOCK_ASSERT(sc); 481 482 rx_npkts = ste_rxeof(sc, count); 483 ste_txeof(sc); 484 ste_txeoc(sc); 485 if (!if_sendq_empty(ifp)) 486 ste_start_locked(ifp); 487 488 if (cmd == POLL_AND_CHECK_STATUS) { 489 uint16_t status; 490 491 status = CSR_READ_2(sc, STE_ISR_ACK); 492 493 if (status & STE_ISR_STATS_OFLOW) 494 ste_stats_update(sc); 495 496 if (status & STE_ISR_HOSTERR) { 497 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 498 ste_init_locked(sc); 499 } 500 } 501 return (rx_npkts); 502 } 503 #endif /* DEVICE_POLLING */ 504 505 static void 506 ste_intr(void *xsc) 507 { 508 struct ste_softc *sc; 509 if_t ifp; 510 uint16_t intrs, status; 511 512 sc = xsc; 513 STE_LOCK(sc); 514 ifp = sc->ste_ifp; 515 516 #ifdef DEVICE_POLLING 517 if (if_getcapenable(ifp) & IFCAP_POLLING) { 518 STE_UNLOCK(sc); 519 return; 520 } 521 #endif 522 /* Reading STE_ISR_ACK clears STE_IMR register. */ 523 status = CSR_READ_2(sc, STE_ISR_ACK); 524 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 525 STE_UNLOCK(sc); 526 return; 527 } 528 529 intrs = STE_INTRS; 530 if (status == 0xFFFF || (status & intrs) == 0) 531 goto done; 532 533 if (sc->ste_int_rx_act > 0) { 534 status &= ~STE_ISR_RX_DMADONE; 535 intrs &= ~STE_IMR_RX_DMADONE; 536 } 537 538 if ((status & (STE_ISR_SOFTINTR | STE_ISR_RX_DMADONE)) != 0) { 539 ste_rxeof(sc, -1); 540 /* 541 * The controller has no ability to Rx interrupt 542 * moderation feature. Receiving 64 bytes frames 543 * from wire generates too many interrupts which in 544 * turn make system useless to process other useful 545 * things. Fortunately ST201 supports single shot 546 * timer so use the timer to implement Rx interrupt 547 * moderation in driver. This adds more register 548 * access but it greatly reduces number of Rx 549 * interrupts under high network load. 550 */ 551 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 552 (sc->ste_int_rx_mod != 0)) { 553 if ((status & STE_ISR_RX_DMADONE) != 0) { 554 CSR_WRITE_2(sc, STE_COUNTDOWN, 555 STE_TIMER_USECS(sc->ste_int_rx_mod)); 556 intrs &= ~STE_IMR_RX_DMADONE; 557 sc->ste_int_rx_act = 1; 558 } else { 559 intrs |= STE_IMR_RX_DMADONE; 560 sc->ste_int_rx_act = 0; 561 } 562 } 563 } 564 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 565 if ((status & STE_ISR_TX_DMADONE) != 0) 566 ste_txeof(sc); 567 if ((status & STE_ISR_TX_DONE) != 0) 568 ste_txeoc(sc); 569 if ((status & STE_ISR_STATS_OFLOW) != 0) 570 ste_stats_update(sc); 571 if ((status & STE_ISR_HOSTERR) != 0) { 572 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 573 ste_init_locked(sc); 574 STE_UNLOCK(sc); 575 return; 576 } 577 if (!if_sendq_empty(ifp)) 578 ste_start_locked(ifp); 579 done: 580 /* Re-enable interrupts */ 581 CSR_WRITE_2(sc, STE_IMR, intrs); 582 } 583 STE_UNLOCK(sc); 584 } 585 586 /* 587 * A frame has been uploaded: pass the resulting mbuf chain up to 588 * the higher level protocols. 589 */ 590 static int 591 ste_rxeof(struct ste_softc *sc, int count) 592 { 593 struct mbuf *m; 594 if_t ifp; 595 struct ste_chain_onefrag *cur_rx; 596 uint32_t rxstat; 597 int total_len, rx_npkts; 598 599 ifp = sc->ste_ifp; 600 601 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 602 sc->ste_cdata.ste_rx_list_map, 603 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 604 605 cur_rx = sc->ste_cdata.ste_rx_head; 606 for (rx_npkts = 0; rx_npkts < STE_RX_LIST_CNT; rx_npkts++, 607 cur_rx = cur_rx->ste_next) { 608 rxstat = le32toh(cur_rx->ste_ptr->ste_status); 609 if ((rxstat & STE_RXSTAT_DMADONE) == 0) 610 break; 611 #ifdef DEVICE_POLLING 612 if (if_getcapenable(ifp) & IFCAP_POLLING) { 613 if (count == 0) 614 break; 615 count--; 616 } 617 #endif 618 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 619 break; 620 /* 621 * If an error occurs, update stats, clear the 622 * status word and leave the mbuf cluster in place: 623 * it should simply get re-used next time this descriptor 624 * comes up in the ring. 625 */ 626 if (rxstat & STE_RXSTAT_FRAME_ERR) { 627 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 628 cur_rx->ste_ptr->ste_status = 0; 629 continue; 630 } 631 632 /* No errors; receive the packet. */ 633 m = cur_rx->ste_mbuf; 634 total_len = STE_RX_BYTES(rxstat); 635 636 /* 637 * Try to conjure up a new mbuf cluster. If that 638 * fails, it means we have an out of memory condition and 639 * should leave the buffer in place and continue. This will 640 * result in a lost packet, but there's little else we 641 * can do in this situation. 642 */ 643 if (ste_newbuf(sc, cur_rx) != 0) { 644 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 645 cur_rx->ste_ptr->ste_status = 0; 646 continue; 647 } 648 649 m->m_pkthdr.rcvif = ifp; 650 m->m_pkthdr.len = m->m_len = total_len; 651 652 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 653 STE_UNLOCK(sc); 654 if_input(ifp, m); 655 STE_LOCK(sc); 656 } 657 658 if (rx_npkts > 0) { 659 sc->ste_cdata.ste_rx_head = cur_rx; 660 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 661 sc->ste_cdata.ste_rx_list_map, 662 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 663 } 664 665 return (rx_npkts); 666 } 667 668 static void 669 ste_txeoc(struct ste_softc *sc) 670 { 671 uint16_t txstat; 672 if_t ifp; 673 674 STE_LOCK_ASSERT(sc); 675 676 ifp = sc->ste_ifp; 677 678 /* 679 * STE_TX_STATUS register implements a queue of up to 31 680 * transmit status byte. Writing an arbitrary value to the 681 * register will advance the queue to the next transmit 682 * status byte. This means if driver does not read 683 * STE_TX_STATUS register after completing sending more 684 * than 31 frames the controller would be stalled so driver 685 * should re-wake the Tx MAC. This is the most severe 686 * limitation of ST201 based controller. 687 */ 688 for (;;) { 689 txstat = CSR_READ_2(sc, STE_TX_STATUS); 690 if ((txstat & STE_TXSTATUS_TXDONE) == 0) 691 break; 692 if ((txstat & (STE_TXSTATUS_UNDERRUN | 693 STE_TXSTATUS_EXCESSCOLLS | STE_TXSTATUS_RECLAIMERR | 694 STE_TXSTATUS_STATSOFLOW)) != 0) { 695 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 696 #ifdef STE_SHOW_TXERRORS 697 device_printf(sc->ste_dev, "TX error : 0x%b\n", 698 txstat & 0xFF, STE_ERR_BITS); 699 #endif 700 if ((txstat & STE_TXSTATUS_UNDERRUN) != 0 && 701 sc->ste_tx_thresh < STE_PACKET_SIZE) { 702 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 703 if (sc->ste_tx_thresh > STE_PACKET_SIZE) 704 sc->ste_tx_thresh = STE_PACKET_SIZE; 705 device_printf(sc->ste_dev, 706 "TX underrun, increasing TX" 707 " start threshold to %d bytes\n", 708 sc->ste_tx_thresh); 709 /* Make sure to disable active DMA cycles. */ 710 STE_SETBIT4(sc, STE_DMACTL, 711 STE_DMACTL_TXDMA_STALL); 712 ste_wait(sc); 713 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 714 ste_init_locked(sc); 715 break; 716 } 717 /* Restart Tx. */ 718 ste_restart_tx(sc); 719 } 720 /* 721 * Advance to next status and ACK TxComplete 722 * interrupt. ST201 data sheet was wrong here, to 723 * get next Tx status, we have to write both 724 * STE_TX_STATUS and STE_TX_FRAMEID register. 725 * Otherwise controller returns the same status 726 * as well as not acknowledge Tx completion 727 * interrupt. 728 */ 729 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 730 } 731 } 732 733 static void 734 ste_tick(void *arg) 735 { 736 struct ste_softc *sc; 737 struct mii_data *mii; 738 739 sc = (struct ste_softc *)arg; 740 741 STE_LOCK_ASSERT(sc); 742 743 mii = device_get_softc(sc->ste_miibus); 744 mii_tick(mii); 745 /* 746 * ukphy(4) does not seem to generate CB that reports 747 * resolved link state so if we know we lost a link, 748 * explicitly check the link state. 749 */ 750 if ((sc->ste_flags & STE_FLAG_LINK) == 0) 751 ste_miibus_statchg(sc->ste_dev); 752 /* 753 * Because we are not generating Tx completion 754 * interrupt for every frame, reclaim transmitted 755 * buffers here. 756 */ 757 ste_txeof(sc); 758 ste_txeoc(sc); 759 ste_stats_update(sc); 760 ste_watchdog(sc); 761 callout_reset(&sc->ste_callout, hz, ste_tick, sc); 762 } 763 764 static void 765 ste_txeof(struct ste_softc *sc) 766 { 767 if_t ifp; 768 struct ste_chain *cur_tx; 769 uint32_t txstat; 770 int idx; 771 772 STE_LOCK_ASSERT(sc); 773 774 ifp = sc->ste_ifp; 775 idx = sc->ste_cdata.ste_tx_cons; 776 if (idx == sc->ste_cdata.ste_tx_prod) 777 return; 778 779 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 780 sc->ste_cdata.ste_tx_list_map, 781 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 782 783 while (idx != sc->ste_cdata.ste_tx_prod) { 784 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 785 txstat = le32toh(cur_tx->ste_ptr->ste_ctl); 786 if ((txstat & STE_TXCTL_DMADONE) == 0) 787 break; 788 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map, 789 BUS_DMASYNC_POSTWRITE); 790 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map); 791 KASSERT(cur_tx->ste_mbuf != NULL, 792 ("%s: freeing NULL mbuf!\n", __func__)); 793 m_freem(cur_tx->ste_mbuf); 794 cur_tx->ste_mbuf = NULL; 795 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 796 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 797 sc->ste_cdata.ste_tx_cnt--; 798 STE_INC(idx, STE_TX_LIST_CNT); 799 } 800 801 sc->ste_cdata.ste_tx_cons = idx; 802 if (sc->ste_cdata.ste_tx_cnt == 0) 803 sc->ste_timer = 0; 804 } 805 806 static void 807 ste_stats_clear(struct ste_softc *sc) 808 { 809 810 STE_LOCK_ASSERT(sc); 811 812 /* Rx stats. */ 813 CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO); 814 CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI); 815 CSR_READ_2(sc, STE_STAT_RX_FRAMES); 816 CSR_READ_1(sc, STE_STAT_RX_BCAST); 817 CSR_READ_1(sc, STE_STAT_RX_MCAST); 818 CSR_READ_1(sc, STE_STAT_RX_LOST); 819 /* Tx stats. */ 820 CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO); 821 CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI); 822 CSR_READ_2(sc, STE_STAT_TX_FRAMES); 823 CSR_READ_1(sc, STE_STAT_TX_BCAST); 824 CSR_READ_1(sc, STE_STAT_TX_MCAST); 825 CSR_READ_1(sc, STE_STAT_CARRIER_ERR); 826 CSR_READ_1(sc, STE_STAT_SINGLE_COLLS); 827 CSR_READ_1(sc, STE_STAT_MULTI_COLLS); 828 CSR_READ_1(sc, STE_STAT_LATE_COLLS); 829 CSR_READ_1(sc, STE_STAT_TX_DEFER); 830 CSR_READ_1(sc, STE_STAT_TX_EXDEFER); 831 CSR_READ_1(sc, STE_STAT_TX_ABORT); 832 } 833 834 static void 835 ste_stats_update(struct ste_softc *sc) 836 { 837 if_t ifp; 838 struct ste_hw_stats *stats; 839 uint32_t val; 840 841 STE_LOCK_ASSERT(sc); 842 843 ifp = sc->ste_ifp; 844 stats = &sc->ste_stats; 845 /* Rx stats. */ 846 val = (uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO) | 847 ((uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI)) << 16; 848 val &= 0x000FFFFF; 849 stats->rx_bytes += val; 850 stats->rx_frames += CSR_READ_2(sc, STE_STAT_RX_FRAMES); 851 stats->rx_bcast_frames += CSR_READ_1(sc, STE_STAT_RX_BCAST); 852 stats->rx_mcast_frames += CSR_READ_1(sc, STE_STAT_RX_MCAST); 853 stats->rx_lost_frames += CSR_READ_1(sc, STE_STAT_RX_LOST); 854 /* Tx stats. */ 855 val = (uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO) | 856 ((uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI)) << 16; 857 val &= 0x000FFFFF; 858 stats->tx_bytes += val; 859 stats->tx_frames += CSR_READ_2(sc, STE_STAT_TX_FRAMES); 860 stats->tx_bcast_frames += CSR_READ_1(sc, STE_STAT_TX_BCAST); 861 stats->tx_mcast_frames += CSR_READ_1(sc, STE_STAT_TX_MCAST); 862 stats->tx_carrsense_errs += CSR_READ_1(sc, STE_STAT_CARRIER_ERR); 863 val = CSR_READ_1(sc, STE_STAT_SINGLE_COLLS); 864 stats->tx_single_colls += val; 865 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, val); 866 val = CSR_READ_1(sc, STE_STAT_MULTI_COLLS); 867 stats->tx_multi_colls += val; 868 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, val); 869 val += CSR_READ_1(sc, STE_STAT_LATE_COLLS); 870 stats->tx_late_colls += val; 871 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, val); 872 stats->tx_frames_defered += CSR_READ_1(sc, STE_STAT_TX_DEFER); 873 stats->tx_excess_defers += CSR_READ_1(sc, STE_STAT_TX_EXDEFER); 874 stats->tx_abort += CSR_READ_1(sc, STE_STAT_TX_ABORT); 875 } 876 877 /* 878 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 879 * IDs against our list and return a device name if we find a match. 880 */ 881 static int 882 ste_probe(device_t dev) 883 { 884 const struct ste_type *t; 885 886 t = ste_devs; 887 888 while (t->ste_name != NULL) { 889 if ((pci_get_vendor(dev) == t->ste_vid) && 890 (pci_get_device(dev) == t->ste_did)) { 891 device_set_desc(dev, t->ste_name); 892 return (BUS_PROBE_DEFAULT); 893 } 894 t++; 895 } 896 897 return (ENXIO); 898 } 899 900 /* 901 * Attach the interface. Allocate softc structures, do ifmedia 902 * setup and ethernet/BPF attach. 903 */ 904 static int 905 ste_attach(device_t dev) 906 { 907 struct ste_softc *sc; 908 if_t ifp; 909 uint16_t eaddr[ETHER_ADDR_LEN / 2]; 910 int error = 0, phy, pmc, prefer_iomap, rid; 911 912 sc = device_get_softc(dev); 913 sc->ste_dev = dev; 914 915 /* 916 * Only use one PHY since this chip reports multiple 917 * Note on the DFE-550 the PHY is at 1 on the DFE-580 918 * it is at 0 & 1. It is rev 0x12. 919 */ 920 if (pci_get_vendor(dev) == DL_VENDORID && 921 pci_get_device(dev) == DL_DEVICEID_DL10050 && 922 pci_get_revid(dev) == 0x12 ) 923 sc->ste_flags |= STE_FLAG_ONE_PHY; 924 925 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 926 MTX_DEF); 927 /* 928 * Map control/status registers. 929 */ 930 pci_enable_busmaster(dev); 931 932 /* 933 * Prefer memory space register mapping over IO space but use 934 * IO space for a device that is known to have issues on memory 935 * mapping. 936 */ 937 prefer_iomap = 0; 938 if (pci_get_device(dev) == ST_DEVICEID_ST201_1) 939 prefer_iomap = 1; 940 else 941 resource_int_value(device_get_name(sc->ste_dev), 942 device_get_unit(sc->ste_dev), "prefer_iomap", 943 &prefer_iomap); 944 if (prefer_iomap == 0) { 945 sc->ste_res_id = PCIR_BAR(1); 946 sc->ste_res_type = SYS_RES_MEMORY; 947 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type, 948 &sc->ste_res_id, RF_ACTIVE); 949 } 950 if (prefer_iomap || sc->ste_res == NULL) { 951 sc->ste_res_id = PCIR_BAR(0); 952 sc->ste_res_type = SYS_RES_IOPORT; 953 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type, 954 &sc->ste_res_id, RF_ACTIVE); 955 } 956 if (sc->ste_res == NULL) { 957 device_printf(dev, "couldn't map ports/memory\n"); 958 error = ENXIO; 959 goto fail; 960 } 961 962 /* Allocate interrupt */ 963 rid = 0; 964 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 965 RF_SHAREABLE | RF_ACTIVE); 966 967 if (sc->ste_irq == NULL) { 968 device_printf(dev, "couldn't map interrupt\n"); 969 error = ENXIO; 970 goto fail; 971 } 972 973 callout_init_mtx(&sc->ste_callout, &sc->ste_mtx, 0); 974 975 /* Reset the adapter. */ 976 ste_reset(sc); 977 978 /* 979 * Get station address from the EEPROM. 980 */ 981 if (ste_read_eeprom(sc, eaddr, STE_EEADDR_NODE0, ETHER_ADDR_LEN / 2)) { 982 device_printf(dev, "failed to read station address\n"); 983 error = ENXIO; 984 goto fail; 985 } 986 ste_sysctl_node(sc); 987 988 if ((error = ste_dma_alloc(sc)) != 0) 989 goto fail; 990 991 ifp = sc->ste_ifp = if_alloc(IFT_ETHER); 992 if (ifp == NULL) { 993 device_printf(dev, "can not if_alloc()\n"); 994 error = ENOSPC; 995 goto fail; 996 } 997 998 /* Do MII setup. */ 999 phy = MII_PHY_ANY; 1000 if ((sc->ste_flags & STE_FLAG_ONE_PHY) != 0) 1001 phy = 0; 1002 error = mii_attach(dev, &sc->ste_miibus, ifp, ste_ifmedia_upd, 1003 ste_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 1004 if (error != 0) { 1005 device_printf(dev, "attaching PHYs failed\n"); 1006 goto fail; 1007 } 1008 1009 if_setsoftc(ifp, sc); 1010 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1011 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1012 if_setioctlfn(ifp, ste_ioctl); 1013 if_setstartfn(ifp, ste_start); 1014 if_setinitfn(ifp, ste_init); 1015 if_setsendqlen(ifp, STE_TX_LIST_CNT - 1); 1016 if_setsendqready(ifp); 1017 1018 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1019 1020 /* 1021 * Call MI attach routine. 1022 */ 1023 ether_ifattach(ifp, (uint8_t *)eaddr); 1024 1025 /* 1026 * Tell the upper layer(s) we support long frames. 1027 */ 1028 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 1029 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 1030 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) 1031 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0); 1032 if_setcapenable(ifp, if_getcapabilities(ifp)); 1033 #ifdef DEVICE_POLLING 1034 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 1035 #endif 1036 1037 /* Hook interrupt last to avoid having to lock softc */ 1038 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE, 1039 NULL, ste_intr, sc, &sc->ste_intrhand); 1040 1041 if (error) { 1042 device_printf(dev, "couldn't set up irq\n"); 1043 ether_ifdetach(ifp); 1044 goto fail; 1045 } 1046 1047 fail: 1048 if (error) 1049 ste_detach(dev); 1050 1051 return (error); 1052 } 1053 1054 /* 1055 * Shutdown hardware and free up resources. This can be called any 1056 * time after the mutex has been initialized. It is called in both 1057 * the error case in attach and the normal detach case so it needs 1058 * to be careful about only freeing resources that have actually been 1059 * allocated. 1060 */ 1061 static int 1062 ste_detach(device_t dev) 1063 { 1064 struct ste_softc *sc; 1065 if_t ifp; 1066 1067 sc = device_get_softc(dev); 1068 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1069 ifp = sc->ste_ifp; 1070 1071 #ifdef DEVICE_POLLING 1072 if (if_getcapenable(ifp) & IFCAP_POLLING) 1073 ether_poll_deregister(ifp); 1074 #endif 1075 1076 /* These should only be active if attach succeeded */ 1077 if (device_is_attached(dev)) { 1078 ether_ifdetach(ifp); 1079 STE_LOCK(sc); 1080 ste_stop(sc); 1081 STE_UNLOCK(sc); 1082 callout_drain(&sc->ste_callout); 1083 } 1084 if (sc->ste_miibus) 1085 device_delete_child(dev, sc->ste_miibus); 1086 bus_generic_detach(dev); 1087 1088 if (sc->ste_intrhand) 1089 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1090 if (sc->ste_irq) 1091 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1092 if (sc->ste_res) 1093 bus_release_resource(dev, sc->ste_res_type, sc->ste_res_id, 1094 sc->ste_res); 1095 1096 if (ifp) 1097 if_free(ifp); 1098 1099 ste_dma_free(sc); 1100 mtx_destroy(&sc->ste_mtx); 1101 1102 return (0); 1103 } 1104 1105 struct ste_dmamap_arg { 1106 bus_addr_t ste_busaddr; 1107 }; 1108 1109 static void 1110 ste_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1111 { 1112 struct ste_dmamap_arg *ctx; 1113 1114 if (error != 0) 1115 return; 1116 1117 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1118 1119 ctx = (struct ste_dmamap_arg *)arg; 1120 ctx->ste_busaddr = segs[0].ds_addr; 1121 } 1122 1123 static int 1124 ste_dma_alloc(struct ste_softc *sc) 1125 { 1126 struct ste_chain *txc; 1127 struct ste_chain_onefrag *rxc; 1128 struct ste_dmamap_arg ctx; 1129 int error, i; 1130 1131 /* Create parent DMA tag. */ 1132 error = bus_dma_tag_create( 1133 bus_get_dma_tag(sc->ste_dev), /* parent */ 1134 1, 0, /* alignment, boundary */ 1135 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1136 BUS_SPACE_MAXADDR, /* highaddr */ 1137 NULL, NULL, /* filter, filterarg */ 1138 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1139 0, /* nsegments */ 1140 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1141 0, /* flags */ 1142 NULL, NULL, /* lockfunc, lockarg */ 1143 &sc->ste_cdata.ste_parent_tag); 1144 if (error != 0) { 1145 device_printf(sc->ste_dev, 1146 "could not create parent DMA tag.\n"); 1147 goto fail; 1148 } 1149 1150 /* Create DMA tag for Tx descriptor list. */ 1151 error = bus_dma_tag_create( 1152 sc->ste_cdata.ste_parent_tag, /* parent */ 1153 STE_DESC_ALIGN, 0, /* alignment, boundary */ 1154 BUS_SPACE_MAXADDR, /* lowaddr */ 1155 BUS_SPACE_MAXADDR, /* highaddr */ 1156 NULL, NULL, /* filter, filterarg */ 1157 STE_TX_LIST_SZ, /* maxsize */ 1158 1, /* nsegments */ 1159 STE_TX_LIST_SZ, /* maxsegsize */ 1160 0, /* flags */ 1161 NULL, NULL, /* lockfunc, lockarg */ 1162 &sc->ste_cdata.ste_tx_list_tag); 1163 if (error != 0) { 1164 device_printf(sc->ste_dev, 1165 "could not create Tx list DMA tag.\n"); 1166 goto fail; 1167 } 1168 1169 /* Create DMA tag for Rx descriptor list. */ 1170 error = bus_dma_tag_create( 1171 sc->ste_cdata.ste_parent_tag, /* parent */ 1172 STE_DESC_ALIGN, 0, /* alignment, boundary */ 1173 BUS_SPACE_MAXADDR, /* lowaddr */ 1174 BUS_SPACE_MAXADDR, /* highaddr */ 1175 NULL, NULL, /* filter, filterarg */ 1176 STE_RX_LIST_SZ, /* maxsize */ 1177 1, /* nsegments */ 1178 STE_RX_LIST_SZ, /* maxsegsize */ 1179 0, /* flags */ 1180 NULL, NULL, /* lockfunc, lockarg */ 1181 &sc->ste_cdata.ste_rx_list_tag); 1182 if (error != 0) { 1183 device_printf(sc->ste_dev, 1184 "could not create Rx list DMA tag.\n"); 1185 goto fail; 1186 } 1187 1188 /* Create DMA tag for Tx buffers. */ 1189 error = bus_dma_tag_create( 1190 sc->ste_cdata.ste_parent_tag, /* parent */ 1191 1, 0, /* alignment, boundary */ 1192 BUS_SPACE_MAXADDR, /* lowaddr */ 1193 BUS_SPACE_MAXADDR, /* highaddr */ 1194 NULL, NULL, /* filter, filterarg */ 1195 MCLBYTES * STE_MAXFRAGS, /* maxsize */ 1196 STE_MAXFRAGS, /* nsegments */ 1197 MCLBYTES, /* maxsegsize */ 1198 0, /* flags */ 1199 NULL, NULL, /* lockfunc, lockarg */ 1200 &sc->ste_cdata.ste_tx_tag); 1201 if (error != 0) { 1202 device_printf(sc->ste_dev, "could not create Tx DMA tag.\n"); 1203 goto fail; 1204 } 1205 1206 /* Create DMA tag for Rx buffers. */ 1207 error = bus_dma_tag_create( 1208 sc->ste_cdata.ste_parent_tag, /* parent */ 1209 1, 0, /* alignment, boundary */ 1210 BUS_SPACE_MAXADDR, /* lowaddr */ 1211 BUS_SPACE_MAXADDR, /* highaddr */ 1212 NULL, NULL, /* filter, filterarg */ 1213 MCLBYTES, /* maxsize */ 1214 1, /* nsegments */ 1215 MCLBYTES, /* maxsegsize */ 1216 0, /* flags */ 1217 NULL, NULL, /* lockfunc, lockarg */ 1218 &sc->ste_cdata.ste_rx_tag); 1219 if (error != 0) { 1220 device_printf(sc->ste_dev, "could not create Rx DMA tag.\n"); 1221 goto fail; 1222 } 1223 1224 /* Allocate DMA'able memory and load the DMA map for Tx list. */ 1225 error = bus_dmamem_alloc(sc->ste_cdata.ste_tx_list_tag, 1226 (void **)&sc->ste_ldata.ste_tx_list, 1227 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1228 &sc->ste_cdata.ste_tx_list_map); 1229 if (error != 0) { 1230 device_printf(sc->ste_dev, 1231 "could not allocate DMA'able memory for Tx list.\n"); 1232 goto fail; 1233 } 1234 ctx.ste_busaddr = 0; 1235 error = bus_dmamap_load(sc->ste_cdata.ste_tx_list_tag, 1236 sc->ste_cdata.ste_tx_list_map, sc->ste_ldata.ste_tx_list, 1237 STE_TX_LIST_SZ, ste_dmamap_cb, &ctx, 0); 1238 if (error != 0 || ctx.ste_busaddr == 0) { 1239 device_printf(sc->ste_dev, 1240 "could not load DMA'able memory for Tx list.\n"); 1241 goto fail; 1242 } 1243 sc->ste_ldata.ste_tx_list_paddr = ctx.ste_busaddr; 1244 1245 /* Allocate DMA'able memory and load the DMA map for Rx list. */ 1246 error = bus_dmamem_alloc(sc->ste_cdata.ste_rx_list_tag, 1247 (void **)&sc->ste_ldata.ste_rx_list, 1248 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1249 &sc->ste_cdata.ste_rx_list_map); 1250 if (error != 0) { 1251 device_printf(sc->ste_dev, 1252 "could not allocate DMA'able memory for Rx list.\n"); 1253 goto fail; 1254 } 1255 ctx.ste_busaddr = 0; 1256 error = bus_dmamap_load(sc->ste_cdata.ste_rx_list_tag, 1257 sc->ste_cdata.ste_rx_list_map, sc->ste_ldata.ste_rx_list, 1258 STE_RX_LIST_SZ, ste_dmamap_cb, &ctx, 0); 1259 if (error != 0 || ctx.ste_busaddr == 0) { 1260 device_printf(sc->ste_dev, 1261 "could not load DMA'able memory for Rx list.\n"); 1262 goto fail; 1263 } 1264 sc->ste_ldata.ste_rx_list_paddr = ctx.ste_busaddr; 1265 1266 /* Create DMA maps for Tx buffers. */ 1267 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1268 txc = &sc->ste_cdata.ste_tx_chain[i]; 1269 txc->ste_ptr = NULL; 1270 txc->ste_mbuf = NULL; 1271 txc->ste_next = NULL; 1272 txc->ste_phys = 0; 1273 txc->ste_map = NULL; 1274 error = bus_dmamap_create(sc->ste_cdata.ste_tx_tag, 0, 1275 &txc->ste_map); 1276 if (error != 0) { 1277 device_printf(sc->ste_dev, 1278 "could not create Tx dmamap.\n"); 1279 goto fail; 1280 } 1281 } 1282 /* Create DMA maps for Rx buffers. */ 1283 if ((error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0, 1284 &sc->ste_cdata.ste_rx_sparemap)) != 0) { 1285 device_printf(sc->ste_dev, 1286 "could not create spare Rx dmamap.\n"); 1287 goto fail; 1288 } 1289 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1290 rxc = &sc->ste_cdata.ste_rx_chain[i]; 1291 rxc->ste_ptr = NULL; 1292 rxc->ste_mbuf = NULL; 1293 rxc->ste_next = NULL; 1294 rxc->ste_map = NULL; 1295 error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0, 1296 &rxc->ste_map); 1297 if (error != 0) { 1298 device_printf(sc->ste_dev, 1299 "could not create Rx dmamap.\n"); 1300 goto fail; 1301 } 1302 } 1303 1304 fail: 1305 return (error); 1306 } 1307 1308 static void 1309 ste_dma_free(struct ste_softc *sc) 1310 { 1311 struct ste_chain *txc; 1312 struct ste_chain_onefrag *rxc; 1313 int i; 1314 1315 /* Tx buffers. */ 1316 if (sc->ste_cdata.ste_tx_tag != NULL) { 1317 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1318 txc = &sc->ste_cdata.ste_tx_chain[i]; 1319 if (txc->ste_map != NULL) { 1320 bus_dmamap_destroy(sc->ste_cdata.ste_tx_tag, 1321 txc->ste_map); 1322 txc->ste_map = NULL; 1323 } 1324 } 1325 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_tag); 1326 sc->ste_cdata.ste_tx_tag = NULL; 1327 } 1328 /* Rx buffers. */ 1329 if (sc->ste_cdata.ste_rx_tag != NULL) { 1330 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1331 rxc = &sc->ste_cdata.ste_rx_chain[i]; 1332 if (rxc->ste_map != NULL) { 1333 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag, 1334 rxc->ste_map); 1335 rxc->ste_map = NULL; 1336 } 1337 } 1338 if (sc->ste_cdata.ste_rx_sparemap != NULL) { 1339 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag, 1340 sc->ste_cdata.ste_rx_sparemap); 1341 sc->ste_cdata.ste_rx_sparemap = NULL; 1342 } 1343 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_tag); 1344 sc->ste_cdata.ste_rx_tag = NULL; 1345 } 1346 /* Tx descriptor list. */ 1347 if (sc->ste_cdata.ste_tx_list_tag != NULL) { 1348 if (sc->ste_ldata.ste_tx_list_paddr != 0) 1349 bus_dmamap_unload(sc->ste_cdata.ste_tx_list_tag, 1350 sc->ste_cdata.ste_tx_list_map); 1351 if (sc->ste_ldata.ste_tx_list != NULL) 1352 bus_dmamem_free(sc->ste_cdata.ste_tx_list_tag, 1353 sc->ste_ldata.ste_tx_list, 1354 sc->ste_cdata.ste_tx_list_map); 1355 sc->ste_ldata.ste_tx_list = NULL; 1356 sc->ste_ldata.ste_tx_list_paddr = 0; 1357 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_list_tag); 1358 sc->ste_cdata.ste_tx_list_tag = NULL; 1359 } 1360 /* Rx descriptor list. */ 1361 if (sc->ste_cdata.ste_rx_list_tag != NULL) { 1362 if (sc->ste_ldata.ste_rx_list_paddr != 0) 1363 bus_dmamap_unload(sc->ste_cdata.ste_rx_list_tag, 1364 sc->ste_cdata.ste_rx_list_map); 1365 if (sc->ste_ldata.ste_rx_list != NULL) 1366 bus_dmamem_free(sc->ste_cdata.ste_rx_list_tag, 1367 sc->ste_ldata.ste_rx_list, 1368 sc->ste_cdata.ste_rx_list_map); 1369 sc->ste_ldata.ste_rx_list = NULL; 1370 sc->ste_ldata.ste_rx_list_paddr = 0; 1371 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_list_tag); 1372 sc->ste_cdata.ste_rx_list_tag = NULL; 1373 } 1374 if (sc->ste_cdata.ste_parent_tag != NULL) { 1375 bus_dma_tag_destroy(sc->ste_cdata.ste_parent_tag); 1376 sc->ste_cdata.ste_parent_tag = NULL; 1377 } 1378 } 1379 1380 static int 1381 ste_newbuf(struct ste_softc *sc, struct ste_chain_onefrag *rxc) 1382 { 1383 struct mbuf *m; 1384 bus_dma_segment_t segs[1]; 1385 bus_dmamap_t map; 1386 int error, nsegs; 1387 1388 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1389 if (m == NULL) 1390 return (ENOBUFS); 1391 m->m_len = m->m_pkthdr.len = MCLBYTES; 1392 m_adj(m, ETHER_ALIGN); 1393 1394 if ((error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_rx_tag, 1395 sc->ste_cdata.ste_rx_sparemap, m, segs, &nsegs, 0)) != 0) { 1396 m_freem(m); 1397 return (error); 1398 } 1399 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1400 1401 if (rxc->ste_mbuf != NULL) { 1402 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map, 1403 BUS_DMASYNC_POSTREAD); 1404 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, rxc->ste_map); 1405 } 1406 map = rxc->ste_map; 1407 rxc->ste_map = sc->ste_cdata.ste_rx_sparemap; 1408 sc->ste_cdata.ste_rx_sparemap = map; 1409 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map, 1410 BUS_DMASYNC_PREREAD); 1411 rxc->ste_mbuf = m; 1412 rxc->ste_ptr->ste_status = 0; 1413 rxc->ste_ptr->ste_frag.ste_addr = htole32(segs[0].ds_addr); 1414 rxc->ste_ptr->ste_frag.ste_len = htole32(segs[0].ds_len | 1415 STE_FRAG_LAST); 1416 return (0); 1417 } 1418 1419 static int 1420 ste_init_rx_list(struct ste_softc *sc) 1421 { 1422 struct ste_chain_data *cd; 1423 struct ste_list_data *ld; 1424 int error, i; 1425 1426 sc->ste_int_rx_act = 0; 1427 cd = &sc->ste_cdata; 1428 ld = &sc->ste_ldata; 1429 bzero(ld->ste_rx_list, STE_RX_LIST_SZ); 1430 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1431 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1432 error = ste_newbuf(sc, &cd->ste_rx_chain[i]); 1433 if (error != 0) 1434 return (error); 1435 if (i == (STE_RX_LIST_CNT - 1)) { 1436 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[0]; 1437 ld->ste_rx_list[i].ste_next = 1438 htole32(ld->ste_rx_list_paddr + 1439 (sizeof(struct ste_desc_onefrag) * 0)); 1440 } else { 1441 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[i + 1]; 1442 ld->ste_rx_list[i].ste_next = 1443 htole32(ld->ste_rx_list_paddr + 1444 (sizeof(struct ste_desc_onefrag) * (i + 1))); 1445 } 1446 } 1447 1448 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1449 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 1450 sc->ste_cdata.ste_rx_list_map, 1451 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1452 1453 return (0); 1454 } 1455 1456 static void 1457 ste_init_tx_list(struct ste_softc *sc) 1458 { 1459 struct ste_chain_data *cd; 1460 struct ste_list_data *ld; 1461 int i; 1462 1463 cd = &sc->ste_cdata; 1464 ld = &sc->ste_ldata; 1465 bzero(ld->ste_tx_list, STE_TX_LIST_SZ); 1466 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1467 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1468 cd->ste_tx_chain[i].ste_mbuf = NULL; 1469 if (i == (STE_TX_LIST_CNT - 1)) { 1470 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[0]; 1471 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO( 1472 ld->ste_tx_list_paddr + 1473 (sizeof(struct ste_desc) * 0))); 1474 } else { 1475 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[i + 1]; 1476 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO( 1477 ld->ste_tx_list_paddr + 1478 (sizeof(struct ste_desc) * (i + 1)))); 1479 } 1480 } 1481 1482 cd->ste_last_tx = NULL; 1483 cd->ste_tx_prod = 0; 1484 cd->ste_tx_cons = 0; 1485 cd->ste_tx_cnt = 0; 1486 1487 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1488 sc->ste_cdata.ste_tx_list_map, 1489 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1490 } 1491 1492 static void 1493 ste_init(void *xsc) 1494 { 1495 struct ste_softc *sc; 1496 1497 sc = xsc; 1498 STE_LOCK(sc); 1499 ste_init_locked(sc); 1500 STE_UNLOCK(sc); 1501 } 1502 1503 static void 1504 ste_init_locked(struct ste_softc *sc) 1505 { 1506 if_t ifp; 1507 struct mii_data *mii; 1508 uint8_t val; 1509 int i; 1510 1511 STE_LOCK_ASSERT(sc); 1512 ifp = sc->ste_ifp; 1513 mii = device_get_softc(sc->ste_miibus); 1514 1515 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1516 return; 1517 1518 ste_stop(sc); 1519 /* Reset the chip to a known state. */ 1520 ste_reset(sc); 1521 1522 /* Init our MAC address */ 1523 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1524 CSR_WRITE_2(sc, STE_PAR0 + i, 1525 ((if_getlladdr(sc->ste_ifp)[i] & 0xff) | 1526 if_getlladdr(sc->ste_ifp)[i + 1] << 8)); 1527 } 1528 1529 /* Init RX list */ 1530 if (ste_init_rx_list(sc) != 0) { 1531 device_printf(sc->ste_dev, 1532 "initialization failed: no memory for RX buffers\n"); 1533 ste_stop(sc); 1534 return; 1535 } 1536 1537 /* Set RX polling interval */ 1538 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); 1539 1540 /* Init TX descriptors */ 1541 ste_init_tx_list(sc); 1542 1543 /* Clear and disable WOL. */ 1544 val = CSR_READ_1(sc, STE_WAKE_EVENT); 1545 val &= ~(STE_WAKEEVENT_WAKEPKT_ENB | STE_WAKEEVENT_MAGICPKT_ENB | 1546 STE_WAKEEVENT_LINKEVT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB); 1547 CSR_WRITE_1(sc, STE_WAKE_EVENT, val); 1548 1549 /* Set the TX freethresh value */ 1550 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1551 1552 /* Set the TX start threshold for best performance. */ 1553 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1554 1555 /* Set the TX reclaim threshold. */ 1556 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1557 1558 /* Accept VLAN length packets */ 1559 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1560 1561 /* Set up the RX filter. */ 1562 ste_rxfilter(sc); 1563 1564 /* Load the address of the RX list. */ 1565 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1566 ste_wait(sc); 1567 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1568 STE_ADDR_LO(sc->ste_ldata.ste_rx_list_paddr)); 1569 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1570 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1571 1572 /* Set TX polling interval(defer until we TX first packet). */ 1573 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1574 1575 /* Load address of the TX list */ 1576 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1577 ste_wait(sc); 1578 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1579 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1580 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1581 ste_wait(sc); 1582 /* Select 3.2us timer. */ 1583 STE_CLRBIT4(sc, STE_DMACTL, STE_DMACTL_COUNTDOWN_SPEED | 1584 STE_DMACTL_COUNTDOWN_MODE); 1585 1586 /* Enable receiver and transmitter */ 1587 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1588 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1589 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1590 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1591 1592 /* Enable stats counters. */ 1593 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1594 /* Clear stats counters. */ 1595 ste_stats_clear(sc); 1596 1597 CSR_WRITE_2(sc, STE_COUNTDOWN, 0); 1598 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1599 #ifdef DEVICE_POLLING 1600 /* Disable interrupts if we are polling. */ 1601 if (if_getcapenable(ifp) & IFCAP_POLLING) 1602 CSR_WRITE_2(sc, STE_IMR, 0); 1603 else 1604 #endif 1605 /* Enable interrupts. */ 1606 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1607 1608 sc->ste_flags &= ~STE_FLAG_LINK; 1609 /* Switch to the current media. */ 1610 mii_mediachg(mii); 1611 1612 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 1613 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1614 1615 callout_reset(&sc->ste_callout, hz, ste_tick, sc); 1616 } 1617 1618 static void 1619 ste_stop(struct ste_softc *sc) 1620 { 1621 if_t ifp; 1622 struct ste_chain_onefrag *cur_rx; 1623 struct ste_chain *cur_tx; 1624 uint32_t val; 1625 int i; 1626 1627 STE_LOCK_ASSERT(sc); 1628 ifp = sc->ste_ifp; 1629 1630 callout_stop(&sc->ste_callout); 1631 sc->ste_timer = 0; 1632 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)); 1633 1634 CSR_WRITE_2(sc, STE_IMR, 0); 1635 CSR_WRITE_2(sc, STE_COUNTDOWN, 0); 1636 /* Stop pending DMA. */ 1637 val = CSR_READ_4(sc, STE_DMACTL); 1638 val |= STE_DMACTL_TXDMA_STALL | STE_DMACTL_RXDMA_STALL; 1639 CSR_WRITE_4(sc, STE_DMACTL, val); 1640 ste_wait(sc); 1641 /* Disable auto-polling. */ 1642 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 0); 1643 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1644 /* Nullify DMA address to stop any further DMA. */ 1645 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 0); 1646 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1647 /* Stop TX/RX MAC. */ 1648 val = CSR_READ_2(sc, STE_MACCTL1); 1649 val |= STE_MACCTL1_TX_DISABLE | STE_MACCTL1_RX_DISABLE | 1650 STE_MACCTL1_STATS_DISABLE; 1651 CSR_WRITE_2(sc, STE_MACCTL1, val); 1652 for (i = 0; i < STE_TIMEOUT; i++) { 1653 DELAY(10); 1654 if ((CSR_READ_2(sc, STE_MACCTL1) & (STE_MACCTL1_TX_DISABLE | 1655 STE_MACCTL1_RX_DISABLE | STE_MACCTL1_STATS_DISABLE)) == 0) 1656 break; 1657 } 1658 if (i == STE_TIMEOUT) 1659 device_printf(sc->ste_dev, "Stopping MAC timed out\n"); 1660 /* Acknowledge any pending interrupts. */ 1661 CSR_READ_2(sc, STE_ISR_ACK); 1662 ste_stats_update(sc); 1663 1664 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1665 cur_rx = &sc->ste_cdata.ste_rx_chain[i]; 1666 if (cur_rx->ste_mbuf != NULL) { 1667 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, 1668 cur_rx->ste_map, BUS_DMASYNC_POSTREAD); 1669 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, 1670 cur_rx->ste_map); 1671 m_freem(cur_rx->ste_mbuf); 1672 cur_rx->ste_mbuf = NULL; 1673 } 1674 } 1675 1676 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1677 cur_tx = &sc->ste_cdata.ste_tx_chain[i]; 1678 if (cur_tx->ste_mbuf != NULL) { 1679 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, 1680 cur_tx->ste_map, BUS_DMASYNC_POSTWRITE); 1681 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, 1682 cur_tx->ste_map); 1683 m_freem(cur_tx->ste_mbuf); 1684 cur_tx->ste_mbuf = NULL; 1685 } 1686 } 1687 } 1688 1689 static void 1690 ste_reset(struct ste_softc *sc) 1691 { 1692 uint32_t ctl; 1693 int i; 1694 1695 ctl = CSR_READ_4(sc, STE_ASICCTL); 1696 ctl |= STE_ASICCTL_GLOBAL_RESET | STE_ASICCTL_RX_RESET | 1697 STE_ASICCTL_TX_RESET | STE_ASICCTL_DMA_RESET | 1698 STE_ASICCTL_FIFO_RESET | STE_ASICCTL_NETWORK_RESET | 1699 STE_ASICCTL_AUTOINIT_RESET |STE_ASICCTL_HOST_RESET | 1700 STE_ASICCTL_EXTRESET_RESET; 1701 CSR_WRITE_4(sc, STE_ASICCTL, ctl); 1702 CSR_READ_4(sc, STE_ASICCTL); 1703 /* 1704 * Due to the need of accessing EEPROM controller can take 1705 * up to 1ms to complete the global reset. 1706 */ 1707 DELAY(1000); 1708 1709 for (i = 0; i < STE_TIMEOUT; i++) { 1710 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1711 break; 1712 DELAY(10); 1713 } 1714 1715 if (i == STE_TIMEOUT) 1716 device_printf(sc->ste_dev, "global reset never completed\n"); 1717 } 1718 1719 static void 1720 ste_restart_tx(struct ste_softc *sc) 1721 { 1722 uint16_t mac; 1723 int i; 1724 1725 for (i = 0; i < STE_TIMEOUT; i++) { 1726 mac = CSR_READ_2(sc, STE_MACCTL1); 1727 mac |= STE_MACCTL1_TX_ENABLE; 1728 CSR_WRITE_2(sc, STE_MACCTL1, mac); 1729 mac = CSR_READ_2(sc, STE_MACCTL1); 1730 if ((mac & STE_MACCTL1_TX_ENABLED) != 0) 1731 break; 1732 DELAY(10); 1733 } 1734 1735 if (i == STE_TIMEOUT) 1736 device_printf(sc->ste_dev, "starting Tx failed"); 1737 } 1738 1739 static int 1740 ste_ioctl(if_t ifp, u_long command, caddr_t data) 1741 { 1742 struct ste_softc *sc; 1743 struct ifreq *ifr; 1744 struct mii_data *mii; 1745 int error = 0, mask; 1746 1747 sc = if_getsoftc(ifp); 1748 ifr = (struct ifreq *)data; 1749 1750 switch (command) { 1751 case SIOCSIFFLAGS: 1752 STE_LOCK(sc); 1753 if ((if_getflags(ifp) & IFF_UP) != 0) { 1754 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 1755 ((if_getflags(ifp) ^ sc->ste_if_flags) & 1756 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1757 ste_rxfilter(sc); 1758 else 1759 ste_init_locked(sc); 1760 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1761 ste_stop(sc); 1762 sc->ste_if_flags = if_getflags(ifp); 1763 STE_UNLOCK(sc); 1764 break; 1765 case SIOCADDMULTI: 1766 case SIOCDELMULTI: 1767 STE_LOCK(sc); 1768 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1769 ste_rxfilter(sc); 1770 STE_UNLOCK(sc); 1771 break; 1772 case SIOCGIFMEDIA: 1773 case SIOCSIFMEDIA: 1774 mii = device_get_softc(sc->ste_miibus); 1775 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1776 break; 1777 case SIOCSIFCAP: 1778 STE_LOCK(sc); 1779 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1780 #ifdef DEVICE_POLLING 1781 if ((mask & IFCAP_POLLING) != 0 && 1782 (IFCAP_POLLING & if_getcapabilities(ifp)) != 0) { 1783 if_togglecapenable(ifp, IFCAP_POLLING); 1784 if ((IFCAP_POLLING & if_getcapenable(ifp)) != 0) { 1785 error = ether_poll_register(ste_poll, ifp); 1786 if (error != 0) { 1787 STE_UNLOCK(sc); 1788 break; 1789 } 1790 /* Disable interrupts. */ 1791 CSR_WRITE_2(sc, STE_IMR, 0); 1792 } else { 1793 error = ether_poll_deregister(ifp); 1794 /* Enable interrupts. */ 1795 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1796 } 1797 } 1798 #endif /* DEVICE_POLLING */ 1799 if ((mask & IFCAP_WOL_MAGIC) != 0 && 1800 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 1801 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 1802 STE_UNLOCK(sc); 1803 break; 1804 default: 1805 error = ether_ioctl(ifp, command, data); 1806 break; 1807 } 1808 1809 return (error); 1810 } 1811 1812 static int 1813 ste_encap(struct ste_softc *sc, struct mbuf **m_head, struct ste_chain *txc) 1814 { 1815 struct ste_frag *frag; 1816 struct mbuf *m; 1817 struct ste_desc *desc; 1818 bus_dma_segment_t txsegs[STE_MAXFRAGS]; 1819 int error, i, nsegs; 1820 1821 STE_LOCK_ASSERT(sc); 1822 M_ASSERTPKTHDR((*m_head)); 1823 1824 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag, 1825 txc->ste_map, *m_head, txsegs, &nsegs, 0); 1826 if (error == EFBIG) { 1827 m = m_collapse(*m_head, M_NOWAIT, STE_MAXFRAGS); 1828 if (m == NULL) { 1829 m_freem(*m_head); 1830 *m_head = NULL; 1831 return (ENOMEM); 1832 } 1833 *m_head = m; 1834 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag, 1835 txc->ste_map, *m_head, txsegs, &nsegs, 0); 1836 if (error != 0) { 1837 m_freem(*m_head); 1838 *m_head = NULL; 1839 return (error); 1840 } 1841 } else if (error != 0) 1842 return (error); 1843 if (nsegs == 0) { 1844 m_freem(*m_head); 1845 *m_head = NULL; 1846 return (EIO); 1847 } 1848 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, txc->ste_map, 1849 BUS_DMASYNC_PREWRITE); 1850 1851 desc = txc->ste_ptr; 1852 for (i = 0; i < nsegs; i++) { 1853 frag = &desc->ste_frags[i]; 1854 frag->ste_addr = htole32(STE_ADDR_LO(txsegs[i].ds_addr)); 1855 frag->ste_len = htole32(txsegs[i].ds_len); 1856 } 1857 desc->ste_frags[i - 1].ste_len |= htole32(STE_FRAG_LAST); 1858 /* 1859 * Because we use Tx polling we can't chain multiple 1860 * Tx descriptors here. Otherwise we race with controller. 1861 */ 1862 desc->ste_next = 0; 1863 if ((sc->ste_cdata.ste_tx_prod % STE_TX_INTR_FRAMES) == 0) 1864 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS | 1865 STE_TXCTL_DMAINTR); 1866 else 1867 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS); 1868 txc->ste_mbuf = *m_head; 1869 STE_INC(sc->ste_cdata.ste_tx_prod, STE_TX_LIST_CNT); 1870 sc->ste_cdata.ste_tx_cnt++; 1871 1872 return (0); 1873 } 1874 1875 static void 1876 ste_start(if_t ifp) 1877 { 1878 struct ste_softc *sc; 1879 1880 sc = if_getsoftc(ifp); 1881 STE_LOCK(sc); 1882 ste_start_locked(ifp); 1883 STE_UNLOCK(sc); 1884 } 1885 1886 static void 1887 ste_start_locked(if_t ifp) 1888 { 1889 struct ste_softc *sc; 1890 struct ste_chain *cur_tx; 1891 struct mbuf *m_head = NULL; 1892 int enq; 1893 1894 sc = if_getsoftc(ifp); 1895 STE_LOCK_ASSERT(sc); 1896 1897 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1898 IFF_DRV_RUNNING || (sc->ste_flags & STE_FLAG_LINK) == 0) 1899 return; 1900 1901 for (enq = 0; !if_sendq_empty(ifp);) { 1902 if (sc->ste_cdata.ste_tx_cnt == STE_TX_LIST_CNT - 1) { 1903 /* 1904 * Controller may have cached copy of the last used 1905 * next ptr so we have to reserve one TFD to avoid 1906 * TFD overruns. 1907 */ 1908 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1909 break; 1910 } 1911 m_head = if_dequeue(ifp); 1912 if (m_head == NULL) 1913 break; 1914 cur_tx = &sc->ste_cdata.ste_tx_chain[sc->ste_cdata.ste_tx_prod]; 1915 if (ste_encap(sc, &m_head, cur_tx) != 0) { 1916 if (m_head == NULL) 1917 break; 1918 if_sendq_prepend(ifp, m_head); 1919 break; 1920 } 1921 if (sc->ste_cdata.ste_last_tx == NULL) { 1922 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1923 sc->ste_cdata.ste_tx_list_map, 1924 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1925 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1926 ste_wait(sc); 1927 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1928 STE_ADDR_LO(sc->ste_ldata.ste_tx_list_paddr)); 1929 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1930 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1931 ste_wait(sc); 1932 } else { 1933 sc->ste_cdata.ste_last_tx->ste_ptr->ste_next = 1934 sc->ste_cdata.ste_last_tx->ste_phys; 1935 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1936 sc->ste_cdata.ste_tx_list_map, 1937 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1938 } 1939 sc->ste_cdata.ste_last_tx = cur_tx; 1940 1941 enq++; 1942 /* 1943 * If there's a BPF listener, bounce a copy of this frame 1944 * to him. 1945 */ 1946 BPF_MTAP(ifp, m_head); 1947 } 1948 1949 if (enq > 0) 1950 sc->ste_timer = STE_TX_TIMEOUT; 1951 } 1952 1953 static void 1954 ste_watchdog(struct ste_softc *sc) 1955 { 1956 if_t ifp; 1957 1958 ifp = sc->ste_ifp; 1959 STE_LOCK_ASSERT(sc); 1960 1961 if (sc->ste_timer == 0 || --sc->ste_timer) 1962 return; 1963 1964 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1965 if_printf(ifp, "watchdog timeout\n"); 1966 1967 ste_txeof(sc); 1968 ste_txeoc(sc); 1969 ste_rxeof(sc, -1); 1970 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1971 ste_init_locked(sc); 1972 1973 if (!if_sendq_empty(ifp)) 1974 ste_start_locked(ifp); 1975 } 1976 1977 static int 1978 ste_shutdown(device_t dev) 1979 { 1980 1981 return (ste_suspend(dev)); 1982 } 1983 1984 static int 1985 ste_suspend(device_t dev) 1986 { 1987 struct ste_softc *sc; 1988 1989 sc = device_get_softc(dev); 1990 1991 STE_LOCK(sc); 1992 ste_stop(sc); 1993 ste_setwol(sc); 1994 STE_UNLOCK(sc); 1995 1996 return (0); 1997 } 1998 1999 static int 2000 ste_resume(device_t dev) 2001 { 2002 struct ste_softc *sc; 2003 if_t ifp; 2004 int pmc; 2005 uint16_t pmstat; 2006 2007 sc = device_get_softc(dev); 2008 STE_LOCK(sc); 2009 if (pci_find_cap(sc->ste_dev, PCIY_PMG, &pmc) == 0) { 2010 /* Disable PME and clear PME status. */ 2011 pmstat = pci_read_config(sc->ste_dev, 2012 pmc + PCIR_POWER_STATUS, 2); 2013 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2014 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2015 pci_write_config(sc->ste_dev, 2016 pmc + PCIR_POWER_STATUS, pmstat, 2); 2017 } 2018 } 2019 ifp = sc->ste_ifp; 2020 if ((if_getflags(ifp) & IFF_UP) != 0) { 2021 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2022 ste_init_locked(sc); 2023 } 2024 STE_UNLOCK(sc); 2025 2026 return (0); 2027 } 2028 2029 #define STE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2030 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2031 #define STE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 2032 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 2033 2034 static void 2035 ste_sysctl_node(struct ste_softc *sc) 2036 { 2037 struct sysctl_ctx_list *ctx; 2038 struct sysctl_oid_list *child, *parent; 2039 struct sysctl_oid *tree; 2040 struct ste_hw_stats *stats; 2041 2042 stats = &sc->ste_stats; 2043 ctx = device_get_sysctl_ctx(sc->ste_dev); 2044 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ste_dev)); 2045 2046 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "int_rx_mod", 2047 CTLFLAG_RW, &sc->ste_int_rx_mod, 0, "ste RX interrupt moderation"); 2048 /* Pull in device tunables. */ 2049 sc->ste_int_rx_mod = STE_IM_RX_TIMER_DEFAULT; 2050 resource_int_value(device_get_name(sc->ste_dev), 2051 device_get_unit(sc->ste_dev), "int_rx_mod", &sc->ste_int_rx_mod); 2052 2053 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 2054 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "STE statistics"); 2055 parent = SYSCTL_CHILDREN(tree); 2056 2057 /* Rx statistics. */ 2058 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 2059 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 2060 child = SYSCTL_CHILDREN(tree); 2061 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 2062 &stats->rx_bytes, "Good octets"); 2063 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 2064 &stats->rx_frames, "Good frames"); 2065 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 2066 &stats->rx_bcast_frames, "Good broadcast frames"); 2067 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 2068 &stats->rx_mcast_frames, "Good multicast frames"); 2069 STE_SYSCTL_STAT_ADD32(ctx, child, "lost_frames", 2070 &stats->rx_lost_frames, "Lost frames"); 2071 2072 /* Tx statistics. */ 2073 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 2074 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 2075 child = SYSCTL_CHILDREN(tree); 2076 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 2077 &stats->tx_bytes, "Good octets"); 2078 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 2079 &stats->tx_frames, "Good frames"); 2080 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 2081 &stats->tx_bcast_frames, "Good broadcast frames"); 2082 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 2083 &stats->tx_mcast_frames, "Good multicast frames"); 2084 STE_SYSCTL_STAT_ADD32(ctx, child, "carrier_errs", 2085 &stats->tx_carrsense_errs, "Carrier sense errors"); 2086 STE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 2087 &stats->tx_single_colls, "Single collisions"); 2088 STE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 2089 &stats->tx_multi_colls, "Multiple collisions"); 2090 STE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 2091 &stats->tx_late_colls, "Late collisions"); 2092 STE_SYSCTL_STAT_ADD32(ctx, child, "defers", 2093 &stats->tx_frames_defered, "Frames with deferrals"); 2094 STE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 2095 &stats->tx_excess_defers, "Frames with excessive derferrals"); 2096 STE_SYSCTL_STAT_ADD32(ctx, child, "abort", 2097 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 2098 } 2099 2100 #undef STE_SYSCTL_STAT_ADD32 2101 #undef STE_SYSCTL_STAT_ADD64 2102 2103 static void 2104 ste_setwol(struct ste_softc *sc) 2105 { 2106 if_t ifp; 2107 uint16_t pmstat; 2108 uint8_t val; 2109 int pmc; 2110 2111 STE_LOCK_ASSERT(sc); 2112 2113 if (pci_find_cap(sc->ste_dev, PCIY_PMG, &pmc) != 0) { 2114 /* Disable WOL. */ 2115 CSR_READ_1(sc, STE_WAKE_EVENT); 2116 CSR_WRITE_1(sc, STE_WAKE_EVENT, 0); 2117 return; 2118 } 2119 2120 ifp = sc->ste_ifp; 2121 val = CSR_READ_1(sc, STE_WAKE_EVENT); 2122 val &= ~(STE_WAKEEVENT_WAKEPKT_ENB | STE_WAKEEVENT_MAGICPKT_ENB | 2123 STE_WAKEEVENT_LINKEVT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB); 2124 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2125 val |= STE_WAKEEVENT_MAGICPKT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB; 2126 CSR_WRITE_1(sc, STE_WAKE_EVENT, val); 2127 /* Request PME. */ 2128 pmstat = pci_read_config(sc->ste_dev, pmc + PCIR_POWER_STATUS, 2); 2129 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2130 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2131 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2132 pci_write_config(sc->ste_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 2133 } 2134