1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012-2016 Ruslan Bukin <br@bsdpad.com> 5 * Copyright (c) 2023-2024 Florian Walpen <dev@submerge.ch> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #define PCI_VENDOR_XILINX 0x10ee 31 #define PCI_DEVICE_XILINX_HDSP 0x3fc5 /* HDSP 9652 */ 32 #define PCI_REVISION_9632 0x9b 33 #define PCI_REVISION_9652 0x6c 34 35 #define HDSP_9632 0 36 #define HDSP_9652 1 37 38 /* Hardware mixer */ 39 #define HDSP_OUT_ENABLE_BASE 128 40 #define HDSP_IN_ENABLE_BASE 384 41 #define HDSP_MIXER_BASE 4096 42 #define HDSP_MAX_GAIN 32768 43 #define HDSP_MIN_GAIN 0 44 #define HDSP_MIX_SLOTS_9632 16 45 #define HDSP_MIX_SLOTS_9652 26 46 #define HDSP_CONTROL2_9652_MIXER (1 << 11) 47 48 /* Buffer */ 49 #define HDSP_PAGE_ADDR_BUF_OUT 32 50 #define HDSP_PAGE_ADDR_BUF_IN 36 51 #define HDSP_BUF_POSITION_MASK 0x000FFC0 52 53 /* Frequency */ 54 #define HDSP_FREQ_0 (1 << 6) 55 #define HDSP_FREQ_1 (1 << 7) 56 #define HDSP_FREQ_DOUBLE (1 << 8) 57 #define HDSP_FREQ_QUAD (1 << 31) 58 59 #define HDSP_FREQ_32000 HDSP_FREQ_0 60 #define HDSP_FREQ_44100 HDSP_FREQ_1 61 #define HDSP_FREQ_48000 (HDSP_FREQ_0 | HDSP_FREQ_1) 62 #define HDSP_FREQ_MASK (HDSP_FREQ_0 | HDSP_FREQ_1 | \ 63 HDSP_FREQ_DOUBLE | HDSP_FREQ_QUAD) 64 #define HDSP_FREQ_MASK_DEFAULT HDSP_FREQ_48000 65 #define HDSP_FREQ_REG 0 66 #define HDSP_FREQ_9632 104857600000000ULL 67 #define hdsp_freq_multiplier(s) (((s) > 96000) ? 4 : \ 68 (((s) > 48000) ? 2 : 1)) 69 #define hdsp_freq_single(s) ((s) / hdsp_freq_multiplier(s)) 70 #define hdsp_freq_reg_value(s) (HDSP_FREQ_9632 / hdsp_freq_single(s)) 71 72 #define HDSP_SPEED_DEFAULT 48000 73 74 /* Latency */ 75 #define HDSP_LAT_0 (1 << 1) 76 #define HDSP_LAT_1 (1 << 2) 77 #define HDSP_LAT_2 (1 << 3) 78 #define HDSP_LAT_MASK (HDSP_LAT_0 | HDSP_LAT_1 | HDSP_LAT_2) 79 #define HDSP_LAT_BYTES_MAX (4096 * 4) 80 #define HDSP_LAT_BYTES_MIN (32 * 4) 81 #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LAT_MASK) 82 83 /* Gain */ 84 #define HDSP_ADGain0 (1 << 25) 85 #define HDSP_ADGain1 (1 << 26) 86 #define HDSP_DAGain0 (1 << 27) 87 #define HDSP_DAGain1 (1 << 28) 88 #define HDSP_PhoneGain0 (1 << 29) 89 #define HDSP_PhoneGain1 (1 << 30) 90 91 #define HDSP_ADGainMask (HDSP_ADGain0 | HDSP_ADGain1) 92 #define HDSP_ADGainMinus10dBV (HDSP_ADGainMask) 93 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0) 94 #define HDSP_ADGainLowGain 0 95 96 #define HDSP_DAGainMask (HDSP_DAGain0 | HDSP_DAGain1) 97 #define HDSP_DAGainHighGain (HDSP_DAGainMask) 98 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0) 99 #define HDSP_DAGainMinus10dBV 0 100 101 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1) 102 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask 103 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0) 104 #define HDSP_PhoneGainMinus12dB 0 105 106 /* Settings */ 107 #define HDSP_RESET_POINTER 0 108 #define HDSP_CONTROL_REG 64 109 #define HDSP_CONTROL2_REG 256 110 #define HDSP_STATUS_REG 0 111 #define HDSP_STATUS2_REG 192 112 113 #define HDSP_ENABLE (1 << 0) 114 #define HDSP_CONTROL_SPDIF_COAX (1 << 14) 115 #define HDSP_CONTROL_LINE_OUT (1 << 24) 116 117 /* Interrupts */ 118 #define HDSP_AUDIO_IRQ_PENDING (1 << 0) 119 #define HDSP_AUDIO_INT_ENABLE (1 << 5) 120 #define HDSP_INTERRUPT_ACK 96 121 122 /* Channels */ 123 #define HDSP_MAX_SLOTS 64 /* Mono channels */ 124 #define HDSP_MAX_CHANS (HDSP_MAX_SLOTS / 2) /* Stereo pairs */ 125 126 #define HDSP_CHANBUF_SAMPLES (16 * 1024) 127 #define HDSP_CHANBUF_SIZE (4 * HDSP_CHANBUF_SAMPLES) 128 #define HDSP_DMASEGSIZE (HDSP_CHANBUF_SIZE * HDSP_MAX_SLOTS) 129 130 #define HDSP_CHAN_9632_ADAT (1 << 0) 131 #define HDSP_CHAN_9632_SPDIF (1 << 1) 132 #define HDSP_CHAN_9632_LINE (1 << 2) 133 #define HDSP_CHAN_9632_EXT (1 << 3) /* Extension boards */ 134 #define HDSP_CHAN_9632_ALL (HDSP_CHAN_9632_ADAT | \ 135 HDSP_CHAN_9632_SPDIF | \ 136 HDSP_CHAN_9632_LINE | \ 137 HDSP_CHAN_9632_EXT) 138 139 #define HDSP_CHAN_9652_ADAT1 (1 << 5) 140 #define HDSP_CHAN_9652_ADAT2 (1 << 6) 141 #define HDSP_CHAN_9652_ADAT3 (1 << 7) 142 #define HDSP_CHAN_9652_ADAT_ALL (HDSP_CHAN_9652_ADAT1 | \ 143 HDSP_CHAN_9652_ADAT2 | \ 144 HDSP_CHAN_9652_ADAT3) 145 #define HDSP_CHAN_9652_SPDIF (1 << 8) 146 #define HDSP_CHAN_9652_ALL (HDSP_CHAN_9652_ADAT_ALL | \ 147 HDSP_CHAN_9652_SPDIF) 148 149 struct hdsp_channel { 150 uint32_t ports; 151 char *descr; 152 }; 153 154 enum hdsp_clock_type { 155 HDSP_CLOCK_INTERNAL, 156 HDSP_CLOCK_ADAT1, 157 HDSP_CLOCK_ADAT2, 158 HDSP_CLOCK_ADAT3, 159 HDSP_CLOCK_SPDIF, 160 HDSP_CLOCK_WORD, 161 HDSP_CLOCK_ADAT_SYNC 162 }; 163 164 /* Preferred clock source. */ 165 #define HDSP_CONTROL_MASTER (1 << 4) 166 #define HDSP_CONTROL_CLOCK_MASK (HDSP_CONTROL_MASTER | (1 << 13) | \ 167 (1 << 16) | (1 << 17)) 168 #define HDSP_CONTROL_CLOCK(n) (((n & 0x04) << 11) | ((n & 0x03) << 16)) 169 170 /* Autosync selected clock source. */ 171 #define HDSP_STATUS2_CLOCK(n) ((n & 0x07) << 8) 172 #define HDSP_STATUS2_CLOCK_MASK HDSP_STATUS2_CLOCK(0x07); 173 174 struct hdsp_clock_source { 175 char *name; 176 enum hdsp_clock_type type; 177 }; 178 179 static MALLOC_DEFINE(M_HDSP, "hdsp", "hdsp audio"); 180 181 /* Channel registers */ 182 struct sc_chinfo { 183 struct snd_dbuf *buffer; 184 struct pcm_channel *channel; 185 struct sc_pcminfo *parent; 186 187 /* Channel information */ 188 struct pcmchan_caps *caps; 189 uint32_t cap_fmts[4]; 190 uint32_t dir; 191 uint32_t format; 192 uint32_t ports; 193 uint32_t lvol; 194 uint32_t rvol; 195 196 /* Buffer */ 197 uint32_t *data; 198 uint32_t size; 199 uint32_t position; 200 201 /* Flags */ 202 uint32_t run; 203 }; 204 205 /* PCM device private data */ 206 struct sc_pcminfo { 207 device_t dev; 208 uint32_t (*ih) (struct sc_pcminfo *scp); 209 uint32_t chnum; 210 struct sc_chinfo chan[HDSP_MAX_CHANS]; 211 struct sc_info *sc; 212 struct hdsp_channel *hc; 213 }; 214 215 /* HDSP device private data */ 216 struct sc_info { 217 device_t dev; 218 struct mtx *lock; 219 220 uint32_t ctrl_register; 221 uint32_t type; 222 223 /* Control/Status register */ 224 struct resource *cs; 225 int csid; 226 bus_space_tag_t cst; 227 bus_space_handle_t csh; 228 229 struct resource *irq; 230 int irqid; 231 void *ih; 232 bus_dma_tag_t dmat; 233 234 /* Play/Record DMA buffers */ 235 uint32_t *pbuf; 236 uint32_t *rbuf; 237 uint32_t bufsize; 238 bus_dmamap_t pmap; 239 bus_dmamap_t rmap; 240 uint32_t period; 241 uint32_t speed; 242 uint32_t force_period; 243 uint32_t force_speed; 244 }; 245 246 #define hdsp_read_1(sc, regno) \ 247 bus_space_read_1((sc)->cst, (sc)->csh, (regno)) 248 #define hdsp_read_2(sc, regno) \ 249 bus_space_read_2((sc)->cst, (sc)->csh, (regno)) 250 #define hdsp_read_4(sc, regno) \ 251 bus_space_read_4((sc)->cst, (sc)->csh, (regno)) 252 253 #define hdsp_write_1(sc, regno, data) \ 254 bus_space_write_1((sc)->cst, (sc)->csh, (regno), (data)) 255 #define hdsp_write_2(sc, regno, data) \ 256 bus_space_write_2((sc)->cst, (sc)->csh, (regno), (data)) 257 #define hdsp_write_4(sc, regno, data) \ 258 bus_space_write_4((sc)->cst, (sc)->csh, (regno), (data)) 259