1 /*- 2 * Copyright (c) 2008 Benno Rice. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 25 #include <sys/cdefs.h> 26 __FBSDID("$FreeBSD$"); 27 28 /* 29 * Driver for SMSC LAN91C111, may work for older variants. 30 */ 31 32 #ifdef HAVE_KERNEL_OPTION_HEADERS 33 #include "opt_device_polling.h" 34 #endif 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/errno.h> 39 #include <sys/kernel.h> 40 #include <sys/sockio.h> 41 #include <sys/malloc.h> 42 #include <sys/mbuf.h> 43 #include <sys/queue.h> 44 #include <sys/socket.h> 45 #include <sys/syslog.h> 46 #include <sys/taskqueue.h> 47 48 #include <sys/module.h> 49 #include <sys/bus.h> 50 51 #include <machine/bus.h> 52 #include <machine/resource.h> 53 #include <sys/rman.h> 54 55 #include <net/ethernet.h> 56 #include <net/if.h> 57 #include <net/if_var.h> 58 #include <net/if_arp.h> 59 #include <net/if_dl.h> 60 #include <net/if_types.h> 61 #include <net/if_mib.h> 62 #include <net/if_media.h> 63 64 #ifdef INET 65 #include <netinet/in.h> 66 #include <netinet/in_systm.h> 67 #include <netinet/in_var.h> 68 #include <netinet/ip.h> 69 #endif 70 71 #include <net/bpf.h> 72 #include <net/bpfdesc.h> 73 74 #include <dev/smc/if_smcreg.h> 75 #include <dev/smc/if_smcvar.h> 76 77 #include <dev/mii/mii.h> 78 #include <dev/mii/mii_bitbang.h> 79 #include <dev/mii/miivar.h> 80 81 #define SMC_LOCK(sc) mtx_lock(&(sc)->smc_mtx) 82 #define SMC_UNLOCK(sc) mtx_unlock(&(sc)->smc_mtx) 83 #define SMC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->smc_mtx, MA_OWNED) 84 85 #define SMC_INTR_PRIORITY 0 86 #define SMC_RX_PRIORITY 5 87 #define SMC_TX_PRIORITY 10 88 89 devclass_t smc_devclass; 90 91 static const char *smc_chip_ids[16] = { 92 NULL, NULL, NULL, 93 /* 3 */ "SMSC LAN91C90 or LAN91C92", 94 /* 4 */ "SMSC LAN91C94", 95 /* 5 */ "SMSC LAN91C95", 96 /* 6 */ "SMSC LAN91C96", 97 /* 7 */ "SMSC LAN91C100", 98 /* 8 */ "SMSC LAN91C100FD", 99 /* 9 */ "SMSC LAN91C110FD or LAN91C111FD", 100 NULL, NULL, NULL, 101 NULL, NULL, NULL 102 }; 103 104 static void smc_init(void *); 105 static void smc_start(struct ifnet *); 106 static void smc_stop(struct smc_softc *); 107 static int smc_ioctl(struct ifnet *, u_long, caddr_t); 108 109 static void smc_init_locked(struct smc_softc *); 110 static void smc_start_locked(struct ifnet *); 111 static void smc_reset(struct smc_softc *); 112 static int smc_mii_ifmedia_upd(struct ifnet *); 113 static void smc_mii_ifmedia_sts(struct ifnet *, struct ifmediareq *); 114 static void smc_mii_tick(void *); 115 static void smc_mii_mediachg(struct smc_softc *); 116 static int smc_mii_mediaioctl(struct smc_softc *, struct ifreq *, u_long); 117 118 static void smc_task_intr(void *, int); 119 static void smc_task_rx(void *, int); 120 static void smc_task_tx(void *, int); 121 122 static driver_filter_t smc_intr; 123 static timeout_t smc_watchdog; 124 #ifdef DEVICE_POLLING 125 static poll_handler_t smc_poll; 126 #endif 127 128 /* 129 * MII bit-bang glue 130 */ 131 static uint32_t smc_mii_bitbang_read(device_t); 132 static void smc_mii_bitbang_write(device_t, uint32_t); 133 134 static const struct mii_bitbang_ops smc_mii_bitbang_ops = { 135 smc_mii_bitbang_read, 136 smc_mii_bitbang_write, 137 { 138 MGMT_MDO, /* MII_BIT_MDO */ 139 MGMT_MDI, /* MII_BIT_MDI */ 140 MGMT_MCLK, /* MII_BIT_MDC */ 141 MGMT_MDOE, /* MII_BIT_DIR_HOST_PHY */ 142 0, /* MII_BIT_DIR_PHY_HOST */ 143 } 144 }; 145 146 static __inline void 147 smc_select_bank(struct smc_softc *sc, uint16_t bank) 148 { 149 150 bus_barrier(sc->smc_reg, BSR, 2, 151 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 152 bus_write_2(sc->smc_reg, BSR, bank & BSR_BANK_MASK); 153 bus_barrier(sc->smc_reg, BSR, 2, 154 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 155 } 156 157 /* Never call this when not in bank 2. */ 158 static __inline void 159 smc_mmu_wait(struct smc_softc *sc) 160 { 161 162 KASSERT((bus_read_2(sc->smc_reg, BSR) & 163 BSR_BANK_MASK) == 2, ("%s: smc_mmu_wait called when not in bank 2", 164 device_get_nameunit(sc->smc_dev))); 165 while (bus_read_2(sc->smc_reg, MMUCR) & MMUCR_BUSY) 166 ; 167 } 168 169 static __inline uint8_t 170 smc_read_1(struct smc_softc *sc, bus_size_t offset) 171 { 172 173 return (bus_read_1(sc->smc_reg, offset)); 174 } 175 176 static __inline void 177 smc_write_1(struct smc_softc *sc, bus_size_t offset, uint8_t val) 178 { 179 180 bus_write_1(sc->smc_reg, offset, val); 181 } 182 183 static __inline uint16_t 184 smc_read_2(struct smc_softc *sc, bus_size_t offset) 185 { 186 187 return (bus_read_2(sc->smc_reg, offset)); 188 } 189 190 static __inline void 191 smc_write_2(struct smc_softc *sc, bus_size_t offset, uint16_t val) 192 { 193 194 bus_write_2(sc->smc_reg, offset, val); 195 } 196 197 static __inline void 198 smc_read_multi_2(struct smc_softc *sc, bus_size_t offset, uint16_t *datap, 199 bus_size_t count) 200 { 201 202 bus_read_multi_2(sc->smc_reg, offset, datap, count); 203 } 204 205 static __inline void 206 smc_write_multi_2(struct smc_softc *sc, bus_size_t offset, uint16_t *datap, 207 bus_size_t count) 208 { 209 210 bus_write_multi_2(sc->smc_reg, offset, datap, count); 211 } 212 213 static __inline void 214 smc_barrier(struct smc_softc *sc, bus_size_t offset, bus_size_t length, 215 int flags) 216 { 217 218 bus_barrier(sc->smc_reg, offset, length, flags); 219 } 220 221 int 222 smc_probe(device_t dev) 223 { 224 int rid, type, error; 225 uint16_t val; 226 struct smc_softc *sc; 227 struct resource *reg; 228 229 sc = device_get_softc(dev); 230 rid = 0; 231 type = SYS_RES_IOPORT; 232 error = 0; 233 234 if (sc->smc_usemem) 235 type = SYS_RES_MEMORY; 236 237 reg = bus_alloc_resource(dev, type, &rid, 0, ~0, 16, RF_ACTIVE); 238 if (reg == NULL) { 239 if (bootverbose) 240 device_printf(dev, 241 "could not allocate I/O resource for probe\n"); 242 return (ENXIO); 243 } 244 245 /* Check for the identification value in the BSR. */ 246 val = bus_read_2(reg, BSR); 247 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) { 248 if (bootverbose) 249 device_printf(dev, "identification value not in BSR\n"); 250 error = ENXIO; 251 goto done; 252 } 253 254 /* 255 * Try switching banks and make sure we still get the identification 256 * value. 257 */ 258 bus_write_2(reg, BSR, 0); 259 val = bus_read_2(reg, BSR); 260 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) { 261 if (bootverbose) 262 device_printf(dev, 263 "identification value not in BSR after write\n"); 264 error = ENXIO; 265 goto done; 266 } 267 268 #if 0 269 /* Check the BAR. */ 270 bus_write_2(reg, BSR, 1); 271 val = bus_read_2(reg, BAR); 272 val = BAR_ADDRESS(val); 273 if (rman_get_start(reg) != val) { 274 if (bootverbose) 275 device_printf(dev, "BAR address %x does not match " 276 "I/O resource address %lx\n", val, 277 rman_get_start(reg)); 278 error = ENXIO; 279 goto done; 280 } 281 #endif 282 283 /* Compare REV against known chip revisions. */ 284 bus_write_2(reg, BSR, 3); 285 val = bus_read_2(reg, REV); 286 val = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT; 287 if (smc_chip_ids[val] == NULL) { 288 if (bootverbose) 289 device_printf(dev, "Unknown chip revision: %d\n", val); 290 error = ENXIO; 291 goto done; 292 } 293 294 device_set_desc(dev, smc_chip_ids[val]); 295 296 done: 297 bus_release_resource(dev, type, rid, reg); 298 return (error); 299 } 300 301 int 302 smc_attach(device_t dev) 303 { 304 int type, error; 305 uint16_t val; 306 u_char eaddr[ETHER_ADDR_LEN]; 307 struct smc_softc *sc; 308 struct ifnet *ifp; 309 310 sc = device_get_softc(dev); 311 error = 0; 312 313 sc->smc_dev = dev; 314 315 ifp = sc->smc_ifp = if_alloc(IFT_ETHER); 316 if (ifp == NULL) { 317 error = ENOSPC; 318 goto done; 319 } 320 321 mtx_init(&sc->smc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 322 323 /* Set up watchdog callout. */ 324 callout_init_mtx(&sc->smc_watchdog, &sc->smc_mtx, 0); 325 326 type = SYS_RES_IOPORT; 327 if (sc->smc_usemem) 328 type = SYS_RES_MEMORY; 329 330 sc->smc_reg_rid = 0; 331 sc->smc_reg = bus_alloc_resource(dev, type, &sc->smc_reg_rid, 0, ~0, 332 16, RF_ACTIVE); 333 if (sc->smc_reg == NULL) { 334 error = ENXIO; 335 goto done; 336 } 337 338 sc->smc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->smc_irq_rid, 0, 339 ~0, 1, RF_ACTIVE | RF_SHAREABLE); 340 if (sc->smc_irq == NULL) { 341 error = ENXIO; 342 goto done; 343 } 344 345 SMC_LOCK(sc); 346 smc_reset(sc); 347 SMC_UNLOCK(sc); 348 349 smc_select_bank(sc, 3); 350 val = smc_read_2(sc, REV); 351 sc->smc_chip = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT; 352 sc->smc_rev = (val * REV_REV_MASK) >> REV_REV_SHIFT; 353 if (bootverbose) 354 device_printf(dev, "revision %x\n", sc->smc_rev); 355 356 callout_init_mtx(&sc->smc_mii_tick_ch, &sc->smc_mtx, 357 CALLOUT_RETURNUNLOCKED); 358 if (sc->smc_chip >= REV_CHIP_91110FD) { 359 (void)mii_attach(dev, &sc->smc_miibus, ifp, 360 smc_mii_ifmedia_upd, smc_mii_ifmedia_sts, BMSR_DEFCAPMASK, 361 MII_PHY_ANY, MII_OFFSET_ANY, 0); 362 if (sc->smc_miibus != NULL) { 363 sc->smc_mii_tick = smc_mii_tick; 364 sc->smc_mii_mediachg = smc_mii_mediachg; 365 sc->smc_mii_mediaioctl = smc_mii_mediaioctl; 366 } 367 } 368 369 smc_select_bank(sc, 1); 370 eaddr[0] = smc_read_1(sc, IAR0); 371 eaddr[1] = smc_read_1(sc, IAR1); 372 eaddr[2] = smc_read_1(sc, IAR2); 373 eaddr[3] = smc_read_1(sc, IAR3); 374 eaddr[4] = smc_read_1(sc, IAR4); 375 eaddr[5] = smc_read_1(sc, IAR5); 376 377 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 378 ifp->if_softc = sc; 379 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 380 ifp->if_init = smc_init; 381 ifp->if_ioctl = smc_ioctl; 382 ifp->if_start = smc_start; 383 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 384 IFQ_SET_READY(&ifp->if_snd); 385 386 ifp->if_capabilities = ifp->if_capenable = 0; 387 388 #ifdef DEVICE_POLLING 389 ifp->if_capabilities |= IFCAP_POLLING; 390 #endif 391 392 ether_ifattach(ifp, eaddr); 393 394 /* Set up taskqueue */ 395 TASK_INIT(&sc->smc_intr, SMC_INTR_PRIORITY, smc_task_intr, ifp); 396 TASK_INIT(&sc->smc_rx, SMC_RX_PRIORITY, smc_task_rx, ifp); 397 TASK_INIT(&sc->smc_tx, SMC_TX_PRIORITY, smc_task_tx, ifp); 398 sc->smc_tq = taskqueue_create_fast("smc_taskq", M_NOWAIT, 399 taskqueue_thread_enqueue, &sc->smc_tq); 400 taskqueue_start_threads(&sc->smc_tq, 1, PI_NET, "%s taskq", 401 device_get_nameunit(sc->smc_dev)); 402 403 /* Mask all interrupts. */ 404 sc->smc_mask = 0; 405 smc_write_1(sc, MSK, 0); 406 407 /* Wire up interrupt */ 408 error = bus_setup_intr(dev, sc->smc_irq, 409 INTR_TYPE_NET|INTR_MPSAFE, smc_intr, NULL, sc, &sc->smc_ih); 410 if (error != 0) 411 goto done; 412 413 done: 414 if (error != 0) 415 smc_detach(dev); 416 return (error); 417 } 418 419 int 420 smc_detach(device_t dev) 421 { 422 int type; 423 struct smc_softc *sc; 424 425 sc = device_get_softc(dev); 426 SMC_LOCK(sc); 427 smc_stop(sc); 428 SMC_UNLOCK(sc); 429 430 if (sc->smc_ifp != NULL) { 431 ether_ifdetach(sc->smc_ifp); 432 } 433 434 callout_drain(&sc->smc_watchdog); 435 callout_drain(&sc->smc_mii_tick_ch); 436 437 #ifdef DEVICE_POLLING 438 if (sc->smc_ifp->if_capenable & IFCAP_POLLING) 439 ether_poll_deregister(sc->smc_ifp); 440 #endif 441 442 if (sc->smc_ih != NULL) 443 bus_teardown_intr(sc->smc_dev, sc->smc_irq, sc->smc_ih); 444 445 if (sc->smc_tq != NULL) { 446 taskqueue_drain(sc->smc_tq, &sc->smc_intr); 447 taskqueue_drain(sc->smc_tq, &sc->smc_rx); 448 taskqueue_drain(sc->smc_tq, &sc->smc_tx); 449 taskqueue_free(sc->smc_tq); 450 sc->smc_tq = NULL; 451 } 452 453 if (sc->smc_ifp != NULL) { 454 if_free(sc->smc_ifp); 455 } 456 457 if (sc->smc_miibus != NULL) { 458 device_delete_child(sc->smc_dev, sc->smc_miibus); 459 bus_generic_detach(sc->smc_dev); 460 } 461 462 if (sc->smc_reg != NULL) { 463 type = SYS_RES_IOPORT; 464 if (sc->smc_usemem) 465 type = SYS_RES_MEMORY; 466 467 bus_release_resource(sc->smc_dev, type, sc->smc_reg_rid, 468 sc->smc_reg); 469 } 470 471 if (sc->smc_irq != NULL) 472 bus_release_resource(sc->smc_dev, SYS_RES_IRQ, sc->smc_irq_rid, 473 sc->smc_irq); 474 475 if (mtx_initialized(&sc->smc_mtx)) 476 mtx_destroy(&sc->smc_mtx); 477 478 return (0); 479 } 480 481 static void 482 smc_start(struct ifnet *ifp) 483 { 484 struct smc_softc *sc; 485 486 sc = ifp->if_softc; 487 SMC_LOCK(sc); 488 smc_start_locked(ifp); 489 SMC_UNLOCK(sc); 490 } 491 492 static void 493 smc_start_locked(struct ifnet *ifp) 494 { 495 struct smc_softc *sc; 496 struct mbuf *m; 497 u_int len, npages, spin_count; 498 499 sc = ifp->if_softc; 500 SMC_ASSERT_LOCKED(sc); 501 502 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 503 return; 504 if (IFQ_IS_EMPTY(&ifp->if_snd)) 505 return; 506 507 /* 508 * Grab the next packet. If it's too big, drop it. 509 */ 510 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 511 len = m_length(m, NULL); 512 len += (len & 1); 513 if (len > ETHER_MAX_LEN - ETHER_CRC_LEN) { 514 if_printf(ifp, "large packet discarded\n"); 515 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 516 m_freem(m); 517 return; /* XXX readcheck? */ 518 } 519 520 /* 521 * Flag that we're busy. 522 */ 523 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 524 sc->smc_pending = m; 525 526 /* 527 * Work out how many 256 byte "pages" we need. We have to include the 528 * control data for the packet in this calculation. 529 */ 530 npages = (len + PKT_CTRL_DATA_LEN) >> 8; 531 if (npages == 0) 532 npages = 1; 533 534 /* 535 * Request memory. 536 */ 537 smc_select_bank(sc, 2); 538 smc_mmu_wait(sc); 539 smc_write_2(sc, MMUCR, MMUCR_CMD_TX_ALLOC | npages); 540 541 /* 542 * Spin briefly to see if the allocation succeeds. 543 */ 544 spin_count = TX_ALLOC_WAIT_TIME; 545 do { 546 if (smc_read_1(sc, IST) & ALLOC_INT) { 547 smc_write_1(sc, ACK, ALLOC_INT); 548 break; 549 } 550 } while (--spin_count); 551 552 /* 553 * If the allocation is taking too long, unmask the alloc interrupt 554 * and wait. 555 */ 556 if (spin_count == 0) { 557 sc->smc_mask |= ALLOC_INT; 558 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 559 smc_write_1(sc, MSK, sc->smc_mask); 560 return; 561 } 562 563 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); 564 } 565 566 static void 567 smc_task_tx(void *context, int pending) 568 { 569 struct ifnet *ifp; 570 struct smc_softc *sc; 571 struct mbuf *m, *m0; 572 u_int packet, len; 573 int last_len; 574 uint8_t *data; 575 576 (void)pending; 577 ifp = (struct ifnet *)context; 578 sc = ifp->if_softc; 579 580 SMC_LOCK(sc); 581 582 if (sc->smc_pending == NULL) { 583 SMC_UNLOCK(sc); 584 goto next_packet; 585 } 586 587 m = m0 = sc->smc_pending; 588 sc->smc_pending = NULL; 589 smc_select_bank(sc, 2); 590 591 /* 592 * Check the allocation result. 593 */ 594 packet = smc_read_1(sc, ARR); 595 596 /* 597 * If the allocation failed, requeue the packet and retry. 598 */ 599 if (packet & ARR_FAILED) { 600 IFQ_DRV_PREPEND(&ifp->if_snd, m); 601 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 602 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 603 smc_start_locked(ifp); 604 SMC_UNLOCK(sc); 605 return; 606 } 607 608 /* 609 * Tell the device to write to our packet number. 610 */ 611 smc_write_1(sc, PNR, packet); 612 smc_write_2(sc, PTR, 0 | PTR_AUTO_INCR); 613 614 /* 615 * Tell the device how long the packet is (including control data). 616 */ 617 len = m_length(m, 0); 618 len += PKT_CTRL_DATA_LEN; 619 smc_write_2(sc, DATA0, 0); 620 smc_write_2(sc, DATA0, len); 621 622 /* 623 * Push the data out to the device. 624 */ 625 data = NULL; 626 last_len = 0; 627 for (; m != NULL; m = m->m_next) { 628 data = mtod(m, uint8_t *); 629 smc_write_multi_2(sc, DATA0, (uint16_t *)data, m->m_len / 2); 630 last_len = m->m_len; 631 } 632 633 /* 634 * Push out the control byte and and the odd byte if needed. 635 */ 636 if ((len & 1) != 0 && data != NULL) 637 smc_write_2(sc, DATA0, (CTRL_ODD << 8) | data[last_len - 1]); 638 else 639 smc_write_2(sc, DATA0, 0); 640 641 /* 642 * Unmask the TX empty interrupt. 643 */ 644 sc->smc_mask |= TX_EMPTY_INT; 645 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 646 smc_write_1(sc, MSK, sc->smc_mask); 647 648 /* 649 * Enqueue the packet. 650 */ 651 smc_mmu_wait(sc); 652 smc_write_2(sc, MMUCR, MMUCR_CMD_ENQUEUE); 653 callout_reset(&sc->smc_watchdog, hz * 2, smc_watchdog, sc); 654 655 /* 656 * Finish up. 657 */ 658 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 659 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 660 SMC_UNLOCK(sc); 661 BPF_MTAP(ifp, m0); 662 m_freem(m0); 663 664 next_packet: 665 /* 666 * See if there's anything else to do. 667 */ 668 smc_start(ifp); 669 } 670 671 static void 672 smc_task_rx(void *context, int pending) 673 { 674 u_int packet, status, len; 675 uint8_t *data; 676 struct ifnet *ifp; 677 struct smc_softc *sc; 678 struct mbuf *m, *mhead, *mtail; 679 680 (void)pending; 681 ifp = (struct ifnet *)context; 682 sc = ifp->if_softc; 683 mhead = mtail = NULL; 684 685 SMC_LOCK(sc); 686 687 packet = smc_read_1(sc, FIFO_RX); 688 while ((packet & FIFO_EMPTY) == 0) { 689 /* 690 * Grab an mbuf and attach a cluster. 691 */ 692 MGETHDR(m, M_NOWAIT, MT_DATA); 693 if (m == NULL) { 694 break; 695 } 696 if (!(MCLGET(m, M_NOWAIT))) { 697 m_freem(m); 698 break; 699 } 700 701 /* 702 * Point to the start of the packet. 703 */ 704 smc_select_bank(sc, 2); 705 smc_write_1(sc, PNR, packet); 706 smc_write_2(sc, PTR, 0 | PTR_READ | PTR_RCV | PTR_AUTO_INCR); 707 708 /* 709 * Grab status and packet length. 710 */ 711 status = smc_read_2(sc, DATA0); 712 len = smc_read_2(sc, DATA0) & RX_LEN_MASK; 713 len -= 6; 714 if (status & RX_ODDFRM) 715 len += 1; 716 717 /* 718 * Check for errors. 719 */ 720 if (status & (RX_TOOSHORT | RX_TOOLNG | RX_BADCRC | RX_ALGNERR)) { 721 smc_mmu_wait(sc); 722 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE); 723 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 724 m_freem(m); 725 break; 726 } 727 728 /* 729 * Set the mbuf up the way we want it. 730 */ 731 m->m_pkthdr.rcvif = ifp; 732 m->m_pkthdr.len = m->m_len = len + 2; /* XXX: Is this right? */ 733 m_adj(m, ETHER_ALIGN); 734 735 /* 736 * Pull the packet out of the device. Make sure we're in the 737 * right bank first as things may have changed while we were 738 * allocating our mbuf. 739 */ 740 smc_select_bank(sc, 2); 741 smc_write_1(sc, PNR, packet); 742 smc_write_2(sc, PTR, 4 | PTR_READ | PTR_RCV | PTR_AUTO_INCR); 743 data = mtod(m, uint8_t *); 744 smc_read_multi_2(sc, DATA0, (uint16_t *)data, len >> 1); 745 if (len & 1) { 746 data += len & ~1; 747 *data = smc_read_1(sc, DATA0); 748 } 749 750 /* 751 * Tell the device we're done. 752 */ 753 smc_mmu_wait(sc); 754 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE); 755 if (m == NULL) { 756 break; 757 } 758 759 if (mhead == NULL) { 760 mhead = mtail = m; 761 m->m_next = NULL; 762 } else { 763 mtail->m_next = m; 764 mtail = m; 765 } 766 packet = smc_read_1(sc, FIFO_RX); 767 } 768 769 sc->smc_mask |= RCV_INT; 770 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 771 smc_write_1(sc, MSK, sc->smc_mask); 772 773 SMC_UNLOCK(sc); 774 775 while (mhead != NULL) { 776 m = mhead; 777 mhead = mhead->m_next; 778 m->m_next = NULL; 779 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 780 (*ifp->if_input)(ifp, m); 781 } 782 } 783 784 #ifdef DEVICE_POLLING 785 static void 786 smc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 787 { 788 struct smc_softc *sc; 789 790 sc = ifp->if_softc; 791 792 SMC_LOCK(sc); 793 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 794 SMC_UNLOCK(sc); 795 return; 796 } 797 SMC_UNLOCK(sc); 798 799 if (cmd == POLL_AND_CHECK_STATUS) 800 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr); 801 } 802 #endif 803 804 static int 805 smc_intr(void *context) 806 { 807 struct smc_softc *sc; 808 uint32_t curbank; 809 810 sc = (struct smc_softc *)context; 811 812 /* 813 * Save current bank and restore later in this function 814 */ 815 curbank = (smc_read_2(sc, BSR) & BSR_BANK_MASK); 816 817 /* 818 * Block interrupts in order to let smc_task_intr to kick in 819 */ 820 smc_select_bank(sc, 2); 821 smc_write_1(sc, MSK, 0); 822 823 /* Restore bank */ 824 smc_select_bank(sc, curbank); 825 826 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr); 827 return (FILTER_HANDLED); 828 } 829 830 static void 831 smc_task_intr(void *context, int pending) 832 { 833 struct smc_softc *sc; 834 struct ifnet *ifp; 835 u_int status, packet, counter, tcr; 836 837 (void)pending; 838 ifp = (struct ifnet *)context; 839 sc = ifp->if_softc; 840 841 SMC_LOCK(sc); 842 843 smc_select_bank(sc, 2); 844 845 /* 846 * Find out what interrupts are flagged. 847 */ 848 status = smc_read_1(sc, IST) & sc->smc_mask; 849 850 /* 851 * Transmit error 852 */ 853 if (status & TX_INT) { 854 /* 855 * Kill off the packet if there is one and re-enable transmit. 856 */ 857 packet = smc_read_1(sc, FIFO_TX); 858 if ((packet & FIFO_EMPTY) == 0) { 859 callout_stop(&sc->smc_watchdog); 860 smc_select_bank(sc, 2); 861 smc_write_1(sc, PNR, packet); 862 smc_write_2(sc, PTR, 0 | PTR_READ | 863 PTR_AUTO_INCR); 864 smc_select_bank(sc, 0); 865 tcr = smc_read_2(sc, EPHSR); 866 #if 0 867 if ((tcr & EPHSR_TX_SUC) == 0) 868 device_printf(sc->smc_dev, 869 "bad packet\n"); 870 #endif 871 smc_select_bank(sc, 2); 872 smc_mmu_wait(sc); 873 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE_PKT); 874 875 smc_select_bank(sc, 0); 876 tcr = smc_read_2(sc, TCR); 877 tcr |= TCR_TXENA | TCR_PAD_EN; 878 smc_write_2(sc, TCR, tcr); 879 smc_select_bank(sc, 2); 880 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); 881 } 882 883 /* 884 * Ack the interrupt. 885 */ 886 smc_write_1(sc, ACK, TX_INT); 887 } 888 889 /* 890 * Receive 891 */ 892 if (status & RCV_INT) { 893 smc_write_1(sc, ACK, RCV_INT); 894 sc->smc_mask &= ~RCV_INT; 895 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_rx); 896 } 897 898 /* 899 * Allocation 900 */ 901 if (status & ALLOC_INT) { 902 smc_write_1(sc, ACK, ALLOC_INT); 903 sc->smc_mask &= ~ALLOC_INT; 904 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); 905 } 906 907 /* 908 * Receive overrun 909 */ 910 if (status & RX_OVRN_INT) { 911 smc_write_1(sc, ACK, RX_OVRN_INT); 912 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 913 } 914 915 /* 916 * Transmit empty 917 */ 918 if (status & TX_EMPTY_INT) { 919 smc_write_1(sc, ACK, TX_EMPTY_INT); 920 sc->smc_mask &= ~TX_EMPTY_INT; 921 callout_stop(&sc->smc_watchdog); 922 923 /* 924 * Update collision stats. 925 */ 926 smc_select_bank(sc, 0); 927 counter = smc_read_2(sc, ECR); 928 smc_select_bank(sc, 2); 929 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 930 ((counter & ECR_SNGLCOL_MASK) >> ECR_SNGLCOL_SHIFT) + 931 ((counter & ECR_MULCOL_MASK) >> ECR_MULCOL_SHIFT)); 932 933 /* 934 * See if there are any packets to transmit. 935 */ 936 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); 937 } 938 939 /* 940 * Update the interrupt mask. 941 */ 942 smc_select_bank(sc, 2); 943 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 944 smc_write_1(sc, MSK, sc->smc_mask); 945 946 SMC_UNLOCK(sc); 947 } 948 949 static uint32_t 950 smc_mii_bitbang_read(device_t dev) 951 { 952 struct smc_softc *sc; 953 uint32_t val; 954 955 sc = device_get_softc(dev); 956 957 SMC_ASSERT_LOCKED(sc); 958 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3, 959 ("%s: smc_mii_bitbang_read called with bank %d (!= 3)", 960 device_get_nameunit(sc->smc_dev), 961 smc_read_2(sc, BSR) & BSR_BANK_MASK)); 962 963 val = smc_read_2(sc, MGMT); 964 smc_barrier(sc, MGMT, 2, 965 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 966 967 return (val); 968 } 969 970 static void 971 smc_mii_bitbang_write(device_t dev, uint32_t val) 972 { 973 struct smc_softc *sc; 974 975 sc = device_get_softc(dev); 976 977 SMC_ASSERT_LOCKED(sc); 978 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3, 979 ("%s: smc_mii_bitbang_write called with bank %d (!= 3)", 980 device_get_nameunit(sc->smc_dev), 981 smc_read_2(sc, BSR) & BSR_BANK_MASK)); 982 983 smc_write_2(sc, MGMT, val); 984 smc_barrier(sc, MGMT, 2, 985 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 986 } 987 988 int 989 smc_miibus_readreg(device_t dev, int phy, int reg) 990 { 991 struct smc_softc *sc; 992 int val; 993 994 sc = device_get_softc(dev); 995 996 SMC_LOCK(sc); 997 998 smc_select_bank(sc, 3); 999 1000 val = mii_bitbang_readreg(dev, &smc_mii_bitbang_ops, phy, reg); 1001 1002 SMC_UNLOCK(sc); 1003 return (val); 1004 } 1005 1006 int 1007 smc_miibus_writereg(device_t dev, int phy, int reg, int data) 1008 { 1009 struct smc_softc *sc; 1010 1011 sc = device_get_softc(dev); 1012 1013 SMC_LOCK(sc); 1014 1015 smc_select_bank(sc, 3); 1016 1017 mii_bitbang_writereg(dev, &smc_mii_bitbang_ops, phy, reg, data); 1018 1019 SMC_UNLOCK(sc); 1020 return (0); 1021 } 1022 1023 void 1024 smc_miibus_statchg(device_t dev) 1025 { 1026 struct smc_softc *sc; 1027 struct mii_data *mii; 1028 uint16_t tcr; 1029 1030 sc = device_get_softc(dev); 1031 mii = device_get_softc(sc->smc_miibus); 1032 1033 SMC_LOCK(sc); 1034 1035 smc_select_bank(sc, 0); 1036 tcr = smc_read_2(sc, TCR); 1037 1038 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1039 tcr |= TCR_SWFDUP; 1040 else 1041 tcr &= ~TCR_SWFDUP; 1042 1043 smc_write_2(sc, TCR, tcr); 1044 1045 SMC_UNLOCK(sc); 1046 } 1047 1048 static int 1049 smc_mii_ifmedia_upd(struct ifnet *ifp) 1050 { 1051 struct smc_softc *sc; 1052 struct mii_data *mii; 1053 1054 sc = ifp->if_softc; 1055 if (sc->smc_miibus == NULL) 1056 return (ENXIO); 1057 1058 mii = device_get_softc(sc->smc_miibus); 1059 return (mii_mediachg(mii)); 1060 } 1061 1062 static void 1063 smc_mii_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1064 { 1065 struct smc_softc *sc; 1066 struct mii_data *mii; 1067 1068 sc = ifp->if_softc; 1069 if (sc->smc_miibus == NULL) 1070 return; 1071 1072 mii = device_get_softc(sc->smc_miibus); 1073 mii_pollstat(mii); 1074 ifmr->ifm_active = mii->mii_media_active; 1075 ifmr->ifm_status = mii->mii_media_status; 1076 } 1077 1078 static void 1079 smc_mii_tick(void *context) 1080 { 1081 struct smc_softc *sc; 1082 1083 sc = (struct smc_softc *)context; 1084 1085 if (sc->smc_miibus == NULL) 1086 return; 1087 1088 SMC_UNLOCK(sc); 1089 1090 mii_tick(device_get_softc(sc->smc_miibus)); 1091 callout_reset(&sc->smc_mii_tick_ch, hz, smc_mii_tick, sc); 1092 } 1093 1094 static void 1095 smc_mii_mediachg(struct smc_softc *sc) 1096 { 1097 1098 if (sc->smc_miibus == NULL) 1099 return; 1100 mii_mediachg(device_get_softc(sc->smc_miibus)); 1101 } 1102 1103 static int 1104 smc_mii_mediaioctl(struct smc_softc *sc, struct ifreq *ifr, u_long command) 1105 { 1106 struct mii_data *mii; 1107 1108 if (sc->smc_miibus == NULL) 1109 return (EINVAL); 1110 1111 mii = device_get_softc(sc->smc_miibus); 1112 return (ifmedia_ioctl(sc->smc_ifp, ifr, &mii->mii_media, command)); 1113 } 1114 1115 static void 1116 smc_reset(struct smc_softc *sc) 1117 { 1118 u_int ctr; 1119 1120 SMC_ASSERT_LOCKED(sc); 1121 1122 smc_select_bank(sc, 2); 1123 1124 /* 1125 * Mask all interrupts. 1126 */ 1127 smc_write_1(sc, MSK, 0); 1128 1129 /* 1130 * Tell the device to reset. 1131 */ 1132 smc_select_bank(sc, 0); 1133 smc_write_2(sc, RCR, RCR_SOFT_RST); 1134 1135 /* 1136 * Set up the configuration register. 1137 */ 1138 smc_select_bank(sc, 1); 1139 smc_write_2(sc, CR, CR_EPH_POWER_EN); 1140 DELAY(1); 1141 1142 /* 1143 * Turn off transmit and receive. 1144 */ 1145 smc_select_bank(sc, 0); 1146 smc_write_2(sc, TCR, 0); 1147 smc_write_2(sc, RCR, 0); 1148 1149 /* 1150 * Set up the control register. 1151 */ 1152 smc_select_bank(sc, 1); 1153 ctr = smc_read_2(sc, CTR); 1154 ctr |= CTR_LE_ENABLE | CTR_AUTO_RELEASE; 1155 smc_write_2(sc, CTR, ctr); 1156 1157 /* 1158 * Reset the MMU. 1159 */ 1160 smc_select_bank(sc, 2); 1161 smc_mmu_wait(sc); 1162 smc_write_2(sc, MMUCR, MMUCR_CMD_MMU_RESET); 1163 } 1164 1165 static void 1166 smc_enable(struct smc_softc *sc) 1167 { 1168 struct ifnet *ifp; 1169 1170 SMC_ASSERT_LOCKED(sc); 1171 ifp = sc->smc_ifp; 1172 1173 /* 1174 * Set up the receive/PHY control register. 1175 */ 1176 smc_select_bank(sc, 0); 1177 smc_write_2(sc, RPCR, RPCR_ANEG | (RPCR_LED_LINK_ANY << RPCR_LSA_SHIFT) 1178 | (RPCR_LED_ACT_ANY << RPCR_LSB_SHIFT)); 1179 1180 /* 1181 * Set up the transmit and receive control registers. 1182 */ 1183 smc_write_2(sc, TCR, TCR_TXENA | TCR_PAD_EN); 1184 smc_write_2(sc, RCR, RCR_RXEN | RCR_STRIP_CRC); 1185 1186 /* 1187 * Set up the interrupt mask. 1188 */ 1189 smc_select_bank(sc, 2); 1190 sc->smc_mask = EPH_INT | RX_OVRN_INT | RCV_INT | TX_INT; 1191 if ((ifp->if_capenable & IFCAP_POLLING) != 0) 1192 smc_write_1(sc, MSK, sc->smc_mask); 1193 } 1194 1195 static void 1196 smc_stop(struct smc_softc *sc) 1197 { 1198 1199 SMC_ASSERT_LOCKED(sc); 1200 1201 /* 1202 * Turn off callouts. 1203 */ 1204 callout_stop(&sc->smc_watchdog); 1205 callout_stop(&sc->smc_mii_tick_ch); 1206 1207 /* 1208 * Mask all interrupts. 1209 */ 1210 smc_select_bank(sc, 2); 1211 sc->smc_mask = 0; 1212 smc_write_1(sc, MSK, 0); 1213 #ifdef DEVICE_POLLING 1214 ether_poll_deregister(sc->smc_ifp); 1215 sc->smc_ifp->if_capenable &= ~IFCAP_POLLING; 1216 sc->smc_ifp->if_capenable &= ~IFCAP_POLLING_NOCOUNT; 1217 #endif 1218 1219 /* 1220 * Disable transmit and receive. 1221 */ 1222 smc_select_bank(sc, 0); 1223 smc_write_2(sc, TCR, 0); 1224 smc_write_2(sc, RCR, 0); 1225 1226 sc->smc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1227 } 1228 1229 static void 1230 smc_watchdog(void *arg) 1231 { 1232 struct smc_softc *sc; 1233 1234 sc = (struct smc_softc *)arg; 1235 device_printf(sc->smc_dev, "watchdog timeout\n"); 1236 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr); 1237 } 1238 1239 static void 1240 smc_init(void *context) 1241 { 1242 struct smc_softc *sc; 1243 1244 sc = (struct smc_softc *)context; 1245 SMC_LOCK(sc); 1246 smc_init_locked(sc); 1247 SMC_UNLOCK(sc); 1248 } 1249 1250 static void 1251 smc_init_locked(struct smc_softc *sc) 1252 { 1253 struct ifnet *ifp; 1254 1255 SMC_ASSERT_LOCKED(sc); 1256 ifp = sc->smc_ifp; 1257 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1258 return; 1259 1260 smc_reset(sc); 1261 smc_enable(sc); 1262 1263 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1264 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1265 1266 smc_start_locked(ifp); 1267 1268 if (sc->smc_mii_tick != NULL) 1269 callout_reset(&sc->smc_mii_tick_ch, hz, sc->smc_mii_tick, sc); 1270 1271 #ifdef DEVICE_POLLING 1272 SMC_UNLOCK(sc); 1273 ether_poll_register(smc_poll, ifp); 1274 SMC_LOCK(sc); 1275 ifp->if_capenable |= IFCAP_POLLING; 1276 ifp->if_capenable |= IFCAP_POLLING_NOCOUNT; 1277 #endif 1278 } 1279 1280 static int 1281 smc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1282 { 1283 struct smc_softc *sc; 1284 int error; 1285 1286 sc = ifp->if_softc; 1287 error = 0; 1288 1289 switch (cmd) { 1290 case SIOCSIFFLAGS: 1291 if ((ifp->if_flags & IFF_UP) == 0 && 1292 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1293 SMC_LOCK(sc); 1294 smc_stop(sc); 1295 SMC_UNLOCK(sc); 1296 } else { 1297 smc_init(sc); 1298 if (sc->smc_mii_mediachg != NULL) 1299 sc->smc_mii_mediachg(sc); 1300 } 1301 break; 1302 1303 case SIOCADDMULTI: 1304 case SIOCDELMULTI: 1305 /* XXX 1306 SMC_LOCK(sc); 1307 smc_setmcast(sc); 1308 SMC_UNLOCK(sc); 1309 */ 1310 error = EINVAL; 1311 break; 1312 1313 case SIOCGIFMEDIA: 1314 case SIOCSIFMEDIA: 1315 if (sc->smc_mii_mediaioctl == NULL) { 1316 error = EINVAL; 1317 break; 1318 } 1319 sc->smc_mii_mediaioctl(sc, (struct ifreq *)data, cmd); 1320 break; 1321 1322 default: 1323 error = ether_ioctl(ifp, cmd, data); 1324 break; 1325 } 1326 1327 return (error); 1328 } 1329