1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright 2008-2018 Solarflare Communications Inc. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #ifndef _SYS_EFX_REGS_MCDI_AOE_H 31 #define _SYS_EFX_REGS_MCDI_AOE_H 32 33 34 35 /***********************************/ 36 /* MC_CMD_FC 37 * Perform an FC operation 38 */ 39 #define MC_CMD_FC 0x9 40 41 /* MC_CMD_FC_IN msgrequest */ 42 #define MC_CMD_FC_IN_LEN 4 43 #define MC_CMD_FC_IN_OP_HDR_OFST 0 44 #define MC_CMD_FC_IN_OP_HDR_LEN 4 45 #define MC_CMD_FC_IN_OP_LBN 0 46 #define MC_CMD_FC_IN_OP_WIDTH 8 47 /* enum: NULL MCDI command to FC. */ 48 #define MC_CMD_FC_OP_NULL 0x1 49 /* enum: Unused opcode */ 50 #define MC_CMD_FC_OP_UNUSED 0x2 51 /* enum: MAC driver commands */ 52 #define MC_CMD_FC_OP_MAC 0x3 53 /* enum: Read FC memory */ 54 #define MC_CMD_FC_OP_READ32 0x4 55 /* enum: Write to FC memory */ 56 #define MC_CMD_FC_OP_WRITE32 0x5 57 /* enum: Read FC memory */ 58 #define MC_CMD_FC_OP_TRC_READ 0x6 59 /* enum: Write to FC memory */ 60 #define MC_CMD_FC_OP_TRC_WRITE 0x7 61 /* enum: FC firmware Version */ 62 #define MC_CMD_FC_OP_GET_VERSION 0x8 63 /* enum: Read FC memory */ 64 #define MC_CMD_FC_OP_TRC_RX_READ 0x9 65 /* enum: Write to FC memory */ 66 #define MC_CMD_FC_OP_TRC_RX_WRITE 0xa 67 /* enum: SFP parameters */ 68 #define MC_CMD_FC_OP_SFP 0xb 69 /* enum: DDR3 test */ 70 #define MC_CMD_FC_OP_DDR_TEST 0xc 71 /* enum: Get Crash context from FC */ 72 #define MC_CMD_FC_OP_GET_ASSERT 0xd 73 /* enum: Get FPGA Build registers */ 74 #define MC_CMD_FC_OP_FPGA_BUILD 0xe 75 /* enum: Read map support commands */ 76 #define MC_CMD_FC_OP_READ_MAP 0xf 77 /* enum: FC Capabilities */ 78 #define MC_CMD_FC_OP_CAPABILITIES 0x10 79 /* enum: FC Global flags */ 80 #define MC_CMD_FC_OP_GLOBAL_FLAGS 0x11 81 /* enum: FC IO using relative addressing modes */ 82 #define MC_CMD_FC_OP_IO_REL 0x12 83 /* enum: FPGA link information */ 84 #define MC_CMD_FC_OP_UHLINK 0x13 85 /* enum: Configure loopbacks and link on FPGA ports */ 86 #define MC_CMD_FC_OP_SET_LINK 0x14 87 /* enum: Licensing operations relating to AOE */ 88 #define MC_CMD_FC_OP_LICENSE 0x15 89 /* enum: Startup information to the FC */ 90 #define MC_CMD_FC_OP_STARTUP 0x16 91 /* enum: Configure a DMA read */ 92 #define MC_CMD_FC_OP_DMA 0x17 93 /* enum: Configure a timed read */ 94 #define MC_CMD_FC_OP_TIMED_READ 0x18 95 /* enum: Control UART logging */ 96 #define MC_CMD_FC_OP_LOG 0x19 97 /* enum: Get the value of a given clock_id */ 98 #define MC_CMD_FC_OP_CLOCK 0x1a 99 /* enum: DDR3/QDR3 parameters */ 100 #define MC_CMD_FC_OP_DDR 0x1b 101 /* enum: PTP and timestamp control */ 102 #define MC_CMD_FC_OP_TIMESTAMP 0x1c 103 /* enum: Commands for SPI Flash interface */ 104 #define MC_CMD_FC_OP_SPI 0x1d 105 /* enum: Commands for diagnostic components */ 106 #define MC_CMD_FC_OP_DIAG 0x1e 107 /* enum: External AOE port. */ 108 #define MC_CMD_FC_IN_PORT_EXT_OFST 0x0 109 /* enum: Internal AOE port. */ 110 #define MC_CMD_FC_IN_PORT_INT_OFST 0x40 111 112 /* MC_CMD_FC_IN_NULL msgrequest */ 113 #define MC_CMD_FC_IN_NULL_LEN 4 114 #define MC_CMD_FC_IN_CMD_OFST 0 115 #define MC_CMD_FC_IN_CMD_LEN 4 116 117 /* MC_CMD_FC_IN_PHY msgrequest */ 118 #define MC_CMD_FC_IN_PHY_LEN 5 119 /* MC_CMD_FC_IN_CMD_OFST 0 */ 120 /* MC_CMD_FC_IN_CMD_LEN 4 */ 121 /* FC PHY driver operation code */ 122 #define MC_CMD_FC_IN_PHY_OP_OFST 4 123 #define MC_CMD_FC_IN_PHY_OP_LEN 1 124 /* enum: PHY init handler */ 125 #define MC_CMD_FC_OP_PHY_OP_INIT 0x1 126 /* enum: PHY reconfigure handler */ 127 #define MC_CMD_FC_OP_PHY_OP_RECONFIGURE 0x2 128 /* enum: PHY reboot handler */ 129 #define MC_CMD_FC_OP_PHY_OP_REBOOT 0x3 130 /* enum: PHY get_supported_cap handler */ 131 #define MC_CMD_FC_OP_PHY_OP_GET_SUPPORTED_CAP 0x4 132 /* enum: PHY get_config handler */ 133 #define MC_CMD_FC_OP_PHY_OP_GET_CONFIG 0x5 134 /* enum: PHY get_media_info handler */ 135 #define MC_CMD_FC_OP_PHY_OP_GET_MEDIA_INFO 0x6 136 /* enum: PHY set_led handler */ 137 #define MC_CMD_FC_OP_PHY_OP_SET_LED 0x7 138 /* enum: PHY lasi_interrupt handler */ 139 #define MC_CMD_FC_OP_PHY_OP_LASI_INTERRUPT 0x8 140 /* enum: PHY check_link handler */ 141 #define MC_CMD_FC_OP_PHY_OP_CHECK_LINK 0x9 142 /* enum: PHY fill_stats handler */ 143 #define MC_CMD_FC_OP_PHY_OP_FILL_STATS 0xa 144 /* enum: PHY bpx_link_state_changed handler */ 145 #define MC_CMD_FC_OP_PHY_OP_BPX_LINK_STATE_CHANGED 0xb 146 /* enum: PHY get_state handler */ 147 #define MC_CMD_FC_OP_PHY_OP_GET_STATE 0xc 148 /* enum: PHY start_bist handler */ 149 #define MC_CMD_FC_OP_PHY_OP_START_BIST 0xd 150 /* enum: PHY poll_bist handler */ 151 #define MC_CMD_FC_OP_PHY_OP_POLL_BIST 0xe 152 /* enum: PHY nvram_test handler */ 153 #define MC_CMD_FC_OP_PHY_OP_NVRAM_TEST 0xf 154 /* enum: PHY relinquish handler */ 155 #define MC_CMD_FC_OP_PHY_OP_RELINQUISH_SPI 0x10 156 /* enum: PHY read connection from FC - may be not required */ 157 #define MC_CMD_FC_OP_PHY_OP_GET_CONNECTION 0x11 158 /* enum: PHY read flags from FC - may be not required */ 159 #define MC_CMD_FC_OP_PHY_OP_GET_FLAGS 0x12 160 161 /* MC_CMD_FC_IN_PHY_INIT msgrequest */ 162 #define MC_CMD_FC_IN_PHY_INIT_LEN 4 163 #define MC_CMD_FC_IN_PHY_CMD_OFST 0 164 #define MC_CMD_FC_IN_PHY_CMD_LEN 4 165 166 /* MC_CMD_FC_IN_MAC msgrequest */ 167 #define MC_CMD_FC_IN_MAC_LEN 8 168 /* MC_CMD_FC_IN_CMD_OFST 0 */ 169 /* MC_CMD_FC_IN_CMD_LEN 4 */ 170 #define MC_CMD_FC_IN_MAC_HEADER_OFST 4 171 #define MC_CMD_FC_IN_MAC_HEADER_LEN 4 172 #define MC_CMD_FC_IN_MAC_OP_LBN 0 173 #define MC_CMD_FC_IN_MAC_OP_WIDTH 8 174 /* enum: MAC reconfigure handler */ 175 #define MC_CMD_FC_OP_MAC_OP_RECONFIGURE 0x1 176 /* enum: MAC Set command - same as MC_CMD_SET_MAC */ 177 #define MC_CMD_FC_OP_MAC_OP_SET_LINK 0x2 178 /* enum: MAC statistics */ 179 #define MC_CMD_FC_OP_MAC_OP_GET_STATS 0x3 180 /* enum: MAC RX statistics */ 181 #define MC_CMD_FC_OP_MAC_OP_GET_RX_STATS 0x6 182 /* enum: MAC TX statistics */ 183 #define MC_CMD_FC_OP_MAC_OP_GET_TX_STATS 0x7 184 /* enum: MAC Read status */ 185 #define MC_CMD_FC_OP_MAC_OP_READ_STATUS 0x8 186 #define MC_CMD_FC_IN_MAC_PORT_TYPE_LBN 8 187 #define MC_CMD_FC_IN_MAC_PORT_TYPE_WIDTH 8 188 /* enum: External FPGA port. */ 189 #define MC_CMD_FC_PORT_EXT 0x0 190 /* enum: Internal Siena-facing FPGA ports. */ 191 #define MC_CMD_FC_PORT_INT 0x1 192 #define MC_CMD_FC_IN_MAC_PORT_IDX_LBN 16 193 #define MC_CMD_FC_IN_MAC_PORT_IDX_WIDTH 8 194 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_LBN 24 195 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_WIDTH 8 196 /* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are 197 * irrelevant. Port number is derived from pci_fn; passed in FC header. 198 */ 199 #define MC_CMD_FC_OP_MAC_CMD_FORMAT_DEFAULT 0x0 200 /* enum: Override default port number. Port number determined by fields 201 * PORT_TYPE and PORT_IDX. 202 */ 203 #define MC_CMD_FC_OP_MAC_CMD_FORMAT_PORT_OVERRIDE 0x1 204 205 /* MC_CMD_FC_IN_MAC_RECONFIGURE msgrequest */ 206 #define MC_CMD_FC_IN_MAC_RECONFIGURE_LEN 8 207 /* MC_CMD_FC_IN_CMD_OFST 0 */ 208 /* MC_CMD_FC_IN_CMD_LEN 4 */ 209 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 210 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 211 212 /* MC_CMD_FC_IN_MAC_SET_LINK msgrequest */ 213 #define MC_CMD_FC_IN_MAC_SET_LINK_LEN 32 214 /* MC_CMD_FC_IN_CMD_OFST 0 */ 215 /* MC_CMD_FC_IN_CMD_LEN 4 */ 216 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 217 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 218 /* MTU size */ 219 #define MC_CMD_FC_IN_MAC_SET_LINK_MTU_OFST 8 220 #define MC_CMD_FC_IN_MAC_SET_LINK_MTU_LEN 4 221 /* Drain Tx FIFO */ 222 #define MC_CMD_FC_IN_MAC_SET_LINK_DRAIN_OFST 12 223 #define MC_CMD_FC_IN_MAC_SET_LINK_DRAIN_LEN 4 224 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_OFST 16 225 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LEN 8 226 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_OFST 16 227 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_OFST 20 228 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_OFST 24 229 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_LEN 4 230 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_LBN 0 231 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_WIDTH 1 232 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_LBN 1 233 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_WIDTH 1 234 #define MC_CMD_FC_IN_MAC_SET_LINK_FCNTL_OFST 28 235 #define MC_CMD_FC_IN_MAC_SET_LINK_FCNTL_LEN 4 236 237 /* MC_CMD_FC_IN_MAC_READ_STATUS msgrequest */ 238 #define MC_CMD_FC_IN_MAC_READ_STATUS_LEN 8 239 /* MC_CMD_FC_IN_CMD_OFST 0 */ 240 /* MC_CMD_FC_IN_CMD_LEN 4 */ 241 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 242 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 243 244 /* MC_CMD_FC_IN_MAC_GET_RX_STATS msgrequest */ 245 #define MC_CMD_FC_IN_MAC_GET_RX_STATS_LEN 8 246 /* MC_CMD_FC_IN_CMD_OFST 0 */ 247 /* MC_CMD_FC_IN_CMD_LEN 4 */ 248 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 249 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 250 251 /* MC_CMD_FC_IN_MAC_GET_TX_STATS msgrequest */ 252 #define MC_CMD_FC_IN_MAC_GET_TX_STATS_LEN 8 253 /* MC_CMD_FC_IN_CMD_OFST 0 */ 254 /* MC_CMD_FC_IN_CMD_LEN 4 */ 255 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 256 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 257 258 /* MC_CMD_FC_IN_MAC_GET_STATS msgrequest */ 259 #define MC_CMD_FC_IN_MAC_GET_STATS_LEN 20 260 /* MC_CMD_FC_IN_CMD_OFST 0 */ 261 /* MC_CMD_FC_IN_CMD_LEN 4 */ 262 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 263 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 264 /* MC Statistics index */ 265 #define MC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_OFST 8 266 #define MC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_LEN 4 267 #define MC_CMD_FC_IN_MAC_GET_STATS_FLAGS_OFST 12 268 #define MC_CMD_FC_IN_MAC_GET_STATS_FLAGS_LEN 4 269 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_LBN 0 270 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_WIDTH 1 271 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_LBN 1 272 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_WIDTH 1 273 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_LBN 2 274 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_WIDTH 1 275 /* Number of statistics to read */ 276 #define MC_CMD_FC_IN_MAC_GET_STATS_NUM_OFST 16 277 #define MC_CMD_FC_IN_MAC_GET_STATS_NUM_LEN 4 278 #define MC_CMD_FC_MAC_NSTATS_PER_BLOCK 0x1e /* enum */ 279 #define MC_CMD_FC_MAC_NBYTES_PER_STAT 0x8 /* enum */ 280 281 /* MC_CMD_FC_IN_READ32 msgrequest */ 282 #define MC_CMD_FC_IN_READ32_LEN 16 283 /* MC_CMD_FC_IN_CMD_OFST 0 */ 284 /* MC_CMD_FC_IN_CMD_LEN 4 */ 285 #define MC_CMD_FC_IN_READ32_ADDR_HI_OFST 4 286 #define MC_CMD_FC_IN_READ32_ADDR_HI_LEN 4 287 #define MC_CMD_FC_IN_READ32_ADDR_LO_OFST 8 288 #define MC_CMD_FC_IN_READ32_ADDR_LO_LEN 4 289 #define MC_CMD_FC_IN_READ32_NUMWORDS_OFST 12 290 #define MC_CMD_FC_IN_READ32_NUMWORDS_LEN 4 291 292 /* MC_CMD_FC_IN_WRITE32 msgrequest */ 293 #define MC_CMD_FC_IN_WRITE32_LENMIN 16 294 #define MC_CMD_FC_IN_WRITE32_LENMAX 252 295 #define MC_CMD_FC_IN_WRITE32_LEN(num) (12+4*(num)) 296 /* MC_CMD_FC_IN_CMD_OFST 0 */ 297 /* MC_CMD_FC_IN_CMD_LEN 4 */ 298 #define MC_CMD_FC_IN_WRITE32_ADDR_HI_OFST 4 299 #define MC_CMD_FC_IN_WRITE32_ADDR_HI_LEN 4 300 #define MC_CMD_FC_IN_WRITE32_ADDR_LO_OFST 8 301 #define MC_CMD_FC_IN_WRITE32_ADDR_LO_LEN 4 302 #define MC_CMD_FC_IN_WRITE32_BUFFER_OFST 12 303 #define MC_CMD_FC_IN_WRITE32_BUFFER_LEN 4 304 #define MC_CMD_FC_IN_WRITE32_BUFFER_MINNUM 1 305 #define MC_CMD_FC_IN_WRITE32_BUFFER_MAXNUM 60 306 307 /* MC_CMD_FC_IN_TRC_READ msgrequest */ 308 #define MC_CMD_FC_IN_TRC_READ_LEN 12 309 /* MC_CMD_FC_IN_CMD_OFST 0 */ 310 /* MC_CMD_FC_IN_CMD_LEN 4 */ 311 #define MC_CMD_FC_IN_TRC_READ_TRC_OFST 4 312 #define MC_CMD_FC_IN_TRC_READ_TRC_LEN 4 313 #define MC_CMD_FC_IN_TRC_READ_CHANNEL_OFST 8 314 #define MC_CMD_FC_IN_TRC_READ_CHANNEL_LEN 4 315 316 /* MC_CMD_FC_IN_TRC_WRITE msgrequest */ 317 #define MC_CMD_FC_IN_TRC_WRITE_LEN 28 318 /* MC_CMD_FC_IN_CMD_OFST 0 */ 319 /* MC_CMD_FC_IN_CMD_LEN 4 */ 320 #define MC_CMD_FC_IN_TRC_WRITE_TRC_OFST 4 321 #define MC_CMD_FC_IN_TRC_WRITE_TRC_LEN 4 322 #define MC_CMD_FC_IN_TRC_WRITE_CHANNEL_OFST 8 323 #define MC_CMD_FC_IN_TRC_WRITE_CHANNEL_LEN 4 324 #define MC_CMD_FC_IN_TRC_WRITE_DATA_OFST 12 325 #define MC_CMD_FC_IN_TRC_WRITE_DATA_LEN 4 326 #define MC_CMD_FC_IN_TRC_WRITE_DATA_NUM 4 327 328 /* MC_CMD_FC_IN_GET_VERSION msgrequest */ 329 #define MC_CMD_FC_IN_GET_VERSION_LEN 4 330 /* MC_CMD_FC_IN_CMD_OFST 0 */ 331 /* MC_CMD_FC_IN_CMD_LEN 4 */ 332 333 /* MC_CMD_FC_IN_TRC_RX_READ msgrequest */ 334 #define MC_CMD_FC_IN_TRC_RX_READ_LEN 12 335 /* MC_CMD_FC_IN_CMD_OFST 0 */ 336 /* MC_CMD_FC_IN_CMD_LEN 4 */ 337 #define MC_CMD_FC_IN_TRC_RX_READ_TRC_OFST 4 338 #define MC_CMD_FC_IN_TRC_RX_READ_TRC_LEN 4 339 #define MC_CMD_FC_IN_TRC_RX_READ_CHANNEL_OFST 8 340 #define MC_CMD_FC_IN_TRC_RX_READ_CHANNEL_LEN 4 341 342 /* MC_CMD_FC_IN_TRC_RX_WRITE msgrequest */ 343 #define MC_CMD_FC_IN_TRC_RX_WRITE_LEN 20 344 /* MC_CMD_FC_IN_CMD_OFST 0 */ 345 /* MC_CMD_FC_IN_CMD_LEN 4 */ 346 #define MC_CMD_FC_IN_TRC_RX_WRITE_TRC_OFST 4 347 #define MC_CMD_FC_IN_TRC_RX_WRITE_TRC_LEN 4 348 #define MC_CMD_FC_IN_TRC_RX_WRITE_CHANNEL_OFST 8 349 #define MC_CMD_FC_IN_TRC_RX_WRITE_CHANNEL_LEN 4 350 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_OFST 12 351 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_LEN 4 352 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_NUM 2 353 354 /* MC_CMD_FC_IN_SFP msgrequest */ 355 #define MC_CMD_FC_IN_SFP_LEN 28 356 /* MC_CMD_FC_IN_CMD_OFST 0 */ 357 /* MC_CMD_FC_IN_CMD_LEN 4 */ 358 /* Link speed is 100, 1000, 10000, 40000 */ 359 #define MC_CMD_FC_IN_SFP_SPEED_OFST 4 360 #define MC_CMD_FC_IN_SFP_SPEED_LEN 4 361 /* Length of copper cable - zero when not relevant (e.g. if cable is fibre) */ 362 #define MC_CMD_FC_IN_SFP_COPPER_LEN_OFST 8 363 #define MC_CMD_FC_IN_SFP_COPPER_LEN_LEN 4 364 /* Not relevant for cards with QSFP modules. For older cards, true if module is 365 * a dual speed SFP+ module. 366 */ 367 #define MC_CMD_FC_IN_SFP_DUAL_SPEED_OFST 12 368 #define MC_CMD_FC_IN_SFP_DUAL_SPEED_LEN 4 369 /* True if an SFP Module is present (other fields valid when true) */ 370 #define MC_CMD_FC_IN_SFP_PRESENT_OFST 16 371 #define MC_CMD_FC_IN_SFP_PRESENT_LEN 4 372 /* The type of the SFP+ Module. For later cards with QSFP modules, this field 373 * is unused and the type is communicated by other means. 374 */ 375 #define MC_CMD_FC_IN_SFP_TYPE_OFST 20 376 #define MC_CMD_FC_IN_SFP_TYPE_LEN 4 377 /* Capabilities corresponding to 1 bits. */ 378 #define MC_CMD_FC_IN_SFP_CAPS_OFST 24 379 #define MC_CMD_FC_IN_SFP_CAPS_LEN 4 380 381 /* MC_CMD_FC_IN_DDR_TEST msgrequest */ 382 #define MC_CMD_FC_IN_DDR_TEST_LEN 8 383 /* MC_CMD_FC_IN_CMD_OFST 0 */ 384 /* MC_CMD_FC_IN_CMD_LEN 4 */ 385 #define MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 386 #define MC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4 387 #define MC_CMD_FC_IN_DDR_TEST_OP_LBN 0 388 #define MC_CMD_FC_IN_DDR_TEST_OP_WIDTH 8 389 /* enum: DRAM Test Start */ 390 #define MC_CMD_FC_OP_DDR_TEST_START 0x1 391 /* enum: DRAM Test Poll */ 392 #define MC_CMD_FC_OP_DDR_TEST_POLL 0x2 393 394 /* MC_CMD_FC_IN_DDR_TEST_START msgrequest */ 395 #define MC_CMD_FC_IN_DDR_TEST_START_LEN 12 396 /* MC_CMD_FC_IN_CMD_OFST 0 */ 397 /* MC_CMD_FC_IN_CMD_LEN 4 */ 398 /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */ 399 /* MC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4 */ 400 #define MC_CMD_FC_IN_DDR_TEST_START_MASK_OFST 8 401 #define MC_CMD_FC_IN_DDR_TEST_START_MASK_LEN 4 402 #define MC_CMD_FC_IN_DDR_TEST_START_T0_LBN 0 403 #define MC_CMD_FC_IN_DDR_TEST_START_T0_WIDTH 1 404 #define MC_CMD_FC_IN_DDR_TEST_START_T1_LBN 1 405 #define MC_CMD_FC_IN_DDR_TEST_START_T1_WIDTH 1 406 #define MC_CMD_FC_IN_DDR_TEST_START_B0_LBN 2 407 #define MC_CMD_FC_IN_DDR_TEST_START_B0_WIDTH 1 408 #define MC_CMD_FC_IN_DDR_TEST_START_B1_LBN 3 409 #define MC_CMD_FC_IN_DDR_TEST_START_B1_WIDTH 1 410 411 /* MC_CMD_FC_IN_DDR_TEST_POLL msgrequest */ 412 #define MC_CMD_FC_IN_DDR_TEST_POLL_LEN 12 413 #define MC_CMD_FC_IN_DDR_TEST_CMD_OFST 0 414 #define MC_CMD_FC_IN_DDR_TEST_CMD_LEN 4 415 /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */ 416 /* MC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4 */ 417 /* Clear previous test result and prepare for restarting DDR test */ 418 #define MC_CMD_FC_IN_DDR_TEST_POLL_CLEAR_RESULT_FOR_DDR_TEST_OFST 8 419 #define MC_CMD_FC_IN_DDR_TEST_POLL_CLEAR_RESULT_FOR_DDR_TEST_LEN 4 420 421 /* MC_CMD_FC_IN_GET_ASSERT msgrequest */ 422 #define MC_CMD_FC_IN_GET_ASSERT_LEN 4 423 /* MC_CMD_FC_IN_CMD_OFST 0 */ 424 /* MC_CMD_FC_IN_CMD_LEN 4 */ 425 426 /* MC_CMD_FC_IN_FPGA_BUILD msgrequest */ 427 #define MC_CMD_FC_IN_FPGA_BUILD_LEN 8 428 /* MC_CMD_FC_IN_CMD_OFST 0 */ 429 /* MC_CMD_FC_IN_CMD_LEN 4 */ 430 /* FPGA build info operation code */ 431 #define MC_CMD_FC_IN_FPGA_BUILD_OP_OFST 4 432 #define MC_CMD_FC_IN_FPGA_BUILD_OP_LEN 4 433 /* enum: Get the build registers */ 434 #define MC_CMD_FC_IN_FPGA_BUILD_BUILD 0x1 435 /* enum: Get the services registers */ 436 #define MC_CMD_FC_IN_FPGA_BUILD_SERVICES 0x2 437 /* enum: Get the BSP version */ 438 #define MC_CMD_FC_IN_FPGA_BUILD_BSP_VERSION 0x3 439 /* enum: Get build register for V2 (SFA974X) */ 440 #define MC_CMD_FC_IN_FPGA_BUILD_BUILD_V2 0x4 441 /* enum: GEt the services register for V2 (SFA974X) */ 442 #define MC_CMD_FC_IN_FPGA_BUILD_SERVICES_V2 0x5 443 444 /* MC_CMD_FC_IN_READ_MAP msgrequest */ 445 #define MC_CMD_FC_IN_READ_MAP_LEN 8 446 /* MC_CMD_FC_IN_CMD_OFST 0 */ 447 /* MC_CMD_FC_IN_CMD_LEN 4 */ 448 #define MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 449 #define MC_CMD_FC_IN_READ_MAP_HEADER_LEN 4 450 #define MC_CMD_FC_IN_READ_MAP_OP_LBN 0 451 #define MC_CMD_FC_IN_READ_MAP_OP_WIDTH 8 452 /* enum: Get the number of map regions */ 453 #define MC_CMD_FC_OP_READ_MAP_COUNT 0x1 454 /* enum: Get the specified map */ 455 #define MC_CMD_FC_OP_READ_MAP_INDEX 0x2 456 457 /* MC_CMD_FC_IN_READ_MAP_COUNT msgrequest */ 458 #define MC_CMD_FC_IN_READ_MAP_COUNT_LEN 8 459 /* MC_CMD_FC_IN_CMD_OFST 0 */ 460 /* MC_CMD_FC_IN_CMD_LEN 4 */ 461 /* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */ 462 /* MC_CMD_FC_IN_READ_MAP_HEADER_LEN 4 */ 463 464 /* MC_CMD_FC_IN_READ_MAP_INDEX msgrequest */ 465 #define MC_CMD_FC_IN_READ_MAP_INDEX_LEN 12 466 /* MC_CMD_FC_IN_CMD_OFST 0 */ 467 /* MC_CMD_FC_IN_CMD_LEN 4 */ 468 /* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */ 469 /* MC_CMD_FC_IN_READ_MAP_HEADER_LEN 4 */ 470 #define MC_CMD_FC_IN_MAP_INDEX_OFST 8 471 #define MC_CMD_FC_IN_MAP_INDEX_LEN 4 472 473 /* MC_CMD_FC_IN_CAPABILITIES msgrequest */ 474 #define MC_CMD_FC_IN_CAPABILITIES_LEN 4 475 /* MC_CMD_FC_IN_CMD_OFST 0 */ 476 /* MC_CMD_FC_IN_CMD_LEN 4 */ 477 478 /* MC_CMD_FC_IN_GLOBAL_FLAGS msgrequest */ 479 #define MC_CMD_FC_IN_GLOBAL_FLAGS_LEN 8 480 /* MC_CMD_FC_IN_CMD_OFST 0 */ 481 /* MC_CMD_FC_IN_CMD_LEN 4 */ 482 #define MC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_OFST 4 483 #define MC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_LEN 4 484 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_LBN 0 485 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_WIDTH 1 486 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_LBN 1 487 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_WIDTH 1 488 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_LBN 2 489 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_WIDTH 1 490 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_LBN 3 491 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_WIDTH 1 492 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_LBN 4 493 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_WIDTH 1 494 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_LBN 5 495 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_WIDTH 1 496 497 /* MC_CMD_FC_IN_IO_REL msgrequest */ 498 #define MC_CMD_FC_IN_IO_REL_LEN 8 499 /* MC_CMD_FC_IN_CMD_OFST 0 */ 500 /* MC_CMD_FC_IN_CMD_LEN 4 */ 501 #define MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 502 #define MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 503 #define MC_CMD_FC_IN_IO_REL_OP_LBN 0 504 #define MC_CMD_FC_IN_IO_REL_OP_WIDTH 8 505 /* enum: Get the base address that the FC applies to relative commands */ 506 #define MC_CMD_FC_IN_IO_REL_GET_ADDR 0x1 507 /* enum: Read data */ 508 #define MC_CMD_FC_IN_IO_REL_READ32 0x2 509 /* enum: Write data */ 510 #define MC_CMD_FC_IN_IO_REL_WRITE32 0x3 511 #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_LBN 8 512 #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_WIDTH 8 513 /* enum: Application address space */ 514 #define MC_CMD_FC_COMP_TYPE_APP_ADDR_SPACE 0x1 515 /* enum: Flash address space */ 516 #define MC_CMD_FC_COMP_TYPE_FLASH 0x2 517 518 /* MC_CMD_FC_IN_IO_REL_GET_ADDR msgrequest */ 519 #define MC_CMD_FC_IN_IO_REL_GET_ADDR_LEN 8 520 /* MC_CMD_FC_IN_CMD_OFST 0 */ 521 /* MC_CMD_FC_IN_CMD_LEN 4 */ 522 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 523 /* MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 */ 524 525 /* MC_CMD_FC_IN_IO_REL_READ32 msgrequest */ 526 #define MC_CMD_FC_IN_IO_REL_READ32_LEN 20 527 /* MC_CMD_FC_IN_CMD_OFST 0 */ 528 /* MC_CMD_FC_IN_CMD_LEN 4 */ 529 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 530 /* MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 */ 531 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_HI_OFST 8 532 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_HI_LEN 4 533 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_LO_OFST 12 534 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_LO_LEN 4 535 #define MC_CMD_FC_IN_IO_REL_READ32_NUMWORDS_OFST 16 536 #define MC_CMD_FC_IN_IO_REL_READ32_NUMWORDS_LEN 4 537 538 /* MC_CMD_FC_IN_IO_REL_WRITE32 msgrequest */ 539 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMIN 20 540 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMAX 252 541 #define MC_CMD_FC_IN_IO_REL_WRITE32_LEN(num) (16+4*(num)) 542 /* MC_CMD_FC_IN_CMD_OFST 0 */ 543 /* MC_CMD_FC_IN_CMD_LEN 4 */ 544 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 545 /* MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 */ 546 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_HI_OFST 8 547 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_HI_LEN 4 548 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_LO_OFST 12 549 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_LO_LEN 4 550 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_OFST 16 551 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_LEN 4 552 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MINNUM 1 553 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MAXNUM 59 554 555 /* MC_CMD_FC_IN_UHLINK msgrequest */ 556 #define MC_CMD_FC_IN_UHLINK_LEN 8 557 /* MC_CMD_FC_IN_CMD_OFST 0 */ 558 /* MC_CMD_FC_IN_CMD_LEN 4 */ 559 #define MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 560 #define MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 561 #define MC_CMD_FC_IN_UHLINK_OP_LBN 0 562 #define MC_CMD_FC_IN_UHLINK_OP_WIDTH 8 563 /* enum: Get PHY configuration info */ 564 #define MC_CMD_FC_OP_UHLINK_PHY 0x1 565 /* enum: Get MAC configuration info */ 566 #define MC_CMD_FC_OP_UHLINK_MAC 0x2 567 /* enum: Get Rx eye table */ 568 #define MC_CMD_FC_OP_UHLINK_RX_EYE 0x3 569 /* enum: Get Rx eye plot */ 570 #define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT 0x4 571 /* enum: Get Rx eye plot */ 572 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT 0x5 573 /* enum: Retune Rx settings */ 574 #define MC_CMD_FC_OP_UHLINK_RX_TUNE 0x6 575 /* enum: Set loopback mode on fpga port */ 576 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET 0x7 577 /* enum: Get loopback mode config state on fpga port */ 578 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET 0x8 579 #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_LBN 8 580 #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_WIDTH 8 581 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_LBN 16 582 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_WIDTH 8 583 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_LBN 24 584 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_WIDTH 8 585 /* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are 586 * irrelevant. Port number is derived from pci_fn; passed in FC header. 587 */ 588 #define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_DEFAULT 0x0 589 /* enum: Override default port number. Port number determined by fields 590 * PORT_TYPE and PORT_IDX. 591 */ 592 #define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_PORT_OVERRIDE 0x1 593 594 /* MC_CMD_FC_OP_UHLINK_PHY msgrequest */ 595 #define MC_CMD_FC_OP_UHLINK_PHY_LEN 8 596 /* MC_CMD_FC_IN_CMD_OFST 0 */ 597 /* MC_CMD_FC_IN_CMD_LEN 4 */ 598 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 599 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 600 601 /* MC_CMD_FC_OP_UHLINK_MAC msgrequest */ 602 #define MC_CMD_FC_OP_UHLINK_MAC_LEN 8 603 /* MC_CMD_FC_IN_CMD_OFST 0 */ 604 /* MC_CMD_FC_IN_CMD_LEN 4 */ 605 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 606 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 607 608 /* MC_CMD_FC_OP_UHLINK_RX_EYE msgrequest */ 609 #define MC_CMD_FC_OP_UHLINK_RX_EYE_LEN 12 610 /* MC_CMD_FC_IN_CMD_OFST 0 */ 611 /* MC_CMD_FC_IN_CMD_LEN 4 */ 612 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 613 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 614 #define MC_CMD_FC_OP_UHLINK_RX_EYE_INDEX_OFST 8 615 #define MC_CMD_FC_OP_UHLINK_RX_EYE_INDEX_LEN 4 616 #define MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 0x30 /* enum */ 617 618 /* MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT msgrequest */ 619 #define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT_LEN 8 620 /* MC_CMD_FC_IN_CMD_OFST 0 */ 621 /* MC_CMD_FC_IN_CMD_LEN 4 */ 622 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 623 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 624 625 /* MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT msgrequest */ 626 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_LEN 20 627 /* MC_CMD_FC_IN_CMD_OFST 0 */ 628 /* MC_CMD_FC_IN_CMD_LEN 4 */ 629 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 630 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 631 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_DC_GAIN_OFST 8 632 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_DC_GAIN_LEN 4 633 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_EQ_CONTROL_OFST 12 634 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_EQ_CONTROL_LEN 4 635 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_INDEX_OFST 16 636 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_INDEX_LEN 4 637 #define MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 0x1e /* enum */ 638 639 /* MC_CMD_FC_OP_UHLINK_RX_TUNE msgrequest */ 640 #define MC_CMD_FC_OP_UHLINK_RX_TUNE_LEN 8 641 /* MC_CMD_FC_IN_CMD_OFST 0 */ 642 /* MC_CMD_FC_IN_CMD_LEN 4 */ 643 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 644 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 645 646 /* MC_CMD_FC_OP_UHLINK_LOOPBACK_SET msgrequest */ 647 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_LEN 16 648 /* MC_CMD_FC_IN_CMD_OFST 0 */ 649 /* MC_CMD_FC_IN_CMD_LEN 4 */ 650 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 651 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 652 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_TYPE_OFST 8 653 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_TYPE_LEN 4 654 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PCS_SERIAL 0x0 /* enum */ 655 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_PRE_CDR 0x1 /* enum */ 656 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_POST_CDR 0x2 /* enum */ 657 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_STATE_OFST 12 658 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_STATE_LEN 4 659 #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_OFF 0x0 /* enum */ 660 #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_ON 0x1 /* enum */ 661 662 /* MC_CMD_FC_OP_UHLINK_LOOPBACK_GET msgrequest */ 663 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_LEN 12 664 /* MC_CMD_FC_IN_CMD_OFST 0 */ 665 /* MC_CMD_FC_IN_CMD_LEN 4 */ 666 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 667 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 668 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_TYPE_OFST 8 669 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_TYPE_LEN 4 670 671 /* MC_CMD_FC_IN_SET_LINK msgrequest */ 672 #define MC_CMD_FC_IN_SET_LINK_LEN 16 673 /* MC_CMD_FC_IN_CMD_OFST 0 */ 674 /* MC_CMD_FC_IN_CMD_LEN 4 */ 675 /* See MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 676 #define MC_CMD_FC_IN_SET_LINK_MODE_OFST 4 677 #define MC_CMD_FC_IN_SET_LINK_MODE_LEN 4 678 #define MC_CMD_FC_IN_SET_LINK_SPEED_OFST 8 679 #define MC_CMD_FC_IN_SET_LINK_SPEED_LEN 4 680 #define MC_CMD_FC_IN_SET_LINK_FLAGS_OFST 12 681 #define MC_CMD_FC_IN_SET_LINK_FLAGS_LEN 4 682 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_LBN 0 683 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_WIDTH 1 684 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_LBN 1 685 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_WIDTH 1 686 #define MC_CMD_FC_IN_SET_LINK_TXDIS_LBN 2 687 #define MC_CMD_FC_IN_SET_LINK_TXDIS_WIDTH 1 688 689 /* MC_CMD_FC_IN_LICENSE msgrequest */ 690 #define MC_CMD_FC_IN_LICENSE_LEN 8 691 /* MC_CMD_FC_IN_CMD_OFST 0 */ 692 /* MC_CMD_FC_IN_CMD_LEN 4 */ 693 #define MC_CMD_FC_IN_LICENSE_OP_OFST 4 694 #define MC_CMD_FC_IN_LICENSE_OP_LEN 4 695 #define MC_CMD_FC_IN_LICENSE_UPDATE_LICENSE 0x0 /* enum */ 696 #define MC_CMD_FC_IN_LICENSE_GET_KEY_STATS 0x1 /* enum */ 697 698 /* MC_CMD_FC_IN_STARTUP msgrequest */ 699 #define MC_CMD_FC_IN_STARTUP_LEN 40 700 /* MC_CMD_FC_IN_CMD_OFST 0 */ 701 /* MC_CMD_FC_IN_CMD_LEN 4 */ 702 #define MC_CMD_FC_IN_STARTUP_BASE_OFST 4 703 #define MC_CMD_FC_IN_STARTUP_BASE_LEN 4 704 #define MC_CMD_FC_IN_STARTUP_LENGTH_OFST 8 705 #define MC_CMD_FC_IN_STARTUP_LENGTH_LEN 4 706 /* Length of identifier */ 707 #define MC_CMD_FC_IN_STARTUP_IDLENGTH_OFST 12 708 #define MC_CMD_FC_IN_STARTUP_IDLENGTH_LEN 4 709 /* Identifier for AOE FPGA */ 710 #define MC_CMD_FC_IN_STARTUP_ID_OFST 16 711 #define MC_CMD_FC_IN_STARTUP_ID_LEN 1 712 #define MC_CMD_FC_IN_STARTUP_ID_NUM 24 713 714 /* MC_CMD_FC_IN_DMA msgrequest */ 715 #define MC_CMD_FC_IN_DMA_LEN 8 716 /* MC_CMD_FC_IN_CMD_OFST 0 */ 717 /* MC_CMD_FC_IN_CMD_LEN 4 */ 718 #define MC_CMD_FC_IN_DMA_OP_OFST 4 719 #define MC_CMD_FC_IN_DMA_OP_LEN 4 720 #define MC_CMD_FC_IN_DMA_STOP 0x0 /* enum */ 721 #define MC_CMD_FC_IN_DMA_READ 0x1 /* enum */ 722 723 /* MC_CMD_FC_IN_DMA_STOP msgrequest */ 724 #define MC_CMD_FC_IN_DMA_STOP_LEN 12 725 /* MC_CMD_FC_IN_CMD_OFST 0 */ 726 /* MC_CMD_FC_IN_CMD_LEN 4 */ 727 /* MC_CMD_FC_IN_DMA_OP_OFST 4 */ 728 /* MC_CMD_FC_IN_DMA_OP_LEN 4 */ 729 /* FC supplied handle */ 730 #define MC_CMD_FC_IN_DMA_STOP_FC_HANDLE_OFST 8 731 #define MC_CMD_FC_IN_DMA_STOP_FC_HANDLE_LEN 4 732 733 /* MC_CMD_FC_IN_DMA_READ msgrequest */ 734 #define MC_CMD_FC_IN_DMA_READ_LEN 16 735 /* MC_CMD_FC_IN_CMD_OFST 0 */ 736 /* MC_CMD_FC_IN_CMD_LEN 4 */ 737 /* MC_CMD_FC_IN_DMA_OP_OFST 4 */ 738 /* MC_CMD_FC_IN_DMA_OP_LEN 4 */ 739 #define MC_CMD_FC_IN_DMA_READ_OFFSET_OFST 8 740 #define MC_CMD_FC_IN_DMA_READ_OFFSET_LEN 4 741 #define MC_CMD_FC_IN_DMA_READ_LENGTH_OFST 12 742 #define MC_CMD_FC_IN_DMA_READ_LENGTH_LEN 4 743 744 /* MC_CMD_FC_IN_TIMED_READ msgrequest */ 745 #define MC_CMD_FC_IN_TIMED_READ_LEN 8 746 /* MC_CMD_FC_IN_CMD_OFST 0 */ 747 /* MC_CMD_FC_IN_CMD_LEN 4 */ 748 #define MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 749 #define MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 750 #define MC_CMD_FC_IN_TIMED_READ_SET 0x0 /* enum */ 751 #define MC_CMD_FC_IN_TIMED_READ_GET 0x1 /* enum */ 752 #define MC_CMD_FC_IN_TIMED_READ_CLEAR 0x2 /* enum */ 753 754 /* MC_CMD_FC_IN_TIMED_READ_SET msgrequest */ 755 #define MC_CMD_FC_IN_TIMED_READ_SET_LEN 52 756 /* MC_CMD_FC_IN_CMD_OFST 0 */ 757 /* MC_CMD_FC_IN_CMD_LEN 4 */ 758 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 759 /* MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 */ 760 /* Host supplied handle (unique) */ 761 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_OFST 8 762 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_LEN 4 763 /* Address into which to transfer data in host */ 764 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_OFST 12 765 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LEN 8 766 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_OFST 12 767 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_OFST 16 768 /* AOE address from which to transfer data */ 769 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_OFST 20 770 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LEN 8 771 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_OFST 20 772 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_OFST 24 773 /* Length of AOE transfer (total) */ 774 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_OFST 28 775 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_LEN 4 776 /* Length of host transfer (total) */ 777 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_OFST 32 778 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_LEN 4 779 /* Offset back from aoe_address to apply operation to */ 780 #define MC_CMD_FC_IN_TIMED_READ_SET_OFFSET_OFST 36 781 #define MC_CMD_FC_IN_TIMED_READ_SET_OFFSET_LEN 4 782 /* Data to apply at offset */ 783 #define MC_CMD_FC_IN_TIMED_READ_SET_DATA_OFST 40 784 #define MC_CMD_FC_IN_TIMED_READ_SET_DATA_LEN 4 785 #define MC_CMD_FC_IN_TIMED_READ_SET_FLAGS_OFST 44 786 #define MC_CMD_FC_IN_TIMED_READ_SET_FLAGS_LEN 4 787 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_LBN 0 788 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_WIDTH 1 789 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_LBN 1 790 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_WIDTH 1 791 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_LBN 2 792 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_WIDTH 1 793 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_LBN 3 794 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_WIDTH 2 795 #define MC_CMD_FC_IN_TIMED_READ_SET_NONE 0x0 /* enum */ 796 #define MC_CMD_FC_IN_TIMED_READ_SET_READ 0x1 /* enum */ 797 #define MC_CMD_FC_IN_TIMED_READ_SET_WRITE 0x2 /* enum */ 798 #define MC_CMD_FC_IN_TIMED_READ_SET_READWRITE 0x3 /* enum */ 799 /* Period at which reads are performed (100ms units) */ 800 #define MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_OFST 48 801 #define MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_LEN 4 802 803 /* MC_CMD_FC_IN_TIMED_READ_GET msgrequest */ 804 #define MC_CMD_FC_IN_TIMED_READ_GET_LEN 12 805 /* MC_CMD_FC_IN_CMD_OFST 0 */ 806 /* MC_CMD_FC_IN_CMD_LEN 4 */ 807 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 808 /* MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 */ 809 /* FC supplied handle */ 810 #define MC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_OFST 8 811 #define MC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_LEN 4 812 813 /* MC_CMD_FC_IN_TIMED_READ_CLEAR msgrequest */ 814 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_LEN 12 815 /* MC_CMD_FC_IN_CMD_OFST 0 */ 816 /* MC_CMD_FC_IN_CMD_LEN 4 */ 817 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 818 /* MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 */ 819 /* FC supplied handle */ 820 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_OFST 8 821 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_LEN 4 822 823 /* MC_CMD_FC_IN_LOG msgrequest */ 824 #define MC_CMD_FC_IN_LOG_LEN 8 825 /* MC_CMD_FC_IN_CMD_OFST 0 */ 826 /* MC_CMD_FC_IN_CMD_LEN 4 */ 827 #define MC_CMD_FC_IN_LOG_OP_OFST 4 828 #define MC_CMD_FC_IN_LOG_OP_LEN 4 829 #define MC_CMD_FC_IN_LOG_ADDR_RANGE 0x0 /* enum */ 830 #define MC_CMD_FC_IN_LOG_JTAG_UART 0x1 /* enum */ 831 832 /* MC_CMD_FC_IN_LOG_ADDR_RANGE msgrequest */ 833 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LEN 20 834 /* MC_CMD_FC_IN_CMD_OFST 0 */ 835 /* MC_CMD_FC_IN_CMD_LEN 4 */ 836 /* MC_CMD_FC_IN_LOG_OP_OFST 4 */ 837 /* MC_CMD_FC_IN_LOG_OP_LEN 4 */ 838 /* Partition offset into flash */ 839 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_OFST 8 840 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_LEN 4 841 /* Partition length */ 842 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_OFST 12 843 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_LEN 4 844 /* Partition erase size */ 845 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_OFST 16 846 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_LEN 4 847 848 /* MC_CMD_FC_IN_LOG_JTAG_UART msgrequest */ 849 #define MC_CMD_FC_IN_LOG_JTAG_UART_LEN 12 850 /* MC_CMD_FC_IN_CMD_OFST 0 */ 851 /* MC_CMD_FC_IN_CMD_LEN 4 */ 852 /* MC_CMD_FC_IN_LOG_OP_OFST 4 */ 853 /* MC_CMD_FC_IN_LOG_OP_LEN 4 */ 854 /* Enable/disable printing to JTAG UART */ 855 #define MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_OFST 8 856 #define MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_LEN 4 857 858 /* MC_CMD_FC_IN_CLOCK msgrequest: Perform a clock operation */ 859 #define MC_CMD_FC_IN_CLOCK_LEN 12 860 /* MC_CMD_FC_IN_CMD_OFST 0 */ 861 /* MC_CMD_FC_IN_CMD_LEN 4 */ 862 #define MC_CMD_FC_IN_CLOCK_OP_OFST 4 863 #define MC_CMD_FC_IN_CLOCK_OP_LEN 4 864 #define MC_CMD_FC_IN_CLOCK_GET_TIME 0x0 /* enum */ 865 #define MC_CMD_FC_IN_CLOCK_SET_TIME 0x1 /* enum */ 866 #define MC_CMD_FC_IN_CLOCK_ID_OFST 8 867 #define MC_CMD_FC_IN_CLOCK_ID_LEN 4 868 #define MC_CMD_FC_IN_CLOCK_STATS 0x0 /* enum */ 869 #define MC_CMD_FC_IN_CLOCK_MAC 0x1 /* enum */ 870 871 /* MC_CMD_FC_IN_CLOCK_GET_TIME msgrequest: Retrieve the clock value of the 872 * specified clock 873 */ 874 #define MC_CMD_FC_IN_CLOCK_GET_TIME_LEN 12 875 /* MC_CMD_FC_IN_CMD_OFST 0 */ 876 /* MC_CMD_FC_IN_CMD_LEN 4 */ 877 /* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */ 878 /* MC_CMD_FC_IN_CLOCK_OP_LEN 4 */ 879 /* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */ 880 /* MC_CMD_FC_IN_CLOCK_ID_LEN 4 */ 881 882 /* MC_CMD_FC_IN_CLOCK_SET_TIME msgrequest: Set the clock value of the specified 883 * clock 884 */ 885 #define MC_CMD_FC_IN_CLOCK_SET_TIME_LEN 24 886 /* MC_CMD_FC_IN_CMD_OFST 0 */ 887 /* MC_CMD_FC_IN_CMD_LEN 4 */ 888 /* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */ 889 /* MC_CMD_FC_IN_CLOCK_OP_LEN 4 */ 890 /* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */ 891 /* MC_CMD_FC_IN_CLOCK_ID_LEN 4 */ 892 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_OFST 12 893 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LEN 8 894 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_OFST 12 895 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_OFST 16 896 #define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_OFST 20 897 #define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_LEN 4 898 899 /* MC_CMD_FC_IN_DDR msgrequest */ 900 #define MC_CMD_FC_IN_DDR_LEN 12 901 /* MC_CMD_FC_IN_CMD_OFST 0 */ 902 /* MC_CMD_FC_IN_CMD_LEN 4 */ 903 #define MC_CMD_FC_IN_DDR_OP_OFST 4 904 #define MC_CMD_FC_IN_DDR_OP_LEN 4 905 #define MC_CMD_FC_IN_DDR_SET_SPD 0x0 /* enum */ 906 #define MC_CMD_FC_IN_DDR_GET_STATUS 0x1 /* enum */ 907 #define MC_CMD_FC_IN_DDR_SET_INFO 0x2 /* enum */ 908 #define MC_CMD_FC_IN_DDR_BANK_OFST 8 909 #define MC_CMD_FC_IN_DDR_BANK_LEN 4 910 #define MC_CMD_FC_IN_DDR_BANK_B0 0x0 /* enum */ 911 #define MC_CMD_FC_IN_DDR_BANK_B1 0x1 /* enum */ 912 #define MC_CMD_FC_IN_DDR_BANK_T0 0x2 /* enum */ 913 #define MC_CMD_FC_IN_DDR_BANK_T1 0x3 /* enum */ 914 #define MC_CMD_FC_IN_DDR_NUM_BANKS 0x4 /* enum */ 915 916 /* MC_CMD_FC_IN_DDR_SET_SPD msgrequest */ 917 #define MC_CMD_FC_IN_DDR_SET_SPD_LEN 148 918 /* MC_CMD_FC_IN_CMD_OFST 0 */ 919 /* MC_CMD_FC_IN_CMD_LEN 4 */ 920 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ 921 /* MC_CMD_FC_IN_DDR_OP_LEN 4 */ 922 /* Affected bank */ 923 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ 924 /* MC_CMD_FC_IN_DDR_BANK_LEN 4 */ 925 /* Flags */ 926 #define MC_CMD_FC_IN_DDR_FLAGS_OFST 12 927 #define MC_CMD_FC_IN_DDR_FLAGS_LEN 4 928 #define MC_CMD_FC_IN_DDR_SET_SPD_ACTIVE 0x1 /* enum */ 929 /* 128-byte page of serial presence detect data read from module's EEPROM */ 930 #define MC_CMD_FC_IN_DDR_SPD_OFST 16 931 #define MC_CMD_FC_IN_DDR_SPD_LEN 1 932 #define MC_CMD_FC_IN_DDR_SPD_NUM 128 933 /* Page index of the spd data copied into MC_CMD_FC_IN_DDR_SPD */ 934 #define MC_CMD_FC_IN_DDR_SPD_PAGE_ID_OFST 144 935 #define MC_CMD_FC_IN_DDR_SPD_PAGE_ID_LEN 4 936 937 /* MC_CMD_FC_IN_DDR_SET_INFO msgrequest */ 938 #define MC_CMD_FC_IN_DDR_SET_INFO_LEN 16 939 /* MC_CMD_FC_IN_CMD_OFST 0 */ 940 /* MC_CMD_FC_IN_CMD_LEN 4 */ 941 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ 942 /* MC_CMD_FC_IN_DDR_OP_LEN 4 */ 943 /* Affected bank */ 944 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ 945 /* MC_CMD_FC_IN_DDR_BANK_LEN 4 */ 946 /* Size of DDR */ 947 #define MC_CMD_FC_IN_DDR_SIZE_OFST 12 948 #define MC_CMD_FC_IN_DDR_SIZE_LEN 4 949 950 /* MC_CMD_FC_IN_DDR_GET_STATUS msgrequest */ 951 #define MC_CMD_FC_IN_DDR_GET_STATUS_LEN 12 952 /* MC_CMD_FC_IN_CMD_OFST 0 */ 953 /* MC_CMD_FC_IN_CMD_LEN 4 */ 954 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ 955 /* MC_CMD_FC_IN_DDR_OP_LEN 4 */ 956 /* Affected bank */ 957 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ 958 /* MC_CMD_FC_IN_DDR_BANK_LEN 4 */ 959 960 /* MC_CMD_FC_IN_TIMESTAMP msgrequest */ 961 #define MC_CMD_FC_IN_TIMESTAMP_LEN 8 962 /* MC_CMD_FC_IN_CMD_OFST 0 */ 963 /* MC_CMD_FC_IN_CMD_LEN 4 */ 964 /* FC timestamp operation code */ 965 #define MC_CMD_FC_IN_TIMESTAMP_OP_OFST 4 966 #define MC_CMD_FC_IN_TIMESTAMP_OP_LEN 4 967 /* enum: Read transmit timestamp(s) */ 968 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT 0x0 969 /* enum: Read snapshot timestamps */ 970 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT 0x1 971 /* enum: Clear all transmit timestamps */ 972 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT 0x2 973 974 /* MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT msgrequest */ 975 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LEN 28 976 /* MC_CMD_FC_IN_CMD_OFST 0 */ 977 /* MC_CMD_FC_IN_CMD_LEN 4 */ 978 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_OFST 4 979 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_LEN 4 980 /* Control filtering of the returned timestamp and sequence number specified 981 * here 982 */ 983 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_OFST 8 984 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_LEN 4 985 /* enum: Return most recent timestamp. No filtering */ 986 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LATEST 0x0 987 /* enum: Match timestamp against the PTP clock ID, port number and sequence 988 * number specified 989 */ 990 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_MATCH 0x1 991 /* Clock identity of PTP packet for which timestamp required */ 992 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_OFST 12 993 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LEN 8 994 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_OFST 12 995 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_OFST 16 996 /* Port number of PTP packet for which timestamp required */ 997 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_OFST 20 998 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_LEN 4 999 /* Sequence number of PTP packet for which timestamp required */ 1000 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_OFST 24 1001 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_LEN 4 1002 1003 /* MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT msgrequest */ 1004 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_LEN 8 1005 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1006 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1007 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_OP_OFST 4 1008 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_OP_LEN 4 1009 1010 /* MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT msgrequest */ 1011 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_LEN 8 1012 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1013 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1014 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_OP_OFST 4 1015 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_OP_LEN 4 1016 1017 /* MC_CMD_FC_IN_SPI msgrequest */ 1018 #define MC_CMD_FC_IN_SPI_LEN 8 1019 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1020 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1021 /* Basic commands for SPI Flash. */ 1022 #define MC_CMD_FC_IN_SPI_OP_OFST 4 1023 #define MC_CMD_FC_IN_SPI_OP_LEN 4 1024 /* enum: SPI Flash read */ 1025 #define MC_CMD_FC_IN_SPI_READ 0x0 1026 /* enum: SPI Flash write */ 1027 #define MC_CMD_FC_IN_SPI_WRITE 0x1 1028 /* enum: SPI Flash erase */ 1029 #define MC_CMD_FC_IN_SPI_ERASE 0x2 1030 1031 /* MC_CMD_FC_IN_SPI_READ msgrequest */ 1032 #define MC_CMD_FC_IN_SPI_READ_LEN 16 1033 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1034 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1035 #define MC_CMD_FC_IN_SPI_READ_OP_OFST 4 1036 #define MC_CMD_FC_IN_SPI_READ_OP_LEN 4 1037 #define MC_CMD_FC_IN_SPI_READ_ADDR_OFST 8 1038 #define MC_CMD_FC_IN_SPI_READ_ADDR_LEN 4 1039 #define MC_CMD_FC_IN_SPI_READ_NUMBYTES_OFST 12 1040 #define MC_CMD_FC_IN_SPI_READ_NUMBYTES_LEN 4 1041 1042 /* MC_CMD_FC_IN_SPI_WRITE msgrequest */ 1043 #define MC_CMD_FC_IN_SPI_WRITE_LENMIN 16 1044 #define MC_CMD_FC_IN_SPI_WRITE_LENMAX 252 1045 #define MC_CMD_FC_IN_SPI_WRITE_LEN(num) (12+4*(num)) 1046 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1047 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1048 #define MC_CMD_FC_IN_SPI_WRITE_OP_OFST 4 1049 #define MC_CMD_FC_IN_SPI_WRITE_OP_LEN 4 1050 #define MC_CMD_FC_IN_SPI_WRITE_ADDR_OFST 8 1051 #define MC_CMD_FC_IN_SPI_WRITE_ADDR_LEN 4 1052 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_OFST 12 1053 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_LEN 4 1054 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MINNUM 1 1055 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MAXNUM 60 1056 1057 /* MC_CMD_FC_IN_SPI_ERASE msgrequest */ 1058 #define MC_CMD_FC_IN_SPI_ERASE_LEN 16 1059 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1060 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1061 #define MC_CMD_FC_IN_SPI_ERASE_OP_OFST 4 1062 #define MC_CMD_FC_IN_SPI_ERASE_OP_LEN 4 1063 #define MC_CMD_FC_IN_SPI_ERASE_ADDR_OFST 8 1064 #define MC_CMD_FC_IN_SPI_ERASE_ADDR_LEN 4 1065 #define MC_CMD_FC_IN_SPI_ERASE_NUMBYTES_OFST 12 1066 #define MC_CMD_FC_IN_SPI_ERASE_NUMBYTES_LEN 4 1067 1068 /* MC_CMD_FC_IN_DIAG msgrequest */ 1069 #define MC_CMD_FC_IN_DIAG_LEN 8 1070 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1071 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1072 /* Operation code indicating component type */ 1073 #define MC_CMD_FC_IN_DIAG_OP_OFST 4 1074 #define MC_CMD_FC_IN_DIAG_OP_LEN 4 1075 /* enum: Power noise generator. */ 1076 #define MC_CMD_FC_IN_DIAG_POWER_NOISE 0x0 1077 /* enum: DDR soak test component. */ 1078 #define MC_CMD_FC_IN_DIAG_DDR_SOAK 0x1 1079 /* enum: Diagnostics datapath control component. */ 1080 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL 0x2 1081 1082 /* MC_CMD_FC_IN_DIAG_POWER_NOISE msgrequest */ 1083 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_LEN 12 1084 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1085 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1086 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_OP_OFST 4 1087 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_OP_LEN 4 1088 /* Sub-opcode describing the operation to be carried out */ 1089 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_OFST 8 1090 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_LEN 4 1091 /* enum: Read the configuration (the 32-bit values in each of the clock enable 1092 * count and toggle count registers) 1093 */ 1094 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG 0x0 1095 /* enum: Write a new configuration to the clock enable count and toggle count 1096 * registers 1097 */ 1098 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG 0x1 1099 1100 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG msgrequest */ 1101 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_LEN 12 1102 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1103 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1104 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_OP_OFST 4 1105 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_OP_LEN 4 1106 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_SUB_OP_OFST 8 1107 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_SUB_OP_LEN 4 1108 1109 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG msgrequest */ 1110 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 20 1111 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1112 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1113 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_OFST 4 1114 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_LEN 4 1115 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_OFST 8 1116 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_LEN 4 1117 /* The 32-bit value to be written to the toggle count register */ 1118 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_OFST 12 1119 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_LEN 4 1120 /* The 32-bit value to be written to the clock enable count register */ 1121 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_OFST 16 1122 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_LEN 4 1123 1124 /* MC_CMD_FC_IN_DIAG_DDR_SOAK msgrequest */ 1125 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_LEN 12 1126 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1127 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1128 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_OP_OFST 4 1129 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_OP_LEN 4 1130 /* Sub-opcode describing the operation to be carried out */ 1131 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_OFST 8 1132 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_LEN 4 1133 /* enum: Starts DDR soak test on selected banks */ 1134 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START 0x0 1135 /* enum: Read status of DDR soak test */ 1136 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT 0x1 1137 /* enum: Stop test */ 1138 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP 0x2 1139 /* enum: Set or clear bit that triggers fake errors. These cause subsequent 1140 * tests to fail until the bit is cleared. 1141 */ 1142 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR 0x3 1143 1144 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_START msgrequest */ 1145 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_LEN 24 1146 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1147 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1148 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_OFST 4 1149 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_LEN 4 1150 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_OFST 8 1151 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_LEN 4 1152 /* Mask of DDR banks to be tested */ 1153 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_OFST 12 1154 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_LEN 4 1155 /* Pattern to use in the soak test */ 1156 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_OFST 16 1157 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_LEN 4 1158 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ZEROS 0x0 /* enum */ 1159 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONES 0x1 /* enum */ 1160 /* Either multiple automatic tests until a STOP command is issued, or one 1161 * single test 1162 */ 1163 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_OFST 20 1164 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_LEN 4 1165 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONGOING_TEST 0x0 /* enum */ 1166 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SINGLE_TEST 0x1 /* enum */ 1167 1168 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT msgrequest */ 1169 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_LEN 16 1170 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1171 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1172 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_OFST 4 1173 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_LEN 4 1174 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_OFST 8 1175 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_LEN 4 1176 /* DDR bank to read status from */ 1177 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_OFST 12 1178 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_LEN 4 1179 #define MC_CMD_FC_DDR_BANK0 0x0 /* enum */ 1180 #define MC_CMD_FC_DDR_BANK1 0x1 /* enum */ 1181 #define MC_CMD_FC_DDR_BANK2 0x2 /* enum */ 1182 #define MC_CMD_FC_DDR_BANK3 0x3 /* enum */ 1183 #define MC_CMD_FC_DDR_AOEMEM_MAX_BANKS 0x4 /* enum */ 1184 1185 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP msgrequest */ 1186 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_LEN 16 1187 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1188 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1189 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_OFST 4 1190 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_LEN 4 1191 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_OFST 8 1192 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_LEN 4 1193 /* Mask of DDR banks to be tested */ 1194 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_OFST 12 1195 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_LEN 4 1196 1197 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR msgrequest */ 1198 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_LEN 20 1199 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1200 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1201 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_OFST 4 1202 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_LEN 4 1203 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_OFST 8 1204 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_LEN 4 1205 /* Mask of DDR banks to set/clear error flag on */ 1206 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_OFST 12 1207 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_LEN 4 1208 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_OFST 16 1209 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_LEN 4 1210 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_CLEAR 0x0 /* enum */ 1211 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SET 0x1 /* enum */ 1212 1213 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL msgrequest */ 1214 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_LEN 12 1215 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1216 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1217 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_OFST 4 1218 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_LEN 4 1219 /* Sub-opcode describing the operation to be carried out */ 1220 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_OFST 8 1221 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_LEN 4 1222 /* enum: Set a known datapath configuration */ 1223 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE 0x0 1224 /* enum: Apply raw config to datapath control registers */ 1225 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG 0x1 1226 1227 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE msgrequest */ 1228 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_LEN 16 1229 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1230 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1231 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_OFST 4 1232 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_LEN 4 1233 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_OFST 8 1234 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_LEN 4 1235 /* Datapath configuration identifier */ 1236 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_OFST 12 1237 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_LEN 4 1238 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_PASSTHROUGH 0x0 /* enum */ 1239 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SNAKE 0x1 /* enum */ 1240 1241 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG msgrequest */ 1242 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 24 1243 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1244 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1245 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_OFST 4 1246 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_LEN 4 1247 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_OFST 8 1248 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_LEN 4 1249 /* Value to write into control register 1 */ 1250 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_OFST 12 1251 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_LEN 4 1252 /* Value to write into control register 2 */ 1253 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_OFST 16 1254 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_LEN 4 1255 /* Value to write into control register 3 */ 1256 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_OFST 20 1257 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_LEN 4 1258 1259 /* MC_CMD_FC_OUT msgresponse */ 1260 #define MC_CMD_FC_OUT_LEN 0 1261 1262 /* MC_CMD_FC_OUT_NULL msgresponse */ 1263 #define MC_CMD_FC_OUT_NULL_LEN 0 1264 1265 /* MC_CMD_FC_OUT_READ32 msgresponse */ 1266 #define MC_CMD_FC_OUT_READ32_LENMIN 4 1267 #define MC_CMD_FC_OUT_READ32_LENMAX 252 1268 #define MC_CMD_FC_OUT_READ32_LEN(num) (0+4*(num)) 1269 #define MC_CMD_FC_OUT_READ32_BUFFER_OFST 0 1270 #define MC_CMD_FC_OUT_READ32_BUFFER_LEN 4 1271 #define MC_CMD_FC_OUT_READ32_BUFFER_MINNUM 1 1272 #define MC_CMD_FC_OUT_READ32_BUFFER_MAXNUM 63 1273 1274 /* MC_CMD_FC_OUT_WRITE32 msgresponse */ 1275 #define MC_CMD_FC_OUT_WRITE32_LEN 0 1276 1277 /* MC_CMD_FC_OUT_TRC_READ msgresponse */ 1278 #define MC_CMD_FC_OUT_TRC_READ_LEN 16 1279 #define MC_CMD_FC_OUT_TRC_READ_DATA_OFST 0 1280 #define MC_CMD_FC_OUT_TRC_READ_DATA_LEN 4 1281 #define MC_CMD_FC_OUT_TRC_READ_DATA_NUM 4 1282 1283 /* MC_CMD_FC_OUT_TRC_WRITE msgresponse */ 1284 #define MC_CMD_FC_OUT_TRC_WRITE_LEN 0 1285 1286 /* MC_CMD_FC_OUT_GET_VERSION msgresponse */ 1287 #define MC_CMD_FC_OUT_GET_VERSION_LEN 12 1288 #define MC_CMD_FC_OUT_GET_VERSION_FIRMWARE_OFST 0 1289 #define MC_CMD_FC_OUT_GET_VERSION_FIRMWARE_LEN 4 1290 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_OFST 4 1291 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LEN 8 1292 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_OFST 4 1293 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_OFST 8 1294 1295 /* MC_CMD_FC_OUT_TRC_RX_READ msgresponse */ 1296 #define MC_CMD_FC_OUT_TRC_RX_READ_LEN 8 1297 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_OFST 0 1298 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_LEN 4 1299 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_NUM 2 1300 1301 /* MC_CMD_FC_OUT_TRC_RX_WRITE msgresponse */ 1302 #define MC_CMD_FC_OUT_TRC_RX_WRITE_LEN 0 1303 1304 /* MC_CMD_FC_OUT_MAC_RECONFIGURE msgresponse */ 1305 #define MC_CMD_FC_OUT_MAC_RECONFIGURE_LEN 0 1306 1307 /* MC_CMD_FC_OUT_MAC_SET_LINK msgresponse */ 1308 #define MC_CMD_FC_OUT_MAC_SET_LINK_LEN 0 1309 1310 /* MC_CMD_FC_OUT_MAC_READ_STATUS msgresponse */ 1311 #define MC_CMD_FC_OUT_MAC_READ_STATUS_LEN 4 1312 #define MC_CMD_FC_OUT_MAC_READ_STATUS_STATUS_OFST 0 1313 #define MC_CMD_FC_OUT_MAC_READ_STATUS_STATUS_LEN 4 1314 1315 /* MC_CMD_FC_OUT_MAC_GET_RX_STATS msgresponse */ 1316 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_RX_NSTATS))+1))>>3) 1317 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_OFST 0 1318 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LEN 8 1319 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_OFST 0 1320 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_OFST 4 1321 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_RX_NSTATS 1322 #define MC_CMD_FC_MAC_RX_STATS_OCTETS 0x0 /* enum */ 1323 #define MC_CMD_FC_MAC_RX_OCTETS_OK 0x1 /* enum */ 1324 #define MC_CMD_FC_MAC_RX_ALIGNMENT_ERRORS 0x2 /* enum */ 1325 #define MC_CMD_FC_MAC_RX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ 1326 #define MC_CMD_FC_MAC_RX_FRAMES_OK 0x4 /* enum */ 1327 #define MC_CMD_FC_MAC_RX_CRC_ERRORS 0x5 /* enum */ 1328 #define MC_CMD_FC_MAC_RX_VLAN_OK 0x6 /* enum */ 1329 #define MC_CMD_FC_MAC_RX_ERRORS 0x7 /* enum */ 1330 #define MC_CMD_FC_MAC_RX_UCAST_PKTS 0x8 /* enum */ 1331 #define MC_CMD_FC_MAC_RX_MULTICAST_PKTS 0x9 /* enum */ 1332 #define MC_CMD_FC_MAC_RX_BROADCAST_PKTS 0xa /* enum */ 1333 #define MC_CMD_FC_MAC_RX_STATS_DROP_EVENTS 0xb /* enum */ 1334 #define MC_CMD_FC_MAC_RX_STATS_PKTS 0xc /* enum */ 1335 #define MC_CMD_FC_MAC_RX_STATS_UNDERSIZE_PKTS 0xd /* enum */ 1336 #define MC_CMD_FC_MAC_RX_STATS_PKTS_64 0xe /* enum */ 1337 #define MC_CMD_FC_MAC_RX_STATS_PKTS_65_127 0xf /* enum */ 1338 #define MC_CMD_FC_MAC_RX_STATS_PKTS_128_255 0x10 /* enum */ 1339 #define MC_CMD_FC_MAC_RX_STATS_PKTS_256_511 0x11 /* enum */ 1340 #define MC_CMD_FC_MAC_RX_STATS_PKTS_512_1023 0x12 /* enum */ 1341 #define MC_CMD_FC_MAC_RX_STATS_PKTS_1024_1518 0x13 /* enum */ 1342 #define MC_CMD_FC_MAC_RX_STATS_PKTS_1519_MAX 0x14 /* enum */ 1343 #define MC_CMD_FC_MAC_RX_STATS_OVERSIZE_PKTS 0x15 /* enum */ 1344 #define MC_CMD_FC_MAC_RX_STATS_JABBERS 0x16 /* enum */ 1345 #define MC_CMD_FC_MAC_RX_STATS_FRAGMENTS 0x17 /* enum */ 1346 #define MC_CMD_FC_MAC_RX_MAC_CONTROL_FRAMES 0x18 /* enum */ 1347 /* enum: (Last entry) */ 1348 #define MC_CMD_FC_MAC_RX_NSTATS 0x19 1349 1350 /* MC_CMD_FC_OUT_MAC_GET_TX_STATS msgresponse */ 1351 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_TX_NSTATS))+1))>>3) 1352 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_OFST 0 1353 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LEN 8 1354 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_OFST 0 1355 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_OFST 4 1356 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_TX_NSTATS 1357 #define MC_CMD_FC_MAC_TX_STATS_OCTETS 0x0 /* enum */ 1358 #define MC_CMD_FC_MAC_TX_OCTETS_OK 0x1 /* enum */ 1359 #define MC_CMD_FC_MAC_TX_ALIGNMENT_ERRORS 0x2 /* enum */ 1360 #define MC_CMD_FC_MAC_TX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ 1361 #define MC_CMD_FC_MAC_TX_FRAMES_OK 0x4 /* enum */ 1362 #define MC_CMD_FC_MAC_TX_CRC_ERRORS 0x5 /* enum */ 1363 #define MC_CMD_FC_MAC_TX_VLAN_OK 0x6 /* enum */ 1364 #define MC_CMD_FC_MAC_TX_ERRORS 0x7 /* enum */ 1365 #define MC_CMD_FC_MAC_TX_UCAST_PKTS 0x8 /* enum */ 1366 #define MC_CMD_FC_MAC_TX_MULTICAST_PKTS 0x9 /* enum */ 1367 #define MC_CMD_FC_MAC_TX_BROADCAST_PKTS 0xa /* enum */ 1368 #define MC_CMD_FC_MAC_TX_STATS_DROP_EVENTS 0xb /* enum */ 1369 #define MC_CMD_FC_MAC_TX_STATS_PKTS 0xc /* enum */ 1370 #define MC_CMD_FC_MAC_TX_STATS_UNDERSIZE_PKTS 0xd /* enum */ 1371 #define MC_CMD_FC_MAC_TX_STATS_PKTS_64 0xe /* enum */ 1372 #define MC_CMD_FC_MAC_TX_STATS_PKTS_65_127 0xf /* enum */ 1373 #define MC_CMD_FC_MAC_TX_STATS_PKTS_128_255 0x10 /* enum */ 1374 #define MC_CMD_FC_MAC_TX_STATS_PKTS_256_511 0x11 /* enum */ 1375 #define MC_CMD_FC_MAC_TX_STATS_PKTS_512_1023 0x12 /* enum */ 1376 #define MC_CMD_FC_MAC_TX_STATS_PKTS_1024_1518 0x13 /* enum */ 1377 #define MC_CMD_FC_MAC_TX_STATS_PKTS_1519_TX_MTU 0x14 /* enum */ 1378 #define MC_CMD_FC_MAC_TX_MAC_CONTROL_FRAMES 0x15 /* enum */ 1379 /* enum: (Last entry) */ 1380 #define MC_CMD_FC_MAC_TX_NSTATS 0x16 1381 1382 /* MC_CMD_FC_OUT_MAC_GET_STATS msgresponse */ 1383 #define MC_CMD_FC_OUT_MAC_GET_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_NSTATS_PER_BLOCK))+1))>>3) 1384 /* MAC Statistics */ 1385 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_OFST 0 1386 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LEN 8 1387 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_OFST 0 1388 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_OFST 4 1389 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_NUM MC_CMD_FC_MAC_NSTATS_PER_BLOCK 1390 1391 /* MC_CMD_FC_OUT_MAC msgresponse */ 1392 #define MC_CMD_FC_OUT_MAC_LEN 0 1393 1394 /* MC_CMD_FC_OUT_SFP msgresponse */ 1395 #define MC_CMD_FC_OUT_SFP_LEN 0 1396 1397 /* MC_CMD_FC_OUT_DDR_TEST_START msgresponse */ 1398 #define MC_CMD_FC_OUT_DDR_TEST_START_LEN 0 1399 1400 /* MC_CMD_FC_OUT_DDR_TEST_POLL msgresponse */ 1401 #define MC_CMD_FC_OUT_DDR_TEST_POLL_LEN 8 1402 #define MC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_OFST 0 1403 #define MC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_LEN 4 1404 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_LBN 0 1405 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_WIDTH 8 1406 /* enum: Test not yet initiated */ 1407 #define MC_CMD_FC_OP_DDR_TEST_NONE 0x0 1408 /* enum: Test is in progress */ 1409 #define MC_CMD_FC_OP_DDR_TEST_INPROGRESS 0x1 1410 /* enum: Timed completed */ 1411 #define MC_CMD_FC_OP_DDR_TEST_SUCCESS 0x2 1412 /* enum: Test did not complete in specified time */ 1413 #define MC_CMD_FC_OP_DDR_TEST_TIMER_EXPIRED 0x3 1414 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_LBN 11 1415 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_WIDTH 1 1416 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_LBN 10 1417 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_WIDTH 1 1418 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_LBN 9 1419 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_WIDTH 1 1420 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_LBN 8 1421 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_WIDTH 1 1422 /* Test result from FPGA */ 1423 #define MC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_OFST 4 1424 #define MC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_LEN 4 1425 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_LBN 31 1426 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_WIDTH 1 1427 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_LBN 30 1428 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_WIDTH 1 1429 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_LBN 29 1430 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_WIDTH 1 1431 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_LBN 28 1432 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_WIDTH 1 1433 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_LBN 15 1434 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_WIDTH 5 1435 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_LBN 10 1436 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_WIDTH 5 1437 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_LBN 5 1438 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_WIDTH 5 1439 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_LBN 0 1440 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_WIDTH 5 1441 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_COMPLETE 0x0 /* enum */ 1442 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_FAIL 0x1 /* enum */ 1443 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_PASS 0x2 /* enum */ 1444 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_FAIL 0x3 /* enum */ 1445 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_SUCCESS 0x4 /* enum */ 1446 1447 /* MC_CMD_FC_OUT_DDR_TEST msgresponse */ 1448 #define MC_CMD_FC_OUT_DDR_TEST_LEN 0 1449 1450 /* MC_CMD_FC_OUT_GET_ASSERT msgresponse */ 1451 #define MC_CMD_FC_OUT_GET_ASSERT_LEN 144 1452 /* Assertion status flag. */ 1453 #define MC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_OFST 0 1454 #define MC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_LEN 4 1455 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_LBN 8 1456 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_WIDTH 8 1457 /* enum: No crash data available */ 1458 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0 1459 /* enum: New crash data available */ 1460 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1 1461 /* enum: Crash data has been sent */ 1462 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2 1463 #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_LBN 0 1464 #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_WIDTH 8 1465 /* enum: No crash has been recorded. */ 1466 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0 1467 /* enum: Crash due to exception. */ 1468 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1 1469 /* enum: Crash due to assertion. */ 1470 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2 1471 /* Failing PC value */ 1472 #define MC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_OFST 4 1473 #define MC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_LEN 4 1474 /* Saved GP regs */ 1475 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_OFST 8 1476 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_LEN 4 1477 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_NUM 31 1478 /* Exception Type */ 1479 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_OFST 132 1480 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_LEN 4 1481 /* Instruction at which exception occurred */ 1482 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_OFST 136 1483 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_LEN 4 1484 /* BAD Address that triggered address-based exception */ 1485 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_OFST 140 1486 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_LEN 4 1487 1488 /* MC_CMD_FC_OUT_FPGA_BUILD msgresponse */ 1489 #define MC_CMD_FC_OUT_FPGA_BUILD_LEN 32 1490 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_OFST 0 1491 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_LEN 4 1492 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_LBN 31 1493 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_WIDTH 1 1494 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_LBN 30 1495 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_WIDTH 1 1496 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_LBN 16 1497 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_WIDTH 14 1498 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_LBN 12 1499 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_WIDTH 4 1500 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_LBN 4 1501 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_WIDTH 8 1502 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_LBN 0 1503 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_WIDTH 4 1504 /* Build timestamp (seconds since epoch) */ 1505 #define MC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_OFST 4 1506 #define MC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_LEN 4 1507 #define MC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_OFST 8 1508 #define MC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_LEN 4 1509 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_LBN 0 1510 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_WIDTH 8 1511 #define MC_CMD_FC_FPGA_TYPE_A7 0xa7 /* enum */ 1512 #define MC_CMD_FC_FPGA_TYPE_A5 0xa5 /* enum */ 1513 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_LBN 8 1514 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_WIDTH 10 1515 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_LBN 18 1516 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_WIDTH 1 1517 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_LBN 19 1518 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_WIDTH 1 1519 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_LBN 20 1520 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_WIDTH 1 1521 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_LBN 21 1522 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_WIDTH 1 1523 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_LBN 22 1524 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_WIDTH 1 1525 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_LBN 23 1526 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_WIDTH 1 1527 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_LBN 24 1528 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_WIDTH 1 1529 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_LBN 25 1530 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_WIDTH 1 1531 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_LBN 26 1532 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_WIDTH 1 1533 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_LBN 27 1534 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_WIDTH 1 1535 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_LBN 28 1536 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_WIDTH 1 1537 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_LBN 29 1538 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_WIDTH 2 1539 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_LBN 31 1540 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_WIDTH 1 1541 #define MC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_OFST 12 1542 #define MC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_LEN 4 1543 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_LBN 0 1544 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_WIDTH 16 1545 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_LBN 16 1546 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_WIDTH 1 1547 #define MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 /* enum */ 1548 #define MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 /* enum */ 1549 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_LBN 17 1550 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_WIDTH 15 1551 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_OFST 16 1552 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_LEN 4 1553 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_LBN 0 1554 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_WIDTH 16 1555 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_LBN 16 1556 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_WIDTH 16 1557 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_OFST 20 1558 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_LEN 4 1559 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_LBN 0 1560 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_WIDTH 16 1561 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_LBN 16 1562 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_WIDTH 16 1563 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_OFST 16 1564 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LEN 8 1565 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_OFST 16 1566 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_OFST 20 1567 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_OFST 24 1568 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_LEN 4 1569 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_OFST 28 1570 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_LEN 4 1571 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_LBN 0 1572 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_WIDTH 16 1573 1574 /* MC_CMD_FC_OUT_FPGA_BUILD_V2 msgresponse */ 1575 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_LEN 32 1576 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_OFST 0 1577 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_LEN 4 1578 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_LBN 31 1579 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_WIDTH 1 1580 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_LBN 30 1581 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_WIDTH 1 1582 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_LBN 16 1583 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_WIDTH 14 1584 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_LBN 12 1585 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_WIDTH 4 1586 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_LBN 4 1587 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_WIDTH 8 1588 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_LBN 0 1589 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_WIDTH 4 1590 /* Build timestamp (seconds since epoch) */ 1591 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_OFST 4 1592 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_LEN 4 1593 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_OFST 8 1594 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_LEN 4 1595 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_LBN 31 1596 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_WIDTH 1 1597 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_LBN 29 1598 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_WIDTH 1 1599 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_LBN 28 1600 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_WIDTH 1 1601 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_LBN 27 1602 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_WIDTH 1 1603 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_LBN 26 1604 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_WIDTH 1 1605 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_LBN 25 1606 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_WIDTH 1 1607 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_LBN 24 1608 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_WIDTH 1 1609 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_LBN 23 1610 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_WIDTH 1 1611 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_LBN 22 1612 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_WIDTH 1 1613 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_LBN 21 1614 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_WIDTH 1 1615 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_LBN 20 1616 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_WIDTH 1 1617 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_LBN 19 1618 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_WIDTH 1 1619 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_LBN 18 1620 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_WIDTH 1 1621 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_10G 0x0 /* enum */ 1622 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_40G 0x1 /* enum */ 1623 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_LBN 17 1624 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_WIDTH 1 1625 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_10G 0x0 /* enum */ 1626 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_40G 0x1 /* enum */ 1627 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_LBN 16 1628 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_WIDTH 1 1629 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_10G 0x0 /* enum */ 1630 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_40G 0x1 /* enum */ 1631 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_LBN 15 1632 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_WIDTH 1 1633 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_LBN 14 1634 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_WIDTH 1 1635 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_LBN 13 1636 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_WIDTH 1 1637 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_LBN 12 1638 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_WIDTH 1 1639 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_LBN 11 1640 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_WIDTH 1 1641 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_LBN 10 1642 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_WIDTH 1 1643 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_LBN 9 1644 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_WIDTH 1 1645 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_LBN 8 1646 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_WIDTH 1 1647 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_LBN 7 1648 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_WIDTH 1 1649 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_LBN 6 1650 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_WIDTH 1 1651 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_LBN 5 1652 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_WIDTH 1 1653 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_LBN 4 1654 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_WIDTH 1 1655 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_LBN 0 1656 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_WIDTH 4 1657 #define MC_CMD_FC_FPGA_V2_TYPE_A3 0x0 /* enum */ 1658 #define MC_CMD_FC_FPGA_V2_TYPE_A4 0x1 /* enum */ 1659 #define MC_CMD_FC_FPGA_V2_TYPE_A5 0x2 /* enum */ 1660 #define MC_CMD_FC_FPGA_V2_TYPE_A7 0x3 /* enum */ 1661 #define MC_CMD_FC_FPGA_V2_TYPE_D3 0x8 /* enum */ 1662 #define MC_CMD_FC_FPGA_V2_TYPE_D4 0x9 /* enum */ 1663 #define MC_CMD_FC_FPGA_V2_TYPE_D5 0xa /* enum */ 1664 #define MC_CMD_FC_FPGA_V2_TYPE_D7 0xb /* enum */ 1665 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_OFST 12 1666 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_LEN 4 1667 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_LBN 0 1668 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_WIDTH 16 1669 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_LBN 16 1670 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_WIDTH 1 1671 /* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */ 1672 /* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */ 1673 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_OFST 16 1674 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_LEN 4 1675 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_LBN 0 1676 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_WIDTH 16 1677 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_LBN 16 1678 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_WIDTH 16 1679 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_OFST 20 1680 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_LEN 4 1681 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_LBN 0 1682 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_WIDTH 16 1683 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_LBN 16 1684 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_WIDTH 16 1685 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_OFST 24 1686 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_LEN 4 1687 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_OFST 28 1688 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_LEN 4 1689 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_LBN 0 1690 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_WIDTH 16 1691 1692 /* MC_CMD_FC_OUT_FPGA_SERVICES msgresponse */ 1693 #define MC_CMD_FC_OUT_FPGA_SERVICES_LEN 32 1694 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_OFST 0 1695 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_LEN 4 1696 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_LBN 31 1697 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_WIDTH 1 1698 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_LBN 30 1699 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_WIDTH 1 1700 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_LBN 16 1701 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_WIDTH 14 1702 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_LBN 12 1703 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_WIDTH 4 1704 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_LBN 4 1705 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_WIDTH 8 1706 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_LBN 0 1707 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_WIDTH 4 1708 /* Build timestamp (seconds since epoch) */ 1709 #define MC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_OFST 4 1710 #define MC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_LEN 4 1711 #define MC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_OFST 8 1712 #define MC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_LEN 4 1713 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_LBN 8 1714 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_WIDTH 1 1715 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_LBN 27 1716 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_WIDTH 1 1717 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_LBN 28 1718 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_WIDTH 1 1719 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_LBN 29 1720 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_WIDTH 1 1721 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_LBN 30 1722 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_WIDTH 1 1723 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_LBN 31 1724 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_WIDTH 1 1725 #define MC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_OFST 12 1726 #define MC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_LEN 4 1727 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_LBN 0 1728 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_WIDTH 16 1729 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_LBN 16 1730 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_WIDTH 1 1731 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_OFST 16 1732 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_LEN 4 1733 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_LBN 0 1734 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_WIDTH 16 1735 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_LBN 16 1736 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_WIDTH 16 1737 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_OFST 20 1738 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_LEN 4 1739 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_LBN 0 1740 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_WIDTH 16 1741 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_LBN 16 1742 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_WIDTH 16 1743 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_OFST 24 1744 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_LEN 4 1745 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_OFST 28 1746 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_LEN 4 1747 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_LBN 0 1748 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_WIDTH 16 1749 1750 /* MC_CMD_FC_OUT_FPGA_SERVICES_V2 msgresponse */ 1751 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_LEN 32 1752 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_OFST 0 1753 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_LEN 4 1754 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_LBN 31 1755 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_WIDTH 1 1756 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_LBN 30 1757 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_WIDTH 1 1758 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_LBN 16 1759 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_WIDTH 14 1760 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_LBN 12 1761 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_WIDTH 4 1762 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_LBN 4 1763 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_WIDTH 8 1764 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_LBN 0 1765 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_WIDTH 4 1766 /* Build timestamp (seconds since epoch) */ 1767 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_OFST 4 1768 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_LEN 4 1769 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_OFST 8 1770 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_LEN 4 1771 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_LBN 0 1772 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_WIDTH 1 1773 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_LBN 8 1774 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_WIDTH 1 1775 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_OFST 12 1776 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_LEN 4 1777 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_LBN 0 1778 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_WIDTH 16 1779 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_LBN 16 1780 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_WIDTH 1 1781 /* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */ 1782 /* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */ 1783 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_OFST 24 1784 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_LEN 4 1785 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_OFST 28 1786 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_LEN 4 1787 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_LBN 0 1788 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_WIDTH 16 1789 1790 /* MC_CMD_FC_OUT_BSP_VERSION msgresponse */ 1791 #define MC_CMD_FC_OUT_BSP_VERSION_LEN 4 1792 /* Qsys system ID */ 1793 #define MC_CMD_FC_OUT_BSP_VERSION_SYSID_OFST 0 1794 #define MC_CMD_FC_OUT_BSP_VERSION_SYSID_LEN 4 1795 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_LBN 12 1796 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_WIDTH 4 1797 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_LBN 4 1798 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_WIDTH 8 1799 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_LBN 0 1800 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_WIDTH 4 1801 1802 /* MC_CMD_FC_OUT_READ_MAP_COUNT msgresponse */ 1803 #define MC_CMD_FC_OUT_READ_MAP_COUNT_LEN 4 1804 /* Number of maps */ 1805 #define MC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_OFST 0 1806 #define MC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_LEN 4 1807 1808 /* MC_CMD_FC_OUT_READ_MAP_INDEX msgresponse */ 1809 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN 164 1810 /* Index of the map */ 1811 #define MC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_OFST 0 1812 #define MC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_LEN 4 1813 /* Options for the map */ 1814 #define MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_OFST 4 1815 #define MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_LEN 4 1816 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_8 0x0 /* enum */ 1817 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_16 0x1 /* enum */ 1818 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_32 0x2 /* enum */ 1819 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_64 0x3 /* enum */ 1820 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_MASK 0x3 /* enum */ 1821 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_FC 0x4 /* enum */ 1822 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_MEM 0x8 /* enum */ 1823 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_READ 0x10 /* enum */ 1824 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_WRITE 0x20 /* enum */ 1825 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_FREE 0x0 /* enum */ 1826 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_LICENSED 0x40 /* enum */ 1827 /* Address of start of map */ 1828 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_OFST 8 1829 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LEN 8 1830 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_OFST 8 1831 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_OFST 12 1832 /* Length of address map */ 1833 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_OFST 16 1834 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LEN 8 1835 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_OFST 16 1836 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_OFST 20 1837 /* Component information field */ 1838 #define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_OFST 24 1839 #define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_LEN 4 1840 /* License expiry data for map */ 1841 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_OFST 28 1842 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LEN 8 1843 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_OFST 28 1844 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_OFST 32 1845 /* Name of the component */ 1846 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_OFST 36 1847 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_LEN 1 1848 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_NUM 128 1849 1850 /* MC_CMD_FC_OUT_READ_MAP msgresponse */ 1851 #define MC_CMD_FC_OUT_READ_MAP_LEN 0 1852 1853 /* MC_CMD_FC_OUT_CAPABILITIES msgresponse */ 1854 #define MC_CMD_FC_OUT_CAPABILITIES_LEN 8 1855 /* Number of internal ports */ 1856 #define MC_CMD_FC_OUT_CAPABILITIES_INTERNAL_OFST 0 1857 #define MC_CMD_FC_OUT_CAPABILITIES_INTERNAL_LEN 4 1858 /* Number of external ports */ 1859 #define MC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_OFST 4 1860 #define MC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_LEN 4 1861 1862 /* MC_CMD_FC_OUT_GLOBAL_FLAGS msgresponse */ 1863 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_LEN 4 1864 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_FLAGS_OFST 0 1865 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_FLAGS_LEN 4 1866 1867 /* MC_CMD_FC_OUT_IO_REL msgresponse */ 1868 #define MC_CMD_FC_OUT_IO_REL_LEN 0 1869 1870 /* MC_CMD_FC_OUT_IO_REL_GET_ADDR msgresponse */ 1871 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_LEN 8 1872 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_HI_OFST 0 1873 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_HI_LEN 4 1874 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_LO_OFST 4 1875 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_LO_LEN 4 1876 1877 /* MC_CMD_FC_OUT_IO_REL_READ32 msgresponse */ 1878 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMIN 4 1879 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMAX 252 1880 #define MC_CMD_FC_OUT_IO_REL_READ32_LEN(num) (0+4*(num)) 1881 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_OFST 0 1882 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_LEN 4 1883 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MINNUM 1 1884 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MAXNUM 63 1885 1886 /* MC_CMD_FC_OUT_IO_REL_WRITE32 msgresponse */ 1887 #define MC_CMD_FC_OUT_IO_REL_WRITE32_LEN 0 1888 1889 /* MC_CMD_FC_OUT_UHLINK_PHY msgresponse */ 1890 #define MC_CMD_FC_OUT_UHLINK_PHY_LEN 48 1891 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_OFST 0 1892 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_LEN 4 1893 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_LBN 0 1894 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_WIDTH 16 1895 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_LBN 16 1896 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_WIDTH 16 1897 /* Transceiver Transmit settings */ 1898 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_OFST 4 1899 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_LEN 4 1900 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_LBN 0 1901 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_WIDTH 16 1902 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_LBN 16 1903 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_WIDTH 16 1904 /* Transceiver Receive settings */ 1905 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_OFST 8 1906 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_LEN 4 1907 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_LBN 0 1908 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_WIDTH 16 1909 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_LBN 16 1910 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_WIDTH 16 1911 /* Rx eye opening */ 1912 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_OFST 12 1913 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_LEN 4 1914 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_LBN 0 1915 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_WIDTH 16 1916 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_LBN 16 1917 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_WIDTH 16 1918 /* PCS status word */ 1919 #define MC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_OFST 16 1920 #define MC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_LEN 4 1921 /* Link status word */ 1922 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_OFST 20 1923 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_LEN 4 1924 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_LBN 0 1925 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WIDTH 1 1926 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_LBN 1 1927 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_WIDTH 1 1928 /* Current SFp parameters applied */ 1929 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_OFST 24 1930 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_LEN 20 1931 /* Link speed is 100, 1000, 10000 */ 1932 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_OFST 24 1933 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_LEN 4 1934 /* Length of copper cable - zero when not relevant */ 1935 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_OFST 28 1936 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_LEN 4 1937 /* True if a dual speed SFP+ module */ 1938 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_OFST 32 1939 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_LEN 4 1940 /* True if an SFP Module is present (other fields valid when true) */ 1941 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_OFST 36 1942 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_LEN 4 1943 /* The type of the SFP+ Module */ 1944 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_OFST 40 1945 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_LEN 4 1946 /* PHY config flags */ 1947 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_OFST 44 1948 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_LEN 4 1949 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_LBN 0 1950 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_WIDTH 1 1951 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_LBN 1 1952 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_WIDTH 1 1953 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_LBN 2 1954 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_WIDTH 1 1955 1956 /* MC_CMD_FC_OUT_UHLINK_MAC msgresponse */ 1957 #define MC_CMD_FC_OUT_UHLINK_MAC_LEN 20 1958 /* MAC configuration applied */ 1959 #define MC_CMD_FC_OUT_UHLINK_MAC_CONFIG_OFST 0 1960 #define MC_CMD_FC_OUT_UHLINK_MAC_CONFIG_LEN 4 1961 /* MTU size */ 1962 #define MC_CMD_FC_OUT_UHLINK_MAC_MTU_OFST 4 1963 #define MC_CMD_FC_OUT_UHLINK_MAC_MTU_LEN 4 1964 /* IF Mode status */ 1965 #define MC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_OFST 8 1966 #define MC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_LEN 4 1967 /* MAC address configured */ 1968 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_OFST 12 1969 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LEN 8 1970 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_OFST 12 1971 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_OFST 16 1972 1973 /* MC_CMD_FC_OUT_UHLINK_RX_EYE msgresponse */ 1974 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_LEN ((((0-1+(32*MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK))+1))>>3) 1975 /* Rx Eye measurements */ 1976 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_OFST 0 1977 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_LEN 4 1978 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_NUM MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 1979 1980 /* MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT msgresponse */ 1981 #define MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT_LEN 0 1982 1983 /* MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT msgresponse */ 1984 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_LEN ((((32-1+(64*MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK))+1))>>3) 1985 /* Has the eye plot dump completed and data returned is valid? */ 1986 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_OFST 0 1987 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_LEN 4 1988 /* Rx Eye binary plot */ 1989 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_OFST 4 1990 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LEN 8 1991 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_OFST 4 1992 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_OFST 8 1993 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_NUM MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 1994 1995 /* MC_CMD_FC_OUT_UHLINK_RX_TUNE msgresponse */ 1996 #define MC_CMD_FC_OUT_UHLINK_RX_TUNE_LEN 0 1997 1998 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET msgresponse */ 1999 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET_LEN 0 2000 2001 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET msgresponse */ 2002 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_LEN 4 2003 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_STATE_OFST 0 2004 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_STATE_LEN 4 2005 2006 /* MC_CMD_FC_OUT_UHLINK msgresponse */ 2007 #define MC_CMD_FC_OUT_UHLINK_LEN 0 2008 2009 /* MC_CMD_FC_OUT_SET_LINK msgresponse */ 2010 #define MC_CMD_FC_OUT_SET_LINK_LEN 0 2011 2012 /* MC_CMD_FC_OUT_LICENSE msgresponse */ 2013 #define MC_CMD_FC_OUT_LICENSE_LEN 12 2014 /* Count of valid keys */ 2015 #define MC_CMD_FC_OUT_LICENSE_VALID_KEYS_OFST 0 2016 #define MC_CMD_FC_OUT_LICENSE_VALID_KEYS_LEN 4 2017 /* Count of invalid keys */ 2018 #define MC_CMD_FC_OUT_LICENSE_INVALID_KEYS_OFST 4 2019 #define MC_CMD_FC_OUT_LICENSE_INVALID_KEYS_LEN 4 2020 /* Count of blacklisted keys */ 2021 #define MC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_OFST 8 2022 #define MC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_LEN 4 2023 2024 /* MC_CMD_FC_OUT_STARTUP msgresponse */ 2025 #define MC_CMD_FC_OUT_STARTUP_LEN 4 2026 /* Capabilities of the FPGA/FC */ 2027 #define MC_CMD_FC_OUT_STARTUP_CAPABILITIES_OFST 0 2028 #define MC_CMD_FC_OUT_STARTUP_CAPABILITIES_LEN 4 2029 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_LBN 0 2030 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_WIDTH 1 2031 2032 /* MC_CMD_FC_OUT_DMA_READ msgresponse */ 2033 #define MC_CMD_FC_OUT_DMA_READ_LENMIN 1 2034 #define MC_CMD_FC_OUT_DMA_READ_LENMAX 252 2035 #define MC_CMD_FC_OUT_DMA_READ_LEN(num) (0+1*(num)) 2036 /* The data read */ 2037 #define MC_CMD_FC_OUT_DMA_READ_DATA_OFST 0 2038 #define MC_CMD_FC_OUT_DMA_READ_DATA_LEN 1 2039 #define MC_CMD_FC_OUT_DMA_READ_DATA_MINNUM 1 2040 #define MC_CMD_FC_OUT_DMA_READ_DATA_MAXNUM 252 2041 2042 /* MC_CMD_FC_OUT_TIMED_READ_SET msgresponse */ 2043 #define MC_CMD_FC_OUT_TIMED_READ_SET_LEN 4 2044 /* Timer handle */ 2045 #define MC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_OFST 0 2046 #define MC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_LEN 4 2047 2048 /* MC_CMD_FC_OUT_TIMED_READ_GET msgresponse */ 2049 #define MC_CMD_FC_OUT_TIMED_READ_GET_LEN 52 2050 /* Host supplied handle (unique) */ 2051 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_OFST 0 2052 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_LEN 4 2053 /* Address into which to transfer data in host */ 2054 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_OFST 4 2055 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LEN 8 2056 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_OFST 4 2057 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_OFST 8 2058 /* AOE address from which to transfer data */ 2059 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_OFST 12 2060 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LEN 8 2061 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_OFST 12 2062 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_OFST 16 2063 /* Length of AOE transfer (total) */ 2064 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_OFST 20 2065 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_LEN 4 2066 /* Length of host transfer (total) */ 2067 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_OFST 24 2068 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_LEN 4 2069 /* See FLAGS entry for MC_CMD_FC_IN_TIMED_READ_SET */ 2070 #define MC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_OFST 28 2071 #define MC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_LEN 4 2072 #define MC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_OFST 32 2073 #define MC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_LEN 4 2074 /* When active, start read time */ 2075 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_OFST 36 2076 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LEN 8 2077 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_OFST 36 2078 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_OFST 40 2079 /* When active, end read time */ 2080 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_OFST 44 2081 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LEN 8 2082 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_OFST 44 2083 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_OFST 48 2084 2085 /* MC_CMD_FC_OUT_LOG_ADDR_RANGE msgresponse */ 2086 #define MC_CMD_FC_OUT_LOG_ADDR_RANGE_LEN 0 2087 2088 /* MC_CMD_FC_OUT_LOG msgresponse */ 2089 #define MC_CMD_FC_OUT_LOG_LEN 0 2090 2091 /* MC_CMD_FC_OUT_CLOCK_GET_TIME msgresponse */ 2092 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_LEN 24 2093 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_CLOCK_ID_OFST 0 2094 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_CLOCK_ID_LEN 4 2095 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_OFST 4 2096 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LEN 8 2097 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_OFST 4 2098 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_OFST 8 2099 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_OFST 12 2100 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_LEN 4 2101 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_OFST 16 2102 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_LEN 4 2103 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_PRECISION_OFST 20 2104 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_PRECISION_LEN 4 2105 2106 /* MC_CMD_FC_OUT_CLOCK_SET_TIME msgresponse */ 2107 #define MC_CMD_FC_OUT_CLOCK_SET_TIME_LEN 0 2108 2109 /* MC_CMD_FC_OUT_DDR_SET_SPD msgresponse */ 2110 #define MC_CMD_FC_OUT_DDR_SET_SPD_LEN 0 2111 2112 /* MC_CMD_FC_OUT_DDR_SET_INFO msgresponse */ 2113 #define MC_CMD_FC_OUT_DDR_SET_INFO_LEN 0 2114 2115 /* MC_CMD_FC_OUT_DDR_GET_STATUS msgresponse */ 2116 #define MC_CMD_FC_OUT_DDR_GET_STATUS_LEN 4 2117 #define MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_OFST 0 2118 #define MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_LEN 4 2119 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_LBN 0 2120 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_WIDTH 1 2121 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_LBN 1 2122 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_WIDTH 1 2123 2124 /* MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT msgresponse */ 2125 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_LEN 8 2126 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_SECONDS_OFST 0 2127 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_SECONDS_LEN 4 2128 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_NANOSECONDS_OFST 4 2129 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_NANOSECONDS_LEN 4 2130 2131 /* MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT msgresponse */ 2132 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMIN 8 2133 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX 248 2134 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LEN(num) (0+8*(num)) 2135 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_OFST 0 2136 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_LEN 4 2137 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_OFST 4 2138 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_LEN 4 2139 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_OFST 0 2140 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LEN 8 2141 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_OFST 0 2142 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_OFST 4 2143 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MINNUM 0 2144 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM 31 2145 2146 /* MC_CMD_FC_OUT_SPI_READ msgresponse */ 2147 #define MC_CMD_FC_OUT_SPI_READ_LENMIN 4 2148 #define MC_CMD_FC_OUT_SPI_READ_LENMAX 252 2149 #define MC_CMD_FC_OUT_SPI_READ_LEN(num) (0+4*(num)) 2150 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_OFST 0 2151 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_LEN 4 2152 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MINNUM 1 2153 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MAXNUM 63 2154 2155 /* MC_CMD_FC_OUT_SPI_WRITE msgresponse */ 2156 #define MC_CMD_FC_OUT_SPI_WRITE_LEN 0 2157 2158 /* MC_CMD_FC_OUT_SPI_ERASE msgresponse */ 2159 #define MC_CMD_FC_OUT_SPI_ERASE_LEN 0 2160 2161 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG msgresponse */ 2162 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_LEN 8 2163 /* The 32-bit value read from the toggle count register */ 2164 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_OFST 0 2165 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_LEN 4 2166 /* The 32-bit value read from the clock enable count register */ 2167 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_OFST 4 2168 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_LEN 4 2169 2170 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG msgresponse */ 2171 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 0 2172 2173 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_START msgresponse */ 2174 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_START_LEN 0 2175 2176 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT msgresponse */ 2177 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_LEN 8 2178 /* DDR soak test status word; bits [4:0] are relevant. */ 2179 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_OFST 0 2180 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_LEN 4 2181 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_LBN 0 2182 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_WIDTH 1 2183 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_LBN 1 2184 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_WIDTH 1 2185 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_LBN 2 2186 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_WIDTH 1 2187 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_LBN 3 2188 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_WIDTH 1 2189 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_LBN 4 2190 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_WIDTH 1 2191 /* DDR soak test error count */ 2192 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_OFST 4 2193 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_LEN 4 2194 2195 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP msgresponse */ 2196 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP_LEN 0 2197 2198 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR msgresponse */ 2199 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR_LEN 0 2200 2201 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE msgresponse */ 2202 #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE_LEN 0 2203 2204 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG msgresponse */ 2205 #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 0 2206 2207 2208 /***********************************/ 2209 /* MC_CMD_AOE 2210 * AOE operations on MC 2211 */ 2212 #define MC_CMD_AOE 0xa 2213 2214 /* MC_CMD_AOE_IN msgrequest */ 2215 #define MC_CMD_AOE_IN_LEN 4 2216 #define MC_CMD_AOE_IN_OP_HDR_OFST 0 2217 #define MC_CMD_AOE_IN_OP_HDR_LEN 4 2218 #define MC_CMD_AOE_IN_OP_LBN 0 2219 #define MC_CMD_AOE_IN_OP_WIDTH 8 2220 /* enum: FPGA and CPLD information */ 2221 #define MC_CMD_AOE_OP_INFO 0x1 2222 /* enum: Currents and voltages read from MCP3424s; DEBUG */ 2223 #define MC_CMD_AOE_OP_CURRENTS 0x2 2224 /* enum: Temperatures at locations around the PCB; DEBUG */ 2225 #define MC_CMD_AOE_OP_TEMPERATURES 0x3 2226 /* enum: Set CPLD to idle */ 2227 #define MC_CMD_AOE_OP_CPLD_IDLE 0x4 2228 /* enum: Read from CPLD register */ 2229 #define MC_CMD_AOE_OP_CPLD_READ 0x5 2230 /* enum: Write to CPLD register */ 2231 #define MC_CMD_AOE_OP_CPLD_WRITE 0x6 2232 /* enum: Execute CPLD instruction */ 2233 #define MC_CMD_AOE_OP_CPLD_INSTRUCTION 0x7 2234 /* enum: Reprogram the CPLD on the AOE device */ 2235 #define MC_CMD_AOE_OP_CPLD_REPROGRAM 0x8 2236 /* enum: AOE power control */ 2237 #define MC_CMD_AOE_OP_POWER 0x9 2238 /* enum: AOE image loading */ 2239 #define MC_CMD_AOE_OP_LOAD 0xa 2240 /* enum: Fan monitoring */ 2241 #define MC_CMD_AOE_OP_FAN_CONTROL 0xb 2242 /* enum: Fan failures since last reset */ 2243 #define MC_CMD_AOE_OP_FAN_FAILURES 0xc 2244 /* enum: Get generic AOE MAC statistics */ 2245 #define MC_CMD_AOE_OP_MAC_STATS 0xd 2246 /* enum: Retrieve PHY specific information */ 2247 #define MC_CMD_AOE_OP_GET_PHY_MEDIA_INFO 0xe 2248 /* enum: Write a number of JTAG primitive commands, return will give data */ 2249 #define MC_CMD_AOE_OP_JTAG_WRITE 0xf 2250 /* enum: Control access to the FPGA via the Siena JTAG Chain */ 2251 #define MC_CMD_AOE_OP_FPGA_ACCESS 0x10 2252 /* enum: Set the MTU offset between Siena and AOE MACs */ 2253 #define MC_CMD_AOE_OP_SET_MTU_OFFSET 0x11 2254 /* enum: How link state is handled */ 2255 #define MC_CMD_AOE_OP_LINK_STATE 0x12 2256 /* enum: How Siena MAC statistics are reported (deprecated - use 2257 * MC_CMD_AOE_OP_ASIC_STATS) 2258 */ 2259 #define MC_CMD_AOE_OP_SIENA_STATS 0x13 2260 /* enum: How native ASIC MAC statistics are reported - replaces the deprecated 2261 * command MC_CMD_AOE_OP_SIENA_STATS 2262 */ 2263 #define MC_CMD_AOE_OP_ASIC_STATS 0x13 2264 /* enum: DDR memory information */ 2265 #define MC_CMD_AOE_OP_DDR 0x14 2266 /* enum: FC control */ 2267 #define MC_CMD_AOE_OP_FC 0x15 2268 /* enum: DDR ECC status reads */ 2269 #define MC_CMD_AOE_OP_DDR_ECC_STATUS 0x16 2270 /* enum: Commands for MC-SPI Master emulation */ 2271 #define MC_CMD_AOE_OP_MC_SPI_MASTER 0x17 2272 /* enum: Commands for FC boot control */ 2273 #define MC_CMD_AOE_OP_FC_BOOT 0x18 2274 /* enum: Get number of internal ports */ 2275 #define MC_CMD_AOE_OP_GET_ASIC_PORTS 0x19 2276 /* enum: Get FC assert information and register dump */ 2277 #define MC_CMD_AOE_OP_GET_FC_ASSERT_INFO 0x1a 2278 2279 /* MC_CMD_AOE_OUT msgresponse */ 2280 #define MC_CMD_AOE_OUT_LEN 0 2281 2282 /* MC_CMD_AOE_IN_INFO msgrequest */ 2283 #define MC_CMD_AOE_IN_INFO_LEN 4 2284 #define MC_CMD_AOE_IN_CMD_OFST 0 2285 #define MC_CMD_AOE_IN_CMD_LEN 4 2286 2287 /* MC_CMD_AOE_IN_CURRENTS msgrequest */ 2288 #define MC_CMD_AOE_IN_CURRENTS_LEN 4 2289 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2290 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2291 2292 /* MC_CMD_AOE_IN_TEMPERATURES msgrequest */ 2293 #define MC_CMD_AOE_IN_TEMPERATURES_LEN 4 2294 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2295 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2296 2297 /* MC_CMD_AOE_IN_CPLD_IDLE msgrequest */ 2298 #define MC_CMD_AOE_IN_CPLD_IDLE_LEN 4 2299 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2300 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2301 2302 /* MC_CMD_AOE_IN_CPLD_READ msgrequest */ 2303 #define MC_CMD_AOE_IN_CPLD_READ_LEN 12 2304 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2305 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2306 #define MC_CMD_AOE_IN_CPLD_READ_REGISTER_OFST 4 2307 #define MC_CMD_AOE_IN_CPLD_READ_REGISTER_LEN 4 2308 #define MC_CMD_AOE_IN_CPLD_READ_WIDTH_OFST 8 2309 #define MC_CMD_AOE_IN_CPLD_READ_WIDTH_LEN 4 2310 2311 /* MC_CMD_AOE_IN_CPLD_WRITE msgrequest */ 2312 #define MC_CMD_AOE_IN_CPLD_WRITE_LEN 16 2313 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2314 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2315 #define MC_CMD_AOE_IN_CPLD_WRITE_REGISTER_OFST 4 2316 #define MC_CMD_AOE_IN_CPLD_WRITE_REGISTER_LEN 4 2317 #define MC_CMD_AOE_IN_CPLD_WRITE_WIDTH_OFST 8 2318 #define MC_CMD_AOE_IN_CPLD_WRITE_WIDTH_LEN 4 2319 #define MC_CMD_AOE_IN_CPLD_WRITE_VALUE_OFST 12 2320 #define MC_CMD_AOE_IN_CPLD_WRITE_VALUE_LEN 4 2321 2322 /* MC_CMD_AOE_IN_CPLD_INSTRUCTION msgrequest */ 2323 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_LEN 8 2324 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2325 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2326 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_INSTRUCTION_OFST 4 2327 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_INSTRUCTION_LEN 4 2328 2329 /* MC_CMD_AOE_IN_CPLD_REPROGRAM msgrequest */ 2330 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_LEN 8 2331 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2332 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2333 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_OP_OFST 4 2334 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_OP_LEN 4 2335 /* enum: Reprogram CPLD, poll for completion */ 2336 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM 0x1 2337 /* enum: Reprogram CPLD, send event on completion */ 2338 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM_EVENT 0x3 2339 /* enum: Get status of reprogramming operation */ 2340 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_STATUS 0x4 2341 2342 /* MC_CMD_AOE_IN_POWER msgrequest */ 2343 #define MC_CMD_AOE_IN_POWER_LEN 8 2344 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2345 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2346 /* Turn on or off AOE power */ 2347 #define MC_CMD_AOE_IN_POWER_OP_OFST 4 2348 #define MC_CMD_AOE_IN_POWER_OP_LEN 4 2349 /* enum: Turn off FPGA power */ 2350 #define MC_CMD_AOE_IN_POWER_OFF 0x0 2351 /* enum: Turn on FPGA power */ 2352 #define MC_CMD_AOE_IN_POWER_ON 0x1 2353 /* enum: Clear peak power measurement */ 2354 #define MC_CMD_AOE_IN_POWER_CLEAR 0x2 2355 /* enum: Show current power in sensors output */ 2356 #define MC_CMD_AOE_IN_POWER_SHOW_CURRENT 0x3 2357 /* enum: Show peak power in sensors output */ 2358 #define MC_CMD_AOE_IN_POWER_SHOW_PEAK 0x4 2359 /* enum: Show current DDR current */ 2360 #define MC_CMD_AOE_IN_POWER_DDR_LAST 0x5 2361 /* enum: Show peak DDR current */ 2362 #define MC_CMD_AOE_IN_POWER_DDR_PEAK 0x6 2363 /* enum: Clear peak DDR current */ 2364 #define MC_CMD_AOE_IN_POWER_DDR_CLEAR 0x7 2365 2366 /* MC_CMD_AOE_IN_LOAD msgrequest */ 2367 #define MC_CMD_AOE_IN_LOAD_LEN 8 2368 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2369 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2370 /* Image to be loaded (0 - main or 1 - diagnostic) to load in normal sequence 2371 */ 2372 #define MC_CMD_AOE_IN_LOAD_IMAGE_OFST 4 2373 #define MC_CMD_AOE_IN_LOAD_IMAGE_LEN 4 2374 2375 /* MC_CMD_AOE_IN_FAN_CONTROL msgrequest */ 2376 #define MC_CMD_AOE_IN_FAN_CONTROL_LEN 8 2377 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2378 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2379 /* If non zero report measured fan RPM rather than nominal */ 2380 #define MC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_OFST 4 2381 #define MC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_LEN 4 2382 2383 /* MC_CMD_AOE_IN_FAN_FAILURES msgrequest */ 2384 #define MC_CMD_AOE_IN_FAN_FAILURES_LEN 4 2385 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2386 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2387 2388 /* MC_CMD_AOE_IN_MAC_STATS msgrequest */ 2389 #define MC_CMD_AOE_IN_MAC_STATS_LEN 24 2390 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2391 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2392 /* AOE port */ 2393 #define MC_CMD_AOE_IN_MAC_STATS_PORT_OFST 4 2394 #define MC_CMD_AOE_IN_MAC_STATS_PORT_LEN 4 2395 /* Host memory address for statistics */ 2396 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_OFST 8 2397 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LEN 8 2398 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_OFST 8 2399 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_OFST 12 2400 #define MC_CMD_AOE_IN_MAC_STATS_CMD_OFST 16 2401 #define MC_CMD_AOE_IN_MAC_STATS_CMD_LEN 4 2402 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LBN 0 2403 #define MC_CMD_AOE_IN_MAC_STATS_DMA_WIDTH 1 2404 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_LBN 1 2405 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_WIDTH 1 2406 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_LBN 2 2407 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_WIDTH 1 2408 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_LBN 3 2409 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_WIDTH 1 2410 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_LBN 4 2411 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_WIDTH 1 2412 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_LBN 5 2413 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_WIDTH 1 2414 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_LBN 16 2415 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_WIDTH 16 2416 /* Length of DMA data (optional) */ 2417 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LEN_OFST 20 2418 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LEN_LEN 4 2419 2420 /* MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO msgrequest */ 2421 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_LEN 12 2422 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2423 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2424 /* AOE port */ 2425 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_OFST 4 2426 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_LEN 4 2427 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_OFST 8 2428 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_LEN 4 2429 2430 /* MC_CMD_AOE_IN_JTAG_WRITE msgrequest */ 2431 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMIN 12 2432 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMAX 252 2433 #define MC_CMD_AOE_IN_JTAG_WRITE_LEN(num) (8+4*(num)) 2434 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2435 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2436 #define MC_CMD_AOE_IN_JTAG_WRITE_DATALEN_OFST 4 2437 #define MC_CMD_AOE_IN_JTAG_WRITE_DATALEN_LEN 4 2438 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_OFST 8 2439 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_LEN 4 2440 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MINNUM 1 2441 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MAXNUM 61 2442 2443 /* MC_CMD_AOE_IN_FPGA_ACCESS msgrequest */ 2444 #define MC_CMD_AOE_IN_FPGA_ACCESS_LEN 8 2445 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2446 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2447 /* Enable or disable access */ 2448 #define MC_CMD_AOE_IN_FPGA_ACCESS_OP_OFST 4 2449 #define MC_CMD_AOE_IN_FPGA_ACCESS_OP_LEN 4 2450 /* enum: Enable access */ 2451 #define MC_CMD_AOE_IN_FPGA_ACCESS_ENABLE 0x1 2452 /* enum: Disable access */ 2453 #define MC_CMD_AOE_IN_FPGA_ACCESS_DISABLE 0x2 2454 2455 /* MC_CMD_AOE_IN_SET_MTU_OFFSET msgrequest */ 2456 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_LEN 12 2457 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2458 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2459 /* AOE port - when not ALL_EXTERNAL or ALL_INTERNAL specifies port number */ 2460 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_OFST 4 2461 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_LEN 4 2462 /* enum: Apply to all external ports */ 2463 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_EXTERNAL 0x8000 2464 /* enum: Apply to all internal ports */ 2465 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_INTERNAL 0x4000 2466 /* The MTU offset to be applied to the external ports */ 2467 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_OFST 8 2468 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_LEN 4 2469 2470 /* MC_CMD_AOE_IN_LINK_STATE msgrequest */ 2471 #define MC_CMD_AOE_IN_LINK_STATE_LEN 8 2472 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2473 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2474 #define MC_CMD_AOE_IN_LINK_STATE_MODE_OFST 4 2475 #define MC_CMD_AOE_IN_LINK_STATE_MODE_LEN 4 2476 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_LBN 0 2477 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_WIDTH 8 2478 /* enum: AOE and associated external port */ 2479 #define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_SEPARATE 0x0 2480 /* enum: AOE and OR of all external ports */ 2481 #define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_COMBINED 0x1 2482 /* enum: Individual ports */ 2483 #define MC_CMD_AOE_IN_LINK_STATE_DIAGNOSTIC 0x2 2484 /* enum: Configure link state mode on given AOE port */ 2485 #define MC_CMD_AOE_IN_LINK_STATE_CUSTOM 0x3 2486 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_LBN 8 2487 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_WIDTH 8 2488 /* enum: No-op */ 2489 #define MC_CMD_AOE_IN_LINK_STATE_OP_NONE 0x0 2490 /* enum: logical OR of all SFP ports link status */ 2491 #define MC_CMD_AOE_IN_LINK_STATE_OP_OR 0x1 2492 /* enum: logical AND of all SFP ports link status */ 2493 #define MC_CMD_AOE_IN_LINK_STATE_OP_AND 0x2 2494 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_LBN 16 2495 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_WIDTH 16 2496 2497 /* MC_CMD_AOE_IN_GET_ASIC_PORTS msgrequest */ 2498 #define MC_CMD_AOE_IN_GET_ASIC_PORTS_LEN 4 2499 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2500 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2501 2502 /* MC_CMD_AOE_IN_GET_FC_ASSERT_INFO msgrequest */ 2503 #define MC_CMD_AOE_IN_GET_FC_ASSERT_INFO_LEN 4 2504 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2505 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2506 2507 /* MC_CMD_AOE_IN_SIENA_STATS msgrequest */ 2508 #define MC_CMD_AOE_IN_SIENA_STATS_LEN 8 2509 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2510 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2511 /* How MAC statistics are reported */ 2512 #define MC_CMD_AOE_IN_SIENA_STATS_MODE_OFST 4 2513 #define MC_CMD_AOE_IN_SIENA_STATS_MODE_LEN 4 2514 /* enum: Statistics from Siena (default) */ 2515 #define MC_CMD_AOE_IN_SIENA_STATS_STATS_SIENA 0x0 2516 /* enum: Statistics from AOE external ports */ 2517 #define MC_CMD_AOE_IN_SIENA_STATS_STATS_AOE 0x1 2518 2519 /* MC_CMD_AOE_IN_ASIC_STATS msgrequest */ 2520 #define MC_CMD_AOE_IN_ASIC_STATS_LEN 8 2521 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2522 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2523 /* How MAC statistics are reported */ 2524 #define MC_CMD_AOE_IN_ASIC_STATS_MODE_OFST 4 2525 #define MC_CMD_AOE_IN_ASIC_STATS_MODE_LEN 4 2526 /* enum: Statistics from the ASIC (default) */ 2527 #define MC_CMD_AOE_IN_ASIC_STATS_STATS_ASIC 0x0 2528 /* enum: Statistics from AOE external ports */ 2529 #define MC_CMD_AOE_IN_ASIC_STATS_STATS_AOE 0x1 2530 2531 /* MC_CMD_AOE_IN_DDR msgrequest */ 2532 #define MC_CMD_AOE_IN_DDR_LEN 12 2533 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2534 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2535 #define MC_CMD_AOE_IN_DDR_BANK_OFST 4 2536 #define MC_CMD_AOE_IN_DDR_BANK_LEN 4 2537 /* Enum values, see field(s): */ 2538 /* MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */ 2539 /* Page index of SPD data */ 2540 #define MC_CMD_AOE_IN_DDR_SPD_PAGE_ID_OFST 8 2541 #define MC_CMD_AOE_IN_DDR_SPD_PAGE_ID_LEN 4 2542 2543 /* MC_CMD_AOE_IN_FC msgrequest */ 2544 #define MC_CMD_AOE_IN_FC_LEN 4 2545 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2546 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2547 2548 /* MC_CMD_AOE_IN_DDR_ECC_STATUS msgrequest */ 2549 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_LEN 8 2550 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2551 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2552 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_OFST 4 2553 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_LEN 4 2554 /* Enum values, see field(s): */ 2555 /* MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */ 2556 2557 /* MC_CMD_AOE_IN_MC_SPI_MASTER msgrequest */ 2558 #define MC_CMD_AOE_IN_MC_SPI_MASTER_LEN 8 2559 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2560 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2561 /* Basic commands for MC SPI Master emulation. */ 2562 #define MC_CMD_AOE_IN_MC_SPI_MASTER_OP_OFST 4 2563 #define MC_CMD_AOE_IN_MC_SPI_MASTER_OP_LEN 4 2564 /* enum: MC SPI read */ 2565 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ 0x0 2566 /* enum: MC SPI write */ 2567 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE 0x1 2568 2569 /* MC_CMD_AOE_IN_MC_SPI_MASTER_READ msgrequest */ 2570 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_LEN 12 2571 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2572 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2573 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OP_OFST 4 2574 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OP_LEN 4 2575 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OFFSET_OFST 8 2576 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OFFSET_LEN 4 2577 2578 /* MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE msgrequest */ 2579 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_LEN 16 2580 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2581 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2582 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OP_OFST 4 2583 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OP_LEN 4 2584 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_OFST 8 2585 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_LEN 4 2586 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_OFST 12 2587 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_LEN 4 2588 2589 /* MC_CMD_AOE_IN_FC_BOOT msgrequest */ 2590 #define MC_CMD_AOE_IN_FC_BOOT_LEN 8 2591 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2592 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2593 /* FC boot control flags */ 2594 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_OFST 4 2595 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_LEN 4 2596 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_LBN 0 2597 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_WIDTH 1 2598 2599 /* MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO msgresponse */ 2600 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_LEN 144 2601 /* Assertion status flag. */ 2602 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GLOBAL_FLAGS_OFST 0 2603 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GLOBAL_FLAGS_LEN 4 2604 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_STATE_LBN 8 2605 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_STATE_WIDTH 8 2606 /* enum: No crash data available */ 2607 /* MC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0 */ 2608 /* enum: New crash data available */ 2609 /* MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1 */ 2610 /* enum: Crash data has been sent */ 2611 /* MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2 */ 2612 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_TYPE_LBN 0 2613 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_TYPE_WIDTH 8 2614 /* enum: No crash has been recorded. */ 2615 /* MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0 */ 2616 /* enum: Crash due to exception. */ 2617 /* MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1 */ 2618 /* enum: Crash due to assertion. */ 2619 /* MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2 */ 2620 /* Failing PC value */ 2621 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_SAVED_PC_OFFS_OFST 4 2622 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_SAVED_PC_OFFS_LEN 4 2623 /* Saved GP regs */ 2624 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GP_REGS_OFFS_OFST 8 2625 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GP_REGS_OFFS_LEN 4 2626 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GP_REGS_OFFS_NUM 31 2627 /* Exception Type */ 2628 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_TYPE_OFFS_OFST 132 2629 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_TYPE_OFFS_LEN 4 2630 /* Instruction at which exception occurred */ 2631 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_PC_ADDR_OFFS_OFST 136 2632 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_PC_ADDR_OFFS_LEN 4 2633 /* BAD Address that triggered address-based exception */ 2634 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_BAD_ADDR_OFFS_OFST 140 2635 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_BAD_ADDR_OFFS_LEN 4 2636 2637 /* MC_CMD_AOE_OUT_INFO msgresponse */ 2638 #define MC_CMD_AOE_OUT_INFO_LEN 44 2639 /* JTAG IDCODE of CPLD */ 2640 #define MC_CMD_AOE_OUT_INFO_CPLD_IDCODE_OFST 0 2641 #define MC_CMD_AOE_OUT_INFO_CPLD_IDCODE_LEN 4 2642 /* Version of CPLD */ 2643 #define MC_CMD_AOE_OUT_INFO_CPLD_VERSION_OFST 4 2644 #define MC_CMD_AOE_OUT_INFO_CPLD_VERSION_LEN 4 2645 /* JTAG IDCODE of FPGA */ 2646 #define MC_CMD_AOE_OUT_INFO_FPGA_IDCODE_OFST 8 2647 #define MC_CMD_AOE_OUT_INFO_FPGA_IDCODE_LEN 4 2648 /* JTAG USERCODE of FPGA */ 2649 #define MC_CMD_AOE_OUT_INFO_FPGA_VERSION_OFST 12 2650 #define MC_CMD_AOE_OUT_INFO_FPGA_VERSION_LEN 4 2651 /* FPGA type - read from CPLD straps */ 2652 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_OFST 16 2653 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_LEN 4 2654 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A5_C2 0x1 /* enum */ 2655 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A7_C2 0x2 /* enum */ 2656 /* FPGA state (debug) */ 2657 #define MC_CMD_AOE_OUT_INFO_FPGA_STATE_OFST 20 2658 #define MC_CMD_AOE_OUT_INFO_FPGA_STATE_LEN 4 2659 /* FPGA image - partition from which loaded */ 2660 #define MC_CMD_AOE_OUT_INFO_FPGA_IMAGE_OFST 24 2661 #define MC_CMD_AOE_OUT_INFO_FPGA_IMAGE_LEN 4 2662 /* FC state */ 2663 #define MC_CMD_AOE_OUT_INFO_FC_STATE_OFST 28 2664 #define MC_CMD_AOE_OUT_INFO_FC_STATE_LEN 4 2665 /* enum: Set if watchdog working */ 2666 #define MC_CMD_AOE_OUT_INFO_WATCHDOG 0x1 2667 /* enum: Set if MC-FC communications working */ 2668 #define MC_CMD_AOE_OUT_INFO_COMMS 0x2 2669 /* Random pieces of information */ 2670 #define MC_CMD_AOE_OUT_INFO_FLAGS_OFST 32 2671 #define MC_CMD_AOE_OUT_INFO_FLAGS_LEN 4 2672 /* enum: Power to FPGA supplied by PEG connector, not PCIe bus */ 2673 #define MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1 2674 /* enum: CPLD apparently good */ 2675 #define MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2 2676 /* enum: FPGA working normally */ 2677 #define MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4 2678 /* enum: FPGA is powered */ 2679 #define MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8 2680 /* enum: Board has incompatible SODIMMs fitted */ 2681 #define MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10 2682 /* enum: Board has ByteBlaster connected */ 2683 #define MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20 2684 /* enum: FPGA Boot flash has an invalid header. */ 2685 #define MC_CMD_AOE_OUT_INFO_FPGA_BAD_BOOT_HDR 0x40 2686 /* enum: FPGA Application flash is accessible. */ 2687 #define MC_CMD_AOE_OUT_INFO_FPGA_APP_FLASH_GOOD 0x80 2688 /* Revision of Modena and Sorrento boards. Sorrento can be R1_2 or R1_3. */ 2689 #define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_OFST 36 2690 #define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_LEN 4 2691 #define MC_CMD_AOE_OUT_INFO_UNKNOWN 0x0 /* enum */ 2692 #define MC_CMD_AOE_OUT_INFO_R1_0 0x10 /* enum */ 2693 #define MC_CMD_AOE_OUT_INFO_R1_1 0x11 /* enum */ 2694 #define MC_CMD_AOE_OUT_INFO_R1_2 0x12 /* enum */ 2695 #define MC_CMD_AOE_OUT_INFO_R1_3 0x13 /* enum */ 2696 /* Result of FC booting - not valid while a ByteBlaster is connected. */ 2697 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_OFST 40 2698 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_LEN 4 2699 /* enum: No error */ 2700 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_NO_ERROR 0x0 2701 /* enum: Bad address set in CPLD */ 2702 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_ADDRESS 0x1 2703 /* enum: Bad header */ 2704 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_MAGIC 0x2 2705 /* enum: Bad text section details */ 2706 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_TEXT 0x3 2707 /* enum: Bad checksum */ 2708 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_CHECKSUM 0x4 2709 /* enum: Bad BSP */ 2710 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_BSP 0x5 2711 /* enum: Flash mode is invalid */ 2712 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_INVALID_FLASH_MODE 0x6 2713 /* enum: FC application loaded and execution attempted */ 2714 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_EXECUTE 0x80 2715 /* enum: FC application Started */ 2716 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_STARTED 0x81 2717 /* enum: No bootrom in FPGA */ 2718 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_NO_BOOTROM 0xff 2719 2720 /* MC_CMD_AOE_OUT_CURRENTS msgresponse */ 2721 #define MC_CMD_AOE_OUT_CURRENTS_LEN 68 2722 /* Set of currents and voltages (mA or mV as appropriate) */ 2723 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_OFST 0 2724 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_LEN 4 2725 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_NUM 17 2726 #define MC_CMD_AOE_OUT_CURRENTS_I_2V5 0x0 /* enum */ 2727 #define MC_CMD_AOE_OUT_CURRENTS_I_1V8 0x1 /* enum */ 2728 #define MC_CMD_AOE_OUT_CURRENTS_I_GXB 0x2 /* enum */ 2729 #define MC_CMD_AOE_OUT_CURRENTS_I_PGM 0x3 /* enum */ 2730 #define MC_CMD_AOE_OUT_CURRENTS_I_XCVR 0x4 /* enum */ 2731 #define MC_CMD_AOE_OUT_CURRENTS_I_1V5 0x5 /* enum */ 2732 #define MC_CMD_AOE_OUT_CURRENTS_V_3V3 0x6 /* enum */ 2733 #define MC_CMD_AOE_OUT_CURRENTS_V_1V5 0x7 /* enum */ 2734 #define MC_CMD_AOE_OUT_CURRENTS_I_IN 0x8 /* enum */ 2735 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT 0x9 /* enum */ 2736 #define MC_CMD_AOE_OUT_CURRENTS_V_IN 0xa /* enum */ 2737 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR1 0xb /* enum */ 2738 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR1 0xc /* enum */ 2739 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR2 0xd /* enum */ 2740 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR2 0xe /* enum */ 2741 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR3 0xf /* enum */ 2742 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR3 0x10 /* enum */ 2743 2744 /* MC_CMD_AOE_OUT_TEMPERATURES msgresponse */ 2745 #define MC_CMD_AOE_OUT_TEMPERATURES_LEN 40 2746 /* Set of temperatures */ 2747 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_OFST 0 2748 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_LEN 4 2749 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_NUM 10 2750 /* enum: The first set of enum values are for Modena code. */ 2751 #define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_0 0x0 2752 #define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_1 0x1 /* enum */ 2753 #define MC_CMD_AOE_OUT_TEMPERATURES_IND_0 0x2 /* enum */ 2754 #define MC_CMD_AOE_OUT_TEMPERATURES_IND_1 0x3 /* enum */ 2755 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO1 0x4 /* enum */ 2756 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO2 0x5 /* enum */ 2757 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO3 0x6 /* enum */ 2758 #define MC_CMD_AOE_OUT_TEMPERATURES_PSU 0x7 /* enum */ 2759 #define MC_CMD_AOE_OUT_TEMPERATURES_FPGA 0x8 /* enum */ 2760 #define MC_CMD_AOE_OUT_TEMPERATURES_SIENA 0x9 /* enum */ 2761 /* enum: The second set of enum values are for Sorrento code. */ 2762 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_0 0x0 2763 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_1 0x1 /* enum */ 2764 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_0 0x2 /* enum */ 2765 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_1 0x3 /* enum */ 2766 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_0 0x4 /* enum */ 2767 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_1 0x5 /* enum */ 2768 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_FPGA 0x6 /* enum */ 2769 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY0 0x7 /* enum */ 2770 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY1 0x8 /* enum */ 2771 2772 /* MC_CMD_AOE_OUT_CPLD_READ msgresponse */ 2773 #define MC_CMD_AOE_OUT_CPLD_READ_LEN 4 2774 /* The value read from the CPLD */ 2775 #define MC_CMD_AOE_OUT_CPLD_READ_VALUE_OFST 0 2776 #define MC_CMD_AOE_OUT_CPLD_READ_VALUE_LEN 4 2777 2778 /* MC_CMD_AOE_OUT_FAN_FAILURES msgresponse */ 2779 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMIN 4 2780 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMAX 252 2781 #define MC_CMD_AOE_OUT_FAN_FAILURES_LEN(num) (0+4*(num)) 2782 /* Failure counts for each fan */ 2783 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_OFST 0 2784 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_LEN 4 2785 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MINNUM 1 2786 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MAXNUM 63 2787 2788 /* MC_CMD_AOE_OUT_CPLD_REPROGRAM msgresponse */ 2789 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_LEN 4 2790 /* Results of status command (only) */ 2791 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_OFST 0 2792 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_LEN 4 2793 2794 /* MC_CMD_AOE_OUT_POWER_OFF msgresponse */ 2795 #define MC_CMD_AOE_OUT_POWER_OFF_LEN 0 2796 2797 /* MC_CMD_AOE_OUT_POWER_ON msgresponse */ 2798 #define MC_CMD_AOE_OUT_POWER_ON_LEN 0 2799 2800 /* MC_CMD_AOE_OUT_LOAD msgresponse */ 2801 #define MC_CMD_AOE_OUT_LOAD_LEN 0 2802 2803 /* MC_CMD_AOE_OUT_MAC_STATS_DMA msgresponse */ 2804 #define MC_CMD_AOE_OUT_MAC_STATS_DMA_LEN 0 2805 2806 /* MC_CMD_AOE_OUT_MAC_STATS_NO_DMA msgresponse: See MC_CMD_MAC_STATS_OUT_NO_DMA 2807 * for details 2808 */ 2809 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) 2810 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_OFST 0 2811 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LEN 8 2812 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_OFST 0 2813 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_OFST 4 2814 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS 2815 2816 /* MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO msgresponse */ 2817 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMIN 5 2818 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX 252 2819 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LEN(num) (4+1*(num)) 2820 /* in bytes */ 2821 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_OFST 0 2822 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_LEN 4 2823 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_OFST 4 2824 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_LEN 1 2825 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MINNUM 1 2826 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MAXNUM 248 2827 2828 /* MC_CMD_AOE_OUT_JTAG_WRITE msgresponse */ 2829 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMIN 12 2830 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMAX 252 2831 #define MC_CMD_AOE_OUT_JTAG_WRITE_LEN(num) (8+4*(num)) 2832 /* Used to align the in and out data blocks so the MC can re-use the cmd */ 2833 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_OFST 0 2834 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_LEN 4 2835 /* out bytes */ 2836 #define MC_CMD_AOE_OUT_JTAG_WRITE_PAD_OFST 4 2837 #define MC_CMD_AOE_OUT_JTAG_WRITE_PAD_LEN 4 2838 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_OFST 8 2839 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_LEN 4 2840 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MINNUM 1 2841 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MAXNUM 61 2842 2843 /* MC_CMD_AOE_OUT_FPGA_ACCESS msgresponse */ 2844 #define MC_CMD_AOE_OUT_FPGA_ACCESS_LEN 0 2845 2846 /* MC_CMD_AOE_OUT_DDR msgresponse */ 2847 #define MC_CMD_AOE_OUT_DDR_LENMIN 17 2848 #define MC_CMD_AOE_OUT_DDR_LENMAX 252 2849 #define MC_CMD_AOE_OUT_DDR_LEN(num) (16+1*(num)) 2850 /* Information on the module. */ 2851 #define MC_CMD_AOE_OUT_DDR_FLAGS_OFST 0 2852 #define MC_CMD_AOE_OUT_DDR_FLAGS_LEN 4 2853 #define MC_CMD_AOE_OUT_DDR_PRESENT_LBN 0 2854 #define MC_CMD_AOE_OUT_DDR_PRESENT_WIDTH 1 2855 #define MC_CMD_AOE_OUT_DDR_POWERED_LBN 1 2856 #define MC_CMD_AOE_OUT_DDR_POWERED_WIDTH 1 2857 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_LBN 2 2858 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_WIDTH 1 2859 #define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_LBN 3 2860 #define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_WIDTH 1 2861 /* Memory size, in MB. */ 2862 #define MC_CMD_AOE_OUT_DDR_CAPACITY_OFST 4 2863 #define MC_CMD_AOE_OUT_DDR_CAPACITY_LEN 4 2864 /* The memory type, as reported from SPD information */ 2865 #define MC_CMD_AOE_OUT_DDR_TYPE_OFST 8 2866 #define MC_CMD_AOE_OUT_DDR_TYPE_LEN 4 2867 /* Nominal voltage of the module (as applied) */ 2868 #define MC_CMD_AOE_OUT_DDR_VOLTAGE_OFST 12 2869 #define MC_CMD_AOE_OUT_DDR_VOLTAGE_LEN 4 2870 /* SPD data read from the module */ 2871 #define MC_CMD_AOE_OUT_DDR_SPD_OFST 16 2872 #define MC_CMD_AOE_OUT_DDR_SPD_LEN 1 2873 #define MC_CMD_AOE_OUT_DDR_SPD_MINNUM 1 2874 #define MC_CMD_AOE_OUT_DDR_SPD_MAXNUM 236 2875 2876 /* MC_CMD_AOE_OUT_SET_MTU_OFFSET msgresponse */ 2877 #define MC_CMD_AOE_OUT_SET_MTU_OFFSET_LEN 0 2878 2879 /* MC_CMD_AOE_OUT_LINK_STATE msgresponse */ 2880 #define MC_CMD_AOE_OUT_LINK_STATE_LEN 0 2881 2882 /* MC_CMD_AOE_OUT_SIENA_STATS msgresponse */ 2883 #define MC_CMD_AOE_OUT_SIENA_STATS_LEN 0 2884 2885 /* MC_CMD_AOE_OUT_ASIC_STATS msgresponse */ 2886 #define MC_CMD_AOE_OUT_ASIC_STATS_LEN 0 2887 2888 /* MC_CMD_AOE_OUT_FC msgresponse */ 2889 #define MC_CMD_AOE_OUT_FC_LEN 0 2890 2891 /* MC_CMD_AOE_OUT_GET_ASIC_PORTS msgresponse */ 2892 #define MC_CMD_AOE_OUT_GET_ASIC_PORTS_LEN 4 2893 /* get the number of internal ports */ 2894 #define MC_CMD_AOE_OUT_GET_ASIC_PORTS_COUNT_PORTS_OFST 0 2895 #define MC_CMD_AOE_OUT_GET_ASIC_PORTS_COUNT_PORTS_LEN 4 2896 2897 /* MC_CMD_AOE_OUT_DDR_ECC_STATUS msgresponse */ 2898 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_LEN 8 2899 /* Flags describing status info on the module. */ 2900 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_OFST 0 2901 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_LEN 4 2902 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_LBN 0 2903 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_WIDTH 1 2904 /* DDR ECC status on the module. */ 2905 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_OFST 4 2906 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_LEN 4 2907 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_LBN 0 2908 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_WIDTH 1 2909 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_LBN 1 2910 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_WIDTH 1 2911 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_LBN 2 2912 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_WIDTH 1 2913 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_LBN 8 2914 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_WIDTH 8 2915 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_LBN 16 2916 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_WIDTH 8 2917 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_LBN 24 2918 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_WIDTH 8 2919 2920 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_READ msgresponse */ 2921 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_LEN 4 2922 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_DATA_OFST 0 2923 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_DATA_LEN 4 2924 2925 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE msgresponse */ 2926 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE_LEN 0 2927 2928 /* MC_CMD_AOE_OUT_MC_SPI_MASTER msgresponse */ 2929 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_LEN 0 2930 2931 /* MC_CMD_AOE_OUT_FC_BOOT msgresponse */ 2932 #define MC_CMD_AOE_OUT_FC_BOOT_LEN 0 2933 2934 #endif /* _SYS_EFX_REGS_MCDI_AOE_H */ 2935