1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright 2008-2013 Solarflare Communications Inc. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #ifndef _SIENA_MC_DRIVER_PCOL_H 31 #define _SIENA_MC_DRIVER_PCOL_H 32 33 34 /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */ 35 /* Power-on reset state */ 36 #define MC_FW_STATE_POR (1) 37 /* If this is set in MC_RESET_STATE_REG then it should be 38 * possible to jump into IMEM without loading code from flash. */ 39 #define MC_FW_WARM_BOOT_OK (2) 40 /* The MC main image has started to boot. */ 41 #define MC_FW_STATE_BOOTING (4) 42 /* The Scheduler has started. */ 43 #define MC_FW_STATE_SCHED (8) 44 /* If this is set in MC_RESET_STATE_REG then it should be 45 * possible to jump into IMEM without loading code from flash. 46 * Unlike a warm boot, assume DMEM has been reloaded, so that 47 * the MC persistent data must be reinitialised. */ 48 #define MC_FW_TEPID_BOOT_OK (16) 49 /* We have entered the main firmware via recovery mode. This 50 * means that MC persistent data must be reinitialised, but that 51 * we shouldn't touch PCIe config. */ 52 #define MC_FW_RECOVERY_MODE_PCIE_INIT_OK (32) 53 /* BIST state has been initialized */ 54 #define MC_FW_BIST_INIT_OK (128) 55 56 /* Siena MC shared memmory offsets */ 57 /* The 'doorbell' addresses are hard-wired to alert the MC when written */ 58 #define MC_SMEM_P0_DOORBELL_OFST 0x000 59 #define MC_SMEM_P1_DOORBELL_OFST 0x004 60 /* The rest of these are firmware-defined */ 61 #define MC_SMEM_P0_PDU_OFST 0x008 62 #define MC_SMEM_P1_PDU_OFST 0x108 63 #define MC_SMEM_PDU_LEN 0x100 64 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0 65 #define MC_SMEM_P0_STATUS_OFST 0x7f8 66 #define MC_SMEM_P1_STATUS_OFST 0x7fc 67 68 /* Values to be written to the per-port status dword in shared 69 * memory on reboot and assert */ 70 #define MC_STATUS_DWORD_REBOOT (0xb007b007) 71 #define MC_STATUS_DWORD_ASSERT (0xdeaddead) 72 73 /* Check whether an mcfw version (in host order) belongs to a bootloader */ 74 #define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007) 75 76 /* The current version of the MCDI protocol. 77 * 78 * Note that the ROM burnt into the card only talks V0, so at the very 79 * least every driver must support version 0 and MCDI_PCOL_VERSION 80 */ 81 #ifdef WITH_MCDI_V2 82 #define MCDI_PCOL_VERSION 2 83 #else 84 #define MCDI_PCOL_VERSION 1 85 #endif 86 87 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */ 88 89 /* MCDI version 1 90 * 91 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit 92 * structure, filled in by the client. 93 * 94 * 0 7 8 16 20 22 23 24 31 95 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS | 96 * | | | 97 * | | \--- Response 98 * | \------- Error 99 * \------------------------------ Resync (always set) 100 * 101 * The client writes it's request into MC shared memory, and rings the 102 * doorbell. Each request is completed by either by the MC writting 103 * back into shared memory, or by writting out an event. 104 * 105 * All MCDI commands support completion by shared memory response. Each 106 * request may also contain additional data (accounted for by HEADER.LEN), 107 * and some response's may also contain additional data (again, accounted 108 * for by HEADER.LEN). 109 * 110 * Some MCDI commands support completion by event, in which any associated 111 * response data is included in the event. 112 * 113 * The protocol requires one response to be delivered for every request, a 114 * request should not be sent unless the response for the previous request 115 * has been received (either by polling shared memory, or by receiving 116 * an event). 117 */ 118 119 /** Request/Response structure */ 120 #define MCDI_HEADER_OFST 0 121 #define MCDI_HEADER_CODE_LBN 0 122 #define MCDI_HEADER_CODE_WIDTH 7 123 #define MCDI_HEADER_RESYNC_LBN 7 124 #define MCDI_HEADER_RESYNC_WIDTH 1 125 #define MCDI_HEADER_DATALEN_LBN 8 126 #define MCDI_HEADER_DATALEN_WIDTH 8 127 #define MCDI_HEADER_SEQ_LBN 16 128 #define MCDI_HEADER_SEQ_WIDTH 4 129 #define MCDI_HEADER_RSVD_LBN 20 130 #define MCDI_HEADER_RSVD_WIDTH 1 131 #define MCDI_HEADER_NOT_EPOCH_LBN 21 132 #define MCDI_HEADER_NOT_EPOCH_WIDTH 1 133 #define MCDI_HEADER_ERROR_LBN 22 134 #define MCDI_HEADER_ERROR_WIDTH 1 135 #define MCDI_HEADER_RESPONSE_LBN 23 136 #define MCDI_HEADER_RESPONSE_WIDTH 1 137 #define MCDI_HEADER_XFLAGS_LBN 24 138 #define MCDI_HEADER_XFLAGS_WIDTH 8 139 /* Request response using event */ 140 #define MCDI_HEADER_XFLAGS_EVREQ 0x01 141 /* Request (and signal) early doorbell return */ 142 #define MCDI_HEADER_XFLAGS_DBRET 0x02 143 144 /* Maximum number of payload bytes */ 145 #define MCDI_CTL_SDU_LEN_MAX_V1 0xfc 146 #define MCDI_CTL_SDU_LEN_MAX_V2 0x400 147 148 #ifdef WITH_MCDI_V2 149 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2 150 #else 151 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V1 152 #endif 153 154 155 /* The MC can generate events for two reasons: 156 * - To advance a shared memory request if XFLAGS_EVREQ was set 157 * - As a notification (link state, i2c event), controlled 158 * via MC_CMD_LOG_CTRL 159 * 160 * Both events share a common structure: 161 * 162 * 0 32 33 36 44 52 60 163 * | Data | Cont | Level | Src | Code | Rsvd | 164 * | 165 * \ There is another event pending in this notification 166 * 167 * If Code==CMDDONE, then the fields are further interpreted as: 168 * 169 * - LEVEL==INFO Command succeeded 170 * - LEVEL==ERR Command failed 171 * 172 * 0 8 16 24 32 173 * | Seq | Datalen | Errno | Rsvd | 174 * 175 * These fields are taken directly out of the standard MCDI header, i.e., 176 * LEVEL==ERR, Datalen == 0 => Reboot 177 * 178 * Events can be squirted out of the UART (using LOG_CTRL) without a 179 * MCDI header. An event can be distinguished from a MCDI response by 180 * examining the first byte which is 0xc0. This corresponds to the 181 * non-existent MCDI command MC_CMD_DEBUG_LOG. 182 * 183 * 0 7 8 184 * | command | Resync | = 0xc0 185 * 186 * Since the event is written in big-endian byte order, this works 187 * providing bits 56-63 of the event are 0xc0. 188 * 189 * 56 60 63 190 * | Rsvd | Code | = 0xc0 191 * 192 * Which means for convenience the event code is 0xc for all MC 193 * generated events. 194 */ 195 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc 196 197 198 /* Operation not permitted. */ 199 #define MC_CMD_ERR_EPERM 1 200 /* Non-existent command target */ 201 #define MC_CMD_ERR_ENOENT 2 202 /* assert() has killed the MC */ 203 #define MC_CMD_ERR_EINTR 4 204 /* I/O failure */ 205 #define MC_CMD_ERR_EIO 5 206 /* Already exists */ 207 #define MC_CMD_ERR_EEXIST 6 208 /* Try again */ 209 #define MC_CMD_ERR_EAGAIN 11 210 /* Out of memory */ 211 #define MC_CMD_ERR_ENOMEM 12 212 /* Caller does not hold required locks */ 213 #define MC_CMD_ERR_EACCES 13 214 /* Resource is currently unavailable (e.g. lock contention) */ 215 #define MC_CMD_ERR_EBUSY 16 216 /* No such device */ 217 #define MC_CMD_ERR_ENODEV 19 218 /* Invalid argument to target */ 219 #define MC_CMD_ERR_EINVAL 22 220 /* Broken pipe */ 221 #define MC_CMD_ERR_EPIPE 32 222 /* Read-only */ 223 #define MC_CMD_ERR_EROFS 30 224 /* Out of range */ 225 #define MC_CMD_ERR_ERANGE 34 226 /* Non-recursive resource is already acquired */ 227 #define MC_CMD_ERR_EDEADLK 35 228 /* Operation not implemented */ 229 #define MC_CMD_ERR_ENOSYS 38 230 /* Operation timed out */ 231 #define MC_CMD_ERR_ETIME 62 232 /* Link has been severed */ 233 #define MC_CMD_ERR_ENOLINK 67 234 /* Protocol error */ 235 #define MC_CMD_ERR_EPROTO 71 236 /* Operation not supported */ 237 #define MC_CMD_ERR_ENOTSUP 95 238 /* Address not available */ 239 #define MC_CMD_ERR_EADDRNOTAVAIL 99 240 /* Not connected */ 241 #define MC_CMD_ERR_ENOTCONN 107 242 /* Operation already in progress */ 243 #define MC_CMD_ERR_EALREADY 114 244 245 /* Resource allocation failed. */ 246 #define MC_CMD_ERR_ALLOC_FAIL 0x1000 247 /* V-adaptor not found. */ 248 #define MC_CMD_ERR_NO_VADAPTOR 0x1001 249 /* EVB port not found. */ 250 #define MC_CMD_ERR_NO_EVB_PORT 0x1002 251 /* V-switch not found. */ 252 #define MC_CMD_ERR_NO_VSWITCH 0x1003 253 /* Too many VLAN tags. */ 254 #define MC_CMD_ERR_VLAN_LIMIT 0x1004 255 /* Bad PCI function number. */ 256 #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005 257 /* Invalid VLAN mode. */ 258 #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006 259 /* Invalid v-switch type. */ 260 #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007 261 /* Invalid v-port type. */ 262 #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008 263 /* MAC address exists. */ 264 #define MC_CMD_ERR_MAC_EXIST 0x1009 265 /* Slave core not present */ 266 #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a 267 /* The datapath is disabled. */ 268 #define MC_CMD_ERR_DATAPATH_DISABLED 0x100b 269 /* The requesting client is not a function */ 270 #define MC_CMD_ERR_CLIENT_NOT_FN 0x100c 271 /* The requested operation might require the 272 command to be passed between MCs, and the 273 transport doesn't support that. Should 274 only ever been seen over the UART. */ 275 #define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d 276 /* VLAN tag(s) exists */ 277 #define MC_CMD_ERR_VLAN_EXIST 0x100e 278 /* No MAC address assigned to an EVB port */ 279 #define MC_CMD_ERR_NO_MAC_ADDR 0x100f 280 /* Notifies the driver that the request has been relayed 281 * to an admin function for authorization. The driver should 282 * wait for a PROXY_RESPONSE event and then resend its request. 283 * This error code is followed by a 32-bit handle that 284 * helps matching it with the respective PROXY_RESPONSE event. */ 285 #define MC_CMD_ERR_PROXY_PENDING 0x1010 286 #define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4 287 /* The request cannot be passed for authorization because 288 * another request from the same function is currently being 289 * authorized. The drvier should try again later. */ 290 #define MC_CMD_ERR_PROXY_INPROGRESS 0x1011 291 /* Returned by MC_CMD_PROXY_COMPLETE if the caller is not the function 292 * that has enabled proxying or BLOCK_INDEX points to a function that 293 * doesn't await an authorization. */ 294 #define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012 295 /* This code is currently only used internally in FW. Its meaning is that 296 * an operation failed due to lack of SR-IOV privilege. 297 * Normally it is translated to EPERM by send_cmd_err(), 298 * but it may also be used to trigger some special mechanism 299 * for handling such case, e.g. to relay the failed request 300 * to a designated admin function for authorization. */ 301 #define MC_CMD_ERR_NO_PRIVILEGE 0x1013 302 /* Workaround 26807 could not be turned on/off because some functions 303 * have already installed filters. See the comment at 304 * MC_CMD_WORKAROUND_BUG26807. 305 * May also returned for other operations such as sub-variant switching. */ 306 #define MC_CMD_ERR_FILTERS_PRESENT 0x1014 307 /* The clock whose frequency you've attempted to set set 308 * doesn't exist on this NIC */ 309 #define MC_CMD_ERR_NO_CLOCK 0x1015 310 /* Returned by MC_CMD_TESTASSERT if the action that should 311 * have caused an assertion failed to do so. */ 312 #define MC_CMD_ERR_UNREACHABLE 0x1016 313 /* This command needs to be processed in the background but there were no 314 * resources to do so. Send it again after a command has completed. */ 315 #define MC_CMD_ERR_QUEUE_FULL 0x1017 316 /* The operation could not be completed because the PCIe link has gone 317 * away. This error code is never expected to be returned over the TLP 318 * transport. */ 319 #define MC_CMD_ERR_NO_PCIE 0x1018 320 /* The operation could not be completed because the datapath has gone 321 * away. This is distinct from MC_CMD_ERR_DATAPATH_DISABLED in that the 322 * datapath absence may be temporary*/ 323 #define MC_CMD_ERR_NO_DATAPATH 0x1019 324 /* The operation could not complete because some VIs are allocated */ 325 #define MC_CMD_ERR_VIS_PRESENT 0x101a 326 /* The operation could not complete because some PIO buffers are allocated */ 327 #define MC_CMD_ERR_PIOBUFS_PRESENT 0x101b 328 329 #define MC_CMD_ERR_CODE_OFST 0 330 331 /* We define 8 "escape" commands to allow 332 for command number space extension */ 333 334 #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78 335 #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79 336 #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A 337 #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B 338 #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C 339 #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D 340 #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E 341 #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F 342 343 /* Vectors in the boot ROM */ 344 /* Point to the copycode entry point. */ 345 #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4) 346 #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4) 347 #define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4) 348 /* Points to the recovery mode entry point. Misnamed but kept for compatibility. */ 349 #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4) 350 #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4) 351 #define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4) 352 /* Points to the recovery mode entry point. Same as above, but the right name. */ 353 #define SIENA_MC_BOOTROM_RECOVERY_VEC (0x800 - 2 * 0x4) 354 #define HUNT_MC_BOOTROM_RECOVERY_VEC (0x8000 - 2 * 0x4) 355 #define MEDFORD_MC_BOOTROM_RECOVERY_VEC (0x10000 - 2 * 0x4) 356 357 /* Points to noflash mode entry point. */ 358 #define MEDFORD_MC_BOOTROM_REAL_NOFLASH_VEC (0x10000 - 4 * 0x4) 359 360 /* The command set exported by the boot ROM (MCDI v0) */ 361 #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \ 362 (1 << MC_CMD_READ32) | \ 363 (1 << MC_CMD_WRITE32) | \ 364 (1 << MC_CMD_COPYCODE) | \ 365 (1 << MC_CMD_GET_VERSION), \ 366 0, 0, 0 } 367 368 #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \ 369 (MC_CMD_SENSOR_ENTRY_OFST + (_x)) 370 371 #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \ 372 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 373 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \ 374 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 375 376 #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \ 377 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 378 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \ 379 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 380 381 #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \ 382 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 383 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \ 384 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 385 386 /* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default 387 * stack ID (which must be in the range 1-255) along with an EVB port ID. 388 */ 389 #define EVB_STACK_ID(n) (((n) & 0xff) << 16) 390 391 392 #ifdef WITH_MCDI_V2 393 394 /* Version 2 adds an optional argument to error returns: the errno value 395 * may be followed by the (0-based) number of the first argument that 396 * could not be processed. 397 */ 398 #define MC_CMD_ERR_ARG_OFST 4 399 400 /* No space */ 401 #define MC_CMD_ERR_ENOSPC 28 402 403 #endif 404 405 /* MCDI_EVENT structuredef */ 406 #define MCDI_EVENT_LEN 8 407 #define MCDI_EVENT_CONT_LBN 32 408 #define MCDI_EVENT_CONT_WIDTH 1 409 #define MCDI_EVENT_LEVEL_LBN 33 410 #define MCDI_EVENT_LEVEL_WIDTH 3 411 /* enum: Info. */ 412 #define MCDI_EVENT_LEVEL_INFO 0x0 413 /* enum: Warning. */ 414 #define MCDI_EVENT_LEVEL_WARN 0x1 415 /* enum: Error. */ 416 #define MCDI_EVENT_LEVEL_ERR 0x2 417 /* enum: Fatal. */ 418 #define MCDI_EVENT_LEVEL_FATAL 0x3 419 #define MCDI_EVENT_DATA_OFST 0 420 #define MCDI_EVENT_DATA_LEN 4 421 #define MCDI_EVENT_CMDDONE_SEQ_LBN 0 422 #define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8 423 #define MCDI_EVENT_CMDDONE_DATALEN_LBN 8 424 #define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8 425 #define MCDI_EVENT_CMDDONE_ERRNO_LBN 16 426 #define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8 427 #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0 428 #define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16 429 #define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16 430 #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4 431 /* enum: Link is down or link speed could not be determined */ 432 #define MCDI_EVENT_LINKCHANGE_SPEED_UNKNOWN 0x0 433 /* enum: 100Mbs */ 434 #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1 435 /* enum: 1Gbs */ 436 #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2 437 /* enum: 10Gbs */ 438 #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3 439 /* enum: 40Gbs */ 440 #define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4 441 /* enum: 25Gbs */ 442 #define MCDI_EVENT_LINKCHANGE_SPEED_25G 0x5 443 /* enum: 50Gbs */ 444 #define MCDI_EVENT_LINKCHANGE_SPEED_50G 0x6 445 /* enum: 100Gbs */ 446 #define MCDI_EVENT_LINKCHANGE_SPEED_100G 0x7 447 #define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20 448 #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4 449 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24 450 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8 451 #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0 452 #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8 453 #define MCDI_EVENT_SENSOREVT_STATE_LBN 8 454 #define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8 455 #define MCDI_EVENT_SENSOREVT_VALUE_LBN 16 456 #define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16 457 #define MCDI_EVENT_FWALERT_DATA_LBN 8 458 #define MCDI_EVENT_FWALERT_DATA_WIDTH 24 459 #define MCDI_EVENT_FWALERT_REASON_LBN 0 460 #define MCDI_EVENT_FWALERT_REASON_WIDTH 8 461 /* enum: SRAM Access. */ 462 #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 463 #define MCDI_EVENT_FLR_VF_LBN 0 464 #define MCDI_EVENT_FLR_VF_WIDTH 8 465 #define MCDI_EVENT_TX_ERR_TXQ_LBN 0 466 #define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12 467 #define MCDI_EVENT_TX_ERR_TYPE_LBN 12 468 #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4 469 /* enum: Descriptor loader reported failure */ 470 #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1 471 /* enum: Descriptor ring empty and no EOP seen for packet */ 472 #define MCDI_EVENT_TX_ERR_NO_EOP 0x2 473 /* enum: Overlength packet */ 474 #define MCDI_EVENT_TX_ERR_2BIG 0x3 475 /* enum: Malformed option descriptor */ 476 #define MCDI_EVENT_TX_BAD_OPTDESC 0x5 477 /* enum: Option descriptor part way through a packet */ 478 #define MCDI_EVENT_TX_OPT_IN_PKT 0x8 479 /* enum: DMA or PIO data access error */ 480 #define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9 481 #define MCDI_EVENT_TX_ERR_INFO_LBN 16 482 #define MCDI_EVENT_TX_ERR_INFO_WIDTH 16 483 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12 484 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1 485 #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0 486 #define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12 487 #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0 488 #define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8 489 /* enum: PLL lost lock */ 490 #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 491 /* enum: Filter overflow (PDMA) */ 492 #define MCDI_EVENT_PTP_ERR_FILTER 0x2 493 /* enum: FIFO overflow (FPGA) */ 494 #define MCDI_EVENT_PTP_ERR_FIFO 0x3 495 /* enum: Merge queue overflow */ 496 #define MCDI_EVENT_PTP_ERR_QUEUE 0x4 497 #define MCDI_EVENT_AOE_ERR_TYPE_LBN 0 498 #define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8 499 /* enum: AOE failed to load - no valid image? */ 500 #define MCDI_EVENT_AOE_NO_LOAD 0x1 501 /* enum: AOE FC reported an exception */ 502 #define MCDI_EVENT_AOE_FC_ASSERT 0x2 503 /* enum: AOE FC watchdogged */ 504 #define MCDI_EVENT_AOE_FC_WATCHDOG 0x3 505 /* enum: AOE FC failed to start */ 506 #define MCDI_EVENT_AOE_FC_NO_START 0x4 507 /* enum: Generic AOE fault - likely to have been reported via other means too 508 * but intended for use by aoex driver. 509 */ 510 #define MCDI_EVENT_AOE_FAULT 0x5 511 /* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */ 512 #define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6 513 /* enum: AOE loaded successfully */ 514 #define MCDI_EVENT_AOE_LOAD 0x7 515 /* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */ 516 #define MCDI_EVENT_AOE_DMA 0x8 517 /* enum: AOE byteblaster connected/disconnected (Connection status in 518 * AOE_ERR_DATA) 519 */ 520 #define MCDI_EVENT_AOE_BYTEBLASTER 0x9 521 /* enum: DDR ECC status update */ 522 #define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa 523 /* enum: PTP status update */ 524 #define MCDI_EVENT_AOE_PTP_STATUS 0xb 525 /* enum: FPGA header incorrect */ 526 #define MCDI_EVENT_AOE_FPGA_LOAD_HEADER_ERR 0xc 527 /* enum: FPGA Powered Off due to error in powering up FPGA */ 528 #define MCDI_EVENT_AOE_FPGA_POWER_OFF 0xd 529 /* enum: AOE FPGA load failed due to MC to MUM communication failure */ 530 #define MCDI_EVENT_AOE_FPGA_LOAD_FAILED 0xe 531 /* enum: Notify that invalid flash type detected */ 532 #define MCDI_EVENT_AOE_INVALID_FPGA_FLASH_TYPE 0xf 533 /* enum: Notify that the attempt to run FPGA Controller firmware timedout */ 534 #define MCDI_EVENT_AOE_FC_RUN_TIMEDOUT 0x10 535 /* enum: Failure to probe one or more FPGA boot flash chips */ 536 #define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_INVALID 0x11 537 /* enum: FPGA boot-flash contains an invalid image header */ 538 #define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_HDR_INVALID 0x12 539 /* enum: Failed to program clocks required by the FPGA */ 540 #define MCDI_EVENT_AOE_FPGA_CLOCKS_PROGRAM_FAILED 0x13 541 /* enum: Notify that FPGA Controller is alive to serve MCDI requests */ 542 #define MCDI_EVENT_AOE_FC_RUNNING 0x14 543 #define MCDI_EVENT_AOE_ERR_DATA_LBN 8 544 #define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8 545 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_LBN 8 546 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_WIDTH 8 547 /* enum: FC Assert happened, but the register information is not available */ 548 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_SEEN 0x0 549 /* enum: The register information for FC Assert is ready for readinng by driver 550 */ 551 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_DATA_READY 0x1 552 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_LBN 8 553 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_WIDTH 8 554 /* enum: Reading from NV failed */ 555 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_NV_READ_FAIL 0x0 556 /* enum: Invalid Magic Number if FPGA header */ 557 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_MAGIC_FAIL 0x1 558 /* enum: Invalid Silicon type detected in header */ 559 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_SILICON_TYPE 0x2 560 /* enum: Unsupported VRatio */ 561 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_VRATIO 0x3 562 /* enum: Unsupported DDR Type */ 563 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_TYPE 0x4 564 /* enum: DDR Voltage out of supported range */ 565 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_VOLTAGE 0x5 566 /* enum: Unsupported DDR speed */ 567 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SPEED 0x6 568 /* enum: Unsupported DDR size */ 569 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SIZE 0x7 570 /* enum: Unsupported DDR rank */ 571 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_RANK 0x8 572 #define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_LBN 8 573 #define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_WIDTH 8 574 /* enum: Primary boot flash */ 575 #define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_PRIMARY 0x0 576 /* enum: Secondary boot flash */ 577 #define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_SECONDARY 0x1 578 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_LBN 8 579 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_WIDTH 8 580 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_LBN 8 581 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_WIDTH 8 582 #define MCDI_EVENT_RX_ERR_RXQ_LBN 0 583 #define MCDI_EVENT_RX_ERR_RXQ_WIDTH 12 584 #define MCDI_EVENT_RX_ERR_TYPE_LBN 12 585 #define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4 586 #define MCDI_EVENT_RX_ERR_INFO_LBN 16 587 #define MCDI_EVENT_RX_ERR_INFO_WIDTH 16 588 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12 589 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1 590 #define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0 591 #define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12 592 #define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0 593 #define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16 594 #define MCDI_EVENT_MUM_ERR_TYPE_LBN 0 595 #define MCDI_EVENT_MUM_ERR_TYPE_WIDTH 8 596 /* enum: MUM failed to load - no valid image? */ 597 #define MCDI_EVENT_MUM_NO_LOAD 0x1 598 /* enum: MUM f/w reported an exception */ 599 #define MCDI_EVENT_MUM_ASSERT 0x2 600 /* enum: MUM not kicking watchdog */ 601 #define MCDI_EVENT_MUM_WATCHDOG 0x3 602 #define MCDI_EVENT_MUM_ERR_DATA_LBN 8 603 #define MCDI_EVENT_MUM_ERR_DATA_WIDTH 8 604 #define MCDI_EVENT_DBRET_SEQ_LBN 0 605 #define MCDI_EVENT_DBRET_SEQ_WIDTH 8 606 #define MCDI_EVENT_SUC_ERR_TYPE_LBN 0 607 #define MCDI_EVENT_SUC_ERR_TYPE_WIDTH 8 608 /* enum: Corrupted or bad SUC application. */ 609 #define MCDI_EVENT_SUC_BAD_APP 0x1 610 /* enum: SUC application reported an assert. */ 611 #define MCDI_EVENT_SUC_ASSERT 0x2 612 /* enum: SUC application reported an exception. */ 613 #define MCDI_EVENT_SUC_EXCEPTION 0x3 614 /* enum: SUC watchdog timer expired. */ 615 #define MCDI_EVENT_SUC_WATCHDOG 0x4 616 #define MCDI_EVENT_SUC_ERR_ADDRESS_LBN 8 617 #define MCDI_EVENT_SUC_ERR_ADDRESS_WIDTH 24 618 #define MCDI_EVENT_SUC_ERR_DATA_LBN 8 619 #define MCDI_EVENT_SUC_ERR_DATA_WIDTH 24 620 #define MCDI_EVENT_DATA_LBN 0 621 #define MCDI_EVENT_DATA_WIDTH 32 622 #define MCDI_EVENT_SRC_LBN 36 623 #define MCDI_EVENT_SRC_WIDTH 8 624 #define MCDI_EVENT_EV_CODE_LBN 60 625 #define MCDI_EVENT_EV_CODE_WIDTH 4 626 #define MCDI_EVENT_CODE_LBN 44 627 #define MCDI_EVENT_CODE_WIDTH 8 628 /* enum: Event generated by host software */ 629 #define MCDI_EVENT_SW_EVENT 0x0 630 /* enum: Bad assert. */ 631 #define MCDI_EVENT_CODE_BADSSERT 0x1 632 /* enum: PM Notice. */ 633 #define MCDI_EVENT_CODE_PMNOTICE 0x2 634 /* enum: Command done. */ 635 #define MCDI_EVENT_CODE_CMDDONE 0x3 636 /* enum: Link change. */ 637 #define MCDI_EVENT_CODE_LINKCHANGE 0x4 638 /* enum: Sensor Event. */ 639 #define MCDI_EVENT_CODE_SENSOREVT 0x5 640 /* enum: Schedule error. */ 641 #define MCDI_EVENT_CODE_SCHEDERR 0x6 642 /* enum: Reboot. */ 643 #define MCDI_EVENT_CODE_REBOOT 0x7 644 /* enum: Mac stats DMA. */ 645 #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8 646 /* enum: Firmware alert. */ 647 #define MCDI_EVENT_CODE_FWALERT 0x9 648 /* enum: Function level reset. */ 649 #define MCDI_EVENT_CODE_FLR 0xa 650 /* enum: Transmit error */ 651 #define MCDI_EVENT_CODE_TX_ERR 0xb 652 /* enum: Tx flush has completed */ 653 #define MCDI_EVENT_CODE_TX_FLUSH 0xc 654 /* enum: PTP packet received timestamp */ 655 #define MCDI_EVENT_CODE_PTP_RX 0xd 656 /* enum: PTP NIC failure */ 657 #define MCDI_EVENT_CODE_PTP_FAULT 0xe 658 /* enum: PTP PPS event */ 659 #define MCDI_EVENT_CODE_PTP_PPS 0xf 660 /* enum: Rx flush has completed */ 661 #define MCDI_EVENT_CODE_RX_FLUSH 0x10 662 /* enum: Receive error */ 663 #define MCDI_EVENT_CODE_RX_ERR 0x11 664 /* enum: AOE fault */ 665 #define MCDI_EVENT_CODE_AOE 0x12 666 /* enum: Network port calibration failed (VCAL). */ 667 #define MCDI_EVENT_CODE_VCAL_FAIL 0x13 668 /* enum: HW PPS event */ 669 #define MCDI_EVENT_CODE_HW_PPS 0x14 670 /* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and 671 * a different format) 672 */ 673 #define MCDI_EVENT_CODE_MC_REBOOT 0x15 674 /* enum: the MC has detected a parity error */ 675 #define MCDI_EVENT_CODE_PAR_ERR 0x16 676 /* enum: the MC has detected a correctable error */ 677 #define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17 678 /* enum: the MC has detected an uncorrectable error */ 679 #define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18 680 /* enum: The MC has entered offline BIST mode */ 681 #define MCDI_EVENT_CODE_MC_BIST 0x19 682 /* enum: PTP tick event providing current NIC time */ 683 #define MCDI_EVENT_CODE_PTP_TIME 0x1a 684 /* enum: MUM fault */ 685 #define MCDI_EVENT_CODE_MUM 0x1b 686 /* enum: notify the designated PF of a new authorization request */ 687 #define MCDI_EVENT_CODE_PROXY_REQUEST 0x1c 688 /* enum: notify a function that awaits an authorization that its request has 689 * been processed and it may now resend the command 690 */ 691 #define MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d 692 /* enum: MCDI command accepted. New commands can be issued but this command is 693 * not done yet. 694 */ 695 #define MCDI_EVENT_CODE_DBRET 0x1e 696 /* enum: The MC has detected a fault on the SUC */ 697 #define MCDI_EVENT_CODE_SUC 0x1f 698 /* enum: Artificial event generated by host and posted via MC for test 699 * purposes. 700 */ 701 #define MCDI_EVENT_CODE_TESTGEN 0xfa 702 #define MCDI_EVENT_CMDDONE_DATA_OFST 0 703 #define MCDI_EVENT_CMDDONE_DATA_LEN 4 704 #define MCDI_EVENT_CMDDONE_DATA_LBN 0 705 #define MCDI_EVENT_CMDDONE_DATA_WIDTH 32 706 #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0 707 #define MCDI_EVENT_LINKCHANGE_DATA_LEN 4 708 #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0 709 #define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32 710 #define MCDI_EVENT_SENSOREVT_DATA_OFST 0 711 #define MCDI_EVENT_SENSOREVT_DATA_LEN 4 712 #define MCDI_EVENT_SENSOREVT_DATA_LBN 0 713 #define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32 714 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0 715 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LEN 4 716 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0 717 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32 718 #define MCDI_EVENT_TX_ERR_DATA_OFST 0 719 #define MCDI_EVENT_TX_ERR_DATA_LEN 4 720 #define MCDI_EVENT_TX_ERR_DATA_LBN 0 721 #define MCDI_EVENT_TX_ERR_DATA_WIDTH 32 722 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of 723 * timestamp 724 */ 725 #define MCDI_EVENT_PTP_SECONDS_OFST 0 726 #define MCDI_EVENT_PTP_SECONDS_LEN 4 727 #define MCDI_EVENT_PTP_SECONDS_LBN 0 728 #define MCDI_EVENT_PTP_SECONDS_WIDTH 32 729 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of 730 * timestamp 731 */ 732 #define MCDI_EVENT_PTP_MAJOR_OFST 0 733 #define MCDI_EVENT_PTP_MAJOR_LEN 4 734 #define MCDI_EVENT_PTP_MAJOR_LBN 0 735 #define MCDI_EVENT_PTP_MAJOR_WIDTH 32 736 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field 737 * of timestamp 738 */ 739 #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0 740 #define MCDI_EVENT_PTP_NANOSECONDS_LEN 4 741 #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0 742 #define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32 743 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of 744 * timestamp 745 */ 746 #define MCDI_EVENT_PTP_MINOR_OFST 0 747 #define MCDI_EVENT_PTP_MINOR_LEN 4 748 #define MCDI_EVENT_PTP_MINOR_LBN 0 749 #define MCDI_EVENT_PTP_MINOR_WIDTH 32 750 /* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet 751 */ 752 #define MCDI_EVENT_PTP_UUID_OFST 0 753 #define MCDI_EVENT_PTP_UUID_LEN 4 754 #define MCDI_EVENT_PTP_UUID_LBN 0 755 #define MCDI_EVENT_PTP_UUID_WIDTH 32 756 #define MCDI_EVENT_RX_ERR_DATA_OFST 0 757 #define MCDI_EVENT_RX_ERR_DATA_LEN 4 758 #define MCDI_EVENT_RX_ERR_DATA_LBN 0 759 #define MCDI_EVENT_RX_ERR_DATA_WIDTH 32 760 #define MCDI_EVENT_PAR_ERR_DATA_OFST 0 761 #define MCDI_EVENT_PAR_ERR_DATA_LEN 4 762 #define MCDI_EVENT_PAR_ERR_DATA_LBN 0 763 #define MCDI_EVENT_PAR_ERR_DATA_WIDTH 32 764 #define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0 765 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LEN 4 766 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0 767 #define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32 768 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0 769 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LEN 4 770 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0 771 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32 772 /* For CODE_PTP_TIME events, the major value of the PTP clock */ 773 #define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0 774 #define MCDI_EVENT_PTP_TIME_MAJOR_LEN 4 775 #define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0 776 #define MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32 777 /* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */ 778 #define MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36 779 #define MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8 780 /* For CODE_PTP_TIME events, most significant bits of the minor value of the 781 * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_19. 782 */ 783 #define MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_LBN 36 784 #define MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_WIDTH 8 785 /* For CODE_PTP_TIME events where report sync status is enabled, indicates 786 * whether the NIC clock has ever been set 787 */ 788 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_LBN 36 789 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1 790 /* For CODE_PTP_TIME events where report sync status is enabled, indicates 791 * whether the NIC and System clocks are in sync 792 */ 793 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_LBN 37 794 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1 795 /* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of 796 * the minor value of the PTP clock 797 */ 798 #define MCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 38 799 #define MCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 6 800 /* For CODE_PTP_TIME events, most significant bits of the minor value of the 801 * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_21. 802 */ 803 #define MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_LBN 38 804 #define MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_WIDTH 6 805 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0 806 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LEN 4 807 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0 808 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 32 809 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0 810 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LEN 4 811 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0 812 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 32 813 /* Zero means that the request has been completed or authorized, and the driver 814 * should resend it. A non-zero value means that the authorization has been 815 * denied, and gives the reason. Typically it will be EPERM. 816 */ 817 #define MCDI_EVENT_PROXY_RESPONSE_RC_LBN 36 818 #define MCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 8 819 #define MCDI_EVENT_DBRET_DATA_OFST 0 820 #define MCDI_EVENT_DBRET_DATA_LEN 4 821 #define MCDI_EVENT_DBRET_DATA_LBN 0 822 #define MCDI_EVENT_DBRET_DATA_WIDTH 32 823 824 /* FCDI_EVENT structuredef */ 825 #define FCDI_EVENT_LEN 8 826 #define FCDI_EVENT_CONT_LBN 32 827 #define FCDI_EVENT_CONT_WIDTH 1 828 #define FCDI_EVENT_LEVEL_LBN 33 829 #define FCDI_EVENT_LEVEL_WIDTH 3 830 /* enum: Info. */ 831 #define FCDI_EVENT_LEVEL_INFO 0x0 832 /* enum: Warning. */ 833 #define FCDI_EVENT_LEVEL_WARN 0x1 834 /* enum: Error. */ 835 #define FCDI_EVENT_LEVEL_ERR 0x2 836 /* enum: Fatal. */ 837 #define FCDI_EVENT_LEVEL_FATAL 0x3 838 #define FCDI_EVENT_DATA_OFST 0 839 #define FCDI_EVENT_DATA_LEN 4 840 #define FCDI_EVENT_LINK_STATE_STATUS_LBN 0 841 #define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1 842 #define FCDI_EVENT_LINK_DOWN 0x0 /* enum */ 843 #define FCDI_EVENT_LINK_UP 0x1 /* enum */ 844 #define FCDI_EVENT_DATA_LBN 0 845 #define FCDI_EVENT_DATA_WIDTH 32 846 #define FCDI_EVENT_SRC_LBN 36 847 #define FCDI_EVENT_SRC_WIDTH 8 848 #define FCDI_EVENT_EV_CODE_LBN 60 849 #define FCDI_EVENT_EV_CODE_WIDTH 4 850 #define FCDI_EVENT_CODE_LBN 44 851 #define FCDI_EVENT_CODE_WIDTH 8 852 /* enum: The FC was rebooted. */ 853 #define FCDI_EVENT_CODE_REBOOT 0x1 854 /* enum: Bad assert. */ 855 #define FCDI_EVENT_CODE_ASSERT 0x2 856 /* enum: DDR3 test result. */ 857 #define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3 858 /* enum: Link status. */ 859 #define FCDI_EVENT_CODE_LINK_STATE 0x4 860 /* enum: A timed read is ready to be serviced. */ 861 #define FCDI_EVENT_CODE_TIMED_READ 0x5 862 /* enum: One or more PPS IN events */ 863 #define FCDI_EVENT_CODE_PPS_IN 0x6 864 /* enum: Tick event from PTP clock */ 865 #define FCDI_EVENT_CODE_PTP_TICK 0x7 866 /* enum: ECC error counters */ 867 #define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8 868 /* enum: Current status of PTP */ 869 #define FCDI_EVENT_CODE_PTP_STATUS 0x9 870 /* enum: Port id config to map MC-FC port idx */ 871 #define FCDI_EVENT_CODE_PORT_CONFIG 0xa 872 /* enum: Boot result or error code */ 873 #define FCDI_EVENT_CODE_BOOT_RESULT 0xb 874 #define FCDI_EVENT_REBOOT_SRC_LBN 36 875 #define FCDI_EVENT_REBOOT_SRC_WIDTH 8 876 #define FCDI_EVENT_REBOOT_FC_FW 0x0 /* enum */ 877 #define FCDI_EVENT_REBOOT_FC_BOOTLOADER 0x1 /* enum */ 878 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0 879 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LEN 4 880 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0 881 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32 882 #define FCDI_EVENT_ASSERT_TYPE_LBN 36 883 #define FCDI_EVENT_ASSERT_TYPE_WIDTH 8 884 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36 885 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8 886 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0 887 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LEN 4 888 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0 889 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32 890 #define FCDI_EVENT_LINK_STATE_DATA_OFST 0 891 #define FCDI_EVENT_LINK_STATE_DATA_LEN 4 892 #define FCDI_EVENT_LINK_STATE_DATA_LBN 0 893 #define FCDI_EVENT_LINK_STATE_DATA_WIDTH 32 894 #define FCDI_EVENT_PTP_STATE_OFST 0 895 #define FCDI_EVENT_PTP_STATE_LEN 4 896 #define FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */ 897 #define FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */ 898 #define FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */ 899 #define FCDI_EVENT_PTP_STATE_LBN 0 900 #define FCDI_EVENT_PTP_STATE_WIDTH 32 901 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36 902 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8 903 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0 904 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LEN 4 905 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0 906 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32 907 /* Index of MC port being referred to */ 908 #define FCDI_EVENT_PORT_CONFIG_SRC_LBN 36 909 #define FCDI_EVENT_PORT_CONFIG_SRC_WIDTH 8 910 /* FC Port index that matches the MC port index in SRC */ 911 #define FCDI_EVENT_PORT_CONFIG_DATA_OFST 0 912 #define FCDI_EVENT_PORT_CONFIG_DATA_LEN 4 913 #define FCDI_EVENT_PORT_CONFIG_DATA_LBN 0 914 #define FCDI_EVENT_PORT_CONFIG_DATA_WIDTH 32 915 #define FCDI_EVENT_BOOT_RESULT_OFST 0 916 #define FCDI_EVENT_BOOT_RESULT_LEN 4 917 /* Enum values, see field(s): */ 918 /* MC_CMD_AOE/MC_CMD_AOE_OUT_INFO/FC_BOOT_RESULT */ 919 #define FCDI_EVENT_BOOT_RESULT_LBN 0 920 #define FCDI_EVENT_BOOT_RESULT_WIDTH 32 921 922 /* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events 923 * to the MC. Note that this structure | is overlayed over a normal FCDI event 924 * such that bits 32-63 containing | event code, level, source etc remain the 925 * same. In this case the data | field of the header is defined to be the 926 * number of timestamps 927 */ 928 #define FCDI_EXTENDED_EVENT_PPS_LENMIN 16 929 #define FCDI_EXTENDED_EVENT_PPS_LENMAX 248 930 #define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num)) 931 /* Number of timestamps following */ 932 #define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0 933 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LEN 4 934 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0 935 #define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32 936 /* Seconds field of a timestamp record */ 937 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8 938 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LEN 4 939 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64 940 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32 941 /* Nanoseconds field of a timestamp record */ 942 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12 943 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LEN 4 944 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96 945 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32 946 /* Timestamp records comprising the event */ 947 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8 948 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8 949 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8 950 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12 951 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1 952 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30 953 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64 954 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64 955 956 /* MUM_EVENT structuredef */ 957 #define MUM_EVENT_LEN 8 958 #define MUM_EVENT_CONT_LBN 32 959 #define MUM_EVENT_CONT_WIDTH 1 960 #define MUM_EVENT_LEVEL_LBN 33 961 #define MUM_EVENT_LEVEL_WIDTH 3 962 /* enum: Info. */ 963 #define MUM_EVENT_LEVEL_INFO 0x0 964 /* enum: Warning. */ 965 #define MUM_EVENT_LEVEL_WARN 0x1 966 /* enum: Error. */ 967 #define MUM_EVENT_LEVEL_ERR 0x2 968 /* enum: Fatal. */ 969 #define MUM_EVENT_LEVEL_FATAL 0x3 970 #define MUM_EVENT_DATA_OFST 0 971 #define MUM_EVENT_DATA_LEN 4 972 #define MUM_EVENT_SENSOR_ID_LBN 0 973 #define MUM_EVENT_SENSOR_ID_WIDTH 8 974 /* Enum values, see field(s): */ 975 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 976 #define MUM_EVENT_SENSOR_STATE_LBN 8 977 #define MUM_EVENT_SENSOR_STATE_WIDTH 8 978 #define MUM_EVENT_PORT_PHY_READY_LBN 0 979 #define MUM_EVENT_PORT_PHY_READY_WIDTH 1 980 #define MUM_EVENT_PORT_PHY_LINK_UP_LBN 1 981 #define MUM_EVENT_PORT_PHY_LINK_UP_WIDTH 1 982 #define MUM_EVENT_PORT_PHY_TX_LOL_LBN 2 983 #define MUM_EVENT_PORT_PHY_TX_LOL_WIDTH 1 984 #define MUM_EVENT_PORT_PHY_RX_LOL_LBN 3 985 #define MUM_EVENT_PORT_PHY_RX_LOL_WIDTH 1 986 #define MUM_EVENT_PORT_PHY_TX_LOS_LBN 4 987 #define MUM_EVENT_PORT_PHY_TX_LOS_WIDTH 1 988 #define MUM_EVENT_PORT_PHY_RX_LOS_LBN 5 989 #define MUM_EVENT_PORT_PHY_RX_LOS_WIDTH 1 990 #define MUM_EVENT_PORT_PHY_TX_FAULT_LBN 6 991 #define MUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 1 992 #define MUM_EVENT_DATA_LBN 0 993 #define MUM_EVENT_DATA_WIDTH 32 994 #define MUM_EVENT_SRC_LBN 36 995 #define MUM_EVENT_SRC_WIDTH 8 996 #define MUM_EVENT_EV_CODE_LBN 60 997 #define MUM_EVENT_EV_CODE_WIDTH 4 998 #define MUM_EVENT_CODE_LBN 44 999 #define MUM_EVENT_CODE_WIDTH 8 1000 /* enum: The MUM was rebooted. */ 1001 #define MUM_EVENT_CODE_REBOOT 0x1 1002 /* enum: Bad assert. */ 1003 #define MUM_EVENT_CODE_ASSERT 0x2 1004 /* enum: Sensor failure. */ 1005 #define MUM_EVENT_CODE_SENSOR 0x3 1006 /* enum: Link fault has been asserted, or has cleared. */ 1007 #define MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4 1008 #define MUM_EVENT_SENSOR_DATA_OFST 0 1009 #define MUM_EVENT_SENSOR_DATA_LEN 4 1010 #define MUM_EVENT_SENSOR_DATA_LBN 0 1011 #define MUM_EVENT_SENSOR_DATA_WIDTH 32 1012 #define MUM_EVENT_PORT_PHY_FLAGS_OFST 0 1013 #define MUM_EVENT_PORT_PHY_FLAGS_LEN 4 1014 #define MUM_EVENT_PORT_PHY_FLAGS_LBN 0 1015 #define MUM_EVENT_PORT_PHY_FLAGS_WIDTH 32 1016 #define MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0 1017 #define MUM_EVENT_PORT_PHY_COPPER_LEN_LEN 4 1018 #define MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0 1019 #define MUM_EVENT_PORT_PHY_COPPER_LEN_WIDTH 32 1020 #define MUM_EVENT_PORT_PHY_CAPS_OFST 0 1021 #define MUM_EVENT_PORT_PHY_CAPS_LEN 4 1022 #define MUM_EVENT_PORT_PHY_CAPS_LBN 0 1023 #define MUM_EVENT_PORT_PHY_CAPS_WIDTH 32 1024 #define MUM_EVENT_PORT_PHY_TECH_OFST 0 1025 #define MUM_EVENT_PORT_PHY_TECH_LEN 4 1026 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */ 1027 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */ 1028 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */ 1029 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */ 1030 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */ 1031 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */ 1032 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */ 1033 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */ 1034 #define MUM_EVENT_PORT_PHY_TECH_LBN 0 1035 #define MUM_EVENT_PORT_PHY_TECH_WIDTH 32 1036 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_LBN 36 1037 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 4 1038 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */ 1039 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */ 1040 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */ 1041 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */ 1042 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */ 1043 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_LBN 40 1044 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4 1045 1046 1047 /***********************************/ 1048 /* MC_CMD_READ32 1049 * Read multiple 32byte words from MC memory. Note - this command really 1050 * belongs to INSECURE category but is required by shmboot. The command handler 1051 * has additional checks to reject insecure calls. 1052 */ 1053 #define MC_CMD_READ32 0x1 1054 #undef MC_CMD_0x1_PRIVILEGE_CTG 1055 1056 #define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1057 1058 /* MC_CMD_READ32_IN msgrequest */ 1059 #define MC_CMD_READ32_IN_LEN 8 1060 #define MC_CMD_READ32_IN_ADDR_OFST 0 1061 #define MC_CMD_READ32_IN_ADDR_LEN 4 1062 #define MC_CMD_READ32_IN_NUMWORDS_OFST 4 1063 #define MC_CMD_READ32_IN_NUMWORDS_LEN 4 1064 1065 /* MC_CMD_READ32_OUT msgresponse */ 1066 #define MC_CMD_READ32_OUT_LENMIN 4 1067 #define MC_CMD_READ32_OUT_LENMAX 252 1068 #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num)) 1069 #define MC_CMD_READ32_OUT_BUFFER_OFST 0 1070 #define MC_CMD_READ32_OUT_BUFFER_LEN 4 1071 #define MC_CMD_READ32_OUT_BUFFER_MINNUM 1 1072 #define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63 1073 1074 1075 /***********************************/ 1076 /* MC_CMD_WRITE32 1077 * Write multiple 32byte words to MC memory. 1078 */ 1079 #define MC_CMD_WRITE32 0x2 1080 #undef MC_CMD_0x2_PRIVILEGE_CTG 1081 1082 #define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_INSECURE 1083 1084 /* MC_CMD_WRITE32_IN msgrequest */ 1085 #define MC_CMD_WRITE32_IN_LENMIN 8 1086 #define MC_CMD_WRITE32_IN_LENMAX 252 1087 #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num)) 1088 #define MC_CMD_WRITE32_IN_ADDR_OFST 0 1089 #define MC_CMD_WRITE32_IN_ADDR_LEN 4 1090 #define MC_CMD_WRITE32_IN_BUFFER_OFST 4 1091 #define MC_CMD_WRITE32_IN_BUFFER_LEN 4 1092 #define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1 1093 #define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62 1094 1095 /* MC_CMD_WRITE32_OUT msgresponse */ 1096 #define MC_CMD_WRITE32_OUT_LEN 0 1097 1098 1099 /***********************************/ 1100 /* MC_CMD_COPYCODE 1101 * Copy MC code between two locations and jump. Note - this command really 1102 * belongs to INSECURE category but is required by shmboot. The command handler 1103 * has additional checks to reject insecure calls. 1104 */ 1105 #define MC_CMD_COPYCODE 0x3 1106 #undef MC_CMD_0x3_PRIVILEGE_CTG 1107 1108 #define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 1109 1110 /* MC_CMD_COPYCODE_IN msgrequest */ 1111 #define MC_CMD_COPYCODE_IN_LEN 16 1112 /* Source address 1113 * 1114 * The main image should be entered via a copy of a single word from and to a 1115 * magic address, which controls various aspects of the boot. The magic address 1116 * is a bitfield, with each bit as documented below. 1117 */ 1118 #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0 1119 #define MC_CMD_COPYCODE_IN_SRC_ADDR_LEN 4 1120 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */ 1121 #define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000 1122 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and 1123 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED (see below) 1124 */ 1125 #define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0 1126 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT, 1127 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED and BOOT_MAGIC_IGNORE_CONFIG (see 1128 * below) 1129 */ 1130 #define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc 1131 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 17 1132 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1 1133 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 2 1134 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1 1135 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 3 1136 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1 1137 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4 1138 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1 1139 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 5 1140 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1 1141 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_LBN 6 1142 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_WIDTH 1 1143 /* Destination address */ 1144 #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4 1145 #define MC_CMD_COPYCODE_IN_DEST_ADDR_LEN 4 1146 #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8 1147 #define MC_CMD_COPYCODE_IN_NUMWORDS_LEN 4 1148 /* Address of where to jump after copy. */ 1149 #define MC_CMD_COPYCODE_IN_JUMP_OFST 12 1150 #define MC_CMD_COPYCODE_IN_JUMP_LEN 4 1151 /* enum: Control should return to the caller rather than jumping */ 1152 #define MC_CMD_COPYCODE_JUMP_NONE 0x1 1153 1154 /* MC_CMD_COPYCODE_OUT msgresponse */ 1155 #define MC_CMD_COPYCODE_OUT_LEN 0 1156 1157 1158 /***********************************/ 1159 /* MC_CMD_SET_FUNC 1160 * Select function for function-specific commands. 1161 */ 1162 #define MC_CMD_SET_FUNC 0x4 1163 #undef MC_CMD_0x4_PRIVILEGE_CTG 1164 1165 #define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_INSECURE 1166 1167 /* MC_CMD_SET_FUNC_IN msgrequest */ 1168 #define MC_CMD_SET_FUNC_IN_LEN 4 1169 /* Set function */ 1170 #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0 1171 #define MC_CMD_SET_FUNC_IN_FUNC_LEN 4 1172 1173 /* MC_CMD_SET_FUNC_OUT msgresponse */ 1174 #define MC_CMD_SET_FUNC_OUT_LEN 0 1175 1176 1177 /***********************************/ 1178 /* MC_CMD_GET_BOOT_STATUS 1179 * Get the instruction address from which the MC booted. 1180 */ 1181 #define MC_CMD_GET_BOOT_STATUS 0x5 1182 #undef MC_CMD_0x5_PRIVILEGE_CTG 1183 1184 #define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1185 1186 /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */ 1187 #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0 1188 1189 /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */ 1190 #define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8 1191 /* ?? */ 1192 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0 1193 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_LEN 4 1194 /* enum: indicates that the MC wasn't flash booted */ 1195 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef 1196 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4 1197 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_LEN 4 1198 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0 1199 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1 1200 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1 1201 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1 1202 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2 1203 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1 1204 1205 1206 /***********************************/ 1207 /* MC_CMD_GET_ASSERTS 1208 * Get (and optionally clear) the current assertion status. Only 1209 * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other 1210 * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS 1211 */ 1212 #define MC_CMD_GET_ASSERTS 0x6 1213 #undef MC_CMD_0x6_PRIVILEGE_CTG 1214 1215 #define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1216 1217 /* MC_CMD_GET_ASSERTS_IN msgrequest */ 1218 #define MC_CMD_GET_ASSERTS_IN_LEN 4 1219 /* Set to clear assertion */ 1220 #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0 1221 #define MC_CMD_GET_ASSERTS_IN_CLEAR_LEN 4 1222 1223 /* MC_CMD_GET_ASSERTS_OUT msgresponse */ 1224 #define MC_CMD_GET_ASSERTS_OUT_LEN 140 1225 /* Assertion status flag. */ 1226 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0 1227 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_LEN 4 1228 /* enum: No assertions have failed. */ 1229 #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 1230 /* enum: A system-level assertion has failed. */ 1231 #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 1232 /* enum: A thread-level assertion has failed. */ 1233 #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 1234 /* enum: The system was reset by the watchdog. */ 1235 #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 1236 /* enum: An illegal address trap stopped the system (huntington and later) */ 1237 #define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 1238 /* Failing PC value */ 1239 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4 1240 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_LEN 4 1241 /* Saved GP regs */ 1242 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8 1243 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4 1244 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31 1245 /* enum: A magic value hinting that the value in this register at the time of 1246 * the failure has likely been lost. 1247 */ 1248 #define MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 1249 /* Failing thread address */ 1250 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132 1251 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_LEN 4 1252 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136 1253 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_LEN 4 1254 1255 1256 /***********************************/ 1257 /* MC_CMD_LOG_CTRL 1258 * Configure the output stream for log events such as link state changes, 1259 * sensor notifications and MCDI completions 1260 */ 1261 #define MC_CMD_LOG_CTRL 0x7 1262 #undef MC_CMD_0x7_PRIVILEGE_CTG 1263 1264 #define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1265 1266 /* MC_CMD_LOG_CTRL_IN msgrequest */ 1267 #define MC_CMD_LOG_CTRL_IN_LEN 8 1268 /* Log destination */ 1269 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0 1270 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_LEN 4 1271 /* enum: UART. */ 1272 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1 1273 /* enum: Event queue. */ 1274 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2 1275 /* Legacy argument. Must be zero. */ 1276 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4 1277 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_LEN 4 1278 1279 /* MC_CMD_LOG_CTRL_OUT msgresponse */ 1280 #define MC_CMD_LOG_CTRL_OUT_LEN 0 1281 1282 1283 /***********************************/ 1284 /* MC_CMD_GET_VERSION 1285 * Get version information about the MC firmware. 1286 */ 1287 #define MC_CMD_GET_VERSION 0x8 1288 #undef MC_CMD_0x8_PRIVILEGE_CTG 1289 1290 #define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1291 1292 /* MC_CMD_GET_VERSION_IN msgrequest */ 1293 #define MC_CMD_GET_VERSION_IN_LEN 0 1294 1295 /* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */ 1296 #define MC_CMD_GET_VERSION_EXT_IN_LEN 4 1297 /* placeholder, set to 0 */ 1298 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0 1299 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_LEN 4 1300 1301 /* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */ 1302 #define MC_CMD_GET_VERSION_V0_OUT_LEN 4 1303 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 1304 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 1305 /* enum: Reserved version number to indicate "any" version. */ 1306 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff 1307 /* enum: Bootrom version value for Siena. */ 1308 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000 1309 /* enum: Bootrom version value for Huntington. */ 1310 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001 1311 /* enum: Bootrom version value for Medford2. */ 1312 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_MEDFORD2_BOOTROM 0xb0070002 1313 1314 /* MC_CMD_GET_VERSION_OUT msgresponse */ 1315 #define MC_CMD_GET_VERSION_OUT_LEN 32 1316 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 1317 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */ 1318 /* Enum values, see field(s): */ 1319 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 1320 #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4 1321 #define MC_CMD_GET_VERSION_OUT_PCOL_LEN 4 1322 /* 128bit mask of functions supported by the current firmware */ 1323 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8 1324 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16 1325 #define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24 1326 #define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8 1327 #define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24 1328 #define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28 1329 1330 /* MC_CMD_GET_VERSION_EXT_OUT msgresponse */ 1331 #define MC_CMD_GET_VERSION_EXT_OUT_LEN 48 1332 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 1333 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */ 1334 /* Enum values, see field(s): */ 1335 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 1336 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4 1337 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_LEN 4 1338 /* 128bit mask of functions supported by the current firmware */ 1339 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8 1340 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16 1341 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24 1342 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8 1343 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24 1344 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28 1345 /* extra info */ 1346 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32 1347 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16 1348 1349 1350 /***********************************/ 1351 /* MC_CMD_PTP 1352 * Perform PTP operation 1353 */ 1354 #define MC_CMD_PTP 0xb 1355 #undef MC_CMD_0xb_PRIVILEGE_CTG 1356 1357 #define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1358 1359 /* MC_CMD_PTP_IN msgrequest */ 1360 #define MC_CMD_PTP_IN_LEN 1 1361 /* PTP operation code */ 1362 #define MC_CMD_PTP_IN_OP_OFST 0 1363 #define MC_CMD_PTP_IN_OP_LEN 1 1364 /* enum: Enable PTP packet timestamping operation. */ 1365 #define MC_CMD_PTP_OP_ENABLE 0x1 1366 /* enum: Disable PTP packet timestamping operation. */ 1367 #define MC_CMD_PTP_OP_DISABLE 0x2 1368 /* enum: Send a PTP packet. This operation is used on Siena and Huntington. 1369 * From Medford onwards it is not supported: on those platforms PTP transmit 1370 * timestamping is done using the fast path. 1371 */ 1372 #define MC_CMD_PTP_OP_TRANSMIT 0x3 1373 /* enum: Read the current NIC time. */ 1374 #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4 1375 /* enum: Get the current PTP status. Note that the clock frequency returned (in 1376 * Hz) is rounded to the nearest MHz (e.g. 666000000 for 666666666). 1377 */ 1378 #define MC_CMD_PTP_OP_STATUS 0x5 1379 /* enum: Adjust the PTP NIC's time. */ 1380 #define MC_CMD_PTP_OP_ADJUST 0x6 1381 /* enum: Synchronize host and NIC time. */ 1382 #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7 1383 /* enum: Basic manufacturing tests. Siena PTP adapters only. */ 1384 #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8 1385 /* enum: Packet based manufacturing tests. Siena PTP adapters only. */ 1386 #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9 1387 /* enum: Reset some of the PTP related statistics */ 1388 #define MC_CMD_PTP_OP_RESET_STATS 0xa 1389 /* enum: Debug operations to MC. */ 1390 #define MC_CMD_PTP_OP_DEBUG 0xb 1391 /* enum: Read an FPGA register. Siena PTP adapters only. */ 1392 #define MC_CMD_PTP_OP_FPGAREAD 0xc 1393 /* enum: Write an FPGA register. Siena PTP adapters only. */ 1394 #define MC_CMD_PTP_OP_FPGAWRITE 0xd 1395 /* enum: Apply an offset to the NIC clock */ 1396 #define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe 1397 /* enum: Change the frequency correction applied to the NIC clock */ 1398 #define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf 1399 /* enum: Set the MC packet filter VLAN tags for received PTP packets. 1400 * Deprecated for Huntington onwards. 1401 */ 1402 #define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10 1403 /* enum: Set the MC packet filter UUID for received PTP packets. Deprecated for 1404 * Huntington onwards. 1405 */ 1406 #define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11 1407 /* enum: Set the MC packet filter Domain for received PTP packets. Deprecated 1408 * for Huntington onwards. 1409 */ 1410 #define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12 1411 /* enum: Set the clock source. Required for snapper tests on Huntington and 1412 * Medford. Not implemented for Siena or Medford2. 1413 */ 1414 #define MC_CMD_PTP_OP_SET_CLK_SRC 0x13 1415 /* enum: Reset value of Timer Reg. Not implemented. */ 1416 #define MC_CMD_PTP_OP_RST_CLK 0x14 1417 /* enum: Enable the forwarding of PPS events to the host */ 1418 #define MC_CMD_PTP_OP_PPS_ENABLE 0x15 1419 /* enum: Get the time format used by this NIC for PTP operations */ 1420 #define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16 1421 /* enum: Get the clock attributes. NOTE- extended version of 1422 * MC_CMD_PTP_OP_GET_TIME_FORMAT 1423 */ 1424 #define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16 1425 /* enum: Get corrections that should be applied to the various different 1426 * timestamps 1427 */ 1428 #define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17 1429 /* enum: Subscribe to receive periodic time events indicating the current NIC 1430 * time 1431 */ 1432 #define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18 1433 /* enum: Unsubscribe to stop receiving time events */ 1434 #define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19 1435 /* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS 1436 * input on the same NIC. Siena PTP adapters only. 1437 */ 1438 #define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a 1439 /* enum: Set the PTP sync status. Status is used by firmware to report to event 1440 * subscribers. 1441 */ 1442 #define MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b 1443 /* enum: Above this for future use. */ 1444 #define MC_CMD_PTP_OP_MAX 0x1c 1445 1446 /* MC_CMD_PTP_IN_ENABLE msgrequest */ 1447 #define MC_CMD_PTP_IN_ENABLE_LEN 16 1448 #define MC_CMD_PTP_IN_CMD_OFST 0 1449 #define MC_CMD_PTP_IN_CMD_LEN 4 1450 #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4 1451 #define MC_CMD_PTP_IN_PERIPH_ID_LEN 4 1452 /* Not used. Events are always sent to function relative queue 0. */ 1453 #define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8 1454 #define MC_CMD_PTP_IN_ENABLE_QUEUE_LEN 4 1455 /* PTP timestamping mode. Not used from Huntington onwards. */ 1456 #define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12 1457 #define MC_CMD_PTP_IN_ENABLE_MODE_LEN 4 1458 /* enum: PTP, version 1 */ 1459 #define MC_CMD_PTP_MODE_V1 0x0 1460 /* enum: PTP, version 1, with VLAN headers - deprecated */ 1461 #define MC_CMD_PTP_MODE_V1_VLAN 0x1 1462 /* enum: PTP, version 2 */ 1463 #define MC_CMD_PTP_MODE_V2 0x2 1464 /* enum: PTP, version 2, with VLAN headers - deprecated */ 1465 #define MC_CMD_PTP_MODE_V2_VLAN 0x3 1466 /* enum: PTP, version 2, with improved UUID filtering */ 1467 #define MC_CMD_PTP_MODE_V2_ENHANCED 0x4 1468 /* enum: FCoE (seconds and microseconds) */ 1469 #define MC_CMD_PTP_MODE_FCOE 0x5 1470 1471 /* MC_CMD_PTP_IN_DISABLE msgrequest */ 1472 #define MC_CMD_PTP_IN_DISABLE_LEN 8 1473 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1474 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1475 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1476 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1477 1478 /* MC_CMD_PTP_IN_TRANSMIT msgrequest */ 1479 #define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13 1480 #define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252 1481 #define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num)) 1482 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1483 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1484 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1485 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1486 /* Transmit packet length */ 1487 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8 1488 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_LEN 4 1489 /* Transmit packet data */ 1490 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12 1491 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1 1492 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1 1493 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240 1494 1495 /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */ 1496 #define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8 1497 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1498 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1499 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1500 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1501 1502 /* MC_CMD_PTP_IN_READ_NIC_TIME_V2 msgrequest */ 1503 #define MC_CMD_PTP_IN_READ_NIC_TIME_V2_LEN 8 1504 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1505 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1506 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1507 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1508 1509 /* MC_CMD_PTP_IN_STATUS msgrequest */ 1510 #define MC_CMD_PTP_IN_STATUS_LEN 8 1511 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1512 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1513 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1514 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1515 1516 /* MC_CMD_PTP_IN_ADJUST msgrequest */ 1517 #define MC_CMD_PTP_IN_ADJUST_LEN 24 1518 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1519 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1520 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1521 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1522 /* Frequency adjustment 40 bit fixed point ns */ 1523 #define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8 1524 #define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8 1525 #define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8 1526 #define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12 1527 /* enum: Number of fractional bits in frequency adjustment */ 1528 #define MC_CMD_PTP_IN_ADJUST_BITS 0x28 1529 /* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ 1530 * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES 1531 * field. 1532 */ 1533 #define MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c 1534 /* Time adjustment in seconds */ 1535 #define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16 1536 #define MC_CMD_PTP_IN_ADJUST_SECONDS_LEN 4 1537 /* Time adjustment major value */ 1538 #define MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16 1539 #define MC_CMD_PTP_IN_ADJUST_MAJOR_LEN 4 1540 /* Time adjustment in nanoseconds */ 1541 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20 1542 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_LEN 4 1543 /* Time adjustment minor value */ 1544 #define MC_CMD_PTP_IN_ADJUST_MINOR_OFST 20 1545 #define MC_CMD_PTP_IN_ADJUST_MINOR_LEN 4 1546 1547 /* MC_CMD_PTP_IN_ADJUST_V2 msgrequest */ 1548 #define MC_CMD_PTP_IN_ADJUST_V2_LEN 28 1549 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1550 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1551 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1552 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1553 /* Frequency adjustment 40 bit fixed point ns */ 1554 #define MC_CMD_PTP_IN_ADJUST_V2_FREQ_OFST 8 1555 #define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LEN 8 1556 #define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_OFST 8 1557 #define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_OFST 12 1558 /* enum: Number of fractional bits in frequency adjustment */ 1559 /* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */ 1560 /* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ 1561 * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES 1562 * field. 1563 */ 1564 /* MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c */ 1565 /* Time adjustment in seconds */ 1566 #define MC_CMD_PTP_IN_ADJUST_V2_SECONDS_OFST 16 1567 #define MC_CMD_PTP_IN_ADJUST_V2_SECONDS_LEN 4 1568 /* Time adjustment major value */ 1569 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_OFST 16 1570 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_LEN 4 1571 /* Time adjustment in nanoseconds */ 1572 #define MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_OFST 20 1573 #define MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_LEN 4 1574 /* Time adjustment minor value */ 1575 #define MC_CMD_PTP_IN_ADJUST_V2_MINOR_OFST 20 1576 #define MC_CMD_PTP_IN_ADJUST_V2_MINOR_LEN 4 1577 /* Upper 32bits of major time offset adjustment */ 1578 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_OFST 24 1579 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_LEN 4 1580 1581 /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */ 1582 #define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20 1583 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1584 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1585 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1586 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1587 /* Number of time readings to capture */ 1588 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8 1589 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_LEN 4 1590 /* Host address in which to write "synchronization started" indication (64 1591 * bits) 1592 */ 1593 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12 1594 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8 1595 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12 1596 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16 1597 1598 /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */ 1599 #define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8 1600 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1601 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1602 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1603 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1604 1605 /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */ 1606 #define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12 1607 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1608 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1609 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1610 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1611 /* Enable or disable packet testing */ 1612 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8 1613 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_LEN 4 1614 1615 /* MC_CMD_PTP_IN_RESET_STATS msgrequest: Reset PTP statistics */ 1616 #define MC_CMD_PTP_IN_RESET_STATS_LEN 8 1617 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1618 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1619 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1620 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1621 1622 /* MC_CMD_PTP_IN_DEBUG msgrequest */ 1623 #define MC_CMD_PTP_IN_DEBUG_LEN 12 1624 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1625 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1626 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1627 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1628 /* Debug operations */ 1629 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8 1630 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_LEN 4 1631 1632 /* MC_CMD_PTP_IN_FPGAREAD msgrequest */ 1633 #define MC_CMD_PTP_IN_FPGAREAD_LEN 16 1634 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1635 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1636 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1637 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1638 #define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8 1639 #define MC_CMD_PTP_IN_FPGAREAD_ADDR_LEN 4 1640 #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12 1641 #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_LEN 4 1642 1643 /* MC_CMD_PTP_IN_FPGAWRITE msgrequest */ 1644 #define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13 1645 #define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252 1646 #define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num)) 1647 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1648 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1649 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1650 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1651 #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8 1652 #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_LEN 4 1653 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12 1654 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1 1655 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1 1656 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240 1657 1658 /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */ 1659 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16 1660 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1661 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1662 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1663 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1664 /* Time adjustment in seconds */ 1665 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8 1666 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_LEN 4 1667 /* Time adjustment major value */ 1668 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8 1669 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_LEN 4 1670 /* Time adjustment in nanoseconds */ 1671 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12 1672 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_LEN 4 1673 /* Time adjustment minor value */ 1674 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12 1675 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_LEN 4 1676 1677 /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2 msgrequest */ 1678 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_LEN 20 1679 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1680 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1681 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1682 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1683 /* Time adjustment in seconds */ 1684 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_OFST 8 1685 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_LEN 4 1686 /* Time adjustment major value */ 1687 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_OFST 8 1688 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_LEN 4 1689 /* Time adjustment in nanoseconds */ 1690 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_OFST 12 1691 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_LEN 4 1692 /* Time adjustment minor value */ 1693 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_OFST 12 1694 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_LEN 4 1695 /* Upper 32bits of major time offset adjustment */ 1696 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_OFST 16 1697 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_LEN 4 1698 1699 /* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */ 1700 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16 1701 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1702 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1703 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1704 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1705 /* Frequency adjustment 40 bit fixed point ns */ 1706 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8 1707 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8 1708 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8 1709 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12 1710 /* Enum values, see field(s): */ 1711 /* MC_CMD_PTP/MC_CMD_PTP_IN_ADJUST/FREQ */ 1712 1713 /* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */ 1714 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24 1715 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1716 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1717 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1718 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1719 /* Number of VLAN tags, 0 if not VLAN */ 1720 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8 1721 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_LEN 4 1722 /* Set of VLAN tags to filter against */ 1723 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12 1724 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4 1725 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3 1726 1727 /* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */ 1728 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20 1729 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1730 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1731 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1732 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1733 /* 1 to enable UUID filtering, 0 to disable */ 1734 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8 1735 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_LEN 4 1736 /* UUID to filter against */ 1737 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12 1738 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8 1739 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12 1740 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16 1741 1742 /* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */ 1743 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16 1744 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1745 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1746 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1747 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1748 /* 1 to enable Domain filtering, 0 to disable */ 1749 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8 1750 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_LEN 4 1751 /* Domain number to filter against */ 1752 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12 1753 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_LEN 4 1754 1755 /* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */ 1756 #define MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12 1757 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1758 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1759 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1760 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1761 /* Set the clock source. */ 1762 #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8 1763 #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_LEN 4 1764 /* enum: Internal. */ 1765 #define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0 1766 /* enum: External. */ 1767 #define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1 1768 1769 /* MC_CMD_PTP_IN_RST_CLK msgrequest: Reset value of Timer Reg. */ 1770 #define MC_CMD_PTP_IN_RST_CLK_LEN 8 1771 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1772 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1773 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1774 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1775 1776 /* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */ 1777 #define MC_CMD_PTP_IN_PPS_ENABLE_LEN 12 1778 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1779 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1780 /* Enable or disable */ 1781 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4 1782 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_LEN 4 1783 /* enum: Enable */ 1784 #define MC_CMD_PTP_ENABLE_PPS 0x0 1785 /* enum: Disable */ 1786 #define MC_CMD_PTP_DISABLE_PPS 0x1 1787 /* Not used. Events are always sent to function relative queue 0. */ 1788 #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8 1789 #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_LEN 4 1790 1791 /* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */ 1792 #define MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8 1793 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1794 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1795 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1796 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1797 1798 /* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */ 1799 #define MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8 1800 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1801 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1802 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1803 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1804 1805 /* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */ 1806 #define MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8 1807 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1808 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1809 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1810 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1811 1812 /* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */ 1813 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12 1814 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1815 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1816 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1817 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1818 /* Original field containing queue ID. Now extended to include flags. */ 1819 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8 1820 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_LEN 4 1821 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0 1822 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 16 1823 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 31 1824 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 1 1825 1826 /* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */ 1827 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16 1828 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1829 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1830 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1831 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1832 /* Unsubscribe options */ 1833 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8 1834 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_LEN 4 1835 /* enum: Unsubscribe a single queue */ 1836 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0 1837 /* enum: Unsubscribe all queues */ 1838 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1 1839 /* Event queue ID */ 1840 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12 1841 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_LEN 4 1842 1843 /* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */ 1844 #define MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12 1845 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1846 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1847 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1848 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1849 /* 1 to enable PPS test mode, 0 to disable and return result. */ 1850 #define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8 1851 #define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_LEN 4 1852 1853 /* MC_CMD_PTP_IN_SET_SYNC_STATUS msgrequest */ 1854 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_LEN 24 1855 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1856 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1857 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1858 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1859 /* NIC - Host System Clock Synchronization status */ 1860 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_OFST 8 1861 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_LEN 4 1862 /* enum: Host System clock and NIC clock are not in sync */ 1863 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0 1864 /* enum: Host System clock and NIC clock are synchronized */ 1865 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1 1866 /* If synchronized, number of seconds until clocks should be considered to be 1867 * no longer in sync. 1868 */ 1869 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_OFST 12 1870 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_LEN 4 1871 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_OFST 16 1872 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_LEN 4 1873 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 20 1874 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_LEN 4 1875 1876 /* MC_CMD_PTP_OUT msgresponse */ 1877 #define MC_CMD_PTP_OUT_LEN 0 1878 1879 /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */ 1880 #define MC_CMD_PTP_OUT_TRANSMIT_LEN 8 1881 /* Value of seconds timestamp */ 1882 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0 1883 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_LEN 4 1884 /* Timestamp major value */ 1885 #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0 1886 #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_LEN 4 1887 /* Value of nanoseconds timestamp */ 1888 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4 1889 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_LEN 4 1890 /* Timestamp minor value */ 1891 #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4 1892 #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_LEN 4 1893 1894 /* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */ 1895 #define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0 1896 1897 /* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */ 1898 #define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0 1899 1900 /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */ 1901 #define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8 1902 /* Value of seconds timestamp */ 1903 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0 1904 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_LEN 4 1905 /* Timestamp major value */ 1906 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0 1907 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_LEN 4 1908 /* Value of nanoseconds timestamp */ 1909 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4 1910 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_LEN 4 1911 /* Timestamp minor value */ 1912 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4 1913 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_LEN 4 1914 1915 /* MC_CMD_PTP_OUT_READ_NIC_TIME_V2 msgresponse */ 1916 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_LEN 12 1917 /* Value of seconds timestamp */ 1918 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_OFST 0 1919 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_LEN 4 1920 /* Timestamp major value */ 1921 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_OFST 0 1922 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_LEN 4 1923 /* Value of nanoseconds timestamp */ 1924 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_OFST 4 1925 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_LEN 4 1926 /* Timestamp minor value */ 1927 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_OFST 4 1928 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_LEN 4 1929 /* Upper 32bits of major timestamp value */ 1930 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_OFST 8 1931 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_LEN 4 1932 1933 /* MC_CMD_PTP_OUT_STATUS msgresponse */ 1934 #define MC_CMD_PTP_OUT_STATUS_LEN 64 1935 /* Frequency of NIC's hardware clock */ 1936 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0 1937 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_LEN 4 1938 /* Number of packets transmitted and timestamped */ 1939 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4 1940 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_LEN 4 1941 /* Number of packets received and timestamped */ 1942 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8 1943 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_LEN 4 1944 /* Number of packets timestamped by the FPGA */ 1945 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12 1946 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_LEN 4 1947 /* Number of packets filter matched */ 1948 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16 1949 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_LEN 4 1950 /* Number of packets not filter matched */ 1951 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20 1952 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_LEN 4 1953 /* Number of PPS overflows (noise on input?) */ 1954 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24 1955 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_LEN 4 1956 /* Number of PPS bad periods */ 1957 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28 1958 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_LEN 4 1959 /* Minimum period of PPS pulse in nanoseconds */ 1960 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32 1961 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_LEN 4 1962 /* Maximum period of PPS pulse in nanoseconds */ 1963 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36 1964 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_LEN 4 1965 /* Last period of PPS pulse in nanoseconds */ 1966 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40 1967 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_LEN 4 1968 /* Mean period of PPS pulse in nanoseconds */ 1969 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44 1970 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_LEN 4 1971 /* Minimum offset of PPS pulse in nanoseconds (signed) */ 1972 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48 1973 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_LEN 4 1974 /* Maximum offset of PPS pulse in nanoseconds (signed) */ 1975 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52 1976 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_LEN 4 1977 /* Last offset of PPS pulse in nanoseconds (signed) */ 1978 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56 1979 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_LEN 4 1980 /* Mean offset of PPS pulse in nanoseconds (signed) */ 1981 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60 1982 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_LEN 4 1983 1984 /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */ 1985 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20 1986 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240 1987 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num)) 1988 /* A set of host and NIC times */ 1989 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0 1990 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20 1991 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1 1992 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12 1993 /* Host time immediately before NIC's hardware clock read */ 1994 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0 1995 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_LEN 4 1996 /* Value of seconds timestamp */ 1997 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4 1998 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_LEN 4 1999 /* Timestamp major value */ 2000 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4 2001 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_LEN 4 2002 /* Value of nanoseconds timestamp */ 2003 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8 2004 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_LEN 4 2005 /* Timestamp minor value */ 2006 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8 2007 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_LEN 4 2008 /* Host time immediately after NIC's hardware clock read */ 2009 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12 2010 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_LEN 4 2011 /* Number of nanoseconds waited after reading NIC's hardware clock */ 2012 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16 2013 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_LEN 4 2014 2015 /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */ 2016 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8 2017 /* Results of testing */ 2018 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0 2019 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_LEN 4 2020 /* enum: Successful test */ 2021 #define MC_CMD_PTP_MANF_SUCCESS 0x0 2022 /* enum: FPGA load failed */ 2023 #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1 2024 /* enum: FPGA version invalid */ 2025 #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2 2026 /* enum: FPGA registers incorrect */ 2027 #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3 2028 /* enum: Oscillator possibly not working? */ 2029 #define MC_CMD_PTP_MANF_OSCILLATOR 0x4 2030 /* enum: Timestamps not increasing */ 2031 #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5 2032 /* enum: Mismatched packet count */ 2033 #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6 2034 /* enum: Mismatched packet count (Siena filter and FPGA) */ 2035 #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7 2036 /* enum: Not enough packets to perform timestamp check */ 2037 #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8 2038 /* enum: Timestamp trigger GPIO not working */ 2039 #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9 2040 /* enum: Insufficient PPS events to perform checks */ 2041 #define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa 2042 /* enum: PPS time event period not sufficiently close to 1s. */ 2043 #define MC_CMD_PTP_MANF_PPS_PERIOD 0xb 2044 /* enum: PPS time event nS reading not sufficiently close to zero. */ 2045 #define MC_CMD_PTP_MANF_PPS_NS 0xc 2046 /* enum: PTP peripheral registers incorrect */ 2047 #define MC_CMD_PTP_MANF_REGISTERS 0xd 2048 /* enum: Failed to read time from PTP peripheral */ 2049 #define MC_CMD_PTP_MANF_CLOCK_READ 0xe 2050 /* Presence of external oscillator */ 2051 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4 2052 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_LEN 4 2053 2054 /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */ 2055 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12 2056 /* Results of testing */ 2057 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0 2058 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_LEN 4 2059 /* Number of packets received by FPGA */ 2060 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4 2061 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_LEN 4 2062 /* Number of packets received by Siena filters */ 2063 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8 2064 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_LEN 4 2065 2066 /* MC_CMD_PTP_OUT_FPGAREAD msgresponse */ 2067 #define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1 2068 #define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252 2069 #define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num)) 2070 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0 2071 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1 2072 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1 2073 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252 2074 2075 /* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */ 2076 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4 2077 /* Time format required/used by for this NIC. Applies to all PTP MCDI 2078 * operations that pass times between the host and firmware. If this operation 2079 * is not supported (older firmware) a format of seconds and nanoseconds should 2080 * be assumed. Note this enum is deprecated. Do not add to it- use the 2081 * TIME_FORMAT field in MC_CMD_PTP_OUT_GET_ATTRIBUTES instead. 2082 */ 2083 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0 2084 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_LEN 4 2085 /* enum: Times are in seconds and nanoseconds */ 2086 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0 2087 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ 2088 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1 2089 /* enum: Major register has units of seconds, minor 2^-27s per tick */ 2090 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2 2091 2092 /* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */ 2093 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 24 2094 /* Time format required/used by for this NIC. Applies to all PTP MCDI 2095 * operations that pass times between the host and firmware. If this operation 2096 * is not supported (older firmware) a format of seconds and nanoseconds should 2097 * be assumed. 2098 */ 2099 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0 2100 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_LEN 4 2101 /* enum: Times are in seconds and nanoseconds */ 2102 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0 2103 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ 2104 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1 2105 /* enum: Major register has units of seconds, minor 2^-27s per tick */ 2106 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2 2107 /* enum: Major register units are seconds, minor units are quarter nanoseconds 2108 */ 2109 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_QTR_NANOSECONDS 0x3 2110 /* Minimum acceptable value for a corrected synchronization timeset. When 2111 * comparing host and NIC clock times, the MC returns a set of samples that 2112 * contain the host start and end time, the MC time when the host start was 2113 * detected and the time the MC waited between reading the time and detecting 2114 * the host end. The corrected sync window is the difference between the host 2115 * end and start times minus the time that the MC waited for host end. 2116 */ 2117 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4 2118 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_LEN 4 2119 /* Various PTP capabilities */ 2120 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 8 2121 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_LEN 4 2122 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0 2123 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1 2124 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_LBN 1 2125 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_WIDTH 1 2126 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_LBN 2 2127 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_WIDTH 1 2128 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_LBN 3 2129 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_WIDTH 1 2130 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 12 2131 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_LEN 4 2132 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_OFST 16 2133 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_LEN 4 2134 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_OFST 20 2135 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_LEN 4 2136 2137 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */ 2138 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16 2139 /* Uncorrected error on PTP transmit timestamps in NIC clock format */ 2140 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0 2141 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_LEN 4 2142 /* Uncorrected error on PTP receive timestamps in NIC clock format */ 2143 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4 2144 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_LEN 4 2145 /* Uncorrected error on PPS output in NIC clock format */ 2146 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8 2147 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_LEN 4 2148 /* Uncorrected error on PPS input in NIC clock format */ 2149 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12 2150 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_LEN 4 2151 2152 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2 msgresponse */ 2153 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_LEN 24 2154 /* Uncorrected error on PTP transmit timestamps in NIC clock format */ 2155 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0 2156 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_LEN 4 2157 /* Uncorrected error on PTP receive timestamps in NIC clock format */ 2158 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4 2159 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_LEN 4 2160 /* Uncorrected error on PPS output in NIC clock format */ 2161 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_OFST 8 2162 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_LEN 4 2163 /* Uncorrected error on PPS input in NIC clock format */ 2164 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_OFST 12 2165 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_LEN 4 2166 /* Uncorrected error on non-PTP transmit timestamps in NIC clock format */ 2167 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_OFST 16 2168 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_LEN 4 2169 /* Uncorrected error on non-PTP receive timestamps in NIC clock format */ 2170 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_OFST 20 2171 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_LEN 4 2172 2173 /* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */ 2174 #define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4 2175 /* Results of testing */ 2176 #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0 2177 #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_LEN 4 2178 /* Enum values, see field(s): */ 2179 /* MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */ 2180 2181 /* MC_CMD_PTP_OUT_SET_SYNC_STATUS msgresponse */ 2182 #define MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0 2183 2184 2185 /***********************************/ 2186 /* MC_CMD_CSR_READ32 2187 * Read 32bit words from the indirect memory map. 2188 */ 2189 #define MC_CMD_CSR_READ32 0xc 2190 #undef MC_CMD_0xc_PRIVILEGE_CTG 2191 2192 #define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_INSECURE 2193 2194 /* MC_CMD_CSR_READ32_IN msgrequest */ 2195 #define MC_CMD_CSR_READ32_IN_LEN 12 2196 /* Address */ 2197 #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0 2198 #define MC_CMD_CSR_READ32_IN_ADDR_LEN 4 2199 #define MC_CMD_CSR_READ32_IN_STEP_OFST 4 2200 #define MC_CMD_CSR_READ32_IN_STEP_LEN 4 2201 #define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8 2202 #define MC_CMD_CSR_READ32_IN_NUMWORDS_LEN 4 2203 2204 /* MC_CMD_CSR_READ32_OUT msgresponse */ 2205 #define MC_CMD_CSR_READ32_OUT_LENMIN 4 2206 #define MC_CMD_CSR_READ32_OUT_LENMAX 252 2207 #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num)) 2208 /* The last dword is the status, not a value read */ 2209 #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0 2210 #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4 2211 #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1 2212 #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63 2213 2214 2215 /***********************************/ 2216 /* MC_CMD_CSR_WRITE32 2217 * Write 32bit dwords to the indirect memory map. 2218 */ 2219 #define MC_CMD_CSR_WRITE32 0xd 2220 #undef MC_CMD_0xd_PRIVILEGE_CTG 2221 2222 #define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_INSECURE 2223 2224 /* MC_CMD_CSR_WRITE32_IN msgrequest */ 2225 #define MC_CMD_CSR_WRITE32_IN_LENMIN 12 2226 #define MC_CMD_CSR_WRITE32_IN_LENMAX 252 2227 #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num)) 2228 /* Address */ 2229 #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0 2230 #define MC_CMD_CSR_WRITE32_IN_ADDR_LEN 4 2231 #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4 2232 #define MC_CMD_CSR_WRITE32_IN_STEP_LEN 4 2233 #define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8 2234 #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4 2235 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1 2236 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61 2237 2238 /* MC_CMD_CSR_WRITE32_OUT msgresponse */ 2239 #define MC_CMD_CSR_WRITE32_OUT_LEN 4 2240 #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0 2241 #define MC_CMD_CSR_WRITE32_OUT_STATUS_LEN 4 2242 2243 2244 /***********************************/ 2245 /* MC_CMD_HP 2246 * These commands are used for HP related features. They are grouped under one 2247 * MCDI command to avoid creating too many MCDI commands. 2248 */ 2249 #define MC_CMD_HP 0x54 2250 #undef MC_CMD_0x54_PRIVILEGE_CTG 2251 2252 #define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 2253 2254 /* MC_CMD_HP_IN msgrequest */ 2255 #define MC_CMD_HP_IN_LEN 16 2256 /* HP OCSD sub-command. When address is not NULL, request activation of OCSD at 2257 * the specified address with the specified interval.When address is NULL, 2258 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current 2259 * state / 2: (debug) Show temperature reported by one of the supported 2260 * sensors. 2261 */ 2262 #define MC_CMD_HP_IN_SUBCMD_OFST 0 2263 #define MC_CMD_HP_IN_SUBCMD_LEN 4 2264 /* enum: OCSD (Option Card Sensor Data) sub-command. */ 2265 #define MC_CMD_HP_IN_OCSD_SUBCMD 0x0 2266 /* enum: Last known valid HP sub-command. */ 2267 #define MC_CMD_HP_IN_LAST_SUBCMD 0x0 2268 /* The address to the array of sensor fields. (Or NULL to use a sub-command.) 2269 */ 2270 #define MC_CMD_HP_IN_OCSD_ADDR_OFST 4 2271 #define MC_CMD_HP_IN_OCSD_ADDR_LEN 8 2272 #define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4 2273 #define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8 2274 /* The requested update interval, in seconds. (Or the sub-command if ADDR is 2275 * NULL.) 2276 */ 2277 #define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12 2278 #define MC_CMD_HP_IN_OCSD_INTERVAL_LEN 4 2279 2280 /* MC_CMD_HP_OUT msgresponse */ 2281 #define MC_CMD_HP_OUT_LEN 4 2282 #define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0 2283 #define MC_CMD_HP_OUT_OCSD_STATUS_LEN 4 2284 /* enum: OCSD stopped for this card. */ 2285 #define MC_CMD_HP_OUT_OCSD_STOPPED 0x1 2286 /* enum: OCSD was successfully started with the address provided. */ 2287 #define MC_CMD_HP_OUT_OCSD_STARTED 0x2 2288 /* enum: OCSD was already started for this card. */ 2289 #define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3 2290 2291 2292 /***********************************/ 2293 /* MC_CMD_STACKINFO 2294 * Get stack information. 2295 */ 2296 #define MC_CMD_STACKINFO 0xf 2297 #undef MC_CMD_0xf_PRIVILEGE_CTG 2298 2299 #define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN 2300 2301 /* MC_CMD_STACKINFO_IN msgrequest */ 2302 #define MC_CMD_STACKINFO_IN_LEN 0 2303 2304 /* MC_CMD_STACKINFO_OUT msgresponse */ 2305 #define MC_CMD_STACKINFO_OUT_LENMIN 12 2306 #define MC_CMD_STACKINFO_OUT_LENMAX 252 2307 #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num)) 2308 /* (thread ptr, stack size, free space) for each thread in system */ 2309 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0 2310 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12 2311 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1 2312 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21 2313 2314 2315 /***********************************/ 2316 /* MC_CMD_MDIO_READ 2317 * MDIO register read. 2318 */ 2319 #define MC_CMD_MDIO_READ 0x10 2320 #undef MC_CMD_0x10_PRIVILEGE_CTG 2321 2322 #define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2323 2324 /* MC_CMD_MDIO_READ_IN msgrequest */ 2325 #define MC_CMD_MDIO_READ_IN_LEN 16 2326 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for 2327 * external devices. 2328 */ 2329 #define MC_CMD_MDIO_READ_IN_BUS_OFST 0 2330 #define MC_CMD_MDIO_READ_IN_BUS_LEN 4 2331 /* enum: Internal. */ 2332 #define MC_CMD_MDIO_BUS_INTERNAL 0x0 2333 /* enum: External. */ 2334 #define MC_CMD_MDIO_BUS_EXTERNAL 0x1 2335 /* Port address */ 2336 #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4 2337 #define MC_CMD_MDIO_READ_IN_PRTAD_LEN 4 2338 /* Device Address or clause 22. */ 2339 #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8 2340 #define MC_CMD_MDIO_READ_IN_DEVAD_LEN 4 2341 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 2342 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 2343 */ 2344 #define MC_CMD_MDIO_CLAUSE22 0x20 2345 /* Address */ 2346 #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12 2347 #define MC_CMD_MDIO_READ_IN_ADDR_LEN 4 2348 2349 /* MC_CMD_MDIO_READ_OUT msgresponse */ 2350 #define MC_CMD_MDIO_READ_OUT_LEN 8 2351 /* Value */ 2352 #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0 2353 #define MC_CMD_MDIO_READ_OUT_VALUE_LEN 4 2354 /* Status the MDIO commands return the raw status bits from the MDIO block. A 2355 * "good" transaction should have the DONE bit set and all other bits clear. 2356 */ 2357 #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4 2358 #define MC_CMD_MDIO_READ_OUT_STATUS_LEN 4 2359 /* enum: Good. */ 2360 #define MC_CMD_MDIO_STATUS_GOOD 0x8 2361 2362 2363 /***********************************/ 2364 /* MC_CMD_MDIO_WRITE 2365 * MDIO register write. 2366 */ 2367 #define MC_CMD_MDIO_WRITE 0x11 2368 #undef MC_CMD_0x11_PRIVILEGE_CTG 2369 2370 #define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN 2371 2372 /* MC_CMD_MDIO_WRITE_IN msgrequest */ 2373 #define MC_CMD_MDIO_WRITE_IN_LEN 20 2374 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for 2375 * external devices. 2376 */ 2377 #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0 2378 #define MC_CMD_MDIO_WRITE_IN_BUS_LEN 4 2379 /* enum: Internal. */ 2380 /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */ 2381 /* enum: External. */ 2382 /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */ 2383 /* Port address */ 2384 #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4 2385 #define MC_CMD_MDIO_WRITE_IN_PRTAD_LEN 4 2386 /* Device Address or clause 22. */ 2387 #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8 2388 #define MC_CMD_MDIO_WRITE_IN_DEVAD_LEN 4 2389 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 2390 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 2391 */ 2392 /* MC_CMD_MDIO_CLAUSE22 0x20 */ 2393 /* Address */ 2394 #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12 2395 #define MC_CMD_MDIO_WRITE_IN_ADDR_LEN 4 2396 /* Value */ 2397 #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16 2398 #define MC_CMD_MDIO_WRITE_IN_VALUE_LEN 4 2399 2400 /* MC_CMD_MDIO_WRITE_OUT msgresponse */ 2401 #define MC_CMD_MDIO_WRITE_OUT_LEN 4 2402 /* Status; the MDIO commands return the raw status bits from the MDIO block. A 2403 * "good" transaction should have the DONE bit set and all other bits clear. 2404 */ 2405 #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0 2406 #define MC_CMD_MDIO_WRITE_OUT_STATUS_LEN 4 2407 /* enum: Good. */ 2408 /* MC_CMD_MDIO_STATUS_GOOD 0x8 */ 2409 2410 2411 /***********************************/ 2412 /* MC_CMD_DBI_WRITE 2413 * Write DBI register(s). 2414 */ 2415 #define MC_CMD_DBI_WRITE 0x12 2416 #undef MC_CMD_0x12_PRIVILEGE_CTG 2417 2418 #define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_INSECURE 2419 2420 /* MC_CMD_DBI_WRITE_IN msgrequest */ 2421 #define MC_CMD_DBI_WRITE_IN_LENMIN 12 2422 #define MC_CMD_DBI_WRITE_IN_LENMAX 252 2423 #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num)) 2424 /* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset 2425 * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF. 2426 */ 2427 #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0 2428 #define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12 2429 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1 2430 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21 2431 2432 /* MC_CMD_DBI_WRITE_OUT msgresponse */ 2433 #define MC_CMD_DBI_WRITE_OUT_LEN 0 2434 2435 /* MC_CMD_DBIWROP_TYPEDEF structuredef */ 2436 #define MC_CMD_DBIWROP_TYPEDEF_LEN 12 2437 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0 2438 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LEN 4 2439 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0 2440 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32 2441 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4 2442 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LEN 4 2443 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16 2444 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16 2445 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15 2446 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1 2447 #define MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14 2448 #define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1 2449 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32 2450 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32 2451 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8 2452 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LEN 4 2453 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64 2454 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32 2455 2456 2457 /***********************************/ 2458 /* MC_CMD_PORT_READ32 2459 * Read a 32-bit register from the indirect port register map. The port to 2460 * access is implied by the Shared memory channel used. 2461 */ 2462 #define MC_CMD_PORT_READ32 0x14 2463 2464 /* MC_CMD_PORT_READ32_IN msgrequest */ 2465 #define MC_CMD_PORT_READ32_IN_LEN 4 2466 /* Address */ 2467 #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0 2468 #define MC_CMD_PORT_READ32_IN_ADDR_LEN 4 2469 2470 /* MC_CMD_PORT_READ32_OUT msgresponse */ 2471 #define MC_CMD_PORT_READ32_OUT_LEN 8 2472 /* Value */ 2473 #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0 2474 #define MC_CMD_PORT_READ32_OUT_VALUE_LEN 4 2475 /* Status */ 2476 #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4 2477 #define MC_CMD_PORT_READ32_OUT_STATUS_LEN 4 2478 2479 2480 /***********************************/ 2481 /* MC_CMD_PORT_WRITE32 2482 * Write a 32-bit register to the indirect port register map. The port to 2483 * access is implied by the Shared memory channel used. 2484 */ 2485 #define MC_CMD_PORT_WRITE32 0x15 2486 2487 /* MC_CMD_PORT_WRITE32_IN msgrequest */ 2488 #define MC_CMD_PORT_WRITE32_IN_LEN 8 2489 /* Address */ 2490 #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0 2491 #define MC_CMD_PORT_WRITE32_IN_ADDR_LEN 4 2492 /* Value */ 2493 #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4 2494 #define MC_CMD_PORT_WRITE32_IN_VALUE_LEN 4 2495 2496 /* MC_CMD_PORT_WRITE32_OUT msgresponse */ 2497 #define MC_CMD_PORT_WRITE32_OUT_LEN 4 2498 /* Status */ 2499 #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0 2500 #define MC_CMD_PORT_WRITE32_OUT_STATUS_LEN 4 2501 2502 2503 /***********************************/ 2504 /* MC_CMD_PORT_READ128 2505 * Read a 128-bit register from the indirect port register map. The port to 2506 * access is implied by the Shared memory channel used. 2507 */ 2508 #define MC_CMD_PORT_READ128 0x16 2509 2510 /* MC_CMD_PORT_READ128_IN msgrequest */ 2511 #define MC_CMD_PORT_READ128_IN_LEN 4 2512 /* Address */ 2513 #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0 2514 #define MC_CMD_PORT_READ128_IN_ADDR_LEN 4 2515 2516 /* MC_CMD_PORT_READ128_OUT msgresponse */ 2517 #define MC_CMD_PORT_READ128_OUT_LEN 20 2518 /* Value */ 2519 #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0 2520 #define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16 2521 /* Status */ 2522 #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16 2523 #define MC_CMD_PORT_READ128_OUT_STATUS_LEN 4 2524 2525 2526 /***********************************/ 2527 /* MC_CMD_PORT_WRITE128 2528 * Write a 128-bit register to the indirect port register map. The port to 2529 * access is implied by the Shared memory channel used. 2530 */ 2531 #define MC_CMD_PORT_WRITE128 0x17 2532 2533 /* MC_CMD_PORT_WRITE128_IN msgrequest */ 2534 #define MC_CMD_PORT_WRITE128_IN_LEN 20 2535 /* Address */ 2536 #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0 2537 #define MC_CMD_PORT_WRITE128_IN_ADDR_LEN 4 2538 /* Value */ 2539 #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4 2540 #define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16 2541 2542 /* MC_CMD_PORT_WRITE128_OUT msgresponse */ 2543 #define MC_CMD_PORT_WRITE128_OUT_LEN 4 2544 /* Status */ 2545 #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0 2546 #define MC_CMD_PORT_WRITE128_OUT_STATUS_LEN 4 2547 2548 /* MC_CMD_CAPABILITIES structuredef */ 2549 #define MC_CMD_CAPABILITIES_LEN 4 2550 /* Small buf table. */ 2551 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0 2552 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1 2553 /* Turbo mode (for Maranello). */ 2554 #define MC_CMD_CAPABILITIES_TURBO_LBN 1 2555 #define MC_CMD_CAPABILITIES_TURBO_WIDTH 1 2556 /* Turbo mode active (for Maranello). */ 2557 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2 2558 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1 2559 /* PTP offload. */ 2560 #define MC_CMD_CAPABILITIES_PTP_LBN 3 2561 #define MC_CMD_CAPABILITIES_PTP_WIDTH 1 2562 /* AOE mode. */ 2563 #define MC_CMD_CAPABILITIES_AOE_LBN 4 2564 #define MC_CMD_CAPABILITIES_AOE_WIDTH 1 2565 /* AOE mode active. */ 2566 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5 2567 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1 2568 /* AOE mode active. */ 2569 #define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6 2570 #define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1 2571 #define MC_CMD_CAPABILITIES_RESERVED_LBN 7 2572 #define MC_CMD_CAPABILITIES_RESERVED_WIDTH 25 2573 2574 2575 /***********************************/ 2576 /* MC_CMD_GET_BOARD_CFG 2577 * Returns the MC firmware configuration structure. 2578 */ 2579 #define MC_CMD_GET_BOARD_CFG 0x18 2580 #undef MC_CMD_0x18_PRIVILEGE_CTG 2581 2582 #define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2583 2584 /* MC_CMD_GET_BOARD_CFG_IN msgrequest */ 2585 #define MC_CMD_GET_BOARD_CFG_IN_LEN 0 2586 2587 /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */ 2588 #define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96 2589 #define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136 2590 #define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num)) 2591 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0 2592 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_LEN 4 2593 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4 2594 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32 2595 /* Capabilities for Siena Port0 (see struct MC_CMD_CAPABILITIES). Unused on 2596 * EF10 and later (use MC_CMD_GET_CAPABILITIES). 2597 */ 2598 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36 2599 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_LEN 4 2600 /* Capabilities for Siena Port1 (see struct MC_CMD_CAPABILITIES). Unused on 2601 * EF10 and later (use MC_CMD_GET_CAPABILITIES). 2602 */ 2603 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40 2604 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_LEN 4 2605 /* Base MAC address for Siena Port0. Unused on EF10 and later (use 2606 * MC_CMD_GET_MAC_ADDRESSES). 2607 */ 2608 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44 2609 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6 2610 /* Base MAC address for Siena Port1. Unused on EF10 and later (use 2611 * MC_CMD_GET_MAC_ADDRESSES). 2612 */ 2613 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50 2614 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6 2615 /* Size of MAC address pool for Siena Port0. Unused on EF10 and later (use 2616 * MC_CMD_GET_MAC_ADDRESSES). 2617 */ 2618 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56 2619 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_LEN 4 2620 /* Size of MAC address pool for Siena Port1. Unused on EF10 and later (use 2621 * MC_CMD_GET_MAC_ADDRESSES). 2622 */ 2623 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60 2624 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_LEN 4 2625 /* Increment between addresses in MAC address pool for Siena Port0. Unused on 2626 * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES). 2627 */ 2628 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64 2629 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_LEN 4 2630 /* Increment between addresses in MAC address pool for Siena Port1. Unused on 2631 * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES). 2632 */ 2633 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68 2634 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_LEN 4 2635 /* Siena only. This field contains a 16-bit value for each of the types of 2636 * NVRAM area. The values are defined in the firmware/mc/platform/.c file for a 2637 * specific board type, but otherwise have no meaning to the MC; they are used 2638 * by the driver to manage selection of appropriate firmware updates. Unused on 2639 * EF10 and later (use MC_CMD_NVRAM_METADATA). 2640 */ 2641 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72 2642 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2 2643 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12 2644 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32 2645 2646 2647 /***********************************/ 2648 /* MC_CMD_DBI_READX 2649 * Read DBI register(s) -- extended functionality 2650 */ 2651 #define MC_CMD_DBI_READX 0x19 2652 #undef MC_CMD_0x19_PRIVILEGE_CTG 2653 2654 #define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_INSECURE 2655 2656 /* MC_CMD_DBI_READX_IN msgrequest */ 2657 #define MC_CMD_DBI_READX_IN_LENMIN 8 2658 #define MC_CMD_DBI_READX_IN_LENMAX 248 2659 #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num)) 2660 /* Each Read op consists of an address (offset 0), VF/CS2) */ 2661 #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0 2662 #define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8 2663 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0 2664 #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4 2665 #define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1 2666 #define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31 2667 2668 /* MC_CMD_DBI_READX_OUT msgresponse */ 2669 #define MC_CMD_DBI_READX_OUT_LENMIN 4 2670 #define MC_CMD_DBI_READX_OUT_LENMAX 252 2671 #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num)) 2672 /* Value */ 2673 #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0 2674 #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4 2675 #define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1 2676 #define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63 2677 2678 /* MC_CMD_DBIRDOP_TYPEDEF structuredef */ 2679 #define MC_CMD_DBIRDOP_TYPEDEF_LEN 8 2680 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0 2681 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LEN 4 2682 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0 2683 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32 2684 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4 2685 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LEN 4 2686 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16 2687 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16 2688 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15 2689 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1 2690 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14 2691 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1 2692 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32 2693 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32 2694 2695 2696 /***********************************/ 2697 /* MC_CMD_SET_RAND_SEED 2698 * Set the 16byte seed for the MC pseudo-random generator. 2699 */ 2700 #define MC_CMD_SET_RAND_SEED 0x1a 2701 #undef MC_CMD_0x1a_PRIVILEGE_CTG 2702 2703 #define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_INSECURE 2704 2705 /* MC_CMD_SET_RAND_SEED_IN msgrequest */ 2706 #define MC_CMD_SET_RAND_SEED_IN_LEN 16 2707 /* Seed value. */ 2708 #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0 2709 #define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16 2710 2711 /* MC_CMD_SET_RAND_SEED_OUT msgresponse */ 2712 #define MC_CMD_SET_RAND_SEED_OUT_LEN 0 2713 2714 2715 /***********************************/ 2716 /* MC_CMD_LTSSM_HIST 2717 * Retrieve the history of the LTSSM, if the build supports it. 2718 */ 2719 #define MC_CMD_LTSSM_HIST 0x1b 2720 2721 /* MC_CMD_LTSSM_HIST_IN msgrequest */ 2722 #define MC_CMD_LTSSM_HIST_IN_LEN 0 2723 2724 /* MC_CMD_LTSSM_HIST_OUT msgresponse */ 2725 #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0 2726 #define MC_CMD_LTSSM_HIST_OUT_LENMAX 252 2727 #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num)) 2728 /* variable number of LTSSM values, as bytes. The history is read-to-clear. */ 2729 #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0 2730 #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4 2731 #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0 2732 #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63 2733 2734 2735 /***********************************/ 2736 /* MC_CMD_DRV_ATTACH 2737 * Inform MCPU that this port is managed on the host (i.e. driver active). For 2738 * Huntington, also request the preferred datapath firmware to use if possible 2739 * (it may not be possible for this request to be fulfilled; the driver must 2740 * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which 2741 * features are actually available). The FIRMWARE_ID field is ignored by older 2742 * platforms. 2743 */ 2744 #define MC_CMD_DRV_ATTACH 0x1c 2745 #undef MC_CMD_0x1c_PRIVILEGE_CTG 2746 2747 #define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2748 2749 /* MC_CMD_DRV_ATTACH_IN msgrequest */ 2750 #define MC_CMD_DRV_ATTACH_IN_LEN 12 2751 /* new state to set if UPDATE=1 */ 2752 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0 2753 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_LEN 4 2754 #define MC_CMD_DRV_ATTACH_LBN 0 2755 #define MC_CMD_DRV_ATTACH_WIDTH 1 2756 #define MC_CMD_DRV_ATTACH_IN_ATTACH_LBN 0 2757 #define MC_CMD_DRV_ATTACH_IN_ATTACH_WIDTH 1 2758 #define MC_CMD_DRV_PREBOOT_LBN 1 2759 #define MC_CMD_DRV_PREBOOT_WIDTH 1 2760 #define MC_CMD_DRV_ATTACH_IN_PREBOOT_LBN 1 2761 #define MC_CMD_DRV_ATTACH_IN_PREBOOT_WIDTH 1 2762 #define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_LBN 2 2763 #define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_WIDTH 1 2764 #define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_LBN 3 2765 #define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_WIDTH 1 2766 /* 1 to set new state, or 0 to just report the existing state */ 2767 #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4 2768 #define MC_CMD_DRV_ATTACH_IN_UPDATE_LEN 4 2769 /* preferred datapath firmware (for Huntington; ignored for Siena) */ 2770 #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8 2771 #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_LEN 4 2772 /* enum: Prefer to use full featured firmware */ 2773 #define MC_CMD_FW_FULL_FEATURED 0x0 2774 /* enum: Prefer to use firmware with fewer features but lower latency */ 2775 #define MC_CMD_FW_LOW_LATENCY 0x1 2776 /* enum: Prefer to use firmware for SolarCapture packed stream mode */ 2777 #define MC_CMD_FW_PACKED_STREAM 0x2 2778 /* enum: Prefer to use firmware with fewer features and simpler TX event 2779 * batching but higher TX packet rate 2780 */ 2781 #define MC_CMD_FW_HIGH_TX_RATE 0x3 2782 /* enum: Reserved value */ 2783 #define MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4 2784 /* enum: Prefer to use firmware with additional "rules engine" filtering 2785 * support 2786 */ 2787 #define MC_CMD_FW_RULES_ENGINE 0x5 2788 /* enum: Prefer to use firmware with additional DPDK support */ 2789 #define MC_CMD_FW_DPDK 0x6 2790 /* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and 2791 * bug69716) 2792 */ 2793 #define MC_CMD_FW_L3XUDP 0x7 2794 /* enum: Requests that the MC keep whatever datapath firmware is currently 2795 * running. It's used for test purposes, where we want to be able to shmboot 2796 * special test firmware variants. This option is only recognised in eftest 2797 * (i.e. non-production) builds. 2798 */ 2799 #define MC_CMD_FW_KEEP_CURRENT_EFTEST_ONLY 0xfffffffe 2800 /* enum: Only this option is allowed for non-admin functions */ 2801 #define MC_CMD_FW_DONT_CARE 0xffffffff 2802 2803 /* MC_CMD_DRV_ATTACH_OUT msgresponse */ 2804 #define MC_CMD_DRV_ATTACH_OUT_LEN 4 2805 /* previous or existing state, see the bitmask at NEW_STATE */ 2806 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0 2807 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_LEN 4 2808 2809 /* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */ 2810 #define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8 2811 /* previous or existing state, see the bitmask at NEW_STATE */ 2812 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0 2813 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_LEN 4 2814 /* Flags associated with this function */ 2815 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4 2816 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_LEN 4 2817 /* enum: Labels the lowest-numbered function visible to the OS */ 2818 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0 2819 /* enum: The function can control the link state of the physical port it is 2820 * bound to. 2821 */ 2822 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1 2823 /* enum: The function can perform privileged operations */ 2824 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2 2825 /* enum: The function does not have an active port associated with it. The port 2826 * refers to the Sorrento external FPGA port. 2827 */ 2828 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3 2829 /* enum: If set, indicates that VI spreading is currently enabled. Will always 2830 * indicate the current state, regardless of the value in the WANT_VI_SPREADING 2831 * input. 2832 */ 2833 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_VI_SPREADING_ENABLED 0x4 2834 2835 2836 /***********************************/ 2837 /* MC_CMD_SHMUART 2838 * Route UART output to circular buffer in shared memory instead. 2839 */ 2840 #define MC_CMD_SHMUART 0x1f 2841 2842 /* MC_CMD_SHMUART_IN msgrequest */ 2843 #define MC_CMD_SHMUART_IN_LEN 4 2844 /* ??? */ 2845 #define MC_CMD_SHMUART_IN_FLAG_OFST 0 2846 #define MC_CMD_SHMUART_IN_FLAG_LEN 4 2847 2848 /* MC_CMD_SHMUART_OUT msgresponse */ 2849 #define MC_CMD_SHMUART_OUT_LEN 0 2850 2851 2852 /***********************************/ 2853 /* MC_CMD_PORT_RESET 2854 * Generic per-port reset. There is no equivalent for per-board reset. Locks 2855 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated - 2856 * use MC_CMD_ENTITY_RESET instead. 2857 */ 2858 #define MC_CMD_PORT_RESET 0x20 2859 #undef MC_CMD_0x20_PRIVILEGE_CTG 2860 2861 #define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2862 2863 /* MC_CMD_PORT_RESET_IN msgrequest */ 2864 #define MC_CMD_PORT_RESET_IN_LEN 0 2865 2866 /* MC_CMD_PORT_RESET_OUT msgresponse */ 2867 #define MC_CMD_PORT_RESET_OUT_LEN 0 2868 2869 2870 /***********************************/ 2871 /* MC_CMD_ENTITY_RESET 2872 * Generic per-resource reset. There is no equivalent for per-board reset. 2873 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an 2874 * extended version of the deprecated MC_CMD_PORT_RESET with added fields. 2875 */ 2876 #define MC_CMD_ENTITY_RESET 0x20 2877 /* MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */ 2878 2879 /* MC_CMD_ENTITY_RESET_IN msgrequest */ 2880 #define MC_CMD_ENTITY_RESET_IN_LEN 4 2881 /* Optional flags field. Omitting this will perform a "legacy" reset action 2882 * (TBD). 2883 */ 2884 #define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0 2885 #define MC_CMD_ENTITY_RESET_IN_FLAG_LEN 4 2886 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0 2887 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1 2888 2889 /* MC_CMD_ENTITY_RESET_OUT msgresponse */ 2890 #define MC_CMD_ENTITY_RESET_OUT_LEN 0 2891 2892 2893 /***********************************/ 2894 /* MC_CMD_PCIE_CREDITS 2895 * Read instantaneous and minimum flow control thresholds. 2896 */ 2897 #define MC_CMD_PCIE_CREDITS 0x21 2898 2899 /* MC_CMD_PCIE_CREDITS_IN msgrequest */ 2900 #define MC_CMD_PCIE_CREDITS_IN_LEN 8 2901 /* poll period. 0 is disabled */ 2902 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0 2903 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_LEN 4 2904 /* wipe statistics */ 2905 #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4 2906 #define MC_CMD_PCIE_CREDITS_IN_WIPE_LEN 4 2907 2908 /* MC_CMD_PCIE_CREDITS_OUT msgresponse */ 2909 #define MC_CMD_PCIE_CREDITS_OUT_LEN 16 2910 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0 2911 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2 2912 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2 2913 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2 2914 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4 2915 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2 2916 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6 2917 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2 2918 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8 2919 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2 2920 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10 2921 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2 2922 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12 2923 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2 2924 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14 2925 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2 2926 2927 2928 /***********************************/ 2929 /* MC_CMD_RXD_MONITOR 2930 * Get histogram of RX queue fill level. 2931 */ 2932 #define MC_CMD_RXD_MONITOR 0x22 2933 2934 /* MC_CMD_RXD_MONITOR_IN msgrequest */ 2935 #define MC_CMD_RXD_MONITOR_IN_LEN 12 2936 #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0 2937 #define MC_CMD_RXD_MONITOR_IN_QID_LEN 4 2938 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4 2939 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_LEN 4 2940 #define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8 2941 #define MC_CMD_RXD_MONITOR_IN_WIPE_LEN 4 2942 2943 /* MC_CMD_RXD_MONITOR_OUT msgresponse */ 2944 #define MC_CMD_RXD_MONITOR_OUT_LEN 80 2945 #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0 2946 #define MC_CMD_RXD_MONITOR_OUT_QID_LEN 4 2947 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4 2948 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_LEN 4 2949 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8 2950 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_LEN 4 2951 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12 2952 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_LEN 4 2953 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16 2954 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_LEN 4 2955 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20 2956 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_LEN 4 2957 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24 2958 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_LEN 4 2959 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28 2960 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_LEN 4 2961 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32 2962 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_LEN 4 2963 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36 2964 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_LEN 4 2965 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40 2966 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_LEN 4 2967 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44 2968 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_LEN 4 2969 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48 2970 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_LEN 4 2971 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52 2972 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_LEN 4 2973 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56 2974 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_LEN 4 2975 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60 2976 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_LEN 4 2977 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64 2978 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_LEN 4 2979 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68 2980 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_LEN 4 2981 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72 2982 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_LEN 4 2983 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76 2984 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_LEN 4 2985 2986 2987 /***********************************/ 2988 /* MC_CMD_PUTS 2989 * Copy the given ASCII string out onto UART and/or out of the network port. 2990 */ 2991 #define MC_CMD_PUTS 0x23 2992 #undef MC_CMD_0x23_PRIVILEGE_CTG 2993 2994 #define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_INSECURE 2995 2996 /* MC_CMD_PUTS_IN msgrequest */ 2997 #define MC_CMD_PUTS_IN_LENMIN 13 2998 #define MC_CMD_PUTS_IN_LENMAX 252 2999 #define MC_CMD_PUTS_IN_LEN(num) (12+1*(num)) 3000 #define MC_CMD_PUTS_IN_DEST_OFST 0 3001 #define MC_CMD_PUTS_IN_DEST_LEN 4 3002 #define MC_CMD_PUTS_IN_UART_LBN 0 3003 #define MC_CMD_PUTS_IN_UART_WIDTH 1 3004 #define MC_CMD_PUTS_IN_PORT_LBN 1 3005 #define MC_CMD_PUTS_IN_PORT_WIDTH 1 3006 #define MC_CMD_PUTS_IN_DHOST_OFST 4 3007 #define MC_CMD_PUTS_IN_DHOST_LEN 6 3008 #define MC_CMD_PUTS_IN_STRING_OFST 12 3009 #define MC_CMD_PUTS_IN_STRING_LEN 1 3010 #define MC_CMD_PUTS_IN_STRING_MINNUM 1 3011 #define MC_CMD_PUTS_IN_STRING_MAXNUM 240 3012 3013 /* MC_CMD_PUTS_OUT msgresponse */ 3014 #define MC_CMD_PUTS_OUT_LEN 0 3015 3016 3017 /***********************************/ 3018 /* MC_CMD_GET_PHY_CFG 3019 * Report PHY configuration. This guarantees to succeed even if the PHY is in a 3020 * 'zombie' state. Locks required: None 3021 */ 3022 #define MC_CMD_GET_PHY_CFG 0x24 3023 #undef MC_CMD_0x24_PRIVILEGE_CTG 3024 3025 #define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL 3026 3027 /* MC_CMD_GET_PHY_CFG_IN msgrequest */ 3028 #define MC_CMD_GET_PHY_CFG_IN_LEN 0 3029 3030 /* MC_CMD_GET_PHY_CFG_OUT msgresponse */ 3031 #define MC_CMD_GET_PHY_CFG_OUT_LEN 72 3032 /* flags */ 3033 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0 3034 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_LEN 4 3035 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0 3036 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1 3037 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1 3038 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1 3039 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2 3040 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1 3041 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3 3042 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1 3043 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4 3044 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1 3045 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5 3046 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1 3047 #define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6 3048 #define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1 3049 /* ?? */ 3050 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4 3051 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_LEN 4 3052 /* Bitmask of supported capabilities */ 3053 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8 3054 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_LEN 4 3055 #define MC_CMD_PHY_CAP_10HDX_LBN 1 3056 #define MC_CMD_PHY_CAP_10HDX_WIDTH 1 3057 #define MC_CMD_PHY_CAP_10FDX_LBN 2 3058 #define MC_CMD_PHY_CAP_10FDX_WIDTH 1 3059 #define MC_CMD_PHY_CAP_100HDX_LBN 3 3060 #define MC_CMD_PHY_CAP_100HDX_WIDTH 1 3061 #define MC_CMD_PHY_CAP_100FDX_LBN 4 3062 #define MC_CMD_PHY_CAP_100FDX_WIDTH 1 3063 #define MC_CMD_PHY_CAP_1000HDX_LBN 5 3064 #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1 3065 #define MC_CMD_PHY_CAP_1000FDX_LBN 6 3066 #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1 3067 #define MC_CMD_PHY_CAP_10000FDX_LBN 7 3068 #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1 3069 #define MC_CMD_PHY_CAP_PAUSE_LBN 8 3070 #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1 3071 #define MC_CMD_PHY_CAP_ASYM_LBN 9 3072 #define MC_CMD_PHY_CAP_ASYM_WIDTH 1 3073 #define MC_CMD_PHY_CAP_AN_LBN 10 3074 #define MC_CMD_PHY_CAP_AN_WIDTH 1 3075 #define MC_CMD_PHY_CAP_40000FDX_LBN 11 3076 #define MC_CMD_PHY_CAP_40000FDX_WIDTH 1 3077 #define MC_CMD_PHY_CAP_DDM_LBN 12 3078 #define MC_CMD_PHY_CAP_DDM_WIDTH 1 3079 #define MC_CMD_PHY_CAP_100000FDX_LBN 13 3080 #define MC_CMD_PHY_CAP_100000FDX_WIDTH 1 3081 #define MC_CMD_PHY_CAP_25000FDX_LBN 14 3082 #define MC_CMD_PHY_CAP_25000FDX_WIDTH 1 3083 #define MC_CMD_PHY_CAP_50000FDX_LBN 15 3084 #define MC_CMD_PHY_CAP_50000FDX_WIDTH 1 3085 #define MC_CMD_PHY_CAP_BASER_FEC_LBN 16 3086 #define MC_CMD_PHY_CAP_BASER_FEC_WIDTH 1 3087 #define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_LBN 17 3088 #define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_WIDTH 1 3089 #define MC_CMD_PHY_CAP_RS_FEC_LBN 18 3090 #define MC_CMD_PHY_CAP_RS_FEC_WIDTH 1 3091 #define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_LBN 19 3092 #define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_WIDTH 1 3093 #define MC_CMD_PHY_CAP_25G_BASER_FEC_LBN 20 3094 #define MC_CMD_PHY_CAP_25G_BASER_FEC_WIDTH 1 3095 #define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_LBN 21 3096 #define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_WIDTH 1 3097 /* ?? */ 3098 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12 3099 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_LEN 4 3100 /* ?? */ 3101 #define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16 3102 #define MC_CMD_GET_PHY_CFG_OUT_PRT_LEN 4 3103 /* ?? */ 3104 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20 3105 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_LEN 4 3106 /* ?? */ 3107 #define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24 3108 #define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20 3109 /* ?? */ 3110 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44 3111 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_LEN 4 3112 /* enum: Xaui. */ 3113 #define MC_CMD_MEDIA_XAUI 0x1 3114 /* enum: CX4. */ 3115 #define MC_CMD_MEDIA_CX4 0x2 3116 /* enum: KX4. */ 3117 #define MC_CMD_MEDIA_KX4 0x3 3118 /* enum: XFP Far. */ 3119 #define MC_CMD_MEDIA_XFP 0x4 3120 /* enum: SFP+. */ 3121 #define MC_CMD_MEDIA_SFP_PLUS 0x5 3122 /* enum: 10GBaseT. */ 3123 #define MC_CMD_MEDIA_BASE_T 0x6 3124 /* enum: QSFP+. */ 3125 #define MC_CMD_MEDIA_QSFP_PLUS 0x7 3126 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48 3127 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_LEN 4 3128 /* enum: Native clause 22 */ 3129 #define MC_CMD_MMD_CLAUSE22 0x0 3130 #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */ 3131 #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */ 3132 #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */ 3133 #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */ 3134 #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */ 3135 #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */ 3136 #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */ 3137 /* enum: Clause22 proxied over clause45 by PHY. */ 3138 #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d 3139 #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */ 3140 #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */ 3141 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52 3142 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20 3143 3144 3145 /***********************************/ 3146 /* MC_CMD_START_BIST 3147 * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST 3148 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held) 3149 */ 3150 #define MC_CMD_START_BIST 0x25 3151 #undef MC_CMD_0x25_PRIVILEGE_CTG 3152 3153 #define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 3154 3155 /* MC_CMD_START_BIST_IN msgrequest */ 3156 #define MC_CMD_START_BIST_IN_LEN 4 3157 /* Type of test. */ 3158 #define MC_CMD_START_BIST_IN_TYPE_OFST 0 3159 #define MC_CMD_START_BIST_IN_TYPE_LEN 4 3160 /* enum: Run the PHY's short cable BIST. */ 3161 #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1 3162 /* enum: Run the PHY's long cable BIST. */ 3163 #define MC_CMD_PHY_BIST_CABLE_LONG 0x2 3164 /* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */ 3165 #define MC_CMD_BPX_SERDES_BIST 0x3 3166 /* enum: Run the MC loopback tests. */ 3167 #define MC_CMD_MC_LOOPBACK_BIST 0x4 3168 /* enum: Run the PHY's standard BIST. */ 3169 #define MC_CMD_PHY_BIST 0x5 3170 /* enum: Run MC RAM test. */ 3171 #define MC_CMD_MC_MEM_BIST 0x6 3172 /* enum: Run Port RAM test. */ 3173 #define MC_CMD_PORT_MEM_BIST 0x7 3174 /* enum: Run register test. */ 3175 #define MC_CMD_REG_BIST 0x8 3176 3177 /* MC_CMD_START_BIST_OUT msgresponse */ 3178 #define MC_CMD_START_BIST_OUT_LEN 0 3179 3180 3181 /***********************************/ 3182 /* MC_CMD_POLL_BIST 3183 * Poll for BIST completion. Returns a single status code, and optionally some 3184 * PHY specific bist output. The driver should only consume the BIST output 3185 * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't 3186 * successfully parse the BIST output, it should still respect the pass/Fail in 3187 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0, 3188 * EACCES (if PHY_LOCK is not held). 3189 */ 3190 #define MC_CMD_POLL_BIST 0x26 3191 #undef MC_CMD_0x26_PRIVILEGE_CTG 3192 3193 #define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 3194 3195 /* MC_CMD_POLL_BIST_IN msgrequest */ 3196 #define MC_CMD_POLL_BIST_IN_LEN 0 3197 3198 /* MC_CMD_POLL_BIST_OUT msgresponse */ 3199 #define MC_CMD_POLL_BIST_OUT_LEN 8 3200 /* result */ 3201 #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 3202 #define MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 3203 /* enum: Running. */ 3204 #define MC_CMD_POLL_BIST_RUNNING 0x1 3205 /* enum: Passed. */ 3206 #define MC_CMD_POLL_BIST_PASSED 0x2 3207 /* enum: Failed. */ 3208 #define MC_CMD_POLL_BIST_FAILED 0x3 3209 /* enum: Timed-out. */ 3210 #define MC_CMD_POLL_BIST_TIMEOUT 0x4 3211 #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4 3212 #define MC_CMD_POLL_BIST_OUT_PRIVATE_LEN 4 3213 3214 /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */ 3215 #define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36 3216 /* result */ 3217 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 3218 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */ 3219 /* Enum values, see field(s): */ 3220 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 3221 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4 3222 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_LEN 4 3223 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8 3224 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_LEN 4 3225 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12 3226 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_LEN 4 3227 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16 3228 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_LEN 4 3229 /* Status of each channel A */ 3230 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20 3231 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_LEN 4 3232 /* enum: Ok. */ 3233 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1 3234 /* enum: Open. */ 3235 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2 3236 /* enum: Intra-pair short. */ 3237 #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3 3238 /* enum: Inter-pair short. */ 3239 #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4 3240 /* enum: Busy. */ 3241 #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9 3242 /* Status of each channel B */ 3243 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24 3244 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_LEN 4 3245 /* Enum values, see field(s): */ 3246 /* CABLE_STATUS_A */ 3247 /* Status of each channel C */ 3248 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28 3249 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_LEN 4 3250 /* Enum values, see field(s): */ 3251 /* CABLE_STATUS_A */ 3252 /* Status of each channel D */ 3253 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32 3254 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_LEN 4 3255 /* Enum values, see field(s): */ 3256 /* CABLE_STATUS_A */ 3257 3258 /* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */ 3259 #define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8 3260 /* result */ 3261 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 3262 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */ 3263 /* Enum values, see field(s): */ 3264 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 3265 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4 3266 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_LEN 4 3267 /* enum: Complete. */ 3268 #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0 3269 /* enum: Bus switch off I2C write. */ 3270 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1 3271 /* enum: Bus switch off I2C no access IO exp. */ 3272 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2 3273 /* enum: Bus switch off I2C no access module. */ 3274 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3 3275 /* enum: IO exp I2C configure. */ 3276 #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4 3277 /* enum: Bus switch I2C no cross talk. */ 3278 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5 3279 /* enum: Module presence. */ 3280 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6 3281 /* enum: Module ID I2C access. */ 3282 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7 3283 /* enum: Module ID sane value. */ 3284 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8 3285 3286 /* MC_CMD_POLL_BIST_OUT_MEM msgresponse */ 3287 #define MC_CMD_POLL_BIST_OUT_MEM_LEN 36 3288 /* result */ 3289 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 3290 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */ 3291 /* Enum values, see field(s): */ 3292 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 3293 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4 3294 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_LEN 4 3295 /* enum: Test has completed. */ 3296 #define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0 3297 /* enum: RAM test - walk ones. */ 3298 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1 3299 /* enum: RAM test - walk zeros. */ 3300 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2 3301 /* enum: RAM test - walking inversions zeros/ones. */ 3302 #define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3 3303 /* enum: RAM test - walking inversions checkerboard. */ 3304 #define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4 3305 /* enum: Register test - set / clear individual bits. */ 3306 #define MC_CMD_POLL_BIST_MEM_REG 0x5 3307 /* enum: ECC error detected. */ 3308 #define MC_CMD_POLL_BIST_MEM_ECC 0x6 3309 /* Failure address, only valid if result is POLL_BIST_FAILED */ 3310 #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8 3311 #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_LEN 4 3312 /* Bus or address space to which the failure address corresponds */ 3313 #define MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12 3314 #define MC_CMD_POLL_BIST_OUT_MEM_BUS_LEN 4 3315 /* enum: MC MIPS bus. */ 3316 #define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0 3317 /* enum: CSR IREG bus. */ 3318 #define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1 3319 /* enum: RX0 DPCPU bus. */ 3320 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2 3321 /* enum: TX0 DPCPU bus. */ 3322 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3 3323 /* enum: TX1 DPCPU bus. */ 3324 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4 3325 /* enum: RX0 DICPU bus. */ 3326 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5 3327 /* enum: TX DICPU bus. */ 3328 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6 3329 /* enum: RX1 DPCPU bus. */ 3330 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX1 0x7 3331 /* enum: RX1 DICPU bus. */ 3332 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX1 0x8 3333 /* Pattern written to RAM / register */ 3334 #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16 3335 #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_LEN 4 3336 /* Actual value read from RAM / register */ 3337 #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20 3338 #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_LEN 4 3339 /* ECC error mask */ 3340 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24 3341 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_LEN 4 3342 /* ECC parity error mask */ 3343 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28 3344 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_LEN 4 3345 /* ECC fatal error mask */ 3346 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32 3347 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_LEN 4 3348 3349 3350 /***********************************/ 3351 /* MC_CMD_FLUSH_RX_QUEUES 3352 * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ 3353 * flushes should be initiated via this MCDI operation, rather than via 3354 * directly writing FLUSH_CMD. 3355 * 3356 * The flush is completed (either done/fail) asynchronously (after this command 3357 * returns). The driver must still wait for flush done/failure events as usual. 3358 */ 3359 #define MC_CMD_FLUSH_RX_QUEUES 0x27 3360 3361 /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */ 3362 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4 3363 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252 3364 #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num)) 3365 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0 3366 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4 3367 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1 3368 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63 3369 3370 /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */ 3371 #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0 3372 3373 3374 /***********************************/ 3375 /* MC_CMD_GET_LOOPBACK_MODES 3376 * Returns a bitmask of loopback modes available at each speed. 3377 */ 3378 #define MC_CMD_GET_LOOPBACK_MODES 0x28 3379 #undef MC_CMD_0x28_PRIVILEGE_CTG 3380 3381 #define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL 3382 3383 /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */ 3384 #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0 3385 3386 /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */ 3387 #define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40 3388 /* Supported loopbacks. */ 3389 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0 3390 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8 3391 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0 3392 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4 3393 /* enum: None. */ 3394 #define MC_CMD_LOOPBACK_NONE 0x0 3395 /* enum: Data. */ 3396 #define MC_CMD_LOOPBACK_DATA 0x1 3397 /* enum: GMAC. */ 3398 #define MC_CMD_LOOPBACK_GMAC 0x2 3399 /* enum: XGMII. */ 3400 #define MC_CMD_LOOPBACK_XGMII 0x3 3401 /* enum: XGXS. */ 3402 #define MC_CMD_LOOPBACK_XGXS 0x4 3403 /* enum: XAUI. */ 3404 #define MC_CMD_LOOPBACK_XAUI 0x5 3405 /* enum: GMII. */ 3406 #define MC_CMD_LOOPBACK_GMII 0x6 3407 /* enum: SGMII. */ 3408 #define MC_CMD_LOOPBACK_SGMII 0x7 3409 /* enum: XGBR. */ 3410 #define MC_CMD_LOOPBACK_XGBR 0x8 3411 /* enum: XFI. */ 3412 #define MC_CMD_LOOPBACK_XFI 0x9 3413 /* enum: XAUI Far. */ 3414 #define MC_CMD_LOOPBACK_XAUI_FAR 0xa 3415 /* enum: GMII Far. */ 3416 #define MC_CMD_LOOPBACK_GMII_FAR 0xb 3417 /* enum: SGMII Far. */ 3418 #define MC_CMD_LOOPBACK_SGMII_FAR 0xc 3419 /* enum: XFI Far. */ 3420 #define MC_CMD_LOOPBACK_XFI_FAR 0xd 3421 /* enum: GPhy. */ 3422 #define MC_CMD_LOOPBACK_GPHY 0xe 3423 /* enum: PhyXS. */ 3424 #define MC_CMD_LOOPBACK_PHYXS 0xf 3425 /* enum: PCS. */ 3426 #define MC_CMD_LOOPBACK_PCS 0x10 3427 /* enum: PMA-PMD. */ 3428 #define MC_CMD_LOOPBACK_PMAPMD 0x11 3429 /* enum: Cross-Port. */ 3430 #define MC_CMD_LOOPBACK_XPORT 0x12 3431 /* enum: XGMII-Wireside. */ 3432 #define MC_CMD_LOOPBACK_XGMII_WS 0x13 3433 /* enum: XAUI Wireside. */ 3434 #define MC_CMD_LOOPBACK_XAUI_WS 0x14 3435 /* enum: XAUI Wireside Far. */ 3436 #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 3437 /* enum: XAUI Wireside near. */ 3438 #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 3439 /* enum: GMII Wireside. */ 3440 #define MC_CMD_LOOPBACK_GMII_WS 0x17 3441 /* enum: XFI Wireside. */ 3442 #define MC_CMD_LOOPBACK_XFI_WS 0x18 3443 /* enum: XFI Wireside Far. */ 3444 #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 3445 /* enum: PhyXS Wireside. */ 3446 #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a 3447 /* enum: PMA lanes MAC-Serdes. */ 3448 #define MC_CMD_LOOPBACK_PMA_INT 0x1b 3449 /* enum: KR Serdes Parallel (Encoder). */ 3450 #define MC_CMD_LOOPBACK_SD_NEAR 0x1c 3451 /* enum: KR Serdes Serial. */ 3452 #define MC_CMD_LOOPBACK_SD_FAR 0x1d 3453 /* enum: PMA lanes MAC-Serdes Wireside. */ 3454 #define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e 3455 /* enum: KR Serdes Parallel Wireside (Full PCS). */ 3456 #define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f 3457 /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */ 3458 #define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 3459 /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */ 3460 #define MC_CMD_LOOPBACK_SD_FEP_WS 0x21 3461 /* enum: KR Serdes Serial Wireside. */ 3462 #define MC_CMD_LOOPBACK_SD_FES_WS 0x22 3463 /* enum: Near side of AOE Siena side port */ 3464 #define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 3465 /* enum: Medford Wireside datapath loopback */ 3466 #define MC_CMD_LOOPBACK_DATA_WS 0x24 3467 /* enum: Force link up without setting up any physical loopback (snapper use 3468 * only) 3469 */ 3470 #define MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 3471 /* Supported loopbacks. */ 3472 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8 3473 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8 3474 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8 3475 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12 3476 /* Enum values, see field(s): */ 3477 /* 100M */ 3478 /* Supported loopbacks. */ 3479 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16 3480 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8 3481 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16 3482 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20 3483 /* Enum values, see field(s): */ 3484 /* 100M */ 3485 /* Supported loopbacks. */ 3486 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24 3487 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8 3488 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24 3489 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28 3490 /* Enum values, see field(s): */ 3491 /* 100M */ 3492 /* Supported loopbacks. */ 3493 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32 3494 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8 3495 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32 3496 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36 3497 /* Enum values, see field(s): */ 3498 /* 100M */ 3499 3500 /* MC_CMD_GET_LOOPBACK_MODES_OUT_V2 msgresponse: Supported loopback modes for 3501 * newer NICs with 25G/50G/100G support 3502 */ 3503 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN 64 3504 /* Supported loopbacks. */ 3505 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_OFST 0 3506 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LEN 8 3507 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_OFST 0 3508 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_OFST 4 3509 /* enum: None. */ 3510 /* MC_CMD_LOOPBACK_NONE 0x0 */ 3511 /* enum: Data. */ 3512 /* MC_CMD_LOOPBACK_DATA 0x1 */ 3513 /* enum: GMAC. */ 3514 /* MC_CMD_LOOPBACK_GMAC 0x2 */ 3515 /* enum: XGMII. */ 3516 /* MC_CMD_LOOPBACK_XGMII 0x3 */ 3517 /* enum: XGXS. */ 3518 /* MC_CMD_LOOPBACK_XGXS 0x4 */ 3519 /* enum: XAUI. */ 3520 /* MC_CMD_LOOPBACK_XAUI 0x5 */ 3521 /* enum: GMII. */ 3522 /* MC_CMD_LOOPBACK_GMII 0x6 */ 3523 /* enum: SGMII. */ 3524 /* MC_CMD_LOOPBACK_SGMII 0x7 */ 3525 /* enum: XGBR. */ 3526 /* MC_CMD_LOOPBACK_XGBR 0x8 */ 3527 /* enum: XFI. */ 3528 /* MC_CMD_LOOPBACK_XFI 0x9 */ 3529 /* enum: XAUI Far. */ 3530 /* MC_CMD_LOOPBACK_XAUI_FAR 0xa */ 3531 /* enum: GMII Far. */ 3532 /* MC_CMD_LOOPBACK_GMII_FAR 0xb */ 3533 /* enum: SGMII Far. */ 3534 /* MC_CMD_LOOPBACK_SGMII_FAR 0xc */ 3535 /* enum: XFI Far. */ 3536 /* MC_CMD_LOOPBACK_XFI_FAR 0xd */ 3537 /* enum: GPhy. */ 3538 /* MC_CMD_LOOPBACK_GPHY 0xe */ 3539 /* enum: PhyXS. */ 3540 /* MC_CMD_LOOPBACK_PHYXS 0xf */ 3541 /* enum: PCS. */ 3542 /* MC_CMD_LOOPBACK_PCS 0x10 */ 3543 /* enum: PMA-PMD. */ 3544 /* MC_CMD_LOOPBACK_PMAPMD 0x11 */ 3545 /* enum: Cross-Port. */ 3546 /* MC_CMD_LOOPBACK_XPORT 0x12 */ 3547 /* enum: XGMII-Wireside. */ 3548 /* MC_CMD_LOOPBACK_XGMII_WS 0x13 */ 3549 /* enum: XAUI Wireside. */ 3550 /* MC_CMD_LOOPBACK_XAUI_WS 0x14 */ 3551 /* enum: XAUI Wireside Far. */ 3552 /* MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 */ 3553 /* enum: XAUI Wireside near. */ 3554 /* MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 */ 3555 /* enum: GMII Wireside. */ 3556 /* MC_CMD_LOOPBACK_GMII_WS 0x17 */ 3557 /* enum: XFI Wireside. */ 3558 /* MC_CMD_LOOPBACK_XFI_WS 0x18 */ 3559 /* enum: XFI Wireside Far. */ 3560 /* MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 */ 3561 /* enum: PhyXS Wireside. */ 3562 /* MC_CMD_LOOPBACK_PHYXS_WS 0x1a */ 3563 /* enum: PMA lanes MAC-Serdes. */ 3564 /* MC_CMD_LOOPBACK_PMA_INT 0x1b */ 3565 /* enum: KR Serdes Parallel (Encoder). */ 3566 /* MC_CMD_LOOPBACK_SD_NEAR 0x1c */ 3567 /* enum: KR Serdes Serial. */ 3568 /* MC_CMD_LOOPBACK_SD_FAR 0x1d */ 3569 /* enum: PMA lanes MAC-Serdes Wireside. */ 3570 /* MC_CMD_LOOPBACK_PMA_INT_WS 0x1e */ 3571 /* enum: KR Serdes Parallel Wireside (Full PCS). */ 3572 /* MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f */ 3573 /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */ 3574 /* MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 */ 3575 /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */ 3576 /* MC_CMD_LOOPBACK_SD_FEP_WS 0x21 */ 3577 /* enum: KR Serdes Serial Wireside. */ 3578 /* MC_CMD_LOOPBACK_SD_FES_WS 0x22 */ 3579 /* enum: Near side of AOE Siena side port */ 3580 /* MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 */ 3581 /* enum: Medford Wireside datapath loopback */ 3582 /* MC_CMD_LOOPBACK_DATA_WS 0x24 */ 3583 /* enum: Force link up without setting up any physical loopback (snapper use 3584 * only) 3585 */ 3586 /* MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 */ 3587 /* Supported loopbacks. */ 3588 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_OFST 8 3589 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LEN 8 3590 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_OFST 8 3591 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_OFST 12 3592 /* Enum values, see field(s): */ 3593 /* 100M */ 3594 /* Supported loopbacks. */ 3595 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_OFST 16 3596 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LEN 8 3597 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_OFST 16 3598 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_OFST 20 3599 /* Enum values, see field(s): */ 3600 /* 100M */ 3601 /* Supported loopbacks. */ 3602 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_OFST 24 3603 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LEN 8 3604 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_OFST 24 3605 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_OFST 28 3606 /* Enum values, see field(s): */ 3607 /* 100M */ 3608 /* Supported loopbacks. */ 3609 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_OFST 32 3610 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LEN 8 3611 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_OFST 32 3612 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_OFST 36 3613 /* Enum values, see field(s): */ 3614 /* 100M */ 3615 /* Supported 25G loopbacks. */ 3616 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST 40 3617 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN 8 3618 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_OFST 40 3619 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_OFST 44 3620 /* Enum values, see field(s): */ 3621 /* 100M */ 3622 /* Supported 50 loopbacks. */ 3623 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST 48 3624 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN 8 3625 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_OFST 48 3626 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_OFST 52 3627 /* Enum values, see field(s): */ 3628 /* 100M */ 3629 /* Supported 100G loopbacks. */ 3630 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST 56 3631 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN 8 3632 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_OFST 56 3633 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_OFST 60 3634 /* Enum values, see field(s): */ 3635 /* 100M */ 3636 3637 /* AN_TYPE structuredef: Auto-negotiation types defined in IEEE802.3 */ 3638 #define AN_TYPE_LEN 4 3639 #define AN_TYPE_TYPE_OFST 0 3640 #define AN_TYPE_TYPE_LEN 4 3641 /* enum: None, AN disabled or not supported */ 3642 #define MC_CMD_AN_NONE 0x0 3643 /* enum: Clause 28 - BASE-T */ 3644 #define MC_CMD_AN_CLAUSE28 0x1 3645 /* enum: Clause 37 - BASE-X */ 3646 #define MC_CMD_AN_CLAUSE37 0x2 3647 /* enum: Clause 73 - BASE-R startup protocol for backplane and copper cable 3648 * assemblies. Includes Clause 72/Clause 92 link-training. 3649 */ 3650 #define MC_CMD_AN_CLAUSE73 0x3 3651 #define AN_TYPE_TYPE_LBN 0 3652 #define AN_TYPE_TYPE_WIDTH 32 3653 3654 /* FEC_TYPE structuredef: Forward error correction types defined in IEEE802.3 3655 */ 3656 #define FEC_TYPE_LEN 4 3657 #define FEC_TYPE_TYPE_OFST 0 3658 #define FEC_TYPE_TYPE_LEN 4 3659 /* enum: No FEC */ 3660 #define MC_CMD_FEC_NONE 0x0 3661 /* enum: Clause 74 BASE-R FEC (a.k.a Firecode) */ 3662 #define MC_CMD_FEC_BASER 0x1 3663 /* enum: Clause 91/Clause 108 Reed-Solomon FEC */ 3664 #define MC_CMD_FEC_RS 0x2 3665 #define FEC_TYPE_TYPE_LBN 0 3666 #define FEC_TYPE_TYPE_WIDTH 32 3667 3668 3669 /***********************************/ 3670 /* MC_CMD_GET_LINK 3671 * Read the unified MAC/PHY link state. Locks required: None Return code: 0, 3672 * ETIME. 3673 */ 3674 #define MC_CMD_GET_LINK 0x29 3675 #undef MC_CMD_0x29_PRIVILEGE_CTG 3676 3677 #define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL 3678 3679 /* MC_CMD_GET_LINK_IN msgrequest */ 3680 #define MC_CMD_GET_LINK_IN_LEN 0 3681 3682 /* MC_CMD_GET_LINK_OUT msgresponse */ 3683 #define MC_CMD_GET_LINK_OUT_LEN 28 3684 /* Near-side advertised capabilities. Refer to 3685 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions. 3686 */ 3687 #define MC_CMD_GET_LINK_OUT_CAP_OFST 0 3688 #define MC_CMD_GET_LINK_OUT_CAP_LEN 4 3689 /* Link-partner advertised capabilities. Refer to 3690 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions. 3691 */ 3692 #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4 3693 #define MC_CMD_GET_LINK_OUT_LP_CAP_LEN 4 3694 /* Autonegotiated speed in mbit/s. The link may still be down even if this 3695 * reads non-zero. 3696 */ 3697 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8 3698 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_LEN 4 3699 /* Current loopback setting. */ 3700 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12 3701 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_LEN 4 3702 /* Enum values, see field(s): */ 3703 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 3704 #define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16 3705 #define MC_CMD_GET_LINK_OUT_FLAGS_LEN 4 3706 #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0 3707 #define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1 3708 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1 3709 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1 3710 #define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2 3711 #define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1 3712 #define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3 3713 #define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1 3714 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6 3715 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1 3716 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7 3717 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1 3718 /* This returns the negotiated flow control value. */ 3719 #define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20 3720 #define MC_CMD_GET_LINK_OUT_FCNTL_LEN 4 3721 /* Enum values, see field(s): */ 3722 /* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */ 3723 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24 3724 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_LEN 4 3725 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 3726 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 3727 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 3728 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 3729 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 3730 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 3731 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 3732 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 3733 3734 /* MC_CMD_GET_LINK_OUT_V2 msgresponse: Extended link state information */ 3735 #define MC_CMD_GET_LINK_OUT_V2_LEN 44 3736 /* Near-side advertised capabilities. Refer to 3737 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions. 3738 */ 3739 #define MC_CMD_GET_LINK_OUT_V2_CAP_OFST 0 3740 #define MC_CMD_GET_LINK_OUT_V2_CAP_LEN 4 3741 /* Link-partner advertised capabilities. Refer to 3742 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions. 3743 */ 3744 #define MC_CMD_GET_LINK_OUT_V2_LP_CAP_OFST 4 3745 #define MC_CMD_GET_LINK_OUT_V2_LP_CAP_LEN 4 3746 /* Autonegotiated speed in mbit/s. The link may still be down even if this 3747 * reads non-zero. 3748 */ 3749 #define MC_CMD_GET_LINK_OUT_V2_LINK_SPEED_OFST 8 3750 #define MC_CMD_GET_LINK_OUT_V2_LINK_SPEED_LEN 4 3751 /* Current loopback setting. */ 3752 #define MC_CMD_GET_LINK_OUT_V2_LOOPBACK_MODE_OFST 12 3753 #define MC_CMD_GET_LINK_OUT_V2_LOOPBACK_MODE_LEN 4 3754 /* Enum values, see field(s): */ 3755 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 3756 #define MC_CMD_GET_LINK_OUT_V2_FLAGS_OFST 16 3757 #define MC_CMD_GET_LINK_OUT_V2_FLAGS_LEN 4 3758 #define MC_CMD_GET_LINK_OUT_V2_LINK_UP_LBN 0 3759 #define MC_CMD_GET_LINK_OUT_V2_LINK_UP_WIDTH 1 3760 #define MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_LBN 1 3761 #define MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_WIDTH 1 3762 #define MC_CMD_GET_LINK_OUT_V2_BPX_LINK_LBN 2 3763 #define MC_CMD_GET_LINK_OUT_V2_BPX_LINK_WIDTH 1 3764 #define MC_CMD_GET_LINK_OUT_V2_PHY_LINK_LBN 3 3765 #define MC_CMD_GET_LINK_OUT_V2_PHY_LINK_WIDTH 1 3766 #define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_LBN 6 3767 #define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_WIDTH 1 3768 #define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_LBN 7 3769 #define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_WIDTH 1 3770 /* This returns the negotiated flow control value. */ 3771 #define MC_CMD_GET_LINK_OUT_V2_FCNTL_OFST 20 3772 #define MC_CMD_GET_LINK_OUT_V2_FCNTL_LEN 4 3773 /* Enum values, see field(s): */ 3774 /* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */ 3775 #define MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_OFST 24 3776 #define MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_LEN 4 3777 /* MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 */ 3778 /* MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 */ 3779 /* MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 */ 3780 /* MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 */ 3781 /* MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 */ 3782 /* MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 */ 3783 /* MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 */ 3784 /* MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 */ 3785 /* True local device capabilities (taking into account currently used PMD/MDI, 3786 * e.g. plugged-in module). In general, subset of 3787 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP, but may include extra _FEC_REQUEST 3788 * bits, if the PMD requires FEC. 0 if unknown (e.g. module unplugged). Equal 3789 * to SUPPORTED_CAP for non-pluggable PMDs. Refer to 3790 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions. 3791 */ 3792 #define MC_CMD_GET_LINK_OUT_V2_LD_CAP_OFST 28 3793 #define MC_CMD_GET_LINK_OUT_V2_LD_CAP_LEN 4 3794 /* Auto-negotiation type used on the link */ 3795 #define MC_CMD_GET_LINK_OUT_V2_AN_TYPE_OFST 32 3796 #define MC_CMD_GET_LINK_OUT_V2_AN_TYPE_LEN 4 3797 /* Enum values, see field(s): */ 3798 /* AN_TYPE/TYPE */ 3799 /* Forward error correction used on the link */ 3800 #define MC_CMD_GET_LINK_OUT_V2_FEC_TYPE_OFST 36 3801 #define MC_CMD_GET_LINK_OUT_V2_FEC_TYPE_LEN 4 3802 /* Enum values, see field(s): */ 3803 /* FEC_TYPE/TYPE */ 3804 #define MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_OFST 40 3805 #define MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_LEN 4 3806 #define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_LBN 0 3807 #define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_WIDTH 1 3808 #define MC_CMD_GET_LINK_OUT_V2_PMD_READY_LBN 1 3809 #define MC_CMD_GET_LINK_OUT_V2_PMD_READY_WIDTH 1 3810 #define MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_LBN 2 3811 #define MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_WIDTH 1 3812 #define MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_LBN 3 3813 #define MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_WIDTH 1 3814 #define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_LBN 4 3815 #define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_WIDTH 1 3816 #define MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_LBN 5 3817 #define MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_WIDTH 1 3818 #define MC_CMD_GET_LINK_OUT_V2_HI_BER_LBN 6 3819 #define MC_CMD_GET_LINK_OUT_V2_HI_BER_WIDTH 1 3820 #define MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_LBN 7 3821 #define MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_WIDTH 1 3822 #define MC_CMD_GET_LINK_OUT_V2_AN_DONE_LBN 8 3823 #define MC_CMD_GET_LINK_OUT_V2_AN_DONE_WIDTH 1 3824 3825 3826 /***********************************/ 3827 /* MC_CMD_SET_LINK 3828 * Write the unified MAC/PHY link configuration. Locks required: None. Return 3829 * code: 0, EINVAL, ETIME 3830 */ 3831 #define MC_CMD_SET_LINK 0x2a 3832 #undef MC_CMD_0x2a_PRIVILEGE_CTG 3833 3834 #define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK 3835 3836 /* MC_CMD_SET_LINK_IN msgrequest */ 3837 #define MC_CMD_SET_LINK_IN_LEN 16 3838 /* Near-side advertised capabilities. Refer to 3839 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions. 3840 */ 3841 #define MC_CMD_SET_LINK_IN_CAP_OFST 0 3842 #define MC_CMD_SET_LINK_IN_CAP_LEN 4 3843 /* Flags */ 3844 #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4 3845 #define MC_CMD_SET_LINK_IN_FLAGS_LEN 4 3846 #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0 3847 #define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1 3848 #define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1 3849 #define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1 3850 #define MC_CMD_SET_LINK_IN_TXDIS_LBN 2 3851 #define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1 3852 /* Loopback mode. */ 3853 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8 3854 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_LEN 4 3855 /* Enum values, see field(s): */ 3856 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 3857 /* A loopback speed of "0" is supported, and means (choose any available 3858 * speed). 3859 */ 3860 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12 3861 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_LEN 4 3862 3863 /* MC_CMD_SET_LINK_OUT msgresponse */ 3864 #define MC_CMD_SET_LINK_OUT_LEN 0 3865 3866 3867 /***********************************/ 3868 /* MC_CMD_SET_ID_LED 3869 * Set identification LED state. Locks required: None. Return code: 0, EINVAL 3870 */ 3871 #define MC_CMD_SET_ID_LED 0x2b 3872 #undef MC_CMD_0x2b_PRIVILEGE_CTG 3873 3874 #define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK 3875 3876 /* MC_CMD_SET_ID_LED_IN msgrequest */ 3877 #define MC_CMD_SET_ID_LED_IN_LEN 4 3878 /* Set LED state. */ 3879 #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0 3880 #define MC_CMD_SET_ID_LED_IN_STATE_LEN 4 3881 #define MC_CMD_LED_OFF 0x0 /* enum */ 3882 #define MC_CMD_LED_ON 0x1 /* enum */ 3883 #define MC_CMD_LED_DEFAULT 0x2 /* enum */ 3884 3885 /* MC_CMD_SET_ID_LED_OUT msgresponse */ 3886 #define MC_CMD_SET_ID_LED_OUT_LEN 0 3887 3888 3889 /***********************************/ 3890 /* MC_CMD_SET_MAC 3891 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL 3892 */ 3893 #define MC_CMD_SET_MAC 0x2c 3894 #undef MC_CMD_0x2c_PRIVILEGE_CTG 3895 3896 #define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 3897 3898 /* MC_CMD_SET_MAC_IN msgrequest */ 3899 #define MC_CMD_SET_MAC_IN_LEN 28 3900 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of 3901 * EtherII, VLAN, bug16011 padding). 3902 */ 3903 #define MC_CMD_SET_MAC_IN_MTU_OFST 0 3904 #define MC_CMD_SET_MAC_IN_MTU_LEN 4 3905 #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4 3906 #define MC_CMD_SET_MAC_IN_DRAIN_LEN 4 3907 #define MC_CMD_SET_MAC_IN_ADDR_OFST 8 3908 #define MC_CMD_SET_MAC_IN_ADDR_LEN 8 3909 #define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8 3910 #define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12 3911 #define MC_CMD_SET_MAC_IN_REJECT_OFST 16 3912 #define MC_CMD_SET_MAC_IN_REJECT_LEN 4 3913 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0 3914 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1 3915 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1 3916 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1 3917 #define MC_CMD_SET_MAC_IN_FCNTL_OFST 20 3918 #define MC_CMD_SET_MAC_IN_FCNTL_LEN 4 3919 /* enum: Flow control is off. */ 3920 #define MC_CMD_FCNTL_OFF 0x0 3921 /* enum: Respond to flow control. */ 3922 #define MC_CMD_FCNTL_RESPOND 0x1 3923 /* enum: Respond to and Issue flow control. */ 3924 #define MC_CMD_FCNTL_BIDIR 0x2 3925 /* enum: Auto neg flow control. */ 3926 #define MC_CMD_FCNTL_AUTO 0x3 3927 /* enum: Priority flow control (eftest builds only). */ 3928 #define MC_CMD_FCNTL_QBB 0x4 3929 /* enum: Issue flow control. */ 3930 #define MC_CMD_FCNTL_GENERATE 0x5 3931 #define MC_CMD_SET_MAC_IN_FLAGS_OFST 24 3932 #define MC_CMD_SET_MAC_IN_FLAGS_LEN 4 3933 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0 3934 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1 3935 3936 /* MC_CMD_SET_MAC_EXT_IN msgrequest */ 3937 #define MC_CMD_SET_MAC_EXT_IN_LEN 32 3938 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of 3939 * EtherII, VLAN, bug16011 padding). 3940 */ 3941 #define MC_CMD_SET_MAC_EXT_IN_MTU_OFST 0 3942 #define MC_CMD_SET_MAC_EXT_IN_MTU_LEN 4 3943 #define MC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 4 3944 #define MC_CMD_SET_MAC_EXT_IN_DRAIN_LEN 4 3945 #define MC_CMD_SET_MAC_EXT_IN_ADDR_OFST 8 3946 #define MC_CMD_SET_MAC_EXT_IN_ADDR_LEN 8 3947 #define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 8 3948 #define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12 3949 #define MC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16 3950 #define MC_CMD_SET_MAC_EXT_IN_REJECT_LEN 4 3951 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0 3952 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 1 3953 #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 1 3954 #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 1 3955 #define MC_CMD_SET_MAC_EXT_IN_FCNTL_OFST 20 3956 #define MC_CMD_SET_MAC_EXT_IN_FCNTL_LEN 4 3957 /* enum: Flow control is off. */ 3958 /* MC_CMD_FCNTL_OFF 0x0 */ 3959 /* enum: Respond to flow control. */ 3960 /* MC_CMD_FCNTL_RESPOND 0x1 */ 3961 /* enum: Respond to and Issue flow control. */ 3962 /* MC_CMD_FCNTL_BIDIR 0x2 */ 3963 /* enum: Auto neg flow control. */ 3964 /* MC_CMD_FCNTL_AUTO 0x3 */ 3965 /* enum: Priority flow control (eftest builds only). */ 3966 /* MC_CMD_FCNTL_QBB 0x4 */ 3967 /* enum: Issue flow control. */ 3968 /* MC_CMD_FCNTL_GENERATE 0x5 */ 3969 #define MC_CMD_SET_MAC_EXT_IN_FLAGS_OFST 24 3970 #define MC_CMD_SET_MAC_EXT_IN_FLAGS_LEN 4 3971 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0 3972 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 1 3973 /* Select which parameters to configure. A parameter will only be modified if 3974 * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in 3975 * capabilities then this field is ignored (and all flags are assumed to be 3976 * set). 3977 */ 3978 #define MC_CMD_SET_MAC_EXT_IN_CONTROL_OFST 28 3979 #define MC_CMD_SET_MAC_EXT_IN_CONTROL_LEN 4 3980 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0 3981 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 1 3982 #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 1 3983 #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_WIDTH 1 3984 #define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_LBN 2 3985 #define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_WIDTH 1 3986 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_LBN 3 3987 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_WIDTH 1 3988 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4 3989 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1 3990 3991 /* MC_CMD_SET_MAC_OUT msgresponse */ 3992 #define MC_CMD_SET_MAC_OUT_LEN 0 3993 3994 /* MC_CMD_SET_MAC_V2_OUT msgresponse */ 3995 #define MC_CMD_SET_MAC_V2_OUT_LEN 4 3996 /* MTU as configured after processing the request. See comment at 3997 * MC_CMD_SET_MAC_IN/MTU. To query MTU without doing any changes, set CONTROL 3998 * to 0. 3999 */ 4000 #define MC_CMD_SET_MAC_V2_OUT_MTU_OFST 0 4001 #define MC_CMD_SET_MAC_V2_OUT_MTU_LEN 4 4002 4003 4004 /***********************************/ 4005 /* MC_CMD_PHY_STATS 4006 * Get generic PHY statistics. This call returns the statistics for a generic 4007 * PHY in a sparse array (indexed by the enumerate). Each value is represented 4008 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the 4009 * statistics may be read from the message response. If DMA_ADDR != 0, then the 4010 * statistics are dmad to that (page-aligned location). Locks required: None. 4011 * Returns: 0, ETIME 4012 */ 4013 #define MC_CMD_PHY_STATS 0x2d 4014 #undef MC_CMD_0x2d_PRIVILEGE_CTG 4015 4016 #define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK 4017 4018 /* MC_CMD_PHY_STATS_IN msgrequest */ 4019 #define MC_CMD_PHY_STATS_IN_LEN 8 4020 /* ??? */ 4021 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0 4022 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8 4023 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0 4024 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4 4025 4026 /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */ 4027 #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0 4028 4029 /* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */ 4030 #define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3) 4031 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0 4032 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4 4033 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS 4034 /* enum: OUI. */ 4035 #define MC_CMD_OUI 0x0 4036 /* enum: PMA-PMD Link Up. */ 4037 #define MC_CMD_PMA_PMD_LINK_UP 0x1 4038 /* enum: PMA-PMD RX Fault. */ 4039 #define MC_CMD_PMA_PMD_RX_FAULT 0x2 4040 /* enum: PMA-PMD TX Fault. */ 4041 #define MC_CMD_PMA_PMD_TX_FAULT 0x3 4042 /* enum: PMA-PMD Signal */ 4043 #define MC_CMD_PMA_PMD_SIGNAL 0x4 4044 /* enum: PMA-PMD SNR A. */ 4045 #define MC_CMD_PMA_PMD_SNR_A 0x5 4046 /* enum: PMA-PMD SNR B. */ 4047 #define MC_CMD_PMA_PMD_SNR_B 0x6 4048 /* enum: PMA-PMD SNR C. */ 4049 #define MC_CMD_PMA_PMD_SNR_C 0x7 4050 /* enum: PMA-PMD SNR D. */ 4051 #define MC_CMD_PMA_PMD_SNR_D 0x8 4052 /* enum: PCS Link Up. */ 4053 #define MC_CMD_PCS_LINK_UP 0x9 4054 /* enum: PCS RX Fault. */ 4055 #define MC_CMD_PCS_RX_FAULT 0xa 4056 /* enum: PCS TX Fault. */ 4057 #define MC_CMD_PCS_TX_FAULT 0xb 4058 /* enum: PCS BER. */ 4059 #define MC_CMD_PCS_BER 0xc 4060 /* enum: PCS Block Errors. */ 4061 #define MC_CMD_PCS_BLOCK_ERRORS 0xd 4062 /* enum: PhyXS Link Up. */ 4063 #define MC_CMD_PHYXS_LINK_UP 0xe 4064 /* enum: PhyXS RX Fault. */ 4065 #define MC_CMD_PHYXS_RX_FAULT 0xf 4066 /* enum: PhyXS TX Fault. */ 4067 #define MC_CMD_PHYXS_TX_FAULT 0x10 4068 /* enum: PhyXS Align. */ 4069 #define MC_CMD_PHYXS_ALIGN 0x11 4070 /* enum: PhyXS Sync. */ 4071 #define MC_CMD_PHYXS_SYNC 0x12 4072 /* enum: AN link-up. */ 4073 #define MC_CMD_AN_LINK_UP 0x13 4074 /* enum: AN Complete. */ 4075 #define MC_CMD_AN_COMPLETE 0x14 4076 /* enum: AN 10GBaseT Status. */ 4077 #define MC_CMD_AN_10GBT_STATUS 0x15 4078 /* enum: Clause 22 Link-Up. */ 4079 #define MC_CMD_CL22_LINK_UP 0x16 4080 /* enum: (Last entry) */ 4081 #define MC_CMD_PHY_NSTATS 0x17 4082 4083 4084 /***********************************/ 4085 /* MC_CMD_MAC_STATS 4086 * Get generic MAC statistics. This call returns unified statistics maintained 4087 * by the MC as it switches between the GMAC and XMAC. The MC will write out 4088 * all supported stats. The driver should zero initialise the buffer to 4089 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is 4090 * performed, and the statistics may be read from the message response. If 4091 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location). 4092 * Locks required: None. The PERIODIC_CLEAR option is not used and now has no 4093 * effect. Returns: 0, ETIME 4094 */ 4095 #define MC_CMD_MAC_STATS 0x2e 4096 #undef MC_CMD_0x2e_PRIVILEGE_CTG 4097 4098 #define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4099 4100 /* MC_CMD_MAC_STATS_IN msgrequest */ 4101 #define MC_CMD_MAC_STATS_IN_LEN 20 4102 /* ??? */ 4103 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0 4104 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8 4105 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0 4106 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4 4107 #define MC_CMD_MAC_STATS_IN_CMD_OFST 8 4108 #define MC_CMD_MAC_STATS_IN_CMD_LEN 4 4109 #define MC_CMD_MAC_STATS_IN_DMA_LBN 0 4110 #define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1 4111 #define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1 4112 #define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1 4113 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2 4114 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1 4115 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3 4116 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1 4117 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4 4118 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1 4119 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5 4120 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1 4121 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16 4122 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16 4123 /* DMA length. Should be set to MAC_STATS_NUM_STATS * sizeof(uint64_t), as 4124 * returned by MC_CMD_GET_CAPABILITIES_V4_OUT. For legacy firmware not 4125 * supporting MC_CMD_GET_CAPABILITIES_V4_OUT, DMA_LEN should be set to 4126 * MC_CMD_MAC_NSTATS * sizeof(uint64_t) 4127 */ 4128 #define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12 4129 #define MC_CMD_MAC_STATS_IN_DMA_LEN_LEN 4 4130 /* port id so vadapter stats can be provided */ 4131 #define MC_CMD_MAC_STATS_IN_PORT_ID_OFST 16 4132 #define MC_CMD_MAC_STATS_IN_PORT_ID_LEN 4 4133 4134 /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */ 4135 #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0 4136 4137 /* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */ 4138 #define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) 4139 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0 4140 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8 4141 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0 4142 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4 4143 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS 4144 #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */ 4145 #define MC_CMD_MAC_DMABUF_START 0x1 /* enum */ 4146 #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */ 4147 #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */ 4148 #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */ 4149 #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */ 4150 #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */ 4151 #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */ 4152 #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */ 4153 #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */ 4154 #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */ 4155 #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */ 4156 #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */ 4157 #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */ 4158 #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */ 4159 #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */ 4160 #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */ 4161 #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */ 4162 #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */ 4163 #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */ 4164 #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */ 4165 #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */ 4166 #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */ 4167 #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */ 4168 #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */ 4169 #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */ 4170 #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */ 4171 #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */ 4172 #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */ 4173 #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */ 4174 #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */ 4175 #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */ 4176 #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */ 4177 #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */ 4178 #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */ 4179 #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */ 4180 #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */ 4181 #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */ 4182 #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */ 4183 #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */ 4184 #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */ 4185 #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */ 4186 #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */ 4187 #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */ 4188 #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */ 4189 #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */ 4190 #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */ 4191 #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */ 4192 #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */ 4193 #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */ 4194 #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */ 4195 #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */ 4196 #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */ 4197 #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */ 4198 #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */ 4199 #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */ 4200 #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */ 4201 #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */ 4202 #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */ 4203 #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */ 4204 #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */ 4205 /* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 4206 * capability only. 4207 */ 4208 #define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c 4209 /* enum: PM discard_bb_overflow counter. Valid for EF10 with 4210 * PM_AND_RXDP_COUNTERS capability only. 4211 */ 4212 #define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d 4213 /* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 4214 * capability only. 4215 */ 4216 #define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e 4217 /* enum: PM discard_vfifo_full counter. Valid for EF10 with 4218 * PM_AND_RXDP_COUNTERS capability only. 4219 */ 4220 #define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f 4221 /* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 4222 * capability only. 4223 */ 4224 #define MC_CMD_MAC_PM_TRUNC_QBB 0x40 4225 /* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 4226 * capability only. 4227 */ 4228 #define MC_CMD_MAC_PM_DISCARD_QBB 0x41 4229 /* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 4230 * capability only. 4231 */ 4232 #define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42 4233 /* enum: RXDP counter: Number of packets dropped due to the queue being 4234 * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 4235 */ 4236 #define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43 4237 /* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10 4238 * with PM_AND_RXDP_COUNTERS capability only. 4239 */ 4240 #define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45 4241 /* enum: RXDP counter: Number of non-host packets. Valid for EF10 with 4242 * PM_AND_RXDP_COUNTERS capability only. 4243 */ 4244 #define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46 4245 /* enum: RXDP counter: Number of times an hlb descriptor fetch was performed. 4246 * Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 4247 */ 4248 #define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47 4249 /* enum: RXDP counter: Number of times the DPCPU waited for an existing 4250 * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 4251 */ 4252 #define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48 4253 #define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */ 4254 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */ 4255 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */ 4256 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */ 4257 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */ 4258 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */ 4259 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */ 4260 #define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */ 4261 #define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */ 4262 #define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */ 4263 #define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */ 4264 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */ 4265 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */ 4266 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */ 4267 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */ 4268 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */ 4269 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */ 4270 #define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */ 4271 #define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */ 4272 #define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */ 4273 /* enum: Start of GMAC stats buffer space, for Siena only. */ 4274 #define MC_CMD_GMAC_DMABUF_START 0x40 4275 /* enum: End of GMAC stats buffer space, for Siena only. */ 4276 #define MC_CMD_GMAC_DMABUF_END 0x5f 4277 /* enum: GENERATION_END value, used together with GENERATION_START to verify 4278 * consistency of DMAd data. For legacy firmware / drivers without extended 4279 * stats (more precisely, when DMA_LEN == MC_CMD_MAC_NSTATS * 4280 * sizeof(uint64_t)), this entry holds the GENERATION_END value. Otherwise, 4281 * this value is invalid/ reserved and GENERATION_END is written as the last 4282 * 64-bit word of the DMA buffer (at DMA_LEN - sizeof(uint64_t)). Note that 4283 * this is consistent with the legacy behaviour, in the sense that entry 96 is 4284 * the last 64-bit word in the buffer when DMA_LEN == MC_CMD_MAC_NSTATS * 4285 * sizeof(uint64_t). See SF-109306-TC, Section 9.2 for details. 4286 */ 4287 #define MC_CMD_MAC_GENERATION_END 0x60 4288 #define MC_CMD_MAC_NSTATS 0x61 /* enum */ 4289 4290 /* MC_CMD_MAC_STATS_V2_OUT_DMA msgresponse */ 4291 #define MC_CMD_MAC_STATS_V2_OUT_DMA_LEN 0 4292 4293 /* MC_CMD_MAC_STATS_V2_OUT_NO_DMA msgresponse */ 4294 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V2*64))>>3) 4295 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_OFST 0 4296 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LEN 8 4297 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_OFST 0 4298 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_OFST 4 4299 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V2 4300 /* enum: Start of FEC stats buffer space, Medford2 and up */ 4301 #define MC_CMD_MAC_FEC_DMABUF_START 0x61 4302 /* enum: Number of uncorrected FEC codewords on link (RS-FEC only for Medford2) 4303 */ 4304 #define MC_CMD_MAC_FEC_UNCORRECTED_ERRORS 0x61 4305 /* enum: Number of corrected FEC codewords on link (RS-FEC only for Medford2) 4306 */ 4307 #define MC_CMD_MAC_FEC_CORRECTED_ERRORS 0x62 4308 /* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */ 4309 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE0 0x63 4310 /* enum: Number of corrected 10-bit symbol errors, lane 1 (RS-FEC only) */ 4311 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE1 0x64 4312 /* enum: Number of corrected 10-bit symbol errors, lane 2 (RS-FEC only) */ 4313 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE2 0x65 4314 /* enum: Number of corrected 10-bit symbol errors, lane 3 (RS-FEC only) */ 4315 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3 0x66 4316 /* enum: This includes the space at offset 103 which is the final 4317 * GENERATION_END in a MAC_STATS_V2 response and otherwise unused. 4318 */ 4319 #define MC_CMD_MAC_NSTATS_V2 0x68 4320 /* Other enum values, see field(s): */ 4321 /* MC_CMD_MAC_STATS_OUT_NO_DMA/STATISTICS */ 4322 4323 /* MC_CMD_MAC_STATS_V3_OUT_DMA msgresponse */ 4324 #define MC_CMD_MAC_STATS_V3_OUT_DMA_LEN 0 4325 4326 /* MC_CMD_MAC_STATS_V3_OUT_NO_DMA msgresponse */ 4327 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V3*64))>>3) 4328 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_OFST 0 4329 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LEN 8 4330 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_OFST 0 4331 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_OFST 4 4332 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V3 4333 /* enum: Start of CTPIO stats buffer space, Medford2 and up */ 4334 #define MC_CMD_MAC_CTPIO_DMABUF_START 0x68 4335 /* enum: Number of CTPIO fallbacks because a DMA packet was in progress on the 4336 * target VI 4337 */ 4338 #define MC_CMD_MAC_CTPIO_VI_BUSY_FALLBACK 0x68 4339 /* enum: Number of times a CTPIO send wrote beyond frame end (informational 4340 * only) 4341 */ 4342 #define MC_CMD_MAC_CTPIO_LONG_WRITE_SUCCESS 0x69 4343 /* enum: Number of CTPIO failures because the TX doorbell was written before 4344 * the end of the frame data 4345 */ 4346 #define MC_CMD_MAC_CTPIO_MISSING_DBELL_FAIL 0x6a 4347 /* enum: Number of CTPIO failures because the internal FIFO overflowed */ 4348 #define MC_CMD_MAC_CTPIO_OVERFLOW_FAIL 0x6b 4349 /* enum: Number of CTPIO failures because the host did not deliver data fast 4350 * enough to avoid MAC underflow 4351 */ 4352 #define MC_CMD_MAC_CTPIO_UNDERFLOW_FAIL 0x6c 4353 /* enum: Number of CTPIO failures because the host did not deliver all the 4354 * frame data within the timeout 4355 */ 4356 #define MC_CMD_MAC_CTPIO_TIMEOUT_FAIL 0x6d 4357 /* enum: Number of CTPIO failures because the frame data arrived out of order 4358 * or with gaps 4359 */ 4360 #define MC_CMD_MAC_CTPIO_NONCONTIG_WR_FAIL 0x6e 4361 /* enum: Number of CTPIO failures because the host started a new frame before 4362 * completing the previous one 4363 */ 4364 #define MC_CMD_MAC_CTPIO_FRM_CLOBBER_FAIL 0x6f 4365 /* enum: Number of CTPIO failures because a write was not a multiple of 32 bits 4366 * or not 32-bit aligned 4367 */ 4368 #define MC_CMD_MAC_CTPIO_INVALID_WR_FAIL 0x70 4369 /* enum: Number of CTPIO fallbacks because another VI on the same port was 4370 * sending a CTPIO frame 4371 */ 4372 #define MC_CMD_MAC_CTPIO_VI_CLOBBER_FALLBACK 0x71 4373 /* enum: Number of CTPIO fallbacks because target VI did not have CTPIO enabled 4374 */ 4375 #define MC_CMD_MAC_CTPIO_UNQUALIFIED_FALLBACK 0x72 4376 /* enum: Number of CTPIO fallbacks because length in header was less than 29 4377 * bytes 4378 */ 4379 #define MC_CMD_MAC_CTPIO_RUNT_FALLBACK 0x73 4380 /* enum: Total number of successful CTPIO sends on this port */ 4381 #define MC_CMD_MAC_CTPIO_SUCCESS 0x74 4382 /* enum: Total number of CTPIO fallbacks on this port */ 4383 #define MC_CMD_MAC_CTPIO_FALLBACK 0x75 4384 /* enum: Total number of CTPIO poisoned frames on this port, whether erased or 4385 * not 4386 */ 4387 #define MC_CMD_MAC_CTPIO_POISON 0x76 4388 /* enum: Total number of CTPIO erased frames on this port */ 4389 #define MC_CMD_MAC_CTPIO_ERASE 0x77 4390 /* enum: This includes the space at offset 120 which is the final 4391 * GENERATION_END in a MAC_STATS_V3 response and otherwise unused. 4392 */ 4393 #define MC_CMD_MAC_NSTATS_V3 0x79 4394 /* Other enum values, see field(s): */ 4395 /* MC_CMD_MAC_STATS_V2_OUT_NO_DMA/STATISTICS */ 4396 4397 /* MC_CMD_MAC_STATS_V4_OUT_DMA msgresponse */ 4398 #define MC_CMD_MAC_STATS_V4_OUT_DMA_LEN 0 4399 4400 /* MC_CMD_MAC_STATS_V4_OUT_NO_DMA msgresponse */ 4401 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V4*64))>>3) 4402 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_OFST 0 4403 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LEN 8 4404 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_OFST 0 4405 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_OFST 4 4406 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V4 4407 /* enum: Start of V4 stats buffer space */ 4408 #define MC_CMD_MAC_V4_DMABUF_START 0x79 4409 /* enum: RXDP counter: Number of packets truncated because scattering was 4410 * disabled. 4411 */ 4412 #define MC_CMD_MAC_RXDP_SCATTER_DISABLED_TRUNC 0x79 4413 /* enum: RXDP counter: Number of times the RXDP head of line blocked waiting 4414 * for descriptors. Will be zero unless RXDP_HLB_IDLE capability is set. 4415 */ 4416 #define MC_CMD_MAC_RXDP_HLB_IDLE 0x7a 4417 /* enum: RXDP counter: Number of times the RXDP timed out while head of line 4418 * blocking. Will be zero unless RXDP_HLB_IDLE capability is set. 4419 */ 4420 #define MC_CMD_MAC_RXDP_HLB_TIMEOUT 0x7b 4421 /* enum: This includes the space at offset 124 which is the final 4422 * GENERATION_END in a MAC_STATS_V4 response and otherwise unused. 4423 */ 4424 #define MC_CMD_MAC_NSTATS_V4 0x7d 4425 /* Other enum values, see field(s): */ 4426 /* MC_CMD_MAC_STATS_V3_OUT_NO_DMA/STATISTICS */ 4427 4428 4429 /***********************************/ 4430 /* MC_CMD_SRIOV 4431 * to be documented 4432 */ 4433 #define MC_CMD_SRIOV 0x30 4434 4435 /* MC_CMD_SRIOV_IN msgrequest */ 4436 #define MC_CMD_SRIOV_IN_LEN 12 4437 #define MC_CMD_SRIOV_IN_ENABLE_OFST 0 4438 #define MC_CMD_SRIOV_IN_ENABLE_LEN 4 4439 #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4 4440 #define MC_CMD_SRIOV_IN_VI_BASE_LEN 4 4441 #define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8 4442 #define MC_CMD_SRIOV_IN_VF_COUNT_LEN 4 4443 4444 /* MC_CMD_SRIOV_OUT msgresponse */ 4445 #define MC_CMD_SRIOV_OUT_LEN 8 4446 #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0 4447 #define MC_CMD_SRIOV_OUT_VI_SCALE_LEN 4 4448 #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4 4449 #define MC_CMD_SRIOV_OUT_VF_TOTAL_LEN 4 4450 4451 /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */ 4452 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32 4453 /* this is only used for the first record */ 4454 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0 4455 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LEN 4 4456 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0 4457 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32 4458 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4 4459 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LEN 4 4460 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32 4461 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32 4462 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8 4463 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8 4464 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8 4465 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12 4466 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64 4467 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64 4468 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16 4469 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LEN 4 4470 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */ 4471 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128 4472 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32 4473 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20 4474 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8 4475 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20 4476 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24 4477 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160 4478 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64 4479 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28 4480 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LEN 4 4481 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224 4482 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32 4483 4484 4485 /***********************************/ 4486 /* MC_CMD_MEMCPY 4487 * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data 4488 * embedded directly in the command. 4489 * 4490 * A common pattern is for a client to use generation counts to signal a dma 4491 * update of a datastructure. To facilitate this, this MCDI operation can 4492 * contain multiple requests which are executed in strict order. Requests take 4493 * the form of duplicating the entire MCDI request continuously (including the 4494 * requests record, which is ignored in all but the first structure) 4495 * 4496 * The source data can either come from a DMA from the host, or it can be 4497 * embedded within the request directly, thereby eliminating a DMA read. To 4498 * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and 4499 * ADDR_LO=offset, and inserts the data at %offset from the start of the 4500 * payload. It's the callers responsibility to ensure that the embedded data 4501 * doesn't overlap the records. 4502 * 4503 * Returns: 0, EINVAL (invalid RID) 4504 */ 4505 #define MC_CMD_MEMCPY 0x31 4506 4507 /* MC_CMD_MEMCPY_IN msgrequest */ 4508 #define MC_CMD_MEMCPY_IN_LENMIN 32 4509 #define MC_CMD_MEMCPY_IN_LENMAX 224 4510 #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num)) 4511 /* see MC_CMD_MEMCPY_RECORD_TYPEDEF */ 4512 #define MC_CMD_MEMCPY_IN_RECORD_OFST 0 4513 #define MC_CMD_MEMCPY_IN_RECORD_LEN 32 4514 #define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1 4515 #define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7 4516 4517 /* MC_CMD_MEMCPY_OUT msgresponse */ 4518 #define MC_CMD_MEMCPY_OUT_LEN 0 4519 4520 4521 /***********************************/ 4522 /* MC_CMD_WOL_FILTER_SET 4523 * Set a WoL filter. 4524 */ 4525 #define MC_CMD_WOL_FILTER_SET 0x32 4526 #undef MC_CMD_0x32_PRIVILEGE_CTG 4527 4528 #define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK 4529 4530 /* MC_CMD_WOL_FILTER_SET_IN msgrequest */ 4531 #define MC_CMD_WOL_FILTER_SET_IN_LEN 192 4532 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 4533 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 4534 #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */ 4535 #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */ 4536 /* A type value of 1 is unused. */ 4537 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 4538 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 4539 /* enum: Magic */ 4540 #define MC_CMD_WOL_TYPE_MAGIC 0x0 4541 /* enum: MS Windows Magic */ 4542 #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 4543 /* enum: IPv4 Syn */ 4544 #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3 4545 /* enum: IPv6 Syn */ 4546 #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4 4547 /* enum: Bitmap */ 4548 #define MC_CMD_WOL_TYPE_BITMAP 0x5 4549 /* enum: Link */ 4550 #define MC_CMD_WOL_TYPE_LINK 0x6 4551 /* enum: (Above this for future use) */ 4552 #define MC_CMD_WOL_TYPE_MAX 0x7 4553 #define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8 4554 #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4 4555 #define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46 4556 4557 /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */ 4558 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16 4559 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 4560 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */ 4561 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 4562 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */ 4563 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8 4564 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8 4565 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8 4566 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12 4567 4568 /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */ 4569 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20 4570 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 4571 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */ 4572 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 4573 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */ 4574 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8 4575 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_LEN 4 4576 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12 4577 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_LEN 4 4578 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16 4579 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2 4580 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18 4581 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2 4582 4583 /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */ 4584 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44 4585 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 4586 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */ 4587 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 4588 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */ 4589 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8 4590 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16 4591 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24 4592 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16 4593 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40 4594 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2 4595 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42 4596 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2 4597 4598 /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */ 4599 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187 4600 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 4601 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */ 4602 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 4603 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */ 4604 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8 4605 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48 4606 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56 4607 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128 4608 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184 4609 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1 4610 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185 4611 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1 4612 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186 4613 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1 4614 4615 /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */ 4616 #define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12 4617 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 4618 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */ 4619 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 4620 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */ 4621 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8 4622 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_LEN 4 4623 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0 4624 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1 4625 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1 4626 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1 4627 4628 /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */ 4629 #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4 4630 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0 4631 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_LEN 4 4632 4633 4634 /***********************************/ 4635 /* MC_CMD_WOL_FILTER_REMOVE 4636 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS 4637 */ 4638 #define MC_CMD_WOL_FILTER_REMOVE 0x33 4639 #undef MC_CMD_0x33_PRIVILEGE_CTG 4640 4641 #define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK 4642 4643 /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */ 4644 #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4 4645 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0 4646 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_LEN 4 4647 4648 /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */ 4649 #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0 4650 4651 4652 /***********************************/ 4653 /* MC_CMD_WOL_FILTER_RESET 4654 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0, 4655 * ENOSYS 4656 */ 4657 #define MC_CMD_WOL_FILTER_RESET 0x34 4658 #undef MC_CMD_0x34_PRIVILEGE_CTG 4659 4660 #define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK 4661 4662 /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */ 4663 #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4 4664 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0 4665 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_LEN 4 4666 #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */ 4667 #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */ 4668 4669 /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */ 4670 #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0 4671 4672 4673 /***********************************/ 4674 /* MC_CMD_SET_MCAST_HASH 4675 * Set the MCAST hash value without otherwise reconfiguring the MAC 4676 */ 4677 #define MC_CMD_SET_MCAST_HASH 0x35 4678 4679 /* MC_CMD_SET_MCAST_HASH_IN msgrequest */ 4680 #define MC_CMD_SET_MCAST_HASH_IN_LEN 32 4681 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0 4682 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16 4683 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16 4684 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16 4685 4686 /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */ 4687 #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0 4688 4689 4690 /***********************************/ 4691 /* MC_CMD_NVRAM_TYPES 4692 * Return bitfield indicating available types of virtual NVRAM partitions. 4693 * Locks required: none. Returns: 0 4694 */ 4695 #define MC_CMD_NVRAM_TYPES 0x36 4696 #undef MC_CMD_0x36_PRIVILEGE_CTG 4697 4698 #define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4699 4700 /* MC_CMD_NVRAM_TYPES_IN msgrequest */ 4701 #define MC_CMD_NVRAM_TYPES_IN_LEN 0 4702 4703 /* MC_CMD_NVRAM_TYPES_OUT msgresponse */ 4704 #define MC_CMD_NVRAM_TYPES_OUT_LEN 4 4705 /* Bit mask of supported types. */ 4706 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0 4707 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_LEN 4 4708 /* enum: Disabled callisto. */ 4709 #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0 4710 /* enum: MC firmware. */ 4711 #define MC_CMD_NVRAM_TYPE_MC_FW 0x1 4712 /* enum: MC backup firmware. */ 4713 #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2 4714 /* enum: Static configuration Port0. */ 4715 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3 4716 /* enum: Static configuration Port1. */ 4717 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4 4718 /* enum: Dynamic configuration Port0. */ 4719 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5 4720 /* enum: Dynamic configuration Port1. */ 4721 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6 4722 /* enum: Expansion Rom. */ 4723 #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7 4724 /* enum: Expansion Rom Configuration Port0. */ 4725 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8 4726 /* enum: Expansion Rom Configuration Port1. */ 4727 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9 4728 /* enum: Phy Configuration Port0. */ 4729 #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa 4730 /* enum: Phy Configuration Port1. */ 4731 #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb 4732 /* enum: Log. */ 4733 #define MC_CMD_NVRAM_TYPE_LOG 0xc 4734 /* enum: FPGA image. */ 4735 #define MC_CMD_NVRAM_TYPE_FPGA 0xd 4736 /* enum: FPGA backup image */ 4737 #define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe 4738 /* enum: FC firmware. */ 4739 #define MC_CMD_NVRAM_TYPE_FC_FW 0xf 4740 /* enum: FC backup firmware. */ 4741 #define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10 4742 /* enum: CPLD image. */ 4743 #define MC_CMD_NVRAM_TYPE_CPLD 0x11 4744 /* enum: Licensing information. */ 4745 #define MC_CMD_NVRAM_TYPE_LICENSE 0x12 4746 /* enum: FC Log. */ 4747 #define MC_CMD_NVRAM_TYPE_FC_LOG 0x13 4748 /* enum: Additional flash on FPGA. */ 4749 #define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14 4750 4751 4752 /***********************************/ 4753 /* MC_CMD_NVRAM_INFO 4754 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0, 4755 * EINVAL (bad type). 4756 */ 4757 #define MC_CMD_NVRAM_INFO 0x37 4758 #undef MC_CMD_0x37_PRIVILEGE_CTG 4759 4760 #define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4761 4762 /* MC_CMD_NVRAM_INFO_IN msgrequest */ 4763 #define MC_CMD_NVRAM_INFO_IN_LEN 4 4764 #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0 4765 #define MC_CMD_NVRAM_INFO_IN_TYPE_LEN 4 4766 /* Enum values, see field(s): */ 4767 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4768 4769 /* MC_CMD_NVRAM_INFO_OUT msgresponse */ 4770 #define MC_CMD_NVRAM_INFO_OUT_LEN 24 4771 #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0 4772 #define MC_CMD_NVRAM_INFO_OUT_TYPE_LEN 4 4773 /* Enum values, see field(s): */ 4774 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4775 #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4 4776 #define MC_CMD_NVRAM_INFO_OUT_SIZE_LEN 4 4777 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8 4778 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_LEN 4 4779 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12 4780 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_LEN 4 4781 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0 4782 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1 4783 #define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1 4784 #define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1 4785 #define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_LBN 2 4786 #define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1 4787 #define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_LBN 5 4788 #define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_WIDTH 1 4789 #define MC_CMD_NVRAM_INFO_OUT_CMAC_LBN 6 4790 #define MC_CMD_NVRAM_INFO_OUT_CMAC_WIDTH 1 4791 #define MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7 4792 #define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1 4793 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16 4794 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_LEN 4 4795 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20 4796 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_LEN 4 4797 4798 /* MC_CMD_NVRAM_INFO_V2_OUT msgresponse */ 4799 #define MC_CMD_NVRAM_INFO_V2_OUT_LEN 28 4800 #define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 0 4801 #define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_LEN 4 4802 /* Enum values, see field(s): */ 4803 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4804 #define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 4 4805 #define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_LEN 4 4806 #define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_OFST 8 4807 #define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_LEN 4 4808 #define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_OFST 12 4809 #define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_LEN 4 4810 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0 4811 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 1 4812 #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 1 4813 #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 1 4814 #define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_LBN 2 4815 #define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1 4816 #define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_LBN 5 4817 #define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_WIDTH 1 4818 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 7 4819 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 1 4820 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_OFST 16 4821 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_LEN 4 4822 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_OFST 20 4823 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_LEN 4 4824 /* Writes must be multiples of this size. Added to support the MUM on Sorrento. 4825 */ 4826 #define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_OFST 24 4827 #define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_LEN 4 4828 4829 4830 /***********************************/ 4831 /* MC_CMD_NVRAM_UPDATE_START 4832 * Start a group of update operations on a virtual NVRAM partition. Locks 4833 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if 4834 * PHY_LOCK required and not held). In an adapter bound to a TSA controller, 4835 * MC_CMD_NVRAM_UPDATE_START can only be used on a subset of partition types 4836 * i.e. static config, dynamic config and expansion ROM config. Attempting to 4837 * perform this operation on a restricted partition will return the error 4838 * EPERM. 4839 */ 4840 #define MC_CMD_NVRAM_UPDATE_START 0x38 4841 #undef MC_CMD_0x38_PRIVILEGE_CTG 4842 4843 #define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4844 4845 /* MC_CMD_NVRAM_UPDATE_START_IN msgrequest: Legacy NVRAM_UPDATE_START request. 4846 * Use NVRAM_UPDATE_START_V2_IN in new code 4847 */ 4848 #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4 4849 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0 4850 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_LEN 4 4851 /* Enum values, see field(s): */ 4852 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4853 4854 /* MC_CMD_NVRAM_UPDATE_START_V2_IN msgrequest: Extended NVRAM_UPDATE_START 4855 * request with additional flags indicating version of command in use. See 4856 * MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended functionality. Use 4857 * paired up with NVRAM_UPDATE_FINISH_V2_IN. 4858 */ 4859 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_LEN 8 4860 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_OFST 0 4861 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_LEN 4 4862 /* Enum values, see field(s): */ 4863 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4864 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_OFST 4 4865 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_LEN 4 4866 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0 4867 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1 4868 4869 /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */ 4870 #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0 4871 4872 4873 /***********************************/ 4874 /* MC_CMD_NVRAM_READ 4875 * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if 4876 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 4877 * PHY_LOCK required and not held) 4878 */ 4879 #define MC_CMD_NVRAM_READ 0x39 4880 #undef MC_CMD_0x39_PRIVILEGE_CTG 4881 4882 #define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4883 4884 /* MC_CMD_NVRAM_READ_IN msgrequest */ 4885 #define MC_CMD_NVRAM_READ_IN_LEN 12 4886 #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0 4887 #define MC_CMD_NVRAM_READ_IN_TYPE_LEN 4 4888 /* Enum values, see field(s): */ 4889 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4890 #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4 4891 #define MC_CMD_NVRAM_READ_IN_OFFSET_LEN 4 4892 /* amount to read in bytes */ 4893 #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8 4894 #define MC_CMD_NVRAM_READ_IN_LENGTH_LEN 4 4895 4896 /* MC_CMD_NVRAM_READ_IN_V2 msgrequest */ 4897 #define MC_CMD_NVRAM_READ_IN_V2_LEN 16 4898 #define MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0 4899 #define MC_CMD_NVRAM_READ_IN_V2_TYPE_LEN 4 4900 /* Enum values, see field(s): */ 4901 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4902 #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4 4903 #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_LEN 4 4904 /* amount to read in bytes */ 4905 #define MC_CMD_NVRAM_READ_IN_V2_LENGTH_OFST 8 4906 #define MC_CMD_NVRAM_READ_IN_V2_LENGTH_LEN 4 4907 /* Optional control info. If a partition is stored with an A/B versioning 4908 * scheme (i.e. in more than one physical partition in NVRAM) the host can set 4909 * this to control which underlying physical partition is used to read data 4910 * from. This allows it to perform a read-modify-write-verify with the write 4911 * lock continuously held by calling NVRAM_UPDATE_START, reading the old 4912 * contents using MODE=TARGET_CURRENT, overwriting the old partition and then 4913 * verifying by reading with MODE=TARGET_BACKUP. 4914 */ 4915 #define MC_CMD_NVRAM_READ_IN_V2_MODE_OFST 12 4916 #define MC_CMD_NVRAM_READ_IN_V2_MODE_LEN 4 4917 /* enum: Same as omitting MODE: caller sees data in current partition unless it 4918 * holds the write lock in which case it sees data in the partition it is 4919 * updating. 4920 */ 4921 #define MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x0 4922 /* enum: Read from the current partition of an A/B pair, even if holding the 4923 * write lock. 4924 */ 4925 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x1 4926 /* enum: Read from the non-current (i.e. to be updated) partition of an A/B 4927 * pair 4928 */ 4929 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x2 4930 4931 /* MC_CMD_NVRAM_READ_OUT msgresponse */ 4932 #define MC_CMD_NVRAM_READ_OUT_LENMIN 1 4933 #define MC_CMD_NVRAM_READ_OUT_LENMAX 252 4934 #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num)) 4935 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0 4936 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1 4937 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1 4938 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252 4939 4940 4941 /***********************************/ 4942 /* MC_CMD_NVRAM_WRITE 4943 * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if 4944 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 4945 * PHY_LOCK required and not held) 4946 */ 4947 #define MC_CMD_NVRAM_WRITE 0x3a 4948 #undef MC_CMD_0x3a_PRIVILEGE_CTG 4949 4950 #define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4951 4952 /* MC_CMD_NVRAM_WRITE_IN msgrequest */ 4953 #define MC_CMD_NVRAM_WRITE_IN_LENMIN 13 4954 #define MC_CMD_NVRAM_WRITE_IN_LENMAX 252 4955 #define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num)) 4956 #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0 4957 #define MC_CMD_NVRAM_WRITE_IN_TYPE_LEN 4 4958 /* Enum values, see field(s): */ 4959 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4960 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4 4961 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_LEN 4 4962 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8 4963 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_LEN 4 4964 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12 4965 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1 4966 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1 4967 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240 4968 4969 /* MC_CMD_NVRAM_WRITE_OUT msgresponse */ 4970 #define MC_CMD_NVRAM_WRITE_OUT_LEN 0 4971 4972 4973 /***********************************/ 4974 /* MC_CMD_NVRAM_ERASE 4975 * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if 4976 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 4977 * PHY_LOCK required and not held) 4978 */ 4979 #define MC_CMD_NVRAM_ERASE 0x3b 4980 #undef MC_CMD_0x3b_PRIVILEGE_CTG 4981 4982 #define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4983 4984 /* MC_CMD_NVRAM_ERASE_IN msgrequest */ 4985 #define MC_CMD_NVRAM_ERASE_IN_LEN 12 4986 #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0 4987 #define MC_CMD_NVRAM_ERASE_IN_TYPE_LEN 4 4988 /* Enum values, see field(s): */ 4989 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4990 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4 4991 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_LEN 4 4992 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8 4993 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_LEN 4 4994 4995 /* MC_CMD_NVRAM_ERASE_OUT msgresponse */ 4996 #define MC_CMD_NVRAM_ERASE_OUT_LEN 0 4997 4998 4999 /***********************************/ 5000 /* MC_CMD_NVRAM_UPDATE_FINISH 5001 * Finish a group of update operations on a virtual NVRAM partition. Locks 5002 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type/offset/ 5003 * length), EACCES (if PHY_LOCK required and not held). In an adapter bound to 5004 * a TSA controller, MC_CMD_NVRAM_UPDATE_FINISH can only be used on a subset of 5005 * partition types i.e. static config, dynamic config and expansion ROM config. 5006 * Attempting to perform this operation on a restricted partition will return 5007 * the error EPERM. 5008 */ 5009 #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c 5010 #undef MC_CMD_0x3c_PRIVILEGE_CTG 5011 5012 #define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5013 5014 /* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest: Legacy NVRAM_UPDATE_FINISH 5015 * request. Use NVRAM_UPDATE_FINISH_V2_IN in new code 5016 */ 5017 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8 5018 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0 5019 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_LEN 4 5020 /* Enum values, see field(s): */ 5021 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 5022 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4 5023 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_LEN 4 5024 5025 /* MC_CMD_NVRAM_UPDATE_FINISH_V2_IN msgrequest: Extended NVRAM_UPDATE_FINISH 5026 * request with additional flags indicating version of NVRAM_UPDATE commands in 5027 * use. See MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended 5028 * functionality. Use paired up with NVRAM_UPDATE_START_V2_IN. 5029 */ 5030 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_LEN 12 5031 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_OFST 0 5032 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_LEN 4 5033 /* Enum values, see field(s): */ 5034 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 5035 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_OFST 4 5036 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_LEN 4 5037 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_OFST 8 5038 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_LEN 4 5039 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0 5040 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1 5041 5042 /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse: Legacy NVRAM_UPDATE_FINISH 5043 * response. Use NVRAM_UPDATE_FINISH_V2_OUT in new code 5044 */ 5045 #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0 5046 5047 /* MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT msgresponse: 5048 * 5049 * Extended NVRAM_UPDATE_FINISH response that communicates the result of secure 5050 * firmware validation where applicable back to the host. 5051 * 5052 * Medford only: For signed firmware images, such as those for medford, the MC 5053 * firmware verifies the signature before marking the firmware image as valid. 5054 * This process takes a few seconds to complete. So is likely to take more than 5055 * the MCDI timeout. Hence signature verification is initiated when 5056 * MC_CMD_NVRAM_UPDATE_FINISH_V2_IN is received by the firmware, however, the 5057 * MCDI command is run in a background MCDI processing thread. This response 5058 * payload includes the results of the signature verification. Note that the 5059 * per-partition nvram lock in firmware is only released after the verification 5060 * has completed. 5061 */ 5062 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_LEN 4 5063 /* Result of nvram update completion processing */ 5064 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_OFST 0 5065 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_LEN 4 5066 /* enum: Invalid return code; only non-zero values are defined. Defined as 5067 * unknown for backwards compatibility with NVRAM_UPDATE_FINISH_OUT. 5068 */ 5069 #define MC_CMD_NVRAM_VERIFY_RC_UNKNOWN 0x0 5070 /* enum: Verify succeeded without any errors. */ 5071 #define MC_CMD_NVRAM_VERIFY_RC_SUCCESS 0x1 5072 /* enum: CMS format verification failed due to an internal error. */ 5073 #define MC_CMD_NVRAM_VERIFY_RC_CMS_CHECK_FAILED 0x2 5074 /* enum: Invalid CMS format in image metadata. */ 5075 #define MC_CMD_NVRAM_VERIFY_RC_INVALID_CMS_FORMAT 0x3 5076 /* enum: Message digest verification failed due to an internal error. */ 5077 #define MC_CMD_NVRAM_VERIFY_RC_MESSAGE_DIGEST_CHECK_FAILED 0x4 5078 /* enum: Error in message digest calculated over the reflash-header, payload 5079 * and reflash-trailer. 5080 */ 5081 #define MC_CMD_NVRAM_VERIFY_RC_BAD_MESSAGE_DIGEST 0x5 5082 /* enum: Signature verification failed due to an internal error. */ 5083 #define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHECK_FAILED 0x6 5084 /* enum: There are no valid signatures in the image. */ 5085 #define MC_CMD_NVRAM_VERIFY_RC_NO_VALID_SIGNATURES 0x7 5086 /* enum: Trusted approvers verification failed due to an internal error. */ 5087 #define MC_CMD_NVRAM_VERIFY_RC_TRUSTED_APPROVERS_CHECK_FAILED 0x8 5088 /* enum: The Trusted approver's list is empty. */ 5089 #define MC_CMD_NVRAM_VERIFY_RC_NO_TRUSTED_APPROVERS 0x9 5090 /* enum: Signature chain verification failed due to an internal error. */ 5091 #define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHAIN_CHECK_FAILED 0xa 5092 /* enum: The signers of the signatures in the image are not listed in the 5093 * Trusted approver's list. 5094 */ 5095 #define MC_CMD_NVRAM_VERIFY_RC_NO_SIGNATURE_MATCH 0xb 5096 /* enum: The image contains a test-signed certificate, but the adapter accepts 5097 * only production signed images. 5098 */ 5099 #define MC_CMD_NVRAM_VERIFY_RC_REJECT_TEST_SIGNED 0xc 5100 /* enum: The image has a lower security level than the current firmware. */ 5101 #define MC_CMD_NVRAM_VERIFY_RC_SECURITY_LEVEL_DOWNGRADE 0xd 5102 5103 5104 /***********************************/ 5105 /* MC_CMD_REBOOT 5106 * Reboot the MC. 5107 * 5108 * The AFTER_ASSERTION flag is intended to be used when the driver notices an 5109 * assertion failure (at which point it is expected to perform a complete tear 5110 * down and reinitialise), to allow both ports to reset the MC once in an 5111 * atomic fashion. 5112 * 5113 * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1, 5114 * which means that they will automatically reboot out of the assertion 5115 * handler, so this is in practise an optional operation. It is still 5116 * recommended that drivers execute this to support custom firmwares with 5117 * REBOOT_ON_ASSERT=0. 5118 * 5119 * Locks required: NONE Returns: Nothing. You get back a response with ERR=1, 5120 * DATALEN=0 5121 */ 5122 #define MC_CMD_REBOOT 0x3d 5123 #undef MC_CMD_0x3d_PRIVILEGE_CTG 5124 5125 #define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 5126 5127 /* MC_CMD_REBOOT_IN msgrequest */ 5128 #define MC_CMD_REBOOT_IN_LEN 4 5129 #define MC_CMD_REBOOT_IN_FLAGS_OFST 0 5130 #define MC_CMD_REBOOT_IN_FLAGS_LEN 4 5131 #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */ 5132 5133 /* MC_CMD_REBOOT_OUT msgresponse */ 5134 #define MC_CMD_REBOOT_OUT_LEN 0 5135 5136 5137 /***********************************/ 5138 /* MC_CMD_SCHEDINFO 5139 * Request scheduler info. Locks required: NONE. Returns: An array of 5140 * (timeslice,maximum overrun), one for each thread, in ascending order of 5141 * thread address. 5142 */ 5143 #define MC_CMD_SCHEDINFO 0x3e 5144 #undef MC_CMD_0x3e_PRIVILEGE_CTG 5145 5146 #define MC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5147 5148 /* MC_CMD_SCHEDINFO_IN msgrequest */ 5149 #define MC_CMD_SCHEDINFO_IN_LEN 0 5150 5151 /* MC_CMD_SCHEDINFO_OUT msgresponse */ 5152 #define MC_CMD_SCHEDINFO_OUT_LENMIN 4 5153 #define MC_CMD_SCHEDINFO_OUT_LENMAX 252 5154 #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num)) 5155 #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0 5156 #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4 5157 #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1 5158 #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63 5159 5160 5161 /***********************************/ 5162 /* MC_CMD_REBOOT_MODE 5163 * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot 5164 * mode to the specified value. Returns the old mode. 5165 */ 5166 #define MC_CMD_REBOOT_MODE 0x3f 5167 #undef MC_CMD_0x3f_PRIVILEGE_CTG 5168 5169 #define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_INSECURE 5170 5171 /* MC_CMD_REBOOT_MODE_IN msgrequest */ 5172 #define MC_CMD_REBOOT_MODE_IN_LEN 4 5173 #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0 5174 #define MC_CMD_REBOOT_MODE_IN_VALUE_LEN 4 5175 /* enum: Normal. */ 5176 #define MC_CMD_REBOOT_MODE_NORMAL 0x0 5177 /* enum: Power-on Reset. */ 5178 #define MC_CMD_REBOOT_MODE_POR 0x2 5179 /* enum: Snapper. */ 5180 #define MC_CMD_REBOOT_MODE_SNAPPER 0x3 5181 /* enum: snapper fake POR */ 5182 #define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4 5183 #define MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7 5184 #define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1 5185 5186 /* MC_CMD_REBOOT_MODE_OUT msgresponse */ 5187 #define MC_CMD_REBOOT_MODE_OUT_LEN 4 5188 #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0 5189 #define MC_CMD_REBOOT_MODE_OUT_VALUE_LEN 4 5190 5191 5192 /***********************************/ 5193 /* MC_CMD_SENSOR_INFO 5194 * Returns information about every available sensor. 5195 * 5196 * Each sensor has a single (16bit) value, and a corresponding state. The 5197 * mapping between value and state is nominally determined by the MC, but may 5198 * be implemented using up to 2 ranges per sensor. 5199 * 5200 * This call returns a mask (32bit) of the sensors that are supported by this 5201 * platform, then an array of sensor information structures, in order of sensor 5202 * type (but without gaps for unimplemented sensors). Each structure defines 5203 * the ranges for the corresponding sensor. An unused range is indicated by 5204 * equal limit values. If one range is used, a value outside that range results 5205 * in STATE_FATAL. If two ranges are used, a value outside the second range 5206 * results in STATE_FATAL while a value outside the first and inside the second 5207 * range results in STATE_WARNING. 5208 * 5209 * Sensor masks and sensor information arrays are organised into pages. For 5210 * backward compatibility, older host software can only use sensors in page 0. 5211 * Bit 32 in the sensor mask was previously unused, and is no reserved for use 5212 * as the next page flag. 5213 * 5214 * If the request does not contain a PAGE value then firmware will only return 5215 * page 0 of sensor information, with bit 31 in the sensor mask cleared. 5216 * 5217 * If the request contains a PAGE value then firmware responds with the sensor 5218 * mask and sensor information array for that page of sensors. In this case bit 5219 * 31 in the mask is set if another page exists. 5220 * 5221 * Locks required: None Returns: 0 5222 */ 5223 #define MC_CMD_SENSOR_INFO 0x41 5224 #undef MC_CMD_0x41_PRIVILEGE_CTG 5225 5226 #define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5227 5228 /* MC_CMD_SENSOR_INFO_IN msgrequest */ 5229 #define MC_CMD_SENSOR_INFO_IN_LEN 0 5230 5231 /* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */ 5232 #define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4 5233 /* Which page of sensors to report. 5234 * 5235 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit). 5236 * 5237 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc. 5238 */ 5239 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0 5240 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_LEN 4 5241 5242 /* MC_CMD_SENSOR_INFO_OUT msgresponse */ 5243 #define MC_CMD_SENSOR_INFO_OUT_LENMIN 4 5244 #define MC_CMD_SENSOR_INFO_OUT_LENMAX 252 5245 #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num)) 5246 #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0 5247 #define MC_CMD_SENSOR_INFO_OUT_MASK_LEN 4 5248 /* enum: Controller temperature: degC */ 5249 #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0 5250 /* enum: Phy common temperature: degC */ 5251 #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1 5252 /* enum: Controller cooling: bool */ 5253 #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2 5254 /* enum: Phy 0 temperature: degC */ 5255 #define MC_CMD_SENSOR_PHY0_TEMP 0x3 5256 /* enum: Phy 0 cooling: bool */ 5257 #define MC_CMD_SENSOR_PHY0_COOLING 0x4 5258 /* enum: Phy 1 temperature: degC */ 5259 #define MC_CMD_SENSOR_PHY1_TEMP 0x5 5260 /* enum: Phy 1 cooling: bool */ 5261 #define MC_CMD_SENSOR_PHY1_COOLING 0x6 5262 /* enum: 1.0v power: mV */ 5263 #define MC_CMD_SENSOR_IN_1V0 0x7 5264 /* enum: 1.2v power: mV */ 5265 #define MC_CMD_SENSOR_IN_1V2 0x8 5266 /* enum: 1.8v power: mV */ 5267 #define MC_CMD_SENSOR_IN_1V8 0x9 5268 /* enum: 2.5v power: mV */ 5269 #define MC_CMD_SENSOR_IN_2V5 0xa 5270 /* enum: 3.3v power: mV */ 5271 #define MC_CMD_SENSOR_IN_3V3 0xb 5272 /* enum: 12v power: mV */ 5273 #define MC_CMD_SENSOR_IN_12V0 0xc 5274 /* enum: 1.2v analogue power: mV */ 5275 #define MC_CMD_SENSOR_IN_1V2A 0xd 5276 /* enum: reference voltage: mV */ 5277 #define MC_CMD_SENSOR_IN_VREF 0xe 5278 /* enum: AOE FPGA power: mV */ 5279 #define MC_CMD_SENSOR_OUT_VAOE 0xf 5280 /* enum: AOE FPGA temperature: degC */ 5281 #define MC_CMD_SENSOR_AOE_TEMP 0x10 5282 /* enum: AOE FPGA PSU temperature: degC */ 5283 #define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11 5284 /* enum: AOE PSU temperature: degC */ 5285 #define MC_CMD_SENSOR_PSU_TEMP 0x12 5286 /* enum: Fan 0 speed: RPM */ 5287 #define MC_CMD_SENSOR_FAN_0 0x13 5288 /* enum: Fan 1 speed: RPM */ 5289 #define MC_CMD_SENSOR_FAN_1 0x14 5290 /* enum: Fan 2 speed: RPM */ 5291 #define MC_CMD_SENSOR_FAN_2 0x15 5292 /* enum: Fan 3 speed: RPM */ 5293 #define MC_CMD_SENSOR_FAN_3 0x16 5294 /* enum: Fan 4 speed: RPM */ 5295 #define MC_CMD_SENSOR_FAN_4 0x17 5296 /* enum: AOE FPGA input power: mV */ 5297 #define MC_CMD_SENSOR_IN_VAOE 0x18 5298 /* enum: AOE FPGA current: mA */ 5299 #define MC_CMD_SENSOR_OUT_IAOE 0x19 5300 /* enum: AOE FPGA input current: mA */ 5301 #define MC_CMD_SENSOR_IN_IAOE 0x1a 5302 /* enum: NIC power consumption: W */ 5303 #define MC_CMD_SENSOR_NIC_POWER 0x1b 5304 /* enum: 0.9v power voltage: mV */ 5305 #define MC_CMD_SENSOR_IN_0V9 0x1c 5306 /* enum: 0.9v power current: mA */ 5307 #define MC_CMD_SENSOR_IN_I0V9 0x1d 5308 /* enum: 1.2v power current: mA */ 5309 #define MC_CMD_SENSOR_IN_I1V2 0x1e 5310 /* enum: Not a sensor: reserved for the next page flag */ 5311 #define MC_CMD_SENSOR_PAGE0_NEXT 0x1f 5312 /* enum: 0.9v power voltage (at ADC): mV */ 5313 #define MC_CMD_SENSOR_IN_0V9_ADC 0x20 5314 /* enum: Controller temperature 2: degC */ 5315 #define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21 5316 /* enum: Voltage regulator internal temperature: degC */ 5317 #define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22 5318 /* enum: 0.9V voltage regulator temperature: degC */ 5319 #define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23 5320 /* enum: 1.2V voltage regulator temperature: degC */ 5321 #define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24 5322 /* enum: controller internal temperature sensor voltage (internal ADC): mV */ 5323 #define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25 5324 /* enum: controller internal temperature (internal ADC): degC */ 5325 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26 5326 /* enum: controller internal temperature sensor voltage (external ADC): mV */ 5327 #define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27 5328 /* enum: controller internal temperature (external ADC): degC */ 5329 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28 5330 /* enum: ambient temperature: degC */ 5331 #define MC_CMD_SENSOR_AMBIENT_TEMP 0x29 5332 /* enum: air flow: bool */ 5333 #define MC_CMD_SENSOR_AIRFLOW 0x2a 5334 /* enum: voltage between VSS08D and VSS08D at CSR: mV */ 5335 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b 5336 /* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */ 5337 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c 5338 /* enum: Hotpoint temperature: degC */ 5339 #define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d 5340 /* enum: Port 0 PHY power switch over-current: bool */ 5341 #define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e 5342 /* enum: Port 1 PHY power switch over-current: bool */ 5343 #define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f 5344 /* enum: Mop-up microcontroller reference voltage: mV */ 5345 #define MC_CMD_SENSOR_MUM_VCC 0x30 5346 /* enum: 0.9v power phase A voltage: mV */ 5347 #define MC_CMD_SENSOR_IN_0V9_A 0x31 5348 /* enum: 0.9v power phase A current: mA */ 5349 #define MC_CMD_SENSOR_IN_I0V9_A 0x32 5350 /* enum: 0.9V voltage regulator phase A temperature: degC */ 5351 #define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33 5352 /* enum: 0.9v power phase B voltage: mV */ 5353 #define MC_CMD_SENSOR_IN_0V9_B 0x34 5354 /* enum: 0.9v power phase B current: mA */ 5355 #define MC_CMD_SENSOR_IN_I0V9_B 0x35 5356 /* enum: 0.9V voltage regulator phase B temperature: degC */ 5357 #define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36 5358 /* enum: CCOM AVREG 1v2 supply (interval ADC): mV */ 5359 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37 5360 /* enum: CCOM AVREG 1v2 supply (external ADC): mV */ 5361 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38 5362 /* enum: CCOM AVREG 1v8 supply (interval ADC): mV */ 5363 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39 5364 /* enum: CCOM AVREG 1v8 supply (external ADC): mV */ 5365 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a 5366 /* enum: CCOM RTS temperature: degC */ 5367 #define MC_CMD_SENSOR_CONTROLLER_RTS 0x3b 5368 /* enum: Not a sensor: reserved for the next page flag */ 5369 #define MC_CMD_SENSOR_PAGE1_NEXT 0x3f 5370 /* enum: controller internal temperature sensor voltage on master core 5371 * (internal ADC): mV 5372 */ 5373 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40 5374 /* enum: controller internal temperature on master core (internal ADC): degC */ 5375 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41 5376 /* enum: controller internal temperature sensor voltage on master core 5377 * (external ADC): mV 5378 */ 5379 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42 5380 /* enum: controller internal temperature on master core (external ADC): degC */ 5381 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43 5382 /* enum: controller internal temperature on slave core sensor voltage (internal 5383 * ADC): mV 5384 */ 5385 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44 5386 /* enum: controller internal temperature on slave core (internal ADC): degC */ 5387 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45 5388 /* enum: controller internal temperature on slave core sensor voltage (external 5389 * ADC): mV 5390 */ 5391 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46 5392 /* enum: controller internal temperature on slave core (external ADC): degC */ 5393 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47 5394 /* enum: Voltage supplied to the SODIMMs from their power supply: mV */ 5395 #define MC_CMD_SENSOR_SODIMM_VOUT 0x49 5396 /* enum: Temperature of SODIMM 0 (if installed): degC */ 5397 #define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a 5398 /* enum: Temperature of SODIMM 1 (if installed): degC */ 5399 #define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b 5400 /* enum: Voltage supplied to the QSFP #0 from their power supply: mV */ 5401 #define MC_CMD_SENSOR_PHY0_VCC 0x4c 5402 /* enum: Voltage supplied to the QSFP #1 from their power supply: mV */ 5403 #define MC_CMD_SENSOR_PHY1_VCC 0x4d 5404 /* enum: Controller die temperature (TDIODE): degC */ 5405 #define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e 5406 /* enum: Board temperature (front): degC */ 5407 #define MC_CMD_SENSOR_BOARD_FRONT_TEMP 0x4f 5408 /* enum: Board temperature (back): degC */ 5409 #define MC_CMD_SENSOR_BOARD_BACK_TEMP 0x50 5410 /* enum: 1.8v power current: mA */ 5411 #define MC_CMD_SENSOR_IN_I1V8 0x51 5412 /* enum: 2.5v power current: mA */ 5413 #define MC_CMD_SENSOR_IN_I2V5 0x52 5414 /* enum: 3.3v power current: mA */ 5415 #define MC_CMD_SENSOR_IN_I3V3 0x53 5416 /* enum: 12v power current: mA */ 5417 #define MC_CMD_SENSOR_IN_I12V0 0x54 5418 /* enum: 1.3v power: mV */ 5419 #define MC_CMD_SENSOR_IN_1V3 0x55 5420 /* enum: 1.3v power current: mA */ 5421 #define MC_CMD_SENSOR_IN_I1V3 0x56 5422 /* enum: Not a sensor: reserved for the next page flag */ 5423 #define MC_CMD_SENSOR_PAGE2_NEXT 0x5f 5424 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 5425 #define MC_CMD_SENSOR_ENTRY_OFST 4 5426 #define MC_CMD_SENSOR_ENTRY_LEN 8 5427 #define MC_CMD_SENSOR_ENTRY_LO_OFST 4 5428 #define MC_CMD_SENSOR_ENTRY_HI_OFST 8 5429 #define MC_CMD_SENSOR_ENTRY_MINNUM 0 5430 #define MC_CMD_SENSOR_ENTRY_MAXNUM 31 5431 5432 /* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */ 5433 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4 5434 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252 5435 #define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num)) 5436 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0 5437 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_LEN 4 5438 /* Enum values, see field(s): */ 5439 /* MC_CMD_SENSOR_INFO_OUT */ 5440 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31 5441 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1 5442 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 5443 /* MC_CMD_SENSOR_ENTRY_OFST 4 */ 5444 /* MC_CMD_SENSOR_ENTRY_LEN 8 */ 5445 /* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */ 5446 /* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */ 5447 /* MC_CMD_SENSOR_ENTRY_MINNUM 0 */ 5448 /* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */ 5449 5450 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */ 5451 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8 5452 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0 5453 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2 5454 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0 5455 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16 5456 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2 5457 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2 5458 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16 5459 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16 5460 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4 5461 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2 5462 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32 5463 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16 5464 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6 5465 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2 5466 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48 5467 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16 5468 5469 5470 /***********************************/ 5471 /* MC_CMD_READ_SENSORS 5472 * Returns the current reading from each sensor. DMAs an array of sensor 5473 * readings, in order of sensor type (but without gaps for unimplemented 5474 * sensors), into host memory. Each array element is a 5475 * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword. 5476 * 5477 * If the request does not contain the LENGTH field then only sensors 0 to 30 5478 * are reported, to avoid DMA buffer overflow in older host software. If the 5479 * sensor reading require more space than the LENGTH allows, then return 5480 * EINVAL. 5481 * 5482 * The MC will send a SENSOREVT event every time any sensor changes state. The 5483 * driver is responsible for ensuring that it doesn't miss any events. The 5484 * board will function normally if all sensors are in STATE_OK or 5485 * STATE_WARNING. Otherwise the board should not be expected to function. 5486 */ 5487 #define MC_CMD_READ_SENSORS 0x42 5488 #undef MC_CMD_0x42_PRIVILEGE_CTG 5489 5490 #define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5491 5492 /* MC_CMD_READ_SENSORS_IN msgrequest */ 5493 #define MC_CMD_READ_SENSORS_IN_LEN 8 5494 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ 5495 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0 5496 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8 5497 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0 5498 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4 5499 5500 /* MC_CMD_READ_SENSORS_EXT_IN msgrequest */ 5501 #define MC_CMD_READ_SENSORS_EXT_IN_LEN 12 5502 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ 5503 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0 5504 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8 5505 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0 5506 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4 5507 /* Size in bytes of host buffer. */ 5508 #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8 5509 #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_LEN 4 5510 5511 /* MC_CMD_READ_SENSORS_OUT msgresponse */ 5512 #define MC_CMD_READ_SENSORS_OUT_LEN 0 5513 5514 /* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */ 5515 #define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0 5516 5517 /* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */ 5518 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4 5519 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0 5520 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2 5521 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0 5522 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16 5523 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2 5524 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1 5525 /* enum: Ok. */ 5526 #define MC_CMD_SENSOR_STATE_OK 0x0 5527 /* enum: Breached warning threshold. */ 5528 #define MC_CMD_SENSOR_STATE_WARNING 0x1 5529 /* enum: Breached fatal threshold. */ 5530 #define MC_CMD_SENSOR_STATE_FATAL 0x2 5531 /* enum: Fault with sensor. */ 5532 #define MC_CMD_SENSOR_STATE_BROKEN 0x3 5533 /* enum: Sensor is working but does not currently have a reading. */ 5534 #define MC_CMD_SENSOR_STATE_NO_READING 0x4 5535 /* enum: Sensor initialisation failed. */ 5536 #define MC_CMD_SENSOR_STATE_INIT_FAILED 0x5 5537 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16 5538 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8 5539 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3 5540 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1 5541 /* Enum values, see field(s): */ 5542 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 5543 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24 5544 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8 5545 5546 5547 /***********************************/ 5548 /* MC_CMD_GET_PHY_STATE 5549 * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot 5550 * (e.g. due to missing or corrupted firmware). Locks required: None. Return 5551 * code: 0 5552 */ 5553 #define MC_CMD_GET_PHY_STATE 0x43 5554 #undef MC_CMD_0x43_PRIVILEGE_CTG 5555 5556 #define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5557 5558 /* MC_CMD_GET_PHY_STATE_IN msgrequest */ 5559 #define MC_CMD_GET_PHY_STATE_IN_LEN 0 5560 5561 /* MC_CMD_GET_PHY_STATE_OUT msgresponse */ 5562 #define MC_CMD_GET_PHY_STATE_OUT_LEN 4 5563 #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0 5564 #define MC_CMD_GET_PHY_STATE_OUT_STATE_LEN 4 5565 /* enum: Ok. */ 5566 #define MC_CMD_PHY_STATE_OK 0x1 5567 /* enum: Faulty. */ 5568 #define MC_CMD_PHY_STATE_ZOMBIE 0x2 5569 5570 5571 /***********************************/ 5572 /* MC_CMD_SETUP_8021QBB 5573 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to 5574 * disable 802.Qbb for a given priority. 5575 */ 5576 #define MC_CMD_SETUP_8021QBB 0x44 5577 5578 /* MC_CMD_SETUP_8021QBB_IN msgrequest */ 5579 #define MC_CMD_SETUP_8021QBB_IN_LEN 32 5580 #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0 5581 #define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32 5582 5583 /* MC_CMD_SETUP_8021QBB_OUT msgresponse */ 5584 #define MC_CMD_SETUP_8021QBB_OUT_LEN 0 5585 5586 5587 /***********************************/ 5588 /* MC_CMD_WOL_FILTER_GET 5589 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS 5590 */ 5591 #define MC_CMD_WOL_FILTER_GET 0x45 5592 #undef MC_CMD_0x45_PRIVILEGE_CTG 5593 5594 #define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK 5595 5596 /* MC_CMD_WOL_FILTER_GET_IN msgrequest */ 5597 #define MC_CMD_WOL_FILTER_GET_IN_LEN 0 5598 5599 /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */ 5600 #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4 5601 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0 5602 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_LEN 4 5603 5604 5605 /***********************************/ 5606 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD 5607 * Add a protocol offload to NIC for lights-out state. Locks required: None. 5608 * Returns: 0, ENOSYS 5609 */ 5610 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46 5611 #undef MC_CMD_0x46_PRIVILEGE_CTG 5612 5613 #define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK 5614 5615 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */ 5616 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8 5617 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252 5618 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num)) 5619 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 5620 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 5621 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */ 5622 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */ 5623 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4 5624 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4 5625 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1 5626 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62 5627 5628 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */ 5629 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14 5630 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 5631 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */ 5632 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4 5633 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6 5634 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10 5635 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_LEN 4 5636 5637 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */ 5638 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42 5639 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 5640 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */ 5641 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4 5642 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6 5643 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10 5644 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16 5645 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26 5646 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16 5647 5648 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 5649 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4 5650 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0 5651 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_LEN 4 5652 5653 5654 /***********************************/ 5655 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 5656 * Remove a protocol offload from NIC for lights-out state. Locks required: 5657 * None. Returns: 0, ENOSYS 5658 */ 5659 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47 5660 #undef MC_CMD_0x47_PRIVILEGE_CTG 5661 5662 #define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK 5663 5664 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */ 5665 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8 5666 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 5667 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 5668 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4 5669 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_LEN 4 5670 5671 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 5672 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0 5673 5674 5675 /***********************************/ 5676 /* MC_CMD_MAC_RESET_RESTORE 5677 * Restore MAC after block reset. Locks required: None. Returns: 0. 5678 */ 5679 #define MC_CMD_MAC_RESET_RESTORE 0x48 5680 5681 /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */ 5682 #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0 5683 5684 /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */ 5685 #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0 5686 5687 5688 /***********************************/ 5689 /* MC_CMD_TESTASSERT 5690 * Deliberately trigger an assert-detonation in the firmware for testing 5691 * purposes (i.e. to allow tests that the driver copes gracefully). Locks 5692 * required: None Returns: 0 5693 */ 5694 #define MC_CMD_TESTASSERT 0x49 5695 #undef MC_CMD_0x49_PRIVILEGE_CTG 5696 5697 #define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 5698 5699 /* MC_CMD_TESTASSERT_IN msgrequest */ 5700 #define MC_CMD_TESTASSERT_IN_LEN 0 5701 5702 /* MC_CMD_TESTASSERT_OUT msgresponse */ 5703 #define MC_CMD_TESTASSERT_OUT_LEN 0 5704 5705 /* MC_CMD_TESTASSERT_V2_IN msgrequest */ 5706 #define MC_CMD_TESTASSERT_V2_IN_LEN 4 5707 /* How to provoke the assertion */ 5708 #define MC_CMD_TESTASSERT_V2_IN_TYPE_OFST 0 5709 #define MC_CMD_TESTASSERT_V2_IN_TYPE_LEN 4 5710 /* enum: Assert using the FAIL_ASSERTION_WITH_USEFUL_VALUES macro. Unless 5711 * you're testing firmware, this is what you want. 5712 */ 5713 #define MC_CMD_TESTASSERT_V2_IN_FAIL_ASSERTION_WITH_USEFUL_VALUES 0x0 5714 /* enum: Assert using assert(0); */ 5715 #define MC_CMD_TESTASSERT_V2_IN_ASSERT_FALSE 0x1 5716 /* enum: Deliberately trigger a watchdog */ 5717 #define MC_CMD_TESTASSERT_V2_IN_WATCHDOG 0x2 5718 /* enum: Deliberately trigger a trap by loading from an invalid address */ 5719 #define MC_CMD_TESTASSERT_V2_IN_LOAD_TRAP 0x3 5720 /* enum: Deliberately trigger a trap by storing to an invalid address */ 5721 #define MC_CMD_TESTASSERT_V2_IN_STORE_TRAP 0x4 5722 /* enum: Jump to an invalid address */ 5723 #define MC_CMD_TESTASSERT_V2_IN_JUMP_TRAP 0x5 5724 5725 /* MC_CMD_TESTASSERT_V2_OUT msgresponse */ 5726 #define MC_CMD_TESTASSERT_V2_OUT_LEN 0 5727 5728 5729 /***********************************/ 5730 /* MC_CMD_WORKAROUND 5731 * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't 5732 * understand the given workaround number - which should not be treated as a 5733 * hard error by client code. This op does not imply any semantics about each 5734 * workaround, that's between the driver and the mcfw on a per-workaround 5735 * basis. Locks required: None. Returns: 0, EINVAL . 5736 */ 5737 #define MC_CMD_WORKAROUND 0x4a 5738 #undef MC_CMD_0x4a_PRIVILEGE_CTG 5739 5740 #define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5741 5742 /* MC_CMD_WORKAROUND_IN msgrequest */ 5743 #define MC_CMD_WORKAROUND_IN_LEN 8 5744 /* The enums here must correspond with those in MC_CMD_GET_WORKAROUND. */ 5745 #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0 5746 #define MC_CMD_WORKAROUND_IN_TYPE_LEN 4 5747 /* enum: Bug 17230 work around. */ 5748 #define MC_CMD_WORKAROUND_BUG17230 0x1 5749 /* enum: Bug 35388 work around (unsafe EVQ writes). */ 5750 #define MC_CMD_WORKAROUND_BUG35388 0x2 5751 /* enum: Bug35017 workaround (A64 tables must be identity map) */ 5752 #define MC_CMD_WORKAROUND_BUG35017 0x3 5753 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ 5754 #define MC_CMD_WORKAROUND_BUG41750 0x4 5755 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution 5756 * - before adding code that queries this workaround, remember that there's 5757 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, 5758 * and will hence (incorrectly) report that the bug doesn't exist. 5759 */ 5760 #define MC_CMD_WORKAROUND_BUG42008 0x5 5761 /* enum: Bug 26807 features present in firmware (multicast filter chaining) 5762 * This feature cannot be turned on/off while there are any filters already 5763 * present. The behaviour in such case depends on the acting client's privilege 5764 * level. If the client has the admin privilege, then all functions that have 5765 * filters installed will be FLRed and the FLR_DONE flag will be set. Otherwise 5766 * the command will fail with MC_CMD_ERR_FILTERS_PRESENT. 5767 */ 5768 #define MC_CMD_WORKAROUND_BUG26807 0x6 5769 /* enum: Bug 61265 work around (broken EVQ TMR writes). */ 5770 #define MC_CMD_WORKAROUND_BUG61265 0x7 5771 /* 0 = disable the workaround indicated by TYPE; any non-zero value = enable 5772 * the workaround 5773 */ 5774 #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4 5775 #define MC_CMD_WORKAROUND_IN_ENABLED_LEN 4 5776 5777 /* MC_CMD_WORKAROUND_OUT msgresponse */ 5778 #define MC_CMD_WORKAROUND_OUT_LEN 0 5779 5780 /* MC_CMD_WORKAROUND_EXT_OUT msgresponse: This response format will be used 5781 * when (TYPE == MC_CMD_WORKAROUND_BUG26807) 5782 */ 5783 #define MC_CMD_WORKAROUND_EXT_OUT_LEN 4 5784 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0 5785 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_LEN 4 5786 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0 5787 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1 5788 5789 5790 /***********************************/ 5791 /* MC_CMD_GET_PHY_MEDIA_INFO 5792 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for 5793 * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG 5794 * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the 5795 * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1 5796 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80. 5797 * Anything else: currently undefined. Locks required: None. Return code: 0. 5798 */ 5799 #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b 5800 #undef MC_CMD_0x4b_PRIVILEGE_CTG 5801 5802 #define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5803 5804 /* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */ 5805 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4 5806 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0 5807 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_LEN 4 5808 5809 /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */ 5810 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5 5811 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252 5812 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num)) 5813 /* in bytes */ 5814 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0 5815 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_LEN 4 5816 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4 5817 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1 5818 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1 5819 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248 5820 5821 5822 /***********************************/ 5823 /* MC_CMD_NVRAM_TEST 5824 * Test a particular NVRAM partition for valid contents (where "valid" depends 5825 * on the type of partition). 5826 */ 5827 #define MC_CMD_NVRAM_TEST 0x4c 5828 #undef MC_CMD_0x4c_PRIVILEGE_CTG 5829 5830 #define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 5831 5832 /* MC_CMD_NVRAM_TEST_IN msgrequest */ 5833 #define MC_CMD_NVRAM_TEST_IN_LEN 4 5834 #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0 5835 #define MC_CMD_NVRAM_TEST_IN_TYPE_LEN 4 5836 /* Enum values, see field(s): */ 5837 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 5838 5839 /* MC_CMD_NVRAM_TEST_OUT msgresponse */ 5840 #define MC_CMD_NVRAM_TEST_OUT_LEN 4 5841 #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0 5842 #define MC_CMD_NVRAM_TEST_OUT_RESULT_LEN 4 5843 /* enum: Passed. */ 5844 #define MC_CMD_NVRAM_TEST_PASS 0x0 5845 /* enum: Failed. */ 5846 #define MC_CMD_NVRAM_TEST_FAIL 0x1 5847 /* enum: Not supported. */ 5848 #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2 5849 5850 5851 /***********************************/ 5852 /* MC_CMD_MRSFP_TWEAK 5853 * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds. 5854 * I2C I/O expander bits are always read; if equaliser parameters are supplied, 5855 * they are configured first. Locks required: None. Return code: 0, EINVAL. 5856 */ 5857 #define MC_CMD_MRSFP_TWEAK 0x4d 5858 5859 /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */ 5860 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16 5861 /* 0-6 low->high de-emph. */ 5862 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0 5863 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_LEN 4 5864 /* 0-8 low->high ref.V */ 5865 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4 5866 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_LEN 4 5867 /* 0-8 0-8 low->high boost */ 5868 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8 5869 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_LEN 4 5870 /* 0-8 low->high ref.V */ 5871 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12 5872 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_LEN 4 5873 5874 /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */ 5875 #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0 5876 5877 /* MC_CMD_MRSFP_TWEAK_OUT msgresponse */ 5878 #define MC_CMD_MRSFP_TWEAK_OUT_LEN 12 5879 /* input bits */ 5880 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0 5881 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_LEN 4 5882 /* output bits */ 5883 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4 5884 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_LEN 4 5885 /* direction */ 5886 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8 5887 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_LEN 4 5888 /* enum: Out. */ 5889 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0 5890 /* enum: In. */ 5891 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1 5892 5893 5894 /***********************************/ 5895 /* MC_CMD_SENSOR_SET_LIMS 5896 * Adjusts the sensor limits. This is a warranty-voiding operation. Returns: 5897 * ENOENT if the sensor specified does not exist, EINVAL if the limits are out 5898 * of range. 5899 */ 5900 #define MC_CMD_SENSOR_SET_LIMS 0x4e 5901 #undef MC_CMD_0x4e_PRIVILEGE_CTG 5902 5903 #define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_INSECURE 5904 5905 /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */ 5906 #define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20 5907 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0 5908 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_LEN 4 5909 /* Enum values, see field(s): */ 5910 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 5911 /* interpretation is is sensor-specific. */ 5912 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4 5913 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_LEN 4 5914 /* interpretation is is sensor-specific. */ 5915 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8 5916 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_LEN 4 5917 /* interpretation is is sensor-specific. */ 5918 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12 5919 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_LEN 4 5920 /* interpretation is is sensor-specific. */ 5921 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16 5922 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_LEN 4 5923 5924 /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */ 5925 #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0 5926 5927 5928 /***********************************/ 5929 /* MC_CMD_GET_RESOURCE_LIMITS 5930 */ 5931 #define MC_CMD_GET_RESOURCE_LIMITS 0x4f 5932 5933 /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */ 5934 #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0 5935 5936 /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */ 5937 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16 5938 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0 5939 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_LEN 4 5940 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4 5941 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_LEN 4 5942 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8 5943 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_LEN 4 5944 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12 5945 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_LEN 4 5946 5947 5948 /***********************************/ 5949 /* MC_CMD_NVRAM_PARTITIONS 5950 * Reads the list of available virtual NVRAM partition types. Locks required: 5951 * none. Returns: 0, EINVAL (bad type). 5952 */ 5953 #define MC_CMD_NVRAM_PARTITIONS 0x51 5954 #undef MC_CMD_0x51_PRIVILEGE_CTG 5955 5956 #define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5957 5958 /* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */ 5959 #define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0 5960 5961 /* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */ 5962 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4 5963 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252 5964 #define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num)) 5965 /* total number of partitions */ 5966 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0 5967 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_LEN 4 5968 /* type ID code for each of NUM_PARTITIONS partitions */ 5969 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4 5970 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4 5971 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0 5972 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62 5973 5974 5975 /***********************************/ 5976 /* MC_CMD_NVRAM_METADATA 5977 * Reads soft metadata for a virtual NVRAM partition type. Locks required: 5978 * none. Returns: 0, EINVAL (bad type). 5979 */ 5980 #define MC_CMD_NVRAM_METADATA 0x52 5981 #undef MC_CMD_0x52_PRIVILEGE_CTG 5982 5983 #define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5984 5985 /* MC_CMD_NVRAM_METADATA_IN msgrequest */ 5986 #define MC_CMD_NVRAM_METADATA_IN_LEN 4 5987 /* Partition type ID code */ 5988 #define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0 5989 #define MC_CMD_NVRAM_METADATA_IN_TYPE_LEN 4 5990 5991 /* MC_CMD_NVRAM_METADATA_OUT msgresponse */ 5992 #define MC_CMD_NVRAM_METADATA_OUT_LENMIN 20 5993 #define MC_CMD_NVRAM_METADATA_OUT_LENMAX 252 5994 #define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num)) 5995 /* Partition type ID code */ 5996 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0 5997 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_LEN 4 5998 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4 5999 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_LEN 4 6000 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0 6001 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1 6002 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1 6003 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1 6004 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2 6005 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1 6006 /* Subtype ID code for content of this partition */ 6007 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8 6008 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_LEN 4 6009 /* 1st component of W.X.Y.Z version number for content of this partition */ 6010 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12 6011 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2 6012 /* 2nd component of W.X.Y.Z version number for content of this partition */ 6013 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14 6014 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2 6015 /* 3rd component of W.X.Y.Z version number for content of this partition */ 6016 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16 6017 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2 6018 /* 4th component of W.X.Y.Z version number for content of this partition */ 6019 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18 6020 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2 6021 /* Zero-terminated string describing the content of this partition */ 6022 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20 6023 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1 6024 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0 6025 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232 6026 6027 6028 /***********************************/ 6029 /* MC_CMD_GET_MAC_ADDRESSES 6030 * Returns the base MAC, count and stride for the requesting function 6031 */ 6032 #define MC_CMD_GET_MAC_ADDRESSES 0x55 6033 #undef MC_CMD_0x55_PRIVILEGE_CTG 6034 6035 #define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6036 6037 /* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */ 6038 #define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0 6039 6040 /* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */ 6041 #define MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16 6042 /* Base MAC address */ 6043 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0 6044 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6 6045 /* Padding */ 6046 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6 6047 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2 6048 /* Number of allocated MAC addresses */ 6049 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8 6050 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_LEN 4 6051 /* Spacing of allocated MAC addresses */ 6052 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12 6053 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_LEN 4 6054 6055 6056 /***********************************/ 6057 /* MC_CMD_CLP 6058 * Perform a CLP related operation 6059 */ 6060 #define MC_CMD_CLP 0x56 6061 #undef MC_CMD_0x56_PRIVILEGE_CTG 6062 6063 #define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 6064 6065 /* MC_CMD_CLP_IN msgrequest */ 6066 #define MC_CMD_CLP_IN_LEN 4 6067 /* Sub operation */ 6068 #define MC_CMD_CLP_IN_OP_OFST 0 6069 #define MC_CMD_CLP_IN_OP_LEN 4 6070 /* enum: Return to factory default settings */ 6071 #define MC_CMD_CLP_OP_DEFAULT 0x1 6072 /* enum: Set MAC address */ 6073 #define MC_CMD_CLP_OP_SET_MAC 0x2 6074 /* enum: Get MAC address */ 6075 #define MC_CMD_CLP_OP_GET_MAC 0x3 6076 /* enum: Set UEFI/GPXE boot mode */ 6077 #define MC_CMD_CLP_OP_SET_BOOT 0x4 6078 /* enum: Get UEFI/GPXE boot mode */ 6079 #define MC_CMD_CLP_OP_GET_BOOT 0x5 6080 6081 /* MC_CMD_CLP_OUT msgresponse */ 6082 #define MC_CMD_CLP_OUT_LEN 0 6083 6084 /* MC_CMD_CLP_IN_DEFAULT msgrequest */ 6085 #define MC_CMD_CLP_IN_DEFAULT_LEN 4 6086 /* MC_CMD_CLP_IN_OP_OFST 0 */ 6087 /* MC_CMD_CLP_IN_OP_LEN 4 */ 6088 6089 /* MC_CMD_CLP_OUT_DEFAULT msgresponse */ 6090 #define MC_CMD_CLP_OUT_DEFAULT_LEN 0 6091 6092 /* MC_CMD_CLP_IN_SET_MAC msgrequest */ 6093 #define MC_CMD_CLP_IN_SET_MAC_LEN 12 6094 /* MC_CMD_CLP_IN_OP_OFST 0 */ 6095 /* MC_CMD_CLP_IN_OP_LEN 4 */ 6096 /* MAC address assigned to port */ 6097 #define MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4 6098 #define MC_CMD_CLP_IN_SET_MAC_ADDR_LEN 6 6099 /* Padding */ 6100 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_OFST 10 6101 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_LEN 2 6102 6103 /* MC_CMD_CLP_OUT_SET_MAC msgresponse */ 6104 #define MC_CMD_CLP_OUT_SET_MAC_LEN 0 6105 6106 /* MC_CMD_CLP_IN_GET_MAC msgrequest */ 6107 #define MC_CMD_CLP_IN_GET_MAC_LEN 4 6108 /* MC_CMD_CLP_IN_OP_OFST 0 */ 6109 /* MC_CMD_CLP_IN_OP_LEN 4 */ 6110 6111 /* MC_CMD_CLP_OUT_GET_MAC msgresponse */ 6112 #define MC_CMD_CLP_OUT_GET_MAC_LEN 8 6113 /* MAC address assigned to port */ 6114 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0 6115 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_LEN 6 6116 /* Padding */ 6117 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_OFST 6 6118 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_LEN 2 6119 6120 /* MC_CMD_CLP_IN_SET_BOOT msgrequest */ 6121 #define MC_CMD_CLP_IN_SET_BOOT_LEN 5 6122 /* MC_CMD_CLP_IN_OP_OFST 0 */ 6123 /* MC_CMD_CLP_IN_OP_LEN 4 */ 6124 /* Boot flag */ 6125 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4 6126 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 1 6127 6128 /* MC_CMD_CLP_OUT_SET_BOOT msgresponse */ 6129 #define MC_CMD_CLP_OUT_SET_BOOT_LEN 0 6130 6131 /* MC_CMD_CLP_IN_GET_BOOT msgrequest */ 6132 #define MC_CMD_CLP_IN_GET_BOOT_LEN 4 6133 /* MC_CMD_CLP_IN_OP_OFST 0 */ 6134 /* MC_CMD_CLP_IN_OP_LEN 4 */ 6135 6136 /* MC_CMD_CLP_OUT_GET_BOOT msgresponse */ 6137 #define MC_CMD_CLP_OUT_GET_BOOT_LEN 4 6138 /* Boot flag */ 6139 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0 6140 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 1 6141 /* Padding */ 6142 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 1 6143 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_LEN 3 6144 6145 6146 /***********************************/ 6147 /* MC_CMD_MUM 6148 * Perform a MUM operation 6149 */ 6150 #define MC_CMD_MUM 0x57 6151 #undef MC_CMD_0x57_PRIVILEGE_CTG 6152 6153 #define MC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_INSECURE 6154 6155 /* MC_CMD_MUM_IN msgrequest */ 6156 #define MC_CMD_MUM_IN_LEN 4 6157 #define MC_CMD_MUM_IN_OP_HDR_OFST 0 6158 #define MC_CMD_MUM_IN_OP_HDR_LEN 4 6159 #define MC_CMD_MUM_IN_OP_LBN 0 6160 #define MC_CMD_MUM_IN_OP_WIDTH 8 6161 /* enum: NULL MCDI command to MUM */ 6162 #define MC_CMD_MUM_OP_NULL 0x1 6163 /* enum: Get MUM version */ 6164 #define MC_CMD_MUM_OP_GET_VERSION 0x2 6165 /* enum: Issue raw I2C command to MUM */ 6166 #define MC_CMD_MUM_OP_RAW_CMD 0x3 6167 /* enum: Read from registers on devices connected to MUM. */ 6168 #define MC_CMD_MUM_OP_READ 0x4 6169 /* enum: Write to registers on devices connected to MUM. */ 6170 #define MC_CMD_MUM_OP_WRITE 0x5 6171 /* enum: Control UART logging. */ 6172 #define MC_CMD_MUM_OP_LOG 0x6 6173 /* enum: Operations on MUM GPIO lines */ 6174 #define MC_CMD_MUM_OP_GPIO 0x7 6175 /* enum: Get sensor readings from MUM */ 6176 #define MC_CMD_MUM_OP_READ_SENSORS 0x8 6177 /* enum: Initiate clock programming on the MUM */ 6178 #define MC_CMD_MUM_OP_PROGRAM_CLOCKS 0x9 6179 /* enum: Initiate FPGA load from flash on the MUM */ 6180 #define MC_CMD_MUM_OP_FPGA_LOAD 0xa 6181 /* enum: Request sensor reading from MUM ADC resulting from earlier request via 6182 * MUM ATB 6183 */ 6184 #define MC_CMD_MUM_OP_READ_ATB_SENSOR 0xb 6185 /* enum: Send commands relating to the QSFP ports via the MUM for PHY 6186 * operations 6187 */ 6188 #define MC_CMD_MUM_OP_QSFP 0xc 6189 /* enum: Request discrete and SODIMM DDR info (type, size, speed grade, voltage 6190 * level) from MUM 6191 */ 6192 #define MC_CMD_MUM_OP_READ_DDR_INFO 0xd 6193 6194 /* MC_CMD_MUM_IN_NULL msgrequest */ 6195 #define MC_CMD_MUM_IN_NULL_LEN 4 6196 /* MUM cmd header */ 6197 #define MC_CMD_MUM_IN_CMD_OFST 0 6198 #define MC_CMD_MUM_IN_CMD_LEN 4 6199 6200 /* MC_CMD_MUM_IN_GET_VERSION msgrequest */ 6201 #define MC_CMD_MUM_IN_GET_VERSION_LEN 4 6202 /* MUM cmd header */ 6203 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6204 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6205 6206 /* MC_CMD_MUM_IN_READ msgrequest */ 6207 #define MC_CMD_MUM_IN_READ_LEN 16 6208 /* MUM cmd header */ 6209 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6210 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6211 /* ID of (device connected to MUM) to read from registers of */ 6212 #define MC_CMD_MUM_IN_READ_DEVICE_OFST 4 6213 #define MC_CMD_MUM_IN_READ_DEVICE_LEN 4 6214 /* enum: Hittite HMC1035 clock generator on Sorrento board */ 6215 #define MC_CMD_MUM_DEV_HITTITE 0x1 6216 /* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */ 6217 #define MC_CMD_MUM_DEV_HITTITE_NIC 0x2 6218 /* 32-bit address to read from */ 6219 #define MC_CMD_MUM_IN_READ_ADDR_OFST 8 6220 #define MC_CMD_MUM_IN_READ_ADDR_LEN 4 6221 /* Number of words to read. */ 6222 #define MC_CMD_MUM_IN_READ_NUMWORDS_OFST 12 6223 #define MC_CMD_MUM_IN_READ_NUMWORDS_LEN 4 6224 6225 /* MC_CMD_MUM_IN_WRITE msgrequest */ 6226 #define MC_CMD_MUM_IN_WRITE_LENMIN 16 6227 #define MC_CMD_MUM_IN_WRITE_LENMAX 252 6228 #define MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num)) 6229 /* MUM cmd header */ 6230 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6231 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6232 /* ID of (device connected to MUM) to write to registers of */ 6233 #define MC_CMD_MUM_IN_WRITE_DEVICE_OFST 4 6234 #define MC_CMD_MUM_IN_WRITE_DEVICE_LEN 4 6235 /* enum: Hittite HMC1035 clock generator on Sorrento board */ 6236 /* MC_CMD_MUM_DEV_HITTITE 0x1 */ 6237 /* 32-bit address to write to */ 6238 #define MC_CMD_MUM_IN_WRITE_ADDR_OFST 8 6239 #define MC_CMD_MUM_IN_WRITE_ADDR_LEN 4 6240 /* Words to write */ 6241 #define MC_CMD_MUM_IN_WRITE_BUFFER_OFST 12 6242 #define MC_CMD_MUM_IN_WRITE_BUFFER_LEN 4 6243 #define MC_CMD_MUM_IN_WRITE_BUFFER_MINNUM 1 6244 #define MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM 60 6245 6246 /* MC_CMD_MUM_IN_RAW_CMD msgrequest */ 6247 #define MC_CMD_MUM_IN_RAW_CMD_LENMIN 17 6248 #define MC_CMD_MUM_IN_RAW_CMD_LENMAX 252 6249 #define MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num)) 6250 /* MUM cmd header */ 6251 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6252 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6253 /* MUM I2C cmd code */ 6254 #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 4 6255 #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_LEN 4 6256 /* Number of bytes to write */ 6257 #define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_OFST 8 6258 #define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_LEN 4 6259 /* Number of bytes to read */ 6260 #define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_OFST 12 6261 #define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_LEN 4 6262 /* Bytes to write */ 6263 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_OFST 16 6264 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 1 6265 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MINNUM 1 6266 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM 236 6267 6268 /* MC_CMD_MUM_IN_LOG msgrequest */ 6269 #define MC_CMD_MUM_IN_LOG_LEN 8 6270 /* MUM cmd header */ 6271 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6272 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6273 #define MC_CMD_MUM_IN_LOG_OP_OFST 4 6274 #define MC_CMD_MUM_IN_LOG_OP_LEN 4 6275 #define MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */ 6276 6277 /* MC_CMD_MUM_IN_LOG_OP_UART msgrequest */ 6278 #define MC_CMD_MUM_IN_LOG_OP_UART_LEN 12 6279 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6280 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6281 /* MC_CMD_MUM_IN_LOG_OP_OFST 4 */ 6282 /* MC_CMD_MUM_IN_LOG_OP_LEN 4 */ 6283 /* Enable/disable debug output to UART */ 6284 #define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_OFST 8 6285 #define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_LEN 4 6286 6287 /* MC_CMD_MUM_IN_GPIO msgrequest */ 6288 #define MC_CMD_MUM_IN_GPIO_LEN 8 6289 /* MUM cmd header */ 6290 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6291 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6292 #define MC_CMD_MUM_IN_GPIO_HDR_OFST 4 6293 #define MC_CMD_MUM_IN_GPIO_HDR_LEN 4 6294 #define MC_CMD_MUM_IN_GPIO_OPCODE_LBN 0 6295 #define MC_CMD_MUM_IN_GPIO_OPCODE_WIDTH 8 6296 #define MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */ 6297 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */ 6298 #define MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */ 6299 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */ 6300 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */ 6301 #define MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */ 6302 6303 /* MC_CMD_MUM_IN_GPIO_IN_READ msgrequest */ 6304 #define MC_CMD_MUM_IN_GPIO_IN_READ_LEN 8 6305 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6306 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6307 #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 4 6308 #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_LEN 4 6309 6310 /* MC_CMD_MUM_IN_GPIO_OUT_WRITE msgrequest */ 6311 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_LEN 16 6312 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6313 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6314 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4 6315 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_LEN 4 6316 /* The first 32-bit word to be written to the GPIO OUT register. */ 6317 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_OFST 8 6318 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_LEN 4 6319 /* The second 32-bit word to be written to the GPIO OUT register. */ 6320 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_OFST 12 6321 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_LEN 4 6322 6323 /* MC_CMD_MUM_IN_GPIO_OUT_READ msgrequest */ 6324 #define MC_CMD_MUM_IN_GPIO_OUT_READ_LEN 8 6325 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6326 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6327 #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 4 6328 #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_LEN 4 6329 6330 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE msgrequest */ 6331 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_LEN 16 6332 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6333 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6334 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4 6335 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_LEN 4 6336 /* The first 32-bit word to be written to the GPIO OUT ENABLE register. */ 6337 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_OFST 8 6338 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_LEN 4 6339 /* The second 32-bit word to be written to the GPIO OUT ENABLE register. */ 6340 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_OFST 12 6341 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_LEN 4 6342 6343 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ msgrequest */ 6344 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_LEN 8 6345 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6346 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6347 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 4 6348 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_LEN 4 6349 6350 /* MC_CMD_MUM_IN_GPIO_OP msgrequest */ 6351 #define MC_CMD_MUM_IN_GPIO_OP_LEN 8 6352 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6353 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6354 #define MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4 6355 #define MC_CMD_MUM_IN_GPIO_OP_HDR_LEN 4 6356 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_LBN 8 6357 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_WIDTH 8 6358 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */ 6359 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */ 6360 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */ 6361 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */ 6362 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_LBN 16 6363 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_WIDTH 8 6364 6365 /* MC_CMD_MUM_IN_GPIO_OP_OUT_READ msgrequest */ 6366 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_LEN 8 6367 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6368 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6369 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 4 6370 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_LEN 4 6371 6372 /* MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE msgrequest */ 6373 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_LEN 8 6374 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6375 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6376 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4 6377 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_LEN 4 6378 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_LBN 24 6379 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_WIDTH 8 6380 6381 /* MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG msgrequest */ 6382 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_LEN 8 6383 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6384 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6385 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4 6386 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_LEN 4 6387 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_LBN 24 6388 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_WIDTH 8 6389 6390 /* MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE msgrequest */ 6391 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_LEN 8 6392 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6393 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6394 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4 6395 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_LEN 4 6396 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_LBN 24 6397 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_WIDTH 8 6398 6399 /* MC_CMD_MUM_IN_READ_SENSORS msgrequest */ 6400 #define MC_CMD_MUM_IN_READ_SENSORS_LEN 8 6401 /* MUM cmd header */ 6402 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6403 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6404 #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4 6405 #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_LEN 4 6406 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0 6407 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_WIDTH 8 6408 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_LBN 8 6409 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_WIDTH 8 6410 6411 /* MC_CMD_MUM_IN_PROGRAM_CLOCKS msgrequest */ 6412 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_LEN 12 6413 /* MUM cmd header */ 6414 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6415 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6416 /* Bit-mask of clocks to be programmed */ 6417 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 4 6418 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_LEN 4 6419 #define MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */ 6420 #define MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */ 6421 #define MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */ 6422 /* Control flags for clock programming */ 6423 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 8 6424 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_LEN 4 6425 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0 6426 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1 6427 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_LBN 1 6428 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_WIDTH 1 6429 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_LBN 2 6430 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_WIDTH 1 6431 6432 /* MC_CMD_MUM_IN_FPGA_LOAD msgrequest */ 6433 #define MC_CMD_MUM_IN_FPGA_LOAD_LEN 8 6434 /* MUM cmd header */ 6435 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6436 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6437 /* Enable/Disable FPGA config from flash */ 6438 #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 4 6439 #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_LEN 4 6440 6441 /* MC_CMD_MUM_IN_READ_ATB_SENSOR msgrequest */ 6442 #define MC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 4 6443 /* MUM cmd header */ 6444 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6445 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6446 6447 /* MC_CMD_MUM_IN_QSFP msgrequest */ 6448 #define MC_CMD_MUM_IN_QSFP_LEN 12 6449 /* MUM cmd header */ 6450 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6451 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6452 #define MC_CMD_MUM_IN_QSFP_HDR_OFST 4 6453 #define MC_CMD_MUM_IN_QSFP_HDR_LEN 4 6454 #define MC_CMD_MUM_IN_QSFP_OPCODE_LBN 0 6455 #define MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4 6456 #define MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */ 6457 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */ 6458 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */ 6459 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */ 6460 #define MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */ 6461 #define MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */ 6462 #define MC_CMD_MUM_IN_QSFP_IDX_OFST 8 6463 #define MC_CMD_MUM_IN_QSFP_IDX_LEN 4 6464 6465 /* MC_CMD_MUM_IN_QSFP_INIT msgrequest */ 6466 #define MC_CMD_MUM_IN_QSFP_INIT_LEN 16 6467 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6468 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6469 #define MC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 4 6470 #define MC_CMD_MUM_IN_QSFP_INIT_HDR_LEN 4 6471 #define MC_CMD_MUM_IN_QSFP_INIT_IDX_OFST 8 6472 #define MC_CMD_MUM_IN_QSFP_INIT_IDX_LEN 4 6473 #define MC_CMD_MUM_IN_QSFP_INIT_CAGE_OFST 12 6474 #define MC_CMD_MUM_IN_QSFP_INIT_CAGE_LEN 4 6475 6476 /* MC_CMD_MUM_IN_QSFP_RECONFIGURE msgrequest */ 6477 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_LEN 24 6478 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6479 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6480 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 4 6481 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_LEN 4 6482 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_OFST 8 6483 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_LEN 4 6484 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_OFST 12 6485 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_LEN 4 6486 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_OFST 16 6487 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_LEN 4 6488 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_OFST 20 6489 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_LEN 4 6490 6491 /* MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP msgrequest */ 6492 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_LEN 12 6493 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6494 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6495 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 4 6496 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_LEN 4 6497 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_OFST 8 6498 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_LEN 4 6499 6500 /* MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO msgrequest */ 6501 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_LEN 16 6502 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6503 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6504 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 4 6505 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_LEN 4 6506 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_OFST 8 6507 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_LEN 4 6508 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_OFST 12 6509 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_LEN 4 6510 6511 /* MC_CMD_MUM_IN_QSFP_FILL_STATS msgrequest */ 6512 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_LEN 12 6513 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6514 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6515 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 4 6516 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_LEN 4 6517 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_OFST 8 6518 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_LEN 4 6519 6520 /* MC_CMD_MUM_IN_QSFP_POLL_BIST msgrequest */ 6521 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_LEN 12 6522 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6523 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6524 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4 6525 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_LEN 4 6526 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_OFST 8 6527 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_LEN 4 6528 6529 /* MC_CMD_MUM_IN_READ_DDR_INFO msgrequest */ 6530 #define MC_CMD_MUM_IN_READ_DDR_INFO_LEN 4 6531 /* MUM cmd header */ 6532 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6533 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6534 6535 /* MC_CMD_MUM_OUT msgresponse */ 6536 #define MC_CMD_MUM_OUT_LEN 0 6537 6538 /* MC_CMD_MUM_OUT_NULL msgresponse */ 6539 #define MC_CMD_MUM_OUT_NULL_LEN 0 6540 6541 /* MC_CMD_MUM_OUT_GET_VERSION msgresponse */ 6542 #define MC_CMD_MUM_OUT_GET_VERSION_LEN 12 6543 #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 0 6544 #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_LEN 4 6545 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4 6546 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 8 6547 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4 6548 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 8 6549 6550 /* MC_CMD_MUM_OUT_RAW_CMD msgresponse */ 6551 #define MC_CMD_MUM_OUT_RAW_CMD_LENMIN 1 6552 #define MC_CMD_MUM_OUT_RAW_CMD_LENMAX 252 6553 #define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num)) 6554 /* returned data */ 6555 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0 6556 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 1 6557 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MINNUM 1 6558 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM 252 6559 6560 /* MC_CMD_MUM_OUT_READ msgresponse */ 6561 #define MC_CMD_MUM_OUT_READ_LENMIN 4 6562 #define MC_CMD_MUM_OUT_READ_LENMAX 252 6563 #define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num)) 6564 #define MC_CMD_MUM_OUT_READ_BUFFER_OFST 0 6565 #define MC_CMD_MUM_OUT_READ_BUFFER_LEN 4 6566 #define MC_CMD_MUM_OUT_READ_BUFFER_MINNUM 1 6567 #define MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM 63 6568 6569 /* MC_CMD_MUM_OUT_WRITE msgresponse */ 6570 #define MC_CMD_MUM_OUT_WRITE_LEN 0 6571 6572 /* MC_CMD_MUM_OUT_LOG msgresponse */ 6573 #define MC_CMD_MUM_OUT_LOG_LEN 0 6574 6575 /* MC_CMD_MUM_OUT_LOG_OP_UART msgresponse */ 6576 #define MC_CMD_MUM_OUT_LOG_OP_UART_LEN 0 6577 6578 /* MC_CMD_MUM_OUT_GPIO_IN_READ msgresponse */ 6579 #define MC_CMD_MUM_OUT_GPIO_IN_READ_LEN 8 6580 /* The first 32-bit word read from the GPIO IN register. */ 6581 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0 6582 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_LEN 4 6583 /* The second 32-bit word read from the GPIO IN register. */ 6584 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4 6585 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_LEN 4 6586 6587 /* MC_CMD_MUM_OUT_GPIO_OUT_WRITE msgresponse */ 6588 #define MC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 0 6589 6590 /* MC_CMD_MUM_OUT_GPIO_OUT_READ msgresponse */ 6591 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_LEN 8 6592 /* The first 32-bit word read from the GPIO OUT register. */ 6593 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0 6594 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_LEN 4 6595 /* The second 32-bit word read from the GPIO OUT register. */ 6596 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4 6597 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_LEN 4 6598 6599 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE msgresponse */ 6600 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 0 6601 6602 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ msgresponse */ 6603 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_LEN 8 6604 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 0 6605 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_LEN 4 6606 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 4 6607 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_LEN 4 6608 6609 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_READ msgresponse */ 6610 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 4 6611 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 0 6612 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_LEN 4 6613 6614 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE msgresponse */ 6615 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 0 6616 6617 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG msgresponse */ 6618 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 0 6619 6620 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE msgresponse */ 6621 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 0 6622 6623 /* MC_CMD_MUM_OUT_READ_SENSORS msgresponse */ 6624 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 4 6625 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX 252 6626 #define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num)) 6627 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0 6628 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4 6629 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 1 6630 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM 63 6631 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0 6632 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_WIDTH 16 6633 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_LBN 16 6634 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_WIDTH 8 6635 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_LBN 24 6636 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_WIDTH 8 6637 6638 /* MC_CMD_MUM_OUT_PROGRAM_CLOCKS msgresponse */ 6639 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 4 6640 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 0 6641 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_LEN 4 6642 6643 /* MC_CMD_MUM_OUT_FPGA_LOAD msgresponse */ 6644 #define MC_CMD_MUM_OUT_FPGA_LOAD_LEN 0 6645 6646 /* MC_CMD_MUM_OUT_READ_ATB_SENSOR msgresponse */ 6647 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 4 6648 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 0 6649 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_LEN 4 6650 6651 /* MC_CMD_MUM_OUT_QSFP_INIT msgresponse */ 6652 #define MC_CMD_MUM_OUT_QSFP_INIT_LEN 0 6653 6654 /* MC_CMD_MUM_OUT_QSFP_RECONFIGURE msgresponse */ 6655 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_LEN 8 6656 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 0 6657 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_LEN 4 6658 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4 6659 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_LEN 4 6660 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0 6661 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 1 6662 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 1 6663 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 1 6664 6665 /* MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP msgresponse */ 6666 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 4 6667 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 0 6668 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_LEN 4 6669 6670 /* MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO msgresponse */ 6671 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMIN 5 6672 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX 252 6673 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num)) 6674 /* in bytes */ 6675 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0 6676 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_LEN 4 6677 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 4 6678 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 1 6679 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 1 6680 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM 248 6681 6682 /* MC_CMD_MUM_OUT_QSFP_FILL_STATS msgresponse */ 6683 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_LEN 8 6684 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 0 6685 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_LEN 4 6686 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 4 6687 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_LEN 4 6688 6689 /* MC_CMD_MUM_OUT_QSFP_POLL_BIST msgresponse */ 6690 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4 6691 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0 6692 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_LEN 4 6693 6694 /* MC_CMD_MUM_OUT_READ_DDR_INFO msgresponse */ 6695 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMIN 24 6696 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX 248 6697 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LEN(num) (8+8*(num)) 6698 /* Discrete (soldered) DDR resistor strap info */ 6699 #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0 6700 #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_LEN 4 6701 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0 6702 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_WIDTH 16 6703 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_LBN 16 6704 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_WIDTH 16 6705 /* Number of SODIMM info records */ 6706 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 4 6707 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_LEN 4 6708 /* Array of SODIMM info records */ 6709 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 8 6710 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 8 6711 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_OFST 8 6712 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 12 6713 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 2 6714 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 30 6715 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 0 6716 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_WIDTH 8 6717 /* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */ 6718 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK1 0x0 6719 /* enum: SODIMM bank 2 (Bottom SODDIMM for Sorrento) */ 6720 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x1 6721 /* enum: Total number of SODIMM banks */ 6722 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x2 6723 #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_LBN 8 6724 #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_WIDTH 8 6725 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_LBN 16 6726 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 4 6727 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_LBN 20 6728 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 4 6729 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */ 6730 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */ 6731 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */ 6732 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */ 6733 /* enum: Values 5-15 are reserved for future usage */ 6734 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x4 6735 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_LBN 24 6736 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_WIDTH 8 6737 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_LBN 32 6738 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_WIDTH 16 6739 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_LBN 48 6740 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 4 6741 /* enum: No module present */ 6742 #define MC_CMD_MUM_OUT_READ_DDR_INFO_ABSENT 0x0 6743 /* enum: Module present supported and powered on */ 6744 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_POWERED 0x1 6745 /* enum: Module present but bad type */ 6746 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_TYPE 0x2 6747 /* enum: Module present but incompatible voltage */ 6748 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_VOLTAGE 0x3 6749 /* enum: Module present but unknown SPD */ 6750 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SPD 0x4 6751 /* enum: Module present but slot cannot support it */ 6752 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SLOT 0x5 6753 /* enum: Modules may or may not be present, but cannot establish contact by I2C 6754 */ 6755 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x6 6756 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_LBN 52 6757 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_WIDTH 12 6758 6759 /* MC_CMD_RESOURCE_SPECIFIER enum */ 6760 /* enum: Any */ 6761 #define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff 6762 /* enum: None */ 6763 #define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe 6764 6765 /* EVB_PORT_ID structuredef */ 6766 #define EVB_PORT_ID_LEN 4 6767 #define EVB_PORT_ID_PORT_ID_OFST 0 6768 #define EVB_PORT_ID_PORT_ID_LEN 4 6769 /* enum: An invalid port handle. */ 6770 #define EVB_PORT_ID_NULL 0x0 6771 /* enum: The port assigned to this function.. */ 6772 #define EVB_PORT_ID_ASSIGNED 0x1000000 6773 /* enum: External network port 0 */ 6774 #define EVB_PORT_ID_MAC0 0x2000000 6775 /* enum: External network port 1 */ 6776 #define EVB_PORT_ID_MAC1 0x2000001 6777 /* enum: External network port 2 */ 6778 #define EVB_PORT_ID_MAC2 0x2000002 6779 /* enum: External network port 3 */ 6780 #define EVB_PORT_ID_MAC3 0x2000003 6781 #define EVB_PORT_ID_PORT_ID_LBN 0 6782 #define EVB_PORT_ID_PORT_ID_WIDTH 32 6783 6784 /* EVB_VLAN_TAG structuredef */ 6785 #define EVB_VLAN_TAG_LEN 2 6786 /* The VLAN tag value */ 6787 #define EVB_VLAN_TAG_VLAN_ID_LBN 0 6788 #define EVB_VLAN_TAG_VLAN_ID_WIDTH 12 6789 #define EVB_VLAN_TAG_MODE_LBN 12 6790 #define EVB_VLAN_TAG_MODE_WIDTH 4 6791 /* enum: Insert the VLAN. */ 6792 #define EVB_VLAN_TAG_INSERT 0x0 6793 /* enum: Replace the VLAN if already present. */ 6794 #define EVB_VLAN_TAG_REPLACE 0x1 6795 6796 /* BUFTBL_ENTRY structuredef */ 6797 #define BUFTBL_ENTRY_LEN 12 6798 /* the owner ID */ 6799 #define BUFTBL_ENTRY_OID_OFST 0 6800 #define BUFTBL_ENTRY_OID_LEN 2 6801 #define BUFTBL_ENTRY_OID_LBN 0 6802 #define BUFTBL_ENTRY_OID_WIDTH 16 6803 /* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */ 6804 #define BUFTBL_ENTRY_PGSZ_OFST 2 6805 #define BUFTBL_ENTRY_PGSZ_LEN 2 6806 #define BUFTBL_ENTRY_PGSZ_LBN 16 6807 #define BUFTBL_ENTRY_PGSZ_WIDTH 16 6808 /* the raw 64-bit address field from the SMC, not adjusted for page size */ 6809 #define BUFTBL_ENTRY_RAWADDR_OFST 4 6810 #define BUFTBL_ENTRY_RAWADDR_LEN 8 6811 #define BUFTBL_ENTRY_RAWADDR_LO_OFST 4 6812 #define BUFTBL_ENTRY_RAWADDR_HI_OFST 8 6813 #define BUFTBL_ENTRY_RAWADDR_LBN 32 6814 #define BUFTBL_ENTRY_RAWADDR_WIDTH 64 6815 6816 /* NVRAM_PARTITION_TYPE structuredef */ 6817 #define NVRAM_PARTITION_TYPE_LEN 2 6818 #define NVRAM_PARTITION_TYPE_ID_OFST 0 6819 #define NVRAM_PARTITION_TYPE_ID_LEN 2 6820 /* enum: Primary MC firmware partition */ 6821 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100 6822 /* enum: Secondary MC firmware partition */ 6823 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200 6824 /* enum: Expansion ROM partition */ 6825 #define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300 6826 /* enum: Static configuration TLV partition */ 6827 #define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400 6828 /* enum: Dynamic configuration TLV partition */ 6829 #define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500 6830 /* enum: Expansion ROM configuration data for port 0 */ 6831 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600 6832 /* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */ 6833 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x600 6834 /* enum: Expansion ROM configuration data for port 1 */ 6835 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601 6836 /* enum: Expansion ROM configuration data for port 2 */ 6837 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602 6838 /* enum: Expansion ROM configuration data for port 3 */ 6839 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603 6840 /* enum: Non-volatile log output partition */ 6841 #define NVRAM_PARTITION_TYPE_LOG 0x700 6842 /* enum: Non-volatile log output of second core on dual-core device */ 6843 #define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701 6844 /* enum: Device state dump output partition */ 6845 #define NVRAM_PARTITION_TYPE_DUMP 0x800 6846 /* enum: Application license key storage partition */ 6847 #define NVRAM_PARTITION_TYPE_LICENSE 0x900 6848 /* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */ 6849 #define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00 6850 /* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */ 6851 #define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff 6852 /* enum: Primary FPGA partition */ 6853 #define NVRAM_PARTITION_TYPE_FPGA 0xb00 6854 /* enum: Secondary FPGA partition */ 6855 #define NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01 6856 /* enum: FC firmware partition */ 6857 #define NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02 6858 /* enum: FC License partition */ 6859 #define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03 6860 /* enum: Non-volatile log output partition for FC */ 6861 #define NVRAM_PARTITION_TYPE_FC_LOG 0xb04 6862 /* enum: MUM firmware partition */ 6863 #define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00 6864 /* enum: SUC firmware partition (this is intentionally an alias of 6865 * MUM_FIRMWARE) 6866 */ 6867 #define NVRAM_PARTITION_TYPE_SUC_FIRMWARE 0xc00 6868 /* enum: MUM Non-volatile log output partition. */ 6869 #define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01 6870 /* enum: MUM Application table partition. */ 6871 #define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02 6872 /* enum: MUM boot rom partition. */ 6873 #define NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03 6874 /* enum: MUM production signatures & calibration rom partition. */ 6875 #define NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04 6876 /* enum: MUM user signatures & calibration rom partition. */ 6877 #define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05 6878 /* enum: MUM fuses and lockbits partition. */ 6879 #define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06 6880 /* enum: UEFI expansion ROM if separate from PXE */ 6881 #define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00 6882 /* enum: Used by the expansion ROM for logging */ 6883 #define NVRAM_PARTITION_TYPE_PXE_LOG 0x1000 6884 /* enum: Used for XIP code of shmbooted images */ 6885 #define NVRAM_PARTITION_TYPE_XIP_SCRATCH 0x1100 6886 /* enum: Spare partition 2 */ 6887 #define NVRAM_PARTITION_TYPE_SPARE_2 0x1200 6888 /* enum: Manufacturing partition. Used during manufacture to pass information 6889 * between XJTAG and Manftest. 6890 */ 6891 #define NVRAM_PARTITION_TYPE_MANUFACTURING 0x1300 6892 /* enum: Spare partition 4 */ 6893 #define NVRAM_PARTITION_TYPE_SPARE_4 0x1400 6894 /* enum: Spare partition 5 */ 6895 #define NVRAM_PARTITION_TYPE_SPARE_5 0x1500 6896 /* enum: Partition for reporting MC status. See mc_flash_layout.h 6897 * medford_mc_status_hdr_t for layout on Medford. 6898 */ 6899 #define NVRAM_PARTITION_TYPE_STATUS 0x1600 6900 /* enum: Spare partition 13 */ 6901 #define NVRAM_PARTITION_TYPE_SPARE_13 0x1700 6902 /* enum: Spare partition 14 */ 6903 #define NVRAM_PARTITION_TYPE_SPARE_14 0x1800 6904 /* enum: Spare partition 15 */ 6905 #define NVRAM_PARTITION_TYPE_SPARE_15 0x1900 6906 /* enum: Spare partition 16 */ 6907 #define NVRAM_PARTITION_TYPE_SPARE_16 0x1a00 6908 /* enum: Factory defaults for dynamic configuration */ 6909 #define NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS 0x1b00 6910 /* enum: Factory defaults for expansion ROM configuration */ 6911 #define NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS 0x1c00 6912 /* enum: Field Replaceable Unit inventory information for use on IPMI 6913 * platforms. See SF-119124-PS. The STATIC_CONFIG partition may contain a 6914 * subset of the information stored in this partition. 6915 */ 6916 #define NVRAM_PARTITION_TYPE_FRU_INFORMATION 0x1d00 6917 /* enum: Start of reserved value range (firmware may use for any purpose) */ 6918 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00 6919 /* enum: End of reserved value range (firmware may use for any purpose) */ 6920 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd 6921 /* enum: Recovery partition map (provided if real map is missing or corrupt) */ 6922 #define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe 6923 /* enum: Partition map (real map as stored in flash) */ 6924 #define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff 6925 #define NVRAM_PARTITION_TYPE_ID_LBN 0 6926 #define NVRAM_PARTITION_TYPE_ID_WIDTH 16 6927 6928 /* LICENSED_APP_ID structuredef */ 6929 #define LICENSED_APP_ID_LEN 4 6930 #define LICENSED_APP_ID_ID_OFST 0 6931 #define LICENSED_APP_ID_ID_LEN 4 6932 /* enum: OpenOnload */ 6933 #define LICENSED_APP_ID_ONLOAD 0x1 6934 /* enum: PTP timestamping */ 6935 #define LICENSED_APP_ID_PTP 0x2 6936 /* enum: SolarCapture Pro */ 6937 #define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4 6938 /* enum: SolarSecure filter engine */ 6939 #define LICENSED_APP_ID_SOLARSECURE 0x8 6940 /* enum: Performance monitor */ 6941 #define LICENSED_APP_ID_PERF_MONITOR 0x10 6942 /* enum: SolarCapture Live */ 6943 #define LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20 6944 /* enum: Capture SolarSystem */ 6945 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40 6946 /* enum: Network Access Control */ 6947 #define LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80 6948 /* enum: TCP Direct */ 6949 #define LICENSED_APP_ID_TCP_DIRECT 0x100 6950 /* enum: Low Latency */ 6951 #define LICENSED_APP_ID_LOW_LATENCY 0x200 6952 /* enum: SolarCapture Tap */ 6953 #define LICENSED_APP_ID_SOLARCAPTURE_TAP 0x400 6954 /* enum: Capture SolarSystem 40G */ 6955 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_40G 0x800 6956 /* enum: Capture SolarSystem 1G */ 6957 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_1G 0x1000 6958 /* enum: ScaleOut Onload */ 6959 #define LICENSED_APP_ID_SCALEOUT_ONLOAD 0x2000 6960 /* enum: SCS Network Analytics Dashboard */ 6961 #define LICENSED_APP_ID_DSHBRD 0x4000 6962 /* enum: SolarCapture Trading Analytics */ 6963 #define LICENSED_APP_ID_SCATRD 0x8000 6964 #define LICENSED_APP_ID_ID_LBN 0 6965 #define LICENSED_APP_ID_ID_WIDTH 32 6966 6967 /* LICENSED_FEATURES structuredef */ 6968 #define LICENSED_FEATURES_LEN 8 6969 /* Bitmask of licensed firmware features */ 6970 #define LICENSED_FEATURES_MASK_OFST 0 6971 #define LICENSED_FEATURES_MASK_LEN 8 6972 #define LICENSED_FEATURES_MASK_LO_OFST 0 6973 #define LICENSED_FEATURES_MASK_HI_OFST 4 6974 #define LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0 6975 #define LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1 6976 #define LICENSED_FEATURES_PIO_LBN 1 6977 #define LICENSED_FEATURES_PIO_WIDTH 1 6978 #define LICENSED_FEATURES_EVQ_TIMER_LBN 2 6979 #define LICENSED_FEATURES_EVQ_TIMER_WIDTH 1 6980 #define LICENSED_FEATURES_CLOCK_LBN 3 6981 #define LICENSED_FEATURES_CLOCK_WIDTH 1 6982 #define LICENSED_FEATURES_RX_TIMESTAMPS_LBN 4 6983 #define LICENSED_FEATURES_RX_TIMESTAMPS_WIDTH 1 6984 #define LICENSED_FEATURES_TX_TIMESTAMPS_LBN 5 6985 #define LICENSED_FEATURES_TX_TIMESTAMPS_WIDTH 1 6986 #define LICENSED_FEATURES_RX_SNIFF_LBN 6 6987 #define LICENSED_FEATURES_RX_SNIFF_WIDTH 1 6988 #define LICENSED_FEATURES_TX_SNIFF_LBN 7 6989 #define LICENSED_FEATURES_TX_SNIFF_WIDTH 1 6990 #define LICENSED_FEATURES_PROXY_FILTER_OPS_LBN 8 6991 #define LICENSED_FEATURES_PROXY_FILTER_OPS_WIDTH 1 6992 #define LICENSED_FEATURES_EVENT_CUT_THROUGH_LBN 9 6993 #define LICENSED_FEATURES_EVENT_CUT_THROUGH_WIDTH 1 6994 #define LICENSED_FEATURES_MASK_LBN 0 6995 #define LICENSED_FEATURES_MASK_WIDTH 64 6996 6997 /* LICENSED_V3_APPS structuredef */ 6998 #define LICENSED_V3_APPS_LEN 8 6999 /* Bitmask of licensed applications */ 7000 #define LICENSED_V3_APPS_MASK_OFST 0 7001 #define LICENSED_V3_APPS_MASK_LEN 8 7002 #define LICENSED_V3_APPS_MASK_LO_OFST 0 7003 #define LICENSED_V3_APPS_MASK_HI_OFST 4 7004 #define LICENSED_V3_APPS_ONLOAD_LBN 0 7005 #define LICENSED_V3_APPS_ONLOAD_WIDTH 1 7006 #define LICENSED_V3_APPS_PTP_LBN 1 7007 #define LICENSED_V3_APPS_PTP_WIDTH 1 7008 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_LBN 2 7009 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_WIDTH 1 7010 #define LICENSED_V3_APPS_SOLARSECURE_LBN 3 7011 #define LICENSED_V3_APPS_SOLARSECURE_WIDTH 1 7012 #define LICENSED_V3_APPS_PERF_MONITOR_LBN 4 7013 #define LICENSED_V3_APPS_PERF_MONITOR_WIDTH 1 7014 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_LBN 5 7015 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_WIDTH 1 7016 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_LBN 6 7017 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_WIDTH 1 7018 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_LBN 7 7019 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_WIDTH 1 7020 #define LICENSED_V3_APPS_TCP_DIRECT_LBN 8 7021 #define LICENSED_V3_APPS_TCP_DIRECT_WIDTH 1 7022 #define LICENSED_V3_APPS_LOW_LATENCY_LBN 9 7023 #define LICENSED_V3_APPS_LOW_LATENCY_WIDTH 1 7024 #define LICENSED_V3_APPS_SOLARCAPTURE_TAP_LBN 10 7025 #define LICENSED_V3_APPS_SOLARCAPTURE_TAP_WIDTH 1 7026 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_LBN 11 7027 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_WIDTH 1 7028 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_LBN 12 7029 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_WIDTH 1 7030 #define LICENSED_V3_APPS_SCALEOUT_ONLOAD_LBN 13 7031 #define LICENSED_V3_APPS_SCALEOUT_ONLOAD_WIDTH 1 7032 #define LICENSED_V3_APPS_DSHBRD_LBN 14 7033 #define LICENSED_V3_APPS_DSHBRD_WIDTH 1 7034 #define LICENSED_V3_APPS_SCATRD_LBN 15 7035 #define LICENSED_V3_APPS_SCATRD_WIDTH 1 7036 #define LICENSED_V3_APPS_MASK_LBN 0 7037 #define LICENSED_V3_APPS_MASK_WIDTH 64 7038 7039 /* LICENSED_V3_FEATURES structuredef */ 7040 #define LICENSED_V3_FEATURES_LEN 8 7041 /* Bitmask of licensed firmware features */ 7042 #define LICENSED_V3_FEATURES_MASK_OFST 0 7043 #define LICENSED_V3_FEATURES_MASK_LEN 8 7044 #define LICENSED_V3_FEATURES_MASK_LO_OFST 0 7045 #define LICENSED_V3_FEATURES_MASK_HI_OFST 4 7046 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0 7047 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1 7048 #define LICENSED_V3_FEATURES_PIO_LBN 1 7049 #define LICENSED_V3_FEATURES_PIO_WIDTH 1 7050 #define LICENSED_V3_FEATURES_EVQ_TIMER_LBN 2 7051 #define LICENSED_V3_FEATURES_EVQ_TIMER_WIDTH 1 7052 #define LICENSED_V3_FEATURES_CLOCK_LBN 3 7053 #define LICENSED_V3_FEATURES_CLOCK_WIDTH 1 7054 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4 7055 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_WIDTH 1 7056 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN 5 7057 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_WIDTH 1 7058 #define LICENSED_V3_FEATURES_RX_SNIFF_LBN 6 7059 #define LICENSED_V3_FEATURES_RX_SNIFF_WIDTH 1 7060 #define LICENSED_V3_FEATURES_TX_SNIFF_LBN 7 7061 #define LICENSED_V3_FEATURES_TX_SNIFF_WIDTH 1 7062 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_LBN 8 7063 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_WIDTH 1 7064 #define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_LBN 9 7065 #define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_WIDTH 1 7066 #define LICENSED_V3_FEATURES_MASK_LBN 0 7067 #define LICENSED_V3_FEATURES_MASK_WIDTH 64 7068 7069 /* TX_TIMESTAMP_EVENT structuredef */ 7070 #define TX_TIMESTAMP_EVENT_LEN 6 7071 /* lower 16 bits of timestamp data */ 7072 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0 7073 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LEN 2 7074 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0 7075 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_WIDTH 16 7076 /* Type of TX event, ordinary TX completion, low or high part of TX timestamp 7077 */ 7078 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_OFST 3 7079 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 1 7080 /* enum: This is a TX completion event, not a timestamp */ 7081 #define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0 7082 /* enum: This is a TX completion event for a CTPIO transmit. The event format 7083 * is the same as for TX_EV_COMPLETION. 7084 */ 7085 #define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_COMPLETION 0x11 7086 /* enum: This is the low part of a TX timestamp for a CTPIO transmission. The 7087 * event format is the same as for TX_EV_TSTAMP_LO 7088 */ 7089 #define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_LO 0x12 7090 /* enum: This is the high part of a TX timestamp for a CTPIO transmission. The 7091 * event format is the same as for TX_EV_TSTAMP_HI 7092 */ 7093 #define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_HI 0x13 7094 /* enum: This is the low part of a TX timestamp event */ 7095 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51 7096 /* enum: This is the high part of a TX timestamp event */ 7097 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52 7098 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LBN 24 7099 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_WIDTH 8 7100 /* upper 16 bits of timestamp data */ 7101 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4 7102 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LEN 2 7103 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LBN 32 7104 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_WIDTH 16 7105 7106 /* RSS_MODE structuredef */ 7107 #define RSS_MODE_LEN 1 7108 /* The RSS mode for a particular packet type is a value from 0 - 15 which can 7109 * be considered as 4 bits selecting which fields are included in the hash. (A 7110 * value 0 effectively disables RSS spreading for the packet type.) The YAML 7111 * generation tools require this structure to be a whole number of bytes wide, 7112 * but only 4 bits are relevant. 7113 */ 7114 #define RSS_MODE_HASH_SELECTOR_OFST 0 7115 #define RSS_MODE_HASH_SELECTOR_LEN 1 7116 #define RSS_MODE_HASH_SRC_ADDR_LBN 0 7117 #define RSS_MODE_HASH_SRC_ADDR_WIDTH 1 7118 #define RSS_MODE_HASH_DST_ADDR_LBN 1 7119 #define RSS_MODE_HASH_DST_ADDR_WIDTH 1 7120 #define RSS_MODE_HASH_SRC_PORT_LBN 2 7121 #define RSS_MODE_HASH_SRC_PORT_WIDTH 1 7122 #define RSS_MODE_HASH_DST_PORT_LBN 3 7123 #define RSS_MODE_HASH_DST_PORT_WIDTH 1 7124 #define RSS_MODE_HASH_SELECTOR_LBN 0 7125 #define RSS_MODE_HASH_SELECTOR_WIDTH 8 7126 7127 /* CTPIO_STATS_MAP structuredef */ 7128 #define CTPIO_STATS_MAP_LEN 4 7129 /* The (function relative) VI number */ 7130 #define CTPIO_STATS_MAP_VI_OFST 0 7131 #define CTPIO_STATS_MAP_VI_LEN 2 7132 #define CTPIO_STATS_MAP_VI_LBN 0 7133 #define CTPIO_STATS_MAP_VI_WIDTH 16 7134 /* The target bucket for the VI */ 7135 #define CTPIO_STATS_MAP_BUCKET_OFST 2 7136 #define CTPIO_STATS_MAP_BUCKET_LEN 2 7137 #define CTPIO_STATS_MAP_BUCKET_LBN 16 7138 #define CTPIO_STATS_MAP_BUCKET_WIDTH 16 7139 7140 /* MESSAGE_TYPE structuredef: When present this defines the meaning of a 7141 * message, and is used to protect against chosen message attacks in signed 7142 * messages, regardless their origin. The message type also defines the 7143 * signature cryptographic algorithm, encoding, and message fields included in 7144 * the signature. The values are used in different commands but must be unique 7145 * across all commands, e.g. MC_CMD_TSA_BIND_IN_SECURE_UNBIND uses different 7146 * message type than MC_CMD_SECURE_NIC_INFO_IN_STATUS. 7147 */ 7148 #define MESSAGE_TYPE_LEN 4 7149 #define MESSAGE_TYPE_MESSAGE_TYPE_OFST 0 7150 #define MESSAGE_TYPE_MESSAGE_TYPE_LEN 4 7151 #define MESSAGE_TYPE_UNUSED 0x0 /* enum */ 7152 /* enum: Message type value for the response to a 7153 * MC_CMD_TSA_BIND_IN_SECURE_UNBIND message. TSA_SECURE_UNBIND messages are 7154 * ECDSA SECP384R1 signed using SHA384 message digest algorithm over fields 7155 * MESSAGE_TYPE, TSANID, TSAID, and UNBINDTOKEN, and encoded as suggested by 7156 * RFC6979 (section 2.4). 7157 */ 7158 #define MESSAGE_TYPE_TSA_SECURE_UNBIND 0x1 7159 /* enum: Message type value for the response to a 7160 * MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION message. TSA_SECURE_DECOMMISSION 7161 * messages are ECDSA SECP384R1 signed using SHA384 message digest algorithm 7162 * over fields MESSAGE_TYPE, TSAID, USER, and REASON, and encoded as suggested 7163 * by RFC6979 (section 2.4). 7164 */ 7165 #define MESSAGE_TYPE_TSA_SECURE_DECOMMISSION 0x2 7166 /* enum: Message type value for the response to a 7167 * MC_CMD_SECURE_NIC_INFO_IN_STATUS message. This enum value is not sequential 7168 * to other message types for backwards compatibility as the message type for 7169 * MC_CMD_SECURE_NIC_INFO_IN_STATUS was defined before the existence of this 7170 * global enum. 7171 */ 7172 #define MESSAGE_TYPE_SECURE_NIC_INFO_STATUS 0xdb4 7173 #define MESSAGE_TYPE_MESSAGE_TYPE_LBN 0 7174 #define MESSAGE_TYPE_MESSAGE_TYPE_WIDTH 32 7175 7176 7177 /***********************************/ 7178 /* MC_CMD_READ_REGS 7179 * Get a dump of the MCPU registers 7180 */ 7181 #define MC_CMD_READ_REGS 0x50 7182 #undef MC_CMD_0x50_PRIVILEGE_CTG 7183 7184 #define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_INSECURE 7185 7186 /* MC_CMD_READ_REGS_IN msgrequest */ 7187 #define MC_CMD_READ_REGS_IN_LEN 0 7188 7189 /* MC_CMD_READ_REGS_OUT msgresponse */ 7190 #define MC_CMD_READ_REGS_OUT_LEN 308 7191 /* Whether the corresponding register entry contains a valid value */ 7192 #define MC_CMD_READ_REGS_OUT_MASK_OFST 0 7193 #define MC_CMD_READ_REGS_OUT_MASK_LEN 16 7194 /* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr, 7195 * fir, fp) 7196 */ 7197 #define MC_CMD_READ_REGS_OUT_REGS_OFST 16 7198 #define MC_CMD_READ_REGS_OUT_REGS_LEN 4 7199 #define MC_CMD_READ_REGS_OUT_REGS_NUM 73 7200 7201 7202 /***********************************/ 7203 /* MC_CMD_INIT_EVQ 7204 * Set up an event queue according to the supplied parameters. The IN arguments 7205 * end with an address for each 4k of host memory required to back the EVQ. 7206 */ 7207 #define MC_CMD_INIT_EVQ 0x80 7208 #undef MC_CMD_0x80_PRIVILEGE_CTG 7209 7210 #define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7211 7212 /* MC_CMD_INIT_EVQ_IN msgrequest */ 7213 #define MC_CMD_INIT_EVQ_IN_LENMIN 44 7214 #define MC_CMD_INIT_EVQ_IN_LENMAX 548 7215 #define MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num)) 7216 /* Size, in entries */ 7217 #define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0 7218 #define MC_CMD_INIT_EVQ_IN_SIZE_LEN 4 7219 /* Desired instance. Must be set to a specific instance, which is a function 7220 * local queue index. 7221 */ 7222 #define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4 7223 #define MC_CMD_INIT_EVQ_IN_INSTANCE_LEN 4 7224 /* The initial timer value. The load value is ignored if the timer mode is DIS. 7225 */ 7226 #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8 7227 #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_LEN 4 7228 /* The reload value is ignored in one-shot modes */ 7229 #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12 7230 #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_LEN 4 7231 /* tbd */ 7232 #define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16 7233 #define MC_CMD_INIT_EVQ_IN_FLAGS_LEN 4 7234 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0 7235 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1 7236 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1 7237 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1 7238 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2 7239 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1 7240 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3 7241 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1 7242 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4 7243 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1 7244 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5 7245 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1 7246 #define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_LBN 6 7247 #define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_WIDTH 1 7248 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20 7249 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_LEN 4 7250 /* enum: Disabled */ 7251 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0 7252 /* enum: Immediate */ 7253 #define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1 7254 /* enum: Triggered */ 7255 #define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2 7256 /* enum: Hold-off */ 7257 #define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3 7258 /* Target EVQ for wakeups if in wakeup mode. */ 7259 #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24 7260 #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_LEN 4 7261 /* Target interrupt if in interrupting mode (note union with target EVQ). Use 7262 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test 7263 * purposes. 7264 */ 7265 #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24 7266 #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_LEN 4 7267 /* Event Counter Mode. */ 7268 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28 7269 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_LEN 4 7270 /* enum: Disabled */ 7271 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0 7272 /* enum: Disabled */ 7273 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1 7274 /* enum: Disabled */ 7275 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2 7276 /* enum: Disabled */ 7277 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3 7278 /* Event queue packet count threshold. */ 7279 #define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32 7280 #define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_LEN 4 7281 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 7282 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36 7283 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8 7284 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36 7285 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40 7286 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1 7287 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64 7288 7289 /* MC_CMD_INIT_EVQ_OUT msgresponse */ 7290 #define MC_CMD_INIT_EVQ_OUT_LEN 4 7291 /* Only valid if INTRFLAG was true */ 7292 #define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0 7293 #define MC_CMD_INIT_EVQ_OUT_IRQ_LEN 4 7294 7295 /* MC_CMD_INIT_EVQ_V2_IN msgrequest */ 7296 #define MC_CMD_INIT_EVQ_V2_IN_LENMIN 44 7297 #define MC_CMD_INIT_EVQ_V2_IN_LENMAX 548 7298 #define MC_CMD_INIT_EVQ_V2_IN_LEN(num) (36+8*(num)) 7299 /* Size, in entries */ 7300 #define MC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0 7301 #define MC_CMD_INIT_EVQ_V2_IN_SIZE_LEN 4 7302 /* Desired instance. Must be set to a specific instance, which is a function 7303 * local queue index. 7304 */ 7305 #define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 4 7306 #define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_LEN 4 7307 /* The initial timer value. The load value is ignored if the timer mode is DIS. 7308 */ 7309 #define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_OFST 8 7310 #define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_LEN 4 7311 /* The reload value is ignored in one-shot modes */ 7312 #define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_OFST 12 7313 #define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_LEN 4 7314 /* tbd */ 7315 #define MC_CMD_INIT_EVQ_V2_IN_FLAGS_OFST 16 7316 #define MC_CMD_INIT_EVQ_V2_IN_FLAGS_LEN 4 7317 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_LBN 0 7318 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_WIDTH 1 7319 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_LBN 1 7320 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_WIDTH 1 7321 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_LBN 2 7322 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_WIDTH 1 7323 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_LBN 3 7324 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_WIDTH 1 7325 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_LBN 4 7326 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_WIDTH 1 7327 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_LBN 5 7328 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_WIDTH 1 7329 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_LBN 6 7330 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_WIDTH 1 7331 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LBN 7 7332 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_WIDTH 4 7333 /* enum: All initialisation flags specified by host. */ 7334 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_MANUAL 0x0 7335 /* enum: MEDFORD only. Certain initialisation flags specified by host may be 7336 * over-ridden by firmware based on licenses and firmware variant in order to 7337 * provide the lowest latency achievable. See 7338 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags. 7339 */ 7340 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY 0x1 7341 /* enum: MEDFORD only. Certain initialisation flags specified by host may be 7342 * over-ridden by firmware based on licenses and firmware variant in order to 7343 * provide the best throughput achievable. See 7344 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags. 7345 */ 7346 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT 0x2 7347 /* enum: MEDFORD only. Certain initialisation flags may be over-ridden by 7348 * firmware based on licenses and firmware variant. See 7349 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags. 7350 */ 7351 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO 0x3 7352 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_OFST 20 7353 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_LEN 4 7354 /* enum: Disabled */ 7355 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS 0x0 7356 /* enum: Immediate */ 7357 #define MC_CMD_INIT_EVQ_V2_IN_TMR_IMMED_START 0x1 7358 /* enum: Triggered */ 7359 #define MC_CMD_INIT_EVQ_V2_IN_TMR_TRIG_START 0x2 7360 /* enum: Hold-off */ 7361 #define MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF 0x3 7362 /* Target EVQ for wakeups if in wakeup mode. */ 7363 #define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_OFST 24 7364 #define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_LEN 4 7365 /* Target interrupt if in interrupting mode (note union with target EVQ). Use 7366 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test 7367 * purposes. 7368 */ 7369 #define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_OFST 24 7370 #define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_LEN 4 7371 /* Event Counter Mode. */ 7372 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_OFST 28 7373 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_LEN 4 7374 /* enum: Disabled */ 7375 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS 0x0 7376 /* enum: Disabled */ 7377 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RX 0x1 7378 /* enum: Disabled */ 7379 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_TX 0x2 7380 /* enum: Disabled */ 7381 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RXTX 0x3 7382 /* Event queue packet count threshold. */ 7383 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_OFST 32 7384 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_LEN 4 7385 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 7386 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_OFST 36 7387 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LEN 8 7388 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_OFST 36 7389 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_OFST 40 7390 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MINNUM 1 7391 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM 64 7392 7393 /* MC_CMD_INIT_EVQ_V2_OUT msgresponse */ 7394 #define MC_CMD_INIT_EVQ_V2_OUT_LEN 8 7395 /* Only valid if INTRFLAG was true */ 7396 #define MC_CMD_INIT_EVQ_V2_OUT_IRQ_OFST 0 7397 #define MC_CMD_INIT_EVQ_V2_OUT_IRQ_LEN 4 7398 /* Actual configuration applied on the card */ 7399 #define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_OFST 4 7400 #define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_LEN 4 7401 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_LBN 0 7402 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_WIDTH 1 7403 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_LBN 1 7404 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_WIDTH 1 7405 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_LBN 2 7406 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_WIDTH 1 7407 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_LBN 3 7408 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_WIDTH 1 7409 7410 /* QUEUE_CRC_MODE structuredef */ 7411 #define QUEUE_CRC_MODE_LEN 1 7412 #define QUEUE_CRC_MODE_MODE_LBN 0 7413 #define QUEUE_CRC_MODE_MODE_WIDTH 4 7414 /* enum: No CRC. */ 7415 #define QUEUE_CRC_MODE_NONE 0x0 7416 /* enum: CRC Fiber channel over ethernet. */ 7417 #define QUEUE_CRC_MODE_FCOE 0x1 7418 /* enum: CRC (digest) iSCSI header only. */ 7419 #define QUEUE_CRC_MODE_ISCSI_HDR 0x2 7420 /* enum: CRC (digest) iSCSI header and payload. */ 7421 #define QUEUE_CRC_MODE_ISCSI 0x3 7422 /* enum: CRC Fiber channel over IP over ethernet. */ 7423 #define QUEUE_CRC_MODE_FCOIPOE 0x4 7424 /* enum: CRC MPA. */ 7425 #define QUEUE_CRC_MODE_MPA 0x5 7426 #define QUEUE_CRC_MODE_SPARE_LBN 4 7427 #define QUEUE_CRC_MODE_SPARE_WIDTH 4 7428 7429 7430 /***********************************/ 7431 /* MC_CMD_INIT_RXQ 7432 * set up a receive queue according to the supplied parameters. The IN 7433 * arguments end with an address for each 4k of host memory required to back 7434 * the RXQ. 7435 */ 7436 #define MC_CMD_INIT_RXQ 0x81 7437 #undef MC_CMD_0x81_PRIVILEGE_CTG 7438 7439 #define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7440 7441 /* MC_CMD_INIT_RXQ_IN msgrequest: Legacy RXQ_INIT request. Use extended version 7442 * in new code. 7443 */ 7444 #define MC_CMD_INIT_RXQ_IN_LENMIN 36 7445 #define MC_CMD_INIT_RXQ_IN_LENMAX 252 7446 #define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num)) 7447 /* Size, in entries */ 7448 #define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0 7449 #define MC_CMD_INIT_RXQ_IN_SIZE_LEN 4 7450 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ 7451 */ 7452 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4 7453 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_LEN 4 7454 /* The value to put in the event data. Check hardware spec. for valid range. */ 7455 #define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8 7456 #define MC_CMD_INIT_RXQ_IN_LABEL_LEN 4 7457 /* Desired instance. Must be set to a specific instance, which is a function 7458 * local queue index. 7459 */ 7460 #define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12 7461 #define MC_CMD_INIT_RXQ_IN_INSTANCE_LEN 4 7462 /* There will be more flags here. */ 7463 #define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16 7464 #define MC_CMD_INIT_RXQ_IN_FLAGS_LEN 4 7465 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0 7466 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1 7467 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1 7468 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1 7469 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2 7470 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1 7471 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3 7472 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4 7473 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7 7474 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1 7475 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8 7476 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1 7477 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9 7478 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1 7479 #define MC_CMD_INIT_RXQ_IN_UNUSED_LBN 10 7480 #define MC_CMD_INIT_RXQ_IN_UNUSED_WIDTH 1 7481 /* Owner ID to use if in buffer mode (zero if physical) */ 7482 #define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20 7483 #define MC_CMD_INIT_RXQ_IN_OWNER_ID_LEN 4 7484 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 7485 #define MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24 7486 #define MC_CMD_INIT_RXQ_IN_PORT_ID_LEN 4 7487 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 7488 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28 7489 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8 7490 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28 7491 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32 7492 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1 7493 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28 7494 7495 /* MC_CMD_INIT_RXQ_EXT_IN msgrequest: Extended RXQ_INIT with additional mode 7496 * flags 7497 */ 7498 #define MC_CMD_INIT_RXQ_EXT_IN_LEN 544 7499 /* Size, in entries */ 7500 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0 7501 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_LEN 4 7502 /* The EVQ to send events to. This is an index originally specified to 7503 * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE. 7504 */ 7505 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4 7506 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_LEN 4 7507 /* The value to put in the event data. Check hardware spec. for valid range. 7508 * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE 7509 * == PACKED_STREAM. 7510 */ 7511 #define MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8 7512 #define MC_CMD_INIT_RXQ_EXT_IN_LABEL_LEN 4 7513 /* Desired instance. Must be set to a specific instance, which is a function 7514 * local queue index. 7515 */ 7516 #define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12 7517 #define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_LEN 4 7518 /* There will be more flags here. */ 7519 #define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 16 7520 #define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_LEN 4 7521 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 7522 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 7523 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1 7524 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 1 7525 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_LBN 2 7526 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 7527 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_LBN 3 7528 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4 7529 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_LBN 7 7530 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 1 7531 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_LBN 8 7532 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 1 7533 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_LBN 9 7534 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 1 7535 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 10 7536 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4 7537 /* enum: One packet per descriptor (for normal networking) */ 7538 #define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0 7539 /* enum: Pack multiple packets into large descriptors (for SolarCapture) */ 7540 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1 7541 /* enum: Pack multiple packets into large descriptors using the format designed 7542 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with 7543 * multiple fixed-size packet buffers within each bucket. For a full 7544 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath 7545 * firmware. 7546 */ 7547 #define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2 7548 /* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */ 7549 #define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_PACKED_STREAM 0x2 7550 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14 7551 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1 7552 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15 7553 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3 7554 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */ 7555 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */ 7556 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */ 7557 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */ 7558 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */ 7559 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 18 7560 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1 7561 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_LBN 19 7562 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 1 7563 /* Owner ID to use if in buffer mode (zero if physical) */ 7564 #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20 7565 #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_LEN 4 7566 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 7567 #define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_OFST 24 7568 #define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_LEN 4 7569 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 7570 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28 7571 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8 7572 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 28 7573 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 32 7574 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_NUM 64 7575 /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */ 7576 #define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540 7577 #define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_LEN 4 7578 7579 /* MC_CMD_INIT_RXQ_V3_IN msgrequest */ 7580 #define MC_CMD_INIT_RXQ_V3_IN_LEN 560 7581 /* Size, in entries */ 7582 #define MC_CMD_INIT_RXQ_V3_IN_SIZE_OFST 0 7583 #define MC_CMD_INIT_RXQ_V3_IN_SIZE_LEN 4 7584 /* The EVQ to send events to. This is an index originally specified to 7585 * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE. 7586 */ 7587 #define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_OFST 4 7588 #define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_LEN 4 7589 /* The value to put in the event data. Check hardware spec. for valid range. 7590 * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE 7591 * == PACKED_STREAM. 7592 */ 7593 #define MC_CMD_INIT_RXQ_V3_IN_LABEL_OFST 8 7594 #define MC_CMD_INIT_RXQ_V3_IN_LABEL_LEN 4 7595 /* Desired instance. Must be set to a specific instance, which is a function 7596 * local queue index. 7597 */ 7598 #define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_OFST 12 7599 #define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_LEN 4 7600 /* There will be more flags here. */ 7601 #define MC_CMD_INIT_RXQ_V3_IN_FLAGS_OFST 16 7602 #define MC_CMD_INIT_RXQ_V3_IN_FLAGS_LEN 4 7603 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_LBN 0 7604 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_WIDTH 1 7605 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_LBN 1 7606 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_WIDTH 1 7607 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_LBN 2 7608 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_WIDTH 1 7609 #define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_LBN 3 7610 #define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_WIDTH 4 7611 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_LBN 7 7612 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_WIDTH 1 7613 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_LBN 8 7614 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_WIDTH 1 7615 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_LBN 9 7616 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_WIDTH 1 7617 #define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_LBN 10 7618 #define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_WIDTH 4 7619 /* enum: One packet per descriptor (for normal networking) */ 7620 #define MC_CMD_INIT_RXQ_V3_IN_SINGLE_PACKET 0x0 7621 /* enum: Pack multiple packets into large descriptors (for SolarCapture) */ 7622 #define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM 0x1 7623 /* enum: Pack multiple packets into large descriptors using the format designed 7624 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with 7625 * multiple fixed-size packet buffers within each bucket. For a full 7626 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath 7627 * firmware. 7628 */ 7629 #define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2 7630 /* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */ 7631 #define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_PACKED_STREAM 0x2 7632 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_LBN 14 7633 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_WIDTH 1 7634 #define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_LBN 15 7635 #define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3 7636 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_1M 0x0 /* enum */ 7637 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_512K 0x1 /* enum */ 7638 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_256K 0x2 /* enum */ 7639 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_128K 0x3 /* enum */ 7640 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_64K 0x4 /* enum */ 7641 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_LBN 18 7642 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1 7643 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_LBN 19 7644 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_WIDTH 1 7645 /* Owner ID to use if in buffer mode (zero if physical) */ 7646 #define MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_OFST 20 7647 #define MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_LEN 4 7648 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 7649 #define MC_CMD_INIT_RXQ_V3_IN_PORT_ID_OFST 24 7650 #define MC_CMD_INIT_RXQ_V3_IN_PORT_ID_LEN 4 7651 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 7652 #define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_OFST 28 7653 #define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LEN 8 7654 #define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_OFST 28 7655 #define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_OFST 32 7656 #define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_NUM 64 7657 /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */ 7658 #define MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_OFST 540 7659 #define MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_LEN 4 7660 /* The number of packet buffers that will be contained within each 7661 * EQUAL_STRIDE_SUPER_BUFFER format bucket supplied by the driver. This field 7662 * is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER. 7663 */ 7664 #define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 544 7665 #define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4 7666 /* The length in bytes of the area in each packet buffer that can be written to 7667 * by the adapter. This is used to store the packet prefix and the packet 7668 * payload. This length does not include any end padding added by the driver. 7669 * This field is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER. 7670 */ 7671 #define MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_OFST 548 7672 #define MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_LEN 4 7673 /* The length in bytes of a single packet buffer within a 7674 * EQUAL_STRIDE_SUPER_BUFFER format bucket. This field is ignored unless 7675 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER. 7676 */ 7677 #define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_OFST 552 7678 #define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_LEN 4 7679 /* The maximum time in nanoseconds that the datapath will be backpressured if 7680 * there are no RX descriptors available. If the timeout is reached and there 7681 * are still no descriptors then the packet will be dropped. A timeout of 0 7682 * means the datapath will never be blocked. This field is ignored unless 7683 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER. 7684 */ 7685 #define MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 556 7686 #define MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4 7687 7688 /* MC_CMD_INIT_RXQ_OUT msgresponse */ 7689 #define MC_CMD_INIT_RXQ_OUT_LEN 0 7690 7691 /* MC_CMD_INIT_RXQ_EXT_OUT msgresponse */ 7692 #define MC_CMD_INIT_RXQ_EXT_OUT_LEN 0 7693 7694 /* MC_CMD_INIT_RXQ_V3_OUT msgresponse */ 7695 #define MC_CMD_INIT_RXQ_V3_OUT_LEN 0 7696 7697 7698 /***********************************/ 7699 /* MC_CMD_INIT_TXQ 7700 */ 7701 #define MC_CMD_INIT_TXQ 0x82 7702 #undef MC_CMD_0x82_PRIVILEGE_CTG 7703 7704 #define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7705 7706 /* MC_CMD_INIT_TXQ_IN msgrequest: Legacy INIT_TXQ request. Use extended version 7707 * in new code. 7708 */ 7709 #define MC_CMD_INIT_TXQ_IN_LENMIN 36 7710 #define MC_CMD_INIT_TXQ_IN_LENMAX 252 7711 #define MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num)) 7712 /* Size, in entries */ 7713 #define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0 7714 #define MC_CMD_INIT_TXQ_IN_SIZE_LEN 4 7715 /* The EVQ to send events to. This is an index originally specified to 7716 * INIT_EVQ. 7717 */ 7718 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4 7719 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_LEN 4 7720 /* The value to put in the event data. Check hardware spec. for valid range. */ 7721 #define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8 7722 #define MC_CMD_INIT_TXQ_IN_LABEL_LEN 4 7723 /* Desired instance. Must be set to a specific instance, which is a function 7724 * local queue index. 7725 */ 7726 #define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12 7727 #define MC_CMD_INIT_TXQ_IN_INSTANCE_LEN 4 7728 /* There will be more flags here. */ 7729 #define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16 7730 #define MC_CMD_INIT_TXQ_IN_FLAGS_LEN 4 7731 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0 7732 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1 7733 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1 7734 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1 7735 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2 7736 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 7737 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3 7738 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 7739 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4 7740 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4 7741 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8 7742 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1 7743 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9 7744 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1 7745 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 7746 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 7747 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 7748 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 7749 /* Owner ID to use if in buffer mode (zero if physical) */ 7750 #define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20 7751 #define MC_CMD_INIT_TXQ_IN_OWNER_ID_LEN 4 7752 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 7753 #define MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24 7754 #define MC_CMD_INIT_TXQ_IN_PORT_ID_LEN 4 7755 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 7756 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28 7757 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8 7758 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28 7759 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32 7760 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1 7761 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28 7762 7763 /* MC_CMD_INIT_TXQ_EXT_IN msgrequest: Extended INIT_TXQ with additional mode 7764 * flags 7765 */ 7766 #define MC_CMD_INIT_TXQ_EXT_IN_LEN 544 7767 /* Size, in entries */ 7768 #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0 7769 #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_LEN 4 7770 /* The EVQ to send events to. This is an index originally specified to 7771 * INIT_EVQ. 7772 */ 7773 #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4 7774 #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_LEN 4 7775 /* The value to put in the event data. Check hardware spec. for valid range. */ 7776 #define MC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 8 7777 #define MC_CMD_INIT_TXQ_EXT_IN_LABEL_LEN 4 7778 /* Desired instance. Must be set to a specific instance, which is a function 7779 * local queue index. 7780 */ 7781 #define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 12 7782 #define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_LEN 4 7783 /* There will be more flags here. */ 7784 #define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_OFST 16 7785 #define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_LEN 4 7786 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 7787 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 7788 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 1 7789 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 1 7790 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_LBN 2 7791 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 7792 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_LBN 3 7793 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 7794 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4 7795 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4 7796 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_LBN 8 7797 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 7798 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_LBN 9 7799 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 1 7800 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 7801 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 7802 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 7803 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 7804 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_LBN 12 7805 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_WIDTH 1 7806 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_LBN 13 7807 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_WIDTH 1 7808 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_LBN 14 7809 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_WIDTH 1 7810 /* Owner ID to use if in buffer mode (zero if physical) */ 7811 #define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 20 7812 #define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_LEN 4 7813 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 7814 #define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_OFST 24 7815 #define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_LEN 4 7816 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 7817 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 28 7818 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 8 7819 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 28 7820 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 32 7821 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 1 7822 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64 7823 /* Flags related to Qbb flow control mode. */ 7824 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_OFST 540 7825 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_LEN 4 7826 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0 7827 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 1 7828 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 1 7829 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_WIDTH 3 7830 7831 /* MC_CMD_INIT_TXQ_OUT msgresponse */ 7832 #define MC_CMD_INIT_TXQ_OUT_LEN 0 7833 7834 7835 /***********************************/ 7836 /* MC_CMD_FINI_EVQ 7837 * Teardown an EVQ. 7838 * 7839 * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first 7840 * or the operation will fail with EBUSY 7841 */ 7842 #define MC_CMD_FINI_EVQ 0x83 7843 #undef MC_CMD_0x83_PRIVILEGE_CTG 7844 7845 #define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7846 7847 /* MC_CMD_FINI_EVQ_IN msgrequest */ 7848 #define MC_CMD_FINI_EVQ_IN_LEN 4 7849 /* Instance of EVQ to destroy. Should be the same instance as that previously 7850 * passed to INIT_EVQ 7851 */ 7852 #define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0 7853 #define MC_CMD_FINI_EVQ_IN_INSTANCE_LEN 4 7854 7855 /* MC_CMD_FINI_EVQ_OUT msgresponse */ 7856 #define MC_CMD_FINI_EVQ_OUT_LEN 0 7857 7858 7859 /***********************************/ 7860 /* MC_CMD_FINI_RXQ 7861 * Teardown a RXQ. 7862 */ 7863 #define MC_CMD_FINI_RXQ 0x84 7864 #undef MC_CMD_0x84_PRIVILEGE_CTG 7865 7866 #define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7867 7868 /* MC_CMD_FINI_RXQ_IN msgrequest */ 7869 #define MC_CMD_FINI_RXQ_IN_LEN 4 7870 /* Instance of RXQ to destroy */ 7871 #define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0 7872 #define MC_CMD_FINI_RXQ_IN_INSTANCE_LEN 4 7873 7874 /* MC_CMD_FINI_RXQ_OUT msgresponse */ 7875 #define MC_CMD_FINI_RXQ_OUT_LEN 0 7876 7877 7878 /***********************************/ 7879 /* MC_CMD_FINI_TXQ 7880 * Teardown a TXQ. 7881 */ 7882 #define MC_CMD_FINI_TXQ 0x85 7883 #undef MC_CMD_0x85_PRIVILEGE_CTG 7884 7885 #define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7886 7887 /* MC_CMD_FINI_TXQ_IN msgrequest */ 7888 #define MC_CMD_FINI_TXQ_IN_LEN 4 7889 /* Instance of TXQ to destroy */ 7890 #define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0 7891 #define MC_CMD_FINI_TXQ_IN_INSTANCE_LEN 4 7892 7893 /* MC_CMD_FINI_TXQ_OUT msgresponse */ 7894 #define MC_CMD_FINI_TXQ_OUT_LEN 0 7895 7896 7897 /***********************************/ 7898 /* MC_CMD_DRIVER_EVENT 7899 * Generate an event on an EVQ belonging to the function issuing the command. 7900 */ 7901 #define MC_CMD_DRIVER_EVENT 0x86 7902 #undef MC_CMD_0x86_PRIVILEGE_CTG 7903 7904 #define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7905 7906 /* MC_CMD_DRIVER_EVENT_IN msgrequest */ 7907 #define MC_CMD_DRIVER_EVENT_IN_LEN 12 7908 /* Handle of target EVQ */ 7909 #define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0 7910 #define MC_CMD_DRIVER_EVENT_IN_EVQ_LEN 4 7911 /* Bits 0 - 63 of event */ 7912 #define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4 7913 #define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8 7914 #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4 7915 #define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8 7916 7917 /* MC_CMD_DRIVER_EVENT_OUT msgresponse */ 7918 #define MC_CMD_DRIVER_EVENT_OUT_LEN 0 7919 7920 7921 /***********************************/ 7922 /* MC_CMD_PROXY_CMD 7923 * Execute an arbitrary MCDI command on behalf of a different function, subject 7924 * to security restrictions. The command to be proxied follows immediately 7925 * afterward in the host buffer (or on the UART). This command supercedes 7926 * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated. 7927 */ 7928 #define MC_CMD_PROXY_CMD 0x5b 7929 #undef MC_CMD_0x5b_PRIVILEGE_CTG 7930 7931 #define MC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7932 7933 /* MC_CMD_PROXY_CMD_IN msgrequest */ 7934 #define MC_CMD_PROXY_CMD_IN_LEN 4 7935 /* The handle of the target function. */ 7936 #define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0 7937 #define MC_CMD_PROXY_CMD_IN_TARGET_LEN 4 7938 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0 7939 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16 7940 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16 7941 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16 7942 #define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */ 7943 7944 /* MC_CMD_PROXY_CMD_OUT msgresponse */ 7945 #define MC_CMD_PROXY_CMD_OUT_LEN 0 7946 7947 /* MC_PROXY_STATUS_BUFFER structuredef: Host memory status buffer used to 7948 * manage proxied requests 7949 */ 7950 #define MC_PROXY_STATUS_BUFFER_LEN 16 7951 /* Handle allocated by the firmware for this proxy transaction */ 7952 #define MC_PROXY_STATUS_BUFFER_HANDLE_OFST 0 7953 #define MC_PROXY_STATUS_BUFFER_HANDLE_LEN 4 7954 /* enum: An invalid handle. */ 7955 #define MC_PROXY_STATUS_BUFFER_HANDLE_INVALID 0x0 7956 #define MC_PROXY_STATUS_BUFFER_HANDLE_LBN 0 7957 #define MC_PROXY_STATUS_BUFFER_HANDLE_WIDTH 32 7958 /* The requesting physical function number */ 7959 #define MC_PROXY_STATUS_BUFFER_PF_OFST 4 7960 #define MC_PROXY_STATUS_BUFFER_PF_LEN 2 7961 #define MC_PROXY_STATUS_BUFFER_PF_LBN 32 7962 #define MC_PROXY_STATUS_BUFFER_PF_WIDTH 16 7963 /* The requesting virtual function number. Set to VF_NULL if the target is a 7964 * PF. 7965 */ 7966 #define MC_PROXY_STATUS_BUFFER_VF_OFST 6 7967 #define MC_PROXY_STATUS_BUFFER_VF_LEN 2 7968 #define MC_PROXY_STATUS_BUFFER_VF_LBN 48 7969 #define MC_PROXY_STATUS_BUFFER_VF_WIDTH 16 7970 /* The target function RID. */ 7971 #define MC_PROXY_STATUS_BUFFER_RID_OFST 8 7972 #define MC_PROXY_STATUS_BUFFER_RID_LEN 2 7973 #define MC_PROXY_STATUS_BUFFER_RID_LBN 64 7974 #define MC_PROXY_STATUS_BUFFER_RID_WIDTH 16 7975 /* The status of the proxy as described in MC_CMD_PROXY_COMPLETE. */ 7976 #define MC_PROXY_STATUS_BUFFER_STATUS_OFST 10 7977 #define MC_PROXY_STATUS_BUFFER_STATUS_LEN 2 7978 #define MC_PROXY_STATUS_BUFFER_STATUS_LBN 80 7979 #define MC_PROXY_STATUS_BUFFER_STATUS_WIDTH 16 7980 /* If a request is authorized rather than carried out by the host, this is the 7981 * elevated privilege mask granted to the requesting function. 7982 */ 7983 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_OFST 12 7984 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LEN 4 7985 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LBN 96 7986 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_WIDTH 32 7987 7988 7989 /***********************************/ 7990 /* MC_CMD_PROXY_CONFIGURE 7991 * Enable/disable authorization of MCDI requests from unprivileged functions by 7992 * a designated admin function 7993 */ 7994 #define MC_CMD_PROXY_CONFIGURE 0x58 7995 #undef MC_CMD_0x58_PRIVILEGE_CTG 7996 7997 #define MC_CMD_0x58_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7998 7999 /* MC_CMD_PROXY_CONFIGURE_IN msgrequest */ 8000 #define MC_CMD_PROXY_CONFIGURE_IN_LEN 108 8001 #define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_OFST 0 8002 #define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_LEN 4 8003 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_LBN 0 8004 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_WIDTH 1 8005 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8006 * of blocks, each of the size REQUEST_BLOCK_SIZE. 8007 */ 8008 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 4 8009 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LEN 8 8010 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 4 8011 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_OFST 8 8012 /* Must be a power of 2 */ 8013 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_OFST 12 8014 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_LEN 4 8015 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8016 * of blocks, each of the size REPLY_BLOCK_SIZE. 8017 */ 8018 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_OFST 16 8019 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LEN 8 8020 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_OFST 16 8021 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_OFST 20 8022 /* Must be a power of 2 */ 8023 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_OFST 24 8024 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_LEN 4 8025 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8026 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if 8027 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. 8028 */ 8029 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_OFST 28 8030 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LEN 8 8031 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_OFST 28 8032 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_OFST 32 8033 /* Must be a power of 2, or zero if this buffer is not provided */ 8034 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_OFST 36 8035 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_LEN 4 8036 /* Applies to all three buffers */ 8037 #define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_OFST 40 8038 #define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_LEN 4 8039 /* A bit mask defining which MCDI operations may be proxied */ 8040 #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_OFST 44 8041 #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_LEN 64 8042 8043 /* MC_CMD_PROXY_CONFIGURE_EXT_IN msgrequest */ 8044 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_LEN 112 8045 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_OFST 0 8046 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_LEN 4 8047 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_LBN 0 8048 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_WIDTH 1 8049 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8050 * of blocks, each of the size REQUEST_BLOCK_SIZE. 8051 */ 8052 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_OFST 4 8053 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LEN 8 8054 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_OFST 4 8055 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_OFST 8 8056 /* Must be a power of 2 */ 8057 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_OFST 12 8058 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_LEN 4 8059 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8060 * of blocks, each of the size REPLY_BLOCK_SIZE. 8061 */ 8062 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_OFST 16 8063 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LEN 8 8064 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_OFST 16 8065 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_OFST 20 8066 /* Must be a power of 2 */ 8067 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_OFST 24 8068 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_LEN 4 8069 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8070 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if 8071 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. 8072 */ 8073 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_OFST 28 8074 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LEN 8 8075 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_OFST 28 8076 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_OFST 32 8077 /* Must be a power of 2, or zero if this buffer is not provided */ 8078 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_OFST 36 8079 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_LEN 4 8080 /* Applies to all three buffers */ 8081 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_OFST 40 8082 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_LEN 4 8083 /* A bit mask defining which MCDI operations may be proxied */ 8084 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_OFST 44 8085 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_LEN 64 8086 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_OFST 108 8087 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_LEN 4 8088 8089 /* MC_CMD_PROXY_CONFIGURE_OUT msgresponse */ 8090 #define MC_CMD_PROXY_CONFIGURE_OUT_LEN 0 8091 8092 8093 /***********************************/ 8094 /* MC_CMD_PROXY_COMPLETE 8095 * Tells FW that a requested proxy operation has either been completed (by 8096 * using MC_CMD_PROXY_CMD) or authorized/declined. May only be sent by the 8097 * function that enabled proxying/authorization (by using 8098 * MC_CMD_PROXY_CONFIGURE). 8099 */ 8100 #define MC_CMD_PROXY_COMPLETE 0x5f 8101 #undef MC_CMD_0x5f_PRIVILEGE_CTG 8102 8103 #define MC_CMD_0x5f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8104 8105 /* MC_CMD_PROXY_COMPLETE_IN msgrequest */ 8106 #define MC_CMD_PROXY_COMPLETE_IN_LEN 12 8107 #define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_OFST 0 8108 #define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_LEN 4 8109 #define MC_CMD_PROXY_COMPLETE_IN_STATUS_OFST 4 8110 #define MC_CMD_PROXY_COMPLETE_IN_STATUS_LEN 4 8111 /* enum: The operation has been completed by using MC_CMD_PROXY_CMD, the reply 8112 * is stored in the REPLY_BUFF. 8113 */ 8114 #define MC_CMD_PROXY_COMPLETE_IN_COMPLETE 0x0 8115 /* enum: The operation has been authorized. The originating function may now 8116 * try again. 8117 */ 8118 #define MC_CMD_PROXY_COMPLETE_IN_AUTHORIZED 0x1 8119 /* enum: The operation has been declined. */ 8120 #define MC_CMD_PROXY_COMPLETE_IN_DECLINED 0x2 8121 /* enum: The authorization failed because the relevant application did not 8122 * respond in time. 8123 */ 8124 #define MC_CMD_PROXY_COMPLETE_IN_TIMEDOUT 0x3 8125 #define MC_CMD_PROXY_COMPLETE_IN_HANDLE_OFST 8 8126 #define MC_CMD_PROXY_COMPLETE_IN_HANDLE_LEN 4 8127 8128 /* MC_CMD_PROXY_COMPLETE_OUT msgresponse */ 8129 #define MC_CMD_PROXY_COMPLETE_OUT_LEN 0 8130 8131 8132 /***********************************/ 8133 /* MC_CMD_ALLOC_BUFTBL_CHUNK 8134 * Allocate a set of buffer table entries using the specified owner ID. This 8135 * operation allocates the required buffer table entries (and fails if it 8136 * cannot do so). The buffer table entries will initially be zeroed. 8137 */ 8138 #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87 8139 #undef MC_CMD_0x87_PRIVILEGE_CTG 8140 8141 #define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 8142 8143 /* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */ 8144 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8 8145 /* Owner ID to use */ 8146 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0 8147 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_LEN 4 8148 /* Size of buffer table pages to use, in bytes (note that only a few values are 8149 * legal on any specific hardware). 8150 */ 8151 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4 8152 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_LEN 4 8153 8154 /* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */ 8155 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12 8156 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0 8157 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_LEN 4 8158 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4 8159 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_LEN 4 8160 /* Buffer table IDs for use in DMA descriptors. */ 8161 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8 8162 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_LEN 4 8163 8164 8165 /***********************************/ 8166 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES 8167 * Reprogram a set of buffer table entries in the specified chunk. 8168 */ 8169 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88 8170 #undef MC_CMD_0x88_PRIVILEGE_CTG 8171 8172 #define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 8173 8174 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */ 8175 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20 8176 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 268 8177 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num)) 8178 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0 8179 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_LEN 4 8180 /* ID */ 8181 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4 8182 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4 8183 /* Num entries */ 8184 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8 8185 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4 8186 /* Buffer table entry address */ 8187 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12 8188 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8 8189 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12 8190 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16 8191 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1 8192 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32 8193 8194 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */ 8195 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0 8196 8197 8198 /***********************************/ 8199 /* MC_CMD_FREE_BUFTBL_CHUNK 8200 */ 8201 #define MC_CMD_FREE_BUFTBL_CHUNK 0x89 8202 #undef MC_CMD_0x89_PRIVILEGE_CTG 8203 8204 #define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 8205 8206 /* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */ 8207 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4 8208 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0 8209 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_LEN 4 8210 8211 /* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */ 8212 #define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0 8213 8214 8215 /***********************************/ 8216 /* MC_CMD_FILTER_OP 8217 * Multiplexed MCDI call for filter operations 8218 */ 8219 #define MC_CMD_FILTER_OP 0x8a 8220 #undef MC_CMD_0x8a_PRIVILEGE_CTG 8221 8222 #define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8223 8224 /* MC_CMD_FILTER_OP_IN msgrequest */ 8225 #define MC_CMD_FILTER_OP_IN_LEN 108 8226 /* identifies the type of operation requested */ 8227 #define MC_CMD_FILTER_OP_IN_OP_OFST 0 8228 #define MC_CMD_FILTER_OP_IN_OP_LEN 4 8229 /* enum: single-recipient filter insert */ 8230 #define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0 8231 /* enum: single-recipient filter remove */ 8232 #define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1 8233 /* enum: multi-recipient filter subscribe */ 8234 #define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2 8235 /* enum: multi-recipient filter unsubscribe */ 8236 #define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3 8237 /* enum: replace one recipient with another (warning - the filter handle may 8238 * change) 8239 */ 8240 #define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4 8241 /* filter handle (for remove / unsubscribe operations) */ 8242 #define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4 8243 #define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8 8244 #define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4 8245 #define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8 8246 /* The port ID associated with the v-adaptor which should contain this filter. 8247 */ 8248 #define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12 8249 #define MC_CMD_FILTER_OP_IN_PORT_ID_LEN 4 8250 /* fields to include in match criteria */ 8251 #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16 8252 #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_LEN 4 8253 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0 8254 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1 8255 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1 8256 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1 8257 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2 8258 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1 8259 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3 8260 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1 8261 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4 8262 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1 8263 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5 8264 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1 8265 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6 8266 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1 8267 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7 8268 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1 8269 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8 8270 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1 8271 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9 8272 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1 8273 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10 8274 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1 8275 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11 8276 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1 8277 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 8278 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 8279 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 8280 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 8281 /* receive destination */ 8282 #define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20 8283 #define MC_CMD_FILTER_OP_IN_RX_DEST_LEN 4 8284 /* enum: drop packets */ 8285 #define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0 8286 /* enum: receive to host */ 8287 #define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1 8288 /* enum: receive to MC */ 8289 #define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2 8290 /* enum: loop back to TXDP 0 */ 8291 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3 8292 /* enum: loop back to TXDP 1 */ 8293 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4 8294 /* receive queue handle (for multiple queue modes, this is the base queue) */ 8295 #define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24 8296 #define MC_CMD_FILTER_OP_IN_RX_QUEUE_LEN 4 8297 /* receive mode */ 8298 #define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28 8299 #define MC_CMD_FILTER_OP_IN_RX_MODE_LEN 4 8300 /* enum: receive to just the specified queue */ 8301 #define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0 8302 /* enum: receive to multiple queues using RSS context */ 8303 #define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1 8304 /* enum: receive to multiple queues using .1p mapping */ 8305 #define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2 8306 /* enum: install a filter entry that will never match; for test purposes only 8307 */ 8308 #define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 8309 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 8310 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 8311 * MC_CMD_DOT1P_MAPPING_ALLOC. 8312 */ 8313 #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32 8314 #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_LEN 4 8315 /* transmit domain (reserved; set to 0) */ 8316 #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36 8317 #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_LEN 4 8318 /* transmit destination (either set the MAC and/or PM bits for explicit 8319 * control, or set this field to TX_DEST_DEFAULT for sensible default 8320 * behaviour) 8321 */ 8322 #define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40 8323 #define MC_CMD_FILTER_OP_IN_TX_DEST_LEN 4 8324 /* enum: request default behaviour (based on filter type) */ 8325 #define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff 8326 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0 8327 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1 8328 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1 8329 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1 8330 /* source MAC address to match (as bytes in network order) */ 8331 #define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44 8332 #define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6 8333 /* source port to match (as bytes in network order) */ 8334 #define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50 8335 #define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2 8336 /* destination MAC address to match (as bytes in network order) */ 8337 #define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52 8338 #define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6 8339 /* destination port to match (as bytes in network order) */ 8340 #define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58 8341 #define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2 8342 /* Ethernet type to match (as bytes in network order) */ 8343 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60 8344 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2 8345 /* Inner VLAN tag to match (as bytes in network order) */ 8346 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62 8347 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2 8348 /* Outer VLAN tag to match (as bytes in network order) */ 8349 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64 8350 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2 8351 /* IP protocol to match (in low byte; set high byte to 0) */ 8352 #define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66 8353 #define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2 8354 /* Firmware defined register 0 to match (reserved; set to 0) */ 8355 #define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68 8356 #define MC_CMD_FILTER_OP_IN_FWDEF0_LEN 4 8357 /* Firmware defined register 1 to match (reserved; set to 0) */ 8358 #define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72 8359 #define MC_CMD_FILTER_OP_IN_FWDEF1_LEN 4 8360 /* source IP address to match (as bytes in network order; set last 12 bytes to 8361 * 0 for IPv4 address) 8362 */ 8363 #define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76 8364 #define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16 8365 /* destination IP address to match (as bytes in network order; set last 12 8366 * bytes to 0 for IPv4 address) 8367 */ 8368 #define MC_CMD_FILTER_OP_IN_DST_IP_OFST 92 8369 #define MC_CMD_FILTER_OP_IN_DST_IP_LEN 16 8370 8371 /* MC_CMD_FILTER_OP_EXT_IN msgrequest: Extension to MC_CMD_FILTER_OP_IN to 8372 * include handling of VXLAN/NVGRE encapsulated frame filtering (which is 8373 * supported on Medford only). 8374 */ 8375 #define MC_CMD_FILTER_OP_EXT_IN_LEN 172 8376 /* identifies the type of operation requested */ 8377 #define MC_CMD_FILTER_OP_EXT_IN_OP_OFST 0 8378 #define MC_CMD_FILTER_OP_EXT_IN_OP_LEN 4 8379 /* Enum values, see field(s): */ 8380 /* MC_CMD_FILTER_OP_IN/OP */ 8381 /* filter handle (for remove / unsubscribe operations) */ 8382 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4 8383 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 8 8384 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4 8385 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 8 8386 /* The port ID associated with the v-adaptor which should contain this filter. 8387 */ 8388 #define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12 8389 #define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_LEN 4 8390 /* fields to include in match criteria */ 8391 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 16 8392 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_LEN 4 8393 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0 8394 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1 8395 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1 8396 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 1 8397 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_LBN 2 8398 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 1 8399 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_LBN 3 8400 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 1 8401 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4 8402 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 1 8403 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_LBN 5 8404 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 1 8405 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN 6 8406 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 1 8407 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_LBN 7 8408 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 1 8409 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_LBN 8 8410 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 1 8411 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN 9 8412 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 1 8413 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_LBN 10 8414 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 1 8415 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_LBN 11 8416 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 1 8417 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_LBN 12 8418 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 1 8419 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_LBN 13 8420 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 1 8421 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_LBN 14 8422 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 1 8423 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_LBN 15 8424 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 1 8425 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_LBN 16 8426 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 1 8427 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_LBN 17 8428 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 1 8429 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_LBN 18 8430 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1 8431 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_LBN 19 8432 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1 8433 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_LBN 20 8434 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1 8435 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_LBN 21 8436 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 1 8437 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_LBN 22 8438 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 1 8439 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_LBN 23 8440 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 1 8441 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24 8442 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1 8443 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25 8444 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1 8445 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 8446 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 8447 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 8448 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 8449 /* receive destination */ 8450 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_OFST 20 8451 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_LEN 4 8452 /* enum: drop packets */ 8453 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0 8454 /* enum: receive to host */ 8455 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1 8456 /* enum: receive to MC */ 8457 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2 8458 /* enum: loop back to TXDP 0 */ 8459 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3 8460 /* enum: loop back to TXDP 1 */ 8461 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4 8462 /* receive queue handle (for multiple queue modes, this is the base queue) */ 8463 #define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_OFST 24 8464 #define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_LEN 4 8465 /* receive mode */ 8466 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_OFST 28 8467 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_LEN 4 8468 /* enum: receive to just the specified queue */ 8469 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0 8470 /* enum: receive to multiple queues using RSS context */ 8471 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1 8472 /* enum: receive to multiple queues using .1p mapping */ 8473 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2 8474 /* enum: install a filter entry that will never match; for test purposes only 8475 */ 8476 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 8477 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 8478 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 8479 * MC_CMD_DOT1P_MAPPING_ALLOC. 8480 */ 8481 #define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_OFST 32 8482 #define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_LEN 4 8483 /* transmit domain (reserved; set to 0) */ 8484 #define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_OFST 36 8485 #define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_LEN 4 8486 /* transmit destination (either set the MAC and/or PM bits for explicit 8487 * control, or set this field to TX_DEST_DEFAULT for sensible default 8488 * behaviour) 8489 */ 8490 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_OFST 40 8491 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_LEN 4 8492 /* enum: request default behaviour (based on filter type) */ 8493 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff 8494 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0 8495 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1 8496 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1 8497 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 1 8498 /* source MAC address to match (as bytes in network order) */ 8499 #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_OFST 44 8500 #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_LEN 6 8501 /* source port to match (as bytes in network order) */ 8502 #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_OFST 50 8503 #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_LEN 2 8504 /* destination MAC address to match (as bytes in network order) */ 8505 #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_OFST 52 8506 #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_LEN 6 8507 /* destination port to match (as bytes in network order) */ 8508 #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_OFST 58 8509 #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_LEN 2 8510 /* Ethernet type to match (as bytes in network order) */ 8511 #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_OFST 60 8512 #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_LEN 2 8513 /* Inner VLAN tag to match (as bytes in network order) */ 8514 #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_OFST 62 8515 #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_LEN 2 8516 /* Outer VLAN tag to match (as bytes in network order) */ 8517 #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_OFST 64 8518 #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_LEN 2 8519 /* IP protocol to match (in low byte; set high byte to 0) */ 8520 #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_OFST 66 8521 #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_LEN 2 8522 /* Firmware defined register 0 to match (reserved; set to 0) */ 8523 #define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_OFST 68 8524 #define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_LEN 4 8525 /* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP 8526 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for 8527 * VXLAN/NVGRE, or 1 for Geneve) 8528 */ 8529 #define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 72 8530 #define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_LEN 4 8531 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0 8532 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 24 8533 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 24 8534 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 8 8535 /* enum: Match VXLAN traffic with this VNI */ 8536 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0 8537 /* enum: Match Geneve traffic with this VNI */ 8538 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1 8539 /* enum: Reserved for experimental development use */ 8540 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe 8541 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0 8542 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 24 8543 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 24 8544 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 8 8545 /* enum: Match NVGRE traffic with this VSID */ 8546 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0 8547 /* source IP address to match (as bytes in network order; set last 12 bytes to 8548 * 0 for IPv4 address) 8549 */ 8550 #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_OFST 76 8551 #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_LEN 16 8552 /* destination IP address to match (as bytes in network order; set last 12 8553 * bytes to 0 for IPv4 address) 8554 */ 8555 #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_OFST 92 8556 #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_LEN 16 8557 /* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network 8558 * order) 8559 */ 8560 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_OFST 108 8561 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_LEN 6 8562 /* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */ 8563 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_OFST 114 8564 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_LEN 2 8565 /* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in 8566 * network order) 8567 */ 8568 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_OFST 116 8569 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_LEN 6 8570 /* VXLAN/NVGRE inner frame destination port to match (as bytes in network 8571 * order) 8572 */ 8573 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_OFST 122 8574 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_LEN 2 8575 /* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order) 8576 */ 8577 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_OFST 124 8578 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_LEN 2 8579 /* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order) 8580 */ 8581 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_OFST 126 8582 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_LEN 2 8583 /* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order) 8584 */ 8585 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_OFST 128 8586 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_LEN 2 8587 /* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to 8588 * 0) 8589 */ 8590 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_OFST 130 8591 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_LEN 2 8592 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set 8593 * to 0) 8594 */ 8595 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_OFST 132 8596 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_LEN 4 8597 /* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set 8598 * to 0) 8599 */ 8600 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_OFST 136 8601 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_LEN 4 8602 /* VXLAN/NVGRE inner frame source IP address to match (as bytes in network 8603 * order; set last 12 bytes to 0 for IPv4 address) 8604 */ 8605 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_OFST 140 8606 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_LEN 16 8607 /* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network 8608 * order; set last 12 bytes to 0 for IPv4 address) 8609 */ 8610 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_OFST 156 8611 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 16 8612 8613 /* MC_CMD_FILTER_OP_V3_IN msgrequest: FILTER_OP extension to support additional 8614 * filter actions for Intel's DPDK (Data Plane Development Kit, dpdk.org) via 8615 * its rte_flow API. This extension is only useful with the sfc_efx driver 8616 * included as part of DPDK, used in conjunction with the dpdk datapath 8617 * firmware variant. 8618 */ 8619 #define MC_CMD_FILTER_OP_V3_IN_LEN 180 8620 /* identifies the type of operation requested */ 8621 #define MC_CMD_FILTER_OP_V3_IN_OP_OFST 0 8622 #define MC_CMD_FILTER_OP_V3_IN_OP_LEN 4 8623 /* Enum values, see field(s): */ 8624 /* MC_CMD_FILTER_OP_IN/OP */ 8625 /* filter handle (for remove / unsubscribe operations) */ 8626 #define MC_CMD_FILTER_OP_V3_IN_HANDLE_OFST 4 8627 #define MC_CMD_FILTER_OP_V3_IN_HANDLE_LEN 8 8628 #define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_OFST 4 8629 #define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_OFST 8 8630 /* The port ID associated with the v-adaptor which should contain this filter. 8631 */ 8632 #define MC_CMD_FILTER_OP_V3_IN_PORT_ID_OFST 12 8633 #define MC_CMD_FILTER_OP_V3_IN_PORT_ID_LEN 4 8634 /* fields to include in match criteria */ 8635 #define MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_OFST 16 8636 #define MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_LEN 4 8637 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_LBN 0 8638 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_WIDTH 1 8639 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_LBN 1 8640 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_WIDTH 1 8641 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_LBN 2 8642 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_WIDTH 1 8643 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_LBN 3 8644 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_WIDTH 1 8645 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_LBN 4 8646 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_WIDTH 1 8647 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_LBN 5 8648 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_WIDTH 1 8649 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_LBN 6 8650 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_WIDTH 1 8651 #define MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_LBN 7 8652 #define MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_WIDTH 1 8653 #define MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_LBN 8 8654 #define MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_WIDTH 1 8655 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_LBN 9 8656 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_WIDTH 1 8657 #define MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_LBN 10 8658 #define MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_WIDTH 1 8659 #define MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_LBN 11 8660 #define MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_WIDTH 1 8661 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_LBN 12 8662 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_WIDTH 1 8663 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_LBN 13 8664 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_WIDTH 1 8665 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_LBN 14 8666 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_WIDTH 1 8667 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_LBN 15 8668 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_WIDTH 1 8669 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_LBN 16 8670 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_WIDTH 1 8671 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_LBN 17 8672 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_WIDTH 1 8673 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_LBN 18 8674 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1 8675 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_LBN 19 8676 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1 8677 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_LBN 20 8678 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1 8679 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_LBN 21 8680 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_WIDTH 1 8681 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_LBN 22 8682 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_WIDTH 1 8683 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_LBN 23 8684 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_WIDTH 1 8685 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24 8686 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1 8687 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25 8688 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1 8689 #define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 8690 #define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 8691 #define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 8692 #define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 8693 /* receive destination */ 8694 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_OFST 20 8695 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_LEN 4 8696 /* enum: drop packets */ 8697 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_DROP 0x0 8698 /* enum: receive to host */ 8699 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_HOST 0x1 8700 /* enum: receive to MC */ 8701 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_MC 0x2 8702 /* enum: loop back to TXDP 0 */ 8703 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX0 0x3 8704 /* enum: loop back to TXDP 1 */ 8705 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX1 0x4 8706 /* receive queue handle (for multiple queue modes, this is the base queue) */ 8707 #define MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_OFST 24 8708 #define MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_LEN 4 8709 /* receive mode */ 8710 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_OFST 28 8711 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_LEN 4 8712 /* enum: receive to just the specified queue */ 8713 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_SIMPLE 0x0 8714 /* enum: receive to multiple queues using RSS context */ 8715 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_RSS 0x1 8716 /* enum: receive to multiple queues using .1p mapping */ 8717 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_DOT1P_MAPPING 0x2 8718 /* enum: install a filter entry that will never match; for test purposes only 8719 */ 8720 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 8721 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 8722 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 8723 * MC_CMD_DOT1P_MAPPING_ALLOC. 8724 */ 8725 #define MC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_OFST 32 8726 #define MC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_LEN 4 8727 /* transmit domain (reserved; set to 0) */ 8728 #define MC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_OFST 36 8729 #define MC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_LEN 4 8730 /* transmit destination (either set the MAC and/or PM bits for explicit 8731 * control, or set this field to TX_DEST_DEFAULT for sensible default 8732 * behaviour) 8733 */ 8734 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_OFST 40 8735 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_LEN 4 8736 /* enum: request default behaviour (based on filter type) */ 8737 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_DEFAULT 0xffffffff 8738 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_LBN 0 8739 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_WIDTH 1 8740 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_LBN 1 8741 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_WIDTH 1 8742 /* source MAC address to match (as bytes in network order) */ 8743 #define MC_CMD_FILTER_OP_V3_IN_SRC_MAC_OFST 44 8744 #define MC_CMD_FILTER_OP_V3_IN_SRC_MAC_LEN 6 8745 /* source port to match (as bytes in network order) */ 8746 #define MC_CMD_FILTER_OP_V3_IN_SRC_PORT_OFST 50 8747 #define MC_CMD_FILTER_OP_V3_IN_SRC_PORT_LEN 2 8748 /* destination MAC address to match (as bytes in network order) */ 8749 #define MC_CMD_FILTER_OP_V3_IN_DST_MAC_OFST 52 8750 #define MC_CMD_FILTER_OP_V3_IN_DST_MAC_LEN 6 8751 /* destination port to match (as bytes in network order) */ 8752 #define MC_CMD_FILTER_OP_V3_IN_DST_PORT_OFST 58 8753 #define MC_CMD_FILTER_OP_V3_IN_DST_PORT_LEN 2 8754 /* Ethernet type to match (as bytes in network order) */ 8755 #define MC_CMD_FILTER_OP_V3_IN_ETHER_TYPE_OFST 60 8756 #define MC_CMD_FILTER_OP_V3_IN_ETHER_TYPE_LEN 2 8757 /* Inner VLAN tag to match (as bytes in network order) */ 8758 #define MC_CMD_FILTER_OP_V3_IN_INNER_VLAN_OFST 62 8759 #define MC_CMD_FILTER_OP_V3_IN_INNER_VLAN_LEN 2 8760 /* Outer VLAN tag to match (as bytes in network order) */ 8761 #define MC_CMD_FILTER_OP_V3_IN_OUTER_VLAN_OFST 64 8762 #define MC_CMD_FILTER_OP_V3_IN_OUTER_VLAN_LEN 2 8763 /* IP protocol to match (in low byte; set high byte to 0) */ 8764 #define MC_CMD_FILTER_OP_V3_IN_IP_PROTO_OFST 66 8765 #define MC_CMD_FILTER_OP_V3_IN_IP_PROTO_LEN 2 8766 /* Firmware defined register 0 to match (reserved; set to 0) */ 8767 #define MC_CMD_FILTER_OP_V3_IN_FWDEF0_OFST 68 8768 #define MC_CMD_FILTER_OP_V3_IN_FWDEF0_LEN 4 8769 /* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP 8770 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for 8771 * VXLAN/NVGRE, or 1 for Geneve) 8772 */ 8773 #define MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_OFST 72 8774 #define MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_LEN 4 8775 #define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_LBN 0 8776 #define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_WIDTH 24 8777 #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_LBN 24 8778 #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_WIDTH 8 8779 /* enum: Match VXLAN traffic with this VNI */ 8780 #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_VXLAN 0x0 8781 /* enum: Match Geneve traffic with this VNI */ 8782 #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_GENEVE 0x1 8783 /* enum: Reserved for experimental development use */ 8784 #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_EXPERIMENTAL 0xfe 8785 #define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_LBN 0 8786 #define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_WIDTH 24 8787 #define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_LBN 24 8788 #define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_WIDTH 8 8789 /* enum: Match NVGRE traffic with this VSID */ 8790 #define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_NVGRE 0x0 8791 /* source IP address to match (as bytes in network order; set last 12 bytes to 8792 * 0 for IPv4 address) 8793 */ 8794 #define MC_CMD_FILTER_OP_V3_IN_SRC_IP_OFST 76 8795 #define MC_CMD_FILTER_OP_V3_IN_SRC_IP_LEN 16 8796 /* destination IP address to match (as bytes in network order; set last 12 8797 * bytes to 0 for IPv4 address) 8798 */ 8799 #define MC_CMD_FILTER_OP_V3_IN_DST_IP_OFST 92 8800 #define MC_CMD_FILTER_OP_V3_IN_DST_IP_LEN 16 8801 /* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network 8802 * order) 8803 */ 8804 #define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_MAC_OFST 108 8805 #define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_MAC_LEN 6 8806 /* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */ 8807 #define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_PORT_OFST 114 8808 #define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_PORT_LEN 2 8809 /* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in 8810 * network order) 8811 */ 8812 #define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_MAC_OFST 116 8813 #define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_MAC_LEN 6 8814 /* VXLAN/NVGRE inner frame destination port to match (as bytes in network 8815 * order) 8816 */ 8817 #define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_PORT_OFST 122 8818 #define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_PORT_LEN 2 8819 /* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order) 8820 */ 8821 #define MC_CMD_FILTER_OP_V3_IN_IFRM_ETHER_TYPE_OFST 124 8822 #define MC_CMD_FILTER_OP_V3_IN_IFRM_ETHER_TYPE_LEN 2 8823 /* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order) 8824 */ 8825 #define MC_CMD_FILTER_OP_V3_IN_IFRM_INNER_VLAN_OFST 126 8826 #define MC_CMD_FILTER_OP_V3_IN_IFRM_INNER_VLAN_LEN 2 8827 /* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order) 8828 */ 8829 #define MC_CMD_FILTER_OP_V3_IN_IFRM_OUTER_VLAN_OFST 128 8830 #define MC_CMD_FILTER_OP_V3_IN_IFRM_OUTER_VLAN_LEN 2 8831 /* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to 8832 * 0) 8833 */ 8834 #define MC_CMD_FILTER_OP_V3_IN_IFRM_IP_PROTO_OFST 130 8835 #define MC_CMD_FILTER_OP_V3_IN_IFRM_IP_PROTO_LEN 2 8836 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set 8837 * to 0) 8838 */ 8839 #define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_OFST 132 8840 #define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_LEN 4 8841 /* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set 8842 * to 0) 8843 */ 8844 #define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_OFST 136 8845 #define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_LEN 4 8846 /* VXLAN/NVGRE inner frame source IP address to match (as bytes in network 8847 * order; set last 12 bytes to 0 for IPv4 address) 8848 */ 8849 #define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_IP_OFST 140 8850 #define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_IP_LEN 16 8851 /* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network 8852 * order; set last 12 bytes to 0 for IPv4 address) 8853 */ 8854 #define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_OFST 156 8855 #define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_LEN 16 8856 /* Set an action for all packets matching this filter. The DPDK driver and dpdk 8857 * f/w variant use their own specific delivery structures, which are documented 8858 * in the DPDK Firmware Driver Interface (SF-119419-TC). Requesting anything 8859 * other than MATCH_ACTION_NONE when the NIC is running another f/w variant 8860 * will cause the filter insertion to fail with ENOTSUP. 8861 */ 8862 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_OFST 172 8863 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_LEN 4 8864 /* enum: do nothing extra */ 8865 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_NONE 0x0 8866 /* enum: Set the match flag in the packet prefix for packets matching the 8867 * filter (only with dpdk firmware, otherwise fails with ENOTSUP). Used to 8868 * support the DPDK rte_flow "FLAG" action. 8869 */ 8870 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAG 0x1 8871 /* enum: Insert MATCH_MARK_VALUE into the packet prefix for packets matching 8872 * the filter (only with dpdk firmware, otherwise fails with ENOTSUP). Used to 8873 * support the DPDK rte_flow "MARK" action. 8874 */ 8875 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_MARK 0x2 8876 /* the mark value for MATCH_ACTION_MARK. Requesting a value larger than the 8877 * maximum (obtained from MC_CMD_GET_CAPABILITIES_V5/FILTER_ACTION_MARK_MAX) 8878 * will cause the filter insertion to fail with EINVAL. 8879 */ 8880 #define MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_OFST 176 8881 #define MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_LEN 4 8882 8883 /* MC_CMD_FILTER_OP_OUT msgresponse */ 8884 #define MC_CMD_FILTER_OP_OUT_LEN 12 8885 /* identifies the type of operation requested */ 8886 #define MC_CMD_FILTER_OP_OUT_OP_OFST 0 8887 #define MC_CMD_FILTER_OP_OUT_OP_LEN 4 8888 /* Enum values, see field(s): */ 8889 /* MC_CMD_FILTER_OP_IN/OP */ 8890 /* Returned filter handle (for insert / subscribe operations). Note that these 8891 * handles should be considered opaque to the host, although a value of 8892 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. 8893 */ 8894 #define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4 8895 #define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8 8896 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4 8897 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8 8898 /* enum: guaranteed invalid filter handle (low 32 bits) */ 8899 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff 8900 /* enum: guaranteed invalid filter handle (high 32 bits) */ 8901 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff 8902 8903 /* MC_CMD_FILTER_OP_EXT_OUT msgresponse */ 8904 #define MC_CMD_FILTER_OP_EXT_OUT_LEN 12 8905 /* identifies the type of operation requested */ 8906 #define MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0 8907 #define MC_CMD_FILTER_OP_EXT_OUT_OP_LEN 4 8908 /* Enum values, see field(s): */ 8909 /* MC_CMD_FILTER_OP_EXT_IN/OP */ 8910 /* Returned filter handle (for insert / subscribe operations). Note that these 8911 * handles should be considered opaque to the host, although a value of 8912 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. 8913 */ 8914 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4 8915 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 8 8916 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4 8917 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 8 8918 /* Enum values, see field(s): */ 8919 /* MC_CMD_FILTER_OP_OUT/HANDLE */ 8920 8921 8922 /***********************************/ 8923 /* MC_CMD_GET_PARSER_DISP_INFO 8924 * Get information related to the parser-dispatcher subsystem 8925 */ 8926 #define MC_CMD_GET_PARSER_DISP_INFO 0xe4 8927 #undef MC_CMD_0xe4_PRIVILEGE_CTG 8928 8929 #define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8930 8931 /* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */ 8932 #define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4 8933 /* identifies the type of operation requested */ 8934 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0 8935 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_LEN 4 8936 /* enum: read the list of supported RX filter matches */ 8937 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1 8938 /* enum: read flags indicating restrictions on filter insertion for the calling 8939 * client 8940 */ 8941 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2 8942 /* enum: read properties relating to security rules (Medford-only; for use by 8943 * SolarSecure apps, not directly by drivers. See SF-114946-SW.) 8944 */ 8945 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SECURITY_RULE_INFO 0x3 8946 /* enum: read the list of supported RX filter matches for VXLAN/NVGRE 8947 * encapsulated frames, which follow a different match sequence to normal 8948 * frames (Medford only) 8949 */ 8950 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x4 8951 8952 /* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */ 8953 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8 8954 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252 8955 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num)) 8956 /* identifies the type of operation requested */ 8957 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0 8958 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_LEN 4 8959 /* Enum values, see field(s): */ 8960 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 8961 /* number of supported match types */ 8962 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4 8963 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_LEN 4 8964 /* array of supported match types (valid MATCH_FIELDS values for 8965 * MC_CMD_FILTER_OP) sorted in decreasing priority order 8966 */ 8967 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8 8968 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4 8969 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0 8970 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61 8971 8972 /* MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT msgresponse */ 8973 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_LEN 8 8974 /* identifies the type of operation requested */ 8975 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 0 8976 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_LEN 4 8977 /* Enum values, see field(s): */ 8978 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 8979 /* bitfield of filter insertion restrictions */ 8980 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4 8981 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_LEN 4 8982 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0 8983 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 1 8984 8985 /* MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT msgresponse: 8986 * GET_PARSER_DISP_INFO response format for OP_GET_SECURITY_RULE_INFO. 8987 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 8988 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 8989 * been used in any released code and may change during development. This note 8990 * will be removed once it is regarded as stable. 8991 */ 8992 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_LEN 36 8993 /* identifies the type of operation requested */ 8994 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_OP_OFST 0 8995 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_OP_LEN 4 8996 /* Enum values, see field(s): */ 8997 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 8998 /* a version number representing the set of rule lookups that are implemented 8999 * by the currently running firmware 9000 */ 9001 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_OFST 4 9002 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_LEN 4 9003 /* enum: implements lookup sequences described in SF-114946-SW draft C */ 9004 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_SF_114946_SW_C 0x0 9005 /* the number of nodes in the subnet map */ 9006 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_NODES_OFST 8 9007 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_NODES_LEN 4 9008 /* the number of entries in one subnet map node */ 9009 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_ENTRIES_PER_NODE_OFST 12 9010 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_ENTRIES_PER_NODE_LEN 4 9011 /* minimum valid value for a subnet ID in a subnet map leaf */ 9012 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MIN_OFST 16 9013 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MIN_LEN 4 9014 /* maximum valid value for a subnet ID in a subnet map leaf */ 9015 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MAX_OFST 20 9016 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MAX_LEN 4 9017 /* the number of entries in the local and remote port range maps */ 9018 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_TREE_NUM_ENTRIES_OFST 24 9019 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_TREE_NUM_ENTRIES_LEN 4 9020 /* minimum valid value for a portrange ID in a port range map leaf */ 9021 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MIN_OFST 28 9022 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MIN_LEN 4 9023 /* maximum valid value for a portrange ID in a port range map leaf */ 9024 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MAX_OFST 32 9025 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MAX_LEN 4 9026 9027 9028 /***********************************/ 9029 /* MC_CMD_PARSER_DISP_RW 9030 * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging. 9031 * Please note that this interface is only of use to debug tools which have 9032 * knowledge of firmware and hardware data structures; nothing here is intended 9033 * for use by normal driver code. Note that although this command is in the 9034 * Admin privilege group, in tamperproof adapters, only read operations are 9035 * permitted. 9036 */ 9037 #define MC_CMD_PARSER_DISP_RW 0xe5 9038 #undef MC_CMD_0xe5_PRIVILEGE_CTG 9039 9040 #define MC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9041 9042 /* MC_CMD_PARSER_DISP_RW_IN msgrequest */ 9043 #define MC_CMD_PARSER_DISP_RW_IN_LEN 32 9044 /* identifies the target of the operation */ 9045 #define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0 9046 #define MC_CMD_PARSER_DISP_RW_IN_TARGET_LEN 4 9047 /* enum: RX dispatcher CPU */ 9048 #define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0 9049 /* enum: TX dispatcher CPU */ 9050 #define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1 9051 /* enum: Lookup engine (with original metadata format). Deprecated; used only 9052 * by cmdclient as a fallback for very old Huntington firmware, and not 9053 * supported in firmware beyond v6.4.0.1005. Use LUE_VERSIONED_METADATA 9054 * instead. 9055 */ 9056 #define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2 9057 /* enum: Lookup engine (with requested metadata format) */ 9058 #define MC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA 0x3 9059 /* enum: RX0 dispatcher CPU (alias for RX_DICPU; Medford has 2 RX DICPUs) */ 9060 #define MC_CMD_PARSER_DISP_RW_IN_RX0_DICPU 0x0 9061 /* enum: RX1 dispatcher CPU (only valid for Medford) */ 9062 #define MC_CMD_PARSER_DISP_RW_IN_RX1_DICPU 0x4 9063 /* enum: Miscellaneous other state (only valid for Medford) */ 9064 #define MC_CMD_PARSER_DISP_RW_IN_MISC_STATE 0x5 9065 /* identifies the type of operation requested */ 9066 #define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4 9067 #define MC_CMD_PARSER_DISP_RW_IN_OP_LEN 4 9068 /* enum: Read a word of DICPU DMEM or a LUE entry */ 9069 #define MC_CMD_PARSER_DISP_RW_IN_READ 0x0 9070 /* enum: Write a word of DICPU DMEM or a LUE entry. Not permitted on 9071 * tamperproof adapters. 9072 */ 9073 #define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1 9074 /* enum: Read-modify-write a word of DICPU DMEM (not valid for LUE). Not 9075 * permitted on tamperproof adapters. 9076 */ 9077 #define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2 9078 /* data memory address (DICPU targets) or LUE index (LUE targets) */ 9079 #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8 9080 #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_LEN 4 9081 /* selector (for MISC_STATE target) */ 9082 #define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_OFST 8 9083 #define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_LEN 4 9084 /* enum: Port to datapath mapping */ 9085 #define MC_CMD_PARSER_DISP_RW_IN_PORT_DP_MAPPING 0x1 9086 /* value to write (for DMEM writes) */ 9087 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12 9088 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_LEN 4 9089 /* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 9090 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 12 9091 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_LEN 4 9092 /* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 9093 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 16 9094 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_LEN 4 9095 /* metadata format (for LUE reads using LUE_VERSIONED_METADATA) */ 9096 #define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_OFST 12 9097 #define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_LEN 4 9098 /* value to write (for LUE writes) */ 9099 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 12 9100 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 20 9101 9102 /* MC_CMD_PARSER_DISP_RW_OUT msgresponse */ 9103 #define MC_CMD_PARSER_DISP_RW_OUT_LEN 52 9104 /* value read (for DMEM reads) */ 9105 #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0 9106 #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_LEN 4 9107 /* value read (for LUE reads) */ 9108 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0 9109 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 20 9110 /* up to 8 32-bit words of additional soft state from the LUE manager (the 9111 * exact content is firmware-dependent and intended only for debug use) 9112 */ 9113 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20 9114 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32 9115 /* datapath(s) used for each port (for MISC_STATE PORT_DP_MAPPING selector) */ 9116 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_OFST 0 9117 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_LEN 4 9118 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_NUM 4 9119 #define MC_CMD_PARSER_DISP_RW_OUT_DP0 0x1 /* enum */ 9120 #define MC_CMD_PARSER_DISP_RW_OUT_DP1 0x2 /* enum */ 9121 9122 9123 /***********************************/ 9124 /* MC_CMD_GET_PF_COUNT 9125 * Get number of PFs on the device. 9126 */ 9127 #define MC_CMD_GET_PF_COUNT 0xb6 9128 #undef MC_CMD_0xb6_PRIVILEGE_CTG 9129 9130 #define MC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9131 9132 /* MC_CMD_GET_PF_COUNT_IN msgrequest */ 9133 #define MC_CMD_GET_PF_COUNT_IN_LEN 0 9134 9135 /* MC_CMD_GET_PF_COUNT_OUT msgresponse */ 9136 #define MC_CMD_GET_PF_COUNT_OUT_LEN 1 9137 /* Identifies the number of PFs on the device. */ 9138 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0 9139 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1 9140 9141 9142 /***********************************/ 9143 /* MC_CMD_SET_PF_COUNT 9144 * Set number of PFs on the device. 9145 */ 9146 #define MC_CMD_SET_PF_COUNT 0xb7 9147 9148 /* MC_CMD_SET_PF_COUNT_IN msgrequest */ 9149 #define MC_CMD_SET_PF_COUNT_IN_LEN 4 9150 /* New number of PFs on the device. */ 9151 #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0 9152 #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_LEN 4 9153 9154 /* MC_CMD_SET_PF_COUNT_OUT msgresponse */ 9155 #define MC_CMD_SET_PF_COUNT_OUT_LEN 0 9156 9157 9158 /***********************************/ 9159 /* MC_CMD_GET_PORT_ASSIGNMENT 9160 * Get port assignment for current PCI function. 9161 */ 9162 #define MC_CMD_GET_PORT_ASSIGNMENT 0xb8 9163 #undef MC_CMD_0xb8_PRIVILEGE_CTG 9164 9165 #define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9166 9167 /* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */ 9168 #define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0 9169 9170 /* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */ 9171 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4 9172 /* Identifies the port assignment for this function. */ 9173 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0 9174 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_LEN 4 9175 9176 9177 /***********************************/ 9178 /* MC_CMD_SET_PORT_ASSIGNMENT 9179 * Set port assignment for current PCI function. 9180 */ 9181 #define MC_CMD_SET_PORT_ASSIGNMENT 0xb9 9182 #undef MC_CMD_0xb9_PRIVILEGE_CTG 9183 9184 #define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9185 9186 /* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */ 9187 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4 9188 /* Identifies the port assignment for this function. */ 9189 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0 9190 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_LEN 4 9191 9192 /* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */ 9193 #define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0 9194 9195 9196 /***********************************/ 9197 /* MC_CMD_ALLOC_VIS 9198 * Allocate VIs for current PCI function. 9199 */ 9200 #define MC_CMD_ALLOC_VIS 0x8b 9201 #undef MC_CMD_0x8b_PRIVILEGE_CTG 9202 9203 #define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9204 9205 /* MC_CMD_ALLOC_VIS_IN msgrequest */ 9206 #define MC_CMD_ALLOC_VIS_IN_LEN 8 9207 /* The minimum number of VIs that is acceptable */ 9208 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0 9209 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_LEN 4 9210 /* The maximum number of VIs that would be useful */ 9211 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4 9212 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_LEN 4 9213 9214 /* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request. 9215 * Use extended version in new code. 9216 */ 9217 #define MC_CMD_ALLOC_VIS_OUT_LEN 8 9218 /* The number of VIs allocated on this function */ 9219 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0 9220 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_LEN 4 9221 /* The base absolute VI number allocated to this function. Required to 9222 * correctly interpret wakeup events. 9223 */ 9224 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4 9225 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_LEN 4 9226 9227 /* MC_CMD_ALLOC_VIS_EXT_OUT msgresponse */ 9228 #define MC_CMD_ALLOC_VIS_EXT_OUT_LEN 12 9229 /* The number of VIs allocated on this function */ 9230 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0 9231 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_LEN 4 9232 /* The base absolute VI number allocated to this function. Required to 9233 * correctly interpret wakeup events. 9234 */ 9235 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4 9236 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_LEN 4 9237 /* Function's port vi_shift value (always 0 on Huntington) */ 9238 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_OFST 8 9239 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_LEN 4 9240 9241 9242 /***********************************/ 9243 /* MC_CMD_FREE_VIS 9244 * Free VIs for current PCI function. Any linked PIO buffers will be unlinked, 9245 * but not freed. 9246 */ 9247 #define MC_CMD_FREE_VIS 0x8c 9248 #undef MC_CMD_0x8c_PRIVILEGE_CTG 9249 9250 #define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9251 9252 /* MC_CMD_FREE_VIS_IN msgrequest */ 9253 #define MC_CMD_FREE_VIS_IN_LEN 0 9254 9255 /* MC_CMD_FREE_VIS_OUT msgresponse */ 9256 #define MC_CMD_FREE_VIS_OUT_LEN 0 9257 9258 9259 /***********************************/ 9260 /* MC_CMD_GET_SRIOV_CFG 9261 * Get SRIOV config for this PF. 9262 */ 9263 #define MC_CMD_GET_SRIOV_CFG 0xba 9264 #undef MC_CMD_0xba_PRIVILEGE_CTG 9265 9266 #define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9267 9268 /* MC_CMD_GET_SRIOV_CFG_IN msgrequest */ 9269 #define MC_CMD_GET_SRIOV_CFG_IN_LEN 0 9270 9271 /* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */ 9272 #define MC_CMD_GET_SRIOV_CFG_OUT_LEN 20 9273 /* Number of VFs currently enabled. */ 9274 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0 9275 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_LEN 4 9276 /* Max number of VFs before sriov stride and offset may need to be changed. */ 9277 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4 9278 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_LEN 4 9279 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8 9280 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_LEN 4 9281 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0 9282 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1 9283 /* RID offset of first VF from PF. */ 9284 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12 9285 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_LEN 4 9286 /* RID offset of each subsequent VF from the previous. */ 9287 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16 9288 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_LEN 4 9289 9290 9291 /***********************************/ 9292 /* MC_CMD_SET_SRIOV_CFG 9293 * Set SRIOV config for this PF. 9294 */ 9295 #define MC_CMD_SET_SRIOV_CFG 0xbb 9296 #undef MC_CMD_0xbb_PRIVILEGE_CTG 9297 9298 #define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9299 9300 /* MC_CMD_SET_SRIOV_CFG_IN msgrequest */ 9301 #define MC_CMD_SET_SRIOV_CFG_IN_LEN 20 9302 /* Number of VFs currently enabled. */ 9303 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0 9304 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_LEN 4 9305 /* Max number of VFs before sriov stride and offset may need to be changed. */ 9306 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4 9307 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_LEN 4 9308 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8 9309 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_LEN 4 9310 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0 9311 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1 9312 /* RID offset of first VF from PF, or 0 for no change, or 9313 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset. 9314 */ 9315 #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12 9316 #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_LEN 4 9317 /* RID offset of each subsequent VF from the previous, 0 for no change, or 9318 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride. 9319 */ 9320 #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16 9321 #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_LEN 4 9322 9323 /* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */ 9324 #define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0 9325 9326 9327 /***********************************/ 9328 /* MC_CMD_GET_VI_ALLOC_INFO 9329 * Get information about number of VI's and base VI number allocated to this 9330 * function. 9331 */ 9332 #define MC_CMD_GET_VI_ALLOC_INFO 0x8d 9333 #undef MC_CMD_0x8d_PRIVILEGE_CTG 9334 9335 #define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9336 9337 /* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */ 9338 #define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0 9339 9340 /* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */ 9341 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 12 9342 /* The number of VIs allocated on this function */ 9343 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0 9344 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_LEN 4 9345 /* The base absolute VI number allocated to this function. Required to 9346 * correctly interpret wakeup events. 9347 */ 9348 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4 9349 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_LEN 4 9350 /* Function's port vi_shift value (always 0 on Huntington) */ 9351 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_OFST 8 9352 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_LEN 4 9353 9354 9355 /***********************************/ 9356 /* MC_CMD_DUMP_VI_STATE 9357 * For CmdClient use. Dump pertinent information on a specific absolute VI. 9358 */ 9359 #define MC_CMD_DUMP_VI_STATE 0x8e 9360 #undef MC_CMD_0x8e_PRIVILEGE_CTG 9361 9362 #define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9363 9364 /* MC_CMD_DUMP_VI_STATE_IN msgrequest */ 9365 #define MC_CMD_DUMP_VI_STATE_IN_LEN 4 9366 /* The VI number to query. */ 9367 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0 9368 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_LEN 4 9369 9370 /* MC_CMD_DUMP_VI_STATE_OUT msgresponse */ 9371 #define MC_CMD_DUMP_VI_STATE_OUT_LEN 96 9372 /* The PF part of the function owning this VI. */ 9373 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0 9374 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2 9375 /* The VF part of the function owning this VI. */ 9376 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2 9377 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2 9378 /* Base of VIs allocated to this function. */ 9379 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4 9380 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2 9381 /* Count of VIs allocated to the owner function. */ 9382 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6 9383 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2 9384 /* Base interrupt vector allocated to this function. */ 9385 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8 9386 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2 9387 /* Number of interrupt vectors allocated to this function. */ 9388 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10 9389 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2 9390 /* Raw evq ptr table data. */ 9391 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12 9392 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8 9393 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12 9394 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16 9395 /* Raw evq timer table data. */ 9396 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20 9397 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8 9398 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20 9399 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24 9400 /* Combined metadata field. */ 9401 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28 9402 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_LEN 4 9403 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0 9404 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16 9405 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16 9406 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8 9407 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24 9408 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8 9409 /* TXDPCPU raw table data for queue. */ 9410 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32 9411 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8 9412 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32 9413 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36 9414 /* TXDPCPU raw table data for queue. */ 9415 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40 9416 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8 9417 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40 9418 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44 9419 /* TXDPCPU raw table data for queue. */ 9420 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48 9421 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8 9422 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48 9423 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52 9424 /* Combined metadata field. */ 9425 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56 9426 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8 9427 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56 9428 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60 9429 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0 9430 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16 9431 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16 9432 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8 9433 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24 9434 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8 9435 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32 9436 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8 9437 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40 9438 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24 9439 /* RXDPCPU raw table data for queue. */ 9440 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64 9441 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8 9442 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64 9443 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68 9444 /* RXDPCPU raw table data for queue. */ 9445 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72 9446 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8 9447 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72 9448 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76 9449 /* Reserved, currently 0. */ 9450 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80 9451 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8 9452 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80 9453 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84 9454 /* Combined metadata field. */ 9455 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88 9456 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8 9457 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88 9458 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92 9459 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0 9460 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16 9461 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16 9462 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8 9463 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24 9464 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8 9465 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32 9466 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8 9467 9468 9469 /***********************************/ 9470 /* MC_CMD_ALLOC_PIOBUF 9471 * Allocate a push I/O buffer for later use with a tx queue. 9472 */ 9473 #define MC_CMD_ALLOC_PIOBUF 0x8f 9474 #undef MC_CMD_0x8f_PRIVILEGE_CTG 9475 9476 #define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 9477 9478 /* MC_CMD_ALLOC_PIOBUF_IN msgrequest */ 9479 #define MC_CMD_ALLOC_PIOBUF_IN_LEN 0 9480 9481 /* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */ 9482 #define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4 9483 /* Handle for allocated push I/O buffer. */ 9484 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0 9485 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_LEN 4 9486 9487 9488 /***********************************/ 9489 /* MC_CMD_FREE_PIOBUF 9490 * Free a push I/O buffer. 9491 */ 9492 #define MC_CMD_FREE_PIOBUF 0x90 9493 #undef MC_CMD_0x90_PRIVILEGE_CTG 9494 9495 #define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 9496 9497 /* MC_CMD_FREE_PIOBUF_IN msgrequest */ 9498 #define MC_CMD_FREE_PIOBUF_IN_LEN 4 9499 /* Handle for allocated push I/O buffer. */ 9500 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 9501 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_LEN 4 9502 9503 /* MC_CMD_FREE_PIOBUF_OUT msgresponse */ 9504 #define MC_CMD_FREE_PIOBUF_OUT_LEN 0 9505 9506 9507 /***********************************/ 9508 /* MC_CMD_GET_VI_TLP_PROCESSING 9509 * Get TLP steering and ordering information for a VI. 9510 */ 9511 #define MC_CMD_GET_VI_TLP_PROCESSING 0xb0 9512 #undef MC_CMD_0xb0_PRIVILEGE_CTG 9513 9514 #define MC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9515 9516 /* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */ 9517 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4 9518 /* VI number to get information for. */ 9519 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 9520 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4 9521 9522 /* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */ 9523 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4 9524 /* Transaction processing steering hint 1 for use with the Rx Queue. */ 9525 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0 9526 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1 9527 /* Transaction processing steering hint 2 for use with the Ev Queue. */ 9528 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1 9529 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1 9530 /* Use Relaxed ordering model for TLPs on this VI. */ 9531 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16 9532 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1 9533 /* Use ID based ordering for TLPs on this VI. */ 9534 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17 9535 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1 9536 /* Set no snoop bit for TLPs on this VI. */ 9537 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_LBN 18 9538 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1 9539 /* Enable TPH for TLPs on this VI. */ 9540 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19 9541 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1 9542 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0 9543 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_LEN 4 9544 9545 9546 /***********************************/ 9547 /* MC_CMD_SET_VI_TLP_PROCESSING 9548 * Set TLP steering and ordering information for a VI. 9549 */ 9550 #define MC_CMD_SET_VI_TLP_PROCESSING 0xb1 9551 #undef MC_CMD_0xb1_PRIVILEGE_CTG 9552 9553 #define MC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9554 9555 /* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */ 9556 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8 9557 /* VI number to set information for. */ 9558 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 9559 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4 9560 /* Transaction processing steering hint 1 for use with the Rx Queue. */ 9561 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4 9562 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1 9563 /* Transaction processing steering hint 2 for use with the Ev Queue. */ 9564 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_OFST 5 9565 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1 9566 /* Use Relaxed ordering model for TLPs on this VI. */ 9567 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48 9568 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1 9569 /* Use ID based ordering for TLPs on this VI. */ 9570 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49 9571 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1 9572 /* Set the no snoop bit for TLPs on this VI. */ 9573 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_LBN 50 9574 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1 9575 /* Enable TPH for TLPs on this VI. */ 9576 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51 9577 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1 9578 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4 9579 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_LEN 4 9580 9581 /* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */ 9582 #define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0 9583 9584 9585 /***********************************/ 9586 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS 9587 * Get global PCIe steering and transaction processing configuration. 9588 */ 9589 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc 9590 #undef MC_CMD_0xbc_PRIVILEGE_CTG 9591 9592 #define MC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9593 9594 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 9595 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4 9596 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 9597 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4 9598 /* enum: MISC. */ 9599 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0 9600 /* enum: IDO. */ 9601 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1 9602 /* enum: RO. */ 9603 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2 9604 /* enum: TPH Type. */ 9605 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3 9606 9607 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 9608 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8 9609 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0 9610 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_LEN 4 9611 /* Enum values, see field(s): */ 9612 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 9613 /* Amalgamated TLP info word. */ 9614 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4 9615 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_LEN 4 9616 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0 9617 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1 9618 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1 9619 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31 9620 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0 9621 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1 9622 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1 9623 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1 9624 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2 9625 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1 9626 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3 9627 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1 9628 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4 9629 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28 9630 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0 9631 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1 9632 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1 9633 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1 9634 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2 9635 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1 9636 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3 9637 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29 9638 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0 9639 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 9640 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2 9641 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2 9642 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4 9643 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2 9644 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6 9645 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2 9646 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8 9647 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2 9648 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9 9649 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23 9650 9651 9652 /***********************************/ 9653 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS 9654 * Set global PCIe steering and transaction processing configuration. 9655 */ 9656 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd 9657 #undef MC_CMD_0xbd_PRIVILEGE_CTG 9658 9659 #define MC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9660 9661 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 9662 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 8 9663 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 9664 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4 9665 /* Enum values, see field(s): */ 9666 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 9667 /* Amalgamated TLP info word. */ 9668 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4 9669 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_LEN 4 9670 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0 9671 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1 9672 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0 9673 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1 9674 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1 9675 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1 9676 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2 9677 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1 9678 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3 9679 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1 9680 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0 9681 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1 9682 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1 9683 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1 9684 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2 9685 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1 9686 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0 9687 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 9688 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2 9689 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2 9690 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4 9691 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2 9692 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6 9693 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2 9694 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8 9695 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2 9696 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10 9697 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22 9698 9699 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 9700 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0 9701 9702 9703 /***********************************/ 9704 /* MC_CMD_SATELLITE_DOWNLOAD 9705 * Download a new set of images to the satellite CPUs from the host. 9706 */ 9707 #define MC_CMD_SATELLITE_DOWNLOAD 0x91 9708 #undef MC_CMD_0x91_PRIVILEGE_CTG 9709 9710 #define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 9711 9712 /* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs 9713 * are subtle, and so downloads must proceed in a number of phases. 9714 * 9715 * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0. 9716 * 9717 * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download 9718 * may consist of multiple chunks. The final chunk (with CHUNK_ID_LAST) should 9719 * be a checksum (a simple 32-bit sum) of the transferred data. An individual 9720 * download may be aborted using CHUNK_ID_ABORT. 9721 * 9722 * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15), 9723 * similar to PHASE_IMEMS. 9724 * 9725 * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0. 9726 * 9727 * After any error (a requested abort is not considered to be an error) the 9728 * sequence must be restarted from PHASE_RESET. 9729 */ 9730 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 20 9731 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252 9732 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num)) 9733 /* Download phase. (Note: the IDLE phase is used internally and is never valid 9734 * in a command from the host.) 9735 */ 9736 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0 9737 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_LEN 4 9738 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */ 9739 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */ 9740 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */ 9741 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */ 9742 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */ 9743 /* Target for download. (These match the blob numbers defined in 9744 * mc_flash_layout.h.) 9745 */ 9746 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4 9747 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_LEN 4 9748 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9749 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0 9750 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9751 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1 9752 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9753 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2 9754 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9755 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3 9756 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9757 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4 9758 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9759 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5 9760 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9761 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6 9762 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9763 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7 9764 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9765 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8 9766 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9767 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9 9768 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9769 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa 9770 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9771 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb 9772 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 9773 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc 9774 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 9775 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd 9776 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 9777 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe 9778 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 9779 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf 9780 /* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */ 9781 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff 9782 /* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */ 9783 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8 9784 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LEN 4 9785 /* enum: Last chunk, containing checksum rather than data */ 9786 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff 9787 /* enum: Abort download of this item */ 9788 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe 9789 /* Length of this chunk in bytes */ 9790 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12 9791 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_LEN 4 9792 /* Data for this chunk */ 9793 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 16 9794 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4 9795 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1 9796 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 59 9797 9798 /* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */ 9799 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8 9800 /* Same as MC_CMD_ERR field, but included as 0 in success cases */ 9801 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0 9802 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_LEN 4 9803 /* Extra status information */ 9804 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4 9805 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_LEN 4 9806 /* enum: Code download OK, completed. */ 9807 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0 9808 /* enum: Code download aborted as requested. */ 9809 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1 9810 /* enum: Code download OK so far, send next chunk. */ 9811 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2 9812 /* enum: Download phases out of sequence */ 9813 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100 9814 /* enum: Bad target for this phase */ 9815 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101 9816 /* enum: Chunk ID out of sequence */ 9817 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200 9818 /* enum: Chunk length zero or too large */ 9819 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201 9820 /* enum: Checksum was incorrect */ 9821 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300 9822 9823 9824 /***********************************/ 9825 /* MC_CMD_GET_CAPABILITIES 9826 * Get device capabilities. 9827 * 9828 * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to 9829 * reference inherent device capabilities as opposed to current NVRAM config. 9830 */ 9831 #define MC_CMD_GET_CAPABILITIES 0xbe 9832 #undef MC_CMD_0xbe_PRIVILEGE_CTG 9833 9834 #define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9835 9836 /* MC_CMD_GET_CAPABILITIES_IN msgrequest */ 9837 #define MC_CMD_GET_CAPABILITIES_IN_LEN 0 9838 9839 /* MC_CMD_GET_CAPABILITIES_OUT msgresponse */ 9840 #define MC_CMD_GET_CAPABILITIES_OUT_LEN 20 9841 /* First word of flags. */ 9842 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0 9843 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_LEN 4 9844 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_LBN 3 9845 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_WIDTH 1 9846 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4 9847 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_WIDTH 1 9848 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN 5 9849 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_WIDTH 1 9850 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 9851 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 9852 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_LBN 7 9853 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 9854 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_LBN 8 9855 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 9856 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_LBN 9 9857 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_WIDTH 1 9858 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 9859 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 9860 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 9861 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 9862 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 9863 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 9864 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN 13 9865 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 9866 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_LBN 14 9867 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_WIDTH 1 9868 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 9869 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 9870 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN 16 9871 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_WIDTH 1 9872 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_LBN 17 9873 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_WIDTH 1 9874 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN 18 9875 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_WIDTH 1 9876 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19 9877 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1 9878 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20 9879 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1 9880 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21 9881 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1 9882 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22 9883 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1 9884 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23 9885 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1 9886 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24 9887 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1 9888 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25 9889 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1 9890 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26 9891 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1 9892 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27 9893 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 9894 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_LBN 28 9895 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_WIDTH 1 9896 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 9897 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 9898 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN 30 9899 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 1 9900 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN 31 9901 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_WIDTH 1 9902 /* RxDPCPU firmware id. */ 9903 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4 9904 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2 9905 /* enum: Standard RXDP firmware */ 9906 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0 9907 /* enum: Low latency RXDP firmware */ 9908 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1 9909 /* enum: Packed stream RXDP firmware */ 9910 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2 9911 /* enum: Rules engine RXDP firmware */ 9912 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE 0x5 9913 /* enum: DPDK RXDP firmware */ 9914 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK 0x6 9915 /* enum: BIST RXDP firmware */ 9916 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a 9917 /* enum: RXDP Test firmware image 1 */ 9918 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 9919 /* enum: RXDP Test firmware image 2 */ 9920 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 9921 /* enum: RXDP Test firmware image 3 */ 9922 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 9923 /* enum: RXDP Test firmware image 4 */ 9924 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 9925 /* enum: RXDP Test firmware image 5 */ 9926 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105 9927 /* enum: RXDP Test firmware image 6 */ 9928 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 9929 /* enum: RXDP Test firmware image 7 */ 9930 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 9931 /* enum: RXDP Test firmware image 8 */ 9932 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 9933 /* enum: RXDP Test firmware image 9 */ 9934 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 9935 /* enum: RXDP Test firmware image 10 */ 9936 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_SLOW 0x10c 9937 /* TxDPCPU firmware id. */ 9938 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6 9939 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2 9940 /* enum: Standard TXDP firmware */ 9941 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0 9942 /* enum: Low latency TXDP firmware */ 9943 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1 9944 /* enum: High packet rate TXDP firmware */ 9945 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3 9946 /* enum: Rules engine TXDP firmware */ 9947 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_RULES_ENGINE 0x5 9948 /* enum: DPDK TXDP firmware */ 9949 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_DPDK 0x6 9950 /* enum: BIST TXDP firmware */ 9951 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d 9952 /* enum: TXDP Test firmware image 1 */ 9953 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 9954 /* enum: TXDP Test firmware image 2 */ 9955 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 9956 /* enum: TXDP CSR bus test firmware */ 9957 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR 0x103 9958 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8 9959 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2 9960 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0 9961 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12 9962 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12 9963 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 9964 /* enum: reserved value - do not use (may indicate alternative interpretation 9965 * of REV field in future) 9966 */ 9967 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x0 9968 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 9969 * development only) 9970 */ 9971 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 9972 /* enum: RX PD firmware with approximately Siena-compatible behaviour 9973 * (Huntington development only) 9974 */ 9975 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 9976 /* enum: Full featured RX PD production firmware */ 9977 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 9978 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 9979 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3 9980 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 9981 * (Huntington development only) 9982 */ 9983 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 9984 /* enum: Low latency RX PD production firmware */ 9985 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 9986 /* enum: Packed stream RX PD production firmware */ 9987 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 9988 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 9989 * tests (Medford development only) 9990 */ 9991 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 9992 /* enum: Rules engine RX PD production firmware */ 9993 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 9994 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 9995 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_L3XUDP 0x9 9996 /* enum: DPDK RX PD production firmware */ 9997 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_DPDK 0xa 9998 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 9999 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10000 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 10001 * encapsulations (Medford development only) 10002 */ 10003 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 10004 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10 10005 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2 10006 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0 10007 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12 10008 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12 10009 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 10010 /* enum: reserved value - do not use (may indicate alternative interpretation 10011 * of REV field in future) 10012 */ 10013 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x0 10014 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 10015 * development only) 10016 */ 10017 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 10018 /* enum: TX PD firmware with approximately Siena-compatible behaviour 10019 * (Huntington development only) 10020 */ 10021 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 10022 /* enum: Full featured TX PD production firmware */ 10023 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 10024 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 10025 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3 10026 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 10027 * (Huntington development only) 10028 */ 10029 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10030 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 10031 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 10032 * tests (Medford development only) 10033 */ 10034 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 10035 /* enum: Rules engine TX PD production firmware */ 10036 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 10037 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 10038 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_L3XUDP 0x9 10039 /* enum: DPDK TX PD production firmware */ 10040 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_DPDK 0xa 10041 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10042 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10043 /* Hardware capabilities of NIC */ 10044 #define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12 10045 #define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_LEN 4 10046 /* Licensed capabilities */ 10047 #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16 10048 #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_LEN 4 10049 10050 /* MC_CMD_GET_CAPABILITIES_V2_IN msgrequest */ 10051 #define MC_CMD_GET_CAPABILITIES_V2_IN_LEN 0 10052 10053 /* MC_CMD_GET_CAPABILITIES_V2_OUT msgresponse */ 10054 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LEN 72 10055 /* First word of flags. */ 10056 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0 10057 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_LEN 4 10058 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_LBN 3 10059 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_WIDTH 1 10060 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4 10061 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_WIDTH 1 10062 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_LBN 5 10063 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_WIDTH 1 10064 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 10065 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 10066 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_LBN 7 10067 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 10068 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_LBN 8 10069 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 10070 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_LBN 9 10071 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_WIDTH 1 10072 #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 10073 #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 10074 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 10075 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 10076 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 10077 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 10078 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_LBN 13 10079 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 10080 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_LBN 14 10081 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_WIDTH 1 10082 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 10083 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 10084 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_LBN 16 10085 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_WIDTH 1 10086 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_LBN 17 10087 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_WIDTH 1 10088 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_LBN 18 10089 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_WIDTH 1 10090 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_LBN 19 10091 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_WIDTH 1 10092 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_LBN 20 10093 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_WIDTH 1 10094 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_LBN 21 10095 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_WIDTH 1 10096 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_LBN 22 10097 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_WIDTH 1 10098 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_LBN 23 10099 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_WIDTH 1 10100 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_LBN 24 10101 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_WIDTH 1 10102 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_LBN 25 10103 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_WIDTH 1 10104 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_LBN 26 10105 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_WIDTH 1 10106 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_LBN 27 10107 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 10108 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_LBN 28 10109 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_WIDTH 1 10110 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 10111 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 10112 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_LBN 30 10113 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_WIDTH 1 10114 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_LBN 31 10115 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_WIDTH 1 10116 /* RxDPCPU firmware id. */ 10117 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 4 10118 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_LEN 2 10119 /* enum: Standard RXDP firmware */ 10120 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x0 10121 /* enum: Low latency RXDP firmware */ 10122 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x1 10123 /* enum: Packed stream RXDP firmware */ 10124 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2 10125 /* enum: Rules engine RXDP firmware */ 10126 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_RULES_ENGINE 0x5 10127 /* enum: DPDK RXDP firmware */ 10128 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_DPDK 0x6 10129 /* enum: BIST RXDP firmware */ 10130 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a 10131 /* enum: RXDP Test firmware image 1 */ 10132 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 10133 /* enum: RXDP Test firmware image 2 */ 10134 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 10135 /* enum: RXDP Test firmware image 3 */ 10136 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 10137 /* enum: RXDP Test firmware image 4 */ 10138 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 10139 /* enum: RXDP Test firmware image 5 */ 10140 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x105 10141 /* enum: RXDP Test firmware image 6 */ 10142 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 10143 /* enum: RXDP Test firmware image 7 */ 10144 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 10145 /* enum: RXDP Test firmware image 8 */ 10146 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 10147 /* enum: RXDP Test firmware image 9 */ 10148 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 10149 /* enum: RXDP Test firmware image 10 */ 10150 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_SLOW 0x10c 10151 /* TxDPCPU firmware id. */ 10152 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_OFST 6 10153 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_LEN 2 10154 /* enum: Standard TXDP firmware */ 10155 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x0 10156 /* enum: Low latency TXDP firmware */ 10157 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x1 10158 /* enum: High packet rate TXDP firmware */ 10159 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3 10160 /* enum: Rules engine TXDP firmware */ 10161 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_RULES_ENGINE 0x5 10162 /* enum: DPDK TXDP firmware */ 10163 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_DPDK 0x6 10164 /* enum: BIST TXDP firmware */ 10165 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d 10166 /* enum: TXDP Test firmware image 1 */ 10167 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 10168 /* enum: TXDP Test firmware image 2 */ 10169 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 10170 /* enum: TXDP CSR bus test firmware */ 10171 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR 0x103 10172 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_OFST 8 10173 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_LEN 2 10174 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0 10175 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_WIDTH 12 10176 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_LBN 12 10177 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 10178 /* enum: reserved value - do not use (may indicate alternative interpretation 10179 * of REV field in future) 10180 */ 10181 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x0 10182 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 10183 * development only) 10184 */ 10185 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 10186 /* enum: RX PD firmware with approximately Siena-compatible behaviour 10187 * (Huntington development only) 10188 */ 10189 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 10190 /* enum: Full featured RX PD production firmware */ 10191 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 10192 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 10193 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x3 10194 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 10195 * (Huntington development only) 10196 */ 10197 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10198 /* enum: Low latency RX PD production firmware */ 10199 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 10200 /* enum: Packed stream RX PD production firmware */ 10201 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 10202 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 10203 * tests (Medford development only) 10204 */ 10205 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 10206 /* enum: Rules engine RX PD production firmware */ 10207 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 10208 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 10209 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_L3XUDP 0x9 10210 /* enum: DPDK RX PD production firmware */ 10211 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_DPDK 0xa 10212 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10213 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10214 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 10215 * encapsulations (Medford development only) 10216 */ 10217 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 10218 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_OFST 10 10219 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_LEN 2 10220 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0 10221 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_WIDTH 12 10222 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_LBN 12 10223 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 10224 /* enum: reserved value - do not use (may indicate alternative interpretation 10225 * of REV field in future) 10226 */ 10227 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x0 10228 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 10229 * development only) 10230 */ 10231 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 10232 /* enum: TX PD firmware with approximately Siena-compatible behaviour 10233 * (Huntington development only) 10234 */ 10235 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 10236 /* enum: Full featured TX PD production firmware */ 10237 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 10238 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 10239 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x3 10240 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 10241 * (Huntington development only) 10242 */ 10243 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10244 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 10245 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 10246 * tests (Medford development only) 10247 */ 10248 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 10249 /* enum: Rules engine TX PD production firmware */ 10250 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 10251 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 10252 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_L3XUDP 0x9 10253 /* enum: DPDK TX PD production firmware */ 10254 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_DPDK 0xa 10255 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10256 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10257 /* Hardware capabilities of NIC */ 10258 #define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_OFST 12 10259 #define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_LEN 4 10260 /* Licensed capabilities */ 10261 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_OFST 16 10262 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_LEN 4 10263 /* Second word of flags. Not present on older firmware (check the length). */ 10264 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_OFST 20 10265 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_LEN 4 10266 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0 10267 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_WIDTH 1 10268 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_LBN 1 10269 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_WIDTH 1 10270 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_LBN 2 10271 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_WIDTH 1 10272 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_LBN 3 10273 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_WIDTH 1 10274 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_LBN 4 10275 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_WIDTH 1 10276 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_LBN 5 10277 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 10278 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 10279 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 10280 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN 7 10281 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_WIDTH 1 10282 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_LBN 8 10283 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 10284 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_LBN 9 10285 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_WIDTH 1 10286 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_LBN 10 10287 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_WIDTH 1 10288 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_LBN 11 10289 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_WIDTH 1 10290 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 10291 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 10292 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_LBN 13 10293 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_WIDTH 1 10294 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_LBN 14 10295 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_WIDTH 1 10296 #define MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_LBN 15 10297 #define MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_WIDTH 1 10298 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_LBN 16 10299 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_WIDTH 1 10300 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_LBN 17 10301 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_WIDTH 1 10302 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18 10303 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1 10304 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_LBN 19 10305 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_WIDTH 1 10306 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_LBN 20 10307 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_WIDTH 1 10308 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21 10309 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1 10310 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21 10311 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1 10312 #define MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_LBN 22 10313 #define MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_WIDTH 1 10314 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23 10315 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1 10316 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_LBN 24 10317 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_WIDTH 1 10318 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_LBN 25 10319 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_WIDTH 1 10320 /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present 10321 * on older firmware (check the length). 10322 */ 10323 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 10324 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 10325 /* One byte per PF containing the number of the external port assigned to this 10326 * PF, indexed by PF number. Special values indicate that a PF is either not 10327 * present or not assigned. 10328 */ 10329 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 10330 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 10331 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 10332 /* enum: The caller is not permitted to access information on this PF. */ 10333 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff 10334 /* enum: PF does not exist. */ 10335 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe 10336 /* enum: PF does exist but is not assigned to any external port. */ 10337 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_ASSIGNED 0xfd 10338 /* enum: This value indicates that PF is assigned, but it cannot be expressed 10339 * in this field. It is intended for a possible future situation where a more 10340 * complex scheme of PFs to ports mapping is being used. The future driver 10341 * should look for a new field supporting the new scheme. The current/old 10342 * driver should treat this value as PF_NOT_ASSIGNED. 10343 */ 10344 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 10345 /* One byte per PF containing the number of its VFs, indexed by PF number. A 10346 * special value indicates that a PF is not present. 10347 */ 10348 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_OFST 42 10349 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_LEN 1 10350 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_NUM 16 10351 /* enum: The caller is not permitted to access information on this PF. */ 10352 /* MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */ 10353 /* enum: PF does not exist. */ 10354 /* MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */ 10355 /* Number of VIs available for each external port */ 10356 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_OFST 58 10357 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_LEN 2 10358 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_NUM 4 10359 /* Size of RX descriptor cache expressed as binary logarithm The actual size 10360 * equals (2 ^ RX_DESC_CACHE_SIZE) 10361 */ 10362 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_OFST 66 10363 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_LEN 1 10364 /* Size of TX descriptor cache expressed as binary logarithm The actual size 10365 * equals (2 ^ TX_DESC_CACHE_SIZE) 10366 */ 10367 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_OFST 67 10368 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_LEN 1 10369 /* Total number of available PIO buffers */ 10370 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_OFST 68 10371 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_LEN 2 10372 /* Size of a single PIO buffer */ 10373 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_OFST 70 10374 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_LEN 2 10375 10376 /* MC_CMD_GET_CAPABILITIES_V3_OUT msgresponse */ 10377 #define MC_CMD_GET_CAPABILITIES_V3_OUT_LEN 76 10378 /* First word of flags. */ 10379 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_OFST 0 10380 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_LEN 4 10381 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_LBN 3 10382 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_WIDTH 1 10383 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_LBN 4 10384 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_WIDTH 1 10385 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_LBN 5 10386 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_WIDTH 1 10387 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 10388 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 10389 #define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_LBN 7 10390 #define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 10391 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_LBN 8 10392 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 10393 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_LBN 9 10394 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_WIDTH 1 10395 #define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 10396 #define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 10397 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 10398 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 10399 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 10400 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 10401 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_LBN 13 10402 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 10403 #define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_LBN 14 10404 #define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_WIDTH 1 10405 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 10406 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 10407 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_LBN 16 10408 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_WIDTH 1 10409 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_LBN 17 10410 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_WIDTH 1 10411 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_LBN 18 10412 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_WIDTH 1 10413 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_LBN 19 10414 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_WIDTH 1 10415 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_LBN 20 10416 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_WIDTH 1 10417 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_LBN 21 10418 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_WIDTH 1 10419 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_LBN 22 10420 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_WIDTH 1 10421 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_LBN 23 10422 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_WIDTH 1 10423 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_LBN 24 10424 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_WIDTH 1 10425 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_LBN 25 10426 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_WIDTH 1 10427 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_LBN 26 10428 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_WIDTH 1 10429 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_LBN 27 10430 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 10431 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_LBN 28 10432 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_WIDTH 1 10433 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 10434 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 10435 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_LBN 30 10436 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_WIDTH 1 10437 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_LBN 31 10438 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_WIDTH 1 10439 /* RxDPCPU firmware id. */ 10440 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_OFST 4 10441 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_LEN 2 10442 /* enum: Standard RXDP firmware */ 10443 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP 0x0 10444 /* enum: Low latency RXDP firmware */ 10445 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_LOW_LATENCY 0x1 10446 /* enum: Packed stream RXDP firmware */ 10447 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_PACKED_STREAM 0x2 10448 /* enum: Rules engine RXDP firmware */ 10449 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_RULES_ENGINE 0x5 10450 /* enum: DPDK RXDP firmware */ 10451 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_DPDK 0x6 10452 /* enum: BIST RXDP firmware */ 10453 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_BIST 0x10a 10454 /* enum: RXDP Test firmware image 1 */ 10455 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 10456 /* enum: RXDP Test firmware image 2 */ 10457 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 10458 /* enum: RXDP Test firmware image 3 */ 10459 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 10460 /* enum: RXDP Test firmware image 4 */ 10461 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 10462 /* enum: RXDP Test firmware image 5 */ 10463 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_BACKPRESSURE 0x105 10464 /* enum: RXDP Test firmware image 6 */ 10465 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 10466 /* enum: RXDP Test firmware image 7 */ 10467 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 10468 /* enum: RXDP Test firmware image 8 */ 10469 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 10470 /* enum: RXDP Test firmware image 9 */ 10471 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 10472 /* enum: RXDP Test firmware image 10 */ 10473 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_SLOW 0x10c 10474 /* TxDPCPU firmware id. */ 10475 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_OFST 6 10476 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_LEN 2 10477 /* enum: Standard TXDP firmware */ 10478 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP 0x0 10479 /* enum: Low latency TXDP firmware */ 10480 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_LOW_LATENCY 0x1 10481 /* enum: High packet rate TXDP firmware */ 10482 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_HIGH_PACKET_RATE 0x3 10483 /* enum: Rules engine TXDP firmware */ 10484 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_RULES_ENGINE 0x5 10485 /* enum: DPDK TXDP firmware */ 10486 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_DPDK 0x6 10487 /* enum: BIST TXDP firmware */ 10488 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_BIST 0x12d 10489 /* enum: TXDP Test firmware image 1 */ 10490 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 10491 /* enum: TXDP Test firmware image 2 */ 10492 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 10493 /* enum: TXDP CSR bus test firmware */ 10494 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_CSR 0x103 10495 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_OFST 8 10496 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_LEN 2 10497 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_LBN 0 10498 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_WIDTH 12 10499 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_LBN 12 10500 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 10501 /* enum: reserved value - do not use (may indicate alternative interpretation 10502 * of REV field in future) 10503 */ 10504 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RESERVED 0x0 10505 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 10506 * development only) 10507 */ 10508 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 10509 /* enum: RX PD firmware with approximately Siena-compatible behaviour 10510 * (Huntington development only) 10511 */ 10512 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 10513 /* enum: Full featured RX PD production firmware */ 10514 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 10515 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 10516 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_VSWITCH 0x3 10517 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 10518 * (Huntington development only) 10519 */ 10520 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10521 /* enum: Low latency RX PD production firmware */ 10522 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 10523 /* enum: Packed stream RX PD production firmware */ 10524 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 10525 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 10526 * tests (Medford development only) 10527 */ 10528 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 10529 /* enum: Rules engine RX PD production firmware */ 10530 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 10531 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 10532 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_L3XUDP 0x9 10533 /* enum: DPDK RX PD production firmware */ 10534 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_DPDK 0xa 10535 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10536 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10537 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 10538 * encapsulations (Medford development only) 10539 */ 10540 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 10541 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_OFST 10 10542 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_LEN 2 10543 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_LBN 0 10544 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_WIDTH 12 10545 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_LBN 12 10546 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 10547 /* enum: reserved value - do not use (may indicate alternative interpretation 10548 * of REV field in future) 10549 */ 10550 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RESERVED 0x0 10551 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 10552 * development only) 10553 */ 10554 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 10555 /* enum: TX PD firmware with approximately Siena-compatible behaviour 10556 * (Huntington development only) 10557 */ 10558 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 10559 /* enum: Full featured TX PD production firmware */ 10560 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 10561 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 10562 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_VSWITCH 0x3 10563 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 10564 * (Huntington development only) 10565 */ 10566 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10567 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 10568 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 10569 * tests (Medford development only) 10570 */ 10571 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 10572 /* enum: Rules engine TX PD production firmware */ 10573 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 10574 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 10575 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_L3XUDP 0x9 10576 /* enum: DPDK TX PD production firmware */ 10577 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_DPDK 0xa 10578 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10579 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10580 /* Hardware capabilities of NIC */ 10581 #define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_OFST 12 10582 #define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_LEN 4 10583 /* Licensed capabilities */ 10584 #define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_OFST 16 10585 #define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_LEN 4 10586 /* Second word of flags. Not present on older firmware (check the length). */ 10587 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_OFST 20 10588 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_LEN 4 10589 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_LBN 0 10590 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_WIDTH 1 10591 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_LBN 1 10592 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_WIDTH 1 10593 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_LBN 2 10594 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_WIDTH 1 10595 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_LBN 3 10596 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_WIDTH 1 10597 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_LBN 4 10598 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_WIDTH 1 10599 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_LBN 5 10600 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 10601 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 10602 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 10603 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_LBN 7 10604 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_WIDTH 1 10605 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_LBN 8 10606 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 10607 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_LBN 9 10608 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_WIDTH 1 10609 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_LBN 10 10610 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_WIDTH 1 10611 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_LBN 11 10612 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_WIDTH 1 10613 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 10614 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 10615 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_LBN 13 10616 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_WIDTH 1 10617 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_LBN 14 10618 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_WIDTH 1 10619 #define MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_LBN 15 10620 #define MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_WIDTH 1 10621 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_LBN 16 10622 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_WIDTH 1 10623 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_LBN 17 10624 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_WIDTH 1 10625 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18 10626 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1 10627 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_LBN 19 10628 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_WIDTH 1 10629 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_LBN 20 10630 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_WIDTH 1 10631 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21 10632 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1 10633 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21 10634 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1 10635 #define MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_LBN 22 10636 #define MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_WIDTH 1 10637 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23 10638 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1 10639 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_LBN 24 10640 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_WIDTH 1 10641 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_LBN 25 10642 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_WIDTH 1 10643 /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present 10644 * on older firmware (check the length). 10645 */ 10646 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 10647 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 10648 /* One byte per PF containing the number of the external port assigned to this 10649 * PF, indexed by PF number. Special values indicate that a PF is either not 10650 * present or not assigned. 10651 */ 10652 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 10653 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 10654 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 10655 /* enum: The caller is not permitted to access information on this PF. */ 10656 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff 10657 /* enum: PF does not exist. */ 10658 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe 10659 /* enum: PF does exist but is not assigned to any external port. */ 10660 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_ASSIGNED 0xfd 10661 /* enum: This value indicates that PF is assigned, but it cannot be expressed 10662 * in this field. It is intended for a possible future situation where a more 10663 * complex scheme of PFs to ports mapping is being used. The future driver 10664 * should look for a new field supporting the new scheme. The current/old 10665 * driver should treat this value as PF_NOT_ASSIGNED. 10666 */ 10667 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 10668 /* One byte per PF containing the number of its VFs, indexed by PF number. A 10669 * special value indicates that a PF is not present. 10670 */ 10671 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_OFST 42 10672 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_LEN 1 10673 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_NUM 16 10674 /* enum: The caller is not permitted to access information on this PF. */ 10675 /* MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff */ 10676 /* enum: PF does not exist. */ 10677 /* MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe */ 10678 /* Number of VIs available for each external port */ 10679 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_OFST 58 10680 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_LEN 2 10681 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_NUM 4 10682 /* Size of RX descriptor cache expressed as binary logarithm The actual size 10683 * equals (2 ^ RX_DESC_CACHE_SIZE) 10684 */ 10685 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_OFST 66 10686 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_LEN 1 10687 /* Size of TX descriptor cache expressed as binary logarithm The actual size 10688 * equals (2 ^ TX_DESC_CACHE_SIZE) 10689 */ 10690 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_OFST 67 10691 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_LEN 1 10692 /* Total number of available PIO buffers */ 10693 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_OFST 68 10694 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_LEN 2 10695 /* Size of a single PIO buffer */ 10696 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_OFST 70 10697 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_LEN 2 10698 /* On chips later than Medford the amount of address space assigned to each VI 10699 * is configurable. This is a global setting that the driver must query to 10700 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available 10701 * with 8k VI windows. 10702 */ 10703 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_OFST 72 10704 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_LEN 1 10705 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k. 10706 * CTPIO is not mapped. 10707 */ 10708 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K 0x0 10709 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */ 10710 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K 0x1 10711 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */ 10712 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K 0x2 10713 /* Number of vFIFOs per adapter that can be used for VFIFO Stuffing 10714 * (SF-115995-SW) in the present configuration of firmware and port mode. 10715 */ 10716 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73 10717 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1 10718 /* Number of buffers per adapter that can be used for VFIFO Stuffing 10719 * (SF-115995-SW) in the present configuration of firmware and port mode. 10720 */ 10721 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74 10722 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2 10723 10724 /* MC_CMD_GET_CAPABILITIES_V4_OUT msgresponse */ 10725 #define MC_CMD_GET_CAPABILITIES_V4_OUT_LEN 78 10726 /* First word of flags. */ 10727 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST 0 10728 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_LEN 4 10729 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_LBN 3 10730 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_WIDTH 1 10731 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_LBN 4 10732 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_WIDTH 1 10733 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_LBN 5 10734 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_WIDTH 1 10735 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 10736 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 10737 #define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_LBN 7 10738 #define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 10739 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_LBN 8 10740 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 10741 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_LBN 9 10742 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_WIDTH 1 10743 #define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 10744 #define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 10745 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 10746 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 10747 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 10748 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 10749 #define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_LBN 13 10750 #define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 10751 #define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_LBN 14 10752 #define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_WIDTH 1 10753 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 10754 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 10755 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_LBN 16 10756 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_WIDTH 1 10757 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_LBN 17 10758 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_WIDTH 1 10759 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_LBN 18 10760 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_WIDTH 1 10761 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_LBN 19 10762 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_WIDTH 1 10763 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_LBN 20 10764 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_WIDTH 1 10765 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_LBN 21 10766 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_WIDTH 1 10767 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_LBN 22 10768 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_WIDTH 1 10769 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_LBN 23 10770 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_WIDTH 1 10771 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_LBN 24 10772 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_WIDTH 1 10773 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_LBN 25 10774 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_WIDTH 1 10775 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_LBN 26 10776 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_WIDTH 1 10777 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_LBN 27 10778 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 10779 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_LBN 28 10780 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_WIDTH 1 10781 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 10782 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 10783 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_LBN 30 10784 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_WIDTH 1 10785 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_LBN 31 10786 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_WIDTH 1 10787 /* RxDPCPU firmware id. */ 10788 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_OFST 4 10789 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_LEN 2 10790 /* enum: Standard RXDP firmware */ 10791 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP 0x0 10792 /* enum: Low latency RXDP firmware */ 10793 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_LOW_LATENCY 0x1 10794 /* enum: Packed stream RXDP firmware */ 10795 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_PACKED_STREAM 0x2 10796 /* enum: Rules engine RXDP firmware */ 10797 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_RULES_ENGINE 0x5 10798 /* enum: DPDK RXDP firmware */ 10799 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_DPDK 0x6 10800 /* enum: BIST RXDP firmware */ 10801 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_BIST 0x10a 10802 /* enum: RXDP Test firmware image 1 */ 10803 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 10804 /* enum: RXDP Test firmware image 2 */ 10805 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 10806 /* enum: RXDP Test firmware image 3 */ 10807 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 10808 /* enum: RXDP Test firmware image 4 */ 10809 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 10810 /* enum: RXDP Test firmware image 5 */ 10811 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_BACKPRESSURE 0x105 10812 /* enum: RXDP Test firmware image 6 */ 10813 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 10814 /* enum: RXDP Test firmware image 7 */ 10815 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 10816 /* enum: RXDP Test firmware image 8 */ 10817 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 10818 /* enum: RXDP Test firmware image 9 */ 10819 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 10820 /* enum: RXDP Test firmware image 10 */ 10821 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_SLOW 0x10c 10822 /* TxDPCPU firmware id. */ 10823 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_OFST 6 10824 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_LEN 2 10825 /* enum: Standard TXDP firmware */ 10826 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP 0x0 10827 /* enum: Low latency TXDP firmware */ 10828 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_LOW_LATENCY 0x1 10829 /* enum: High packet rate TXDP firmware */ 10830 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_HIGH_PACKET_RATE 0x3 10831 /* enum: Rules engine TXDP firmware */ 10832 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_RULES_ENGINE 0x5 10833 /* enum: DPDK TXDP firmware */ 10834 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_DPDK 0x6 10835 /* enum: BIST TXDP firmware */ 10836 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_BIST 0x12d 10837 /* enum: TXDP Test firmware image 1 */ 10838 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 10839 /* enum: TXDP Test firmware image 2 */ 10840 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 10841 /* enum: TXDP CSR bus test firmware */ 10842 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_CSR 0x103 10843 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_OFST 8 10844 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_LEN 2 10845 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_LBN 0 10846 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_WIDTH 12 10847 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_LBN 12 10848 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 10849 /* enum: reserved value - do not use (may indicate alternative interpretation 10850 * of REV field in future) 10851 */ 10852 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RESERVED 0x0 10853 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 10854 * development only) 10855 */ 10856 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 10857 /* enum: RX PD firmware with approximately Siena-compatible behaviour 10858 * (Huntington development only) 10859 */ 10860 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 10861 /* enum: Full featured RX PD production firmware */ 10862 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 10863 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 10864 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_VSWITCH 0x3 10865 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 10866 * (Huntington development only) 10867 */ 10868 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10869 /* enum: Low latency RX PD production firmware */ 10870 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 10871 /* enum: Packed stream RX PD production firmware */ 10872 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 10873 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 10874 * tests (Medford development only) 10875 */ 10876 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 10877 /* enum: Rules engine RX PD production firmware */ 10878 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 10879 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 10880 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_L3XUDP 0x9 10881 /* enum: DPDK RX PD production firmware */ 10882 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_DPDK 0xa 10883 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10884 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10885 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 10886 * encapsulations (Medford development only) 10887 */ 10888 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 10889 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_OFST 10 10890 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_LEN 2 10891 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_LBN 0 10892 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_WIDTH 12 10893 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_LBN 12 10894 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 10895 /* enum: reserved value - do not use (may indicate alternative interpretation 10896 * of REV field in future) 10897 */ 10898 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RESERVED 0x0 10899 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 10900 * development only) 10901 */ 10902 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 10903 /* enum: TX PD firmware with approximately Siena-compatible behaviour 10904 * (Huntington development only) 10905 */ 10906 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 10907 /* enum: Full featured TX PD production firmware */ 10908 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 10909 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 10910 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_VSWITCH 0x3 10911 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 10912 * (Huntington development only) 10913 */ 10914 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10915 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 10916 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 10917 * tests (Medford development only) 10918 */ 10919 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 10920 /* enum: Rules engine TX PD production firmware */ 10921 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 10922 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 10923 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_L3XUDP 0x9 10924 /* enum: DPDK TX PD production firmware */ 10925 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_DPDK 0xa 10926 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10927 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10928 /* Hardware capabilities of NIC */ 10929 #define MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_OFST 12 10930 #define MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_LEN 4 10931 /* Licensed capabilities */ 10932 #define MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_OFST 16 10933 #define MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_LEN 4 10934 /* Second word of flags. Not present on older firmware (check the length). */ 10935 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_OFST 20 10936 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_LEN 4 10937 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_LBN 0 10938 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_WIDTH 1 10939 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_LBN 1 10940 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_WIDTH 1 10941 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_LBN 2 10942 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_WIDTH 1 10943 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_LBN 3 10944 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_WIDTH 1 10945 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_LBN 4 10946 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_WIDTH 1 10947 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_LBN 5 10948 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 10949 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 10950 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 10951 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_LBN 7 10952 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_WIDTH 1 10953 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_LBN 8 10954 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 10955 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_LBN 9 10956 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_WIDTH 1 10957 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_LBN 10 10958 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_WIDTH 1 10959 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_LBN 11 10960 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_WIDTH 1 10961 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 10962 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 10963 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_LBN 13 10964 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_WIDTH 1 10965 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_LBN 14 10966 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_WIDTH 1 10967 #define MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_LBN 15 10968 #define MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_WIDTH 1 10969 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_LBN 16 10970 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_WIDTH 1 10971 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_LBN 17 10972 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_WIDTH 1 10973 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18 10974 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1 10975 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_LBN 19 10976 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_WIDTH 1 10977 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_LBN 20 10978 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_WIDTH 1 10979 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21 10980 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1 10981 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21 10982 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1 10983 #define MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_LBN 22 10984 #define MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_WIDTH 1 10985 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23 10986 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1 10987 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_LBN 24 10988 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_WIDTH 1 10989 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_LBN 25 10990 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_WIDTH 1 10991 /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present 10992 * on older firmware (check the length). 10993 */ 10994 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 10995 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 10996 /* One byte per PF containing the number of the external port assigned to this 10997 * PF, indexed by PF number. Special values indicate that a PF is either not 10998 * present or not assigned. 10999 */ 11000 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 11001 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 11002 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 11003 /* enum: The caller is not permitted to access information on this PF. */ 11004 #define MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff 11005 /* enum: PF does not exist. */ 11006 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe 11007 /* enum: PF does exist but is not assigned to any external port. */ 11008 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_ASSIGNED 0xfd 11009 /* enum: This value indicates that PF is assigned, but it cannot be expressed 11010 * in this field. It is intended for a possible future situation where a more 11011 * complex scheme of PFs to ports mapping is being used. The future driver 11012 * should look for a new field supporting the new scheme. The current/old 11013 * driver should treat this value as PF_NOT_ASSIGNED. 11014 */ 11015 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 11016 /* One byte per PF containing the number of its VFs, indexed by PF number. A 11017 * special value indicates that a PF is not present. 11018 */ 11019 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_OFST 42 11020 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_LEN 1 11021 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_NUM 16 11022 /* enum: The caller is not permitted to access information on this PF. */ 11023 /* MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff */ 11024 /* enum: PF does not exist. */ 11025 /* MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe */ 11026 /* Number of VIs available for each external port */ 11027 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_OFST 58 11028 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_LEN 2 11029 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_NUM 4 11030 /* Size of RX descriptor cache expressed as binary logarithm The actual size 11031 * equals (2 ^ RX_DESC_CACHE_SIZE) 11032 */ 11033 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_OFST 66 11034 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_LEN 1 11035 /* Size of TX descriptor cache expressed as binary logarithm The actual size 11036 * equals (2 ^ TX_DESC_CACHE_SIZE) 11037 */ 11038 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_OFST 67 11039 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_LEN 1 11040 /* Total number of available PIO buffers */ 11041 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_PIO_BUFFS_OFST 68 11042 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_PIO_BUFFS_LEN 2 11043 /* Size of a single PIO buffer */ 11044 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SIZE_PIO_BUFF_OFST 70 11045 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SIZE_PIO_BUFF_LEN 2 11046 /* On chips later than Medford the amount of address space assigned to each VI 11047 * is configurable. This is a global setting that the driver must query to 11048 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available 11049 * with 8k VI windows. 11050 */ 11051 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_OFST 72 11052 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_LEN 1 11053 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k. 11054 * CTPIO is not mapped. 11055 */ 11056 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_8K 0x0 11057 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */ 11058 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_16K 0x1 11059 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */ 11060 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_64K 0x2 11061 /* Number of vFIFOs per adapter that can be used for VFIFO Stuffing 11062 * (SF-115995-SW) in the present configuration of firmware and port mode. 11063 */ 11064 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73 11065 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1 11066 /* Number of buffers per adapter that can be used for VFIFO Stuffing 11067 * (SF-115995-SW) in the present configuration of firmware and port mode. 11068 */ 11069 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74 11070 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2 11071 /* Entry count in the MAC stats array, including the final GENERATION_END 11072 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to 11073 * hold at least this many 64-bit stats values, if they wish to receive all 11074 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the 11075 * stats array returned will be truncated. 11076 */ 11077 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_OFST 76 11078 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_LEN 2 11079 11080 /* MC_CMD_GET_CAPABILITIES_V5_OUT msgresponse */ 11081 #define MC_CMD_GET_CAPABILITIES_V5_OUT_LEN 84 11082 /* First word of flags. */ 11083 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_OFST 0 11084 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_LEN 4 11085 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_LBN 3 11086 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_WIDTH 1 11087 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_LBN 4 11088 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_WIDTH 1 11089 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_LBN 5 11090 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_WIDTH 1 11091 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 11092 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 11093 #define MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_LBN 7 11094 #define MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 11095 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_LBN 8 11096 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 11097 #define MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_LBN 9 11098 #define MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_WIDTH 1 11099 #define MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 11100 #define MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 11101 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 11102 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 11103 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 11104 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 11105 #define MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_LBN 13 11106 #define MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 11107 #define MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_LBN 14 11108 #define MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_WIDTH 1 11109 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 11110 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 11111 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_LBN 16 11112 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_WIDTH 1 11113 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_LBN 17 11114 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_WIDTH 1 11115 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_LBN 18 11116 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_WIDTH 1 11117 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_LBN 19 11118 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_WIDTH 1 11119 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_LBN 20 11120 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_WIDTH 1 11121 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_LBN 21 11122 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_WIDTH 1 11123 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_LBN 22 11124 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_WIDTH 1 11125 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_LBN 23 11126 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_WIDTH 1 11127 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_LBN 24 11128 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_WIDTH 1 11129 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_LBN 25 11130 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_WIDTH 1 11131 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_LBN 26 11132 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_WIDTH 1 11133 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_LBN 27 11134 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 11135 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_LBN 28 11136 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_WIDTH 1 11137 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 11138 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 11139 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_LBN 30 11140 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_WIDTH 1 11141 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_LBN 31 11142 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_WIDTH 1 11143 /* RxDPCPU firmware id. */ 11144 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DPCPU_FW_ID_OFST 4 11145 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DPCPU_FW_ID_LEN 2 11146 /* enum: Standard RXDP firmware */ 11147 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP 0x0 11148 /* enum: Low latency RXDP firmware */ 11149 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_LOW_LATENCY 0x1 11150 /* enum: Packed stream RXDP firmware */ 11151 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_PACKED_STREAM 0x2 11152 /* enum: Rules engine RXDP firmware */ 11153 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_RULES_ENGINE 0x5 11154 /* enum: DPDK RXDP firmware */ 11155 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_DPDK 0x6 11156 /* enum: BIST RXDP firmware */ 11157 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_BIST 0x10a 11158 /* enum: RXDP Test firmware image 1 */ 11159 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 11160 /* enum: RXDP Test firmware image 2 */ 11161 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 11162 /* enum: RXDP Test firmware image 3 */ 11163 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 11164 /* enum: RXDP Test firmware image 4 */ 11165 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 11166 /* enum: RXDP Test firmware image 5 */ 11167 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_BACKPRESSURE 0x105 11168 /* enum: RXDP Test firmware image 6 */ 11169 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 11170 /* enum: RXDP Test firmware image 7 */ 11171 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 11172 /* enum: RXDP Test firmware image 8 */ 11173 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 11174 /* enum: RXDP Test firmware image 9 */ 11175 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 11176 /* enum: RXDP Test firmware image 10 */ 11177 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_SLOW 0x10c 11178 /* TxDPCPU firmware id. */ 11179 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DPCPU_FW_ID_OFST 6 11180 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DPCPU_FW_ID_LEN 2 11181 /* enum: Standard TXDP firmware */ 11182 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP 0x0 11183 /* enum: Low latency TXDP firmware */ 11184 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_LOW_LATENCY 0x1 11185 /* enum: High packet rate TXDP firmware */ 11186 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_HIGH_PACKET_RATE 0x3 11187 /* enum: Rules engine TXDP firmware */ 11188 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_RULES_ENGINE 0x5 11189 /* enum: DPDK TXDP firmware */ 11190 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_DPDK 0x6 11191 /* enum: BIST TXDP firmware */ 11192 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_BIST 0x12d 11193 /* enum: TXDP Test firmware image 1 */ 11194 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 11195 /* enum: TXDP Test firmware image 2 */ 11196 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 11197 /* enum: TXDP CSR bus test firmware */ 11198 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_CSR 0x103 11199 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_OFST 8 11200 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_LEN 2 11201 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_LBN 0 11202 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_WIDTH 12 11203 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_LBN 12 11204 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 11205 /* enum: reserved value - do not use (may indicate alternative interpretation 11206 * of REV field in future) 11207 */ 11208 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_RESERVED 0x0 11209 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 11210 * development only) 11211 */ 11212 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 11213 /* enum: RX PD firmware with approximately Siena-compatible behaviour 11214 * (Huntington development only) 11215 */ 11216 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 11217 /* enum: Full featured RX PD production firmware */ 11218 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 11219 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 11220 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_VSWITCH 0x3 11221 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 11222 * (Huntington development only) 11223 */ 11224 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 11225 /* enum: Low latency RX PD production firmware */ 11226 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 11227 /* enum: Packed stream RX PD production firmware */ 11228 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 11229 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 11230 * tests (Medford development only) 11231 */ 11232 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 11233 /* enum: Rules engine RX PD production firmware */ 11234 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 11235 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 11236 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_L3XUDP 0x9 11237 /* enum: DPDK RX PD production firmware */ 11238 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_DPDK 0xa 11239 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 11240 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 11241 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 11242 * encapsulations (Medford development only) 11243 */ 11244 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 11245 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_OFST 10 11246 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_LEN 2 11247 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_LBN 0 11248 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_WIDTH 12 11249 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_LBN 12 11250 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 11251 /* enum: reserved value - do not use (may indicate alternative interpretation 11252 * of REV field in future) 11253 */ 11254 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_RESERVED 0x0 11255 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 11256 * development only) 11257 */ 11258 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 11259 /* enum: TX PD firmware with approximately Siena-compatible behaviour 11260 * (Huntington development only) 11261 */ 11262 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 11263 /* enum: Full featured TX PD production firmware */ 11264 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 11265 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 11266 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_VSWITCH 0x3 11267 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 11268 * (Huntington development only) 11269 */ 11270 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 11271 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 11272 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 11273 * tests (Medford development only) 11274 */ 11275 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 11276 /* enum: Rules engine TX PD production firmware */ 11277 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 11278 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */ 11279 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_L3XUDP 0x9 11280 /* enum: DPDK TX PD production firmware */ 11281 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_DPDK 0xa 11282 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 11283 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 11284 /* Hardware capabilities of NIC */ 11285 #define MC_CMD_GET_CAPABILITIES_V5_OUT_HW_CAPABILITIES_OFST 12 11286 #define MC_CMD_GET_CAPABILITIES_V5_OUT_HW_CAPABILITIES_LEN 4 11287 /* Licensed capabilities */ 11288 #define MC_CMD_GET_CAPABILITIES_V5_OUT_LICENSE_CAPABILITIES_OFST 16 11289 #define MC_CMD_GET_CAPABILITIES_V5_OUT_LICENSE_CAPABILITIES_LEN 4 11290 /* Second word of flags. Not present on older firmware (check the length). */ 11291 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS2_OFST 20 11292 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS2_LEN 4 11293 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_LBN 0 11294 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_WIDTH 1 11295 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_LBN 1 11296 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_WIDTH 1 11297 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_LBN 2 11298 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_WIDTH 1 11299 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_LBN 3 11300 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_WIDTH 1 11301 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_LBN 4 11302 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_WIDTH 1 11303 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_LBN 5 11304 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 11305 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 11306 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 11307 #define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_LBN 7 11308 #define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_WIDTH 1 11309 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_LBN 8 11310 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 11311 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_LBN 9 11312 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_WIDTH 1 11313 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_LBN 10 11314 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_WIDTH 1 11315 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_LBN 11 11316 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_WIDTH 1 11317 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 11318 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 11319 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_LBN 13 11320 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_WIDTH 1 11321 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_LBN 14 11322 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_WIDTH 1 11323 #define MC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_LBN 15 11324 #define MC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_WIDTH 1 11325 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_LBN 16 11326 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_WIDTH 1 11327 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_LBN 17 11328 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_WIDTH 1 11329 #define MC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18 11330 #define MC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1 11331 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_LBN 19 11332 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_WIDTH 1 11333 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_LBN 20 11334 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_WIDTH 1 11335 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21 11336 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1 11337 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21 11338 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1 11339 #define MC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_LBN 22 11340 #define MC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_WIDTH 1 11341 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23 11342 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1 11343 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_LBN 24 11344 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_WIDTH 1 11345 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_LBN 25 11346 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_WIDTH 1 11347 /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present 11348 * on older firmware (check the length). 11349 */ 11350 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 11351 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 11352 /* One byte per PF containing the number of the external port assigned to this 11353 * PF, indexed by PF number. Special values indicate that a PF is either not 11354 * present or not assigned. 11355 */ 11356 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 11357 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 11358 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 11359 /* enum: The caller is not permitted to access information on this PF. */ 11360 #define MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff 11361 /* enum: PF does not exist. */ 11362 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe 11363 /* enum: PF does exist but is not assigned to any external port. */ 11364 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_ASSIGNED 0xfd 11365 /* enum: This value indicates that PF is assigned, but it cannot be expressed 11366 * in this field. It is intended for a possible future situation where a more 11367 * complex scheme of PFs to ports mapping is being used. The future driver 11368 * should look for a new field supporting the new scheme. The current/old 11369 * driver should treat this value as PF_NOT_ASSIGNED. 11370 */ 11371 #define MC_CMD_GET_CAPABILITIES_V5_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 11372 /* One byte per PF containing the number of its VFs, indexed by PF number. A 11373 * special value indicates that a PF is not present. 11374 */ 11375 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VFS_PER_PF_OFST 42 11376 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VFS_PER_PF_LEN 1 11377 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VFS_PER_PF_NUM 16 11378 /* enum: The caller is not permitted to access information on this PF. */ 11379 /* MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff */ 11380 /* enum: PF does not exist. */ 11381 /* MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe */ 11382 /* Number of VIs available for each external port */ 11383 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_OFST 58 11384 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_LEN 2 11385 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_NUM 4 11386 /* Size of RX descriptor cache expressed as binary logarithm The actual size 11387 * equals (2 ^ RX_DESC_CACHE_SIZE) 11388 */ 11389 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DESC_CACHE_SIZE_OFST 66 11390 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DESC_CACHE_SIZE_LEN 1 11391 /* Size of TX descriptor cache expressed as binary logarithm The actual size 11392 * equals (2 ^ TX_DESC_CACHE_SIZE) 11393 */ 11394 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DESC_CACHE_SIZE_OFST 67 11395 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DESC_CACHE_SIZE_LEN 1 11396 /* Total number of available PIO buffers */ 11397 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_PIO_BUFFS_OFST 68 11398 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_PIO_BUFFS_LEN 2 11399 /* Size of a single PIO buffer */ 11400 #define MC_CMD_GET_CAPABILITIES_V5_OUT_SIZE_PIO_BUFF_OFST 70 11401 #define MC_CMD_GET_CAPABILITIES_V5_OUT_SIZE_PIO_BUFF_LEN 2 11402 /* On chips later than Medford the amount of address space assigned to each VI 11403 * is configurable. This is a global setting that the driver must query to 11404 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available 11405 * with 8k VI windows. 11406 */ 11407 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_OFST 72 11408 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_LEN 1 11409 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k. 11410 * CTPIO is not mapped. 11411 */ 11412 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_8K 0x0 11413 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */ 11414 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_16K 0x1 11415 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */ 11416 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_64K 0x2 11417 /* Number of vFIFOs per adapter that can be used for VFIFO Stuffing 11418 * (SF-115995-SW) in the present configuration of firmware and port mode. 11419 */ 11420 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73 11421 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1 11422 /* Number of buffers per adapter that can be used for VFIFO Stuffing 11423 * (SF-115995-SW) in the present configuration of firmware and port mode. 11424 */ 11425 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74 11426 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2 11427 /* Entry count in the MAC stats array, including the final GENERATION_END 11428 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to 11429 * hold at least this many 64-bit stats values, if they wish to receive all 11430 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the 11431 * stats array returned will be truncated. 11432 */ 11433 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_NUM_STATS_OFST 76 11434 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_NUM_STATS_LEN 2 11435 /* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field 11436 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set. 11437 */ 11438 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX_OFST 80 11439 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX_LEN 4 11440 11441 11442 /***********************************/ 11443 /* MC_CMD_V2_EXTN 11444 * Encapsulation for a v2 extended command 11445 */ 11446 #define MC_CMD_V2_EXTN 0x7f 11447 11448 /* MC_CMD_V2_EXTN_IN msgrequest */ 11449 #define MC_CMD_V2_EXTN_IN_LEN 4 11450 /* the extended command number */ 11451 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0 11452 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15 11453 #define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15 11454 #define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1 11455 /* the actual length of the encapsulated command (which is not in the v1 11456 * header) 11457 */ 11458 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16 11459 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10 11460 #define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26 11461 #define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 2 11462 /* Type of command/response */ 11463 #define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_LBN 28 11464 #define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_WIDTH 4 11465 /* enum: MCDI command directed to or response originating from the MC. */ 11466 #define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_MC 0x0 11467 /* enum: MCDI command directed to a TSA controller. MCDI responses of this type 11468 * are not defined. 11469 */ 11470 #define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_TSA 0x1 11471 11472 11473 /***********************************/ 11474 /* MC_CMD_TCM_BUCKET_ALLOC 11475 * Allocate a pacer bucket (for qau rp or a snapper test) 11476 */ 11477 #define MC_CMD_TCM_BUCKET_ALLOC 0xb2 11478 #undef MC_CMD_0xb2_PRIVILEGE_CTG 11479 11480 #define MC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11481 11482 /* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */ 11483 #define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0 11484 11485 /* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */ 11486 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4 11487 /* the bucket id */ 11488 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0 11489 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_LEN 4 11490 11491 11492 /***********************************/ 11493 /* MC_CMD_TCM_BUCKET_FREE 11494 * Free a pacer bucket 11495 */ 11496 #define MC_CMD_TCM_BUCKET_FREE 0xb3 11497 #undef MC_CMD_0xb3_PRIVILEGE_CTG 11498 11499 #define MC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11500 11501 /* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */ 11502 #define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4 11503 /* the bucket id */ 11504 #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0 11505 #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_LEN 4 11506 11507 /* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */ 11508 #define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0 11509 11510 11511 /***********************************/ 11512 /* MC_CMD_TCM_BUCKET_INIT 11513 * Initialise pacer bucket with a given rate 11514 */ 11515 #define MC_CMD_TCM_BUCKET_INIT 0xb4 11516 #undef MC_CMD_0xb4_PRIVILEGE_CTG 11517 11518 #define MC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11519 11520 /* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */ 11521 #define MC_CMD_TCM_BUCKET_INIT_IN_LEN 8 11522 /* the bucket id */ 11523 #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0 11524 #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_LEN 4 11525 /* the rate in mbps */ 11526 #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4 11527 #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_LEN 4 11528 11529 /* MC_CMD_TCM_BUCKET_INIT_EXT_IN msgrequest */ 11530 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_LEN 12 11531 /* the bucket id */ 11532 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_OFST 0 11533 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_LEN 4 11534 /* the rate in mbps */ 11535 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_OFST 4 11536 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_LEN 4 11537 /* the desired maximum fill level */ 11538 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_OFST 8 11539 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_LEN 4 11540 11541 /* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */ 11542 #define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0 11543 11544 11545 /***********************************/ 11546 /* MC_CMD_TCM_TXQ_INIT 11547 * Initialise txq in pacer with given options or set options 11548 */ 11549 #define MC_CMD_TCM_TXQ_INIT 0xb5 11550 #undef MC_CMD_0xb5_PRIVILEGE_CTG 11551 11552 #define MC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11553 11554 /* MC_CMD_TCM_TXQ_INIT_IN msgrequest */ 11555 #define MC_CMD_TCM_TXQ_INIT_IN_LEN 28 11556 /* the txq id */ 11557 #define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0 11558 #define MC_CMD_TCM_TXQ_INIT_IN_QID_LEN 4 11559 /* the static priority associated with the txq */ 11560 #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4 11561 #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_LEN 4 11562 /* bitmask of the priority queues this txq is inserted into when inserted. */ 11563 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8 11564 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_LEN 4 11565 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 0 11566 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 11567 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_LBN 1 11568 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_WIDTH 1 11569 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_LBN 2 11570 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_WIDTH 1 11571 /* the reaction point (RP) bucket */ 11572 #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12 11573 #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_LEN 4 11574 /* an already reserved bucket (typically set to bucket associated with outer 11575 * vswitch) 11576 */ 11577 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16 11578 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_LEN 4 11579 /* an already reserved bucket (typically set to bucket associated with inner 11580 * vswitch) 11581 */ 11582 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20 11583 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_LEN 4 11584 /* the min bucket (typically for ETS/minimum bandwidth) */ 11585 #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24 11586 #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_LEN 4 11587 11588 /* MC_CMD_TCM_TXQ_INIT_EXT_IN msgrequest */ 11589 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LEN 32 11590 /* the txq id */ 11591 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_OFST 0 11592 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_LEN 4 11593 /* the static priority associated with the txq */ 11594 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_OFST 4 11595 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_LEN 4 11596 /* bitmask of the priority queues this txq is inserted into when inserted. */ 11597 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_OFST 8 11598 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_LEN 4 11599 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 0 11600 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 11601 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_LBN 1 11602 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_WIDTH 1 11603 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_LBN 2 11604 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_WIDTH 1 11605 /* the reaction point (RP) bucket */ 11606 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_OFST 12 11607 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_LEN 4 11608 /* an already reserved bucket (typically set to bucket associated with outer 11609 * vswitch) 11610 */ 11611 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_OFST 16 11612 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_LEN 4 11613 /* an already reserved bucket (typically set to bucket associated with inner 11614 * vswitch) 11615 */ 11616 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_OFST 20 11617 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_LEN 4 11618 /* the min bucket (typically for ETS/minimum bandwidth) */ 11619 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_OFST 24 11620 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_LEN 4 11621 /* the static priority associated with the txq */ 11622 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_OFST 28 11623 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_LEN 4 11624 11625 /* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */ 11626 #define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0 11627 11628 11629 /***********************************/ 11630 /* MC_CMD_LINK_PIOBUF 11631 * Link a push I/O buffer to a TxQ 11632 */ 11633 #define MC_CMD_LINK_PIOBUF 0x92 11634 #undef MC_CMD_0x92_PRIVILEGE_CTG 11635 11636 #define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 11637 11638 /* MC_CMD_LINK_PIOBUF_IN msgrequest */ 11639 #define MC_CMD_LINK_PIOBUF_IN_LEN 8 11640 /* Handle for allocated push I/O buffer. */ 11641 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 11642 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_LEN 4 11643 /* Function Local Instance (VI) number. */ 11644 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4 11645 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4 11646 11647 /* MC_CMD_LINK_PIOBUF_OUT msgresponse */ 11648 #define MC_CMD_LINK_PIOBUF_OUT_LEN 0 11649 11650 11651 /***********************************/ 11652 /* MC_CMD_UNLINK_PIOBUF 11653 * Unlink a push I/O buffer from a TxQ 11654 */ 11655 #define MC_CMD_UNLINK_PIOBUF 0x93 11656 #undef MC_CMD_0x93_PRIVILEGE_CTG 11657 11658 #define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 11659 11660 /* MC_CMD_UNLINK_PIOBUF_IN msgrequest */ 11661 #define MC_CMD_UNLINK_PIOBUF_IN_LEN 4 11662 /* Function Local Instance (VI) number. */ 11663 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0 11664 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4 11665 11666 /* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */ 11667 #define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0 11668 11669 11670 /***********************************/ 11671 /* MC_CMD_VSWITCH_ALLOC 11672 * allocate and initialise a v-switch. 11673 */ 11674 #define MC_CMD_VSWITCH_ALLOC 0x94 11675 #undef MC_CMD_0x94_PRIVILEGE_CTG 11676 11677 #define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11678 11679 /* MC_CMD_VSWITCH_ALLOC_IN msgrequest */ 11680 #define MC_CMD_VSWITCH_ALLOC_IN_LEN 16 11681 /* The port to connect to the v-switch's upstream port. */ 11682 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 11683 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 11684 /* The type of v-switch to create. */ 11685 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4 11686 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_LEN 4 11687 /* enum: VLAN */ 11688 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1 11689 /* enum: VEB */ 11690 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2 11691 /* enum: VEPA (obsolete) */ 11692 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3 11693 /* enum: MUX */ 11694 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x4 11695 /* enum: Snapper specific; semantics TBD */ 11696 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x5 11697 /* Flags controlling v-port creation */ 11698 #define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8 11699 #define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_LEN 4 11700 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 11701 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 11702 /* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators, 11703 * this must be one or greated, and the attached v-ports must have exactly this 11704 * number of tags. For other v-switch types, this must be zero of greater, and 11705 * is an upper limit on the number of VLAN tags for attached v-ports. An error 11706 * will be returned if existing configuration means we can't support attached 11707 * v-ports with this number of tags. 11708 */ 11709 #define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 11710 #define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_LEN 4 11711 11712 /* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */ 11713 #define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0 11714 11715 11716 /***********************************/ 11717 /* MC_CMD_VSWITCH_FREE 11718 * de-allocate a v-switch. 11719 */ 11720 #define MC_CMD_VSWITCH_FREE 0x95 11721 #undef MC_CMD_0x95_PRIVILEGE_CTG 11722 11723 #define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11724 11725 /* MC_CMD_VSWITCH_FREE_IN msgrequest */ 11726 #define MC_CMD_VSWITCH_FREE_IN_LEN 4 11727 /* The port to which the v-switch is connected. */ 11728 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0 11729 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_LEN 4 11730 11731 /* MC_CMD_VSWITCH_FREE_OUT msgresponse */ 11732 #define MC_CMD_VSWITCH_FREE_OUT_LEN 0 11733 11734 11735 /***********************************/ 11736 /* MC_CMD_VSWITCH_QUERY 11737 * read some config of v-switch. For now this command is an empty placeholder. 11738 * It may be used to check if a v-switch is connected to a given EVB port (if 11739 * not, then the command returns ENOENT). 11740 */ 11741 #define MC_CMD_VSWITCH_QUERY 0x63 11742 #undef MC_CMD_0x63_PRIVILEGE_CTG 11743 11744 #define MC_CMD_0x63_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11745 11746 /* MC_CMD_VSWITCH_QUERY_IN msgrequest */ 11747 #define MC_CMD_VSWITCH_QUERY_IN_LEN 4 11748 /* The port to which the v-switch is connected. */ 11749 #define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_OFST 0 11750 #define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_LEN 4 11751 11752 /* MC_CMD_VSWITCH_QUERY_OUT msgresponse */ 11753 #define MC_CMD_VSWITCH_QUERY_OUT_LEN 0 11754 11755 11756 /***********************************/ 11757 /* MC_CMD_VPORT_ALLOC 11758 * allocate a v-port. 11759 */ 11760 #define MC_CMD_VPORT_ALLOC 0x96 11761 #undef MC_CMD_0x96_PRIVILEGE_CTG 11762 11763 #define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11764 11765 /* MC_CMD_VPORT_ALLOC_IN msgrequest */ 11766 #define MC_CMD_VPORT_ALLOC_IN_LEN 20 11767 /* The port to which the v-switch is connected. */ 11768 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 11769 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 11770 /* The type of the new v-port. */ 11771 #define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4 11772 #define MC_CMD_VPORT_ALLOC_IN_TYPE_LEN 4 11773 /* enum: VLAN (obsolete) */ 11774 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1 11775 /* enum: VEB (obsolete) */ 11776 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2 11777 /* enum: VEPA (obsolete) */ 11778 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3 11779 /* enum: A normal v-port receives packets which match a specified MAC and/or 11780 * VLAN. 11781 */ 11782 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4 11783 /* enum: An expansion v-port packets traffic which don't match any other 11784 * v-port. 11785 */ 11786 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5 11787 /* enum: An test v-port receives packets which match any filters installed by 11788 * its downstream components. 11789 */ 11790 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6 11791 /* Flags controlling v-port creation */ 11792 #define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8 11793 #define MC_CMD_VPORT_ALLOC_IN_FLAGS_LEN 4 11794 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 11795 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 11796 #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_LBN 1 11797 #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_WIDTH 1 11798 /* The number of VLAN tags to insert/remove. An error will be returned if 11799 * incompatible with the number of VLAN tags specified for the upstream 11800 * v-switch. 11801 */ 11802 #define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 11803 #define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_LEN 4 11804 /* The actual VLAN tags to insert/remove */ 11805 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16 11806 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_LEN 4 11807 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0 11808 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16 11809 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16 11810 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16 11811 11812 /* MC_CMD_VPORT_ALLOC_OUT msgresponse */ 11813 #define MC_CMD_VPORT_ALLOC_OUT_LEN 4 11814 /* The handle of the new v-port */ 11815 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0 11816 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_LEN 4 11817 11818 11819 /***********************************/ 11820 /* MC_CMD_VPORT_FREE 11821 * de-allocate a v-port. 11822 */ 11823 #define MC_CMD_VPORT_FREE 0x97 11824 #undef MC_CMD_0x97_PRIVILEGE_CTG 11825 11826 #define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11827 11828 /* MC_CMD_VPORT_FREE_IN msgrequest */ 11829 #define MC_CMD_VPORT_FREE_IN_LEN 4 11830 /* The handle of the v-port */ 11831 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0 11832 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_LEN 4 11833 11834 /* MC_CMD_VPORT_FREE_OUT msgresponse */ 11835 #define MC_CMD_VPORT_FREE_OUT_LEN 0 11836 11837 11838 /***********************************/ 11839 /* MC_CMD_VADAPTOR_ALLOC 11840 * allocate a v-adaptor. 11841 */ 11842 #define MC_CMD_VADAPTOR_ALLOC 0x98 11843 #undef MC_CMD_0x98_PRIVILEGE_CTG 11844 11845 #define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11846 11847 /* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */ 11848 #define MC_CMD_VADAPTOR_ALLOC_IN_LEN 30 11849 /* The port to connect to the v-adaptor's port. */ 11850 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 11851 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 11852 /* Flags controlling v-adaptor creation */ 11853 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8 11854 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_LEN 4 11855 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0 11856 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1 11857 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1 11858 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 11859 /* The number of VLAN tags to strip on receive */ 11860 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12 11861 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_LEN 4 11862 /* The number of VLAN tags to transparently insert/remove. */ 11863 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_OFST 16 11864 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_LEN 4 11865 /* The actual VLAN tags to insert/remove */ 11866 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 20 11867 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_LEN 4 11868 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0 11869 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 16 11870 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 16 11871 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_WIDTH 16 11872 /* The MAC address to assign to this v-adaptor */ 11873 #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_OFST 24 11874 #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_LEN 6 11875 /* enum: Derive the MAC address from the upstream port */ 11876 #define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0 11877 11878 /* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */ 11879 #define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0 11880 11881 11882 /***********************************/ 11883 /* MC_CMD_VADAPTOR_FREE 11884 * de-allocate a v-adaptor. 11885 */ 11886 #define MC_CMD_VADAPTOR_FREE 0x99 11887 #undef MC_CMD_0x99_PRIVILEGE_CTG 11888 11889 #define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11890 11891 /* MC_CMD_VADAPTOR_FREE_IN msgrequest */ 11892 #define MC_CMD_VADAPTOR_FREE_IN_LEN 4 11893 /* The port to which the v-adaptor is connected. */ 11894 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0 11895 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_LEN 4 11896 11897 /* MC_CMD_VADAPTOR_FREE_OUT msgresponse */ 11898 #define MC_CMD_VADAPTOR_FREE_OUT_LEN 0 11899 11900 11901 /***********************************/ 11902 /* MC_CMD_VADAPTOR_SET_MAC 11903 * assign a new MAC address to a v-adaptor. 11904 */ 11905 #define MC_CMD_VADAPTOR_SET_MAC 0x5d 11906 #undef MC_CMD_0x5d_PRIVILEGE_CTG 11907 11908 #define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11909 11910 /* MC_CMD_VADAPTOR_SET_MAC_IN msgrequest */ 11911 #define MC_CMD_VADAPTOR_SET_MAC_IN_LEN 10 11912 /* The port to which the v-adaptor is connected. */ 11913 #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 11914 #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_LEN 4 11915 /* The new MAC address to assign to this v-adaptor */ 11916 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4 11917 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_LEN 6 11918 11919 /* MC_CMD_VADAPTOR_SET_MAC_OUT msgresponse */ 11920 #define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0 11921 11922 11923 /***********************************/ 11924 /* MC_CMD_VADAPTOR_GET_MAC 11925 * read the MAC address assigned to a v-adaptor. 11926 */ 11927 #define MC_CMD_VADAPTOR_GET_MAC 0x5e 11928 #undef MC_CMD_0x5e_PRIVILEGE_CTG 11929 11930 #define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11931 11932 /* MC_CMD_VADAPTOR_GET_MAC_IN msgrequest */ 11933 #define MC_CMD_VADAPTOR_GET_MAC_IN_LEN 4 11934 /* The port to which the v-adaptor is connected. */ 11935 #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 11936 #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_LEN 4 11937 11938 /* MC_CMD_VADAPTOR_GET_MAC_OUT msgresponse */ 11939 #define MC_CMD_VADAPTOR_GET_MAC_OUT_LEN 6 11940 /* The MAC address assigned to this v-adaptor */ 11941 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0 11942 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_LEN 6 11943 11944 11945 /***********************************/ 11946 /* MC_CMD_VADAPTOR_QUERY 11947 * read some config of v-adaptor. 11948 */ 11949 #define MC_CMD_VADAPTOR_QUERY 0x61 11950 #undef MC_CMD_0x61_PRIVILEGE_CTG 11951 11952 #define MC_CMD_0x61_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11953 11954 /* MC_CMD_VADAPTOR_QUERY_IN msgrequest */ 11955 #define MC_CMD_VADAPTOR_QUERY_IN_LEN 4 11956 /* The port to which the v-adaptor is connected. */ 11957 #define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_OFST 0 11958 #define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_LEN 4 11959 11960 /* MC_CMD_VADAPTOR_QUERY_OUT msgresponse */ 11961 #define MC_CMD_VADAPTOR_QUERY_OUT_LEN 12 11962 /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */ 11963 #define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_OFST 0 11964 #define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_LEN 4 11965 /* The v-adaptor flags as defined at MC_CMD_VADAPTOR_ALLOC. */ 11966 #define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_OFST 4 11967 #define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_LEN 4 11968 /* The number of VLAN tags that may still be added */ 11969 #define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 8 11970 #define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4 11971 11972 11973 /***********************************/ 11974 /* MC_CMD_EVB_PORT_ASSIGN 11975 * assign a port to a PCI function. 11976 */ 11977 #define MC_CMD_EVB_PORT_ASSIGN 0x9a 11978 #undef MC_CMD_0x9a_PRIVILEGE_CTG 11979 11980 #define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11981 11982 /* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */ 11983 #define MC_CMD_EVB_PORT_ASSIGN_IN_LEN 8 11984 /* The port to assign. */ 11985 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0 11986 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_LEN 4 11987 /* The target function to modify. */ 11988 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4 11989 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_LEN 4 11990 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0 11991 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16 11992 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16 11993 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16 11994 11995 /* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */ 11996 #define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0 11997 11998 11999 /***********************************/ 12000 /* MC_CMD_RDWR_A64_REGIONS 12001 * Assign the 64 bit region addresses. 12002 */ 12003 #define MC_CMD_RDWR_A64_REGIONS 0x9b 12004 #undef MC_CMD_0x9b_PRIVILEGE_CTG 12005 12006 #define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12007 12008 /* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */ 12009 #define MC_CMD_RDWR_A64_REGIONS_IN_LEN 17 12010 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0 12011 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_LEN 4 12012 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4 12013 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_LEN 4 12014 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8 12015 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_LEN 4 12016 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12 12017 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_LEN 4 12018 /* Write enable bits 0-3, set to write, clear to read. */ 12019 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128 12020 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4 12021 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 16 12022 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1 12023 12024 /* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included 12025 * regardless of state of write bits in the request. 12026 */ 12027 #define MC_CMD_RDWR_A64_REGIONS_OUT_LEN 16 12028 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0 12029 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_LEN 4 12030 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4 12031 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_LEN 4 12032 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8 12033 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_LEN 4 12034 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12 12035 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_LEN 4 12036 12037 12038 /***********************************/ 12039 /* MC_CMD_ONLOAD_STACK_ALLOC 12040 * Allocate an Onload stack ID. 12041 */ 12042 #define MC_CMD_ONLOAD_STACK_ALLOC 0x9c 12043 #undef MC_CMD_0x9c_PRIVILEGE_CTG 12044 12045 #define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 12046 12047 /* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */ 12048 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4 12049 /* The handle of the owning upstream port */ 12050 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 12051 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 12052 12053 /* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */ 12054 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4 12055 /* The handle of the new Onload stack */ 12056 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0 12057 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_LEN 4 12058 12059 12060 /***********************************/ 12061 /* MC_CMD_ONLOAD_STACK_FREE 12062 * Free an Onload stack ID. 12063 */ 12064 #define MC_CMD_ONLOAD_STACK_FREE 0x9d 12065 #undef MC_CMD_0x9d_PRIVILEGE_CTG 12066 12067 #define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 12068 12069 /* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */ 12070 #define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4 12071 /* The handle of the Onload stack */ 12072 #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0 12073 #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_LEN 4 12074 12075 /* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */ 12076 #define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0 12077 12078 12079 /***********************************/ 12080 /* MC_CMD_RSS_CONTEXT_ALLOC 12081 * Allocate an RSS context. 12082 */ 12083 #define MC_CMD_RSS_CONTEXT_ALLOC 0x9e 12084 #undef MC_CMD_0x9e_PRIVILEGE_CTG 12085 12086 #define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12087 12088 /* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */ 12089 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12 12090 /* The handle of the owning upstream port */ 12091 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 12092 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 12093 /* The type of context to allocate */ 12094 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4 12095 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_LEN 4 12096 /* enum: Allocate a context for exclusive use. The key and indirection table 12097 * must be explicitly configured. 12098 */ 12099 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0 12100 /* enum: Allocate a context for shared use; this will spread across a range of 12101 * queues, but the key and indirection table are pre-configured and may not be 12102 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64. 12103 */ 12104 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1 12105 /* Number of queues spanned by this context, in the range 1-64; valid offsets 12106 * in the indirection table will be in the range 0 to NUM_QUEUES-1. 12107 */ 12108 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8 12109 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_LEN 4 12110 12111 /* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */ 12112 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4 12113 /* The handle of the new RSS context. This should be considered opaque to the 12114 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid 12115 * handle. 12116 */ 12117 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0 12118 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_LEN 4 12119 /* enum: guaranteed invalid RSS context handle value */ 12120 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff 12121 12122 12123 /***********************************/ 12124 /* MC_CMD_RSS_CONTEXT_FREE 12125 * Free an RSS context. 12126 */ 12127 #define MC_CMD_RSS_CONTEXT_FREE 0x9f 12128 #undef MC_CMD_0x9f_PRIVILEGE_CTG 12129 12130 #define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12131 12132 /* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */ 12133 #define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4 12134 /* The handle of the RSS context */ 12135 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0 12136 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_LEN 4 12137 12138 /* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */ 12139 #define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0 12140 12141 12142 /***********************************/ 12143 /* MC_CMD_RSS_CONTEXT_SET_KEY 12144 * Set the Toeplitz hash key for an RSS context. 12145 */ 12146 #define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0 12147 #undef MC_CMD_0xa0_PRIVILEGE_CTG 12148 12149 #define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12150 12151 /* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */ 12152 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44 12153 /* The handle of the RSS context */ 12154 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0 12155 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_LEN 4 12156 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 12157 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4 12158 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40 12159 12160 /* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */ 12161 #define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0 12162 12163 12164 /***********************************/ 12165 /* MC_CMD_RSS_CONTEXT_GET_KEY 12166 * Get the Toeplitz hash key for an RSS context. 12167 */ 12168 #define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1 12169 #undef MC_CMD_0xa1_PRIVILEGE_CTG 12170 12171 #define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12172 12173 /* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */ 12174 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4 12175 /* The handle of the RSS context */ 12176 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0 12177 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_LEN 4 12178 12179 /* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */ 12180 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44 12181 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 12182 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4 12183 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40 12184 12185 12186 /***********************************/ 12187 /* MC_CMD_RSS_CONTEXT_SET_TABLE 12188 * Set the indirection table for an RSS context. 12189 */ 12190 #define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2 12191 #undef MC_CMD_0xa2_PRIVILEGE_CTG 12192 12193 #define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12194 12195 /* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */ 12196 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132 12197 /* The handle of the RSS context */ 12198 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 12199 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_LEN 4 12200 /* The 128-byte indirection table (1 byte per entry) */ 12201 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4 12202 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128 12203 12204 /* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */ 12205 #define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0 12206 12207 12208 /***********************************/ 12209 /* MC_CMD_RSS_CONTEXT_GET_TABLE 12210 * Get the indirection table for an RSS context. 12211 */ 12212 #define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3 12213 #undef MC_CMD_0xa3_PRIVILEGE_CTG 12214 12215 #define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12216 12217 /* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */ 12218 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4 12219 /* The handle of the RSS context */ 12220 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 12221 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_LEN 4 12222 12223 /* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */ 12224 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132 12225 /* The 128-byte indirection table (1 byte per entry) */ 12226 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4 12227 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128 12228 12229 12230 /***********************************/ 12231 /* MC_CMD_RSS_CONTEXT_SET_FLAGS 12232 * Set various control flags for an RSS context. 12233 */ 12234 #define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1 12235 #undef MC_CMD_0xe1_PRIVILEGE_CTG 12236 12237 #define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12238 12239 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */ 12240 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8 12241 /* The handle of the RSS context */ 12242 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 12243 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4 12244 /* Hash control flags. The _EN bits are always supported, but new modes are 12245 * available when ADDITIONAL_RSS_MODES is reported by MC_CMD_GET_CAPABILITIES: 12246 * in this case, the MODE fields may be set to non-zero values, and will take 12247 * effect regardless of the settings of the _EN flags. See the RSS_MODE 12248 * structure for the meaning of the mode bits. Drivers must check the 12249 * capability before trying to set any _MODE fields, as older firmware will 12250 * reject any attempt to set the FLAGS field to a value > 0xff with EINVAL. In 12251 * the case where all the _MODE flags are zero, the _EN flags take effect, 12252 * providing backward compatibility for existing drivers. (Setting all _MODE 12253 * *and* all _EN flags to zero is valid, to disable RSS spreading for that 12254 * particular packet type.) 12255 */ 12256 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4 12257 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_LEN 4 12258 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0 12259 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1 12260 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1 12261 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1 12262 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2 12263 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1 12264 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3 12265 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1 12266 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4 12267 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4 12268 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN 8 12269 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4 12270 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_LBN 12 12271 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4 12272 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN 16 12273 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4 12274 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN 20 12275 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4 12276 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_LBN 24 12277 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4 12278 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN 28 12279 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4 12280 12281 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */ 12282 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0 12283 12284 12285 /***********************************/ 12286 /* MC_CMD_RSS_CONTEXT_GET_FLAGS 12287 * Get various control flags for an RSS context. 12288 */ 12289 #define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2 12290 #undef MC_CMD_0xe2_PRIVILEGE_CTG 12291 12292 #define MC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12293 12294 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */ 12295 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4 12296 /* The handle of the RSS context */ 12297 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 12298 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4 12299 12300 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */ 12301 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8 12302 /* Hash control flags. If all _MODE bits are zero (which will always be true 12303 * for older firmware which does not report the ADDITIONAL_RSS_MODES 12304 * capability), the _EN bits report the state. If any _MODE bits are non-zero 12305 * (which will only be true when the firmware reports ADDITIONAL_RSS_MODES) 12306 * then the _EN bits should be disregarded, although the _MODE flags are 12307 * guaranteed to be consistent with the _EN flags for a freshly-allocated RSS 12308 * context and in the case where the _EN flags were used in the SET. This 12309 * provides backward compatibility: old drivers will not be attempting to 12310 * derive any meaning from the _MODE bits (and can never set them to any value 12311 * not representable by the _EN bits); new drivers can always determine the 12312 * mode by looking only at the _MODE bits; the value returned by a GET can 12313 * always be used for a SET regardless of old/new driver vs. old/new firmware. 12314 */ 12315 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4 12316 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_LEN 4 12317 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0 12318 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1 12319 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1 12320 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1 12321 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2 12322 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1 12323 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3 12324 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1 12325 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4 12326 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4 12327 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN 8 12328 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4 12329 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN 12 12330 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4 12331 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN 16 12332 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4 12333 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN 20 12334 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4 12335 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN 24 12336 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4 12337 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN 28 12338 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4 12339 12340 12341 /***********************************/ 12342 /* MC_CMD_DOT1P_MAPPING_ALLOC 12343 * Allocate a .1p mapping. 12344 */ 12345 #define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4 12346 #undef MC_CMD_0xa4_PRIVILEGE_CTG 12347 12348 #define MC_CMD_0xa4_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12349 12350 /* MC_CMD_DOT1P_MAPPING_ALLOC_IN msgrequest */ 12351 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_LEN 8 12352 /* The handle of the owning upstream port */ 12353 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 12354 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 12355 /* Number of queues spanned by this mapping, in the range 1-64; valid fixed 12356 * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and 12357 * referenced RSS contexts must span no more than this number. 12358 */ 12359 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4 12360 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_LEN 4 12361 12362 /* MC_CMD_DOT1P_MAPPING_ALLOC_OUT msgresponse */ 12363 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4 12364 /* The handle of the new .1p mapping. This should be considered opaque to the 12365 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid 12366 * handle. 12367 */ 12368 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0 12369 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_LEN 4 12370 /* enum: guaranteed invalid .1p mapping handle value */ 12371 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_INVALID 0xffffffff 12372 12373 12374 /***********************************/ 12375 /* MC_CMD_DOT1P_MAPPING_FREE 12376 * Free a .1p mapping. 12377 */ 12378 #define MC_CMD_DOT1P_MAPPING_FREE 0xa5 12379 #undef MC_CMD_0xa5_PRIVILEGE_CTG 12380 12381 #define MC_CMD_0xa5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12382 12383 /* MC_CMD_DOT1P_MAPPING_FREE_IN msgrequest */ 12384 #define MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4 12385 /* The handle of the .1p mapping */ 12386 #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0 12387 #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_LEN 4 12388 12389 /* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */ 12390 #define MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0 12391 12392 12393 /***********************************/ 12394 /* MC_CMD_DOT1P_MAPPING_SET_TABLE 12395 * Set the mapping table for a .1p mapping. 12396 */ 12397 #define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6 12398 #undef MC_CMD_0xa6_PRIVILEGE_CTG 12399 12400 #define MC_CMD_0xa6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12401 12402 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_IN msgrequest */ 12403 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_LEN 36 12404 /* The handle of the .1p mapping */ 12405 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 12406 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_LEN 4 12407 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 12408 * handle) 12409 */ 12410 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4 12411 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_LEN 32 12412 12413 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT msgresponse */ 12414 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0 12415 12416 12417 /***********************************/ 12418 /* MC_CMD_DOT1P_MAPPING_GET_TABLE 12419 * Get the mapping table for a .1p mapping. 12420 */ 12421 #define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7 12422 #undef MC_CMD_0xa7_PRIVILEGE_CTG 12423 12424 #define MC_CMD_0xa7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12425 12426 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_IN msgrequest */ 12427 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4 12428 /* The handle of the .1p mapping */ 12429 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 12430 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_LEN 4 12431 12432 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT msgresponse */ 12433 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_LEN 36 12434 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 12435 * handle) 12436 */ 12437 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4 12438 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_LEN 32 12439 12440 12441 /***********************************/ 12442 /* MC_CMD_GET_VECTOR_CFG 12443 * Get Interrupt Vector config for this PF. 12444 */ 12445 #define MC_CMD_GET_VECTOR_CFG 0xbf 12446 #undef MC_CMD_0xbf_PRIVILEGE_CTG 12447 12448 #define MC_CMD_0xbf_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12449 12450 /* MC_CMD_GET_VECTOR_CFG_IN msgrequest */ 12451 #define MC_CMD_GET_VECTOR_CFG_IN_LEN 0 12452 12453 /* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */ 12454 #define MC_CMD_GET_VECTOR_CFG_OUT_LEN 12 12455 /* Base absolute interrupt vector number. */ 12456 #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0 12457 #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_LEN 4 12458 /* Number of interrupt vectors allocate to this PF. */ 12459 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4 12460 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_LEN 4 12461 /* Number of interrupt vectors to allocate per VF. */ 12462 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8 12463 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_LEN 4 12464 12465 12466 /***********************************/ 12467 /* MC_CMD_SET_VECTOR_CFG 12468 * Set Interrupt Vector config for this PF. 12469 */ 12470 #define MC_CMD_SET_VECTOR_CFG 0xc0 12471 #undef MC_CMD_0xc0_PRIVILEGE_CTG 12472 12473 #define MC_CMD_0xc0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12474 12475 /* MC_CMD_SET_VECTOR_CFG_IN msgrequest */ 12476 #define MC_CMD_SET_VECTOR_CFG_IN_LEN 12 12477 /* Base absolute interrupt vector number, or MC_CMD_RESOURCE_INSTANCE_ANY to 12478 * let the system find a suitable base. 12479 */ 12480 #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0 12481 #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_LEN 4 12482 /* Number of interrupt vectors allocate to this PF. */ 12483 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4 12484 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_LEN 4 12485 /* Number of interrupt vectors to allocate per VF. */ 12486 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8 12487 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_LEN 4 12488 12489 /* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */ 12490 #define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0 12491 12492 12493 /***********************************/ 12494 /* MC_CMD_VPORT_ADD_MAC_ADDRESS 12495 * Add a MAC address to a v-port 12496 */ 12497 #define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8 12498 #undef MC_CMD_0xa8_PRIVILEGE_CTG 12499 12500 #define MC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12501 12502 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */ 12503 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10 12504 /* The handle of the v-port */ 12505 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0 12506 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_LEN 4 12507 /* MAC address to add */ 12508 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4 12509 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6 12510 12511 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */ 12512 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0 12513 12514 12515 /***********************************/ 12516 /* MC_CMD_VPORT_DEL_MAC_ADDRESS 12517 * Delete a MAC address from a v-port 12518 */ 12519 #define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9 12520 #undef MC_CMD_0xa9_PRIVILEGE_CTG 12521 12522 #define MC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12523 12524 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */ 12525 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10 12526 /* The handle of the v-port */ 12527 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0 12528 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_LEN 4 12529 /* MAC address to add */ 12530 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4 12531 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6 12532 12533 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */ 12534 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0 12535 12536 12537 /***********************************/ 12538 /* MC_CMD_VPORT_GET_MAC_ADDRESSES 12539 * Delete a MAC address from a v-port 12540 */ 12541 #define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa 12542 #undef MC_CMD_0xaa_PRIVILEGE_CTG 12543 12544 #define MC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12545 12546 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */ 12547 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4 12548 /* The handle of the v-port */ 12549 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0 12550 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_LEN 4 12551 12552 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */ 12553 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4 12554 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250 12555 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num)) 12556 /* The number of MAC addresses returned */ 12557 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0 12558 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_LEN 4 12559 /* Array of MAC addresses */ 12560 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4 12561 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6 12562 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0 12563 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41 12564 12565 12566 /***********************************/ 12567 /* MC_CMD_VPORT_RECONFIGURE 12568 * Replace VLAN tags and/or MAC addresses of an existing v-port. If the v-port 12569 * has already been passed to another function (v-port's user), then that 12570 * function will be reset before applying the changes. 12571 */ 12572 #define MC_CMD_VPORT_RECONFIGURE 0xeb 12573 #undef MC_CMD_0xeb_PRIVILEGE_CTG 12574 12575 #define MC_CMD_0xeb_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12576 12577 /* MC_CMD_VPORT_RECONFIGURE_IN msgrequest */ 12578 #define MC_CMD_VPORT_RECONFIGURE_IN_LEN 44 12579 /* The handle of the v-port */ 12580 #define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_OFST 0 12581 #define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_LEN 4 12582 /* Flags requesting what should be changed. */ 12583 #define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 4 12584 #define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_LEN 4 12585 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 0 12586 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_WIDTH 1 12587 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_LBN 1 12588 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_WIDTH 1 12589 /* The number of VLAN tags to insert/remove. An error will be returned if 12590 * incompatible with the number of VLAN tags specified for the upstream 12591 * v-switch. 12592 */ 12593 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_OFST 8 12594 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_LEN 4 12595 /* The actual VLAN tags to insert/remove */ 12596 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_OFST 12 12597 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_LEN 4 12598 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 0 12599 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_WIDTH 16 12600 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_LBN 16 12601 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_WIDTH 16 12602 /* The number of MAC addresses to add */ 12603 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_OFST 16 12604 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_LEN 4 12605 /* MAC addresses to add */ 12606 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_OFST 20 12607 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_LEN 6 12608 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_NUM 4 12609 12610 /* MC_CMD_VPORT_RECONFIGURE_OUT msgresponse */ 12611 #define MC_CMD_VPORT_RECONFIGURE_OUT_LEN 4 12612 #define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 0 12613 #define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_LEN 4 12614 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0 12615 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_WIDTH 1 12616 12617 12618 /***********************************/ 12619 /* MC_CMD_EVB_PORT_QUERY 12620 * read some config of v-port. 12621 */ 12622 #define MC_CMD_EVB_PORT_QUERY 0x62 12623 #undef MC_CMD_0x62_PRIVILEGE_CTG 12624 12625 #define MC_CMD_0x62_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12626 12627 /* MC_CMD_EVB_PORT_QUERY_IN msgrequest */ 12628 #define MC_CMD_EVB_PORT_QUERY_IN_LEN 4 12629 /* The handle of the v-port */ 12630 #define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_OFST 0 12631 #define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_LEN 4 12632 12633 /* MC_CMD_EVB_PORT_QUERY_OUT msgresponse */ 12634 #define MC_CMD_EVB_PORT_QUERY_OUT_LEN 8 12635 /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */ 12636 #define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_OFST 0 12637 #define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_LEN 4 12638 /* The number of VLAN tags that may be used on a v-adaptor connected to this 12639 * EVB port. 12640 */ 12641 #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 4 12642 #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4 12643 12644 12645 /***********************************/ 12646 /* MC_CMD_DUMP_BUFTBL_ENTRIES 12647 * Dump buffer table entries, mainly for command client debug use. Dumps 12648 * absolute entries, and does not use chunk handles. All entries must be in 12649 * range, and used for q page mapping, Although the latter restriction may be 12650 * lifted in future. 12651 */ 12652 #define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab 12653 #undef MC_CMD_0xab_PRIVILEGE_CTG 12654 12655 #define MC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_INSECURE 12656 12657 /* MC_CMD_DUMP_BUFTBL_ENTRIES_IN msgrequest */ 12658 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_LEN 8 12659 /* Index of the first buffer table entry. */ 12660 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0 12661 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4 12662 /* Number of buffer table entries to dump. */ 12663 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4 12664 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4 12665 12666 /* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */ 12667 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12 12668 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252 12669 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num)) 12670 /* Raw buffer table entries, layed out as BUFTBL_ENTRY. */ 12671 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0 12672 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12 12673 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1 12674 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21 12675 12676 12677 /***********************************/ 12678 /* MC_CMD_SET_RXDP_CONFIG 12679 * Set global RXDP configuration settings 12680 */ 12681 #define MC_CMD_SET_RXDP_CONFIG 0xc1 12682 #undef MC_CMD_0xc1_PRIVILEGE_CTG 12683 12684 #define MC_CMD_0xc1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12685 12686 /* MC_CMD_SET_RXDP_CONFIG_IN msgrequest */ 12687 #define MC_CMD_SET_RXDP_CONFIG_IN_LEN 4 12688 #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0 12689 #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_LEN 4 12690 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0 12691 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1 12692 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_LBN 1 12693 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_WIDTH 2 12694 /* enum: pad to 64 bytes */ 12695 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64 0x0 12696 /* enum: pad to 128 bytes (Medford only) */ 12697 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128 0x1 12698 /* enum: pad to 256 bytes (Medford only) */ 12699 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256 0x2 12700 12701 /* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */ 12702 #define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0 12703 12704 12705 /***********************************/ 12706 /* MC_CMD_GET_RXDP_CONFIG 12707 * Get global RXDP configuration settings 12708 */ 12709 #define MC_CMD_GET_RXDP_CONFIG 0xc2 12710 #undef MC_CMD_0xc2_PRIVILEGE_CTG 12711 12712 #define MC_CMD_0xc2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12713 12714 /* MC_CMD_GET_RXDP_CONFIG_IN msgrequest */ 12715 #define MC_CMD_GET_RXDP_CONFIG_IN_LEN 0 12716 12717 /* MC_CMD_GET_RXDP_CONFIG_OUT msgresponse */ 12718 #define MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4 12719 #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0 12720 #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_LEN 4 12721 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0 12722 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1 12723 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_LBN 1 12724 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_WIDTH 2 12725 /* Enum values, see field(s): */ 12726 /* MC_CMD_SET_RXDP_CONFIG/MC_CMD_SET_RXDP_CONFIG_IN/PAD_HOST_LEN */ 12727 12728 12729 /***********************************/ 12730 /* MC_CMD_GET_CLOCK 12731 * Return the system and PDCPU clock frequencies. 12732 */ 12733 #define MC_CMD_GET_CLOCK 0xac 12734 #undef MC_CMD_0xac_PRIVILEGE_CTG 12735 12736 #define MC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12737 12738 /* MC_CMD_GET_CLOCK_IN msgrequest */ 12739 #define MC_CMD_GET_CLOCK_IN_LEN 0 12740 12741 /* MC_CMD_GET_CLOCK_OUT msgresponse */ 12742 #define MC_CMD_GET_CLOCK_OUT_LEN 8 12743 /* System frequency, MHz */ 12744 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0 12745 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_LEN 4 12746 /* DPCPU frequency, MHz */ 12747 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4 12748 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_LEN 4 12749 12750 12751 /***********************************/ 12752 /* MC_CMD_SET_CLOCK 12753 * Control the system and DPCPU clock frequencies. Changes are lost reboot. 12754 */ 12755 #define MC_CMD_SET_CLOCK 0xad 12756 #undef MC_CMD_0xad_PRIVILEGE_CTG 12757 12758 #define MC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_INSECURE 12759 12760 /* MC_CMD_SET_CLOCK_IN msgrequest */ 12761 #define MC_CMD_SET_CLOCK_IN_LEN 28 12762 /* Requested frequency in MHz for system clock domain */ 12763 #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0 12764 #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_LEN 4 12765 /* enum: Leave the system clock domain frequency unchanged */ 12766 #define MC_CMD_SET_CLOCK_IN_SYS_DOMAIN_DONT_CHANGE 0x0 12767 /* Requested frequency in MHz for inter-core clock domain */ 12768 #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4 12769 #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_LEN 4 12770 /* enum: Leave the inter-core clock domain frequency unchanged */ 12771 #define MC_CMD_SET_CLOCK_IN_ICORE_DOMAIN_DONT_CHANGE 0x0 12772 /* Requested frequency in MHz for DPCPU clock domain */ 12773 #define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8 12774 #define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_LEN 4 12775 /* enum: Leave the DPCPU clock domain frequency unchanged */ 12776 #define MC_CMD_SET_CLOCK_IN_DPCPU_DOMAIN_DONT_CHANGE 0x0 12777 /* Requested frequency in MHz for PCS clock domain */ 12778 #define MC_CMD_SET_CLOCK_IN_PCS_FREQ_OFST 12 12779 #define MC_CMD_SET_CLOCK_IN_PCS_FREQ_LEN 4 12780 /* enum: Leave the PCS clock domain frequency unchanged */ 12781 #define MC_CMD_SET_CLOCK_IN_PCS_DOMAIN_DONT_CHANGE 0x0 12782 /* Requested frequency in MHz for MC clock domain */ 12783 #define MC_CMD_SET_CLOCK_IN_MC_FREQ_OFST 16 12784 #define MC_CMD_SET_CLOCK_IN_MC_FREQ_LEN 4 12785 /* enum: Leave the MC clock domain frequency unchanged */ 12786 #define MC_CMD_SET_CLOCK_IN_MC_DOMAIN_DONT_CHANGE 0x0 12787 /* Requested frequency in MHz for rmon clock domain */ 12788 #define MC_CMD_SET_CLOCK_IN_RMON_FREQ_OFST 20 12789 #define MC_CMD_SET_CLOCK_IN_RMON_FREQ_LEN 4 12790 /* enum: Leave the rmon clock domain frequency unchanged */ 12791 #define MC_CMD_SET_CLOCK_IN_RMON_DOMAIN_DONT_CHANGE 0x0 12792 /* Requested frequency in MHz for vswitch clock domain */ 12793 #define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_OFST 24 12794 #define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_LEN 4 12795 /* enum: Leave the vswitch clock domain frequency unchanged */ 12796 #define MC_CMD_SET_CLOCK_IN_VSWITCH_DOMAIN_DONT_CHANGE 0x0 12797 12798 /* MC_CMD_SET_CLOCK_OUT msgresponse */ 12799 #define MC_CMD_SET_CLOCK_OUT_LEN 28 12800 /* Resulting system frequency in MHz */ 12801 #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0 12802 #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_LEN 4 12803 /* enum: The system clock domain doesn't exist */ 12804 #define MC_CMD_SET_CLOCK_OUT_SYS_DOMAIN_UNSUPPORTED 0x0 12805 /* Resulting inter-core frequency in MHz */ 12806 #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4 12807 #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_LEN 4 12808 /* enum: The inter-core clock domain doesn't exist / isn't used */ 12809 #define MC_CMD_SET_CLOCK_OUT_ICORE_DOMAIN_UNSUPPORTED 0x0 12810 /* Resulting DPCPU frequency in MHz */ 12811 #define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8 12812 #define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_LEN 4 12813 /* enum: The dpcpu clock domain doesn't exist */ 12814 #define MC_CMD_SET_CLOCK_OUT_DPCPU_DOMAIN_UNSUPPORTED 0x0 12815 /* Resulting PCS frequency in MHz */ 12816 #define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_OFST 12 12817 #define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_LEN 4 12818 /* enum: The PCS clock domain doesn't exist / isn't controlled */ 12819 #define MC_CMD_SET_CLOCK_OUT_PCS_DOMAIN_UNSUPPORTED 0x0 12820 /* Resulting MC frequency in MHz */ 12821 #define MC_CMD_SET_CLOCK_OUT_MC_FREQ_OFST 16 12822 #define MC_CMD_SET_CLOCK_OUT_MC_FREQ_LEN 4 12823 /* enum: The MC clock domain doesn't exist / isn't controlled */ 12824 #define MC_CMD_SET_CLOCK_OUT_MC_DOMAIN_UNSUPPORTED 0x0 12825 /* Resulting rmon frequency in MHz */ 12826 #define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_OFST 20 12827 #define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_LEN 4 12828 /* enum: The rmon clock domain doesn't exist / isn't controlled */ 12829 #define MC_CMD_SET_CLOCK_OUT_RMON_DOMAIN_UNSUPPORTED 0x0 12830 /* Resulting vswitch frequency in MHz */ 12831 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_OFST 24 12832 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_LEN 4 12833 /* enum: The vswitch clock domain doesn't exist / isn't controlled */ 12834 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_DOMAIN_UNSUPPORTED 0x0 12835 12836 12837 /***********************************/ 12838 /* MC_CMD_DPCPU_RPC 12839 * Send an arbitrary DPCPU message. 12840 */ 12841 #define MC_CMD_DPCPU_RPC 0xae 12842 #undef MC_CMD_0xae_PRIVILEGE_CTG 12843 12844 #define MC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_INSECURE 12845 12846 /* MC_CMD_DPCPU_RPC_IN msgrequest */ 12847 #define MC_CMD_DPCPU_RPC_IN_LEN 36 12848 #define MC_CMD_DPCPU_RPC_IN_CPU_OFST 0 12849 #define MC_CMD_DPCPU_RPC_IN_CPU_LEN 4 12850 /* enum: RxDPCPU0 */ 12851 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX0 0x0 12852 /* enum: TxDPCPU0 */ 12853 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1 12854 /* enum: TxDPCPU1 */ 12855 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2 12856 /* enum: RxDPCPU1 (Medford only) */ 12857 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX1 0x3 12858 /* enum: RxDPCPU (will be for the calling function; for now, just an alias of 12859 * DPCPU_RX0) 12860 */ 12861 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x80 12862 /* enum: TxDPCPU (will be for the calling function; for now, just an alias of 12863 * DPCPU_TX0) 12864 */ 12865 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX 0x81 12866 /* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be 12867 * initialised to zero 12868 */ 12869 #define MC_CMD_DPCPU_RPC_IN_DATA_OFST 4 12870 #define MC_CMD_DPCPU_RPC_IN_DATA_LEN 32 12871 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8 12872 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8 12873 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */ 12874 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */ 12875 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */ 12876 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */ 12877 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */ 12878 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */ 12879 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */ 12880 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */ 12881 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */ 12882 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16 12883 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16 12884 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16 12885 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16 12886 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48 12887 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16 12888 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16 12889 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240 12890 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16 12891 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16 12892 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */ 12893 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */ 12894 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */ 12895 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */ 12896 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */ 12897 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48 12898 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16 12899 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64 12900 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16 12901 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80 12902 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16 12903 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16 12904 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16 12905 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */ 12906 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */ 12907 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */ 12908 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64 12909 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16 12910 #define MC_CMD_DPCPU_RPC_IN_WDATA_OFST 12 12911 #define MC_CMD_DPCPU_RPC_IN_WDATA_LEN 24 12912 /* Register data to write. Only valid in write/write-read. */ 12913 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_OFST 16 12914 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_LEN 4 12915 /* Register address. */ 12916 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_OFST 20 12917 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_LEN 4 12918 12919 /* MC_CMD_DPCPU_RPC_OUT msgresponse */ 12920 #define MC_CMD_DPCPU_RPC_OUT_LEN 36 12921 #define MC_CMD_DPCPU_RPC_OUT_RC_OFST 0 12922 #define MC_CMD_DPCPU_RPC_OUT_RC_LEN 4 12923 /* DATA */ 12924 #define MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4 12925 #define MC_CMD_DPCPU_RPC_OUT_DATA_LEN 32 12926 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32 12927 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16 12928 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48 12929 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16 12930 #define MC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12 12931 #define MC_CMD_DPCPU_RPC_OUT_RDATA_LEN 24 12932 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_OFST 12 12933 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_LEN 4 12934 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_OFST 16 12935 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_LEN 4 12936 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_OFST 20 12937 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_LEN 4 12938 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24 12939 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_LEN 4 12940 12941 12942 /***********************************/ 12943 /* MC_CMD_TRIGGER_INTERRUPT 12944 * Trigger an interrupt by prodding the BIU. 12945 */ 12946 #define MC_CMD_TRIGGER_INTERRUPT 0xe3 12947 #undef MC_CMD_0xe3_PRIVILEGE_CTG 12948 12949 #define MC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12950 12951 /* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */ 12952 #define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4 12953 /* Interrupt level relative to base for function. */ 12954 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0 12955 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_LEN 4 12956 12957 /* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */ 12958 #define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0 12959 12960 12961 /***********************************/ 12962 /* MC_CMD_SHMBOOT_OP 12963 * Special operations to support (for now) shmboot. 12964 */ 12965 #define MC_CMD_SHMBOOT_OP 0xe6 12966 #undef MC_CMD_0xe6_PRIVILEGE_CTG 12967 12968 #define MC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 12969 12970 /* MC_CMD_SHMBOOT_OP_IN msgrequest */ 12971 #define MC_CMD_SHMBOOT_OP_IN_LEN 4 12972 /* Identifies the operation to perform */ 12973 #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 0 12974 #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_LEN 4 12975 /* enum: Copy slave_data section to the slave core. (Greenport only) */ 12976 #define MC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA 0x0 12977 12978 /* MC_CMD_SHMBOOT_OP_OUT msgresponse */ 12979 #define MC_CMD_SHMBOOT_OP_OUT_LEN 0 12980 12981 12982 /***********************************/ 12983 /* MC_CMD_CAP_BLK_READ 12984 * Read multiple 64bit words from capture block memory 12985 */ 12986 #define MC_CMD_CAP_BLK_READ 0xe7 12987 #undef MC_CMD_0xe7_PRIVILEGE_CTG 12988 12989 #define MC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_INSECURE 12990 12991 /* MC_CMD_CAP_BLK_READ_IN msgrequest */ 12992 #define MC_CMD_CAP_BLK_READ_IN_LEN 12 12993 #define MC_CMD_CAP_BLK_READ_IN_CAP_REG_OFST 0 12994 #define MC_CMD_CAP_BLK_READ_IN_CAP_REG_LEN 4 12995 #define MC_CMD_CAP_BLK_READ_IN_ADDR_OFST 4 12996 #define MC_CMD_CAP_BLK_READ_IN_ADDR_LEN 4 12997 #define MC_CMD_CAP_BLK_READ_IN_COUNT_OFST 8 12998 #define MC_CMD_CAP_BLK_READ_IN_COUNT_LEN 4 12999 13000 /* MC_CMD_CAP_BLK_READ_OUT msgresponse */ 13001 #define MC_CMD_CAP_BLK_READ_OUT_LENMIN 8 13002 #define MC_CMD_CAP_BLK_READ_OUT_LENMAX 248 13003 #define MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num)) 13004 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0 13005 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8 13006 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0 13007 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4 13008 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1 13009 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31 13010 13011 13012 /***********************************/ 13013 /* MC_CMD_DUMP_DO 13014 * Take a dump of the DUT state 13015 */ 13016 #define MC_CMD_DUMP_DO 0xe8 13017 #undef MC_CMD_0xe8_PRIVILEGE_CTG 13018 13019 #define MC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_INSECURE 13020 13021 /* MC_CMD_DUMP_DO_IN msgrequest */ 13022 #define MC_CMD_DUMP_DO_IN_LEN 52 13023 #define MC_CMD_DUMP_DO_IN_PADDING_OFST 0 13024 #define MC_CMD_DUMP_DO_IN_PADDING_LEN 4 13025 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4 13026 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_LEN 4 13027 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */ 13028 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */ 13029 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 13030 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4 13031 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */ 13032 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */ 13033 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */ 13034 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */ 13035 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 13036 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4 13037 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 13038 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4 13039 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 13040 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4 13041 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 13042 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4 13043 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 13044 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4 13045 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */ 13046 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 13047 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4 13048 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 13049 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4 13050 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */ 13051 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 13052 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4 13053 /* enum: The uart port this command was received over (if using a uart 13054 * transport) 13055 */ 13056 #define MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff 13057 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 13058 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4 13059 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28 13060 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_LEN 4 13061 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */ 13062 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */ 13063 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 13064 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4 13065 /* Enum values, see field(s): */ 13066 /* MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 13067 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 13068 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4 13069 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 13070 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4 13071 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 13072 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4 13073 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 13074 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4 13075 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 13076 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4 13077 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 13078 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4 13079 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 13080 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4 13081 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 13082 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4 13083 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 13084 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4 13085 13086 /* MC_CMD_DUMP_DO_OUT msgresponse */ 13087 #define MC_CMD_DUMP_DO_OUT_LEN 4 13088 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0 13089 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_LEN 4 13090 13091 13092 /***********************************/ 13093 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED 13094 * Configure unsolicited dumps 13095 */ 13096 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9 13097 #undef MC_CMD_0xe9_PRIVILEGE_CTG 13098 13099 #define MC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_INSECURE 13100 13101 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN msgrequest */ 13102 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_LEN 52 13103 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0 13104 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_LEN 4 13105 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4 13106 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_LEN 4 13107 /* Enum values, see field(s): */ 13108 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC */ 13109 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 13110 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4 13111 /* Enum values, see field(s): */ 13112 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 13113 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 13114 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4 13115 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 13116 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4 13117 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 13118 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4 13119 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 13120 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4 13121 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 13122 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4 13123 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 13124 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4 13125 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 13126 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4 13127 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 13128 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4 13129 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 13130 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4 13131 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_OFST 28 13132 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_LEN 4 13133 /* Enum values, see field(s): */ 13134 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPFILE_DST */ 13135 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 13136 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4 13137 /* Enum values, see field(s): */ 13138 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 13139 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 13140 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4 13141 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 13142 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4 13143 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 13144 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4 13145 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 13146 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4 13147 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 13148 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4 13149 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 13150 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4 13151 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 13152 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4 13153 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 13154 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4 13155 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 13156 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4 13157 13158 13159 /***********************************/ 13160 /* MC_CMD_SET_PSU 13161 * Adjusts power supply parameters. This is a warranty-voiding operation. 13162 * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if 13163 * the parameter is out of range. 13164 */ 13165 #define MC_CMD_SET_PSU 0xea 13166 #undef MC_CMD_0xea_PRIVILEGE_CTG 13167 13168 #define MC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_INSECURE 13169 13170 /* MC_CMD_SET_PSU_IN msgrequest */ 13171 #define MC_CMD_SET_PSU_IN_LEN 12 13172 #define MC_CMD_SET_PSU_IN_PARAM_OFST 0 13173 #define MC_CMD_SET_PSU_IN_PARAM_LEN 4 13174 #define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */ 13175 #define MC_CMD_SET_PSU_IN_RAIL_OFST 4 13176 #define MC_CMD_SET_PSU_IN_RAIL_LEN 4 13177 #define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */ 13178 #define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */ 13179 /* desired value, eg voltage in mV */ 13180 #define MC_CMD_SET_PSU_IN_VALUE_OFST 8 13181 #define MC_CMD_SET_PSU_IN_VALUE_LEN 4 13182 13183 /* MC_CMD_SET_PSU_OUT msgresponse */ 13184 #define MC_CMD_SET_PSU_OUT_LEN 0 13185 13186 13187 /***********************************/ 13188 /* MC_CMD_GET_FUNCTION_INFO 13189 * Get function information. PF and VF number. 13190 */ 13191 #define MC_CMD_GET_FUNCTION_INFO 0xec 13192 #undef MC_CMD_0xec_PRIVILEGE_CTG 13193 13194 #define MC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13195 13196 /* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */ 13197 #define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0 13198 13199 /* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */ 13200 #define MC_CMD_GET_FUNCTION_INFO_OUT_LEN 8 13201 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0 13202 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_LEN 4 13203 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4 13204 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_LEN 4 13205 13206 13207 /***********************************/ 13208 /* MC_CMD_ENABLE_OFFLINE_BIST 13209 * Enters offline BIST mode. All queues are torn down, chip enters quiescent 13210 * mode, calling function gets exclusive MCDI ownership. The only way out is 13211 * reboot. 13212 */ 13213 #define MC_CMD_ENABLE_OFFLINE_BIST 0xed 13214 #undef MC_CMD_0xed_PRIVILEGE_CTG 13215 13216 #define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 13217 13218 /* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */ 13219 #define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0 13220 13221 /* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */ 13222 #define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0 13223 13224 13225 /***********************************/ 13226 /* MC_CMD_UART_SEND_DATA 13227 * Send checksummed[sic] block of data over the uart. Response is a placeholder 13228 * should we wish to make this reliable; currently requests are fire-and- 13229 * forget. 13230 */ 13231 #define MC_CMD_UART_SEND_DATA 0xee 13232 #undef MC_CMD_0xee_PRIVILEGE_CTG 13233 13234 #define MC_CMD_0xee_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13235 13236 /* MC_CMD_UART_SEND_DATA_OUT msgrequest */ 13237 #define MC_CMD_UART_SEND_DATA_OUT_LENMIN 16 13238 #define MC_CMD_UART_SEND_DATA_OUT_LENMAX 252 13239 #define MC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num)) 13240 /* CRC32 over OFFSET, LENGTH, RESERVED, DATA */ 13241 #define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0 13242 #define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_LEN 4 13243 /* Offset at which to write the data */ 13244 #define MC_CMD_UART_SEND_DATA_OUT_OFFSET_OFST 4 13245 #define MC_CMD_UART_SEND_DATA_OUT_OFFSET_LEN 4 13246 /* Length of data */ 13247 #define MC_CMD_UART_SEND_DATA_OUT_LENGTH_OFST 8 13248 #define MC_CMD_UART_SEND_DATA_OUT_LENGTH_LEN 4 13249 /* Reserved for future use */ 13250 #define MC_CMD_UART_SEND_DATA_OUT_RESERVED_OFST 12 13251 #define MC_CMD_UART_SEND_DATA_OUT_RESERVED_LEN 4 13252 #define MC_CMD_UART_SEND_DATA_OUT_DATA_OFST 16 13253 #define MC_CMD_UART_SEND_DATA_OUT_DATA_LEN 1 13254 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0 13255 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM 236 13256 13257 /* MC_CMD_UART_SEND_DATA_IN msgresponse */ 13258 #define MC_CMD_UART_SEND_DATA_IN_LEN 0 13259 13260 13261 /***********************************/ 13262 /* MC_CMD_UART_RECV_DATA 13263 * Request checksummed[sic] block of data over the uart. Only a placeholder, 13264 * subject to change and not currently implemented. 13265 */ 13266 #define MC_CMD_UART_RECV_DATA 0xef 13267 #undef MC_CMD_0xef_PRIVILEGE_CTG 13268 13269 #define MC_CMD_0xef_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13270 13271 /* MC_CMD_UART_RECV_DATA_OUT msgrequest */ 13272 #define MC_CMD_UART_RECV_DATA_OUT_LEN 16 13273 /* CRC32 over OFFSET, LENGTH, RESERVED */ 13274 #define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_OFST 0 13275 #define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_LEN 4 13276 /* Offset from which to read the data */ 13277 #define MC_CMD_UART_RECV_DATA_OUT_OFFSET_OFST 4 13278 #define MC_CMD_UART_RECV_DATA_OUT_OFFSET_LEN 4 13279 /* Length of data */ 13280 #define MC_CMD_UART_RECV_DATA_OUT_LENGTH_OFST 8 13281 #define MC_CMD_UART_RECV_DATA_OUT_LENGTH_LEN 4 13282 /* Reserved for future use */ 13283 #define MC_CMD_UART_RECV_DATA_OUT_RESERVED_OFST 12 13284 #define MC_CMD_UART_RECV_DATA_OUT_RESERVED_LEN 4 13285 13286 /* MC_CMD_UART_RECV_DATA_IN msgresponse */ 13287 #define MC_CMD_UART_RECV_DATA_IN_LENMIN 16 13288 #define MC_CMD_UART_RECV_DATA_IN_LENMAX 252 13289 #define MC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num)) 13290 /* CRC32 over RESERVED1, RESERVED2, RESERVED3, DATA */ 13291 #define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0 13292 #define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_LEN 4 13293 /* Offset at which to write the data */ 13294 #define MC_CMD_UART_RECV_DATA_IN_RESERVED1_OFST 4 13295 #define MC_CMD_UART_RECV_DATA_IN_RESERVED1_LEN 4 13296 /* Length of data */ 13297 #define MC_CMD_UART_RECV_DATA_IN_RESERVED2_OFST 8 13298 #define MC_CMD_UART_RECV_DATA_IN_RESERVED2_LEN 4 13299 /* Reserved for future use */ 13300 #define MC_CMD_UART_RECV_DATA_IN_RESERVED3_OFST 12 13301 #define MC_CMD_UART_RECV_DATA_IN_RESERVED3_LEN 4 13302 #define MC_CMD_UART_RECV_DATA_IN_DATA_OFST 16 13303 #define MC_CMD_UART_RECV_DATA_IN_DATA_LEN 1 13304 #define MC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0 13305 #define MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM 236 13306 13307 13308 /***********************************/ 13309 /* MC_CMD_READ_FUSES 13310 * Read data programmed into the device One-Time-Programmable (OTP) Fuses 13311 */ 13312 #define MC_CMD_READ_FUSES 0xf0 13313 #undef MC_CMD_0xf0_PRIVILEGE_CTG 13314 13315 #define MC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_INSECURE 13316 13317 /* MC_CMD_READ_FUSES_IN msgrequest */ 13318 #define MC_CMD_READ_FUSES_IN_LEN 8 13319 /* Offset in OTP to read */ 13320 #define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0 13321 #define MC_CMD_READ_FUSES_IN_OFFSET_LEN 4 13322 /* Length of data to read in bytes */ 13323 #define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4 13324 #define MC_CMD_READ_FUSES_IN_LENGTH_LEN 4 13325 13326 /* MC_CMD_READ_FUSES_OUT msgresponse */ 13327 #define MC_CMD_READ_FUSES_OUT_LENMIN 4 13328 #define MC_CMD_READ_FUSES_OUT_LENMAX 252 13329 #define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num)) 13330 /* Length of returned OTP data in bytes */ 13331 #define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0 13332 #define MC_CMD_READ_FUSES_OUT_LENGTH_LEN 4 13333 /* Returned data */ 13334 #define MC_CMD_READ_FUSES_OUT_DATA_OFST 4 13335 #define MC_CMD_READ_FUSES_OUT_DATA_LEN 1 13336 #define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0 13337 #define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248 13338 13339 13340 /***********************************/ 13341 /* MC_CMD_KR_TUNE 13342 * Get or set KR Serdes RXEQ and TX Driver settings 13343 */ 13344 #define MC_CMD_KR_TUNE 0xf1 13345 #undef MC_CMD_0xf1_PRIVILEGE_CTG 13346 13347 #define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 13348 13349 /* MC_CMD_KR_TUNE_IN msgrequest */ 13350 #define MC_CMD_KR_TUNE_IN_LENMIN 4 13351 #define MC_CMD_KR_TUNE_IN_LENMAX 252 13352 #define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num)) 13353 /* Requested operation */ 13354 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0 13355 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1 13356 /* enum: Get current RXEQ settings */ 13357 #define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0 13358 /* enum: Override RXEQ settings */ 13359 #define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1 13360 /* enum: Get current TX Driver settings */ 13361 #define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2 13362 /* enum: Override TX Driver settings */ 13363 #define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3 13364 /* enum: Force KR Serdes reset / recalibration */ 13365 #define MC_CMD_KR_TUNE_IN_RECAL 0x4 13366 /* enum: Start KR Serdes Eye diagram plot on a given lane. Lane must have valid 13367 * signal. 13368 */ 13369 #define MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5 13370 /* enum: Poll KR Serdes Eye diagram plot. Returns one row of BER data. The 13371 * caller should call this command repeatedly after starting eye plot, until no 13372 * more data is returned. 13373 */ 13374 #define MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6 13375 /* enum: Read Figure Of Merit (eye quality, higher is better). */ 13376 #define MC_CMD_KR_TUNE_IN_READ_FOM 0x7 13377 /* enum: Start/stop link training frames */ 13378 #define MC_CMD_KR_TUNE_IN_LINK_TRAIN_RUN 0x8 13379 /* enum: Issue KR link training command (control training coefficients) */ 13380 #define MC_CMD_KR_TUNE_IN_LINK_TRAIN_CMD 0x9 13381 /* Align the arguments to 32 bits */ 13382 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1 13383 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3 13384 /* Arguments specific to the operation */ 13385 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4 13386 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4 13387 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0 13388 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM 62 13389 13390 /* MC_CMD_KR_TUNE_OUT msgresponse */ 13391 #define MC_CMD_KR_TUNE_OUT_LEN 0 13392 13393 /* MC_CMD_KR_TUNE_RXEQ_GET_IN msgrequest */ 13394 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4 13395 /* Requested operation */ 13396 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0 13397 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1 13398 /* Align the arguments to 32 bits */ 13399 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 13400 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 13401 13402 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT msgresponse */ 13403 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4 13404 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252 13405 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 13406 /* RXEQ Parameter */ 13407 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 13408 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 13409 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 13410 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 13411 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 13412 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 13413 /* enum: Attenuation (0-15, Huntington) */ 13414 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0 13415 /* enum: CTLE Boost (0-15, Huntington) */ 13416 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1 13417 /* enum: Edge DFE Tap1 (Huntington - 0 - max negative, 64 - zero, 127 - max 13418 * positive, Medford - 0-31) 13419 */ 13420 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2 13421 /* enum: Edge DFE Tap2 (Huntington - 0 - max negative, 32 - zero, 63 - max 13422 * positive, Medford - 0-31) 13423 */ 13424 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3 13425 /* enum: Edge DFE Tap3 (Huntington - 0 - max negative, 32 - zero, 63 - max 13426 * positive, Medford - 0-16) 13427 */ 13428 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4 13429 /* enum: Edge DFE Tap4 (Huntington - 0 - max negative, 32 - zero, 63 - max 13430 * positive, Medford - 0-16) 13431 */ 13432 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5 13433 /* enum: Edge DFE Tap5 (Huntington - 0 - max negative, 32 - zero, 63 - max 13434 * positive, Medford - 0-16) 13435 */ 13436 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6 13437 /* enum: Edge DFE DLEV (0-128 for Medford) */ 13438 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV 0x7 13439 /* enum: Variable Gain Amplifier (0-15, Medford) */ 13440 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_VGA 0x8 13441 /* enum: CTLE EQ Capacitor (0-15, Medford) */ 13442 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9 13443 /* enum: CTLE EQ Resistor (0-7, Medford) */ 13444 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa 13445 /* enum: CTLE gain (0-31, Medford2) */ 13446 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_GAIN 0xb 13447 /* enum: CTLE pole (0-31, Medford2) */ 13448 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_POLE 0xc 13449 /* enum: CTLE peaking (0-31, Medford2) */ 13450 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_PEAK 0xd 13451 /* enum: DFE Tap1 - even path (Medford2 - 6 bit signed (-29 - +29)) */ 13452 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_EVEN 0xe 13453 /* enum: DFE Tap1 - odd path (Medford2 - 6 bit signed (-29 - +29)) */ 13454 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_ODD 0xf 13455 /* enum: DFE Tap2 (Medford2 - 6 bit signed (-20 - +20)) */ 13456 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x10 13457 /* enum: DFE Tap3 (Medford2 - 6 bit signed (-20 - +20)) */ 13458 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x11 13459 /* enum: DFE Tap4 (Medford2 - 6 bit signed (-20 - +20)) */ 13460 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x12 13461 /* enum: DFE Tap5 (Medford2 - 6 bit signed (-24 - +24)) */ 13462 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x13 13463 /* enum: DFE Tap6 (Medford2 - 6 bit signed (-24 - +24)) */ 13464 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP6 0x14 13465 /* enum: DFE Tap7 (Medford2 - 6 bit signed (-24 - +24)) */ 13466 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP7 0x15 13467 /* enum: DFE Tap8 (Medford2 - 6 bit signed (-24 - +24)) */ 13468 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP8 0x16 13469 /* enum: DFE Tap9 (Medford2 - 6 bit signed (-24 - +24)) */ 13470 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP9 0x17 13471 /* enum: DFE Tap10 (Medford2 - 6 bit signed (-24 - +24)) */ 13472 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP10 0x18 13473 /* enum: DFE Tap11 (Medford2 - 6 bit signed (-24 - +24)) */ 13474 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP11 0x19 13475 /* enum: DFE Tap12 (Medford2 - 6 bit signed (-24 - +24)) */ 13476 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP12 0x1a 13477 /* enum: I/Q clk offset (Medford2 - 4 bit signed (-5 - +5))) */ 13478 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_IQ_OFF 0x1b 13479 /* enum: Negative h1 polarity data sampler offset calibration code, even path 13480 * (Medford2 - 6 bit signed (-29 - +29))) 13481 */ 13482 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_EVEN 0x1c 13483 /* enum: Negative h1 polarity data sampler offset calibration code, odd path 13484 * (Medford2 - 6 bit signed (-29 - +29))) 13485 */ 13486 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_ODD 0x1d 13487 /* enum: Positive h1 polarity data sampler offset calibration code, even path 13488 * (Medford2 - 6 bit signed (-29 - +29))) 13489 */ 13490 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_EVEN 0x1e 13491 /* enum: Positive h1 polarity data sampler offset calibration code, odd path 13492 * (Medford2 - 6 bit signed (-29 - +29))) 13493 */ 13494 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_ODD 0x1f 13495 /* enum: CDR calibration loop code (Medford2) */ 13496 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_PVT 0x20 13497 /* enum: CDR integral loop code (Medford2) */ 13498 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_INTEG 0x21 13499 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 13500 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3 13501 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 13502 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 13503 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 13504 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 13505 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ 13506 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11 13507 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 13508 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12 13509 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4 13510 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16 13511 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 13512 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 13513 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 13514 13515 /* MC_CMD_KR_TUNE_RXEQ_SET_IN msgrequest */ 13516 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMIN 8 13517 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252 13518 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) 13519 /* Requested operation */ 13520 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0 13521 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1 13522 /* Align the arguments to 32 bits */ 13523 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 13524 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 13525 /* RXEQ Parameter */ 13526 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4 13527 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4 13528 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 13529 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 13530 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 13531 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 13532 /* Enum values, see field(s): */ 13533 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */ 13534 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 13535 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3 13536 /* Enum values, see field(s): */ 13537 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 13538 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11 13539 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 13540 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12 13541 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4 13542 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 13543 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 13544 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 13545 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 13546 13547 /* MC_CMD_KR_TUNE_RXEQ_SET_OUT msgresponse */ 13548 #define MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0 13549 13550 /* MC_CMD_KR_TUNE_TXEQ_GET_IN msgrequest */ 13551 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_LEN 4 13552 /* Requested operation */ 13553 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_OFST 0 13554 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_LEN 1 13555 /* Align the arguments to 32 bits */ 13556 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 13557 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 13558 13559 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT msgresponse */ 13560 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4 13561 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX 252 13562 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 13563 /* TXEQ Parameter */ 13564 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 13565 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 13566 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 13567 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 13568 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 13569 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 13570 /* enum: TX Amplitude (Huntington, Medford, Medford2) */ 13571 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0 13572 /* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */ 13573 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1 13574 /* enum: De-Emphasis Tap1 Fine */ 13575 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2 13576 /* enum: De-Emphasis Tap2 Magnitude (0-6) (Huntington) */ 13577 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3 13578 /* enum: De-Emphasis Tap2 Fine (Huntington) */ 13579 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4 13580 /* enum: Pre-Emphasis Magnitude (Huntington) */ 13581 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5 13582 /* enum: Pre-Emphasis Fine (Huntington) */ 13583 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6 13584 /* enum: TX Slew Rate Coarse control (Huntington) */ 13585 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7 13586 /* enum: TX Slew Rate Fine control (Huntington) */ 13587 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8 13588 /* enum: TX Termination Impedance control (Huntington) */ 13589 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9 13590 /* enum: TX Amplitude Fine control (Medford) */ 13591 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_FINE 0xa 13592 /* enum: Pre-shoot Tap (Medford, Medford2) */ 13593 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV 0xb 13594 /* enum: De-emphasis Tap (Medford, Medford2) */ 13595 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY 0xc 13596 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 13597 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3 13598 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */ 13599 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */ 13600 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */ 13601 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */ 13602 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ 13603 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_LBN 11 13604 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 5 13605 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_LBN 16 13606 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 13607 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_LBN 24 13608 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_WIDTH 8 13609 13610 /* MC_CMD_KR_TUNE_TXEQ_SET_IN msgrequest */ 13611 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMIN 8 13612 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX 252 13613 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num)) 13614 /* Requested operation */ 13615 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0 13616 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_LEN 1 13617 /* Align the arguments to 32 bits */ 13618 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 13619 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 13620 /* TXEQ Parameter */ 13621 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_OFST 4 13622 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4 13623 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MINNUM 1 13624 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM 62 13625 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0 13626 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_WIDTH 8 13627 /* Enum values, see field(s): */ 13628 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_ID */ 13629 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_LBN 8 13630 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_WIDTH 3 13631 /* Enum values, see field(s): */ 13632 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_LANE */ 13633 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_LBN 11 13634 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_WIDTH 5 13635 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_LBN 16 13636 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 13637 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_LBN 24 13638 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_WIDTH 8 13639 13640 /* MC_CMD_KR_TUNE_TXEQ_SET_OUT msgresponse */ 13641 #define MC_CMD_KR_TUNE_TXEQ_SET_OUT_LEN 0 13642 13643 /* MC_CMD_KR_TUNE_RECAL_IN msgrequest */ 13644 #define MC_CMD_KR_TUNE_RECAL_IN_LEN 4 13645 /* Requested operation */ 13646 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0 13647 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1 13648 /* Align the arguments to 32 bits */ 13649 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1 13650 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_LEN 3 13651 13652 /* MC_CMD_KR_TUNE_RECAL_OUT msgresponse */ 13653 #define MC_CMD_KR_TUNE_RECAL_OUT_LEN 0 13654 13655 /* MC_CMD_KR_TUNE_START_EYE_PLOT_IN msgrequest */ 13656 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LEN 8 13657 /* Requested operation */ 13658 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 13659 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 13660 /* Align the arguments to 32 bits */ 13661 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 13662 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 13663 /* Port-relative lane to scan eye on */ 13664 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 13665 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_LEN 4 13666 13667 /* MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN msgrequest */ 13668 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LEN 12 13669 /* Requested operation */ 13670 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_OP_OFST 0 13671 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_OP_LEN 1 13672 /* Align the arguments to 32 bits */ 13673 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_OFST 1 13674 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_LEN 3 13675 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_OFST 4 13676 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_LEN 4 13677 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_LBN 0 13678 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_WIDTH 8 13679 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_LBN 31 13680 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_WIDTH 1 13681 /* Scan duration / cycle count */ 13682 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_OFST 8 13683 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_LEN 4 13684 13685 /* MC_CMD_KR_TUNE_START_EYE_PLOT_OUT msgresponse */ 13686 #define MC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0 13687 13688 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN msgrequest */ 13689 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_LEN 4 13690 /* Requested operation */ 13691 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 13692 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 13693 /* Align the arguments to 32 bits */ 13694 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 13695 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 13696 13697 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT msgresponse */ 13698 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 13699 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 13700 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 13701 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 13702 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 13703 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 13704 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 13705 13706 /* MC_CMD_KR_TUNE_READ_FOM_IN msgrequest */ 13707 #define MC_CMD_KR_TUNE_READ_FOM_IN_LEN 8 13708 /* Requested operation */ 13709 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_OFST 0 13710 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_LEN 1 13711 /* Align the arguments to 32 bits */ 13712 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_OFST 1 13713 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_LEN 3 13714 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4 13715 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_LEN 4 13716 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_LBN 0 13717 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_WIDTH 8 13718 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_LBN 31 13719 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_WIDTH 1 13720 13721 /* MC_CMD_KR_TUNE_READ_FOM_OUT msgresponse */ 13722 #define MC_CMD_KR_TUNE_READ_FOM_OUT_LEN 4 13723 #define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_OFST 0 13724 #define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_LEN 4 13725 13726 /* MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN msgrequest */ 13727 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_LEN 8 13728 /* Requested operation */ 13729 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_OP_OFST 0 13730 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_OP_LEN 1 13731 /* Align the arguments to 32 bits */ 13732 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_RSVD_OFST 1 13733 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_RSVD_LEN 3 13734 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_RUN_OFST 4 13735 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_RUN_LEN 4 13736 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_STOP 0x0 /* enum */ 13737 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_START 0x1 /* enum */ 13738 13739 /* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN msgrequest */ 13740 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LEN 28 13741 /* Requested operation */ 13742 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_OP_OFST 0 13743 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_OP_LEN 1 13744 /* Align the arguments to 32 bits */ 13745 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_RSVD_OFST 1 13746 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_RSVD_LEN 3 13747 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LANE_OFST 4 13748 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LANE_LEN 4 13749 /* Set INITIALIZE state */ 13750 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_INITIALIZE_OFST 8 13751 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_INITIALIZE_LEN 4 13752 /* Set PRESET state */ 13753 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_PRESET_OFST 12 13754 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_PRESET_LEN 4 13755 /* C(-1) request */ 13756 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CM1_OFST 16 13757 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CM1_LEN 4 13758 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_HOLD 0x0 /* enum */ 13759 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_INCREMENT 0x1 /* enum */ 13760 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_DECREMENT 0x2 /* enum */ 13761 /* C(0) request */ 13762 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_C0_OFST 20 13763 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_C0_LEN 4 13764 /* Enum values, see field(s): */ 13765 /* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */ 13766 /* C(+1) request */ 13767 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CP1_OFST 24 13768 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CP1_LEN 4 13769 /* Enum values, see field(s): */ 13770 /* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */ 13771 13772 /* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT msgresponse */ 13773 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_LEN 24 13774 /* C(-1) status */ 13775 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_STATUS_OFST 0 13776 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_STATUS_LEN 4 13777 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_NOT_UPDATED 0x0 /* enum */ 13778 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_UPDATED 0x1 /* enum */ 13779 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MINIMUM 0x2 /* enum */ 13780 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MAXIMUM 0x3 /* enum */ 13781 /* C(0) status */ 13782 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_STATUS_OFST 4 13783 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_STATUS_LEN 4 13784 /* Enum values, see field(s): */ 13785 /* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */ 13786 /* C(+1) status */ 13787 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_STATUS_OFST 8 13788 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_STATUS_LEN 4 13789 /* Enum values, see field(s): */ 13790 /* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */ 13791 /* C(-1) value */ 13792 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_VALUE_OFST 12 13793 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_VALUE_LEN 4 13794 /* C(0) value */ 13795 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_VALUE_OFST 16 13796 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_VALUE_LEN 4 13797 /* C(+1) status */ 13798 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_VALUE_OFST 20 13799 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_VALUE_LEN 4 13800 13801 13802 /***********************************/ 13803 /* MC_CMD_PCIE_TUNE 13804 * Get or set PCIE Serdes RXEQ and TX Driver settings 13805 */ 13806 #define MC_CMD_PCIE_TUNE 0xf2 13807 #undef MC_CMD_0xf2_PRIVILEGE_CTG 13808 13809 #define MC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 13810 13811 /* MC_CMD_PCIE_TUNE_IN msgrequest */ 13812 #define MC_CMD_PCIE_TUNE_IN_LENMIN 4 13813 #define MC_CMD_PCIE_TUNE_IN_LENMAX 252 13814 #define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num)) 13815 /* Requested operation */ 13816 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0 13817 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1 13818 /* enum: Get current RXEQ settings */ 13819 #define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0 13820 /* enum: Override RXEQ settings */ 13821 #define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1 13822 /* enum: Get current TX Driver settings */ 13823 #define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2 13824 /* enum: Override TX Driver settings */ 13825 #define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3 13826 /* enum: Start PCIe Serdes Eye diagram plot on a given lane. */ 13827 #define MC_CMD_PCIE_TUNE_IN_START_EYE_PLOT 0x5 13828 /* enum: Poll PCIe Serdes Eye diagram plot. Returns one row of BER data. The 13829 * caller should call this command repeatedly after starting eye plot, until no 13830 * more data is returned. 13831 */ 13832 #define MC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT 0x6 13833 /* enum: Enable the SERDES BIST and set it to generate a 200MHz square wave */ 13834 #define MC_CMD_PCIE_TUNE_IN_BIST_SQUARE_WAVE 0x7 13835 /* Align the arguments to 32 bits */ 13836 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1 13837 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_LEN 3 13838 /* Arguments specific to the operation */ 13839 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4 13840 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4 13841 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0 13842 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM 62 13843 13844 /* MC_CMD_PCIE_TUNE_OUT msgresponse */ 13845 #define MC_CMD_PCIE_TUNE_OUT_LEN 0 13846 13847 /* MC_CMD_PCIE_TUNE_RXEQ_GET_IN msgrequest */ 13848 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4 13849 /* Requested operation */ 13850 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 13851 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 13852 /* Align the arguments to 32 bits */ 13853 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 13854 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 13855 13856 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT msgresponse */ 13857 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4 13858 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252 13859 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 13860 /* RXEQ Parameter */ 13861 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 13862 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 13863 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 13864 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 13865 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 13866 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 13867 /* enum: Attenuation (0-15) */ 13868 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0 13869 /* enum: CTLE Boost (0-15) */ 13870 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1 13871 /* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */ 13872 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2 13873 /* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */ 13874 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3 13875 /* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */ 13876 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4 13877 /* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */ 13878 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5 13879 /* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */ 13880 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6 13881 /* enum: DFE DLev */ 13882 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_DLEV 0x7 13883 /* enum: Figure of Merit */ 13884 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_FOM 0x8 13885 /* enum: CTLE EQ Capacitor (HF Gain) */ 13886 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9 13887 /* enum: CTLE EQ Resistor (DC Gain) */ 13888 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa 13889 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 13890 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 5 13891 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 13892 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 13893 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 13894 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 13895 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */ 13896 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */ 13897 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */ 13898 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */ 13899 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_8 0x8 /* enum */ 13900 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_9 0x9 /* enum */ 13901 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_10 0xa /* enum */ 13902 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_11 0xb /* enum */ 13903 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_12 0xc /* enum */ 13904 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_13 0xd /* enum */ 13905 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_14 0xe /* enum */ 13906 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_15 0xf /* enum */ 13907 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x10 /* enum */ 13908 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 13 13909 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 13910 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 14 13911 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 10 13912 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 13913 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 13914 13915 /* MC_CMD_PCIE_TUNE_RXEQ_SET_IN msgrequest */ 13916 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMIN 8 13917 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMAX 252 13918 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) 13919 /* Requested operation */ 13920 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_OFST 0 13921 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_LEN 1 13922 /* Align the arguments to 32 bits */ 13923 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_OFST 1 13924 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_LEN 3 13925 /* RXEQ Parameter */ 13926 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_OFST 4 13927 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LEN 4 13928 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 13929 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 13930 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 13931 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 13932 /* Enum values, see field(s): */ 13933 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_ID */ 13934 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 13935 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 5 13936 /* Enum values, see field(s): */ 13937 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 13938 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 13 13939 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 13940 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_LBN 14 13941 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 2 13942 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 13943 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 13944 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 13945 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 13946 13947 /* MC_CMD_PCIE_TUNE_RXEQ_SET_OUT msgresponse */ 13948 #define MC_CMD_PCIE_TUNE_RXEQ_SET_OUT_LEN 0 13949 13950 /* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */ 13951 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4 13952 /* Requested operation */ 13953 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 13954 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 13955 /* Align the arguments to 32 bits */ 13956 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 13957 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 13958 13959 /* MC_CMD_PCIE_TUNE_TXEQ_GET_OUT msgresponse */ 13960 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4 13961 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252 13962 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 13963 /* RXEQ Parameter */ 13964 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 13965 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 13966 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 13967 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 13968 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 13969 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 13970 /* enum: TxMargin (PIPE) */ 13971 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0 13972 /* enum: TxSwing (PIPE) */ 13973 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1 13974 /* enum: De-emphasis coefficient C(-1) (PIPE) */ 13975 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2 13976 /* enum: De-emphasis coefficient C(0) (PIPE) */ 13977 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3 13978 /* enum: De-emphasis coefficient C(+1) (PIPE) */ 13979 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4 13980 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 13981 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4 13982 /* Enum values, see field(s): */ 13983 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 13984 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12 13985 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12 13986 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24 13987 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 13988 13989 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN msgrequest */ 13990 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LEN 8 13991 /* Requested operation */ 13992 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 13993 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 13994 /* Align the arguments to 32 bits */ 13995 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 13996 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 13997 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 13998 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_LEN 4 13999 14000 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT msgresponse */ 14001 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT_LEN 0 14002 14003 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN msgrequest */ 14004 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_LEN 4 14005 /* Requested operation */ 14006 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 14007 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 14008 /* Align the arguments to 32 bits */ 14009 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 14010 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 14011 14012 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT msgresponse */ 14013 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 14014 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 14015 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 14016 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 14017 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 14018 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 14019 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 14020 14021 /* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN msgrequest */ 14022 #define MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN_LEN 0 14023 14024 /* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT msgrequest */ 14025 #define MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT_LEN 0 14026 14027 14028 /***********************************/ 14029 /* MC_CMD_LICENSING 14030 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition 14031 * - not used for V3 licensing 14032 */ 14033 #define MC_CMD_LICENSING 0xf3 14034 #undef MC_CMD_0xf3_PRIVILEGE_CTG 14035 14036 #define MC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14037 14038 /* MC_CMD_LICENSING_IN msgrequest */ 14039 #define MC_CMD_LICENSING_IN_LEN 4 14040 /* identifies the type of operation requested */ 14041 #define MC_CMD_LICENSING_IN_OP_OFST 0 14042 #define MC_CMD_LICENSING_IN_OP_LEN 4 14043 /* enum: re-read and apply licenses after a license key partition update; note 14044 * that this operation returns a zero-length response 14045 */ 14046 #define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0 14047 /* enum: report counts of installed licenses */ 14048 #define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1 14049 14050 /* MC_CMD_LICENSING_OUT msgresponse */ 14051 #define MC_CMD_LICENSING_OUT_LEN 28 14052 /* count of application keys which are valid */ 14053 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0 14054 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_LEN 4 14055 /* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with 14056 * MC_CMD_FC_OP_LICENSE) 14057 */ 14058 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4 14059 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_LEN 4 14060 /* count of application keys which are invalid due to being blacklisted */ 14061 #define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8 14062 #define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_LEN 4 14063 /* count of application keys which are invalid due to being unverifiable */ 14064 #define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12 14065 #define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_LEN 4 14066 /* count of application keys which are invalid due to being for the wrong node 14067 */ 14068 #define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16 14069 #define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_LEN 4 14070 /* licensing state (for diagnostics; the exact meaning of the bits in this 14071 * field are private to the firmware) 14072 */ 14073 #define MC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20 14074 #define MC_CMD_LICENSING_OUT_LICENSING_STATE_LEN 4 14075 /* licensing subsystem self-test report (for manftest) */ 14076 #define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24 14077 #define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_LEN 4 14078 /* enum: licensing subsystem self-test failed */ 14079 #define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0 14080 /* enum: licensing subsystem self-test passed */ 14081 #define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1 14082 14083 14084 /***********************************/ 14085 /* MC_CMD_LICENSING_V3 14086 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition 14087 * - V3 licensing (Medford) 14088 */ 14089 #define MC_CMD_LICENSING_V3 0xd0 14090 #undef MC_CMD_0xd0_PRIVILEGE_CTG 14091 14092 #define MC_CMD_0xd0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14093 14094 /* MC_CMD_LICENSING_V3_IN msgrequest */ 14095 #define MC_CMD_LICENSING_V3_IN_LEN 4 14096 /* identifies the type of operation requested */ 14097 #define MC_CMD_LICENSING_V3_IN_OP_OFST 0 14098 #define MC_CMD_LICENSING_V3_IN_OP_LEN 4 14099 /* enum: re-read and apply licenses after a license key partition update; note 14100 * that this operation returns a zero-length response 14101 */ 14102 #define MC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE 0x0 14103 /* enum: report counts of installed licenses Returns EAGAIN if license 14104 * processing (updating) has been started but not yet completed. 14105 */ 14106 #define MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE 0x1 14107 14108 /* MC_CMD_LICENSING_V3_OUT msgresponse */ 14109 #define MC_CMD_LICENSING_V3_OUT_LEN 88 14110 /* count of keys which are valid */ 14111 #define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_OFST 0 14112 #define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_LEN 4 14113 /* sum of UNVERIFIABLE_KEYS + WRONG_NODE_KEYS (for compatibility with 14114 * MC_CMD_FC_OP_LICENSE) 14115 */ 14116 #define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_OFST 4 14117 #define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_LEN 4 14118 /* count of keys which are invalid due to being unverifiable */ 14119 #define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_OFST 8 14120 #define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_LEN 4 14121 /* count of keys which are invalid due to being for the wrong node */ 14122 #define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_OFST 12 14123 #define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_LEN 4 14124 /* licensing state (for diagnostics; the exact meaning of the bits in this 14125 * field are private to the firmware) 14126 */ 14127 #define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_OFST 16 14128 #define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_LEN 4 14129 /* licensing subsystem self-test report (for manftest) */ 14130 #define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_OFST 20 14131 #define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_LEN 4 14132 /* enum: licensing subsystem self-test failed */ 14133 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL 0x0 14134 /* enum: licensing subsystem self-test passed */ 14135 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS 0x1 14136 /* bitmask of licensed applications */ 14137 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_OFST 24 14138 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LEN 8 14139 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_OFST 24 14140 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_OFST 28 14141 /* reserved for future use */ 14142 #define MC_CMD_LICENSING_V3_OUT_RESERVED_0_OFST 32 14143 #define MC_CMD_LICENSING_V3_OUT_RESERVED_0_LEN 24 14144 /* bitmask of licensed features */ 14145 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_OFST 56 14146 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LEN 8 14147 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_OFST 56 14148 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_OFST 60 14149 /* reserved for future use */ 14150 #define MC_CMD_LICENSING_V3_OUT_RESERVED_1_OFST 64 14151 #define MC_CMD_LICENSING_V3_OUT_RESERVED_1_LEN 24 14152 14153 14154 /***********************************/ 14155 /* MC_CMD_LICENSING_GET_ID_V3 14156 * Get ID and type from the NVRAM_PARTITION_TYPE_LICENSE application license 14157 * partition - V3 licensing (Medford) 14158 */ 14159 #define MC_CMD_LICENSING_GET_ID_V3 0xd1 14160 #undef MC_CMD_0xd1_PRIVILEGE_CTG 14161 14162 #define MC_CMD_0xd1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14163 14164 /* MC_CMD_LICENSING_GET_ID_V3_IN msgrequest */ 14165 #define MC_CMD_LICENSING_GET_ID_V3_IN_LEN 0 14166 14167 /* MC_CMD_LICENSING_GET_ID_V3_OUT msgresponse */ 14168 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMIN 8 14169 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX 252 14170 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LEN(num) (8+1*(num)) 14171 /* type of license (eg 3) */ 14172 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 0 14173 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_LEN 4 14174 /* length of the license ID (in bytes) */ 14175 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_OFST 4 14176 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_LEN 4 14177 /* the unique license ID of the adapter */ 14178 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_OFST 8 14179 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LEN 1 14180 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MINNUM 0 14181 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM 244 14182 14183 14184 /***********************************/ 14185 /* MC_CMD_MC2MC_PROXY 14186 * Execute an arbitrary MCDI command on the slave MC of a dual-core device. 14187 * This will fail on a single-core system. 14188 */ 14189 #define MC_CMD_MC2MC_PROXY 0xf4 14190 #undef MC_CMD_0xf4_PRIVILEGE_CTG 14191 14192 #define MC_CMD_0xf4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14193 14194 /* MC_CMD_MC2MC_PROXY_IN msgrequest */ 14195 #define MC_CMD_MC2MC_PROXY_IN_LEN 0 14196 14197 /* MC_CMD_MC2MC_PROXY_OUT msgresponse */ 14198 #define MC_CMD_MC2MC_PROXY_OUT_LEN 0 14199 14200 14201 /***********************************/ 14202 /* MC_CMD_GET_LICENSED_APP_STATE 14203 * Query the state of an individual licensed application. (Note that the actual 14204 * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation 14205 * or a reboot of the MC.) Not used for V3 licensing 14206 */ 14207 #define MC_CMD_GET_LICENSED_APP_STATE 0xf5 14208 #undef MC_CMD_0xf5_PRIVILEGE_CTG 14209 14210 #define MC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14211 14212 /* MC_CMD_GET_LICENSED_APP_STATE_IN msgrequest */ 14213 #define MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4 14214 /* application ID to query (LICENSED_APP_ID_xxx) */ 14215 #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0 14216 #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_LEN 4 14217 14218 /* MC_CMD_GET_LICENSED_APP_STATE_OUT msgresponse */ 14219 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4 14220 /* state of this application */ 14221 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0 14222 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_LEN 4 14223 /* enum: no (or invalid) license is present for the application */ 14224 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0 14225 /* enum: a valid license is present for the application */ 14226 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1 14227 14228 14229 /***********************************/ 14230 /* MC_CMD_GET_LICENSED_V3_APP_STATE 14231 * Query the state of an individual licensed application. (Note that the actual 14232 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE 14233 * operation or a reboot of the MC.) Used for V3 licensing (Medford) 14234 */ 14235 #define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd2 14236 #undef MC_CMD_0xd2_PRIVILEGE_CTG 14237 14238 #define MC_CMD_0xd2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14239 14240 /* MC_CMD_GET_LICENSED_V3_APP_STATE_IN msgrequest */ 14241 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_LEN 8 14242 /* application ID to query (LICENSED_V3_APPS_xxx) expressed as a single bit 14243 * mask 14244 */ 14245 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0 14246 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LEN 8 14247 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0 14248 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4 14249 14250 /* MC_CMD_GET_LICENSED_V3_APP_STATE_OUT msgresponse */ 14251 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4 14252 /* state of this application */ 14253 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_OFST 0 14254 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_LEN 4 14255 /* enum: no (or invalid) license is present for the application */ 14256 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED 0x0 14257 /* enum: a valid license is present for the application */ 14258 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED 0x1 14259 14260 14261 /***********************************/ 14262 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES 14263 * Query the state of an one or more licensed features. (Note that the actual 14264 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE 14265 * operation or a reboot of the MC.) Used for V3 licensing (Medford) 14266 */ 14267 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3 14268 #undef MC_CMD_0xd3_PRIVILEGE_CTG 14269 14270 #define MC_CMD_0xd3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14271 14272 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN msgrequest */ 14273 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_LEN 8 14274 /* features to query (LICENSED_V3_FEATURES_xxx) expressed as a mask with one or 14275 * more bits set 14276 */ 14277 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0 14278 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LEN 8 14279 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0 14280 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4 14281 14282 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT msgresponse */ 14283 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_LEN 8 14284 /* states of these features - bit set for licensed, clear for not licensed */ 14285 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0 14286 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LEN 8 14287 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0 14288 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4 14289 14290 14291 /***********************************/ 14292 /* MC_CMD_LICENSED_APP_OP 14293 * Perform an action for an individual licensed application - not used for V3 14294 * licensing. 14295 */ 14296 #define MC_CMD_LICENSED_APP_OP 0xf6 14297 #undef MC_CMD_0xf6_PRIVILEGE_CTG 14298 14299 #define MC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14300 14301 /* MC_CMD_LICENSED_APP_OP_IN msgrequest */ 14302 #define MC_CMD_LICENSED_APP_OP_IN_LENMIN 8 14303 #define MC_CMD_LICENSED_APP_OP_IN_LENMAX 252 14304 #define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num)) 14305 /* application ID */ 14306 #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0 14307 #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_LEN 4 14308 /* the type of operation requested */ 14309 #define MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4 14310 #define MC_CMD_LICENSED_APP_OP_IN_OP_LEN 4 14311 /* enum: validate application */ 14312 #define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0 14313 /* enum: mask application */ 14314 #define MC_CMD_LICENSED_APP_OP_IN_OP_MASK 0x1 14315 /* arguments specific to this particular operation */ 14316 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_OFST 8 14317 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4 14318 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0 14319 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM 61 14320 14321 /* MC_CMD_LICENSED_APP_OP_OUT msgresponse */ 14322 #define MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0 14323 #define MC_CMD_LICENSED_APP_OP_OUT_LENMAX 252 14324 #define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num)) 14325 /* result specific to this particular operation */ 14326 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0 14327 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4 14328 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0 14329 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM 63 14330 14331 /* MC_CMD_LICENSED_APP_OP_VALIDATE_IN msgrequest */ 14332 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_LEN 72 14333 /* application ID */ 14334 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0 14335 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_LEN 4 14336 /* the type of operation requested */ 14337 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4 14338 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_LEN 4 14339 /* validation challenge */ 14340 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_OFST 8 14341 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_LEN 64 14342 14343 /* MC_CMD_LICENSED_APP_OP_VALIDATE_OUT msgresponse */ 14344 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_LEN 68 14345 /* feature expiry (time_t) */ 14346 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0 14347 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_LEN 4 14348 /* validation response */ 14349 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4 14350 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_LEN 64 14351 14352 /* MC_CMD_LICENSED_APP_OP_MASK_IN msgrequest */ 14353 #define MC_CMD_LICENSED_APP_OP_MASK_IN_LEN 12 14354 /* application ID */ 14355 #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_OFST 0 14356 #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_LEN 4 14357 /* the type of operation requested */ 14358 #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_OFST 4 14359 #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_LEN 4 14360 /* flag */ 14361 #define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_OFST 8 14362 #define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_LEN 4 14363 14364 /* MC_CMD_LICENSED_APP_OP_MASK_OUT msgresponse */ 14365 #define MC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 0 14366 14367 14368 /***********************************/ 14369 /* MC_CMD_LICENSED_V3_VALIDATE_APP 14370 * Perform validation for an individual licensed application - V3 licensing 14371 * (Medford) 14372 */ 14373 #define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd4 14374 #undef MC_CMD_0xd4_PRIVILEGE_CTG 14375 14376 #define MC_CMD_0xd4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14377 14378 /* MC_CMD_LICENSED_V3_VALIDATE_APP_IN msgrequest */ 14379 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_LEN 56 14380 /* challenge for validation (384 bits) */ 14381 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_OFST 0 14382 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_LEN 48 14383 /* application ID expressed as a single bit mask */ 14384 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_OFST 48 14385 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LEN 8 14386 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_OFST 48 14387 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_OFST 52 14388 14389 /* MC_CMD_LICENSED_V3_VALIDATE_APP_OUT msgresponse */ 14390 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_LEN 116 14391 /* validation response to challenge in the form of ECDSA signature consisting 14392 * of two 384-bit integers, r and s, in big-endian order. The signature signs a 14393 * SHA-384 digest of a message constructed from the concatenation of the input 14394 * message and the remaining fields of this output message, e.g. challenge[48 14395 * bytes] ... expiry_time[4 bytes] ... 14396 */ 14397 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_OFST 0 14398 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_LEN 96 14399 /* application expiry time */ 14400 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_OFST 96 14401 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_LEN 4 14402 /* application expiry units */ 14403 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_OFST 100 14404 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_LEN 4 14405 /* enum: expiry units are accounting units */ 14406 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC 0x0 14407 /* enum: expiry units are calendar days */ 14408 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_DAYS 0x1 14409 /* base MAC address of the NIC stored in NVRAM (note that this is a constant 14410 * value for a given NIC regardless which function is calling, effectively this 14411 * is PF0 base MAC address) 14412 */ 14413 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_OFST 104 14414 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_LEN 6 14415 /* MAC address of v-adaptor associated with the client. If no such v-adapator 14416 * exists, then the field is filled with 0xFF. 14417 */ 14418 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_OFST 110 14419 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_LEN 6 14420 14421 14422 /***********************************/ 14423 /* MC_CMD_LICENSED_V3_MASK_FEATURES 14424 * Mask features - V3 licensing (Medford) 14425 */ 14426 #define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd5 14427 #undef MC_CMD_0xd5_PRIVILEGE_CTG 14428 14429 #define MC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14430 14431 /* MC_CMD_LICENSED_V3_MASK_FEATURES_IN msgrequest */ 14432 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_LEN 12 14433 /* mask to be applied to features to be changed */ 14434 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0 14435 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LEN 8 14436 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0 14437 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4 14438 /* whether to turn on or turn off the masked features */ 14439 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_OFST 8 14440 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_LEN 4 14441 /* enum: turn the features off */ 14442 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF 0x0 14443 /* enum: turn the features back on */ 14444 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_ON 0x1 14445 14446 /* MC_CMD_LICENSED_V3_MASK_FEATURES_OUT msgresponse */ 14447 #define MC_CMD_LICENSED_V3_MASK_FEATURES_OUT_LEN 0 14448 14449 14450 /***********************************/ 14451 /* MC_CMD_LICENSING_V3_TEMPORARY 14452 * Perform operations to support installation of a single temporary license in 14453 * the adapter, in addition to those found in the licensing partition. See 14454 * SF-116124-SW for an overview of how this could be used. The license is 14455 * stored in MC persistent data and so will survive a MC reboot, but will be 14456 * erased when the adapter is power cycled 14457 */ 14458 #define MC_CMD_LICENSING_V3_TEMPORARY 0xd6 14459 #undef MC_CMD_0xd6_PRIVILEGE_CTG 14460 14461 #define MC_CMD_0xd6_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 14462 14463 /* MC_CMD_LICENSING_V3_TEMPORARY_IN msgrequest */ 14464 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_LEN 4 14465 /* operation code */ 14466 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_OFST 0 14467 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_LEN 4 14468 /* enum: install a new license, overwriting any existing temporary license. 14469 * This is an asynchronous operation owing to the time taken to validate an 14470 * ECDSA license 14471 */ 14472 #define MC_CMD_LICENSING_V3_TEMPORARY_SET 0x0 14473 /* enum: clear the license immediately rather than waiting for the next power 14474 * cycle 14475 */ 14476 #define MC_CMD_LICENSING_V3_TEMPORARY_CLEAR 0x1 14477 /* enum: get the status of the asynchronous MC_CMD_LICENSING_V3_TEMPORARY_SET 14478 * operation 14479 */ 14480 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS 0x2 14481 14482 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_SET msgrequest */ 14483 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LEN 164 14484 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_OFST 0 14485 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_LEN 4 14486 /* ECDSA license and signature */ 14487 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_OFST 4 14488 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_LEN 160 14489 14490 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR msgrequest */ 14491 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_LEN 4 14492 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_OFST 0 14493 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_LEN 4 14494 14495 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS msgrequest */ 14496 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_LEN 4 14497 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_OFST 0 14498 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_LEN 4 14499 14500 /* MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS msgresponse */ 14501 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LEN 12 14502 /* status code */ 14503 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_OFST 0 14504 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_LEN 4 14505 /* enum: finished validating and installing license */ 14506 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_OK 0x0 14507 /* enum: license validation and installation in progress */ 14508 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_IN_PROGRESS 0x1 14509 /* enum: licensing error. More specific error messages are not provided to 14510 * avoid exposing details of the licensing system to the client 14511 */ 14512 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_ERROR 0x2 14513 /* bitmask of licensed features */ 14514 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_OFST 4 14515 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LEN 8 14516 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_OFST 4 14517 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_OFST 8 14518 14519 14520 /***********************************/ 14521 /* MC_CMD_SET_PORT_SNIFF_CONFIG 14522 * Configure RX port sniffing for the physical port associated with the calling 14523 * function. Only a privileged function may change the port sniffing 14524 * configuration. A copy of all traffic delivered to the host (non-promiscuous 14525 * mode) or all traffic arriving at the port (promiscuous mode) may be 14526 * delivered to a specific queue, or a set of queues with RSS. 14527 */ 14528 #define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7 14529 #undef MC_CMD_0xf7_PRIVILEGE_CTG 14530 14531 #define MC_CMD_0xf7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14532 14533 /* MC_CMD_SET_PORT_SNIFF_CONFIG_IN msgrequest */ 14534 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_LEN 16 14535 /* configuration flags */ 14536 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 14537 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4 14538 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 14539 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 14540 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1 14541 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1 14542 /* receive queue handle (for RSS mode, this is the base queue) */ 14543 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 14544 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_LEN 4 14545 /* receive mode */ 14546 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 14547 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4 14548 /* enum: receive to just the specified queue */ 14549 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 14550 /* enum: receive to multiple queues using RSS context */ 14551 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 14552 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note 14553 * that these handles should be considered opaque to the host, although a value 14554 * of 0xFFFFFFFF is guaranteed never to be a valid handle. 14555 */ 14556 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 14557 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_LEN 4 14558 14559 /* MC_CMD_SET_PORT_SNIFF_CONFIG_OUT msgresponse */ 14560 #define MC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0 14561 14562 14563 /***********************************/ 14564 /* MC_CMD_GET_PORT_SNIFF_CONFIG 14565 * Obtain the current RX port sniffing configuration for the physical port 14566 * associated with the calling function. Only a privileged function may read 14567 * the configuration. 14568 */ 14569 #define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8 14570 #undef MC_CMD_0xf8_PRIVILEGE_CTG 14571 14572 #define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14573 14574 /* MC_CMD_GET_PORT_SNIFF_CONFIG_IN msgrequest */ 14575 #define MC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0 14576 14577 /* MC_CMD_GET_PORT_SNIFF_CONFIG_OUT msgresponse */ 14578 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_LEN 16 14579 /* configuration flags */ 14580 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 14581 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4 14582 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 14583 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 14584 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1 14585 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1 14586 /* receiving queue handle (for RSS mode, this is the base queue) */ 14587 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 14588 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_LEN 4 14589 /* receive mode */ 14590 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 14591 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4 14592 /* enum: receiving to just the specified queue */ 14593 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 14594 /* enum: receiving to multiple queues using RSS context */ 14595 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 14596 /* RSS context (for RX_MODE_RSS) */ 14597 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 14598 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4 14599 14600 14601 /***********************************/ 14602 /* MC_CMD_SET_PARSER_DISP_CONFIG 14603 * Change configuration related to the parser-dispatcher subsystem. 14604 */ 14605 #define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9 14606 #undef MC_CMD_0xf9_PRIVILEGE_CTG 14607 14608 #define MC_CMD_0xf9_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14609 14610 /* MC_CMD_SET_PARSER_DISP_CONFIG_IN msgrequest */ 14611 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMIN 12 14612 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX 252 14613 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num)) 14614 /* the type of configuration setting to change */ 14615 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 14616 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4 14617 /* enum: Per-TXQ enable for multicast UDP destination lookup for possible 14618 * internal loopback. (ENTITY is a queue handle, VALUE is a single boolean.) 14619 */ 14620 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x0 14621 /* enum: Per-v-adaptor enable for suppression of self-transmissions on the 14622 * internal loopback path. (ENTITY is an EVB_PORT_ID, VALUE is a single 14623 * boolean.) 14624 */ 14625 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x1 14626 /* handle for the entity to update: queue handle, EVB port ID, etc. depending 14627 * on the type of configuration setting being changed 14628 */ 14629 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 14630 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4 14631 /* new value: the details depend on the type of configuration setting being 14632 * changed 14633 */ 14634 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_OFST 8 14635 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 4 14636 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MINNUM 1 14637 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM 61 14638 14639 /* MC_CMD_SET_PARSER_DISP_CONFIG_OUT msgresponse */ 14640 #define MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0 14641 14642 14643 /***********************************/ 14644 /* MC_CMD_GET_PARSER_DISP_CONFIG 14645 * Read configuration related to the parser-dispatcher subsystem. 14646 */ 14647 #define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa 14648 #undef MC_CMD_0xfa_PRIVILEGE_CTG 14649 14650 #define MC_CMD_0xfa_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14651 14652 /* MC_CMD_GET_PARSER_DISP_CONFIG_IN msgrequest */ 14653 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_LEN 8 14654 /* the type of configuration setting to read */ 14655 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 14656 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4 14657 /* Enum values, see field(s): */ 14658 /* MC_CMD_SET_PARSER_DISP_CONFIG/MC_CMD_SET_PARSER_DISP_CONFIG_IN/TYPE */ 14659 /* handle for the entity to query: queue handle, EVB port ID, etc. depending on 14660 * the type of configuration setting being read 14661 */ 14662 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 14663 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4 14664 14665 /* MC_CMD_GET_PARSER_DISP_CONFIG_OUT msgresponse */ 14666 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 4 14667 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX 252 14668 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num)) 14669 /* current value: the details depend on the type of configuration setting being 14670 * read 14671 */ 14672 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_OFST 0 14673 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_LEN 4 14674 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MINNUM 1 14675 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM 63 14676 14677 14678 /***********************************/ 14679 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG 14680 * Configure TX port sniffing for the physical port associated with the calling 14681 * function. Only a privileged function may change the port sniffing 14682 * configuration. A copy of all traffic transmitted through the port may be 14683 * delivered to a specific queue, or a set of queues with RSS. Note that these 14684 * packets are delivered with transmit timestamps in the packet prefix, not 14685 * receive timestamps, so it is likely that the queue(s) will need to be 14686 * dedicated as TX sniff receivers. 14687 */ 14688 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb 14689 #undef MC_CMD_0xfb_PRIVILEGE_CTG 14690 14691 #define MC_CMD_0xfb_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14692 14693 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ 14694 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_LEN 16 14695 /* configuration flags */ 14696 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 14697 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4 14698 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 14699 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 14700 /* receive queue handle (for RSS mode, this is the base queue) */ 14701 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 14702 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_LEN 4 14703 /* receive mode */ 14704 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 14705 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4 14706 /* enum: receive to just the specified queue */ 14707 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 14708 /* enum: receive to multiple queues using RSS context */ 14709 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 14710 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note 14711 * that these handles should be considered opaque to the host, although a value 14712 * of 0xFFFFFFFF is guaranteed never to be a valid handle. 14713 */ 14714 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 14715 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_LEN 4 14716 14717 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ 14718 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT_LEN 0 14719 14720 14721 /***********************************/ 14722 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG 14723 * Obtain the current TX port sniffing configuration for the physical port 14724 * associated with the calling function. Only a privileged function may read 14725 * the configuration. 14726 */ 14727 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc 14728 #undef MC_CMD_0xfc_PRIVILEGE_CTG 14729 14730 #define MC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14731 14732 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ 14733 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN_LEN 0 14734 14735 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ 14736 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_LEN 16 14737 /* configuration flags */ 14738 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 14739 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4 14740 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 14741 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 14742 /* receiving queue handle (for RSS mode, this is the base queue) */ 14743 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 14744 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_LEN 4 14745 /* receive mode */ 14746 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 14747 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4 14748 /* enum: receiving to just the specified queue */ 14749 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 14750 /* enum: receiving to multiple queues using RSS context */ 14751 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 14752 /* RSS context (for RX_MODE_RSS) */ 14753 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 14754 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4 14755 14756 14757 /***********************************/ 14758 /* MC_CMD_RMON_STATS_RX_ERRORS 14759 * Per queue rx error stats. 14760 */ 14761 #define MC_CMD_RMON_STATS_RX_ERRORS 0xfe 14762 #undef MC_CMD_0xfe_PRIVILEGE_CTG 14763 14764 #define MC_CMD_0xfe_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14765 14766 /* MC_CMD_RMON_STATS_RX_ERRORS_IN msgrequest */ 14767 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_LEN 8 14768 /* The rx queue to get stats for. */ 14769 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_OFST 0 14770 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_LEN 4 14771 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_OFST 4 14772 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_LEN 4 14773 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_LBN 0 14774 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_WIDTH 1 14775 14776 /* MC_CMD_RMON_STATS_RX_ERRORS_OUT msgresponse */ 14777 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_LEN 16 14778 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_OFST 0 14779 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_LEN 4 14780 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_OFST 4 14781 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_LEN 4 14782 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_OFST 8 14783 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_LEN 4 14784 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_OFST 12 14785 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_LEN 4 14786 14787 14788 /***********************************/ 14789 /* MC_CMD_GET_PCIE_RESOURCE_INFO 14790 * Find out about available PCIE resources 14791 */ 14792 #define MC_CMD_GET_PCIE_RESOURCE_INFO 0xfd 14793 #undef MC_CMD_0xfd_PRIVILEGE_CTG 14794 14795 #define MC_CMD_0xfd_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14796 14797 /* MC_CMD_GET_PCIE_RESOURCE_INFO_IN msgrequest */ 14798 #define MC_CMD_GET_PCIE_RESOURCE_INFO_IN_LEN 0 14799 14800 /* MC_CMD_GET_PCIE_RESOURCE_INFO_OUT msgresponse */ 14801 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_LEN 28 14802 /* The maximum number of PFs the device can expose */ 14803 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_OFST 0 14804 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_LEN 4 14805 /* The maximum number of VFs the device can expose in total */ 14806 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_OFST 4 14807 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_LEN 4 14808 /* The maximum number of MSI-X vectors the device can provide in total */ 14809 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_OFST 8 14810 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_LEN 4 14811 /* the number of MSI-X vectors the device will allocate by default to each PF 14812 */ 14813 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_OFST 12 14814 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_LEN 4 14815 /* the number of MSI-X vectors the device will allocate by default to each VF 14816 */ 14817 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_OFST 16 14818 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_LEN 4 14819 /* the maximum number of MSI-X vectors the device can allocate to any one PF */ 14820 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_OFST 20 14821 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_LEN 4 14822 /* the maximum number of MSI-X vectors the device can allocate to any one VF */ 14823 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_OFST 24 14824 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_LEN 4 14825 14826 14827 /***********************************/ 14828 /* MC_CMD_GET_PORT_MODES 14829 * Find out about available port modes 14830 */ 14831 #define MC_CMD_GET_PORT_MODES 0xff 14832 #undef MC_CMD_0xff_PRIVILEGE_CTG 14833 14834 #define MC_CMD_0xff_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14835 14836 /* MC_CMD_GET_PORT_MODES_IN msgrequest */ 14837 #define MC_CMD_GET_PORT_MODES_IN_LEN 0 14838 14839 /* MC_CMD_GET_PORT_MODES_OUT msgresponse */ 14840 #define MC_CMD_GET_PORT_MODES_OUT_LEN 12 14841 /* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*) */ 14842 #define MC_CMD_GET_PORT_MODES_OUT_MODES_OFST 0 14843 #define MC_CMD_GET_PORT_MODES_OUT_MODES_LEN 4 14844 /* Default (canonical) board mode */ 14845 #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_OFST 4 14846 #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_LEN 4 14847 /* Current board mode */ 14848 #define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST 8 14849 #define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_LEN 4 14850 14851 14852 /***********************************/ 14853 /* MC_CMD_READ_ATB 14854 * Sample voltages on the ATB 14855 */ 14856 #define MC_CMD_READ_ATB 0x100 14857 #undef MC_CMD_0x100_PRIVILEGE_CTG 14858 14859 #define MC_CMD_0x100_PRIVILEGE_CTG SRIOV_CTG_INSECURE 14860 14861 /* MC_CMD_READ_ATB_IN msgrequest */ 14862 #define MC_CMD_READ_ATB_IN_LEN 16 14863 #define MC_CMD_READ_ATB_IN_SIGNAL_BUS_OFST 0 14864 #define MC_CMD_READ_ATB_IN_SIGNAL_BUS_LEN 4 14865 #define MC_CMD_READ_ATB_IN_BUS_CCOM 0x0 /* enum */ 14866 #define MC_CMD_READ_ATB_IN_BUS_CKR 0x1 /* enum */ 14867 #define MC_CMD_READ_ATB_IN_BUS_CPCIE 0x8 /* enum */ 14868 #define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_OFST 4 14869 #define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_LEN 4 14870 #define MC_CMD_READ_ATB_IN_SIGNAL_SEL_OFST 8 14871 #define MC_CMD_READ_ATB_IN_SIGNAL_SEL_LEN 4 14872 #define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_OFST 12 14873 #define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_LEN 4 14874 14875 /* MC_CMD_READ_ATB_OUT msgresponse */ 14876 #define MC_CMD_READ_ATB_OUT_LEN 4 14877 #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_OFST 0 14878 #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_LEN 4 14879 14880 14881 /***********************************/ 14882 /* MC_CMD_GET_WORKAROUNDS 14883 * Read the list of all implemented and all currently enabled workarounds. The 14884 * enums here must correspond with those in MC_CMD_WORKAROUND. 14885 */ 14886 #define MC_CMD_GET_WORKAROUNDS 0x59 14887 #undef MC_CMD_0x59_PRIVILEGE_CTG 14888 14889 #define MC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14890 14891 /* MC_CMD_GET_WORKAROUNDS_OUT msgresponse */ 14892 #define MC_CMD_GET_WORKAROUNDS_OUT_LEN 8 14893 /* Each workaround is represented by a single bit according to the enums below. 14894 */ 14895 #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0 14896 #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_LEN 4 14897 #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4 14898 #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_LEN 4 14899 /* enum: Bug 17230 work around. */ 14900 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2 14901 /* enum: Bug 35388 work around (unsafe EVQ writes). */ 14902 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4 14903 /* enum: Bug35017 workaround (A64 tables must be identity map) */ 14904 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8 14905 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ 14906 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x10 14907 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution 14908 * - before adding code that queries this workaround, remember that there's 14909 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, 14910 * and will hence (incorrectly) report that the bug doesn't exist. 14911 */ 14912 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x20 14913 /* enum: Bug 26807 features present in firmware (multicast filter chaining) */ 14914 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x40 14915 /* enum: Bug 61265 work around (broken EVQ TMR writes). */ 14916 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG61265 0x80 14917 14918 14919 /***********************************/ 14920 /* MC_CMD_PRIVILEGE_MASK 14921 * Read/set privileges of an arbitrary PCIe function 14922 */ 14923 #define MC_CMD_PRIVILEGE_MASK 0x5a 14924 #undef MC_CMD_0x5a_PRIVILEGE_CTG 14925 14926 #define MC_CMD_0x5a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14927 14928 /* MC_CMD_PRIVILEGE_MASK_IN msgrequest */ 14929 #define MC_CMD_PRIVILEGE_MASK_IN_LEN 8 14930 /* The target function to have its mask read or set e.g. PF 0 = 0xFFFF0000, VF 14931 * 1,3 = 0x00030001 14932 */ 14933 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0 14934 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_LEN 4 14935 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0 14936 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_WIDTH 16 14937 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_LBN 16 14938 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_WIDTH 16 14939 #define MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */ 14940 /* New privilege mask to be set. The mask will only be changed if the MSB is 14941 * set to 1. 14942 */ 14943 #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4 14944 #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_LEN 4 14945 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */ 14946 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */ 14947 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */ 14948 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */ 14949 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */ 14950 /* enum: Deprecated. Equivalent to MAC_SPOOFING_TX combined with CHANGE_MAC. */ 14951 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20 14952 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */ 14953 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */ 14954 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */ 14955 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */ 14956 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */ 14957 /* enum: Allows to set the TX packets' source MAC address to any arbitrary MAC 14958 * adress. 14959 */ 14960 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING_TX 0x800 14961 /* enum: Privilege that allows a Function to change the MAC address configured 14962 * in its associated vAdapter/vPort. 14963 */ 14964 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_CHANGE_MAC 0x1000 14965 /* enum: Privilege that allows a Function to install filters that specify VLANs 14966 * that are not in the permit list for the associated vPort. This privilege is 14967 * primarily to support ESX where vPorts are created that restrict traffic to 14968 * only a set of permitted VLANs. See the vPort flag FLAG_VLAN_RESTRICT. 14969 */ 14970 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN 0x2000 14971 /* enum: Privilege for insecure commands. Commands that belong to this group 14972 * are not permitted on secure adapters regardless of the privilege mask. 14973 */ 14974 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE 0x4000 14975 /* enum: Trusted Server Adapter (TSA) / ServerLock. Privilege for 14976 * administrator-level operations that are not allowed from the local host once 14977 * an adapter has Bound to a remote ServerLock Controller (see doxbox 14978 * SF-117064-DG for background). 14979 */ 14980 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN_TSA_UNBOUND 0x8000 14981 /* enum: Set this bit to indicate that a new privilege mask is to be set, 14982 * otherwise the command will only read the existing mask. 14983 */ 14984 #define MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x80000000 14985 14986 /* MC_CMD_PRIVILEGE_MASK_OUT msgresponse */ 14987 #define MC_CMD_PRIVILEGE_MASK_OUT_LEN 4 14988 /* For an admin function, always all the privileges are reported. */ 14989 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0 14990 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_LEN 4 14991 14992 14993 /***********************************/ 14994 /* MC_CMD_LINK_STATE_MODE 14995 * Read/set link state mode of a VF 14996 */ 14997 #define MC_CMD_LINK_STATE_MODE 0x5c 14998 #undef MC_CMD_0x5c_PRIVILEGE_CTG 14999 15000 #define MC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 15001 15002 /* MC_CMD_LINK_STATE_MODE_IN msgrequest */ 15003 #define MC_CMD_LINK_STATE_MODE_IN_LEN 8 15004 /* The target function to have its link state mode read or set, must be a VF 15005 * e.g. VF 1,3 = 0x00030001 15006 */ 15007 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0 15008 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_LEN 4 15009 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0 15010 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_WIDTH 16 15011 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_LBN 16 15012 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_WIDTH 16 15013 /* New link state mode to be set */ 15014 #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4 15015 #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_LEN 4 15016 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */ 15017 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */ 15018 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */ 15019 /* enum: Use this value to just read the existing setting without modifying it. 15020 */ 15021 #define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff 15022 15023 /* MC_CMD_LINK_STATE_MODE_OUT msgresponse */ 15024 #define MC_CMD_LINK_STATE_MODE_OUT_LEN 4 15025 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0 15026 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_LEN 4 15027 15028 15029 /***********************************/ 15030 /* MC_CMD_GET_SNAPSHOT_LENGTH 15031 * Obtain the current range of allowable values for the SNAPSHOT_LENGTH 15032 * parameter to MC_CMD_INIT_RXQ. 15033 */ 15034 #define MC_CMD_GET_SNAPSHOT_LENGTH 0x101 15035 #undef MC_CMD_0x101_PRIVILEGE_CTG 15036 15037 #define MC_CMD_0x101_PRIVILEGE_CTG SRIOV_CTG_GENERAL 15038 15039 /* MC_CMD_GET_SNAPSHOT_LENGTH_IN msgrequest */ 15040 #define MC_CMD_GET_SNAPSHOT_LENGTH_IN_LEN 0 15041 15042 /* MC_CMD_GET_SNAPSHOT_LENGTH_OUT msgresponse */ 15043 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_LEN 8 15044 /* Minimum acceptable snapshot length. */ 15045 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_OFST 0 15046 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_LEN 4 15047 /* Maximum acceptable snapshot length. */ 15048 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_OFST 4 15049 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_LEN 4 15050 15051 15052 /***********************************/ 15053 /* MC_CMD_FUSE_DIAGS 15054 * Additional fuse diagnostics 15055 */ 15056 #define MC_CMD_FUSE_DIAGS 0x102 15057 #undef MC_CMD_0x102_PRIVILEGE_CTG 15058 15059 #define MC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_INSECURE 15060 15061 /* MC_CMD_FUSE_DIAGS_IN msgrequest */ 15062 #define MC_CMD_FUSE_DIAGS_IN_LEN 0 15063 15064 /* MC_CMD_FUSE_DIAGS_OUT msgresponse */ 15065 #define MC_CMD_FUSE_DIAGS_OUT_LEN 48 15066 /* Total number of mismatched bits between pairs in area 0 */ 15067 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_OFST 0 15068 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_LEN 4 15069 /* Total number of unexpectedly clear (set in B but not A) bits in area 0 */ 15070 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_OFST 4 15071 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_LEN 4 15072 /* Total number of unexpectedly clear (set in A but not B) bits in area 0 */ 15073 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_OFST 8 15074 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_LEN 4 15075 /* Checksum of data after logical OR of pairs in area 0 */ 15076 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_OFST 12 15077 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_LEN 4 15078 /* Total number of mismatched bits between pairs in area 1 */ 15079 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_OFST 16 15080 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_LEN 4 15081 /* Total number of unexpectedly clear (set in B but not A) bits in area 1 */ 15082 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_OFST 20 15083 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_LEN 4 15084 /* Total number of unexpectedly clear (set in A but not B) bits in area 1 */ 15085 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_OFST 24 15086 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_LEN 4 15087 /* Checksum of data after logical OR of pairs in area 1 */ 15088 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_OFST 28 15089 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_LEN 4 15090 /* Total number of mismatched bits between pairs in area 2 */ 15091 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_OFST 32 15092 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_LEN 4 15093 /* Total number of unexpectedly clear (set in B but not A) bits in area 2 */ 15094 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_OFST 36 15095 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_LEN 4 15096 /* Total number of unexpectedly clear (set in A but not B) bits in area 2 */ 15097 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_OFST 40 15098 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_LEN 4 15099 /* Checksum of data after logical OR of pairs in area 2 */ 15100 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_OFST 44 15101 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_LEN 4 15102 15103 15104 /***********************************/ 15105 /* MC_CMD_PRIVILEGE_MODIFY 15106 * Modify the privileges of a set of PCIe functions. Note that this operation 15107 * only effects non-admin functions unless the admin privilege itself is 15108 * included in one of the masks provided. 15109 */ 15110 #define MC_CMD_PRIVILEGE_MODIFY 0x60 15111 #undef MC_CMD_0x60_PRIVILEGE_CTG 15112 15113 #define MC_CMD_0x60_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15114 15115 /* MC_CMD_PRIVILEGE_MODIFY_IN msgrequest */ 15116 #define MC_CMD_PRIVILEGE_MODIFY_IN_LEN 16 15117 /* The groups of functions to have their privilege masks modified. */ 15118 #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 0 15119 #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_LEN 4 15120 #define MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */ 15121 #define MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */ 15122 #define MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */ 15123 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */ 15124 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */ 15125 #define MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */ 15126 /* For VFS_OF_PF specify the PF, for ONE specify the target function */ 15127 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4 15128 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_LEN 4 15129 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0 15130 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_WIDTH 16 15131 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_LBN 16 15132 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_WIDTH 16 15133 /* Privileges to be added to the target functions. For privilege definitions 15134 * refer to the command MC_CMD_PRIVILEGE_MASK 15135 */ 15136 #define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_OFST 8 15137 #define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_LEN 4 15138 /* Privileges to be removed from the target functions. For privilege 15139 * definitions refer to the command MC_CMD_PRIVILEGE_MASK 15140 */ 15141 #define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_OFST 12 15142 #define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_LEN 4 15143 15144 /* MC_CMD_PRIVILEGE_MODIFY_OUT msgresponse */ 15145 #define MC_CMD_PRIVILEGE_MODIFY_OUT_LEN 0 15146 15147 15148 /***********************************/ 15149 /* MC_CMD_XPM_READ_BYTES 15150 * Read XPM memory 15151 */ 15152 #define MC_CMD_XPM_READ_BYTES 0x103 15153 #undef MC_CMD_0x103_PRIVILEGE_CTG 15154 15155 #define MC_CMD_0x103_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15156 15157 /* MC_CMD_XPM_READ_BYTES_IN msgrequest */ 15158 #define MC_CMD_XPM_READ_BYTES_IN_LEN 8 15159 /* Start address (byte) */ 15160 #define MC_CMD_XPM_READ_BYTES_IN_ADDR_OFST 0 15161 #define MC_CMD_XPM_READ_BYTES_IN_ADDR_LEN 4 15162 /* Count (bytes) */ 15163 #define MC_CMD_XPM_READ_BYTES_IN_COUNT_OFST 4 15164 #define MC_CMD_XPM_READ_BYTES_IN_COUNT_LEN 4 15165 15166 /* MC_CMD_XPM_READ_BYTES_OUT msgresponse */ 15167 #define MC_CMD_XPM_READ_BYTES_OUT_LENMIN 0 15168 #define MC_CMD_XPM_READ_BYTES_OUT_LENMAX 252 15169 #define MC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num)) 15170 /* Data */ 15171 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_OFST 0 15172 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_LEN 1 15173 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MINNUM 0 15174 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MAXNUM 252 15175 15176 15177 /***********************************/ 15178 /* MC_CMD_XPM_WRITE_BYTES 15179 * Write XPM memory 15180 */ 15181 #define MC_CMD_XPM_WRITE_BYTES 0x104 15182 #undef MC_CMD_0x104_PRIVILEGE_CTG 15183 15184 #define MC_CMD_0x104_PRIVILEGE_CTG SRIOV_CTG_INSECURE 15185 15186 /* MC_CMD_XPM_WRITE_BYTES_IN msgrequest */ 15187 #define MC_CMD_XPM_WRITE_BYTES_IN_LENMIN 8 15188 #define MC_CMD_XPM_WRITE_BYTES_IN_LENMAX 252 15189 #define MC_CMD_XPM_WRITE_BYTES_IN_LEN(num) (8+1*(num)) 15190 /* Start address (byte) */ 15191 #define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_OFST 0 15192 #define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_LEN 4 15193 /* Count (bytes) */ 15194 #define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_OFST 4 15195 #define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_LEN 4 15196 /* Data */ 15197 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_OFST 8 15198 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_LEN 1 15199 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MINNUM 0 15200 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MAXNUM 244 15201 15202 /* MC_CMD_XPM_WRITE_BYTES_OUT msgresponse */ 15203 #define MC_CMD_XPM_WRITE_BYTES_OUT_LEN 0 15204 15205 15206 /***********************************/ 15207 /* MC_CMD_XPM_READ_SECTOR 15208 * Read XPM sector 15209 */ 15210 #define MC_CMD_XPM_READ_SECTOR 0x105 15211 #undef MC_CMD_0x105_PRIVILEGE_CTG 15212 15213 #define MC_CMD_0x105_PRIVILEGE_CTG SRIOV_CTG_INSECURE 15214 15215 /* MC_CMD_XPM_READ_SECTOR_IN msgrequest */ 15216 #define MC_CMD_XPM_READ_SECTOR_IN_LEN 8 15217 /* Sector index */ 15218 #define MC_CMD_XPM_READ_SECTOR_IN_INDEX_OFST 0 15219 #define MC_CMD_XPM_READ_SECTOR_IN_INDEX_LEN 4 15220 /* Sector size */ 15221 #define MC_CMD_XPM_READ_SECTOR_IN_SIZE_OFST 4 15222 #define MC_CMD_XPM_READ_SECTOR_IN_SIZE_LEN 4 15223 15224 /* MC_CMD_XPM_READ_SECTOR_OUT msgresponse */ 15225 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMIN 4 15226 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMAX 36 15227 #define MC_CMD_XPM_READ_SECTOR_OUT_LEN(num) (4+1*(num)) 15228 /* Sector type */ 15229 #define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_OFST 0 15230 #define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_LEN 4 15231 #define MC_CMD_XPM_READ_SECTOR_OUT_BLANK 0x0 /* enum */ 15232 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_128 0x1 /* enum */ 15233 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_256 0x2 /* enum */ 15234 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_DATA 0x3 /* enum */ 15235 #define MC_CMD_XPM_READ_SECTOR_OUT_INVALID 0xff /* enum */ 15236 /* Sector data */ 15237 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_OFST 4 15238 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_LEN 1 15239 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MINNUM 0 15240 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MAXNUM 32 15241 15242 15243 /***********************************/ 15244 /* MC_CMD_XPM_WRITE_SECTOR 15245 * Write XPM sector 15246 */ 15247 #define MC_CMD_XPM_WRITE_SECTOR 0x106 15248 #undef MC_CMD_0x106_PRIVILEGE_CTG 15249 15250 #define MC_CMD_0x106_PRIVILEGE_CTG SRIOV_CTG_INSECURE 15251 15252 /* MC_CMD_XPM_WRITE_SECTOR_IN msgrequest */ 15253 #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMIN 12 15254 #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMAX 44 15255 #define MC_CMD_XPM_WRITE_SECTOR_IN_LEN(num) (12+1*(num)) 15256 /* If writing fails due to an uncorrectable error, try up to RETRIES following 15257 * sectors (or until no more space available). If 0, only one write attempt is 15258 * made. Note that uncorrectable errors are unlikely, thanks to XPM self-repair 15259 * mechanism. 15260 */ 15261 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_OFST 0 15262 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_LEN 1 15263 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_OFST 1 15264 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_LEN 3 15265 /* Sector type */ 15266 #define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_OFST 4 15267 #define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_LEN 4 15268 /* Enum values, see field(s): */ 15269 /* MC_CMD_XPM_READ_SECTOR/MC_CMD_XPM_READ_SECTOR_OUT/TYPE */ 15270 /* Sector size */ 15271 #define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_OFST 8 15272 #define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_LEN 4 15273 /* Sector data */ 15274 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_OFST 12 15275 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_LEN 1 15276 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MINNUM 0 15277 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MAXNUM 32 15278 15279 /* MC_CMD_XPM_WRITE_SECTOR_OUT msgresponse */ 15280 #define MC_CMD_XPM_WRITE_SECTOR_OUT_LEN 4 15281 /* New sector index */ 15282 #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_OFST 0 15283 #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_LEN 4 15284 15285 15286 /***********************************/ 15287 /* MC_CMD_XPM_INVALIDATE_SECTOR 15288 * Invalidate XPM sector 15289 */ 15290 #define MC_CMD_XPM_INVALIDATE_SECTOR 0x107 15291 #undef MC_CMD_0x107_PRIVILEGE_CTG 15292 15293 #define MC_CMD_0x107_PRIVILEGE_CTG SRIOV_CTG_INSECURE 15294 15295 /* MC_CMD_XPM_INVALIDATE_SECTOR_IN msgrequest */ 15296 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_LEN 4 15297 /* Sector index */ 15298 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_OFST 0 15299 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_LEN 4 15300 15301 /* MC_CMD_XPM_INVALIDATE_SECTOR_OUT msgresponse */ 15302 #define MC_CMD_XPM_INVALIDATE_SECTOR_OUT_LEN 0 15303 15304 15305 /***********************************/ 15306 /* MC_CMD_XPM_BLANK_CHECK 15307 * Blank-check XPM memory and report bad locations 15308 */ 15309 #define MC_CMD_XPM_BLANK_CHECK 0x108 15310 #undef MC_CMD_0x108_PRIVILEGE_CTG 15311 15312 #define MC_CMD_0x108_PRIVILEGE_CTG SRIOV_CTG_INSECURE 15313 15314 /* MC_CMD_XPM_BLANK_CHECK_IN msgrequest */ 15315 #define MC_CMD_XPM_BLANK_CHECK_IN_LEN 8 15316 /* Start address (byte) */ 15317 #define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_OFST 0 15318 #define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_LEN 4 15319 /* Count (bytes) */ 15320 #define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_OFST 4 15321 #define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_LEN 4 15322 15323 /* MC_CMD_XPM_BLANK_CHECK_OUT msgresponse */ 15324 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMIN 4 15325 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMAX 252 15326 #define MC_CMD_XPM_BLANK_CHECK_OUT_LEN(num) (4+2*(num)) 15327 /* Total number of bad (non-blank) locations */ 15328 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_OFST 0 15329 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_LEN 4 15330 /* Addresses of bad locations (may be less than BAD_COUNT, if all cannot fit 15331 * into MCDI response) 15332 */ 15333 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_OFST 4 15334 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_LEN 2 15335 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MINNUM 0 15336 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MAXNUM 124 15337 15338 15339 /***********************************/ 15340 /* MC_CMD_XPM_REPAIR 15341 * Blank-check and repair XPM memory 15342 */ 15343 #define MC_CMD_XPM_REPAIR 0x109 15344 #undef MC_CMD_0x109_PRIVILEGE_CTG 15345 15346 #define MC_CMD_0x109_PRIVILEGE_CTG SRIOV_CTG_INSECURE 15347 15348 /* MC_CMD_XPM_REPAIR_IN msgrequest */ 15349 #define MC_CMD_XPM_REPAIR_IN_LEN 8 15350 /* Start address (byte) */ 15351 #define MC_CMD_XPM_REPAIR_IN_ADDR_OFST 0 15352 #define MC_CMD_XPM_REPAIR_IN_ADDR_LEN 4 15353 /* Count (bytes) */ 15354 #define MC_CMD_XPM_REPAIR_IN_COUNT_OFST 4 15355 #define MC_CMD_XPM_REPAIR_IN_COUNT_LEN 4 15356 15357 /* MC_CMD_XPM_REPAIR_OUT msgresponse */ 15358 #define MC_CMD_XPM_REPAIR_OUT_LEN 0 15359 15360 15361 /***********************************/ 15362 /* MC_CMD_XPM_DECODER_TEST 15363 * Test XPM memory address decoders for gross manufacturing defects. Can only 15364 * be performed on an unprogrammed part. 15365 */ 15366 #define MC_CMD_XPM_DECODER_TEST 0x10a 15367 #undef MC_CMD_0x10a_PRIVILEGE_CTG 15368 15369 #define MC_CMD_0x10a_PRIVILEGE_CTG SRIOV_CTG_INSECURE 15370 15371 /* MC_CMD_XPM_DECODER_TEST_IN msgrequest */ 15372 #define MC_CMD_XPM_DECODER_TEST_IN_LEN 0 15373 15374 /* MC_CMD_XPM_DECODER_TEST_OUT msgresponse */ 15375 #define MC_CMD_XPM_DECODER_TEST_OUT_LEN 0 15376 15377 15378 /***********************************/ 15379 /* MC_CMD_XPM_WRITE_TEST 15380 * XPM memory write test. Test XPM write logic for gross manufacturing defects 15381 * by writing to a dedicated test row. There are 16 locations in the test row 15382 * and the test can only be performed on locations that have not been 15383 * previously used (i.e. can be run at most 16 times). The test will pick the 15384 * first available location to use, or fail with ENOSPC if none left. 15385 */ 15386 #define MC_CMD_XPM_WRITE_TEST 0x10b 15387 #undef MC_CMD_0x10b_PRIVILEGE_CTG 15388 15389 #define MC_CMD_0x10b_PRIVILEGE_CTG SRIOV_CTG_INSECURE 15390 15391 /* MC_CMD_XPM_WRITE_TEST_IN msgrequest */ 15392 #define MC_CMD_XPM_WRITE_TEST_IN_LEN 0 15393 15394 /* MC_CMD_XPM_WRITE_TEST_OUT msgresponse */ 15395 #define MC_CMD_XPM_WRITE_TEST_OUT_LEN 0 15396 15397 15398 /***********************************/ 15399 /* MC_CMD_EXEC_SIGNED 15400 * Check the CMAC of the contents of IMEM and DMEM against the value supplied 15401 * and if correct begin execution from the start of IMEM. The caller supplies a 15402 * key ID, the length of IMEM and DMEM to validate and the expected CMAC. CMAC 15403 * computation runs from the start of IMEM, and from the start of DMEM + 16k, 15404 * to match flash booting. The command will respond with EINVAL if the CMAC 15405 * does match, otherwise it will respond with success before it jumps to IMEM. 15406 */ 15407 #define MC_CMD_EXEC_SIGNED 0x10c 15408 #undef MC_CMD_0x10c_PRIVILEGE_CTG 15409 15410 #define MC_CMD_0x10c_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 15411 15412 /* MC_CMD_EXEC_SIGNED_IN msgrequest */ 15413 #define MC_CMD_EXEC_SIGNED_IN_LEN 28 15414 /* the length of code to include in the CMAC */ 15415 #define MC_CMD_EXEC_SIGNED_IN_CODELEN_OFST 0 15416 #define MC_CMD_EXEC_SIGNED_IN_CODELEN_LEN 4 15417 /* the length of date to include in the CMAC */ 15418 #define MC_CMD_EXEC_SIGNED_IN_DATALEN_OFST 4 15419 #define MC_CMD_EXEC_SIGNED_IN_DATALEN_LEN 4 15420 /* the XPM sector containing the key to use */ 15421 #define MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_OFST 8 15422 #define MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_LEN 4 15423 /* the expected CMAC value */ 15424 #define MC_CMD_EXEC_SIGNED_IN_CMAC_OFST 12 15425 #define MC_CMD_EXEC_SIGNED_IN_CMAC_LEN 16 15426 15427 /* MC_CMD_EXEC_SIGNED_OUT msgresponse */ 15428 #define MC_CMD_EXEC_SIGNED_OUT_LEN 0 15429 15430 15431 /***********************************/ 15432 /* MC_CMD_PREPARE_SIGNED 15433 * Prepare to upload a signed image. This will scrub the specified length of 15434 * the data region, which must be at least as large as the DATALEN supplied to 15435 * MC_CMD_EXEC_SIGNED. 15436 */ 15437 #define MC_CMD_PREPARE_SIGNED 0x10d 15438 #undef MC_CMD_0x10d_PRIVILEGE_CTG 15439 15440 #define MC_CMD_0x10d_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 15441 15442 /* MC_CMD_PREPARE_SIGNED_IN msgrequest */ 15443 #define MC_CMD_PREPARE_SIGNED_IN_LEN 4 15444 /* the length of data area to clear */ 15445 #define MC_CMD_PREPARE_SIGNED_IN_DATALEN_OFST 0 15446 #define MC_CMD_PREPARE_SIGNED_IN_DATALEN_LEN 4 15447 15448 /* MC_CMD_PREPARE_SIGNED_OUT msgresponse */ 15449 #define MC_CMD_PREPARE_SIGNED_OUT_LEN 0 15450 15451 15452 /***********************************/ 15453 /* MC_CMD_SET_SECURITY_RULE 15454 * Set blacklist and/or whitelist action for a particular match criteria. 15455 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 15456 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 15457 * been used in any released code and may change during development. This note 15458 * will be removed once it is regarded as stable. 15459 */ 15460 #define MC_CMD_SET_SECURITY_RULE 0x10f 15461 #undef MC_CMD_0x10f_PRIVILEGE_CTG 15462 15463 #define MC_CMD_0x10f_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 15464 15465 /* MC_CMD_SET_SECURITY_RULE_IN msgrequest */ 15466 #define MC_CMD_SET_SECURITY_RULE_IN_LEN 92 15467 /* fields to include in match criteria */ 15468 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_FIELDS_OFST 0 15469 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_FIELDS_LEN 4 15470 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_IP_LBN 0 15471 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_IP_WIDTH 1 15472 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_IP_LBN 1 15473 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_IP_WIDTH 1 15474 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_MAC_LBN 2 15475 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_MAC_WIDTH 1 15476 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORT_LBN 3 15477 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORT_WIDTH 1 15478 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_MAC_LBN 4 15479 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_MAC_WIDTH 1 15480 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORT_LBN 5 15481 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORT_WIDTH 1 15482 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_ETHER_TYPE_LBN 6 15483 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_ETHER_TYPE_WIDTH 1 15484 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_INNER_VLAN_LBN 7 15485 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_INNER_VLAN_WIDTH 1 15486 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_OUTER_VLAN_LBN 8 15487 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_OUTER_VLAN_WIDTH 1 15488 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_IP_PROTO_LBN 9 15489 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_IP_PROTO_WIDTH 1 15490 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_PHYSICAL_PORT_LBN 10 15491 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_PHYSICAL_PORT_WIDTH 1 15492 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_RESERVED_LBN 11 15493 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_RESERVED_WIDTH 1 15494 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_SUBNET_ID_LBN 12 15495 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_SUBNET_ID_WIDTH 1 15496 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORTRANGE_ID_LBN 13 15497 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORTRANGE_ID_WIDTH 1 15498 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORTRANGE_ID_LBN 14 15499 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORTRANGE_ID_WIDTH 1 15500 /* remote MAC address to match (as bytes in network order) */ 15501 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_MAC_OFST 4 15502 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_MAC_LEN 6 15503 /* remote port to match (as bytes in network order) */ 15504 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORT_OFST 10 15505 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORT_LEN 2 15506 /* local MAC address to match (as bytes in network order) */ 15507 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_MAC_OFST 12 15508 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_MAC_LEN 6 15509 /* local port to match (as bytes in network order) */ 15510 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORT_OFST 18 15511 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORT_LEN 2 15512 /* Ethernet type to match (as bytes in network order) */ 15513 #define MC_CMD_SET_SECURITY_RULE_IN_ETHER_TYPE_OFST 20 15514 #define MC_CMD_SET_SECURITY_RULE_IN_ETHER_TYPE_LEN 2 15515 /* Inner VLAN tag to match (as bytes in network order) */ 15516 #define MC_CMD_SET_SECURITY_RULE_IN_INNER_VLAN_OFST 22 15517 #define MC_CMD_SET_SECURITY_RULE_IN_INNER_VLAN_LEN 2 15518 /* Outer VLAN tag to match (as bytes in network order) */ 15519 #define MC_CMD_SET_SECURITY_RULE_IN_OUTER_VLAN_OFST 24 15520 #define MC_CMD_SET_SECURITY_RULE_IN_OUTER_VLAN_LEN 2 15521 /* IP protocol to match (in low byte; set high byte to 0) */ 15522 #define MC_CMD_SET_SECURITY_RULE_IN_IP_PROTO_OFST 26 15523 #define MC_CMD_SET_SECURITY_RULE_IN_IP_PROTO_LEN 2 15524 /* Physical port to match (as little-endian 32-bit value) */ 15525 #define MC_CMD_SET_SECURITY_RULE_IN_PHYSICAL_PORT_OFST 28 15526 #define MC_CMD_SET_SECURITY_RULE_IN_PHYSICAL_PORT_LEN 4 15527 /* Reserved; set to 0 */ 15528 #define MC_CMD_SET_SECURITY_RULE_IN_RESERVED_OFST 32 15529 #define MC_CMD_SET_SECURITY_RULE_IN_RESERVED_LEN 4 15530 /* remote IP address to match (as bytes in network order; set last 12 bytes to 15531 * 0 for IPv4 address) 15532 */ 15533 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_IP_OFST 36 15534 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_IP_LEN 16 15535 /* local IP address to match (as bytes in network order; set last 12 bytes to 0 15536 * for IPv4 address) 15537 */ 15538 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_IP_OFST 52 15539 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_IP_LEN 16 15540 /* remote subnet ID to match (as little-endian 32-bit value); note that remote 15541 * subnets are matched by mapping the remote IP address to a "subnet ID" via a 15542 * data structure which must already have been configured using 15543 * MC_CMD_SUBNET_MAP_SET_NODE appropriately 15544 */ 15545 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_SUBNET_ID_OFST 68 15546 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_SUBNET_ID_LEN 4 15547 /* remote portrange ID to match (as little-endian 32-bit value); note that 15548 * remote port ranges are matched by mapping the remote port to a "portrange 15549 * ID" via a data structure which must already have been configured using 15550 * MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE 15551 */ 15552 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORTRANGE_ID_OFST 72 15553 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORTRANGE_ID_LEN 4 15554 /* local portrange ID to match (as little-endian 32-bit value); note that local 15555 * port ranges are matched by mapping the local port to a "portrange ID" via a 15556 * data structure which must already have been configured using 15557 * MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE 15558 */ 15559 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORTRANGE_ID_OFST 76 15560 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORTRANGE_ID_LEN 4 15561 /* set the action for transmitted packets matching this rule */ 15562 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_OFST 80 15563 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_LEN 4 15564 /* enum: make no decision */ 15565 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_NONE 0x0 15566 /* enum: decide to accept the packet */ 15567 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_WHITELIST 0x1 15568 /* enum: decide to drop the packet */ 15569 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_BLACKLIST 0x2 15570 /* enum: inform the TSA controller about some sample of packets matching this 15571 * rule (via MC_CMD_TSA_INFO_IN_PKT_SAMPLE messages); may be bitwise-ORed with 15572 * either the WHITELIST or BLACKLIST action 15573 */ 15574 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_SAMPLE 0x4 15575 /* enum: do not change the current TX action */ 15576 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_UNCHANGED 0xffffffff 15577 /* set the action for received packets matching this rule */ 15578 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_OFST 84 15579 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_LEN 4 15580 /* enum: make no decision */ 15581 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_NONE 0x0 15582 /* enum: decide to accept the packet */ 15583 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_WHITELIST 0x1 15584 /* enum: decide to drop the packet */ 15585 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_BLACKLIST 0x2 15586 /* enum: inform the TSA controller about some sample of packets matching this 15587 * rule (via MC_CMD_TSA_INFO_IN_PKT_SAMPLE messages); may be bitwise-ORed with 15588 * either the WHITELIST or BLACKLIST action 15589 */ 15590 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_SAMPLE 0x4 15591 /* enum: do not change the current RX action */ 15592 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_UNCHANGED 0xffffffff 15593 /* counter ID to associate with this rule; IDs are allocated using 15594 * MC_CMD_SECURITY_RULE_COUNTER_ALLOC 15595 */ 15596 #define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_OFST 88 15597 #define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_LEN 4 15598 /* enum: special value for the null counter ID */ 15599 #define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_NONE 0x0 15600 /* enum: special value to tell the MC to allocate an available counter */ 15601 #define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_SW_AUTO 0xeeeeeeee 15602 /* enum: special value to request use of hardware counter (Medford2 only) */ 15603 #define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_HW 0xffffffff 15604 15605 /* MC_CMD_SET_SECURITY_RULE_OUT msgresponse */ 15606 #define MC_CMD_SET_SECURITY_RULE_OUT_LEN 32 15607 /* new reference count for uses of counter ID */ 15608 #define MC_CMD_SET_SECURITY_RULE_OUT_COUNTER_REFCNT_OFST 0 15609 #define MC_CMD_SET_SECURITY_RULE_OUT_COUNTER_REFCNT_LEN 4 15610 /* constructed match bits for this rule (as a tracing aid only) */ 15611 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_MATCH_BITS_OFST 4 15612 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_MATCH_BITS_LEN 12 15613 /* constructed discriminator bits for this rule (as a tracing aid only) */ 15614 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_DISCRIMINATOR_OFST 16 15615 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_DISCRIMINATOR_LEN 4 15616 /* base location for probes for this rule (as a tracing aid only) */ 15617 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_BASE_OFST 20 15618 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_BASE_LEN 4 15619 /* step for probes for this rule (as a tracing aid only) */ 15620 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_STEP_OFST 24 15621 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_STEP_LEN 4 15622 /* ID for reading back the counter */ 15623 #define MC_CMD_SET_SECURITY_RULE_OUT_COUNTER_ID_OFST 28 15624 #define MC_CMD_SET_SECURITY_RULE_OUT_COUNTER_ID_LEN 4 15625 15626 15627 /***********************************/ 15628 /* MC_CMD_RESET_SECURITY_RULES 15629 * Reset all blacklist and whitelist actions for a particular physical port, or 15630 * all ports. (Medford-only; for use by SolarSecure apps, not directly by 15631 * drivers. See SF-114946-SW.) NOTE - this message definition is provisional. 15632 * It has not yet been used in any released code and may change during 15633 * development. This note will be removed once it is regarded as stable. 15634 */ 15635 #define MC_CMD_RESET_SECURITY_RULES 0x110 15636 #undef MC_CMD_0x110_PRIVILEGE_CTG 15637 15638 #define MC_CMD_0x110_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 15639 15640 /* MC_CMD_RESET_SECURITY_RULES_IN msgrequest */ 15641 #define MC_CMD_RESET_SECURITY_RULES_IN_LEN 4 15642 /* index of physical port to reset (or ALL_PHYSICAL_PORTS to reset all) */ 15643 #define MC_CMD_RESET_SECURITY_RULES_IN_PHYSICAL_PORT_OFST 0 15644 #define MC_CMD_RESET_SECURITY_RULES_IN_PHYSICAL_PORT_LEN 4 15645 /* enum: special value to reset all physical ports */ 15646 #define MC_CMD_RESET_SECURITY_RULES_IN_ALL_PHYSICAL_PORTS 0xffffffff 15647 15648 /* MC_CMD_RESET_SECURITY_RULES_OUT msgresponse */ 15649 #define MC_CMD_RESET_SECURITY_RULES_OUT_LEN 0 15650 15651 15652 /***********************************/ 15653 /* MC_CMD_GET_SECURITY_RULESET_VERSION 15654 * Return a large hash value representing a "version" of the complete set of 15655 * currently active blacklist / whitelist rules and associated data structures. 15656 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 15657 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 15658 * been used in any released code and may change during development. This note 15659 * will be removed once it is regarded as stable. 15660 */ 15661 #define MC_CMD_GET_SECURITY_RULESET_VERSION 0x111 15662 #undef MC_CMD_0x111_PRIVILEGE_CTG 15663 15664 #define MC_CMD_0x111_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15665 15666 /* MC_CMD_GET_SECURITY_RULESET_VERSION_IN msgrequest */ 15667 #define MC_CMD_GET_SECURITY_RULESET_VERSION_IN_LEN 0 15668 15669 /* MC_CMD_GET_SECURITY_RULESET_VERSION_OUT msgresponse */ 15670 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LENMIN 1 15671 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LENMAX 252 15672 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LEN(num) (0+1*(num)) 15673 /* Opaque hash value; length may vary depending on the hash scheme used */ 15674 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_OFST 0 15675 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_LEN 1 15676 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_MINNUM 1 15677 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_MAXNUM 252 15678 15679 15680 /***********************************/ 15681 /* MC_CMD_SECURITY_RULE_COUNTER_ALLOC 15682 * Allocate counters for use with blacklist / whitelist rules. (Medford-only; 15683 * for use by SolarSecure apps, not directly by drivers. See SF-114946-SW.) 15684 * NOTE - this message definition is provisional. It has not yet been used in 15685 * any released code and may change during development. This note will be 15686 * removed once it is regarded as stable. 15687 */ 15688 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC 0x112 15689 #undef MC_CMD_0x112_PRIVILEGE_CTG 15690 15691 #define MC_CMD_0x112_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 15692 15693 /* MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN msgrequest */ 15694 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN_LEN 4 15695 /* the number of new counter IDs to request */ 15696 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN_NUM_COUNTERS_OFST 0 15697 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN_NUM_COUNTERS_LEN 4 15698 15699 /* MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT msgresponse */ 15700 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LENMIN 4 15701 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LENMAX 252 15702 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LEN(num) (4+4*(num)) 15703 /* the number of new counter IDs allocated (may be less than the number 15704 * requested if resources are unavailable) 15705 */ 15706 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_NUM_COUNTERS_OFST 0 15707 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_NUM_COUNTERS_LEN 4 15708 /* new counter ID(s) */ 15709 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_OFST 4 15710 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_LEN 4 15711 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_MINNUM 0 15712 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_MAXNUM 62 15713 15714 15715 /***********************************/ 15716 /* MC_CMD_SECURITY_RULE_COUNTER_FREE 15717 * Allocate counters for use with blacklist / whitelist rules. (Medford-only; 15718 * for use by SolarSecure apps, not directly by drivers. See SF-114946-SW.) 15719 * NOTE - this message definition is provisional. It has not yet been used in 15720 * any released code and may change during development. This note will be 15721 * removed once it is regarded as stable. 15722 */ 15723 #define MC_CMD_SECURITY_RULE_COUNTER_FREE 0x113 15724 #undef MC_CMD_0x113_PRIVILEGE_CTG 15725 15726 #define MC_CMD_0x113_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 15727 15728 /* MC_CMD_SECURITY_RULE_COUNTER_FREE_IN msgrequest */ 15729 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LENMIN 4 15730 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LENMAX 252 15731 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LEN(num) (4+4*(num)) 15732 /* the number of counter IDs to free */ 15733 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_NUM_COUNTERS_OFST 0 15734 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_NUM_COUNTERS_LEN 4 15735 /* the counter ID(s) to free */ 15736 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_OFST 4 15737 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_LEN 4 15738 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_MINNUM 0 15739 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_MAXNUM 62 15740 15741 /* MC_CMD_SECURITY_RULE_COUNTER_FREE_OUT msgresponse */ 15742 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_OUT_LEN 0 15743 15744 15745 /***********************************/ 15746 /* MC_CMD_SUBNET_MAP_SET_NODE 15747 * Atomically update a trie node in the map of subnets to subnet IDs. The 15748 * constants in the descriptions of the fields of this message may be retrieved 15749 * by the GET_SECURITY_RULE_INFO op of MC_CMD_GET_PARSER_DISP_INFO. (Medford- 15750 * only; for use by SolarSecure apps, not directly by drivers. See 15751 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 15752 * been used in any released code and may change during development. This note 15753 * will be removed once it is regarded as stable. 15754 */ 15755 #define MC_CMD_SUBNET_MAP_SET_NODE 0x114 15756 #undef MC_CMD_0x114_PRIVILEGE_CTG 15757 15758 #define MC_CMD_0x114_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 15759 15760 /* MC_CMD_SUBNET_MAP_SET_NODE_IN msgrequest */ 15761 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_LENMIN 6 15762 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_LENMAX 252 15763 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_LEN(num) (4+2*(num)) 15764 /* node to update in the range 0 .. SUBNET_MAP_NUM_NODES-1 */ 15765 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_NODE_ID_OFST 0 15766 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_NODE_ID_LEN 4 15767 /* SUBNET_MAP_NUM_ENTRIES_PER_NODE new entries; each entry is either a pointer 15768 * to the next node, expressed as an offset in the trie memory (i.e. node ID 15769 * multiplied by SUBNET_MAP_NUM_ENTRIES_PER_NODE), or a leaf value in the range 15770 * SUBNET_ID_MIN .. SUBNET_ID_MAX 15771 */ 15772 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_OFST 4 15773 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_LEN 2 15774 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_MINNUM 1 15775 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_MAXNUM 124 15776 15777 /* MC_CMD_SUBNET_MAP_SET_NODE_OUT msgresponse */ 15778 #define MC_CMD_SUBNET_MAP_SET_NODE_OUT_LEN 0 15779 15780 /* PORTRANGE_TREE_ENTRY structuredef */ 15781 #define PORTRANGE_TREE_ENTRY_LEN 4 15782 /* key for branch nodes (<= key takes left branch, > key takes right branch), 15783 * or magic value for leaf nodes 15784 */ 15785 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_OFST 0 15786 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_LEN 2 15787 #define PORTRANGE_TREE_ENTRY_LEAF_NODE_KEY 0xffff /* enum */ 15788 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_LBN 0 15789 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_WIDTH 16 15790 /* final portrange ID for leaf nodes (don't care for branch nodes) */ 15791 #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_OFST 2 15792 #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_LEN 2 15793 #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_LBN 16 15794 #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_WIDTH 16 15795 15796 15797 /***********************************/ 15798 /* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE 15799 * Atomically update the entire tree mapping remote port ranges to portrange 15800 * IDs. The constants in the descriptions of the fields of this message may be 15801 * retrieved by the GET_SECURITY_RULE_INFO op of MC_CMD_GET_PARSER_DISP_INFO. 15802 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 15803 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 15804 * been used in any released code and may change during development. This note 15805 * will be removed once it is regarded as stable. 15806 */ 15807 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE 0x115 15808 #undef MC_CMD_0x115_PRIVILEGE_CTG 15809 15810 #define MC_CMD_0x115_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 15811 15812 /* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN msgrequest */ 15813 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LENMIN 4 15814 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LENMAX 252 15815 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LEN(num) (0+4*(num)) 15816 /* PORTRANGE_TREE_NUM_ENTRIES new entries, each laid out as a 15817 * PORTRANGE_TREE_ENTRY 15818 */ 15819 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_OFST 0 15820 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_LEN 4 15821 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MINNUM 1 15822 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MAXNUM 63 15823 15824 /* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_OUT msgresponse */ 15825 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_OUT_LEN 0 15826 15827 15828 /***********************************/ 15829 /* MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE 15830 * Atomically update the entire tree mapping remote port ranges to portrange 15831 * IDs. The constants in the descriptions of the fields of this message may be 15832 * retrieved by the GET_SECURITY_RULE_INFO op of MC_CMD_GET_PARSER_DISP_INFO. 15833 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 15834 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 15835 * been used in any released code and may change during development. This note 15836 * will be removed once it is regarded as stable. 15837 */ 15838 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE 0x116 15839 #undef MC_CMD_0x116_PRIVILEGE_CTG 15840 15841 #define MC_CMD_0x116_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 15842 15843 /* MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN msgrequest */ 15844 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LENMIN 4 15845 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LENMAX 252 15846 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LEN(num) (0+4*(num)) 15847 /* PORTRANGE_TREE_NUM_ENTRIES new entries, each laid out as a 15848 * PORTRANGE_TREE_ENTRY 15849 */ 15850 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_OFST 0 15851 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_LEN 4 15852 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MINNUM 1 15853 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MAXNUM 63 15854 15855 /* MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_OUT msgresponse */ 15856 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_OUT_LEN 0 15857 15858 /* TUNNEL_ENCAP_UDP_PORT_ENTRY structuredef */ 15859 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_LEN 4 15860 /* UDP port (the standard ports are named below but any port may be used) */ 15861 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_OFST 0 15862 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LEN 2 15863 /* enum: the IANA allocated UDP port for VXLAN */ 15864 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_VXLAN_UDP_PORT 0x12b5 15865 /* enum: the IANA allocated UDP port for Geneve */ 15866 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_GENEVE_UDP_PORT 0x17c1 15867 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LBN 0 15868 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_WIDTH 16 15869 /* tunnel encapsulation protocol (only those named below are supported) */ 15870 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_OFST 2 15871 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LEN 2 15872 /* enum: This port will be used for VXLAN on both IPv4 and IPv6 */ 15873 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN 0x0 15874 /* enum: This port will be used for Geneve on both IPv4 and IPv6 */ 15875 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE 0x1 15876 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LBN 16 15877 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_WIDTH 16 15878 15879 15880 /***********************************/ 15881 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 15882 * Configure UDP ports for tunnel encapsulation hardware acceleration. The 15883 * parser-dispatcher will attempt to parse traffic on these ports as tunnel 15884 * encapsulation PDUs and filter them using the tunnel encapsulation filter 15885 * chain rather than the standard filter chain. Note that this command can 15886 * cause all functions to see a reset. (Available on Medford only.) 15887 */ 15888 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117 15889 #undef MC_CMD_0x117_PRIVILEGE_CTG 15890 15891 #define MC_CMD_0x117_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15892 15893 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN msgrequest */ 15894 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMIN 4 15895 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX 68 15896 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num) (4+4*(num)) 15897 /* Flags */ 15898 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST 0 15899 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_LEN 2 15900 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_LBN 0 15901 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_WIDTH 1 15902 /* The number of entries in the ENTRIES array */ 15903 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST 2 15904 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN 2 15905 /* Entries defining the UDP port to protocol mapping, each laid out as a 15906 * TUNNEL_ENCAP_UDP_PORT_ENTRY 15907 */ 15908 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_OFST 4 15909 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_LEN 4 15910 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MINNUM 0 15911 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM 16 15912 15913 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT msgresponse */ 15914 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN 2 15915 /* Flags */ 15916 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_OFST 0 15917 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_LEN 2 15918 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 0 15919 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_WIDTH 1 15920 15921 15922 /***********************************/ 15923 /* MC_CMD_RX_BALANCING 15924 * Configure a port upconverter to distribute the packets on both RX engines. 15925 * Packets are distributed based on a table with the destination vFIFO. The 15926 * index of the table is a hash of source and destination of IPV4 and VLAN 15927 * priority. 15928 */ 15929 #define MC_CMD_RX_BALANCING 0x118 15930 #undef MC_CMD_0x118_PRIVILEGE_CTG 15931 15932 #define MC_CMD_0x118_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 15933 15934 /* MC_CMD_RX_BALANCING_IN msgrequest */ 15935 #define MC_CMD_RX_BALANCING_IN_LEN 16 15936 /* The RX port whose upconverter table will be modified */ 15937 #define MC_CMD_RX_BALANCING_IN_PORT_OFST 0 15938 #define MC_CMD_RX_BALANCING_IN_PORT_LEN 4 15939 /* The VLAN priority associated to the table index and vFIFO */ 15940 #define MC_CMD_RX_BALANCING_IN_PRIORITY_OFST 4 15941 #define MC_CMD_RX_BALANCING_IN_PRIORITY_LEN 4 15942 /* The resulting bit of SRC^DST for indexing the table */ 15943 #define MC_CMD_RX_BALANCING_IN_SRC_DST_OFST 8 15944 #define MC_CMD_RX_BALANCING_IN_SRC_DST_LEN 4 15945 /* The RX engine to which the vFIFO in the table entry will point to */ 15946 #define MC_CMD_RX_BALANCING_IN_ENG_OFST 12 15947 #define MC_CMD_RX_BALANCING_IN_ENG_LEN 4 15948 15949 /* MC_CMD_RX_BALANCING_OUT msgresponse */ 15950 #define MC_CMD_RX_BALANCING_OUT_LEN 0 15951 15952 15953 /***********************************/ 15954 /* MC_CMD_TSA_BIND 15955 * TSAN - TSAC binding communication protocol. Refer to SF-115479-TC for more 15956 * info in respect to the binding protocol. 15957 */ 15958 #define MC_CMD_TSA_BIND 0x119 15959 #undef MC_CMD_0x119_PRIVILEGE_CTG 15960 15961 #define MC_CMD_0x119_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15962 15963 /* MC_CMD_TSA_BIND_IN msgrequest: Protocol operation code */ 15964 #define MC_CMD_TSA_BIND_IN_LEN 4 15965 #define MC_CMD_TSA_BIND_IN_OP_OFST 0 15966 #define MC_CMD_TSA_BIND_IN_OP_LEN 4 15967 /* enum: Obsolete. Use MC_CMD_SECURE_NIC_INFO_IN_STATUS. */ 15968 #define MC_CMD_TSA_BIND_OP_GET_ID 0x1 15969 /* enum: Get a binding ticket from the TSAN. The binding ticket is used as part 15970 * of the binding procedure to authorize the binding of an adapter to a TSAID. 15971 * Refer to SF-114946-SW for more information. This sub-command is only 15972 * available over a TLS secure connection between the TSAN and TSAC. 15973 */ 15974 #define MC_CMD_TSA_BIND_OP_GET_TICKET 0x2 15975 /* enum: Opcode associated with the propagation of a private key that TSAN uses 15976 * as part of post-binding authentication procedure. More specifically, TSAN 15977 * uses this key for a signing operation. TSAC uses the counterpart public key 15978 * to verify the signature. Note - The post-binding authentication occurs when 15979 * the TSAN-TSAC connection terminates and TSAN tries to reconnect. Refer to 15980 * SF-114946-SW for more information. This sub-command is only available over a 15981 * TLS secure connection between the TSAN and TSAC. 15982 */ 15983 #define MC_CMD_TSA_BIND_OP_SET_KEY 0x3 15984 /* enum: Request an insecure unbinding operation. This sub-command is available 15985 * for any privileged client. 15986 */ 15987 #define MC_CMD_TSA_BIND_OP_UNBIND 0x4 15988 /* enum: Obsolete. Use MC_CMD_TSA_BIND_OP_SECURE_UNBIND. */ 15989 #define MC_CMD_TSA_BIND_OP_UNBIND_EXT 0x5 15990 /* enum: Opcode associated with the propagation of the unbinding secret token. 15991 * TSAN persists the unbinding secret token. Refer to SF-115479-TC for more 15992 * information. This sub-command is only available over a TLS secure connection 15993 * between the TSAN and TSAC. 15994 */ 15995 #define MC_CMD_TSA_BIND_OP_SET_UNBINDTOKEN 0x6 15996 /* enum: Obsolete. Use MC_CMD_TSA_BIND_OP_SECURE_DECOMMISSION. */ 15997 #define MC_CMD_TSA_BIND_OP_DECOMMISSION 0x7 15998 /* enum: Obsolete. Use MC_CMD_GET_CERTIFICATE. */ 15999 #define MC_CMD_TSA_BIND_OP_GET_CERTIFICATE 0x8 16000 /* enum: Request a secure unbinding operation using unbinding token. This sub- 16001 * command is available for any privileged client. 16002 */ 16003 #define MC_CMD_TSA_BIND_OP_SECURE_UNBIND 0x9 16004 /* enum: Request a secure decommissioning operation. This sub-command is 16005 * available for any privileged client. 16006 */ 16007 #define MC_CMD_TSA_BIND_OP_SECURE_DECOMMISSION 0xa 16008 /* enum: Test facility that allows an adapter to be configured to behave as if 16009 * Bound to a TSA controller with restricted MCDI administrator operations. 16010 * This operation is primarily intended to aid host driver development. 16011 */ 16012 #define MC_CMD_TSA_BIND_OP_TEST_MCDI 0xb 16013 16014 /* MC_CMD_TSA_BIND_IN_GET_ID msgrequest: Obsolete. Use 16015 * MC_CMD_SECURE_NIC_INFO_IN_STATUS. 16016 */ 16017 #define MC_CMD_TSA_BIND_IN_GET_ID_LEN 20 16018 /* The operation requested. */ 16019 #define MC_CMD_TSA_BIND_IN_GET_ID_OP_OFST 0 16020 #define MC_CMD_TSA_BIND_IN_GET_ID_OP_LEN 4 16021 /* Cryptographic nonce that TSAC generates and sends to TSAN. TSAC generates 16022 * the nonce every time as part of the TSAN post-binding authentication 16023 * procedure when the TSAN-TSAC connection terminates and TSAN does need to re- 16024 * connect to the TSAC. Refer to SF-114946-SW for more information. 16025 */ 16026 #define MC_CMD_TSA_BIND_IN_GET_ID_NONCE_OFST 4 16027 #define MC_CMD_TSA_BIND_IN_GET_ID_NONCE_LEN 16 16028 16029 /* MC_CMD_TSA_BIND_IN_GET_TICKET msgrequest */ 16030 #define MC_CMD_TSA_BIND_IN_GET_TICKET_LEN 4 16031 /* The operation requested. */ 16032 #define MC_CMD_TSA_BIND_IN_GET_TICKET_OP_OFST 0 16033 #define MC_CMD_TSA_BIND_IN_GET_TICKET_OP_LEN 4 16034 16035 /* MC_CMD_TSA_BIND_IN_SET_KEY msgrequest */ 16036 #define MC_CMD_TSA_BIND_IN_SET_KEY_LENMIN 5 16037 #define MC_CMD_TSA_BIND_IN_SET_KEY_LENMAX 252 16038 #define MC_CMD_TSA_BIND_IN_SET_KEY_LEN(num) (4+1*(num)) 16039 /* The operation requested. */ 16040 #define MC_CMD_TSA_BIND_IN_SET_KEY_OP_OFST 0 16041 #define MC_CMD_TSA_BIND_IN_SET_KEY_OP_LEN 4 16042 /* This data blob contains the private key generated by the TSAC. TSAN uses 16043 * this key for a signing operation. Note- This private key is used in 16044 * conjunction with the post-binding TSAN authentication procedure that occurs 16045 * when the TSAN-TSAC connection terminates and TSAN tries to reconnect. Refer 16046 * to SF-114946-SW for more information. 16047 */ 16048 #define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_OFST 4 16049 #define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_LEN 1 16050 #define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_MINNUM 1 16051 #define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_MAXNUM 248 16052 16053 /* MC_CMD_TSA_BIND_IN_UNBIND msgrequest: Request an insecure unbinding 16054 * operation. 16055 */ 16056 #define MC_CMD_TSA_BIND_IN_UNBIND_LEN 10 16057 /* The operation requested. */ 16058 #define MC_CMD_TSA_BIND_IN_UNBIND_OP_OFST 0 16059 #define MC_CMD_TSA_BIND_IN_UNBIND_OP_LEN 4 16060 /* TSAN unique identifier for the network adapter */ 16061 #define MC_CMD_TSA_BIND_IN_UNBIND_TSANID_OFST 4 16062 #define MC_CMD_TSA_BIND_IN_UNBIND_TSANID_LEN 6 16063 16064 /* MC_CMD_TSA_BIND_IN_UNBIND_EXT msgrequest: Obsolete. Use 16065 * MC_CMD_TSA_BIND_IN_SECURE_UNBIND. 16066 */ 16067 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_LENMIN 93 16068 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_LENMAX 252 16069 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_LEN(num) (92+1*(num)) 16070 /* The operation requested. */ 16071 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_OP_OFST 0 16072 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_OP_LEN 4 16073 /* TSAN unique identifier for the network adapter */ 16074 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_TSANID_OFST 4 16075 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_TSANID_LEN 6 16076 /* Align the arguments to 32 bits */ 16077 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_TSANID_RSVD_OFST 10 16078 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_TSANID_RSVD_LEN 2 16079 /* This attribute identifies the TSA infrastructure domain. The length of the 16080 * TSAID attribute is limited to 64 bytes. This is how TSA SDK defines the max 16081 * length. Note- The TSAID is the Organizational Unit Name filed as part of the 16082 * root and server certificates. 16083 */ 16084 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_TSAID_OFST 12 16085 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_TSAID_LEN 1 16086 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_TSAID_NUM 64 16087 /* Unbinding secret token. The adapter validates this unbinding token by 16088 * comparing it against the one stored on the adapter as part of the 16089 * MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN msgrequest. Refer to SF-115479-TC for 16090 * more information. 16091 */ 16092 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_UNBINDTOKEN_OFST 76 16093 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_UNBINDTOKEN_LEN 16 16094 /* This is the signature of the above mentioned fields- TSANID, TSAID and 16095 * UNBINDTOKEN. As per current requirements, the SIG opaque data blob contains 16096 * ECDSA ECC-384 based signature. The ECC curve is secp384r1. The signature is 16097 * also ASN-1 encoded. Note- The signature is verified based on the public key 16098 * stored into the root certificate that is provisioned on the adapter side. 16099 * This key is known as the PUKtsaid. Refer to SF-115479-TC for more 16100 * information. 16101 */ 16102 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_SIG_OFST 92 16103 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_SIG_LEN 1 16104 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_SIG_MINNUM 1 16105 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_SIG_MAXNUM 160 16106 16107 /* MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN msgrequest */ 16108 #define MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_LEN 20 16109 /* The operation requested. */ 16110 #define MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_OP_OFST 0 16111 #define MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_OP_LEN 4 16112 /* Unbinding secret token. TSAN persists the unbinding secret token. Refer to 16113 * SF-115479-TC for more information. 16114 */ 16115 #define MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_UNBINDTOKEN_OFST 4 16116 #define MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_UNBINDTOKEN_LEN 16 16117 /* enum: There are situations when the binding process does not complete 16118 * successfully due to key, other attributes corruption at the database level 16119 * (Controller). Adapter can't connect to the controller anymore. To recover, 16120 * make usage of the decommission command that forces the adapter into 16121 * unbinding state. 16122 */ 16123 #define MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_ADAPTER_BINDING_FAILURE 0x1 16124 16125 /* MC_CMD_TSA_BIND_IN_DECOMMISSION msgrequest: Obsolete. Use 16126 * MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION. 16127 */ 16128 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_LENMIN 109 16129 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_LENMAX 252 16130 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_LEN(num) (108+1*(num)) 16131 /* This is the signature of the above mentioned fields- TSAID, USER and REASON. 16132 * As per current requirements, the SIG opaque data blob contains ECDSA ECC-384 16133 * based signature. The ECC curve is secp384r1. The signature is also ASN-1 16134 * encoded . Note- The signature is verified based on the public key stored 16135 * into the root certificate that is provisioned on the adapter side. This key 16136 * is known as the PUKtsaid. Refer to SF-115479-TC for more information. 16137 */ 16138 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_SIG_OFST 108 16139 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_SIG_LEN 1 16140 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_SIG_MINNUM 1 16141 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_SIG_MAXNUM 144 16142 /* The operation requested. */ 16143 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_OP_OFST 0 16144 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_OP_LEN 4 16145 /* This attribute identifies the TSA infrastructure domain. The length of the 16146 * TSAID attribute is limited to 64 bytes. This is how TSA SDK defines the max 16147 * length. Note- The TSAID is the Organizational Unit Name filed as part of the 16148 * root and server certificates. 16149 */ 16150 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_TSAID_OFST 4 16151 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_TSAID_LEN 1 16152 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_TSAID_NUM 64 16153 /* User ID that comes, as an example, from the Controller. Note- The 33 byte 16154 * length of this attribute is max length of the linux user name plus null 16155 * character. 16156 */ 16157 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_USER_OFST 68 16158 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_USER_LEN 1 16159 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_USER_NUM 33 16160 /* Align the arguments to 32 bits */ 16161 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_USER_RSVD_OFST 101 16162 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_USER_RSVD_LEN 3 16163 /* Reason of why decommissioning happens Note- The list of reasons, defined as 16164 * part of the enumeration below, can be extended. 16165 */ 16166 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_REASON_OFST 104 16167 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_REASON_LEN 4 16168 16169 /* MC_CMD_TSA_BIND_IN_GET_CERTIFICATE msgrequest: Obsolete. Use 16170 * MC_CMD_GET_CERTIFICATE. 16171 */ 16172 #define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_LEN 8 16173 /* The operation requested, must be MC_CMD_TSA_BIND_OP_GET_CERTIFICATE. */ 16174 #define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_OP_OFST 0 16175 #define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_OP_LEN 4 16176 /* Type of the certificate to be retrieved. */ 16177 #define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_TYPE_OFST 4 16178 #define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_TYPE_LEN 4 16179 #define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_UNUSED 0x0 /* enum */ 16180 /* enum: Adapter Authentication Certificate (AAC). The AAC is used by the 16181 * controller to verify the authenticity of the adapter. 16182 */ 16183 #define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_AAC 0x1 16184 /* enum: Adapter Authentication Signing Certificate (AASC). The AASC is used by 16185 * the controller to verify the validity of AAC. 16186 */ 16187 #define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_AASC 0x2 16188 16189 /* MC_CMD_TSA_BIND_IN_SECURE_UNBIND msgrequest: Request a secure unbinding 16190 * operation using unbinding token. 16191 */ 16192 #define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_LENMIN 97 16193 #define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_LENMAX 200 16194 #define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_LEN(num) (96+1*(num)) 16195 /* The operation requested, must be MC_CMD_TSA_BIND_OP_SECURE_UNBIND. */ 16196 #define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_OP_OFST 0 16197 #define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_OP_LEN 4 16198 /* Type of the message. (MESSAGE_TYPE_xxx) Must be 16199 * MESSAGE_TYPE_TSA_SECURE_UNBIND. 16200 */ 16201 #define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_MESSAGE_TYPE_OFST 4 16202 #define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_MESSAGE_TYPE_LEN 4 16203 /* TSAN unique identifier for the network adapter */ 16204 #define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_TSANID_OFST 8 16205 #define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_TSANID_LEN 6 16206 /* Align the arguments to 32 bits */ 16207 #define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_TSANID_RSVD_OFST 14 16208 #define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_TSANID_RSVD_LEN 2 16209 /* A NUL padded US-ASCII string identifying the TSA infrastructure domain. This 16210 * field is for information only, and not used by the firmware. Note- The TSAID 16211 * is the Organizational Unit Name field as part of the root and server 16212 * certificates. 16213 */ 16214 #define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_TSAID_OFST 16 16215 #define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_TSAID_LEN 1 16216 #define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_TSAID_NUM 64 16217 /* Unbinding secret token. The adapter validates this unbinding token by 16218 * comparing it against the one stored on the adapter as part of the 16219 * MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN msgrequest. Refer to SF-115479-TC for 16220 * more information. 16221 */ 16222 #define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_UNBINDTOKEN_OFST 80 16223 #define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_UNBINDTOKEN_LEN 16 16224 /* The signature computed and encoded as specified by MESSAGE_TYPE. */ 16225 #define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_SIG_OFST 96 16226 #define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_SIG_LEN 1 16227 #define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_SIG_MINNUM 1 16228 #define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_SIG_MAXNUM 104 16229 16230 /* MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION msgrequest: Request a secure 16231 * decommissioning operation. 16232 */ 16233 #define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_LENMIN 113 16234 #define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_LENMAX 216 16235 #define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_LEN(num) (112+1*(num)) 16236 /* The operation requested, must be MC_CMD_TSA_BIND_OP_SECURE_DECOMMISSION. */ 16237 #define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_OP_OFST 0 16238 #define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_OP_LEN 4 16239 /* Type of the message. (MESSAGE_TYPE_xxx) Must be 16240 * MESSAGE_TYPE_SECURE_DECOMMISSION. 16241 */ 16242 #define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_MESSAGE_TYPE_OFST 4 16243 #define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_MESSAGE_TYPE_LEN 4 16244 /* A NUL padded US-ASCII string identifying the TSA infrastructure domain. This 16245 * field is for information only, and not used by the firmware. Note- The TSAID 16246 * is the Organizational Unit Name field as part of the root and server 16247 * certificates. 16248 */ 16249 #define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_TSAID_OFST 8 16250 #define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_TSAID_LEN 1 16251 #define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_TSAID_NUM 64 16252 /* A NUL padded US-ASCII string containing user name of the creator of the 16253 * decommissioning ticket. This field is for information only, and not used by 16254 * the firmware. 16255 */ 16256 #define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_USER_OFST 72 16257 #define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_USER_LEN 1 16258 #define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_USER_NUM 36 16259 /* Reason of why decommissioning happens */ 16260 #define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_REASON_OFST 108 16261 #define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_REASON_LEN 4 16262 /* enum: There are situations when the binding process does not complete 16263 * successfully due to key, other attributes corruption at the database level 16264 * (Controller). Adapter can't connect to the controller anymore. To recover, 16265 * use the decommission command to force the adapter into unbound state. 16266 */ 16267 #define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_ADAPTER_BINDING_FAILURE 0x1 16268 /* The signature computed and encoded as specified by MESSAGE_TYPE. */ 16269 #define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_SIG_OFST 112 16270 #define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_SIG_LEN 1 16271 #define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_SIG_MINNUM 1 16272 #define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_SIG_MAXNUM 104 16273 16274 /* MC_CMD_TSA_BIND_IN_TEST_MCDI msgrequest: Test mode that emulates MCDI 16275 * interface restrictions of a bound adapter. This operation is intended for 16276 * test use on adapters that are not deployed and bound to a TSA Controller. 16277 * Using it on a Bound adapter will succeed but will not alter the MCDI 16278 * privileges as MCDI operations will already be restricted. 16279 */ 16280 #define MC_CMD_TSA_BIND_IN_TEST_MCDI_LEN 8 16281 /* The operation requested must be MC_CMD_TSA_BIND_OP_TEST_MCDI. */ 16282 #define MC_CMD_TSA_BIND_IN_TEST_MCDI_OP_OFST 0 16283 #define MC_CMD_TSA_BIND_IN_TEST_MCDI_OP_LEN 4 16284 /* Enable or disable emulation of bound adapter */ 16285 #define MC_CMD_TSA_BIND_IN_TEST_MCDI_CTRL_OFST 4 16286 #define MC_CMD_TSA_BIND_IN_TEST_MCDI_CTRL_LEN 4 16287 #define MC_CMD_TSA_BIND_IN_TEST_MCDI_DISABLE 0x0 /* enum */ 16288 #define MC_CMD_TSA_BIND_IN_TEST_MCDI_ENABLE 0x1 /* enum */ 16289 16290 /* MC_CMD_TSA_BIND_OUT_GET_ID msgresponse: Obsolete. Use 16291 * MC_CMD_SECURE_NIC_INFO_OUT_STATUS. 16292 */ 16293 #define MC_CMD_TSA_BIND_OUT_GET_ID_LENMIN 15 16294 #define MC_CMD_TSA_BIND_OUT_GET_ID_LENMAX 252 16295 #define MC_CMD_TSA_BIND_OUT_GET_ID_LEN(num) (14+1*(num)) 16296 /* The protocol operation code MC_CMD_TSA_BIND_OP_GET_ID that is sent back to 16297 * the caller. 16298 */ 16299 #define MC_CMD_TSA_BIND_OUT_GET_ID_OP_OFST 0 16300 #define MC_CMD_TSA_BIND_OUT_GET_ID_OP_LEN 4 16301 /* Rules engine type. Note- The rules engine type allows TSAC to further 16302 * identify the connected endpoint (e.g. TSAN, NIC Emulator) type and take the 16303 * proper action accordingly. As an example, TSAC uses the rules engine type to 16304 * select the SF key that differs in the case of TSAN vs. NIC Emulator. 16305 */ 16306 #define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_OFST 4 16307 #define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_LEN 4 16308 /* enum: Hardware rules engine. */ 16309 #define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_TSAN 0x1 16310 /* enum: Nic emulator rules engine. */ 16311 #define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_NEMU 0x2 16312 /* enum: SSFE. */ 16313 #define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_SSFE 0x3 16314 /* TSAN unique identifier for the network adapter */ 16315 #define MC_CMD_TSA_BIND_OUT_GET_ID_TSANID_OFST 8 16316 #define MC_CMD_TSA_BIND_OUT_GET_ID_TSANID_LEN 6 16317 /* The signature data blob. The signature is computed against the message 16318 * formed by TSAN ID concatenated with the NONCE value. Refer to SF-115479-TC 16319 * for more information also in respect to the private keys that are used to 16320 * sign the message based on TSAN pre/post-binding authentication procedure. 16321 */ 16322 #define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_OFST 14 16323 #define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_LEN 1 16324 #define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_MINNUM 1 16325 #define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_MAXNUM 238 16326 16327 /* MC_CMD_TSA_BIND_OUT_GET_TICKET msgresponse */ 16328 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_LENMIN 5 16329 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_LENMAX 252 16330 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_LEN(num) (4+1*(num)) 16331 /* The protocol operation code MC_CMD_TSA_BIND_OP_GET_TICKET that is sent back 16332 * to the caller. 16333 */ 16334 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_OP_OFST 0 16335 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_OP_LEN 4 16336 /* The ticket represents the data blob construct that TSAN sends to TSAC as 16337 * part of the binding protocol. From the TSAN perspective the ticket is an 16338 * opaque construct. For more info refer to SF-115479-TC. 16339 */ 16340 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_OFST 4 16341 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_LEN 1 16342 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_MINNUM 1 16343 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_MAXNUM 248 16344 16345 /* MC_CMD_TSA_BIND_OUT_SET_KEY msgresponse */ 16346 #define MC_CMD_TSA_BIND_OUT_SET_KEY_LEN 4 16347 /* The protocol operation code MC_CMD_TSA_BIND_OP_SET_KEY that is sent back to 16348 * the caller. 16349 */ 16350 #define MC_CMD_TSA_BIND_OUT_SET_KEY_OP_OFST 0 16351 #define MC_CMD_TSA_BIND_OUT_SET_KEY_OP_LEN 4 16352 16353 /* MC_CMD_TSA_BIND_OUT_UNBIND msgresponse: Response to insecure unbind request. 16354 */ 16355 #define MC_CMD_TSA_BIND_OUT_UNBIND_LEN 8 16356 /* Same as MC_CMD_ERR field, but included as 0 in success cases */ 16357 #define MC_CMD_TSA_BIND_OUT_UNBIND_RESULT_OFST 0 16358 #define MC_CMD_TSA_BIND_OUT_UNBIND_RESULT_LEN 4 16359 /* Extra status information */ 16360 #define MC_CMD_TSA_BIND_OUT_UNBIND_INFO_OFST 4 16361 #define MC_CMD_TSA_BIND_OUT_UNBIND_INFO_LEN 4 16362 /* enum: Unbind successful. */ 16363 #define MC_CMD_TSA_BIND_OUT_UNBIND_OK_UNBOUND 0x0 16364 /* enum: TSANID mismatch */ 16365 #define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_BAD_TSANID 0x1 16366 /* enum: Unable to remove the binding ticket from persistent storage. */ 16367 #define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_REMOVE_TICKET 0x2 16368 /* enum: TSAN is not bound to a binding ticket. */ 16369 #define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_NOT_BOUND 0x3 16370 16371 /* MC_CMD_TSA_BIND_OUT_UNBIND_EXT msgresponse: Obsolete. Use 16372 * MC_CMD_TSA_BIND_OUT_SECURE_UNBIND. 16373 */ 16374 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_LEN 8 16375 /* Same as MC_CMD_ERR field, but included as 0 in success cases */ 16376 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_RESULT_OFST 0 16377 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_RESULT_LEN 4 16378 /* Extra status information */ 16379 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_INFO_OFST 4 16380 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_INFO_LEN 4 16381 /* enum: Unbind successful. */ 16382 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_OK_UNBOUND 0x0 16383 /* enum: TSANID mismatch */ 16384 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_BAD_TSANID 0x1 16385 /* enum: Unable to remove the binding ticket from persistent storage. */ 16386 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_REMOVE_TICKET 0x2 16387 /* enum: TSAN is not bound to a binding ticket. */ 16388 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_NOT_BOUND 0x3 16389 /* enum: Invalid unbind token */ 16390 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_BAD_TOKEN 0x4 16391 /* enum: Invalid signature */ 16392 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_BAD_SIGNATURE 0x5 16393 16394 /* MC_CMD_TSA_BIND_OUT_SET_UNBINDTOKEN msgresponse */ 16395 #define MC_CMD_TSA_BIND_OUT_SET_UNBINDTOKEN_LEN 4 16396 /* The protocol operation code MC_CMD_TSA_BIND_OP_SET_UNBINDTOKEN that is sent 16397 * back to the caller. 16398 */ 16399 #define MC_CMD_TSA_BIND_OUT_SET_UNBINDTOKEN_OP_OFST 0 16400 #define MC_CMD_TSA_BIND_OUT_SET_UNBINDTOKEN_OP_LEN 4 16401 16402 /* MC_CMD_TSA_BIND_OUT_DECOMMISSION msgresponse: Obsolete. Use 16403 * MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION. 16404 */ 16405 #define MC_CMD_TSA_BIND_OUT_DECOMMISSION_LEN 4 16406 /* The protocol operation code MC_CMD_TSA_BIND_OP_DECOMMISSION that is sent 16407 * back to the caller. 16408 */ 16409 #define MC_CMD_TSA_BIND_OUT_DECOMMISSION_OP_OFST 0 16410 #define MC_CMD_TSA_BIND_OUT_DECOMMISSION_OP_LEN 4 16411 16412 /* MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE msgresponse */ 16413 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_LENMIN 9 16414 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_LENMAX 252 16415 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_LEN(num) (8+1*(num)) 16416 /* The protocol operation code MC_CMD_TSA_BIND_OP_GET_CERTIFICATE that is sent 16417 * back to the caller. 16418 */ 16419 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_OP_OFST 0 16420 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_OP_LEN 4 16421 /* Type of the certificate. */ 16422 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_TYPE_OFST 4 16423 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_TYPE_LEN 4 16424 /* Enum values, see field(s): */ 16425 /* MC_CMD_TSA_BIND_IN_GET_CERTIFICATE/TYPE */ 16426 /* The certificate data. */ 16427 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_DATA_OFST 8 16428 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_DATA_LEN 1 16429 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_DATA_MINNUM 1 16430 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_DATA_MAXNUM 244 16431 16432 /* MC_CMD_TSA_BIND_OUT_SECURE_UNBIND msgresponse: Response to secure unbind 16433 * request. 16434 */ 16435 #define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_LEN 8 16436 /* The protocol operation code that is sent back to the caller. */ 16437 #define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_OP_OFST 0 16438 #define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_OP_LEN 4 16439 #define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_RESULT_OFST 4 16440 #define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_RESULT_LEN 4 16441 /* enum: Unbind successful. */ 16442 #define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_OK_UNBOUND 0x0 16443 /* enum: TSANID mismatch */ 16444 #define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_ERR_BAD_TSANID 0x1 16445 /* enum: Unable to remove the binding ticket from persistent storage. */ 16446 #define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_ERR_REMOVE_TICKET 0x2 16447 /* enum: TSAN is not bound to a domain. */ 16448 #define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_ERR_NOT_BOUND 0x3 16449 /* enum: Invalid unbind token */ 16450 #define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_ERR_BAD_TOKEN 0x4 16451 /* enum: Invalid signature */ 16452 #define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_ERR_BAD_SIGNATURE 0x5 16453 16454 /* MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION msgresponse: Response to secure 16455 * decommission request. 16456 */ 16457 #define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_LEN 8 16458 /* The protocol operation code that is sent back to the caller. */ 16459 #define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_OP_OFST 0 16460 #define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_OP_LEN 4 16461 #define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_RESULT_OFST 4 16462 #define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_RESULT_LEN 4 16463 /* enum: Unbind successful. */ 16464 #define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_OK_UNBOUND 0x0 16465 /* enum: TSANID mismatch */ 16466 #define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_ERR_BAD_TSANID 0x1 16467 /* enum: Unable to remove the binding ticket from persistent storage. */ 16468 #define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_ERR_REMOVE_TICKET 0x2 16469 /* enum: TSAN is not bound to a domain. */ 16470 #define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_ERR_NOT_BOUND 0x3 16471 /* enum: Invalid unbind token */ 16472 #define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_ERR_BAD_TOKEN 0x4 16473 /* enum: Invalid signature */ 16474 #define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_ERR_BAD_SIGNATURE 0x5 16475 16476 /* MC_CMD_TSA_BIND_OUT_TEST_MCDI msgrequest */ 16477 #define MC_CMD_TSA_BIND_OUT_TEST_MCDI_LEN 4 16478 /* The protocol operation code MC_CMD_TSA_BIND_OP_TEST_MCDI that is sent back 16479 * to the caller. 16480 */ 16481 #define MC_CMD_TSA_BIND_OUT_TEST_MCDI_OP_OFST 0 16482 #define MC_CMD_TSA_BIND_OUT_TEST_MCDI_OP_LEN 4 16483 16484 16485 /***********************************/ 16486 /* MC_CMD_MANAGE_SECURITY_RULESET_CACHE 16487 * Manage the persistent NVRAM cache of security rules created with 16488 * MC_CMD_SET_SECURITY_RULE. Note that the cache is not automatically updated 16489 * as rules are added or removed; the active ruleset must be explicitly 16490 * committed to the cache. The cache may also be explicitly invalidated, 16491 * without affecting the currently active ruleset. When the cache is valid, it 16492 * will be loaded at power on or MC reboot, instead of the default ruleset. 16493 * Rollback of the currently active ruleset to the cached version (when it is 16494 * valid) is also supported. (Medford-only; for use by SolarSecure apps, not 16495 * directly by drivers. See SF-114946-SW.) NOTE - The only sub-operation 16496 * allowed in an adapter bound to a TSA controller from the local host is 16497 * OP_GET_CACHED_VERSION. All other sub-operations are prohibited. 16498 */ 16499 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE 0x11a 16500 #undef MC_CMD_0x11a_PRIVILEGE_CTG 16501 16502 #define MC_CMD_0x11a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 16503 16504 /* MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN msgrequest */ 16505 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_LEN 4 16506 /* the operation to perform */ 16507 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_OFST 0 16508 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_LEN 4 16509 /* enum: reports the ruleset version that is cached in persistent storage but 16510 * performs no other action 16511 */ 16512 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_GET_CACHED_VERSION 0x0 16513 /* enum: rolls back the active state to the cached version. (May fail with 16514 * ENOENT if there is no valid cached version.) 16515 */ 16516 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_ROLLBACK 0x1 16517 /* enum: commits the active state to the persistent cache */ 16518 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_COMMIT 0x2 16519 /* enum: invalidates the persistent cache without affecting the active state */ 16520 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_INVALIDATE 0x3 16521 16522 /* MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT msgresponse */ 16523 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LENMIN 5 16524 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LENMAX 252 16525 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LEN(num) (4+1*(num)) 16526 /* indicates whether the persistent cache is valid (after completion of the 16527 * requested operation in the case of rollback, commit, or invalidate) 16528 */ 16529 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_OFST 0 16530 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_LEN 4 16531 /* enum: persistent cache is invalid (the VERSION field will be empty in this 16532 * case) 16533 */ 16534 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_INVALID 0x0 16535 /* enum: persistent cache is valid */ 16536 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_VALID 0x1 16537 /* cached ruleset version (after completion of the requested operation, in the 16538 * case of rollback, commit, or invalidate) as an opaque hash value in the same 16539 * form as MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION 16540 */ 16541 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_OFST 4 16542 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_LEN 1 16543 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_MINNUM 1 16544 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_MAXNUM 248 16545 16546 16547 /***********************************/ 16548 /* MC_CMD_NVRAM_PRIVATE_APPEND 16549 * Append a single TLV to the MC_USAGE_TLV partition. Returns MC_CMD_ERR_EEXIST 16550 * if the tag is already present. 16551 */ 16552 #define MC_CMD_NVRAM_PRIVATE_APPEND 0x11c 16553 #undef MC_CMD_0x11c_PRIVILEGE_CTG 16554 16555 #define MC_CMD_0x11c_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 16556 16557 /* MC_CMD_NVRAM_PRIVATE_APPEND_IN msgrequest */ 16558 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMIN 9 16559 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMAX 252 16560 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LEN(num) (8+1*(num)) 16561 /* The tag to be appended */ 16562 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_OFST 0 16563 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_LEN 4 16564 /* The length of the data */ 16565 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_OFST 4 16566 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_LEN 4 16567 /* The data to be contained in the TLV structure */ 16568 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_OFST 8 16569 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_LEN 1 16570 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MINNUM 1 16571 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MAXNUM 244 16572 16573 /* MC_CMD_NVRAM_PRIVATE_APPEND_OUT msgresponse */ 16574 #define MC_CMD_NVRAM_PRIVATE_APPEND_OUT_LEN 0 16575 16576 16577 /***********************************/ 16578 /* MC_CMD_XPM_VERIFY_CONTENTS 16579 * Verify that the contents of the XPM memory is correct (Medford only). This 16580 * is used during manufacture to check that the XPM memory has been programmed 16581 * correctly at ATE. 16582 */ 16583 #define MC_CMD_XPM_VERIFY_CONTENTS 0x11b 16584 #undef MC_CMD_0x11b_PRIVILEGE_CTG 16585 16586 #define MC_CMD_0x11b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 16587 16588 /* MC_CMD_XPM_VERIFY_CONTENTS_IN msgrequest */ 16589 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_LEN 4 16590 /* Data type to be checked */ 16591 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_OFST 0 16592 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_LEN 4 16593 16594 /* MC_CMD_XPM_VERIFY_CONTENTS_OUT msgresponse */ 16595 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMIN 12 16596 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMAX 252 16597 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LEN(num) (12+1*(num)) 16598 /* Number of sectors found (test builds only) */ 16599 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_OFST 0 16600 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_LEN 4 16601 /* Number of bytes found (test builds only) */ 16602 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_OFST 4 16603 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_LEN 4 16604 /* Length of signature */ 16605 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_OFST 8 16606 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_LEN 4 16607 /* Signature */ 16608 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_OFST 12 16609 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_LEN 1 16610 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MINNUM 0 16611 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MAXNUM 240 16612 16613 16614 /***********************************/ 16615 /* MC_CMD_SET_EVQ_TMR 16616 * Update the timer load, timer reload and timer mode values for a given EVQ. 16617 * The requested timer values (in TMR_LOAD_REQ_NS and TMR_RELOAD_REQ_NS) will 16618 * be rounded up to the granularity supported by the hardware, then truncated 16619 * to the range supported by the hardware. The resulting value after the 16620 * rounding and truncation will be returned to the caller (in TMR_LOAD_ACT_NS 16621 * and TMR_RELOAD_ACT_NS). 16622 */ 16623 #define MC_CMD_SET_EVQ_TMR 0x120 16624 #undef MC_CMD_0x120_PRIVILEGE_CTG 16625 16626 #define MC_CMD_0x120_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16627 16628 /* MC_CMD_SET_EVQ_TMR_IN msgrequest */ 16629 #define MC_CMD_SET_EVQ_TMR_IN_LEN 16 16630 /* Function-relative queue instance */ 16631 #define MC_CMD_SET_EVQ_TMR_IN_INSTANCE_OFST 0 16632 #define MC_CMD_SET_EVQ_TMR_IN_INSTANCE_LEN 4 16633 /* Requested value for timer load (in nanoseconds) */ 16634 #define MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_OFST 4 16635 #define MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_LEN 4 16636 /* Requested value for timer reload (in nanoseconds) */ 16637 #define MC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_OFST 8 16638 #define MC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_LEN 4 16639 /* Timer mode. Meanings as per EVQ_TMR_REG.TC_TIMER_VAL */ 16640 #define MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_OFST 12 16641 #define MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_LEN 4 16642 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS 0x0 /* enum */ 16643 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START 0x1 /* enum */ 16644 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START 0x2 /* enum */ 16645 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF 0x3 /* enum */ 16646 16647 /* MC_CMD_SET_EVQ_TMR_OUT msgresponse */ 16648 #define MC_CMD_SET_EVQ_TMR_OUT_LEN 8 16649 /* Actual value for timer load (in nanoseconds) */ 16650 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_OFST 0 16651 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_LEN 4 16652 /* Actual value for timer reload (in nanoseconds) */ 16653 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_OFST 4 16654 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_LEN 4 16655 16656 16657 /***********************************/ 16658 /* MC_CMD_GET_EVQ_TMR_PROPERTIES 16659 * Query properties about the event queue timers. 16660 */ 16661 #define MC_CMD_GET_EVQ_TMR_PROPERTIES 0x122 16662 #undef MC_CMD_0x122_PRIVILEGE_CTG 16663 16664 #define MC_CMD_0x122_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16665 16666 /* MC_CMD_GET_EVQ_TMR_PROPERTIES_IN msgrequest */ 16667 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_IN_LEN 0 16668 16669 /* MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT msgresponse */ 16670 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN 36 16671 /* Reserved for future use. */ 16672 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_OFST 0 16673 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_LEN 4 16674 /* For timers updated via writes to EVQ_TMR_REG, this is the time interval (in 16675 * nanoseconds) for each increment of the timer load/reload count. The 16676 * requested duration of a timer is this value multiplied by the timer 16677 * load/reload count. 16678 */ 16679 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_OFST 4 16680 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_LEN 4 16681 /* For timers updated via writes to EVQ_TMR_REG, this is the maximum value 16682 * allowed for timer load/reload counts. 16683 */ 16684 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_OFST 8 16685 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_LEN 4 16686 /* For timers updated via writes to EVQ_TMR_REG, timer load/reload counts not a 16687 * multiple of this step size will be rounded in an implementation defined 16688 * manner. 16689 */ 16690 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_OFST 12 16691 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_LEN 4 16692 /* Maximum timer duration (in nanoseconds) for timers updated via MCDI. Only 16693 * meaningful if MC_CMD_SET_EVQ_TMR is implemented. 16694 */ 16695 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_OFST 16 16696 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_LEN 4 16697 /* Timer durations requested via MCDI that are not a multiple of this step size 16698 * will be rounded up. Only meaningful if MC_CMD_SET_EVQ_TMR is implemented. 16699 */ 16700 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_OFST 20 16701 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_LEN 4 16702 /* For timers updated using the bug35388 workaround, this is the time interval 16703 * (in nanoseconds) for each increment of the timer load/reload count. The 16704 * requested duration of a timer is this value multiplied by the timer 16705 * load/reload count. This field is only meaningful if the bug35388 workaround 16706 * is enabled. 16707 */ 16708 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_OFST 24 16709 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_LEN 4 16710 /* For timers updated using the bug35388 workaround, this is the maximum value 16711 * allowed for timer load/reload counts. This field is only meaningful if the 16712 * bug35388 workaround is enabled. 16713 */ 16714 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_OFST 28 16715 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_LEN 4 16716 /* For timers updated using the bug35388 workaround, timer load/reload counts 16717 * not a multiple of this step size will be rounded in an implementation 16718 * defined manner. This field is only meaningful if the bug35388 workaround is 16719 * enabled. 16720 */ 16721 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_OFST 32 16722 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_LEN 4 16723 16724 16725 /***********************************/ 16726 /* MC_CMD_ALLOCATE_TX_VFIFO_CP 16727 * When we use the TX_vFIFO_ULL mode, we can allocate common pools using the 16728 * non used switch buffers. 16729 */ 16730 #define MC_CMD_ALLOCATE_TX_VFIFO_CP 0x11d 16731 #undef MC_CMD_0x11d_PRIVILEGE_CTG 16732 16733 #define MC_CMD_0x11d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16734 16735 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN msgrequest */ 16736 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_LEN 20 16737 /* Desired instance. Must be set to a specific instance, which is a function 16738 * local queue index. 16739 */ 16740 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_OFST 0 16741 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_LEN 4 16742 /* Will the common pool be used as TX_vFIFO_ULL (1) */ 16743 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_OFST 4 16744 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_LEN 4 16745 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_ENABLED 0x1 /* enum */ 16746 /* enum: Using this interface without TX_vFIFO_ULL is not supported for now */ 16747 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_DISABLED 0x0 16748 /* Number of buffers to reserve for the common pool */ 16749 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_OFST 8 16750 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_LEN 4 16751 /* TX datapath to which the Common Pool is connected to. */ 16752 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_OFST 12 16753 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_LEN 4 16754 /* enum: Extracts information from function */ 16755 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 16756 /* Network port or RX Engine to which the common pool connects. */ 16757 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_OFST 16 16758 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_LEN 4 16759 /* enum: Extracts information from function */ 16760 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 */ 16761 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT0 0x0 /* enum */ 16762 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT1 0x1 /* enum */ 16763 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT2 0x2 /* enum */ 16764 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT3 0x3 /* enum */ 16765 /* enum: To enable Switch loopback with Rx engine 0 */ 16766 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE0 0x4 16767 /* enum: To enable Switch loopback with Rx engine 1 */ 16768 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE1 0x5 16769 16770 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT msgresponse */ 16771 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_LEN 4 16772 /* ID of the common pool allocated */ 16773 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_OFST 0 16774 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_LEN 4 16775 16776 16777 /***********************************/ 16778 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 16779 * When we use the TX_vFIFO_ULL mode, we can allocate vFIFOs using the 16780 * previously allocated common pools. 16781 */ 16782 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 0x11e 16783 #undef MC_CMD_0x11e_PRIVILEGE_CTG 16784 16785 #define MC_CMD_0x11e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16786 16787 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN msgrequest */ 16788 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LEN 20 16789 /* Common pool previously allocated to which the new vFIFO will be associated 16790 */ 16791 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_OFST 0 16792 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_LEN 4 16793 /* Port or RX engine to associate the vFIFO egress */ 16794 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_OFST 4 16795 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_LEN 4 16796 /* enum: Extracts information from common pool */ 16797 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_USE_CP_VALUE -0x1 16798 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT0 0x0 /* enum */ 16799 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT1 0x1 /* enum */ 16800 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT2 0x2 /* enum */ 16801 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT3 0x3 /* enum */ 16802 /* enum: To enable Switch loopback with Rx engine 0 */ 16803 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE0 0x4 16804 /* enum: To enable Switch loopback with Rx engine 1 */ 16805 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE1 0x5 16806 /* Minimum number of buffers that the pool must have */ 16807 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_OFST 8 16808 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_LEN 4 16809 /* enum: Do not check the space available */ 16810 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_NO_MINIMUM 0x0 16811 /* Will the vFIFO be used as TX_vFIFO_ULL */ 16812 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_OFST 12 16813 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_LEN 4 16814 /* Network priority of the vFIFO,if applicable */ 16815 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_OFST 16 16816 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_LEN 4 16817 /* enum: Search for the lowest unused priority */ 16818 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LOWEST_AVAILABLE -0x1 16819 16820 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT msgresponse */ 16821 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_LEN 8 16822 /* Short vFIFO ID */ 16823 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_OFST 0 16824 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_LEN 4 16825 /* Network priority of the vFIFO */ 16826 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_OFST 4 16827 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_LEN 4 16828 16829 16830 /***********************************/ 16831 /* MC_CMD_TEARDOWN_TX_VFIFO_VF 16832 * This interface clears the configuration of the given vFIFO and leaves it 16833 * ready to be re-used. 16834 */ 16835 #define MC_CMD_TEARDOWN_TX_VFIFO_VF 0x11f 16836 #undef MC_CMD_0x11f_PRIVILEGE_CTG 16837 16838 #define MC_CMD_0x11f_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16839 16840 /* MC_CMD_TEARDOWN_TX_VFIFO_VF_IN msgrequest */ 16841 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_LEN 4 16842 /* Short vFIFO ID */ 16843 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_OFST 0 16844 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_LEN 4 16845 16846 /* MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT msgresponse */ 16847 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT_LEN 0 16848 16849 16850 /***********************************/ 16851 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP 16852 * This interface clears the configuration of the given common pool and leaves 16853 * it ready to be re-used. 16854 */ 16855 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP 0x121 16856 #undef MC_CMD_0x121_PRIVILEGE_CTG 16857 16858 #define MC_CMD_0x121_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16859 16860 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN msgrequest */ 16861 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_LEN 4 16862 /* Common pool ID given when pool allocated */ 16863 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_OFST 0 16864 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_LEN 4 16865 16866 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT msgresponse */ 16867 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT_LEN 0 16868 16869 16870 /***********************************/ 16871 /* MC_CMD_REKEY 16872 * This request causes the NIC to generate a new per-NIC key and program it 16873 * into the write-once memory. During the process all flash partitions that are 16874 * protected with a CMAC are verified with the old per-NIC key and then signed 16875 * with the new per-NIC key. If the NIC has already reached its rekey limit the 16876 * REKEY op will return MC_CMD_ERR_ERANGE. The REKEY op may block until 16877 * completion or it may return 0 and continue processing, therefore the caller 16878 * must poll at least once to confirm that the rekeying has completed. The POLL 16879 * operation returns MC_CMD_ERR_EBUSY if the rekey process is still running 16880 * otherwise it will return the result of the last completed rekey operation, 16881 * or 0 if there has not been a previous rekey. 16882 */ 16883 #define MC_CMD_REKEY 0x123 16884 #undef MC_CMD_0x123_PRIVILEGE_CTG 16885 16886 #define MC_CMD_0x123_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 16887 16888 /* MC_CMD_REKEY_IN msgrequest */ 16889 #define MC_CMD_REKEY_IN_LEN 4 16890 /* the type of operation requested */ 16891 #define MC_CMD_REKEY_IN_OP_OFST 0 16892 #define MC_CMD_REKEY_IN_OP_LEN 4 16893 /* enum: Start the rekeying operation */ 16894 #define MC_CMD_REKEY_IN_OP_REKEY 0x0 16895 /* enum: Poll for completion of the rekeying operation */ 16896 #define MC_CMD_REKEY_IN_OP_POLL 0x1 16897 16898 /* MC_CMD_REKEY_OUT msgresponse */ 16899 #define MC_CMD_REKEY_OUT_LEN 0 16900 16901 16902 /***********************************/ 16903 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 16904 * This interface allows the host to find out how many common pool buffers are 16905 * not yet assigned. 16906 */ 16907 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 0x124 16908 #undef MC_CMD_0x124_PRIVILEGE_CTG 16909 16910 #define MC_CMD_0x124_PRIVILEGE_CTG SRIOV_CTG_GENERAL 16911 16912 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN msgrequest */ 16913 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN_LEN 0 16914 16915 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT msgresponse */ 16916 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_LEN 8 16917 /* Available buffers for the ENG to NET vFIFOs. */ 16918 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_OFST 0 16919 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_LEN 4 16920 /* Available buffers for the ENG to ENG and NET to ENG vFIFOs. */ 16921 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_OFST 4 16922 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_LEN 4 16923 16924 16925 /***********************************/ 16926 /* MC_CMD_SET_SECURITY_FUSES 16927 * Change the security level of the adapter by setting bits in the write-once 16928 * memory. The firmware maps each flag in the message to a set of one or more 16929 * hardware-defined or software-defined bits and sets these bits in the write- 16930 * once memory. For Medford the hardware-defined bits are defined in 16931 * SF-112079-PS 5.3, the software-defined bits are defined in xpm.h. Returns 0 16932 * if all of the required bits were set and returns MC_CMD_ERR_EIO if any of 16933 * the required bits were not set. 16934 */ 16935 #define MC_CMD_SET_SECURITY_FUSES 0x126 16936 #undef MC_CMD_0x126_PRIVILEGE_CTG 16937 16938 #define MC_CMD_0x126_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 16939 16940 /* MC_CMD_SET_SECURITY_FUSES_IN msgrequest */ 16941 #define MC_CMD_SET_SECURITY_FUSES_IN_LEN 4 16942 /* Flags specifying what type of security features are being set */ 16943 #define MC_CMD_SET_SECURITY_FUSES_IN_FLAGS_OFST 0 16944 #define MC_CMD_SET_SECURITY_FUSES_IN_FLAGS_LEN 4 16945 #define MC_CMD_SET_SECURITY_FUSES_IN_SECURE_BOOT_LBN 0 16946 #define MC_CMD_SET_SECURITY_FUSES_IN_SECURE_BOOT_WIDTH 1 16947 #define MC_CMD_SET_SECURITY_FUSES_IN_REJECT_TEST_SIGNED_LBN 1 16948 #define MC_CMD_SET_SECURITY_FUSES_IN_REJECT_TEST_SIGNED_WIDTH 1 16949 #define MC_CMD_SET_SECURITY_FUSES_IN_SOFT_CONFIG_LBN 31 16950 #define MC_CMD_SET_SECURITY_FUSES_IN_SOFT_CONFIG_WIDTH 1 16951 16952 /* MC_CMD_SET_SECURITY_FUSES_OUT msgresponse */ 16953 #define MC_CMD_SET_SECURITY_FUSES_OUT_LEN 0 16954 16955 /* MC_CMD_SET_SECURITY_FUSES_V2_OUT msgresponse */ 16956 #define MC_CMD_SET_SECURITY_FUSES_V2_OUT_LEN 4 16957 /* Flags specifying which security features are enforced on the NIC after the 16958 * flags in the request have been applied. See 16959 * MC_CMD_SET_SECURITY_FUSES_IN/FLAGS for flag definitions. 16960 */ 16961 #define MC_CMD_SET_SECURITY_FUSES_V2_OUT_FLAGS_OFST 0 16962 #define MC_CMD_SET_SECURITY_FUSES_V2_OUT_FLAGS_LEN 4 16963 16964 16965 /***********************************/ 16966 /* MC_CMD_TSA_INFO 16967 * Messages sent from TSA adapter to TSA controller. This command is only valid 16968 * when the MCDI header has MESSAGE_TYPE set to MCDI_MESSAGE_TYPE_TSA. This 16969 * command is not sent by the driver to the MC; it is sent from the MC to a TSA 16970 * controller, being treated more like an alert message rather than a command; 16971 * hence the MC does not expect a response in return. Doxbox reference 16972 * SF-117371-SW 16973 */ 16974 #define MC_CMD_TSA_INFO 0x127 16975 #undef MC_CMD_0x127_PRIVILEGE_CTG 16976 16977 #define MC_CMD_0x127_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 16978 16979 /* MC_CMD_TSA_INFO_IN msgrequest */ 16980 #define MC_CMD_TSA_INFO_IN_LEN 4 16981 #define MC_CMD_TSA_INFO_IN_OP_HDR_OFST 0 16982 #define MC_CMD_TSA_INFO_IN_OP_HDR_LEN 4 16983 #define MC_CMD_TSA_INFO_IN_OP_LBN 0 16984 #define MC_CMD_TSA_INFO_IN_OP_WIDTH 16 16985 /* enum: Information about recently discovered local IP address of the adapter 16986 */ 16987 #define MC_CMD_TSA_INFO_OP_LOCAL_IP 0x1 16988 /* enum: Information about a sampled packet that either - did not match any 16989 * black/white-list filters and was allowed by the default filter or - did not 16990 * match any black/white-list filters and was denied by the default filter 16991 */ 16992 #define MC_CMD_TSA_INFO_OP_PKT_SAMPLE 0x2 16993 16994 /* MC_CMD_TSA_INFO_IN_LOCAL_IP msgrequest: 16995 * 16996 * The TSA controller maintains a list of IP addresses valid for each port of a 16997 * TSA adapter. The TSA controller requires information from the adapter 16998 * inorder to learn new IP addresses assigned to a physical port and to 16999 * identify those that are no longer assigned to the physical port. For this 17000 * purpose, the TSA adapter snoops ARP replies, gratuitous ARP requests and ARP 17001 * probe packets seen on each physical port. This definition describes the 17002 * format of the notification message sent from a TSA adapter to a TSA 17003 * controller related to any information related to a change in IP address 17004 * assignment for a port. Doxbox reference SF-117371. 17005 * 17006 * There may be a possibility of combining multiple notifications in a single 17007 * message in future. When that happens, a new flag can be defined using the 17008 * reserved bits to describe the extended format of this notification. 17009 */ 17010 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_LEN 18 17011 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_OP_HDR_OFST 0 17012 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_OP_HDR_LEN 4 17013 /* Additional metadata describing the IP address information such as source of 17014 * information retrieval, type of IP address, physical port number. 17015 */ 17016 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_OFST 4 17017 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_LEN 4 17018 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_PORT_INDEX_LBN 0 17019 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_PORT_INDEX_WIDTH 8 17020 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_RESERVED_LBN 8 17021 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_RESERVED_WIDTH 8 17022 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_REASON_LBN 16 17023 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_REASON_WIDTH 8 17024 /* enum: ARP reply sent out of the physical port */ 17025 #define MC_CMD_TSA_INFO_IP_REASON_TX_ARP 0x0 17026 /* enum: ARP probe packet received on the physical port */ 17027 #define MC_CMD_TSA_INFO_IP_REASON_RX_ARP_PROBE 0x1 17028 /* enum: Gratuitous ARP packet received on the physical port */ 17029 #define MC_CMD_TSA_INFO_IP_REASON_RX_GRATUITOUS_ARP 0x2 17030 /* enum: DHCP ACK packet received on the physical port */ 17031 #define MC_CMD_TSA_INFO_IP_REASON_RX_DHCP_ACK 0x3 17032 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_IPV4_LBN 24 17033 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_IPV4_WIDTH 1 17034 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_RESERVED1_LBN 25 17035 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_RESERVED1_WIDTH 7 17036 /* IPV4 address retrieved from the sampled packets. This field is relevant only 17037 * when META_IPV4 is set to 1. 17038 */ 17039 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_IPV4_ADDR_OFST 8 17040 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_IPV4_ADDR_LEN 4 17041 /* Target MAC address retrieved from the sampled packet. */ 17042 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_MAC_ADDR_OFST 12 17043 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_MAC_ADDR_LEN 1 17044 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_MAC_ADDR_NUM 6 17045 17046 /* MC_CMD_TSA_INFO_IN_PKT_SAMPLE msgrequest: 17047 * 17048 * It is desireable for the TSA controller to learn the traffic pattern of 17049 * packets seen at the network port being monitored. In order to learn about 17050 * the traffic pattern, the TSA controller may want to sample packets seen at 17051 * the network port. Based on the packet samples that the TSA controller 17052 * receives from the adapter, the controller may choose to configure additional 17053 * black-list or white-list rules to allow or block packets as required. 17054 * 17055 * Although the entire sampled packet as seen on the network port is available 17056 * to the MC the length of sampled packet sent to controller is restricted by 17057 * MCDI payload size. Besides, the TSA controller does not require the entire 17058 * packet to make decisions about filter updates. Hence the packet sample being 17059 * passed to the controller is truncated to 128 bytes. This length is large 17060 * enough to hold the ethernet header, IP header and maximum length of 17061 * supported L4 protocol headers (IPv4 only, but can hold IPv6 header too, if 17062 * required in future). 17063 * 17064 * The intention is that any future changes to this message format that are not 17065 * backwards compatible will be defined with a new operation code. 17066 */ 17067 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_LEN 136 17068 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_OP_HDR_OFST 0 17069 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_OP_HDR_LEN 4 17070 /* Additional metadata describing the sampled packet */ 17071 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_OFST 4 17072 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_LEN 4 17073 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_PORT_INDEX_LBN 0 17074 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_PORT_INDEX_WIDTH 8 17075 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_DIRECTION_LBN 8 17076 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_DIRECTION_WIDTH 1 17077 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_RESERVED_LBN 9 17078 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_RESERVED_WIDTH 7 17079 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_MASK_LBN 16 17080 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_MASK_WIDTH 4 17081 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_ALLOW_LBN 16 17082 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_ALLOW_WIDTH 1 17083 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_DENY_LBN 17 17084 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_DENY_WIDTH 1 17085 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_COUNT_LBN 18 17086 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_COUNT_WIDTH 1 17087 /* 128-byte raw prefix of the sampled packet which includes the ethernet 17088 * header, IP header and L4 protocol header (only IPv4 supported initially). 17089 * This provides the controller enough information about the packet sample to 17090 * report traffic patterns seen on a network port and to make decisions 17091 * concerning rule-set updates. 17092 */ 17093 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_PACKET_DATA_OFST 8 17094 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_PACKET_DATA_LEN 1 17095 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_PACKET_DATA_NUM 128 17096 17097 /* MC_CMD_TSA_INFO_OUT msgresponse */ 17098 #define MC_CMD_TSA_INFO_OUT_LEN 0 17099 17100 17101 /***********************************/ 17102 /* MC_CMD_HOST_INFO 17103 * Commands to appply or retrieve host-related information from an adapter. 17104 * Doxbox reference SF-117371-SW 17105 */ 17106 #define MC_CMD_HOST_INFO 0x128 17107 #undef MC_CMD_0x128_PRIVILEGE_CTG 17108 17109 #define MC_CMD_0x128_PRIVILEGE_CTG SRIOV_CTG_ADMIN 17110 17111 /* MC_CMD_HOST_INFO_IN msgrequest */ 17112 #define MC_CMD_HOST_INFO_IN_LEN 4 17113 /* sub-operation code info */ 17114 #define MC_CMD_HOST_INFO_IN_OP_HDR_OFST 0 17115 #define MC_CMD_HOST_INFO_IN_OP_HDR_LEN 4 17116 #define MC_CMD_HOST_INFO_IN_OP_LBN 0 17117 #define MC_CMD_HOST_INFO_IN_OP_WIDTH 16 17118 /* enum: Read a 16-byte unique host identifier from the adapter. This UUID 17119 * helps to identify the host that an adapter is plugged into. This identifier 17120 * is ideally the system UUID retrieved and set by the UEFI driver. If the UEFI 17121 * driver is unable to extract the system UUID, it would still set a random 17122 * 16-byte value into each supported SF adapter plugged into it. Host UUIDs may 17123 * change if the system is power-cycled, however, they persist across adapter 17124 * resets. If the host UUID was not set on an adapter, due to an unsupported 17125 * version of UEFI driver, then this command returns an error. Doxbox reference 17126 * - SF-117371-SW section 'Host UUID'. 17127 */ 17128 #define MC_CMD_HOST_INFO_OP_GET_UUID 0x0 17129 /* enum: Set a 16-byte unique host identifier on the adapter to identify the 17130 * host that the adapter is plugged into. See MC_CMD_HOST_INFO_OP_GET_UUID for 17131 * further details. 17132 */ 17133 #define MC_CMD_HOST_INFO_OP_SET_UUID 0x1 17134 17135 /* MC_CMD_HOST_INFO_IN_GET_UUID msgrequest */ 17136 #define MC_CMD_HOST_INFO_IN_GET_UUID_LEN 4 17137 /* sub-operation code info */ 17138 #define MC_CMD_HOST_INFO_IN_GET_UUID_OP_HDR_OFST 0 17139 #define MC_CMD_HOST_INFO_IN_GET_UUID_OP_HDR_LEN 4 17140 17141 /* MC_CMD_HOST_INFO_OUT_GET_UUID msgresponse */ 17142 #define MC_CMD_HOST_INFO_OUT_GET_UUID_LEN 16 17143 /* 16-byte host UUID read out of the adapter. See MC_CMD_HOST_INFO_OP_GET_UUID 17144 * for further details. 17145 */ 17146 #define MC_CMD_HOST_INFO_OUT_GET_UUID_HOST_UUID_OFST 0 17147 #define MC_CMD_HOST_INFO_OUT_GET_UUID_HOST_UUID_LEN 1 17148 #define MC_CMD_HOST_INFO_OUT_GET_UUID_HOST_UUID_NUM 16 17149 17150 /* MC_CMD_HOST_INFO_IN_SET_UUID msgrequest */ 17151 #define MC_CMD_HOST_INFO_IN_SET_UUID_LEN 20 17152 /* sub-operation code info */ 17153 #define MC_CMD_HOST_INFO_IN_SET_UUID_OP_HDR_OFST 0 17154 #define MC_CMD_HOST_INFO_IN_SET_UUID_OP_HDR_LEN 4 17155 /* 16-byte host UUID set on the adapter. See MC_CMD_HOST_INFO_OP_GET_UUID for 17156 * further details. 17157 */ 17158 #define MC_CMD_HOST_INFO_IN_SET_UUID_HOST_UUID_OFST 4 17159 #define MC_CMD_HOST_INFO_IN_SET_UUID_HOST_UUID_LEN 1 17160 #define MC_CMD_HOST_INFO_IN_SET_UUID_HOST_UUID_NUM 16 17161 17162 /* MC_CMD_HOST_INFO_OUT_SET_UUID msgresponse */ 17163 #define MC_CMD_HOST_INFO_OUT_SET_UUID_LEN 0 17164 17165 17166 /***********************************/ 17167 /* MC_CMD_TSAN_INFO 17168 * Get TSA adapter information. TSA controllers query each TSA adapter to learn 17169 * some configuration parameters of each adapter. Doxbox reference SF-117371-SW 17170 * section 'Adapter Information' 17171 */ 17172 #define MC_CMD_TSAN_INFO 0x129 17173 #undef MC_CMD_0x129_PRIVILEGE_CTG 17174 17175 #define MC_CMD_0x129_PRIVILEGE_CTG SRIOV_CTG_ADMIN 17176 17177 /* MC_CMD_TSAN_INFO_IN msgrequest */ 17178 #define MC_CMD_TSAN_INFO_IN_LEN 4 17179 /* sub-operation code info */ 17180 #define MC_CMD_TSAN_INFO_IN_OP_HDR_OFST 0 17181 #define MC_CMD_TSAN_INFO_IN_OP_HDR_LEN 4 17182 #define MC_CMD_TSAN_INFO_IN_OP_LBN 0 17183 #define MC_CMD_TSAN_INFO_IN_OP_WIDTH 16 17184 /* enum: Read configuration parameters and IDs that uniquely identify an 17185 * adapter. The parameters include - host identification, adapter 17186 * identification string and number of physical ports on the adapter. 17187 */ 17188 #define MC_CMD_TSAN_INFO_OP_GET_CFG 0x0 17189 17190 /* MC_CMD_TSAN_INFO_IN_GET_CFG msgrequest */ 17191 #define MC_CMD_TSAN_INFO_IN_GET_CFG_LEN 4 17192 /* sub-operation code info */ 17193 #define MC_CMD_TSAN_INFO_IN_GET_CFG_OP_HDR_OFST 0 17194 #define MC_CMD_TSAN_INFO_IN_GET_CFG_OP_HDR_LEN 4 17195 17196 /* MC_CMD_TSAN_INFO_OUT_GET_CFG msgresponse */ 17197 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_LEN 26 17198 /* Information about the configuration parameters returned in this response. */ 17199 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_CONFIG_WORD_OFST 0 17200 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_CONFIG_WORD_LEN 4 17201 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_CAP_FLAGS_LBN 0 17202 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_CAP_FLAGS_WIDTH 16 17203 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_FLAG_HOST_UUID_VALID_LBN 0 17204 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_FLAG_HOST_UUID_VALID_WIDTH 1 17205 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_NUM_PORTS_LBN 16 17206 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_NUM_PORTS_WIDTH 8 17207 /* 16-byte host UUID read out of the adapter. See MC_CMD_HOST_INFO_OP_GET_UUID 17208 * for further details. 17209 */ 17210 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_HOST_UUID_OFST 4 17211 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_HOST_UUID_LEN 1 17212 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_HOST_UUID_NUM 16 17213 /* A unique identifier per adapter. The base MAC address of the card is used 17214 * for this purpose. 17215 */ 17216 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_GUID_OFST 20 17217 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_GUID_LEN 1 17218 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_GUID_NUM 6 17219 17220 /* MC_CMD_TSAN_INFO_OUT_GET_CFG_V2 msgresponse */ 17221 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_LEN 36 17222 /* Information about the configuration parameters returned in this response. */ 17223 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_CONFIG_WORD_OFST 0 17224 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_CONFIG_WORD_LEN 4 17225 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_CAP_FLAGS_LBN 0 17226 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_CAP_FLAGS_WIDTH 16 17227 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_FLAG_HOST_UUID_VALID_LBN 0 17228 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_FLAG_HOST_UUID_VALID_WIDTH 1 17229 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_NUM_PORTS_LBN 16 17230 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_NUM_PORTS_WIDTH 8 17231 /* 16-byte host UUID read out of the adapter. See MC_CMD_HOST_INFO_OP_GET_UUID 17232 * for further details. 17233 */ 17234 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_HOST_UUID_OFST 4 17235 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_HOST_UUID_LEN 1 17236 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_HOST_UUID_NUM 16 17237 /* A unique identifier per adapter. The base MAC address of the card is used 17238 * for this purpose. 17239 */ 17240 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_GUID_OFST 20 17241 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_GUID_LEN 1 17242 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_GUID_NUM 6 17243 /* Unused bytes, defined for 32-bit alignment of new fields. */ 17244 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_UNUSED_OFST 26 17245 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_UNUSED_LEN 2 17246 /* Maximum number of TSA statistics counters in each direction of dataflow 17247 * supported on the card. Note that the statistics counters are always 17248 * allocated in pairs, i.e. a counter ID is associated with one Tx and one Rx 17249 * counter. 17250 */ 17251 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_MAX_STATS_OFST 28 17252 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_MAX_STATS_LEN 4 17253 /* Width of each statistics counter (represented in bits). This gives an 17254 * indication of wrap point to the user. 17255 */ 17256 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_STATS_WIDTH_OFST 32 17257 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_STATS_WIDTH_LEN 4 17258 17259 17260 /***********************************/ 17261 /* MC_CMD_TSA_STATISTICS 17262 * TSA adapter statistics operations. 17263 */ 17264 #define MC_CMD_TSA_STATISTICS 0x130 17265 #undef MC_CMD_0x130_PRIVILEGE_CTG 17266 17267 #define MC_CMD_0x130_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 17268 17269 /* MC_CMD_TSA_STATISTICS_IN msgrequest */ 17270 #define MC_CMD_TSA_STATISTICS_IN_LEN 4 17271 /* TSA statistics sub-operation code */ 17272 #define MC_CMD_TSA_STATISTICS_IN_OP_CODE_OFST 0 17273 #define MC_CMD_TSA_STATISTICS_IN_OP_CODE_LEN 4 17274 /* enum: Get the configuration parameters that describe the TSA statistics 17275 * layout on the adapter. 17276 */ 17277 #define MC_CMD_TSA_STATISTICS_OP_GET_CONFIG 0x0 17278 /* enum: Read and/or clear TSA statistics counters. */ 17279 #define MC_CMD_TSA_STATISTICS_OP_READ_CLEAR 0x1 17280 17281 /* MC_CMD_TSA_STATISTICS_IN_GET_CONFIG msgrequest */ 17282 #define MC_CMD_TSA_STATISTICS_IN_GET_CONFIG_LEN 4 17283 /* TSA statistics sub-operation code */ 17284 #define MC_CMD_TSA_STATISTICS_IN_GET_CONFIG_OP_CODE_OFST 0 17285 #define MC_CMD_TSA_STATISTICS_IN_GET_CONFIG_OP_CODE_LEN 4 17286 17287 /* MC_CMD_TSA_STATISTICS_OUT_GET_CONFIG msgresponse */ 17288 #define MC_CMD_TSA_STATISTICS_OUT_GET_CONFIG_LEN 8 17289 /* Maximum number of TSA statistics counters in each direction of dataflow 17290 * supported on the card. Note that the statistics counters are always 17291 * allocated in pairs, i.e. a counter ID is associated with one Tx and one Rx 17292 * counter. 17293 */ 17294 #define MC_CMD_TSA_STATISTICS_OUT_GET_CONFIG_MAX_STATS_OFST 0 17295 #define MC_CMD_TSA_STATISTICS_OUT_GET_CONFIG_MAX_STATS_LEN 4 17296 /* Width of each statistics counter (represented in bits). This gives an 17297 * indication of wrap point to the user. 17298 */ 17299 #define MC_CMD_TSA_STATISTICS_OUT_GET_CONFIG_STATS_WIDTH_OFST 4 17300 #define MC_CMD_TSA_STATISTICS_OUT_GET_CONFIG_STATS_WIDTH_LEN 4 17301 17302 /* MC_CMD_TSA_STATISTICS_IN_READ_CLEAR msgrequest */ 17303 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_LENMIN 20 17304 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_LENMAX 252 17305 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_LEN(num) (16+4*(num)) 17306 /* TSA statistics sub-operation code */ 17307 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_OP_CODE_OFST 0 17308 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_OP_CODE_LEN 4 17309 /* Parameters describing the statistics operation */ 17310 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_FLAGS_OFST 4 17311 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_FLAGS_LEN 4 17312 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_READ_LBN 0 17313 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_READ_WIDTH 1 17314 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_CLEAR_LBN 1 17315 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_CLEAR_WIDTH 1 17316 /* Counter ID list specification type */ 17317 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_MODE_OFST 8 17318 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_MODE_LEN 4 17319 /* enum: The statistics counters are specified as an unordered list of 17320 * individual counter ID. 17321 */ 17322 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_LIST 0x0 17323 /* enum: The statistics counters are specified as a range of consecutive 17324 * counter IDs. 17325 */ 17326 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_RANGE 0x1 17327 /* Number of statistics counters */ 17328 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_NUM_STATS_OFST 12 17329 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_NUM_STATS_LEN 4 17330 /* Counter IDs to be read/cleared. When mode is set to LIST, this entry holds a 17331 * list of counter IDs to be operated on. When mode is set to RANGE, this entry 17332 * holds a single counter ID representing the start of the range of counter IDs 17333 * to be operated on. 17334 */ 17335 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_COUNTER_ID_OFST 16 17336 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_COUNTER_ID_LEN 4 17337 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_COUNTER_ID_MINNUM 1 17338 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_COUNTER_ID_MAXNUM 59 17339 17340 /* MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR msgresponse */ 17341 #define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_LENMIN 24 17342 #define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_LENMAX 248 17343 #define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_LEN(num) (8+16*(num)) 17344 /* Number of statistics counters returned in this response */ 17345 #define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_NUM_STATS_OFST 0 17346 #define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_NUM_STATS_LEN 4 17347 /* MC_TSA_STATISTICS_ENTRY Note that this field is expected to start at a 17348 * 64-bit aligned offset 17349 */ 17350 #define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_STATS_COUNTERS_OFST 8 17351 #define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_STATS_COUNTERS_LEN 16 17352 #define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_STATS_COUNTERS_MINNUM 1 17353 #define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_STATS_COUNTERS_MAXNUM 15 17354 17355 /* MC_TSA_STATISTICS_ENTRY structuredef */ 17356 #define MC_TSA_STATISTICS_ENTRY_LEN 16 17357 /* Tx statistics counter */ 17358 #define MC_TSA_STATISTICS_ENTRY_TX_STAT_OFST 0 17359 #define MC_TSA_STATISTICS_ENTRY_TX_STAT_LEN 8 17360 #define MC_TSA_STATISTICS_ENTRY_TX_STAT_LO_OFST 0 17361 #define MC_TSA_STATISTICS_ENTRY_TX_STAT_HI_OFST 4 17362 #define MC_TSA_STATISTICS_ENTRY_TX_STAT_LBN 0 17363 #define MC_TSA_STATISTICS_ENTRY_TX_STAT_WIDTH 64 17364 /* Rx statistics counter */ 17365 #define MC_TSA_STATISTICS_ENTRY_RX_STAT_OFST 8 17366 #define MC_TSA_STATISTICS_ENTRY_RX_STAT_LEN 8 17367 #define MC_TSA_STATISTICS_ENTRY_RX_STAT_LO_OFST 8 17368 #define MC_TSA_STATISTICS_ENTRY_RX_STAT_HI_OFST 12 17369 #define MC_TSA_STATISTICS_ENTRY_RX_STAT_LBN 64 17370 #define MC_TSA_STATISTICS_ENTRY_RX_STAT_WIDTH 64 17371 17372 17373 /***********************************/ 17374 /* MC_CMD_ERASE_INITIAL_NIC_SECRET 17375 * This request causes the NIC to find the initial NIC secret (programmed 17376 * during ATE) in XPM memory and if and only if the NIC has already been 17377 * rekeyed with MC_CMD_REKEY, erase it. This is used by manftest after 17378 * installing TSA binding certificates. See SF-117631-TC. 17379 */ 17380 #define MC_CMD_ERASE_INITIAL_NIC_SECRET 0x131 17381 #undef MC_CMD_0x131_PRIVILEGE_CTG 17382 17383 #define MC_CMD_0x131_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 17384 17385 /* MC_CMD_ERASE_INITIAL_NIC_SECRET_IN msgrequest */ 17386 #define MC_CMD_ERASE_INITIAL_NIC_SECRET_IN_LEN 0 17387 17388 /* MC_CMD_ERASE_INITIAL_NIC_SECRET_OUT msgresponse */ 17389 #define MC_CMD_ERASE_INITIAL_NIC_SECRET_OUT_LEN 0 17390 17391 17392 /***********************************/ 17393 /* MC_CMD_TSA_CONFIG 17394 * TSA adapter configuration operations. This command is used to prepare the 17395 * NIC for TSA binding. 17396 */ 17397 #define MC_CMD_TSA_CONFIG 0x64 17398 #undef MC_CMD_0x64_PRIVILEGE_CTG 17399 17400 #define MC_CMD_0x64_PRIVILEGE_CTG SRIOV_CTG_ADMIN 17401 17402 /* MC_CMD_TSA_CONFIG_IN msgrequest */ 17403 #define MC_CMD_TSA_CONFIG_IN_LEN 4 17404 /* TSA configuration sub-operation code */ 17405 #define MC_CMD_TSA_CONFIG_IN_OP_OFST 0 17406 #define MC_CMD_TSA_CONFIG_IN_OP_LEN 4 17407 /* enum: Append a single item to the tsa_config partition. Items will be 17408 * encrypted unless they are declared as non-sensitive. Returns 17409 * MC_CMD_ERR_EEXIST if the tag is already present. 17410 */ 17411 #define MC_CMD_TSA_CONFIG_OP_APPEND 0x1 17412 /* enum: Reset the tsa_config partition to a clean state. */ 17413 #define MC_CMD_TSA_CONFIG_OP_RESET 0x2 17414 /* enum: Read back a configured item from tsa_config partition. Returns 17415 * MC_CMD_ERR_ENOENT if the item doesn't exist, or MC_CMD_ERR_EPERM if the item 17416 * is declared as sensitive (i.e. is encrypted). 17417 */ 17418 #define MC_CMD_TSA_CONFIG_OP_READ 0x3 17419 17420 /* MC_CMD_TSA_CONFIG_IN_APPEND msgrequest */ 17421 #define MC_CMD_TSA_CONFIG_IN_APPEND_LENMIN 12 17422 #define MC_CMD_TSA_CONFIG_IN_APPEND_LENMAX 252 17423 #define MC_CMD_TSA_CONFIG_IN_APPEND_LEN(num) (12+1*(num)) 17424 /* TSA configuration sub-operation code. The value shall be 17425 * MC_CMD_TSA_CONFIG_OP_APPEND. 17426 */ 17427 #define MC_CMD_TSA_CONFIG_IN_APPEND_OP_OFST 0 17428 #define MC_CMD_TSA_CONFIG_IN_APPEND_OP_LEN 4 17429 /* The tag to be appended */ 17430 #define MC_CMD_TSA_CONFIG_IN_APPEND_TAG_OFST 4 17431 #define MC_CMD_TSA_CONFIG_IN_APPEND_TAG_LEN 4 17432 /* The length of the data in bytes */ 17433 #define MC_CMD_TSA_CONFIG_IN_APPEND_LENGTH_OFST 8 17434 #define MC_CMD_TSA_CONFIG_IN_APPEND_LENGTH_LEN 4 17435 /* The item data */ 17436 #define MC_CMD_TSA_CONFIG_IN_APPEND_DATA_OFST 12 17437 #define MC_CMD_TSA_CONFIG_IN_APPEND_DATA_LEN 1 17438 #define MC_CMD_TSA_CONFIG_IN_APPEND_DATA_MINNUM 0 17439 #define MC_CMD_TSA_CONFIG_IN_APPEND_DATA_MAXNUM 240 17440 17441 /* MC_CMD_TSA_CONFIG_OUT_APPEND msgresponse */ 17442 #define MC_CMD_TSA_CONFIG_OUT_APPEND_LEN 0 17443 17444 /* MC_CMD_TSA_CONFIG_IN_RESET msgrequest */ 17445 #define MC_CMD_TSA_CONFIG_IN_RESET_LEN 4 17446 /* TSA configuration sub-operation code. The value shall be 17447 * MC_CMD_TSA_CONFIG_OP_RESET. 17448 */ 17449 #define MC_CMD_TSA_CONFIG_IN_RESET_OP_OFST 0 17450 #define MC_CMD_TSA_CONFIG_IN_RESET_OP_LEN 4 17451 17452 /* MC_CMD_TSA_CONFIG_OUT_RESET msgresponse */ 17453 #define MC_CMD_TSA_CONFIG_OUT_RESET_LEN 0 17454 17455 /* MC_CMD_TSA_CONFIG_IN_READ msgrequest */ 17456 #define MC_CMD_TSA_CONFIG_IN_READ_LEN 8 17457 /* TSA configuration sub-operation code. The value shall be 17458 * MC_CMD_TSA_CONFIG_OP_READ. 17459 */ 17460 #define MC_CMD_TSA_CONFIG_IN_READ_OP_OFST 0 17461 #define MC_CMD_TSA_CONFIG_IN_READ_OP_LEN 4 17462 /* The tag to be read */ 17463 #define MC_CMD_TSA_CONFIG_IN_READ_TAG_OFST 4 17464 #define MC_CMD_TSA_CONFIG_IN_READ_TAG_LEN 4 17465 17466 /* MC_CMD_TSA_CONFIG_OUT_READ msgresponse */ 17467 #define MC_CMD_TSA_CONFIG_OUT_READ_LENMIN 8 17468 #define MC_CMD_TSA_CONFIG_OUT_READ_LENMAX 252 17469 #define MC_CMD_TSA_CONFIG_OUT_READ_LEN(num) (8+1*(num)) 17470 /* The tag that was read */ 17471 #define MC_CMD_TSA_CONFIG_OUT_READ_TAG_OFST 0 17472 #define MC_CMD_TSA_CONFIG_OUT_READ_TAG_LEN 4 17473 /* The length of the data in bytes */ 17474 #define MC_CMD_TSA_CONFIG_OUT_READ_LENGTH_OFST 4 17475 #define MC_CMD_TSA_CONFIG_OUT_READ_LENGTH_LEN 4 17476 /* The data of the item. */ 17477 #define MC_CMD_TSA_CONFIG_OUT_READ_DATA_OFST 8 17478 #define MC_CMD_TSA_CONFIG_OUT_READ_DATA_LEN 1 17479 #define MC_CMD_TSA_CONFIG_OUT_READ_DATA_MINNUM 0 17480 #define MC_CMD_TSA_CONFIG_OUT_READ_DATA_MAXNUM 244 17481 17482 /* MC_TSA_IPV4_ITEM structuredef */ 17483 #define MC_TSA_IPV4_ITEM_LEN 8 17484 /* Additional metadata describing the IP address information such as the 17485 * physical port number the address is being used on. Unused space in this 17486 * field is reserved for future expansion. 17487 */ 17488 #define MC_TSA_IPV4_ITEM_IPV4_ADDR_META_OFST 0 17489 #define MC_TSA_IPV4_ITEM_IPV4_ADDR_META_LEN 4 17490 #define MC_TSA_IPV4_ITEM_PORT_IDX_LBN 0 17491 #define MC_TSA_IPV4_ITEM_PORT_IDX_WIDTH 8 17492 #define MC_TSA_IPV4_ITEM_IPV4_ADDR_META_LBN 0 17493 #define MC_TSA_IPV4_ITEM_IPV4_ADDR_META_WIDTH 32 17494 /* The IPv4 address in little endian byte order. */ 17495 #define MC_TSA_IPV4_ITEM_IPV4_ADDR_OFST 4 17496 #define MC_TSA_IPV4_ITEM_IPV4_ADDR_LEN 4 17497 #define MC_TSA_IPV4_ITEM_IPV4_ADDR_LBN 32 17498 #define MC_TSA_IPV4_ITEM_IPV4_ADDR_WIDTH 32 17499 17500 17501 /***********************************/ 17502 /* MC_CMD_TSA_IPADDR 17503 * TSA operations relating to the monitoring and expiry of local IP addresses 17504 * discovered by the controller. These commands are sent from a TSA controller 17505 * to a TSA adapter. 17506 */ 17507 #define MC_CMD_TSA_IPADDR 0x65 17508 #undef MC_CMD_0x65_PRIVILEGE_CTG 17509 17510 #define MC_CMD_0x65_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 17511 17512 /* MC_CMD_TSA_IPADDR_IN msgrequest */ 17513 #define MC_CMD_TSA_IPADDR_IN_LEN 4 17514 /* Header containing information to identify which sub-operation of this 17515 * command to perform. The header contains a 16-bit op-code. Unused space in 17516 * this field is reserved for future expansion. 17517 */ 17518 #define MC_CMD_TSA_IPADDR_IN_OP_HDR_OFST 0 17519 #define MC_CMD_TSA_IPADDR_IN_OP_HDR_LEN 4 17520 #define MC_CMD_TSA_IPADDR_IN_OP_LBN 0 17521 #define MC_CMD_TSA_IPADDR_IN_OP_WIDTH 16 17522 /* enum: Request that the adapter verifies that the IPv4 addresses supplied are 17523 * still in use by the host by sending ARP probes to the host. The MC does not 17524 * wait for a response to the probes and sends an MCDI response to the 17525 * controller once the probes have been sent to the host. The response to the 17526 * probes (if there are any) will be forwarded to the controller using 17527 * MC_CMD_TSA_INFO alerts. 17528 */ 17529 #define MC_CMD_TSA_IPADDR_OP_VALIDATE_IPV4 0x1 17530 /* enum: Notify the adapter that one or more IPv4 addresses are no longer valid 17531 * for the host of the adapter. The adapter should remove the IPv4 addresses 17532 * from its local cache. 17533 */ 17534 #define MC_CMD_TSA_IPADDR_OP_REMOVE_IPV4 0x2 17535 17536 /* MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4 msgrequest */ 17537 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_LENMIN 16 17538 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_LENMAX 248 17539 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_LEN(num) (8+8*(num)) 17540 /* Header containing information to identify which sub-operation of this 17541 * command to perform. The header contains a 16-bit op-code. Unused space in 17542 * this field is reserved for future expansion. 17543 */ 17544 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_OP_HDR_OFST 0 17545 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_OP_HDR_LEN 4 17546 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_OP_LBN 0 17547 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_OP_WIDTH 16 17548 /* Number of IPv4 addresses to validate. */ 17549 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_NUM_ITEMS_OFST 4 17550 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_NUM_ITEMS_LEN 4 17551 /* The IPv4 addresses to validate, in struct MC_TSA_IPV4_ITEM format. */ 17552 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_OFST 8 17553 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LEN 8 17554 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LO_OFST 8 17555 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_HI_OFST 12 17556 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_MINNUM 1 17557 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_MAXNUM 30 17558 17559 /* MC_CMD_TSA_IPADDR_OUT_VALIDATE_IPV4 msgresponse */ 17560 #define MC_CMD_TSA_IPADDR_OUT_VALIDATE_IPV4_LEN 0 17561 17562 /* MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4 msgrequest */ 17563 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_LENMIN 16 17564 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_LENMAX 248 17565 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_LEN(num) (8+8*(num)) 17566 /* Header containing information to identify which sub-operation of this 17567 * command to perform. The header contains a 16-bit op-code. Unused space in 17568 * this field is reserved for future expansion. 17569 */ 17570 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_OP_HDR_OFST 0 17571 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_OP_HDR_LEN 4 17572 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_OP_LBN 0 17573 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_OP_WIDTH 16 17574 /* Number of IPv4 addresses to remove. */ 17575 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_NUM_ITEMS_OFST 4 17576 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_NUM_ITEMS_LEN 4 17577 /* The IPv4 addresses that have expired, in struct MC_TSA_IPV4_ITEM format. */ 17578 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_OFST 8 17579 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LEN 8 17580 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LO_OFST 8 17581 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_HI_OFST 12 17582 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_MINNUM 1 17583 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_MAXNUM 30 17584 17585 /* MC_CMD_TSA_IPADDR_OUT_REMOVE_IPV4 msgresponse */ 17586 #define MC_CMD_TSA_IPADDR_OUT_REMOVE_IPV4_LEN 0 17587 17588 17589 /***********************************/ 17590 /* MC_CMD_SECURE_NIC_INFO 17591 * Get secure NIC information. While many of the features reported by these 17592 * commands are related to TSA, they must be supported in firmware where TSA is 17593 * disabled. 17594 */ 17595 #define MC_CMD_SECURE_NIC_INFO 0x132 17596 #undef MC_CMD_0x132_PRIVILEGE_CTG 17597 17598 #define MC_CMD_0x132_PRIVILEGE_CTG SRIOV_CTG_GENERAL 17599 17600 /* MC_CMD_SECURE_NIC_INFO_IN msgrequest */ 17601 #define MC_CMD_SECURE_NIC_INFO_IN_LEN 4 17602 /* sub-operation code info */ 17603 #define MC_CMD_SECURE_NIC_INFO_IN_OP_HDR_OFST 0 17604 #define MC_CMD_SECURE_NIC_INFO_IN_OP_HDR_LEN 4 17605 #define MC_CMD_SECURE_NIC_INFO_IN_OP_LBN 0 17606 #define MC_CMD_SECURE_NIC_INFO_IN_OP_WIDTH 16 17607 /* enum: Get the status of various security settings, all signed along with a 17608 * challenge chosen by the host. 17609 */ 17610 #define MC_CMD_SECURE_NIC_INFO_OP_STATUS 0x0 17611 17612 /* MC_CMD_SECURE_NIC_INFO_IN_STATUS msgrequest */ 17613 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_LEN 24 17614 /* sub-operation code, must be MC_CMD_SECURE_NIC_INFO_OP_STATUS */ 17615 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_OP_HDR_OFST 0 17616 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_OP_HDR_LEN 4 17617 /* Type of key to be used to sign response. */ 17618 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_KEY_TYPE_OFST 4 17619 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_KEY_TYPE_LEN 4 17620 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_UNUSED 0x0 /* enum */ 17621 /* enum: Solarflare adapter authentication key, installed by Manftest. */ 17622 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_SF_ADAPTER_AUTH 0x1 17623 /* enum: TSA binding key, installed after adapter is bound to a TSA controller. 17624 * This is not supported in firmware which does not support TSA. 17625 */ 17626 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_TSA_BINDING 0x2 17627 /* enum: Customer adapter authentication key. Installed by the customer in the 17628 * field, but otherwise similar to the Solarflare adapter authentication key. 17629 */ 17630 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_CUSTOMER_ADAPTER_AUTH 0x3 17631 /* Random challenge generated by the host. */ 17632 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_CHALLENGE_OFST 8 17633 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_CHALLENGE_LEN 16 17634 17635 /* MC_CMD_SECURE_NIC_INFO_OUT_STATUS msgresponse */ 17636 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_LEN 420 17637 /* Length of the signature in MSG_SIGNATURE. */ 17638 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_MSG_SIGNATURE_LEN_OFST 0 17639 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_MSG_SIGNATURE_LEN_LEN 4 17640 /* Signature over the message, starting at MESSAGE_TYPE and continuing to the 17641 * end of the MCDI response, allowing the message format to be extended. The 17642 * signature uses ECDSA 384 encoding in ASN.1 format. It has variable length, 17643 * with a maximum of 384 bytes. 17644 */ 17645 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_MSG_SIGNATURE_OFST 4 17646 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_MSG_SIGNATURE_LEN 384 17647 /* Enum value indicating the type of response. This protects against chosen 17648 * message attacks. The enum values are random rather than sequential to make 17649 * it unlikely that values will be reused should other commands in a different 17650 * namespace need to create signed messages. 17651 */ 17652 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_MESSAGE_TYPE_OFST 388 17653 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_MESSAGE_TYPE_LEN 4 17654 /* enum: Message type value for the response to a 17655 * MC_CMD_SECURE_NIC_INFO_IN_STATUS message. 17656 */ 17657 #define MC_CMD_SECURE_NIC_INFO_STATUS 0xdb4 17658 /* The challenge provided by the host in the MC_CMD_SECURE_NIC_INFO_IN_STATUS 17659 * message 17660 */ 17661 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_CHALLENGE_OFST 392 17662 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_CHALLENGE_LEN 16 17663 /* The first 32 bits of XPM memory, which include security and flag bits, die 17664 * ID and chip ID revision. The meaning of these bits is defined in 17665 * mc/include/mc/xpm.h in the firmwaresrc repository. 17666 */ 17667 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_XPM_STATUS_BITS_OFST 408 17668 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_XPM_STATUS_BITS_LEN 4 17669 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_A_OFST 412 17670 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_A_LEN 2 17671 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_B_OFST 414 17672 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_B_LEN 2 17673 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_C_OFST 416 17674 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_C_LEN 2 17675 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_D_OFST 418 17676 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_D_LEN 2 17677 17678 17679 /***********************************/ 17680 /* MC_CMD_TSA_TEST 17681 * A simple ping-pong command just to test the adapter<>controller MCDI 17682 * communication channel. This command makes not changes to the TSA adapter's 17683 * internal state. It is used by the controller just to verify that the MCDI 17684 * communication channel is working fine. This command takes no additonal 17685 * parameters in request or response. 17686 */ 17687 #define MC_CMD_TSA_TEST 0x125 17688 #undef MC_CMD_0x125_PRIVILEGE_CTG 17689 17690 #define MC_CMD_0x125_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 17691 17692 /* MC_CMD_TSA_TEST_IN msgrequest */ 17693 #define MC_CMD_TSA_TEST_IN_LEN 0 17694 17695 /* MC_CMD_TSA_TEST_OUT msgresponse */ 17696 #define MC_CMD_TSA_TEST_OUT_LEN 0 17697 17698 17699 /***********************************/ 17700 /* MC_CMD_TSA_RULESET_OVERRIDE 17701 * Override TSA ruleset that is currently active on the adapter. This operation 17702 * does not modify the ruleset itself. This operation provides a mechanism to 17703 * apply an allow-all or deny-all operation on all packets, thereby completely 17704 * ignoring the rule-set configured on the adapter. The main purpose of this 17705 * operation is to provide a deterministic state to the TSA firewall during 17706 * rule-set transitions. 17707 */ 17708 #define MC_CMD_TSA_RULESET_OVERRIDE 0x12a 17709 #undef MC_CMD_0x12a_PRIVILEGE_CTG 17710 17711 #define MC_CMD_0x12a_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 17712 17713 /* MC_CMD_TSA_RULESET_OVERRIDE_IN msgrequest */ 17714 #define MC_CMD_TSA_RULESET_OVERRIDE_IN_LEN 4 17715 /* The override state to apply. */ 17716 #define MC_CMD_TSA_RULESET_OVERRIDE_IN_STATE_OFST 0 17717 #define MC_CMD_TSA_RULESET_OVERRIDE_IN_STATE_LEN 4 17718 /* enum: No override in place - the existing ruleset is in operation. */ 17719 #define MC_CMD_TSA_RULESET_OVERRIDE_NONE 0x0 17720 /* enum: Block all packets seen on all datapath channel except those packets 17721 * required for basic configuration of the TSA NIC such as ARPs and TSA- 17722 * communication traffic. Such exceptional traffic is handled differently 17723 * compared to TSA rulesets. 17724 */ 17725 #define MC_CMD_TSA_RULESET_OVERRIDE_BLOCK 0x1 17726 /* enum: Allow all packets through all datapath channel. The TSA adapter 17727 * behaves like a normal NIC without any firewalls. 17728 */ 17729 #define MC_CMD_TSA_RULESET_OVERRIDE_ALLOW 0x2 17730 17731 /* MC_CMD_TSA_RULESET_OVERRIDE_OUT msgresponse */ 17732 #define MC_CMD_TSA_RULESET_OVERRIDE_OUT_LEN 0 17733 17734 17735 /***********************************/ 17736 /* MC_CMD_TSAC_REQUEST 17737 * Generic command to send requests from a TSA controller to a TSA adapter. 17738 * Specific usage is determined by the TYPE field. 17739 */ 17740 #define MC_CMD_TSAC_REQUEST 0x12b 17741 #undef MC_CMD_0x12b_PRIVILEGE_CTG 17742 17743 #define MC_CMD_0x12b_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 17744 17745 /* MC_CMD_TSAC_REQUEST_IN msgrequest */ 17746 #define MC_CMD_TSAC_REQUEST_IN_LEN 4 17747 /* The type of request from the controller. */ 17748 #define MC_CMD_TSAC_REQUEST_IN_TYPE_OFST 0 17749 #define MC_CMD_TSAC_REQUEST_IN_TYPE_LEN 4 17750 /* enum: Request the adapter to resend localIP information from it's cache. The 17751 * command does not return any IP address information; IP addresses are sent as 17752 * TSA notifications as descibed in MC_CMD_TSA_INFO_IN_LOCAL_IP. 17753 */ 17754 #define MC_CMD_TSAC_REQUEST_LOCALIP 0x0 17755 17756 /* MC_CMD_TSAC_REQUEST_OUT msgresponse */ 17757 #define MC_CMD_TSAC_REQUEST_OUT_LEN 0 17758 17759 17760 /***********************************/ 17761 /* MC_CMD_SUC_VERSION 17762 * Get the version of the SUC 17763 */ 17764 #define MC_CMD_SUC_VERSION 0x134 17765 #undef MC_CMD_0x134_PRIVILEGE_CTG 17766 17767 #define MC_CMD_0x134_PRIVILEGE_CTG SRIOV_CTG_GENERAL 17768 17769 /* MC_CMD_SUC_VERSION_IN msgrequest */ 17770 #define MC_CMD_SUC_VERSION_IN_LEN 0 17771 17772 /* MC_CMD_SUC_VERSION_OUT msgresponse */ 17773 #define MC_CMD_SUC_VERSION_OUT_LEN 24 17774 /* The SUC firmware version as four numbers - a.b.c.d */ 17775 #define MC_CMD_SUC_VERSION_OUT_VERSION_OFST 0 17776 #define MC_CMD_SUC_VERSION_OUT_VERSION_LEN 4 17777 #define MC_CMD_SUC_VERSION_OUT_VERSION_NUM 4 17778 /* The date, in seconds since the Unix epoch, when the firmware image was 17779 * built. 17780 */ 17781 #define MC_CMD_SUC_VERSION_OUT_BUILD_DATE_OFST 16 17782 #define MC_CMD_SUC_VERSION_OUT_BUILD_DATE_LEN 4 17783 /* The ID of the SUC chip. This is specific to the platform but typically 17784 * indicates family, memory sizes etc. See SF-116728-SW for further details. 17785 */ 17786 #define MC_CMD_SUC_VERSION_OUT_CHIP_ID_OFST 20 17787 #define MC_CMD_SUC_VERSION_OUT_CHIP_ID_LEN 4 17788 17789 /* MC_CMD_SUC_BOOT_VERSION_IN msgrequest: Get the version of the SUC boot 17790 * loader. 17791 */ 17792 #define MC_CMD_SUC_BOOT_VERSION_IN_LEN 4 17793 #define MC_CMD_SUC_BOOT_VERSION_IN_MAGIC_OFST 0 17794 #define MC_CMD_SUC_BOOT_VERSION_IN_MAGIC_LEN 4 17795 /* enum: Requests the SUC boot version. */ 17796 #define MC_CMD_SUC_VERSION_GET_BOOT_VERSION 0xb007700b 17797 17798 /* MC_CMD_SUC_BOOT_VERSION_OUT msgresponse */ 17799 #define MC_CMD_SUC_BOOT_VERSION_OUT_LEN 4 17800 /* The SUC boot version */ 17801 #define MC_CMD_SUC_BOOT_VERSION_OUT_VERSION_OFST 0 17802 #define MC_CMD_SUC_BOOT_VERSION_OUT_VERSION_LEN 4 17803 17804 17805 /***********************************/ 17806 /* MC_CMD_SUC_MANFTEST 17807 * Operations to support manftest on SUC based systems. 17808 */ 17809 #define MC_CMD_SUC_MANFTEST 0x135 17810 #undef MC_CMD_0x135_PRIVILEGE_CTG 17811 17812 #define MC_CMD_0x135_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND 17813 17814 /* MC_CMD_SUC_MANFTEST_IN msgrequest */ 17815 #define MC_CMD_SUC_MANFTEST_IN_LEN 4 17816 /* The manftest operation to be performed. */ 17817 #define MC_CMD_SUC_MANFTEST_IN_OP_OFST 0 17818 #define MC_CMD_SUC_MANFTEST_IN_OP_LEN 4 17819 /* enum: Read serial number and use count. */ 17820 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ 0x0 17821 /* enum: Update use count on wearout adapter. */ 17822 #define MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE 0x1 17823 /* enum: Start an ADC calibration. */ 17824 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START 0x2 17825 /* enum: Read the status of an ADC calibration. */ 17826 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS 0x3 17827 /* enum: Read the results of an ADC calibration. */ 17828 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT 0x4 17829 /* enum: Read the PCIe configuration. */ 17830 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ 0x5 17831 /* enum: Write the PCIe configuration. */ 17832 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE 0x6 17833 /* enum: Write FRU information to SUC. The FRU information is taken from the 17834 * FRU_INFORMATION partition. Attempts to write to read-only FRUs are rejected. 17835 */ 17836 #define MC_CMD_SUC_MANFTEST_FRU_WRITE 0x7 17837 17838 /* MC_CMD_SUC_MANFTEST_OUT msgresponse */ 17839 #define MC_CMD_SUC_MANFTEST_OUT_LEN 0 17840 17841 /* MC_CMD_SUC_MANFTEST_WEAROUT_READ_IN msgrequest */ 17842 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ_IN_LEN 4 17843 /* The manftest operation to be performed. This must be 17844 * MC_CMD_SUC_MANFTEST_WEAROUT_READ. 17845 */ 17846 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ_IN_OP_OFST 0 17847 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ_IN_OP_LEN 4 17848 17849 /* MC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT msgresponse */ 17850 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT_LEN 20 17851 /* The serial number of the wearout adapter, see SF-112717-PR for format. */ 17852 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT_SERIAL_NUMBER_OFST 0 17853 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT_SERIAL_NUMBER_LEN 16 17854 /* The use count of the wearout adapter. */ 17855 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT_USE_COUNT_OFST 16 17856 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT_USE_COUNT_LEN 4 17857 17858 /* MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_IN msgrequest */ 17859 #define MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_IN_LEN 4 17860 /* The manftest operation to be performed. This must be 17861 * MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE. 17862 */ 17863 #define MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_IN_OP_OFST 0 17864 #define MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_IN_OP_LEN 4 17865 17866 /* MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_OUT msgresponse */ 17867 #define MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_OUT_LEN 0 17868 17869 /* MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_IN msgrequest */ 17870 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_IN_LEN 4 17871 /* The manftest operation to be performed. This must be 17872 * MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START. 17873 */ 17874 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_IN_OP_OFST 0 17875 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_IN_OP_LEN 4 17876 17877 /* MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_OUT msgresponse */ 17878 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_OUT_LEN 0 17879 17880 /* MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_IN msgrequest */ 17881 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_IN_LEN 4 17882 /* The manftest operation to be performed. This must be 17883 * MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS. 17884 */ 17885 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_IN_OP_OFST 0 17886 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_IN_OP_LEN 4 17887 17888 /* MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT msgresponse */ 17889 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_LEN 4 17890 /* The combined status of the calibration operation. */ 17891 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_FLAGS_OFST 0 17892 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_FLAGS_LEN 4 17893 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_CALIBRATING_LBN 0 17894 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_CALIBRATING_WIDTH 1 17895 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_FAILED_LBN 1 17896 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_FAILED_WIDTH 1 17897 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_RESULT_LBN 2 17898 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_RESULT_WIDTH 4 17899 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_INDEX_LBN 6 17900 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_INDEX_WIDTH 2 17901 17902 /* MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_IN msgrequest */ 17903 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_IN_LEN 4 17904 /* The manftest operation to be performed. This must be 17905 * MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT. 17906 */ 17907 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_IN_OP_OFST 0 17908 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_IN_OP_LEN 4 17909 17910 /* MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_OUT msgresponse */ 17911 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_OUT_LEN 12 17912 /* The set of calibration results. */ 17913 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_OUT_VALUE_OFST 0 17914 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_OUT_VALUE_LEN 4 17915 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_OUT_VALUE_NUM 3 17916 17917 /* MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_IN msgrequest */ 17918 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_IN_LEN 4 17919 /* The manftest operation to be performed. This must be 17920 * MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ. 17921 */ 17922 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_IN_OP_OFST 0 17923 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_IN_OP_LEN 4 17924 17925 /* MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_OUT msgresponse */ 17926 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_OUT_LEN 4 17927 /* The PCIe vendor ID. */ 17928 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_OUT_VENDOR_ID_OFST 0 17929 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_OUT_VENDOR_ID_LEN 2 17930 /* The PCIe device ID. */ 17931 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_OUT_DEVICE_ID_OFST 2 17932 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_OUT_DEVICE_ID_LEN 2 17933 17934 /* MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN msgrequest */ 17935 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_LEN 8 17936 /* The manftest operation to be performed. This must be 17937 * MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE. 17938 */ 17939 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_OP_OFST 0 17940 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_OP_LEN 4 17941 /* The PCIe vendor ID. */ 17942 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_VENDOR_ID_OFST 4 17943 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_VENDOR_ID_LEN 2 17944 /* The PCIe device ID. */ 17945 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_DEVICE_ID_OFST 6 17946 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_DEVICE_ID_LEN 2 17947 17948 /* MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_OUT msgresponse */ 17949 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_OUT_LEN 0 17950 17951 /* MC_CMD_SUC_MANFTEST_FRU_WRITE_IN msgrequest */ 17952 #define MC_CMD_SUC_MANFTEST_FRU_WRITE_IN_LEN 4 17953 /* The manftest operation to be performed. This must be 17954 * MC_CMD_SUC_MANFTEST_FRU_WRITE 17955 */ 17956 #define MC_CMD_SUC_MANFTEST_FRU_WRITE_IN_OP_OFST 0 17957 #define MC_CMD_SUC_MANFTEST_FRU_WRITE_IN_OP_LEN 4 17958 17959 /* MC_CMD_SUC_MANFTEST_FRU_WRITE_OUT msgresponse */ 17960 #define MC_CMD_SUC_MANFTEST_FRU_WRITE_OUT_LEN 0 17961 17962 17963 /***********************************/ 17964 /* MC_CMD_GET_CERTIFICATE 17965 * Request a certificate. 17966 */ 17967 #define MC_CMD_GET_CERTIFICATE 0x12c 17968 #undef MC_CMD_0x12c_PRIVILEGE_CTG 17969 17970 #define MC_CMD_0x12c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 17971 17972 /* MC_CMD_GET_CERTIFICATE_IN msgrequest */ 17973 #define MC_CMD_GET_CERTIFICATE_IN_LEN 8 17974 /* Type of the certificate to be retrieved. */ 17975 #define MC_CMD_GET_CERTIFICATE_IN_TYPE_OFST 0 17976 #define MC_CMD_GET_CERTIFICATE_IN_TYPE_LEN 4 17977 #define MC_CMD_GET_CERTIFICATE_IN_UNUSED 0x0 /* enum */ 17978 #define MC_CMD_GET_CERTIFICATE_IN_AAC 0x1 /* enum */ 17979 /* enum: Adapter Authentication Certificate (AAC). The AAC is unique to each 17980 * adapter and is used to verify its authenticity. It is installed by Manftest. 17981 */ 17982 #define MC_CMD_GET_CERTIFICATE_IN_ADAPTER_AUTH 0x1 17983 #define MC_CMD_GET_CERTIFICATE_IN_AASC 0x2 /* enum */ 17984 /* enum: Adapter Authentication Signing Certificate (AASC). The AASC is shared 17985 * by a group of adapters (typically a purchase order) and is used to verify 17986 * the validity of AAC along with the SF root certificate. It is installed by 17987 * Manftest. 17988 */ 17989 #define MC_CMD_GET_CERTIFICATE_IN_ADAPTER_AUTH_SIGNING 0x2 17990 #define MC_CMD_GET_CERTIFICATE_IN_CUSTOMER_AAC 0x3 /* enum */ 17991 /* enum: Customer Adapter Authentication Certificate. The Customer AAC is 17992 * unique to each adapter and is used to verify its authenticity in cases where 17993 * either the AAC is not installed or a customer desires to use their own 17994 * certificate chain. It is installed by the customer. 17995 */ 17996 #define MC_CMD_GET_CERTIFICATE_IN_CUSTOMER_ADAPTER_AUTH 0x3 17997 #define MC_CMD_GET_CERTIFICATE_IN_CUSTOMER_AASC 0x4 /* enum */ 17998 /* enum: Customer Adapter Authentication Certificate. The Customer AASC is 17999 * shared by a group of adapters and is used to verify the validity of the 18000 * Customer AAC along with the customers root certificate. It is installed by 18001 * the customer. 18002 */ 18003 #define MC_CMD_GET_CERTIFICATE_IN_CUSTOMER_ADAPTER_AUTH_SIGNING 0x4 18004 /* Offset, measured in bytes, relative to the start of the certificate data 18005 * from which the certificate is to be retrieved. 18006 */ 18007 #define MC_CMD_GET_CERTIFICATE_IN_OFFSET_OFST 4 18008 #define MC_CMD_GET_CERTIFICATE_IN_OFFSET_LEN 4 18009 18010 /* MC_CMD_GET_CERTIFICATE_OUT msgresponse */ 18011 #define MC_CMD_GET_CERTIFICATE_OUT_LENMIN 13 18012 #define MC_CMD_GET_CERTIFICATE_OUT_LENMAX 252 18013 #define MC_CMD_GET_CERTIFICATE_OUT_LEN(num) (12+1*(num)) 18014 /* Type of the certificate. */ 18015 #define MC_CMD_GET_CERTIFICATE_OUT_TYPE_OFST 0 18016 #define MC_CMD_GET_CERTIFICATE_OUT_TYPE_LEN 4 18017 /* Enum values, see field(s): */ 18018 /* MC_CMD_GET_CERTIFICATE_IN/TYPE */ 18019 /* Offset, measured in bytes, relative to the start of the certificate data 18020 * from which data in this message starts. 18021 */ 18022 #define MC_CMD_GET_CERTIFICATE_OUT_OFFSET_OFST 4 18023 #define MC_CMD_GET_CERTIFICATE_OUT_OFFSET_LEN 4 18024 /* Total length of the certificate data. */ 18025 #define MC_CMD_GET_CERTIFICATE_OUT_TOTAL_LENGTH_OFST 8 18026 #define MC_CMD_GET_CERTIFICATE_OUT_TOTAL_LENGTH_LEN 4 18027 /* The certificate data. */ 18028 #define MC_CMD_GET_CERTIFICATE_OUT_DATA_OFST 12 18029 #define MC_CMD_GET_CERTIFICATE_OUT_DATA_LEN 1 18030 #define MC_CMD_GET_CERTIFICATE_OUT_DATA_MINNUM 1 18031 #define MC_CMD_GET_CERTIFICATE_OUT_DATA_MAXNUM 240 18032 18033 18034 /***********************************/ 18035 /* MC_CMD_GET_NIC_GLOBAL 18036 * Get a global value which applies to all PCI functions 18037 */ 18038 #define MC_CMD_GET_NIC_GLOBAL 0x12d 18039 #undef MC_CMD_0x12d_PRIVILEGE_CTG 18040 18041 #define MC_CMD_0x12d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 18042 18043 /* MC_CMD_GET_NIC_GLOBAL_IN msgrequest */ 18044 #define MC_CMD_GET_NIC_GLOBAL_IN_LEN 4 18045 /* Key to request value for, see enum values in MC_CMD_SET_NIC_GLOBAL. If the 18046 * given key is unknown to the current firmware, the call will fail with 18047 * ENOENT. 18048 */ 18049 #define MC_CMD_GET_NIC_GLOBAL_IN_KEY_OFST 0 18050 #define MC_CMD_GET_NIC_GLOBAL_IN_KEY_LEN 4 18051 18052 /* MC_CMD_GET_NIC_GLOBAL_OUT msgresponse */ 18053 #define MC_CMD_GET_NIC_GLOBAL_OUT_LEN 4 18054 /* Value of requested key, see key descriptions below. */ 18055 #define MC_CMD_GET_NIC_GLOBAL_OUT_VALUE_OFST 0 18056 #define MC_CMD_GET_NIC_GLOBAL_OUT_VALUE_LEN 4 18057 18058 18059 /***********************************/ 18060 /* MC_CMD_SET_NIC_GLOBAL 18061 * Set a global value which applies to all PCI functions. Most global values 18062 * can only be changed under specific conditions, and this call will return an 18063 * appropriate error otherwise (see key descriptions). 18064 */ 18065 #define MC_CMD_SET_NIC_GLOBAL 0x12e 18066 #undef MC_CMD_0x12e_PRIVILEGE_CTG 18067 18068 #define MC_CMD_0x12e_PRIVILEGE_CTG SRIOV_CTG_ADMIN 18069 18070 /* MC_CMD_SET_NIC_GLOBAL_IN msgrequest */ 18071 #define MC_CMD_SET_NIC_GLOBAL_IN_LEN 8 18072 /* Key to change value of. Firmware will return ENOENT for keys it doesn't know 18073 * about. 18074 */ 18075 #define MC_CMD_SET_NIC_GLOBAL_IN_KEY_OFST 0 18076 #define MC_CMD_SET_NIC_GLOBAL_IN_KEY_LEN 4 18077 /* enum: Request switching the datapath firmware sub-variant. Currently only 18078 * useful when running the DPDK f/w variant. See key values below, and the DPDK 18079 * section of the EF10 Driver Writers Guide. Note that any driver attaching 18080 * with the SUBVARIANT_AWARE flag cleared is implicitly considered as a request 18081 * to switch back to the default sub-variant, and will thus reset this value. 18082 * If a sub-variant switch happens, all other PCI functions will get their 18083 * resources reset (they will see an MC reboot). 18084 */ 18085 #define MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT 0x1 18086 /* New value to set, see key descriptions above. */ 18087 #define MC_CMD_SET_NIC_GLOBAL_IN_VALUE_OFST 4 18088 #define MC_CMD_SET_NIC_GLOBAL_IN_VALUE_LEN 4 18089 /* enum: Only if KEY = FIRMWARE_SUBVARIANT. Default sub-variant with support 18090 * for maximum features for the current f/w variant. A request from a 18091 * privileged function to set this particular value will always succeed. 18092 */ 18093 #define MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT 0x0 18094 /* enum: Only if KEY = FIRMWARE_SUBVARIANT. Increases packet rate at the cost 18095 * of not supporting any TX checksum offloads. Only supported when running some 18096 * f/w variants, others will return ENOTSUP (as reported by the homonymous bit 18097 * in MC_CMD_GET_CAPABILITIES_V2). Can only be set when no other drivers are 18098 * attached, and the calling driver must have no resources allocated. See the 18099 * DPDK section of the EF10 Driver Writers Guide for a more detailed 18100 * description with possible error codes. 18101 */ 18102 #define MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM 0x1 18103 18104 18105 /***********************************/ 18106 /* MC_CMD_LTSSM_TRACE_POLL 18107 * Medford2 hardware has support for logging all LTSSM state transitions to a 18108 * hardware buffer. When built with WITH_LTSSM_TRACE=1, the firmware will 18109 * periodially dump the contents of this hardware buffer to an internal 18110 * firmware buffer for later extraction. 18111 */ 18112 #define MC_CMD_LTSSM_TRACE_POLL 0x12f 18113 #undef MC_CMD_0x12f_PRIVILEGE_CTG 18114 18115 #define MC_CMD_0x12f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 18116 18117 /* MC_CMD_LTSSM_TRACE_POLL_IN msgrequest: Read transitions from the firmware 18118 * internal buffer. 18119 */ 18120 #define MC_CMD_LTSSM_TRACE_POLL_IN_LEN 4 18121 /* The maximum number of row that the caller can accept. The format of each row 18122 * is defined in MC_CMD_LTSSM_TRACE_POLL_OUT. 18123 */ 18124 #define MC_CMD_LTSSM_TRACE_POLL_IN_MAX_ROW_COUNT_OFST 0 18125 #define MC_CMD_LTSSM_TRACE_POLL_IN_MAX_ROW_COUNT_LEN 4 18126 18127 /* MC_CMD_LTSSM_TRACE_POLL_OUT msgresponse */ 18128 #define MC_CMD_LTSSM_TRACE_POLL_OUT_LENMIN 16 18129 #define MC_CMD_LTSSM_TRACE_POLL_OUT_LENMAX 248 18130 #define MC_CMD_LTSSM_TRACE_POLL_OUT_LEN(num) (8+8*(num)) 18131 #define MC_CMD_LTSSM_TRACE_POLL_OUT_FLAGS_OFST 0 18132 #define MC_CMD_LTSSM_TRACE_POLL_OUT_FLAGS_LEN 4 18133 #define MC_CMD_LTSSM_TRACE_POLL_OUT_HW_BUFFER_OVERFLOW_LBN 0 18134 #define MC_CMD_LTSSM_TRACE_POLL_OUT_HW_BUFFER_OVERFLOW_WIDTH 1 18135 #define MC_CMD_LTSSM_TRACE_POLL_OUT_FW_BUFFER_OVERFLOW_LBN 1 18136 #define MC_CMD_LTSSM_TRACE_POLL_OUT_FW_BUFFER_OVERFLOW_WIDTH 1 18137 #define MC_CMD_LTSSM_TRACE_POLL_OUT_CONTINUES_LBN 31 18138 #define MC_CMD_LTSSM_TRACE_POLL_OUT_CONTINUES_WIDTH 1 18139 /* The number of rows present in this response. */ 18140 #define MC_CMD_LTSSM_TRACE_POLL_OUT_ROW_COUNT_OFST 4 18141 #define MC_CMD_LTSSM_TRACE_POLL_OUT_ROW_COUNT_LEN 4 18142 #define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_OFST 8 18143 #define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_LEN 8 18144 #define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_LO_OFST 8 18145 #define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_HI_OFST 12 18146 #define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_MINNUM 0 18147 #define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_MAXNUM 30 18148 #define MC_CMD_LTSSM_TRACE_POLL_OUT_LTSSM_STATE_LBN 0 18149 #define MC_CMD_LTSSM_TRACE_POLL_OUT_LTSSM_STATE_WIDTH 6 18150 #define MC_CMD_LTSSM_TRACE_POLL_OUT_RDLH_LINK_UP_LBN 6 18151 #define MC_CMD_LTSSM_TRACE_POLL_OUT_RDLH_LINK_UP_WIDTH 1 18152 #define MC_CMD_LTSSM_TRACE_POLL_OUT_WAKE_N_LBN 7 18153 #define MC_CMD_LTSSM_TRACE_POLL_OUT_WAKE_N_WIDTH 1 18154 #define MC_CMD_LTSSM_TRACE_POLL_OUT_TIMESTAMP_PS_LBN 8 18155 #define MC_CMD_LTSSM_TRACE_POLL_OUT_TIMESTAMP_PS_WIDTH 24 18156 /* The time of the LTSSM transition. Times are reported as fractional 18157 * microseconds since MC boot (wrapping at 2^32us). The fractional part is 18158 * reported in picoseconds. 0 <= TIMESTAMP_PS < 1000000 timestamp in seconds = 18159 * ((TIMESTAMP_US + TIMESTAMP_PS / 1000000) / 1000000) 18160 */ 18161 #define MC_CMD_LTSSM_TRACE_POLL_OUT_TIMESTAMP_US_OFST 12 18162 #define MC_CMD_LTSSM_TRACE_POLL_OUT_TIMESTAMP_US_LEN 4 18163 18164 #endif /* _SIENA_MC_DRIVER_PCOL_H */ 18165