1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018 Rubicon Communications, LLC (Netgate) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * Marvell Xenon SDHCI controller driver. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/lock.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/resource.h> 43 #include <sys/rman.h> 44 #include <sys/sysctl.h> 45 #include <sys/taskqueue.h> 46 47 #include <machine/bus.h> 48 #include <machine/resource.h> 49 50 #include <dev/extres/regulator/regulator.h> 51 #include <dev/fdt/fdt_common.h> 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 55 #include <dev/mmc/bridge.h> 56 #include <dev/mmc/mmc_fdt_helpers.h> 57 #include <dev/mmc/mmcbrvar.h> 58 #include <dev/mmc/mmcreg.h> 59 60 #include <dev/sdhci/sdhci.h> 61 #include <dev/sdhci/sdhci_fdt_gpio.h> 62 #include <dev/sdhci/sdhci_xenon.h> 63 64 #include "mmcbr_if.h" 65 #include "sdhci_if.h" 66 67 #include "opt_mmccam.h" 68 #include "opt_soc.h" 69 70 #define MAX_SLOTS 6 71 72 static struct ofw_compat_data compat_data[] = { 73 { "marvell,armada-3700-sdhci", 1 }, 74 #ifdef SOC_MARVELL_8K 75 { "marvell,armada-cp110-sdhci", 1 }, 76 { "marvell,armada-ap806-sdhci", 1 }, 77 #endif 78 { NULL, 0 } 79 }; 80 81 struct sdhci_xenon_softc { 82 device_t dev; /* Controller device */ 83 int slot_id; /* Controller ID */ 84 phandle_t node; /* FDT node */ 85 uint32_t quirks; /* Chip specific quirks */ 86 uint32_t caps; /* If we override SDHCI_CAPABILITIES */ 87 uint32_t max_clk; /* Max possible freq */ 88 struct resource *irq_res; /* IRQ resource */ 89 void *intrhand; /* Interrupt handle */ 90 struct sdhci_fdt_gpio *gpio; /* GPIO pins for CD detection. */ 91 92 struct sdhci_slot *slot; /* SDHCI internal data */ 93 struct resource *mem_res; /* Memory resource */ 94 95 uint8_t znr; /* PHY ZNR */ 96 uint8_t zpr; /* PHY ZPR */ 97 bool no_18v; /* No 1.8V support */ 98 bool slow_mode; /* PHY slow mode */ 99 100 struct mmc_fdt_helper mmc_helper; /* MMC helper for parsing FDT */ 101 }; 102 103 static uint8_t 104 sdhci_xenon_read_1(device_t dev, struct sdhci_slot *slot __unused, 105 bus_size_t off) 106 { 107 struct sdhci_xenon_softc *sc = device_get_softc(dev); 108 109 return (bus_read_1(sc->mem_res, off)); 110 } 111 112 static void 113 sdhci_xenon_write_1(device_t dev, struct sdhci_slot *slot __unused, 114 bus_size_t off, uint8_t val) 115 { 116 struct sdhci_xenon_softc *sc = device_get_softc(dev); 117 118 bus_write_1(sc->mem_res, off, val); 119 } 120 121 static uint16_t 122 sdhci_xenon_read_2(device_t dev, struct sdhci_slot *slot __unused, 123 bus_size_t off) 124 { 125 struct sdhci_xenon_softc *sc = device_get_softc(dev); 126 127 return (bus_read_2(sc->mem_res, off)); 128 } 129 130 static void 131 sdhci_xenon_write_2(device_t dev, struct sdhci_slot *slot __unused, 132 bus_size_t off, uint16_t val) 133 { 134 struct sdhci_xenon_softc *sc = device_get_softc(dev); 135 136 bus_write_2(sc->mem_res, off, val); 137 } 138 139 static uint32_t 140 sdhci_xenon_read_4(device_t dev, struct sdhci_slot *slot __unused, 141 bus_size_t off) 142 { 143 struct sdhci_xenon_softc *sc = device_get_softc(dev); 144 145 return bus_read_4(sc->mem_res, off); 146 } 147 148 static void 149 sdhci_xenon_write_4(device_t dev, struct sdhci_slot *slot __unused, 150 bus_size_t off, uint32_t val) 151 { 152 struct sdhci_xenon_softc *sc = device_get_softc(dev); 153 154 bus_write_4(sc->mem_res, off, val); 155 } 156 157 static void 158 sdhci_xenon_read_multi_4(device_t dev, struct sdhci_slot *slot __unused, 159 bus_size_t off, uint32_t *data, bus_size_t count) 160 { 161 struct sdhci_xenon_softc *sc = device_get_softc(dev); 162 163 bus_read_multi_4(sc->mem_res, off, data, count); 164 } 165 166 static void 167 sdhci_xenon_write_multi_4(device_t dev, struct sdhci_slot *slot __unused, 168 bus_size_t off, uint32_t *data, bus_size_t count) 169 { 170 struct sdhci_xenon_softc *sc = device_get_softc(dev); 171 172 bus_write_multi_4(sc->mem_res, off, data, count); 173 } 174 175 static void 176 sdhci_xenon_intr(void *arg) 177 { 178 struct sdhci_xenon_softc *sc = (struct sdhci_xenon_softc *)arg; 179 180 sdhci_generic_intr(sc->slot); 181 } 182 183 static int 184 sdhci_xenon_get_ro(device_t bus, device_t dev) 185 { 186 struct sdhci_xenon_softc *sc = device_get_softc(bus); 187 188 return (sdhci_generic_get_ro(bus, dev) ^ 189 (sc->mmc_helper.props & MMC_PROP_WP_INVERTED)); 190 } 191 192 static bool 193 sdhci_xenon_get_card_present(device_t dev, struct sdhci_slot *slot) 194 { 195 struct sdhci_xenon_softc *sc = device_get_softc(dev); 196 197 return (sdhci_fdt_gpio_get_present(sc->gpio)); 198 } 199 200 static int 201 sdhci_xenon_phy_init(device_t brdev, struct mmc_ios *ios) 202 { 203 int i; 204 struct sdhci_xenon_softc *sc; 205 uint32_t reg; 206 207 sc = device_get_softc(brdev); 208 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST); 209 reg |= XENON_SAMPL_INV_QSP_PHASE_SELECT; 210 switch (ios->timing) { 211 case bus_timing_normal: 212 case bus_timing_hs: 213 case bus_timing_uhs_sdr12: 214 case bus_timing_uhs_sdr25: 215 case bus_timing_uhs_sdr50: 216 reg |= XENON_TIMING_ADJUST_SLOW_MODE; 217 break; 218 default: 219 reg &= ~XENON_TIMING_ADJUST_SLOW_MODE; 220 } 221 if (sc->slow_mode) 222 reg |= XENON_TIMING_ADJUST_SLOW_MODE; 223 bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg); 224 225 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST); 226 reg |= XENON_PHY_INITIALIZATION; 227 bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg); 228 229 /* Wait for the eMMC PHY init. */ 230 for (i = 100; i > 0; i--) { 231 DELAY(100); 232 233 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST); 234 if ((reg & XENON_PHY_INITIALIZATION) == 0) 235 break; 236 } 237 238 if (i == 0) { 239 device_printf(brdev, "eMMC PHY failed to initialize\n"); 240 return (ETIMEDOUT); 241 } 242 243 return (0); 244 } 245 246 static int 247 sdhci_xenon_phy_set(device_t brdev, struct mmc_ios *ios) 248 { 249 struct sdhci_xenon_softc *sc; 250 uint32_t reg; 251 252 sc = device_get_softc(brdev); 253 /* Setup pad, set bit[28] and bits[26:24] */ 254 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL); 255 reg |= (XENON_FC_DQ_RECEN | XENON_FC_CMD_RECEN | 256 XENON_FC_QSP_RECEN | XENON_OEN_QSN); 257 /* All FC_XX_RECEIVCE should be set as CMOS Type */ 258 reg |= XENON_FC_ALL_CMOS_RECEIVER; 259 bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL, reg); 260 261 /* Set CMD and DQ Pull Up */ 262 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1); 263 reg |= (XENON_EMMC_FC_CMD_PU | XENON_EMMC_FC_DQ_PU); 264 reg &= ~(XENON_EMMC_FC_CMD_PD | XENON_EMMC_FC_DQ_PD); 265 bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1, reg); 266 267 if (ios->timing == bus_timing_normal) 268 return (sdhci_xenon_phy_init(brdev, ios)); 269 270 /* Clear SDIO mode, no SDIO support for now. */ 271 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST); 272 reg &= ~XENON_TIMING_ADJUST_SDIO_MODE; 273 bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg); 274 275 /* 276 * Set preferred ZNR and ZPR value. 277 * The ZNR and ZPR value vary between different boards. 278 * Define them both in the DTS for the board! 279 */ 280 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL2); 281 reg &= ~((XENON_ZNR_MASK << XENON_ZNR_SHIFT) | XENON_ZPR_MASK); 282 reg |= ((sc->znr << XENON_ZNR_SHIFT) | sc->zpr); 283 bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL2, reg); 284 285 /* Disable the SD clock to set EMMC_PHY_FUNC_CONTROL. */ 286 reg = bus_read_4(sc->mem_res, SDHCI_CLOCK_CONTROL); 287 reg &= ~SDHCI_CLOCK_CARD_EN; 288 bus_write_4(sc->mem_res, SDHCI_CLOCK_CONTROL, reg); 289 290 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_FUNC_CONTROL); 291 switch (ios->timing) { 292 case bus_timing_mmc_hs400: 293 reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | 294 XENON_CMD_DDR_MODE; 295 reg &= ~XENON_DQ_ASYNC_MODE; 296 break; 297 case bus_timing_uhs_ddr50: 298 case bus_timing_mmc_ddr52: 299 reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | 300 XENON_CMD_DDR_MODE | XENON_DQ_ASYNC_MODE; 301 break; 302 default: 303 reg &= ~((XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | 304 XENON_CMD_DDR_MODE); 305 reg |= XENON_DQ_ASYNC_MODE; 306 } 307 bus_write_4(sc->mem_res, XENON_EMMC_PHY_FUNC_CONTROL, reg); 308 309 /* Enable SD clock. */ 310 reg = bus_read_4(sc->mem_res, SDHCI_CLOCK_CONTROL); 311 reg |= SDHCI_CLOCK_CARD_EN; 312 bus_write_4(sc->mem_res, SDHCI_CLOCK_CONTROL, reg); 313 314 if (ios->timing == bus_timing_mmc_hs400) 315 bus_write_4(sc->mem_res, XENON_EMMC_PHY_LOGIC_TIMING_ADJUST, 316 XENON_LOGIC_TIMING_VALUE); 317 else { 318 /* Disable both SDHC Data Strobe and Enhanced Strobe. */ 319 reg = bus_read_4(sc->mem_res, XENON_SLOT_EMMC_CTRL); 320 reg &= ~(XENON_ENABLE_DATA_STROBE | XENON_ENABLE_RESP_STROBE); 321 bus_write_4(sc->mem_res, XENON_SLOT_EMMC_CTRL, reg); 322 323 /* Clear Strobe line Pull down or Pull up. */ 324 reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1); 325 reg &= ~(XENON_EMMC_FC_QSP_PD | XENON_EMMC_FC_QSP_PU); 326 bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1, reg); 327 } 328 329 return (sdhci_xenon_phy_init(brdev, ios)); 330 } 331 332 static int 333 sdhci_xenon_update_ios(device_t brdev, device_t reqdev) 334 { 335 int err; 336 struct sdhci_xenon_softc *sc; 337 struct mmc_ios *ios; 338 struct sdhci_slot *slot; 339 uint32_t reg; 340 341 err = sdhci_generic_update_ios(brdev, reqdev); 342 if (err != 0) 343 return (err); 344 345 sc = device_get_softc(brdev); 346 slot = device_get_ivars(reqdev); 347 ios = &slot->host.ios; 348 349 switch (ios->power_mode) { 350 case power_on: 351 break; 352 case power_off: 353 if (bootverbose) 354 device_printf(sc->dev, "Powering down sd/mmc\n"); 355 356 if (sc->mmc_helper.vmmc_supply) 357 regulator_disable(sc->mmc_helper.vmmc_supply); 358 if (sc->mmc_helper.vqmmc_supply) 359 regulator_disable(sc->mmc_helper.vqmmc_supply); 360 break; 361 case power_up: 362 if (bootverbose) 363 device_printf(sc->dev, "Powering up sd/mmc\n"); 364 365 if (sc->mmc_helper.vmmc_supply) 366 regulator_enable(sc->mmc_helper.vmmc_supply); 367 if (sc->mmc_helper.vqmmc_supply) 368 regulator_enable(sc->mmc_helper.vqmmc_supply); 369 break; 370 }; 371 372 /* Update the PHY settings. */ 373 if (ios->clock != 0) 374 sdhci_xenon_phy_set(brdev, ios); 375 376 if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) { 377 /* Enable SDCLK_IDLEOFF. */ 378 reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL); 379 reg |= 1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sc->slot_id); 380 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg); 381 } 382 383 return (0); 384 } 385 386 static int 387 sdhci_xenon_switch_vccq(device_t brdev, device_t reqdev) 388 { 389 struct sdhci_xenon_softc *sc; 390 struct sdhci_slot *slot; 391 uint16_t hostctrl2; 392 int uvolt, err; 393 394 slot = device_get_ivars(reqdev); 395 396 if (slot->version < SDHCI_SPEC_300) 397 return (0); 398 399 sc = device_get_softc(brdev); 400 401 if (sc->mmc_helper.vqmmc_supply == NULL) 402 return EOPNOTSUPP; 403 404 err = 0; 405 406 hostctrl2 = bus_read_2(sc->mem_res, SDHCI_HOST_CONTROL2); 407 switch (slot->host.ios.vccq) { 408 case vccq_330: 409 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 410 return (0); 411 hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE; 412 bus_write_2(sc->mem_res, SDHCI_HOST_CONTROL2, hostctrl2); 413 414 uvolt = 3300000; 415 err = regulator_set_voltage(sc->mmc_helper.vqmmc_supply, 416 uvolt, uvolt); 417 if (err != 0) { 418 device_printf(sc->dev, 419 "Cannot set vqmmc to %d<->%d\n", 420 uvolt, 421 uvolt); 422 return (err); 423 } 424 425 /* 426 * According to the 'SD Host Controller Simplified 427 * Specification 4.20 the host driver should take more 428 * than 5ms for stable time of host voltage regulator 429 * from changing 1.8V Signaling Enable. 430 */ 431 DELAY(5000); 432 hostctrl2 = bus_read_2(sc->mem_res, SDHCI_HOST_CONTROL2); 433 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 434 return (0); 435 return EAGAIN; 436 case vccq_180: 437 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) { 438 return EINVAL; 439 } 440 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 441 return (0); 442 hostctrl2 |= SDHCI_CTRL2_S18_ENABLE; 443 bus_write_2(sc->mem_res, SDHCI_HOST_CONTROL2, hostctrl2); 444 445 uvolt = 1800000; 446 err = regulator_set_voltage(sc->mmc_helper.vqmmc_supply, 447 uvolt, uvolt); 448 if (err != 0) { 449 device_printf(sc->dev, 450 "Cannot set vqmmc to %d<->%d\n", 451 uvolt, 452 uvolt); 453 return (err); 454 } 455 456 /* 457 * According to the 'SD Host Controller Simplified 458 * Specification 4.20 the host driver should take more 459 * than 5ms for stable time of host voltage regulator 460 * from changing 1.8V Signaling Enable. 461 */ 462 DELAY(5000); 463 hostctrl2 = bus_read_2(sc->mem_res, SDHCI_HOST_CONTROL2); 464 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 465 return (0); 466 return EAGAIN; 467 default: 468 device_printf(brdev, 469 "Attempt to set unsupported signaling voltage\n"); 470 return EINVAL; 471 } 472 } 473 474 static int 475 sdhci_xenon_probe(device_t dev) 476 { 477 struct sdhci_xenon_softc *sc = device_get_softc(dev); 478 pcell_t cid; 479 480 sc->quirks = 0; 481 sc->slot_id = 0; 482 sc->max_clk = XENON_MMC_MAX_CLK; 483 484 if (!ofw_bus_status_okay(dev)) 485 return (ENXIO); 486 487 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 488 return (ENXIO); 489 490 sc->node = ofw_bus_get_node(dev); 491 device_set_desc(dev, "Armada Xenon SDHCI controller"); 492 493 /* Allow dts to patch quirks, slots, and max-frequency. */ 494 if ((OF_getencprop(sc->node, "quirks", &cid, sizeof(cid))) > 0) 495 sc->quirks = cid; 496 if ((OF_getencprop(sc->node, "max-frequency", &cid, sizeof(cid))) > 0) 497 sc->max_clk = cid; 498 if (OF_hasprop(sc->node, "no-1-8-v")) 499 sc->no_18v = true; 500 if (OF_hasprop(sc->node, "marvell,xenon-phy-slow-mode")) 501 sc->slow_mode = true; 502 sc->znr = XENON_ZNR_DEF_VALUE; 503 if ((OF_getencprop(sc->node, "marvell,xenon-phy-znr", &cid, 504 sizeof(cid))) > 0) 505 sc->znr = cid & XENON_ZNR_MASK; 506 sc->zpr = XENON_ZPR_DEF_VALUE; 507 if ((OF_getencprop(sc->node, "marvell,xenon-phy-zpr", &cid, 508 sizeof(cid))) > 0) 509 sc->zpr = cid & XENON_ZPR_MASK; 510 511 return (0); 512 } 513 514 static int 515 sdhci_xenon_attach(device_t dev) 516 { 517 struct sdhci_xenon_softc *sc = device_get_softc(dev); 518 struct sdhci_slot *slot; 519 int err, rid; 520 uint32_t reg; 521 522 sc->dev = dev; 523 524 /* Allocate IRQ. */ 525 rid = 0; 526 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 527 RF_ACTIVE); 528 if (sc->irq_res == NULL) { 529 device_printf(dev, "Can't allocate IRQ\n"); 530 return (ENOMEM); 531 } 532 533 /* Allocate memory. */ 534 rid = 0; 535 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 536 &rid, RF_ACTIVE); 537 if (sc->mem_res == NULL) { 538 bus_release_resource(dev, SYS_RES_IRQ, 539 rman_get_rid(sc->irq_res), sc->irq_res); 540 device_printf(dev, "Can't allocate memory for slot\n"); 541 return (ENOMEM); 542 } 543 544 slot = malloc(sizeof(*slot), M_DEVBUF, M_ZERO | M_WAITOK); 545 546 /* Check if the device is flagged as non-removable. */ 547 if (OF_hasprop(sc->node, "non-removable")) { 548 slot->opt |= SDHCI_NON_REMOVABLE; 549 if (bootverbose) 550 device_printf(dev, "Non-removable media\n"); 551 } 552 553 slot->quirks = sc->quirks; 554 slot->caps = sc->caps; 555 slot->max_clk = sc->max_clk; 556 sc->slot = slot; 557 558 /* 559 * Set up any gpio pin handling described in the FDT data. This cannot 560 * fail; see comments in sdhci_fdt_gpio.h for details. 561 */ 562 sc->gpio = sdhci_fdt_gpio_setup(dev, slot); 563 564 mmc_fdt_parse(dev, 0, &sc->mmc_helper, &sc->slot->host); 565 566 if (sdhci_init_slot(dev, sc->slot, 0)) 567 goto fail; 568 569 /* 1.2V signaling is not supported. */ 570 sc->slot->host.caps &= ~MMC_CAP_SIGNALING_120; 571 572 /* Disable UHS in case of lack of 1.8V VCCQ or the PHY slow mode. */ 573 if (sc->no_18v || sc->slow_mode) 574 sc->slot->host.caps &= ~MMC_CAP_SIGNALING_180; 575 576 /* Activate the interrupt */ 577 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 578 NULL, sdhci_xenon_intr, sc, &sc->intrhand); 579 if (err) { 580 device_printf(dev, "Cannot setup IRQ\n"); 581 goto fail; 582 } 583 584 /* Disable Auto Clock Gating. */ 585 reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL); 586 reg |= XENON_AUTO_CLKGATE_DISABLE; 587 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg); 588 589 /* Enable this SD controller. */ 590 reg |= (1 << sc->slot_id); 591 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg); 592 593 /* Enable Parallel Transfer. */ 594 reg = bus_read_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL); 595 reg |= (1 << sc->slot_id); 596 bus_write_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL, reg); 597 598 /* Enable Auto Clock Gating. */ 599 reg &= ~XENON_AUTO_CLKGATE_DISABLE; 600 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg); 601 602 /* Disable SDCLK_IDLEOFF before the card initialization. */ 603 reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL); 604 reg &= ~(1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sc->slot_id)); 605 bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg); 606 607 /* Mask command conflict errors. */ 608 reg = bus_read_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL); 609 reg |= XENON_MASK_CMD_CONFLICT_ERR; 610 bus_write_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL, reg); 611 612 /* Process cards detection. */ 613 sdhci_start_slot(sc->slot); 614 615 return (0); 616 617 fail: 618 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res), 619 sc->irq_res); 620 bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->mem_res), 621 sc->mem_res); 622 free(sc->slot, M_DEVBUF); 623 sc->slot = NULL; 624 625 return (ENXIO); 626 } 627 628 static int 629 sdhci_xenon_detach(device_t dev) 630 { 631 struct sdhci_xenon_softc *sc = device_get_softc(dev); 632 633 if (sc->gpio != NULL) 634 sdhci_fdt_gpio_teardown(sc->gpio); 635 636 bus_generic_detach(dev); 637 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 638 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res), 639 sc->irq_res); 640 sdhci_cleanup_slot(sc->slot); 641 bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->mem_res), 642 sc->mem_res); 643 free(sc->slot, M_DEVBUF); 644 sc->slot = NULL; 645 646 return (0); 647 } 648 649 static device_method_t sdhci_xenon_methods[] = { 650 /* device_if */ 651 DEVMETHOD(device_probe, sdhci_xenon_probe), 652 DEVMETHOD(device_attach, sdhci_xenon_attach), 653 DEVMETHOD(device_detach, sdhci_xenon_detach), 654 655 /* Bus interface */ 656 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 657 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 658 659 /* mmcbr_if */ 660 DEVMETHOD(mmcbr_update_ios, sdhci_xenon_update_ios), 661 DEVMETHOD(mmcbr_request, sdhci_generic_request), 662 DEVMETHOD(mmcbr_get_ro, sdhci_xenon_get_ro), 663 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 664 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 665 DEVMETHOD(mmcbr_switch_vccq, sdhci_xenon_switch_vccq), 666 667 /* SDHCI registers accessors */ 668 DEVMETHOD(sdhci_read_1, sdhci_xenon_read_1), 669 DEVMETHOD(sdhci_read_2, sdhci_xenon_read_2), 670 DEVMETHOD(sdhci_read_4, sdhci_xenon_read_4), 671 DEVMETHOD(sdhci_read_multi_4, sdhci_xenon_read_multi_4), 672 DEVMETHOD(sdhci_write_1, sdhci_xenon_write_1), 673 DEVMETHOD(sdhci_write_2, sdhci_xenon_write_2), 674 DEVMETHOD(sdhci_write_4, sdhci_xenon_write_4), 675 DEVMETHOD(sdhci_write_multi_4, sdhci_xenon_write_multi_4), 676 DEVMETHOD(sdhci_get_card_present, sdhci_xenon_get_card_present), 677 678 DEVMETHOD_END 679 }; 680 681 static driver_t sdhci_xenon_driver = { 682 "sdhci_xenon", 683 sdhci_xenon_methods, 684 sizeof(struct sdhci_xenon_softc), 685 }; 686 static devclass_t sdhci_xenon_devclass; 687 688 DRIVER_MODULE(sdhci_xenon, simplebus, sdhci_xenon_driver, sdhci_xenon_devclass, 689 NULL, NULL); 690 691 SDHCI_DEPEND(sdhci_xenon); 692 #ifndef MMCCAM 693 MMC_DECLARE_BRIDGE(sdhci_xenon); 694 #endif 695