1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #ifndef __SDHCI_H__ 31 #define __SDHCI_H__ 32 33 #include "opt_mmccam.h" 34 35 #define DMA_BLOCK_SIZE 4096 36 #define DMA_BOUNDARY 0 /* DMA reload every 4K */ 37 38 /* Controller doesn't honor resets unless we touch the clock register */ 39 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1 << 0) 40 /* Controller really supports DMA */ 41 #define SDHCI_QUIRK_FORCE_DMA (1 << 1) 42 /* Controller has unusable DMA engine */ 43 #define SDHCI_QUIRK_BROKEN_DMA (1 << 2) 44 /* Controller doesn't like to be reset when there is no card inserted. */ 45 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1 << 3) 46 /* Controller has flaky internal state so reset it on each ios change */ 47 #define SDHCI_QUIRK_RESET_ON_IOS (1 << 4) 48 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 49 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1 << 5) 50 /* Controller needs to be reset after each request to stay stable */ 51 #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1 << 6) 52 /* Controller has an off-by-one issue with timeout value */ 53 #define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1 << 7) 54 /* Controller has broken read timings */ 55 #define SDHCI_QUIRK_BROKEN_TIMINGS (1 << 8) 56 /* Controller needs lowered frequency */ 57 #define SDHCI_QUIRK_LOWER_FREQUENCY (1 << 9) 58 /* Data timeout is invalid, should use SD clock */ 59 #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1 << 10) 60 /* Timeout value is invalid, should be overriden */ 61 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1 << 11) 62 /* SDHCI_CAPABILITIES is invalid */ 63 #define SDHCI_QUIRK_MISSING_CAPS (1 << 12) 64 /* Hardware shifts the 136-bit response, don't do it in software. */ 65 #define SDHCI_QUIRK_DONT_SHIFT_RESPONSE (1 << 13) 66 /* Wait to see reset bit asserted before waiting for de-asserted */ 67 #define SDHCI_QUIRK_WAITFOR_RESET_ASSERTED (1 << 14) 68 /* Leave controller in standard mode when putting card in HS mode. */ 69 #define SDHCI_QUIRK_DONT_SET_HISPD_BIT (1 << 15) 70 /* Alternate clock source is required when supplying a 400 KHz clock. */ 71 #define SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC (1 << 16) 72 /* Card insert/remove interrupts don't work, polling required. */ 73 #define SDHCI_QUIRK_POLL_CARD_PRESENT (1 << 17) 74 /* All controller slots are non-removable. */ 75 #define SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE (1 << 18) 76 /* Issue custom Intel controller reset sequence after power-up. */ 77 #define SDHCI_QUIRK_INTEL_POWER_UP_RESET (1 << 19) 78 /* Data timeout is invalid, use 1 MHz clock instead. */ 79 #define SDHCI_QUIRK_DATA_TIMEOUT_1MHZ (1 << 20) 80 /* Controller doesn't allow access boot partitions. */ 81 #define SDHCI_QUIRK_BOOT_NOACC (1 << 21) 82 /* Controller waits for busy responses. */ 83 #define SDHCI_QUIRK_WAIT_WHILE_BUSY (1 << 22) 84 /* Controller supports eMMC DDR52 mode. */ 85 #define SDHCI_QUIRK_MMC_DDR52 (1 << 23) 86 /* Controller support for UHS DDR50 mode is broken. */ 87 #define SDHCI_QUIRK_BROKEN_UHS_DDR50 (1 << 24) 88 /* Controller support for eMMC HS200 mode is broken. */ 89 #define SDHCI_QUIRK_BROKEN_MMC_HS200 (1 << 25) 90 /* Controller reports support for eMMC HS400 mode as SDHCI_CAN_MMC_HS400. */ 91 #define SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 (1 << 26) 92 /* Controller support for SDHCI_CTRL2_PRESET_VALUE is broken. */ 93 #define SDHCI_QUIRK_PRESET_VALUE_BROKEN (1 << 27) 94 /* Controller does not support or the support for ACMD12 is broken. */ 95 #define SDHCI_QUIRK_BROKEN_AUTO_STOP (1 << 28) 96 97 /* 98 * Controller registers 99 */ 100 #define SDHCI_DMA_ADDRESS 0x00 101 102 #define SDHCI_BLOCK_SIZE 0x04 103 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 104 105 #define SDHCI_BLOCK_COUNT 0x06 106 107 #define SDHCI_ARGUMENT 0x08 108 109 #define SDHCI_TRANSFER_MODE 0x0C 110 #define SDHCI_TRNS_DMA 0x01 111 #define SDHCI_TRNS_BLK_CNT_EN 0x02 112 #define SDHCI_TRNS_ACMD12 0x04 113 #define SDHCI_TRNS_READ 0x10 114 #define SDHCI_TRNS_MULTI 0x20 115 116 #define SDHCI_COMMAND_FLAGS 0x0E 117 #define SDHCI_CMD_RESP_NONE 0x00 118 #define SDHCI_CMD_RESP_LONG 0x01 119 #define SDHCI_CMD_RESP_SHORT 0x02 120 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 121 #define SDHCI_CMD_RESP_MASK 0x03 122 #define SDHCI_CMD_CRC 0x08 123 #define SDHCI_CMD_INDEX 0x10 124 #define SDHCI_CMD_DATA 0x20 125 #define SDHCI_CMD_TYPE_NORMAL 0x00 126 #define SDHCI_CMD_TYPE_SUSPEND 0x40 127 #define SDHCI_CMD_TYPE_RESUME 0x80 128 #define SDHCI_CMD_TYPE_ABORT 0xc0 129 #define SDHCI_CMD_TYPE_MASK 0xc0 130 131 #define SDHCI_COMMAND 0x0F 132 133 #define SDHCI_RESPONSE 0x10 134 135 #define SDHCI_BUFFER 0x20 136 137 #define SDHCI_PRESENT_STATE 0x24 138 #define SDHCI_CMD_INHIBIT 0x00000001 139 #define SDHCI_DAT_INHIBIT 0x00000002 140 #define SDHCI_DAT_ACTIVE 0x00000004 141 #define SDHCI_RETUNE_REQUEST 0x00000008 142 #define SDHCI_DOING_WRITE 0x00000100 143 #define SDHCI_DOING_READ 0x00000200 144 #define SDHCI_SPACE_AVAILABLE 0x00000400 145 #define SDHCI_DATA_AVAILABLE 0x00000800 146 #define SDHCI_CARD_PRESENT 0x00010000 147 #define SDHCI_CARD_STABLE 0x00020000 148 #define SDHCI_CARD_PIN 0x00040000 149 #define SDHCI_WRITE_PROTECT 0x00080000 150 #define SDHCI_STATE_DAT_MASK 0x00f00000 151 #define SDHCI_STATE_CMD 0x01000000 152 153 #define SDHCI_HOST_CONTROL 0x28 154 #define SDHCI_CTRL_LED 0x01 155 #define SDHCI_CTRL_4BITBUS 0x02 156 #define SDHCI_CTRL_HISPD 0x04 157 #define SDHCI_CTRL_SDMA 0x08 158 #define SDHCI_CTRL_ADMA2 0x10 159 #define SDHCI_CTRL_ADMA264 0x18 160 #define SDHCI_CTRL_DMA_MASK 0x18 161 #define SDHCI_CTRL_8BITBUS 0x20 162 #define SDHCI_CTRL_CARD_DET 0x40 163 #define SDHCI_CTRL_FORCE_CARD 0x80 164 165 #define SDHCI_POWER_CONTROL 0x29 166 #define SDHCI_POWER_ON 0x01 167 #define SDHCI_POWER_180 0x0A 168 #define SDHCI_POWER_300 0x0C 169 #define SDHCI_POWER_330 0x0E 170 171 #define SDHCI_BLOCK_GAP_CONTROL 0x2A 172 173 #define SDHCI_WAKE_UP_CONTROL 0x2B 174 175 #define SDHCI_CLOCK_CONTROL 0x2C 176 #define SDHCI_DIVIDER_MASK 0xff 177 #define SDHCI_DIVIDER_MASK_LEN 8 178 #define SDHCI_DIVIDER_SHIFT 8 179 #define SDHCI_DIVIDER_HI_MASK 3 180 #define SDHCI_DIVIDER_HI_SHIFT 6 181 #define SDHCI_CLOCK_CARD_EN 0x0004 182 #define SDHCI_CLOCK_INT_STABLE 0x0002 183 #define SDHCI_CLOCK_INT_EN 0x0001 184 #define SDHCI_DIVIDERS_MASK \ 185 ((SDHCI_DIVIDER_MASK << SDHCI_DIVIDER_SHIFT) | \ 186 (SDHCI_DIVIDER_HI_MASK << SDHCI_DIVIDER_HI_SHIFT)) 187 188 #define SDHCI_TIMEOUT_CONTROL 0x2E 189 190 #define SDHCI_SOFTWARE_RESET 0x2F 191 #define SDHCI_RESET_ALL 0x01 192 #define SDHCI_RESET_CMD 0x02 193 #define SDHCI_RESET_DATA 0x04 194 195 #define SDHCI_INT_STATUS 0x30 196 #define SDHCI_INT_ENABLE 0x34 197 #define SDHCI_SIGNAL_ENABLE 0x38 198 #define SDHCI_INT_RESPONSE 0x00000001 199 #define SDHCI_INT_DATA_END 0x00000002 200 #define SDHCI_INT_BLOCK_GAP 0x00000004 201 #define SDHCI_INT_DMA_END 0x00000008 202 #define SDHCI_INT_SPACE_AVAIL 0x00000010 203 #define SDHCI_INT_DATA_AVAIL 0x00000020 204 #define SDHCI_INT_CARD_INSERT 0x00000040 205 #define SDHCI_INT_CARD_REMOVE 0x00000080 206 #define SDHCI_INT_CARD_INT 0x00000100 207 #define SDHCI_INT_INT_A 0x00000200 208 #define SDHCI_INT_INT_B 0x00000400 209 #define SDHCI_INT_INT_C 0x00000800 210 #define SDHCI_INT_RETUNE 0x00001000 211 #define SDHCI_INT_ERROR 0x00008000 212 #define SDHCI_INT_TIMEOUT 0x00010000 213 #define SDHCI_INT_CRC 0x00020000 214 #define SDHCI_INT_END_BIT 0x00040000 215 #define SDHCI_INT_INDEX 0x00080000 216 #define SDHCI_INT_DATA_TIMEOUT 0x00100000 217 #define SDHCI_INT_DATA_CRC 0x00200000 218 #define SDHCI_INT_DATA_END_BIT 0x00400000 219 #define SDHCI_INT_BUS_POWER 0x00800000 220 #define SDHCI_INT_ACMD12ERR 0x01000000 221 #define SDHCI_INT_ADMAERR 0x02000000 222 #define SDHCI_INT_TUNEERR 0x04000000 223 224 #define SDHCI_INT_NORMAL_MASK 0x00007FFF 225 #define SDHCI_INT_ERROR_MASK 0xFFFF8000 226 227 #define SDHCI_INT_CMD_ERROR_MASK (SDHCI_INT_TIMEOUT | \ 228 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) 229 230 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_CMD_ERROR_MASK) 231 232 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 233 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 234 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 235 SDHCI_INT_DATA_END_BIT) 236 237 #define SDHCI_ACMD12_ERR 0x3C 238 239 #define SDHCI_HOST_CONTROL2 0x3E 240 #define SDHCI_CTRL2_PRESET_VALUE 0x8000 241 #define SDHCI_CTRL2_ASYNC_INTR 0x4000 242 #define SDHCI_CTRL2_64BIT_ENABLE 0x2000 243 #define SDHCI_CTRL2_HOST_V4_ENABLE 0x1000 244 #define SDHCI_CTRL2_CMD23_ENABLE 0x0800 245 #define SDHCI_CTRL2_ADMA2_LENGTH_MODE 0x0400 246 #define SDHCI_CTRL2_UHS2_IFACE_ENABLE 0x0100 247 #define SDHCI_CTRL2_SAMPLING_CLOCK 0x0080 248 #define SDHCI_CTRL2_EXEC_TUNING 0x0040 249 #define SDHCI_CTRL2_DRIVER_TYPE_MASK 0x0030 250 #define SDHCI_CTRL2_DRIVER_TYPE_B 0x0000 251 #define SDHCI_CTRL2_DRIVER_TYPE_A 0x0010 252 #define SDHCI_CTRL2_DRIVER_TYPE_C 0x0020 253 #define SDHCI_CTRL2_DRIVER_TYPE_D 0x0030 254 #define SDHCI_CTRL2_S18_ENABLE 0x0008 255 #define SDHCI_CTRL2_UHS_MASK 0x0007 256 #define SDHCI_CTRL2_UHS_SDR12 0x0000 257 #define SDHCI_CTRL2_UHS_SDR25 0x0001 258 #define SDHCI_CTRL2_UHS_SDR50 0x0002 259 #define SDHCI_CTRL2_UHS_SDR104 0x0003 260 #define SDHCI_CTRL2_UHS_DDR50 0x0004 261 #define SDHCI_CTRL2_MMC_HS400 0x0005 /* non-standard */ 262 263 #define SDHCI_CAPABILITIES 0x40 264 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 265 #define SDHCI_TIMEOUT_CLK_SHIFT 0 266 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 267 #define SDHCI_CLOCK_BASE_MASK 0x00003F00 268 #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 269 #define SDHCI_CLOCK_BASE_SHIFT 8 270 #define SDHCI_MAX_BLOCK_MASK 0x00030000 271 #define SDHCI_MAX_BLOCK_SHIFT 16 272 #define SDHCI_CAN_DO_8BITBUS 0x00040000 273 #define SDHCI_CAN_DO_ADMA2 0x00080000 274 #define SDHCI_CAN_DO_HISPD 0x00200000 275 #define SDHCI_CAN_DO_DMA 0x00400000 276 #define SDHCI_CAN_DO_SUSPEND 0x00800000 277 #define SDHCI_CAN_VDD_330 0x01000000 278 #define SDHCI_CAN_VDD_300 0x02000000 279 #define SDHCI_CAN_VDD_180 0x04000000 280 #define SDHCI_CAN_DO_64BIT 0x10000000 281 #define SDHCI_CAN_ASYNC_INTR 0x20000000 282 #define SDHCI_SLOTTYPE_MASK 0xC0000000 283 #define SDHCI_SLOTTYPE_REMOVABLE 0x00000000 284 #define SDHCI_SLOTTYPE_EMBEDDED 0x40000000 285 #define SDHCI_SLOTTYPE_SHARED 0x80000000 286 287 #define SDHCI_CAPABILITIES2 0x44 288 #define SDHCI_CAN_SDR50 0x00000001 289 #define SDHCI_CAN_SDR104 0x00000002 290 #define SDHCI_CAN_DDR50 0x00000004 291 #define SDHCI_CAN_DRIVE_TYPE_A 0x00000010 292 #define SDHCI_CAN_DRIVE_TYPE_C 0x00000020 293 #define SDHCI_CAN_DRIVE_TYPE_D 0x00000040 294 #define SDHCI_RETUNE_CNT_MASK 0x00000F00 295 #define SDHCI_RETUNE_CNT_SHIFT 8 296 #define SDHCI_TUNE_SDR50 0x00002000 297 #define SDHCI_RETUNE_MODES_MASK 0x0000C000 298 #define SDHCI_RETUNE_MODES_SHIFT 14 299 #define SDHCI_CLOCK_MULT_MASK 0x00FF0000 300 #define SDHCI_CLOCK_MULT_SHIFT 16 301 #define SDHCI_CAN_MMC_HS400 0x80000000 /* non-standard */ 302 303 #define SDHCI_MAX_CURRENT 0x48 304 #define SDHCI_FORCE_AUTO_EVENT 0x50 305 #define SDHCI_FORCE_INTR_EVENT 0x52 306 307 #define SDHCI_ADMA_ERR 0x54 308 #define SDHCI_ADMA_ERR_LENGTH 0x04 309 #define SDHCI_ADMA_ERR_STATE_MASK 0x03 310 #define SDHCI_ADMA_ERR_STATE_STOP 0x00 311 #define SDHCI_ADMA_ERR_STATE_FDS 0x01 312 #define SDHCI_ADMA_ERR_STATE_TFR 0x03 313 314 #define SDHCI_ADMA_ADDRESS_LO 0x58 315 #define SDHCI_ADMA_ADDRESS_HI 0x5C 316 317 #define SDHCI_PRESET_VALUE 0x60 318 #define SDHCI_SHARED_BUS_CTRL 0xE0 319 320 #define SDHCI_SLOT_INT_STATUS 0xFC 321 322 #define SDHCI_HOST_VERSION 0xFE 323 #define SDHCI_VENDOR_VER_MASK 0xFF00 324 #define SDHCI_VENDOR_VER_SHIFT 8 325 #define SDHCI_SPEC_VER_MASK 0x00FF 326 #define SDHCI_SPEC_VER_SHIFT 0 327 #define SDHCI_SPEC_100 0 328 #define SDHCI_SPEC_200 1 329 #define SDHCI_SPEC_300 2 330 #define SDHCI_SPEC_400 3 331 #define SDHCI_SPEC_410 4 332 #define SDHCI_SPEC_420 5 333 334 SYSCTL_DECL(_hw_sdhci); 335 336 extern u_int sdhci_quirk_clear; 337 extern u_int sdhci_quirk_set; 338 339 struct sdhci_slot { 340 struct mtx mtx; /* Slot mutex */ 341 u_int quirks; /* Chip specific quirks */ 342 u_int caps; /* Override SDHCI_CAPABILITIES */ 343 u_int caps2; /* Override SDHCI_CAPABILITIES2 */ 344 device_t bus; /* Bus device */ 345 device_t dev; /* Slot device */ 346 u_char num; /* Slot number */ 347 u_char opt; /* Slot options */ 348 #define SDHCI_HAVE_DMA 0x01 349 #define SDHCI_PLATFORM_TRANSFER 0x02 350 #define SDHCI_NON_REMOVABLE 0x04 351 #define SDHCI_TUNING_SUPPORTED 0x08 352 #define SDHCI_TUNING_ENABLED 0x10 353 #define SDHCI_SDR50_NEEDS_TUNING 0x20 354 #define SDHCI_SLOT_EMBEDDED 0x40 355 u_char version; 356 int timeout; /* Transfer timeout */ 357 uint32_t max_clk; /* Max possible freq */ 358 uint32_t timeout_clk; /* Timeout freq */ 359 bus_dma_tag_t dmatag; 360 bus_dmamap_t dmamap; 361 u_char *dmamem; 362 bus_addr_t paddr; /* DMA buffer address */ 363 struct task card_task; /* Card presence check task */ 364 struct timeout_task 365 card_delayed_task;/* Card insert delayed task */ 366 struct callout card_poll_callout;/* Card present polling callout */ 367 struct callout timeout_callout;/* Card command/data response timeout */ 368 struct callout retune_callout; /* Re-tuning mode 1 callout */ 369 struct mmc_host host; /* Host parameters */ 370 struct mmc_request *req; /* Current request */ 371 struct mmc_command *curcmd; /* Current command of current request */ 372 373 struct mmc_request *tune_req; /* Tuning request */ 374 struct mmc_command *tune_cmd; /* Tuning command of tuning request */ 375 struct mmc_data *tune_data; /* Tuning data of tuning command */ 376 uint32_t retune_ticks; /* Re-tuning callout ticks [hz] */ 377 uint32_t intmask; /* Current interrupt mask */ 378 uint32_t clock; /* Current clock freq. */ 379 size_t offset; /* Data buffer offset */ 380 uint8_t hostctrl; /* Current host control register */ 381 uint8_t retune_count; /* Controller re-tuning count [s] */ 382 uint8_t retune_mode; /* Controller re-tuning mode */ 383 #define SDHCI_RETUNE_MODE_1 0x00 384 #define SDHCI_RETUNE_MODE_2 0x01 385 #define SDHCI_RETUNE_MODE_3 0x02 386 uint8_t retune_req; /* Re-tuning request status */ 387 #define SDHCI_RETUNE_REQ_NEEDED 0x01 /* Re-tuning w/o circuit reset needed */ 388 #define SDHCI_RETUNE_REQ_RESET 0x02 /* Re-tuning w/ circuit reset needed */ 389 u_char power; /* Current power */ 390 u_char bus_busy; /* Bus busy status */ 391 u_char cmd_done; /* CMD command part done flag */ 392 u_char data_done; /* DAT command part done flag */ 393 u_char flags; /* Request execution flags */ 394 #define CMD_STARTED 1 395 #define STOP_STARTED 2 396 #define SDHCI_USE_DMA 4 /* Use DMA for this req. */ 397 #define PLATFORM_DATA_STARTED 8 /* Data xfer is handled by platform */ 398 399 #ifdef MMCCAM 400 /* CAM stuff */ 401 union ccb *ccb; 402 struct cam_devq *devq; 403 struct cam_sim *sim; 404 struct mtx sim_mtx; 405 u_char card_present; /* XXX Maybe derive this from elsewhere? */ 406 #endif 407 }; 408 409 int sdhci_generic_read_ivar(device_t bus, device_t child, int which, 410 uintptr_t *result); 411 int sdhci_generic_write_ivar(device_t bus, device_t child, int which, 412 uintptr_t value); 413 int sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num); 414 void sdhci_start_slot(struct sdhci_slot *slot); 415 /* performs generic clean-up for platform transfers */ 416 void sdhci_finish_data(struct sdhci_slot *slot); 417 int sdhci_cleanup_slot(struct sdhci_slot *slot); 418 int sdhci_generic_suspend(struct sdhci_slot *slot); 419 int sdhci_generic_resume(struct sdhci_slot *slot); 420 int sdhci_generic_update_ios(device_t brdev, device_t reqdev); 421 int sdhci_generic_tune(device_t brdev, device_t reqdev, bool hs400); 422 int sdhci_generic_switch_vccq(device_t brdev, device_t reqdev); 423 int sdhci_generic_retune(device_t brdev, device_t reqdev, bool reset); 424 int sdhci_generic_request(device_t brdev, device_t reqdev, 425 struct mmc_request *req); 426 int sdhci_generic_get_ro(device_t brdev, device_t reqdev); 427 int sdhci_generic_acquire_host(device_t brdev, device_t reqdev); 428 int sdhci_generic_release_host(device_t brdev, device_t reqdev); 429 void sdhci_generic_intr(struct sdhci_slot *slot); 430 uint32_t sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot); 431 bool sdhci_generic_get_card_present(device_t brdev, struct sdhci_slot *slot); 432 void sdhci_generic_set_uhs_timing(device_t brdev, struct sdhci_slot *slot); 433 void sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present); 434 435 #endif /* __SDHCI_H__ */ 436