1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #ifndef __SDHCI_H__ 31 #define __SDHCI_H__ 32 33 #include "opt_mmccam.h" 34 35 /* Macro for sizing the SDMA bounce buffer on the SDMA buffer boundary. */ 36 #define SDHCI_SDMA_BNDRY_TO_BBUFSZ(bndry) (4096 * (1 << bndry)) 37 38 /* Controller doesn't honor resets unless we touch the clock register */ 39 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1 << 0) 40 /* Controller really supports DMA */ 41 #define SDHCI_QUIRK_FORCE_DMA (1 << 1) 42 /* Controller has unusable DMA engine */ 43 #define SDHCI_QUIRK_BROKEN_DMA (1 << 2) 44 /* Controller doesn't like to be reset when there is no card inserted. */ 45 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1 << 3) 46 /* Controller has flaky internal state so reset it on each ios change */ 47 #define SDHCI_QUIRK_RESET_ON_IOS (1 << 4) 48 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 49 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1 << 5) 50 /* Controller needs to be reset after each request to stay stable */ 51 #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1 << 6) 52 /* Controller has an off-by-one issue with timeout value */ 53 #define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1 << 7) 54 /* Controller has broken read timings */ 55 #define SDHCI_QUIRK_BROKEN_TIMINGS (1 << 8) 56 /* Controller needs lowered frequency */ 57 #define SDHCI_QUIRK_LOWER_FREQUENCY (1 << 9) 58 /* Data timeout is invalid, should use SD clock */ 59 #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1 << 10) 60 /* Timeout value is invalid, should be overriden */ 61 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1 << 11) 62 /* SDHCI_CAPABILITIES is invalid */ 63 #define SDHCI_QUIRK_MISSING_CAPS (1 << 12) 64 /* Hardware shifts the 136-bit response, don't do it in software. */ 65 #define SDHCI_QUIRK_DONT_SHIFT_RESPONSE (1 << 13) 66 /* Wait to see reset bit asserted before waiting for de-asserted */ 67 #define SDHCI_QUIRK_WAITFOR_RESET_ASSERTED (1 << 14) 68 /* Leave controller in standard mode when putting card in HS mode. */ 69 #define SDHCI_QUIRK_DONT_SET_HISPD_BIT (1 << 15) 70 /* Alternate clock source is required when supplying a 400 KHz clock. */ 71 #define SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC (1 << 16) 72 /* Card insert/remove interrupts don't work, polling required. */ 73 #define SDHCI_QUIRK_POLL_CARD_PRESENT (1 << 17) 74 /* All controller slots are non-removable. */ 75 #define SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE (1 << 18) 76 /* Issue custom Intel controller reset sequence after power-up. */ 77 #define SDHCI_QUIRK_INTEL_POWER_UP_RESET (1 << 19) 78 /* Data timeout is invalid, use 1 MHz clock instead. */ 79 #define SDHCI_QUIRK_DATA_TIMEOUT_1MHZ (1 << 20) 80 /* Controller doesn't allow access boot partitions. */ 81 #define SDHCI_QUIRK_BOOT_NOACC (1 << 21) 82 /* Controller waits for busy responses. */ 83 #define SDHCI_QUIRK_WAIT_WHILE_BUSY (1 << 22) 84 /* Controller supports eMMC DDR52 mode. */ 85 #define SDHCI_QUIRK_MMC_DDR52 (1 << 23) 86 /* Controller support for UHS DDR50 mode is broken. */ 87 #define SDHCI_QUIRK_BROKEN_UHS_DDR50 (1 << 24) 88 /* Controller support for eMMC HS200 mode is broken. */ 89 #define SDHCI_QUIRK_BROKEN_MMC_HS200 (1 << 25) 90 /* Controller reports support for eMMC HS400 mode as SDHCI_CAN_MMC_HS400. */ 91 #define SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 (1 << 26) 92 /* Controller support for SDHCI_CTRL2_PRESET_VALUE is broken. */ 93 #define SDHCI_QUIRK_PRESET_VALUE_BROKEN (1 << 27) 94 /* Controller does not support or the support for ACMD12 is broken. */ 95 #define SDHCI_QUIRK_BROKEN_AUTO_STOP (1 << 28) 96 /* Controller supports eMMC HS400 mode if SDHCI_CAN_SDR104 is set. */ 97 #define SDHCI_QUIRK_MMC_HS400_IF_CAN_SDR104 (1 << 29) 98 /* SDMA boundary in SDHCI_BLOCK_SIZE broken - use front-end supplied value. */ 99 #define SDHCI_QUIRK_BROKEN_SDMA_BOUNDARY (1 << 30) 100 101 /* 102 * Controller registers 103 */ 104 #define SDHCI_DMA_ADDRESS 0x00 105 106 #define SDHCI_BLOCK_SIZE 0x04 107 #define SDHCI_BLKSZ_SDMA_BNDRY_4K 0x00 108 #define SDHCI_BLKSZ_SDMA_BNDRY_8K 0x01 109 #define SDHCI_BLKSZ_SDMA_BNDRY_16K 0x02 110 #define SDHCI_BLKSZ_SDMA_BNDRY_32K 0x03 111 #define SDHCI_BLKSZ_SDMA_BNDRY_64K 0x04 112 #define SDHCI_BLKSZ_SDMA_BNDRY_128K 0x05 113 #define SDHCI_BLKSZ_SDMA_BNDRY_256K 0x06 114 #define SDHCI_BLKSZ_SDMA_BNDRY_512K 0x07 115 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 116 117 #define SDHCI_BLOCK_COUNT 0x06 118 119 #define SDHCI_ARGUMENT 0x08 120 121 #define SDHCI_TRANSFER_MODE 0x0C 122 #define SDHCI_TRNS_DMA 0x01 123 #define SDHCI_TRNS_BLK_CNT_EN 0x02 124 #define SDHCI_TRNS_ACMD12 0x04 125 #define SDHCI_TRNS_READ 0x10 126 #define SDHCI_TRNS_MULTI 0x20 127 128 #define SDHCI_COMMAND_FLAGS 0x0E 129 #define SDHCI_CMD_RESP_NONE 0x00 130 #define SDHCI_CMD_RESP_LONG 0x01 131 #define SDHCI_CMD_RESP_SHORT 0x02 132 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 133 #define SDHCI_CMD_RESP_MASK 0x03 134 #define SDHCI_CMD_CRC 0x08 135 #define SDHCI_CMD_INDEX 0x10 136 #define SDHCI_CMD_DATA 0x20 137 #define SDHCI_CMD_TYPE_NORMAL 0x00 138 #define SDHCI_CMD_TYPE_SUSPEND 0x40 139 #define SDHCI_CMD_TYPE_RESUME 0x80 140 #define SDHCI_CMD_TYPE_ABORT 0xc0 141 #define SDHCI_CMD_TYPE_MASK 0xc0 142 143 #define SDHCI_COMMAND 0x0F 144 145 #define SDHCI_RESPONSE 0x10 146 147 #define SDHCI_BUFFER 0x20 148 149 #define SDHCI_PRESENT_STATE 0x24 150 #define SDHCI_CMD_INHIBIT 0x00000001 151 #define SDHCI_DAT_INHIBIT 0x00000002 152 #define SDHCI_DAT_ACTIVE 0x00000004 153 #define SDHCI_RETUNE_REQUEST 0x00000008 154 #define SDHCI_DOING_WRITE 0x00000100 155 #define SDHCI_DOING_READ 0x00000200 156 #define SDHCI_SPACE_AVAILABLE 0x00000400 157 #define SDHCI_DATA_AVAILABLE 0x00000800 158 #define SDHCI_CARD_PRESENT 0x00010000 159 #define SDHCI_CARD_STABLE 0x00020000 160 #define SDHCI_CARD_PIN 0x00040000 161 #define SDHCI_WRITE_PROTECT 0x00080000 162 #define SDHCI_STATE_DAT_MASK 0x00f00000 163 #define SDHCI_STATE_CMD 0x01000000 164 165 #define SDHCI_HOST_CONTROL 0x28 166 #define SDHCI_CTRL_LED 0x01 167 #define SDHCI_CTRL_4BITBUS 0x02 168 #define SDHCI_CTRL_HISPD 0x04 169 #define SDHCI_CTRL_SDMA 0x08 170 #define SDHCI_CTRL_ADMA2 0x10 171 #define SDHCI_CTRL_ADMA264 0x18 172 #define SDHCI_CTRL_DMA_MASK 0x18 173 #define SDHCI_CTRL_8BITBUS 0x20 174 #define SDHCI_CTRL_CARD_DET 0x40 175 #define SDHCI_CTRL_FORCE_CARD 0x80 176 177 #define SDHCI_POWER_CONTROL 0x29 178 #define SDHCI_POWER_ON 0x01 179 #define SDHCI_POWER_180 0x0A 180 #define SDHCI_POWER_300 0x0C 181 #define SDHCI_POWER_330 0x0E 182 183 #define SDHCI_BLOCK_GAP_CONTROL 0x2A 184 185 #define SDHCI_WAKE_UP_CONTROL 0x2B 186 187 #define SDHCI_CLOCK_CONTROL 0x2C 188 #define SDHCI_DIVIDER_MASK 0xff 189 #define SDHCI_DIVIDER_MASK_LEN 8 190 #define SDHCI_DIVIDER_SHIFT 8 191 #define SDHCI_DIVIDER_HI_MASK 3 192 #define SDHCI_DIVIDER_HI_SHIFT 6 193 #define SDHCI_CLOCK_CARD_EN 0x0004 194 #define SDHCI_CLOCK_INT_STABLE 0x0002 195 #define SDHCI_CLOCK_INT_EN 0x0001 196 #define SDHCI_DIVIDERS_MASK \ 197 ((SDHCI_DIVIDER_MASK << SDHCI_DIVIDER_SHIFT) | \ 198 (SDHCI_DIVIDER_HI_MASK << SDHCI_DIVIDER_HI_SHIFT)) 199 200 #define SDHCI_TIMEOUT_CONTROL 0x2E 201 202 #define SDHCI_SOFTWARE_RESET 0x2F 203 #define SDHCI_RESET_ALL 0x01 204 #define SDHCI_RESET_CMD 0x02 205 #define SDHCI_RESET_DATA 0x04 206 207 #define SDHCI_INT_STATUS 0x30 208 #define SDHCI_INT_ENABLE 0x34 209 #define SDHCI_SIGNAL_ENABLE 0x38 210 #define SDHCI_INT_RESPONSE 0x00000001 211 #define SDHCI_INT_DATA_END 0x00000002 212 #define SDHCI_INT_BLOCK_GAP 0x00000004 213 #define SDHCI_INT_DMA_END 0x00000008 214 #define SDHCI_INT_SPACE_AVAIL 0x00000010 215 #define SDHCI_INT_DATA_AVAIL 0x00000020 216 #define SDHCI_INT_CARD_INSERT 0x00000040 217 #define SDHCI_INT_CARD_REMOVE 0x00000080 218 #define SDHCI_INT_CARD_INT 0x00000100 219 #define SDHCI_INT_INT_A 0x00000200 220 #define SDHCI_INT_INT_B 0x00000400 221 #define SDHCI_INT_INT_C 0x00000800 222 #define SDHCI_INT_RETUNE 0x00001000 223 #define SDHCI_INT_ERROR 0x00008000 224 #define SDHCI_INT_TIMEOUT 0x00010000 225 #define SDHCI_INT_CRC 0x00020000 226 #define SDHCI_INT_END_BIT 0x00040000 227 #define SDHCI_INT_INDEX 0x00080000 228 #define SDHCI_INT_DATA_TIMEOUT 0x00100000 229 #define SDHCI_INT_DATA_CRC 0x00200000 230 #define SDHCI_INT_DATA_END_BIT 0x00400000 231 #define SDHCI_INT_BUS_POWER 0x00800000 232 #define SDHCI_INT_ACMD12ERR 0x01000000 233 #define SDHCI_INT_ADMAERR 0x02000000 234 #define SDHCI_INT_TUNEERR 0x04000000 235 236 #define SDHCI_INT_NORMAL_MASK 0x00007FFF 237 #define SDHCI_INT_ERROR_MASK 0xFFFF8000 238 239 #define SDHCI_INT_CMD_ERROR_MASK (SDHCI_INT_TIMEOUT | \ 240 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) 241 242 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_CMD_ERROR_MASK) 243 244 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 245 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 246 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 247 SDHCI_INT_DATA_END_BIT) 248 249 #define SDHCI_ACMD12_ERR 0x3C 250 251 #define SDHCI_HOST_CONTROL2 0x3E 252 #define SDHCI_CTRL2_PRESET_VALUE 0x8000 253 #define SDHCI_CTRL2_ASYNC_INTR 0x4000 254 #define SDHCI_CTRL2_64BIT_ENABLE 0x2000 255 #define SDHCI_CTRL2_HOST_V4_ENABLE 0x1000 256 #define SDHCI_CTRL2_CMD23_ENABLE 0x0800 257 #define SDHCI_CTRL2_ADMA2_LENGTH_MODE 0x0400 258 #define SDHCI_CTRL2_UHS2_IFACE_ENABLE 0x0100 259 #define SDHCI_CTRL2_SAMPLING_CLOCK 0x0080 260 #define SDHCI_CTRL2_EXEC_TUNING 0x0040 261 #define SDHCI_CTRL2_DRIVER_TYPE_MASK 0x0030 262 #define SDHCI_CTRL2_DRIVER_TYPE_B 0x0000 263 #define SDHCI_CTRL2_DRIVER_TYPE_A 0x0010 264 #define SDHCI_CTRL2_DRIVER_TYPE_C 0x0020 265 #define SDHCI_CTRL2_DRIVER_TYPE_D 0x0030 266 #define SDHCI_CTRL2_S18_ENABLE 0x0008 267 #define SDHCI_CTRL2_UHS_MASK 0x0007 268 #define SDHCI_CTRL2_UHS_SDR12 0x0000 269 #define SDHCI_CTRL2_UHS_SDR25 0x0001 270 #define SDHCI_CTRL2_UHS_SDR50 0x0002 271 #define SDHCI_CTRL2_UHS_SDR104 0x0003 272 #define SDHCI_CTRL2_UHS_DDR50 0x0004 273 #define SDHCI_CTRL2_MMC_HS400 0x0005 /* non-standard */ 274 275 #define SDHCI_CAPABILITIES 0x40 276 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 277 #define SDHCI_TIMEOUT_CLK_SHIFT 0 278 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 279 #define SDHCI_CLOCK_BASE_MASK 0x00003F00 280 #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 281 #define SDHCI_CLOCK_BASE_SHIFT 8 282 #define SDHCI_MAX_BLOCK_MASK 0x00030000 283 #define SDHCI_MAX_BLOCK_SHIFT 16 284 #define SDHCI_CAN_DO_8BITBUS 0x00040000 285 #define SDHCI_CAN_DO_ADMA2 0x00080000 286 #define SDHCI_CAN_DO_HISPD 0x00200000 287 #define SDHCI_CAN_DO_DMA 0x00400000 288 #define SDHCI_CAN_DO_SUSPEND 0x00800000 289 #define SDHCI_CAN_VDD_330 0x01000000 290 #define SDHCI_CAN_VDD_300 0x02000000 291 #define SDHCI_CAN_VDD_180 0x04000000 292 #define SDHCI_CAN_DO_64BIT 0x10000000 293 #define SDHCI_CAN_ASYNC_INTR 0x20000000 294 #define SDHCI_SLOTTYPE_MASK 0xC0000000 295 #define SDHCI_SLOTTYPE_REMOVABLE 0x00000000 296 #define SDHCI_SLOTTYPE_EMBEDDED 0x40000000 297 #define SDHCI_SLOTTYPE_SHARED 0x80000000 298 299 #define SDHCI_CAPABILITIES2 0x44 300 #define SDHCI_CAN_SDR50 0x00000001 301 #define SDHCI_CAN_SDR104 0x00000002 302 #define SDHCI_CAN_DDR50 0x00000004 303 #define SDHCI_CAN_DRIVE_TYPE_A 0x00000010 304 #define SDHCI_CAN_DRIVE_TYPE_C 0x00000020 305 #define SDHCI_CAN_DRIVE_TYPE_D 0x00000040 306 #define SDHCI_RETUNE_CNT_MASK 0x00000F00 307 #define SDHCI_RETUNE_CNT_SHIFT 8 308 #define SDHCI_TUNE_SDR50 0x00002000 309 #define SDHCI_RETUNE_MODES_MASK 0x0000C000 310 #define SDHCI_RETUNE_MODES_SHIFT 14 311 #define SDHCI_CLOCK_MULT_MASK 0x00FF0000 312 #define SDHCI_CLOCK_MULT_SHIFT 16 313 #define SDHCI_CAN_MMC_HS400 0x80000000 /* non-standard */ 314 315 #define SDHCI_MAX_CURRENT 0x48 316 #define SDHCI_FORCE_AUTO_EVENT 0x50 317 #define SDHCI_FORCE_INTR_EVENT 0x52 318 319 #define SDHCI_ADMA_ERR 0x54 320 #define SDHCI_ADMA_ERR_LENGTH 0x04 321 #define SDHCI_ADMA_ERR_STATE_MASK 0x03 322 #define SDHCI_ADMA_ERR_STATE_STOP 0x00 323 #define SDHCI_ADMA_ERR_STATE_FDS 0x01 324 #define SDHCI_ADMA_ERR_STATE_TFR 0x03 325 326 #define SDHCI_ADMA_ADDRESS_LO 0x58 327 #define SDHCI_ADMA_ADDRESS_HI 0x5C 328 329 #define SDHCI_PRESET_VALUE 0x60 330 #define SDHCI_SHARED_BUS_CTRL 0xE0 331 332 #define SDHCI_SLOT_INT_STATUS 0xFC 333 334 #define SDHCI_HOST_VERSION 0xFE 335 #define SDHCI_VENDOR_VER_MASK 0xFF00 336 #define SDHCI_VENDOR_VER_SHIFT 8 337 #define SDHCI_SPEC_VER_MASK 0x00FF 338 #define SDHCI_SPEC_VER_SHIFT 0 339 #define SDHCI_SPEC_100 0 340 #define SDHCI_SPEC_200 1 341 #define SDHCI_SPEC_300 2 342 #define SDHCI_SPEC_400 3 343 #define SDHCI_SPEC_410 4 344 #define SDHCI_SPEC_420 5 345 346 SYSCTL_DECL(_hw_sdhci); 347 348 extern u_int sdhci_quirk_clear; 349 extern u_int sdhci_quirk_set; 350 351 struct sdhci_slot { 352 struct mtx mtx; /* Slot mutex */ 353 u_int quirks; /* Chip specific quirks */ 354 u_int caps; /* Override SDHCI_CAPABILITIES */ 355 u_int caps2; /* Override SDHCI_CAPABILITIES2 */ 356 device_t bus; /* Bus device */ 357 device_t dev; /* Slot device */ 358 u_char num; /* Slot number */ 359 u_char opt; /* Slot options */ 360 #define SDHCI_HAVE_DMA 0x01 361 #define SDHCI_PLATFORM_TRANSFER 0x02 362 #define SDHCI_NON_REMOVABLE 0x04 363 #define SDHCI_TUNING_SUPPORTED 0x08 364 #define SDHCI_TUNING_ENABLED 0x10 365 #define SDHCI_SDR50_NEEDS_TUNING 0x20 366 #define SDHCI_SLOT_EMBEDDED 0x40 367 u_char version; 368 int timeout; /* Transfer timeout */ 369 uint32_t max_clk; /* Max possible freq */ 370 uint32_t timeout_clk; /* Timeout freq */ 371 bus_dma_tag_t dmatag; 372 bus_dmamap_t dmamap; 373 u_char *dmamem; 374 bus_addr_t paddr; /* DMA buffer address */ 375 uint32_t sdma_bbufsz; /* SDMA bounce buffer size */ 376 uint8_t sdma_boundary; /* SDMA boundary */ 377 struct task card_task; /* Card presence check task */ 378 struct timeout_task 379 card_delayed_task;/* Card insert delayed task */ 380 struct callout card_poll_callout;/* Card present polling callout */ 381 struct callout timeout_callout;/* Card command/data response timeout */ 382 struct callout retune_callout; /* Re-tuning mode 1 callout */ 383 struct mmc_host host; /* Host parameters */ 384 struct mmc_request *req; /* Current request */ 385 struct mmc_command *curcmd; /* Current command of current request */ 386 387 struct mmc_request *tune_req; /* Tuning request */ 388 struct mmc_command *tune_cmd; /* Tuning command of tuning request */ 389 struct mmc_data *tune_data; /* Tuning data of tuning command */ 390 uint32_t retune_ticks; /* Re-tuning callout ticks [hz] */ 391 uint32_t intmask; /* Current interrupt mask */ 392 uint32_t clock; /* Current clock freq. */ 393 size_t offset; /* Data buffer offset */ 394 uint8_t hostctrl; /* Current host control register */ 395 uint8_t retune_count; /* Controller re-tuning count [s] */ 396 uint8_t retune_mode; /* Controller re-tuning mode */ 397 #define SDHCI_RETUNE_MODE_1 0x00 398 #define SDHCI_RETUNE_MODE_2 0x01 399 #define SDHCI_RETUNE_MODE_3 0x02 400 uint8_t retune_req; /* Re-tuning request status */ 401 #define SDHCI_RETUNE_REQ_NEEDED 0x01 /* Re-tuning w/o circuit reset needed */ 402 #define SDHCI_RETUNE_REQ_RESET 0x02 /* Re-tuning w/ circuit reset needed */ 403 u_char power; /* Current power */ 404 u_char bus_busy; /* Bus busy status */ 405 u_char cmd_done; /* CMD command part done flag */ 406 u_char data_done; /* DAT command part done flag */ 407 u_char flags; /* Request execution flags */ 408 #define CMD_STARTED 1 409 #define STOP_STARTED 2 410 #define SDHCI_USE_DMA 4 /* Use DMA for this req. */ 411 #define PLATFORM_DATA_STARTED 8 /* Data xfer is handled by platform */ 412 413 #ifdef MMCCAM 414 /* CAM stuff */ 415 union ccb *ccb; 416 struct cam_devq *devq; 417 struct cam_sim *sim; 418 struct mtx sim_mtx; 419 u_char card_present; /* XXX Maybe derive this from elsewhere? */ 420 #endif 421 }; 422 423 int sdhci_generic_read_ivar(device_t bus, device_t child, int which, 424 uintptr_t *result); 425 int sdhci_generic_write_ivar(device_t bus, device_t child, int which, 426 uintptr_t value); 427 int sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num); 428 void sdhci_start_slot(struct sdhci_slot *slot); 429 /* performs generic clean-up for platform transfers */ 430 void sdhci_finish_data(struct sdhci_slot *slot); 431 int sdhci_cleanup_slot(struct sdhci_slot *slot); 432 int sdhci_generic_suspend(struct sdhci_slot *slot); 433 int sdhci_generic_resume(struct sdhci_slot *slot); 434 void sdhci_generic_reset(device_t brdev, struct sdhci_slot *slot, uint8_t mask); 435 int sdhci_generic_update_ios(device_t brdev, device_t reqdev); 436 int sdhci_generic_tune(device_t brdev, device_t reqdev, bool hs400); 437 int sdhci_generic_switch_vccq(device_t brdev, device_t reqdev); 438 int sdhci_generic_retune(device_t brdev, device_t reqdev, bool reset); 439 int sdhci_generic_request(device_t brdev, device_t reqdev, 440 struct mmc_request *req); 441 int sdhci_generic_get_ro(device_t brdev, device_t reqdev); 442 int sdhci_generic_acquire_host(device_t brdev, device_t reqdev); 443 int sdhci_generic_release_host(device_t brdev, device_t reqdev); 444 void sdhci_generic_intr(struct sdhci_slot *slot); 445 uint32_t sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot); 446 bool sdhci_generic_get_card_present(device_t brdev, struct sdhci_slot *slot); 447 void sdhci_generic_set_uhs_timing(device_t brdev, struct sdhci_slot *slot); 448 void sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present); 449 450 #define SDHCI_VERSION 2 451 452 #define SDHCI_DEPEND(name) \ 453 MODULE_DEPEND(name, sdhci, SDHCI_VERSION, SDHCI_VERSION, SDHCI_VERSION); 454 455 #endif /* __SDHCI_H__ */ 456