1 /*-
2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 */
27 #include <sys/cdefs.h>
28 /*
29 * SDHCI driver glue for Freescale i.MX SoC and QorIQ families.
30 *
31 * This supports both eSDHC (earlier SoCs) and uSDHC (more recent SoCs).
32 */
33
34 #include "opt_mmccam.h"
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/types.h>
39 #include <sys/bus.h>
40 #include <sys/callout.h>
41 #include <sys/kernel.h>
42 #include <sys/libkern.h>
43 #include <sys/lock.h>
44 #include <sys/malloc.h>
45 #include <sys/module.h>
46 #include <sys/mutex.h>
47 #include <sys/resource.h>
48 #include <sys/rman.h>
49 #include <sys/sysctl.h>
50 #include <sys/taskqueue.h>
51 #include <sys/time.h>
52
53 #include <machine/bus.h>
54 #include <machine/resource.h>
55 #ifdef __arm__
56 #include <machine/intr.h>
57
58 #include <arm/freescale/imx/imx_ccmvar.h>
59 #endif
60
61 #ifdef __powerpc__
62 #include <powerpc/mpc85xx/mpc85xx.h>
63 #endif
64
65 #include <dev/gpio/gpiobusvar.h>
66
67 #include <dev/ofw/ofw_bus.h>
68 #include <dev/ofw/ofw_bus_subr.h>
69
70 #include <dev/mmc/bridge.h>
71
72 #include <dev/sdhci/sdhci.h>
73 #include <dev/sdhci/sdhci_fdt_gpio.h>
74
75 #include "mmcbr_if.h"
76 #include "sdhci_if.h"
77
78 struct fsl_sdhci_softc {
79 device_t dev;
80 struct resource * mem_res;
81 struct resource * irq_res;
82 void * intr_cookie;
83 struct sdhci_slot slot;
84 struct callout r1bfix_callout;
85 sbintime_t r1bfix_timeout_at;
86 struct sdhci_fdt_gpio * gpio;
87 uint32_t baseclk_hz;
88 uint32_t cmd_and_mode;
89 uint32_t r1bfix_intmask;
90 uint16_t sdclockreg_freq_bits;
91 uint8_t r1bfix_type;
92 uint8_t hwtype;
93 bool slot_init_done;
94 };
95
96 #define R1BFIX_NONE 0 /* No fix needed at next interrupt. */
97 #define R1BFIX_NODATA 1 /* Synthesize DATA_END for R1B w/o data. */
98 #define R1BFIX_AC12 2 /* Wait for busy after auto command 12. */
99
100 #define HWTYPE_NONE 0 /* Hardware not recognized/supported. */
101 #define HWTYPE_ESDHC 1 /* fsl5x and earlier. */
102 #define HWTYPE_USDHC 2 /* fsl6. */
103
104 /*
105 * Freescale-specific registers, or in some cases the layout of bits within the
106 * sdhci-defined register is different on Freescale. These names all begin with
107 * SDHC_ (not SDHCI_).
108 */
109
110 #define SDHC_WTMK_LVL 0x44 /* Watermark Level register. */
111 #define USDHC_MIX_CONTROL 0x48 /* Mix(ed) Control register. */
112 #define SDHC_VEND_SPEC 0xC0 /* Vendor-specific register. */
113 #define SDHC_VEND_FRC_SDCLK_ON (1 << 8)
114 #define SDHC_VEND_IPGEN (1 << 11)
115 #define SDHC_VEND_HCKEN (1 << 12)
116 #define SDHC_VEND_PEREN (1 << 13)
117
118 #define SDHC_PRES_STATE 0x24
119 #define SDHC_PRES_CIHB (1 << 0)
120 #define SDHC_PRES_CDIHB (1 << 1)
121 #define SDHC_PRES_DLA (1 << 2)
122 #define SDHC_PRES_SDSTB (1 << 3)
123 #define SDHC_PRES_IPGOFF (1 << 4)
124 #define SDHC_PRES_HCKOFF (1 << 5)
125 #define SDHC_PRES_PEROFF (1 << 6)
126 #define SDHC_PRES_SDOFF (1 << 7)
127 #define SDHC_PRES_WTA (1 << 8)
128 #define SDHC_PRES_RTA (1 << 9)
129 #define SDHC_PRES_BWEN (1 << 10)
130 #define SDHC_PRES_BREN (1 << 11)
131 #define SDHC_PRES_RTR (1 << 12)
132 #define SDHC_PRES_CINST (1 << 16)
133 #define SDHC_PRES_CDPL (1 << 18)
134 #define SDHC_PRES_WPSPL (1 << 19)
135 #define SDHC_PRES_CLSL (1 << 23)
136 #define SDHC_PRES_DLSL_SHIFT 24
137 #define SDHC_PRES_DLSL_MASK (0xffU << SDHC_PRES_DLSL_SHIFT)
138
139 #define SDHC_PROT_CTRL 0x28
140 #define SDHC_PROT_LED (1 << 0)
141 #define SDHC_PROT_WIDTH_1BIT (0 << 1)
142 #define SDHC_PROT_WIDTH_4BIT (1 << 1)
143 #define SDHC_PROT_WIDTH_8BIT (2 << 1)
144 #define SDHC_PROT_WIDTH_MASK (3 << 1)
145 #define SDHC_PROT_D3CD (1 << 3)
146 #define SDHC_PROT_EMODE_BIG (0 << 4)
147 #define SDHC_PROT_EMODE_HALF (1 << 4)
148 #define SDHC_PROT_EMODE_LITTLE (2 << 4)
149 #define SDHC_PROT_EMODE_MASK (3 << 4)
150 #define SDHC_PROT_SDMA (0 << 8)
151 #define SDHC_PROT_ADMA1 (1 << 8)
152 #define SDHC_PROT_ADMA2 (2 << 8)
153 #define SDHC_PROT_ADMA264 (3 << 8)
154 #define SDHC_PROT_DMA_MASK (3 << 8)
155 #define SDHC_PROT_CDTL (1 << 6)
156 #define SDHC_PROT_CDSS (1 << 7)
157
158 #define SDHC_SYS_CTRL 0x2c
159
160 /*
161 * The clock enable bits exist in different registers for ESDHC vs USDHC, but
162 * they are the same bits in both cases. The divisor values go into the
163 * standard sdhci clock register, but in different bit positions and meanings
164 than the sdhci spec values.
165 */
166 #define SDHC_CLK_IPGEN (1 << 0)
167 #define SDHC_CLK_HCKEN (1 << 1)
168 #define SDHC_CLK_PEREN (1 << 2)
169 #define SDHC_CLK_SDCLKEN (1 << 3)
170 #define SDHC_CLK_ENABLE_MASK 0x0000000f
171 #define SDHC_CLK_DIVISOR_MASK 0x000000f0
172 #define SDHC_CLK_DIVISOR_SHIFT 4
173 #define SDHC_CLK_PRESCALE_MASK 0x0000ff00
174 #define SDHC_CLK_PRESCALE_SHIFT 8
175
176 static struct ofw_compat_data compat_data[] = {
177 {"fsl,imx6q-usdhc", HWTYPE_USDHC},
178 {"fsl,imx6sl-usdhc", HWTYPE_USDHC},
179 {"fsl,imx53-esdhc", HWTYPE_ESDHC},
180 {"fsl,imx51-esdhc", HWTYPE_ESDHC},
181 {"fsl,esdhc", HWTYPE_ESDHC},
182 {NULL, HWTYPE_NONE},
183 };
184
185 static uint16_t fsl_sdhc_get_clock(struct fsl_sdhci_softc *sc);
186 static void fsl_sdhc_set_clock(struct fsl_sdhci_softc *sc, uint16_t val);
187 static void fsl_sdhci_r1bfix_func(void *arg);
188
189 static inline uint32_t
RD4(struct fsl_sdhci_softc * sc,bus_size_t off)190 RD4(struct fsl_sdhci_softc *sc, bus_size_t off)
191 {
192
193 return (bus_read_4(sc->mem_res, off));
194 }
195
196 static inline void
WR4(struct fsl_sdhci_softc * sc,bus_size_t off,uint32_t val)197 WR4(struct fsl_sdhci_softc *sc, bus_size_t off, uint32_t val)
198 {
199
200 bus_write_4(sc->mem_res, off, val);
201 }
202
203 static uint8_t
fsl_sdhci_read_1(device_t dev,struct sdhci_slot * slot,bus_size_t off)204 fsl_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
205 {
206 struct fsl_sdhci_softc *sc = device_get_softc(dev);
207 uint32_t val32, wrk32;
208
209 /*
210 * Most of the things in the standard host control register are in the
211 * hardware's wider protocol control register, but some of the bits are
212 * moved around.
213 */
214 if (off == SDHCI_HOST_CONTROL) {
215 wrk32 = RD4(sc, SDHC_PROT_CTRL);
216 val32 = wrk32 & (SDHCI_CTRL_LED | SDHCI_CTRL_CARD_DET |
217 SDHCI_CTRL_FORCE_CARD);
218 switch (wrk32 & SDHC_PROT_WIDTH_MASK) {
219 case SDHC_PROT_WIDTH_1BIT:
220 /* Value is already 0. */
221 break;
222 case SDHC_PROT_WIDTH_4BIT:
223 val32 |= SDHCI_CTRL_4BITBUS;
224 break;
225 case SDHC_PROT_WIDTH_8BIT:
226 val32 |= SDHCI_CTRL_8BITBUS;
227 break;
228 }
229 switch (wrk32 & SDHC_PROT_DMA_MASK) {
230 case SDHC_PROT_SDMA:
231 /* Value is already 0. */
232 break;
233 case SDHC_PROT_ADMA1:
234 /* This value is deprecated, should never appear. */
235 break;
236 case SDHC_PROT_ADMA2:
237 val32 |= SDHCI_CTRL_ADMA2;
238 break;
239 case SDHC_PROT_ADMA264:
240 val32 |= SDHCI_CTRL_ADMA264;
241 break;
242 }
243 return val32;
244 }
245
246 /*
247 * XXX can't find the bus power on/off knob. For now we have to say the
248 * power is always on and always set to the same voltage.
249 */
250 if (off == SDHCI_POWER_CONTROL) {
251 return (SDHCI_POWER_ON | SDHCI_POWER_300);
252 }
253
254 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff);
255 }
256
257 static uint16_t
fsl_sdhci_read_2(device_t dev,struct sdhci_slot * slot,bus_size_t off)258 fsl_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
259 {
260 struct fsl_sdhci_softc *sc = device_get_softc(dev);
261 uint32_t val32;
262
263 if (sc->hwtype == HWTYPE_USDHC) {
264 /*
265 * The USDHC hardware has nothing in the version register, but
266 * it's v3 compatible with all our translation code.
267 */
268 if (off == SDHCI_HOST_VERSION) {
269 return (SDHCI_SPEC_300 << SDHCI_SPEC_VER_SHIFT);
270 }
271 /*
272 * The USDHC hardware moved the transfer mode bits to the mixed
273 * control register, fetch them from there.
274 */
275 if (off == SDHCI_TRANSFER_MODE)
276 return (RD4(sc, USDHC_MIX_CONTROL) & 0x37);
277
278 } else if (sc->hwtype == HWTYPE_ESDHC) {
279 /*
280 * The ESDHC hardware has the typical 32-bit combined "command
281 * and mode" register that we have to cache so that command
282 * isn't written until after mode. On a read, just retrieve the
283 * cached values last written.
284 */
285 if (off == SDHCI_TRANSFER_MODE) {
286 return (sc->cmd_and_mode & 0x0000ffff);
287 } else if (off == SDHCI_COMMAND_FLAGS) {
288 return (sc->cmd_and_mode >> 16);
289 }
290 }
291
292 /*
293 * This hardware only manages one slot. Synthesize a slot interrupt
294 * status register... if there are any enabled interrupts active they
295 * must be coming from our one and only slot.
296 */
297 if (off == SDHCI_SLOT_INT_STATUS) {
298 val32 = RD4(sc, SDHCI_INT_STATUS);
299 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE);
300 return (val32 ? 1 : 0);
301 }
302
303 /*
304 * Clock bits are scattered into various registers which differ by
305 * hardware type, complex enough to have their own function.
306 */
307 if (off == SDHCI_CLOCK_CONTROL) {
308 return (fsl_sdhc_get_clock(sc));
309 }
310
311 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff);
312 }
313
314 static uint32_t
fsl_sdhci_read_4(device_t dev,struct sdhci_slot * slot,bus_size_t off)315 fsl_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
316 {
317 struct fsl_sdhci_softc *sc = device_get_softc(dev);
318 uint32_t val32, wrk32;
319
320 val32 = RD4(sc, off);
321
322 /*
323 * The hardware leaves the base clock frequency out of the capabilities
324 * register, but we filled it in by setting slot->max_clk at attach time
325 * rather than here, because we can't represent frequencies above 63MHz
326 * in an sdhci 2.0 capabliities register. The timeout clock is the same
327 * as the active output sdclock; we indicate that with a quirk setting
328 * so don't populate the timeout frequency bits.
329 *
330 * XXX Turn off (for now) features the hardware can do but this driver
331 * doesn't yet handle (1.8v, suspend/resume, etc).
332 */
333 if (off == SDHCI_CAPABILITIES) {
334 val32 &= ~SDHCI_CAN_VDD_180;
335 val32 &= ~SDHCI_CAN_DO_SUSPEND;
336 val32 |= SDHCI_CAN_DO_8BITBUS;
337 return (val32);
338 }
339
340 /*
341 * The hardware moves bits around in the present state register to make
342 * room for all 8 data line state bits. To translate, mask out all the
343 * bits which are not in the same position in both registers (this also
344 * masks out some Freescale-specific bits in locations defined as
345 * reserved by sdhci), then shift the data line and retune request bits
346 * down to their standard locations.
347 */
348 if (off == SDHCI_PRESENT_STATE) {
349 wrk32 = val32;
350 val32 &= 0x000F0F07;
351 val32 |= (wrk32 >> 4) & SDHCI_STATE_DAT_MASK;
352 val32 |= (wrk32 >> 9) & SDHCI_RETUNE_REQUEST;
353 return (val32);
354 }
355
356 /*
357 * fsl_sdhci_intr() can synthesize a DATA_END interrupt following a
358 * command with an R1B response, mix it into the hardware status.
359 */
360 if (off == SDHCI_INT_STATUS) {
361 return (val32 | sc->r1bfix_intmask);
362 }
363
364 return val32;
365 }
366
367 static void
fsl_sdhci_read_multi_4(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint32_t * data,bus_size_t count)368 fsl_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
369 uint32_t *data, bus_size_t count)
370 {
371 struct fsl_sdhci_softc *sc = device_get_softc(dev);
372
373 bus_read_multi_4(sc->mem_res, off, data, count);
374 }
375
376 static void
fsl_sdhci_write_1(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint8_t val)377 fsl_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val)
378 {
379 struct fsl_sdhci_softc *sc = device_get_softc(dev);
380 uint32_t val32;
381
382 /*
383 * Most of the things in the standard host control register are in the
384 * hardware's wider protocol control register, but some of the bits are
385 * moved around.
386 */
387 if (off == SDHCI_HOST_CONTROL) {
388 val32 = RD4(sc, SDHC_PROT_CTRL);
389 val32 &= ~(SDHC_PROT_LED | SDHC_PROT_DMA_MASK |
390 SDHC_PROT_WIDTH_MASK | SDHC_PROT_CDTL | SDHC_PROT_CDSS);
391 val32 |= (val & SDHCI_CTRL_LED);
392 if (val & SDHCI_CTRL_8BITBUS)
393 val32 |= SDHC_PROT_WIDTH_8BIT;
394 else
395 val32 |= (val & SDHCI_CTRL_4BITBUS);
396 val32 |= (val & (SDHCI_CTRL_SDMA | SDHCI_CTRL_ADMA2)) << 4;
397 val32 |= (val & (SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD));
398 WR4(sc, SDHC_PROT_CTRL, val32);
399 return;
400 }
401
402 /* XXX I can't find the bus power on/off knob; do nothing. */
403 if (off == SDHCI_POWER_CONTROL) {
404 return;
405 }
406 #ifdef __powerpc__
407 /* XXX Reset doesn't seem to work as expected. Do nothing for now. */
408 if (off == SDHCI_SOFTWARE_RESET)
409 return;
410 #endif
411
412 val32 = RD4(sc, off & ~3);
413 val32 &= ~(0xff << (off & 3) * 8);
414 val32 |= (val << (off & 3) * 8);
415
416 WR4(sc, off & ~3, val32);
417 }
418
419 static void
fsl_sdhci_write_2(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint16_t val)420 fsl_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val)
421 {
422 struct fsl_sdhci_softc *sc = device_get_softc(dev);
423 uint32_t val32;
424
425 /*
426 * The clock control stuff is complex enough to have its own function
427 * that can handle the ESDHC versus USDHC differences.
428 */
429 if (off == SDHCI_CLOCK_CONTROL) {
430 fsl_sdhc_set_clock(sc, val);
431 return;
432 }
433
434 /*
435 * Figure out whether we need to check the DAT0 line for busy status at
436 * interrupt time. The controller should be doing this, but for some
437 * reason it doesn't. There are two cases:
438 * - R1B response with no data transfer should generate a DATA_END (aka
439 * TRANSFER_COMPLETE) interrupt after waiting for busy, but if
440 * there's no data transfer there's no DATA_END interrupt. This is
441 * documented; they seem to think it's a feature.
442 * - R1B response after Auto-CMD12 appears to not work, even though
443 * there's a control bit for it (bit 3) in the vendor register.
444 * When we're starting a command that needs a manual DAT0 line check at
445 * interrupt time, we leave ourselves a note in r1bfix_type so that we
446 * can do the extra work in fsl_sdhci_intr().
447 */
448 if (off == SDHCI_COMMAND_FLAGS) {
449 if (val & SDHCI_CMD_DATA) {
450 const uint32_t MBAUTOCMD = SDHCI_TRNS_ACMD12 | SDHCI_TRNS_MULTI;
451 val32 = RD4(sc, USDHC_MIX_CONTROL);
452 if ((val32 & MBAUTOCMD) == MBAUTOCMD)
453 sc->r1bfix_type = R1BFIX_AC12;
454 } else {
455 if ((val & SDHCI_CMD_RESP_MASK) == SDHCI_CMD_RESP_SHORT_BUSY) {
456 WR4(sc, SDHCI_INT_ENABLE, slot->intmask | SDHCI_INT_RESPONSE);
457 WR4(sc, SDHCI_SIGNAL_ENABLE, slot->intmask | SDHCI_INT_RESPONSE);
458 sc->r1bfix_type = R1BFIX_NODATA;
459 }
460 }
461 }
462
463 /*
464 * The USDHC hardware moved the transfer mode bits to mixed control; we
465 * just write them there and we're done. The ESDHC hardware has the
466 * typical combined cmd-and-mode register that allows only 32-bit
467 * access, so when writing the mode bits just save them, then later when
468 * writing the command bits, add in the saved mode bits.
469 */
470 if (sc->hwtype == HWTYPE_USDHC) {
471 if (off == SDHCI_TRANSFER_MODE) {
472 val32 = RD4(sc, USDHC_MIX_CONTROL);
473 val32 &= ~0x3f;
474 val32 |= val & 0x37;
475 // XXX acmd23 not supported here (or by sdhci driver)
476 WR4(sc, USDHC_MIX_CONTROL, val32);
477 return;
478 }
479 } else if (sc->hwtype == HWTYPE_ESDHC) {
480 if (off == SDHCI_TRANSFER_MODE) {
481 sc->cmd_and_mode =
482 (sc->cmd_and_mode & 0xffff0000) | val;
483 return;
484 } else if (off == SDHCI_COMMAND_FLAGS) {
485 sc->cmd_and_mode =
486 (sc->cmd_and_mode & 0xffff) | (val << 16);
487 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode);
488 return;
489 }
490 }
491
492 val32 = RD4(sc, off & ~3);
493 val32 &= ~(0xffff << (off & 3) * 8);
494 val32 |= ((val & 0xffff) << (off & 3) * 8);
495 WR4(sc, off & ~3, val32);
496 }
497
498 static void
fsl_sdhci_write_4(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint32_t val)499 fsl_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val)
500 {
501 struct fsl_sdhci_softc *sc = device_get_softc(dev);
502
503 /* Clear synthesized interrupts, then pass the value to the hardware. */
504 if (off == SDHCI_INT_STATUS) {
505 sc->r1bfix_intmask &= ~val;
506 }
507
508 WR4(sc, off, val);
509 }
510
511 static void
fsl_sdhci_write_multi_4(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint32_t * data,bus_size_t count)512 fsl_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
513 uint32_t *data, bus_size_t count)
514 {
515 struct fsl_sdhci_softc *sc = device_get_softc(dev);
516
517 bus_write_multi_4(sc->mem_res, off, data, count);
518 }
519
520 static uint16_t
fsl_sdhc_get_clock(struct fsl_sdhci_softc * sc)521 fsl_sdhc_get_clock(struct fsl_sdhci_softc *sc)
522 {
523 uint16_t val;
524
525 /*
526 * Whenever the sdhci driver writes the clock register we save a
527 * snapshot of just the frequency bits, so that we can play them back
528 * here on a register read without recalculating the frequency from the
529 * prescalar and divisor bits in the real register. We'll start with
530 * those bits, and mix in the clock status and enable bits that come
531 * from different places depending on which hardware we've got.
532 */
533 val = sc->sdclockreg_freq_bits;
534
535 /*
536 * The internal clock is always enabled (actually, the hardware manages
537 * it). Whether the internal clock is stable yet after a frequency
538 * change comes from the present-state register on both hardware types.
539 */
540 val |= SDHCI_CLOCK_INT_EN;
541 if (RD4(sc, SDHC_PRES_STATE) & SDHC_PRES_SDSTB)
542 val |= SDHCI_CLOCK_INT_STABLE;
543
544 /*
545 * On i.MX ESDHC hardware the card bus clock enable is in the usual
546 * sdhci register but it's a different bit, so transcribe it (note the
547 * difference between standard SDHCI_ and Freescale SDHC_ prefixes
548 * here). On USDHC and QorIQ ESDHC hardware there is a force-on bit, but
549 * no force-off for the card bus clock (the hardware runs the clock when
550 * transfers are active no matter what), so we always say the clock is
551 * on.
552 * XXX Maybe we should say it's in whatever state the sdhci driver last
553 * set it to.
554 */
555 if (sc->hwtype == HWTYPE_ESDHC) {
556 #ifdef __arm__
557 if (RD4(sc, SDHC_SYS_CTRL) & SDHC_CLK_SDCLKEN)
558 #endif
559 val |= SDHCI_CLOCK_CARD_EN;
560 } else {
561 val |= SDHCI_CLOCK_CARD_EN;
562 }
563
564 return (val);
565 }
566
567 static void
fsl_sdhc_set_clock(struct fsl_sdhci_softc * sc,uint16_t val)568 fsl_sdhc_set_clock(struct fsl_sdhci_softc *sc, uint16_t val)
569 {
570 uint32_t divisor, freq, prescale, val32;
571
572 val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
573
574 /*
575 * Save the frequency-setting bits in SDHCI format so that we can play
576 * them back in get_clock without complex decoding of hardware regs,
577 * then deal with the freqency part of the value based on hardware type.
578 */
579 sc->sdclockreg_freq_bits = val & SDHCI_DIVIDERS_MASK;
580 if (sc->hwtype == HWTYPE_ESDHC) {
581 /*
582 * The i.MX5 ESDHC hardware requires the driver to manually
583 * start and stop the sd bus clock. If the enable bit is not
584 * set, turn off the clock in hardware and we're done, otherwise
585 * decode the requested frequency. ESDHC hardware is sdhci 2.0;
586 * the sdhci driver will use the original 8-bit divisor field
587 * and the "base / 2^N" divisor scheme.
588 */
589 if ((val & SDHCI_CLOCK_CARD_EN) == 0) {
590 #ifdef __arm__
591 /* On QorIQ, this is a reserved bit. */
592 WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHC_CLK_SDCLKEN);
593 #endif
594 return;
595 }
596 divisor = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK;
597 freq = sc->baseclk_hz >> ffs(divisor);
598 } else {
599 /*
600 * The USDHC hardware provides only "force always on" control
601 * over the sd bus clock, but no way to turn it off. (If a cmd
602 * or data transfer is in progress the clock is on, otherwise it
603 * is off.) If the clock is being disabled, we can just return
604 * now, otherwise we decode the requested frequency. USDHC
605 * hardware is sdhci 3.0; the sdhci driver will use a 10-bit
606 * divisor using the "base / 2*N" divisor scheme.
607 */
608 if ((val & SDHCI_CLOCK_CARD_EN) == 0)
609 return;
610 divisor = ((val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK) |
611 ((val >> SDHCI_DIVIDER_HI_SHIFT) & SDHCI_DIVIDER_HI_MASK) <<
612 SDHCI_DIVIDER_MASK_LEN;
613 if (divisor == 0)
614 freq = sc->baseclk_hz;
615 else
616 freq = sc->baseclk_hz / (2 * divisor);
617 }
618
619 /*
620 * Get a prescaler and final divisor to achieve the desired frequency.
621 */
622 for (prescale = 2; freq < sc->baseclk_hz / (prescale * 16);)
623 prescale <<= 1;
624
625 for (divisor = 1; freq < sc->baseclk_hz / (prescale * divisor);)
626 ++divisor;
627
628 #ifdef DEBUG
629 device_printf(sc->dev,
630 "desired SD freq: %d, actual: %d; base %d prescale %d divisor %d\n",
631 freq, sc->baseclk_hz / (prescale * divisor), sc->baseclk_hz,
632 prescale, divisor);
633 #endif
634
635 /*
636 * Adjust to zero-based values, and store them to the hardware.
637 */
638 prescale >>= 1;
639 divisor -= 1;
640
641 val32 &= ~(SDHC_CLK_DIVISOR_MASK | SDHC_CLK_PRESCALE_MASK);
642 val32 |= divisor << SDHC_CLK_DIVISOR_SHIFT;
643 val32 |= prescale << SDHC_CLK_PRESCALE_SHIFT;
644 val32 |= SDHC_CLK_IPGEN;
645 WR4(sc, SDHCI_CLOCK_CONTROL, val32);
646 }
647
648 static boolean_t
fsl_sdhci_r1bfix_is_wait_done(struct fsl_sdhci_softc * sc)649 fsl_sdhci_r1bfix_is_wait_done(struct fsl_sdhci_softc *sc)
650 {
651 uint32_t inhibit;
652
653 mtx_assert(&sc->slot.mtx, MA_OWNED);
654
655 /*
656 * Check the DAT0 line status using both the DLA (data line active) and
657 * CDIHB (data inhibit) bits in the present state register. In theory
658 * just DLA should do the trick, but in practice it takes both. If the
659 * DAT0 line is still being held and we're not yet beyond the timeout
660 * point, just schedule another callout to check again later.
661 */
662 inhibit = RD4(sc, SDHC_PRES_STATE) & (SDHC_PRES_DLA | SDHC_PRES_CDIHB);
663
664 if (inhibit && getsbinuptime() < sc->r1bfix_timeout_at) {
665 callout_reset_sbt(&sc->r1bfix_callout, SBT_1MS, 0,
666 fsl_sdhci_r1bfix_func, sc, 0);
667 return (false);
668 }
669
670 /*
671 * If we reach this point with the inhibit bits still set, we've got a
672 * timeout, synthesize a DATA_TIMEOUT interrupt. Otherwise the DAT0
673 * line has been released, and we synthesize a DATA_END, and if the type
674 * of fix needed was on a command-without-data we also now add in the
675 * original INT_RESPONSE that we suppressed earlier.
676 */
677 if (inhibit)
678 sc->r1bfix_intmask |= SDHCI_INT_DATA_TIMEOUT;
679 else {
680 sc->r1bfix_intmask |= SDHCI_INT_DATA_END;
681 if (sc->r1bfix_type == R1BFIX_NODATA)
682 sc->r1bfix_intmask |= SDHCI_INT_RESPONSE;
683 }
684
685 sc->r1bfix_type = R1BFIX_NONE;
686 return (true);
687 }
688
689 static void
fsl_sdhci_r1bfix_func(void * arg)690 fsl_sdhci_r1bfix_func(void * arg)
691 {
692 struct fsl_sdhci_softc *sc = arg;
693 boolean_t r1bwait_done;
694
695 mtx_lock(&sc->slot.mtx);
696 r1bwait_done = fsl_sdhci_r1bfix_is_wait_done(sc);
697 mtx_unlock(&sc->slot.mtx);
698 if (r1bwait_done)
699 sdhci_generic_intr(&sc->slot);
700 }
701
702 static void
fsl_sdhci_intr(void * arg)703 fsl_sdhci_intr(void *arg)
704 {
705 struct fsl_sdhci_softc *sc = arg;
706 uint32_t intmask;
707
708 mtx_lock(&sc->slot.mtx);
709
710 /*
711 * Manually check the DAT0 line for R1B response types that the
712 * controller fails to handle properly. The controller asserts the done
713 * interrupt while the card is still asserting busy with the DAT0 line.
714 *
715 * We check DAT0 immediately because most of the time, especially on a
716 * read, the card will actually be done by time we get here. If it's
717 * not, then the wait_done routine will schedule a callout to re-check
718 * periodically until it is done. In that case we clear the interrupt
719 * out of the hardware now so that we can present it later when the DAT0
720 * line is released.
721 *
722 * If we need to wait for the DAT0 line to be released, we set up a
723 * timeout point 250ms in the future. This number comes from the SD
724 * spec, which allows a command to take that long. In the real world,
725 * cards tend to take 10-20ms for a long-running command such as a write
726 * or erase that spans two pages.
727 */
728 switch (sc->r1bfix_type) {
729 case R1BFIX_NODATA:
730 intmask = RD4(sc, SDHCI_INT_STATUS) & SDHCI_INT_RESPONSE;
731 break;
732 case R1BFIX_AC12:
733 intmask = RD4(sc, SDHCI_INT_STATUS) & SDHCI_INT_DATA_END;
734 break;
735 default:
736 intmask = 0;
737 break;
738 }
739 if (intmask) {
740 sc->r1bfix_timeout_at = getsbinuptime() + 250 * SBT_1MS;
741 if (!fsl_sdhci_r1bfix_is_wait_done(sc)) {
742 WR4(sc, SDHCI_INT_STATUS, intmask);
743 bus_barrier(sc->mem_res, SDHCI_INT_STATUS, 4,
744 BUS_SPACE_BARRIER_WRITE);
745 }
746 }
747
748 mtx_unlock(&sc->slot.mtx);
749 sdhci_generic_intr(&sc->slot);
750 }
751
752 static int
fsl_sdhci_get_ro(device_t bus,device_t child)753 fsl_sdhci_get_ro(device_t bus, device_t child)
754 {
755 struct fsl_sdhci_softc *sc = device_get_softc(bus);
756
757 return (sdhci_fdt_gpio_get_readonly(sc->gpio));
758 }
759
760 static bool
fsl_sdhci_get_card_present(device_t dev,struct sdhci_slot * slot)761 fsl_sdhci_get_card_present(device_t dev, struct sdhci_slot *slot)
762 {
763 struct fsl_sdhci_softc *sc = device_get_softc(dev);
764
765 return (sdhci_fdt_gpio_get_present(sc->gpio));
766 }
767
768 #ifdef __powerpc__
769 static uint32_t
fsl_sdhci_get_platform_clock(device_t dev)770 fsl_sdhci_get_platform_clock(device_t dev)
771 {
772 phandle_t node;
773 uint32_t clock;
774
775 node = ofw_bus_get_node(dev);
776
777 /* Get sdhci node properties */
778 if((OF_getprop(node, "clock-frequency", (void *)&clock,
779 sizeof(clock)) <= 0) || (clock == 0)) {
780 clock = mpc85xx_get_system_clock();
781
782 if (clock == 0) {
783 device_printf(dev,"Cannot acquire correct sdhci "
784 "frequency from DTS.\n");
785
786 return (0);
787 }
788 }
789
790 if (bootverbose)
791 device_printf(dev, "Acquired clock: %d from DTS\n", clock);
792
793 return (clock);
794 }
795 #endif
796
797 static int
fsl_sdhci_detach(device_t dev)798 fsl_sdhci_detach(device_t dev)
799 {
800 struct fsl_sdhci_softc *sc = device_get_softc(dev);
801
802 if (sc->gpio != NULL)
803 sdhci_fdt_gpio_teardown(sc->gpio);
804
805 callout_drain(&sc->r1bfix_callout);
806
807 if (sc->slot_init_done)
808 sdhci_cleanup_slot(&sc->slot);
809
810 if (sc->intr_cookie != NULL)
811 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie);
812 if (sc->irq_res != NULL)
813 bus_release_resource(dev, SYS_RES_IRQ,
814 rman_get_rid(sc->irq_res), sc->irq_res);
815
816 if (sc->mem_res != NULL) {
817 bus_release_resource(dev, SYS_RES_MEMORY,
818 rman_get_rid(sc->mem_res), sc->mem_res);
819 }
820
821 return (0);
822 }
823
824 static int
fsl_sdhci_attach(device_t dev)825 fsl_sdhci_attach(device_t dev)
826 {
827 struct fsl_sdhci_softc *sc = device_get_softc(dev);
828 int rid, err;
829 #ifdef __powerpc__
830 phandle_t node;
831 uint32_t protctl;
832 #endif
833
834 sc->dev = dev;
835
836 callout_init(&sc->r1bfix_callout, 1);
837
838 sc->hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
839 if (sc->hwtype == HWTYPE_NONE)
840 panic("Impossible: not compatible in fsl_sdhci_attach()");
841
842 rid = 0;
843 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
844 RF_ACTIVE);
845 if (!sc->mem_res) {
846 device_printf(dev, "cannot allocate memory window\n");
847 err = ENXIO;
848 goto fail;
849 }
850
851 rid = 0;
852 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
853 RF_ACTIVE);
854 if (!sc->irq_res) {
855 device_printf(dev, "cannot allocate interrupt\n");
856 err = ENXIO;
857 goto fail;
858 }
859
860 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
861 NULL, fsl_sdhci_intr, sc, &sc->intr_cookie)) {
862 device_printf(dev, "cannot setup interrupt handler\n");
863 err = ENXIO;
864 goto fail;
865 }
866
867 sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
868
869 /*
870 * DMA is not really broken, I just haven't implemented it yet.
871 */
872 sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA;
873
874 /*
875 * Set the buffer watermark level to 128 words (512 bytes) for both read
876 * and write. The hardware has a restriction that when the read or
877 * write ready status is asserted, that means you can read exactly the
878 * number of words set in the watermark register before you have to
879 * re-check the status and potentially wait for more data. The main
880 * sdhci driver provides no hook for doing status checking on less than
881 * a full block boundary, so we set the watermark level to be a full
882 * block. Reads and writes where the block size is less than the
883 * watermark size will work correctly too, no need to change the
884 * watermark for different size blocks. However, 128 is the maximum
885 * allowed for the watermark, so PIO is limitted to 512 byte blocks
886 * (which works fine for SD cards, may be a problem for SDIO some day).
887 *
888 * XXX need named constants for this stuff.
889 */
890 /* P1022 has the '*_BRST_LEN' fields as reserved, always reading 0x10 */
891 if (ofw_bus_is_compatible(dev, "fsl,p1022-esdhc"))
892 WR4(sc, SDHC_WTMK_LVL, 0x10801080);
893 else
894 WR4(sc, SDHC_WTMK_LVL, 0x08800880);
895
896 /*
897 * We read in native byte order in the main driver, but the register
898 * defaults to little endian.
899 */
900 #ifdef __powerpc__
901 sc->baseclk_hz = fsl_sdhci_get_platform_clock(dev);
902 #else
903 sc->baseclk_hz = imx_ccm_sdhci_hz();
904 #endif
905 sc->slot.max_clk = sc->baseclk_hz;
906
907 /*
908 * Set up any gpio pin handling described in the FDT data. This cannot
909 * fail; see comments in sdhci_fdt_gpio.h for details.
910 */
911 sc->gpio = sdhci_fdt_gpio_setup(dev, &sc->slot);
912
913 #ifdef __powerpc__
914 node = ofw_bus_get_node(dev);
915 /* Default to big-endian on powerpc */
916 protctl = RD4(sc, SDHC_PROT_CTRL);
917 protctl &= ~SDHC_PROT_EMODE_MASK;
918 if (OF_hasprop(node, "little-endian"))
919 protctl |= SDHC_PROT_EMODE_LITTLE;
920 else
921 protctl |= SDHC_PROT_EMODE_BIG;
922 WR4(sc, SDHC_PROT_CTRL, protctl);
923 #endif
924
925 sdhci_init_slot(dev, &sc->slot, 0);
926 sc->slot_init_done = true;
927
928 bus_generic_probe(dev);
929 bus_generic_attach(dev);
930
931 sdhci_start_slot(&sc->slot);
932
933 return (0);
934
935 fail:
936 fsl_sdhci_detach(dev);
937 return (err);
938 }
939
940 static int
fsl_sdhci_probe(device_t dev)941 fsl_sdhci_probe(device_t dev)
942 {
943
944 if (!ofw_bus_status_okay(dev))
945 return (ENXIO);
946
947 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) {
948 case HWTYPE_ESDHC:
949 device_set_desc(dev, "Freescale eSDHC controller");
950 return (BUS_PROBE_DEFAULT);
951 case HWTYPE_USDHC:
952 device_set_desc(dev, "Freescale uSDHC controller");
953 return (BUS_PROBE_DEFAULT);
954 default:
955 break;
956 }
957 return (ENXIO);
958 }
959
960 static device_method_t fsl_sdhci_methods[] = {
961 /* Device interface */
962 DEVMETHOD(device_probe, fsl_sdhci_probe),
963 DEVMETHOD(device_attach, fsl_sdhci_attach),
964 DEVMETHOD(device_detach, fsl_sdhci_detach),
965
966 /* Bus interface */
967 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
968 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
969
970 /* MMC bridge interface */
971 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
972 DEVMETHOD(mmcbr_request, sdhci_generic_request),
973 DEVMETHOD(mmcbr_get_ro, fsl_sdhci_get_ro),
974 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
975 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
976
977 /* SDHCI accessors */
978 DEVMETHOD(sdhci_read_1, fsl_sdhci_read_1),
979 DEVMETHOD(sdhci_read_2, fsl_sdhci_read_2),
980 DEVMETHOD(sdhci_read_4, fsl_sdhci_read_4),
981 DEVMETHOD(sdhci_read_multi_4, fsl_sdhci_read_multi_4),
982 DEVMETHOD(sdhci_write_1, fsl_sdhci_write_1),
983 DEVMETHOD(sdhci_write_2, fsl_sdhci_write_2),
984 DEVMETHOD(sdhci_write_4, fsl_sdhci_write_4),
985 DEVMETHOD(sdhci_write_multi_4, fsl_sdhci_write_multi_4),
986 DEVMETHOD(sdhci_get_card_present,fsl_sdhci_get_card_present),
987
988 DEVMETHOD_END
989 };
990
991 static driver_t fsl_sdhci_driver = {
992 "sdhci_fsl",
993 fsl_sdhci_methods,
994 sizeof(struct fsl_sdhci_softc),
995 };
996
997 DRIVER_MODULE(sdhci_fsl, simplebus, fsl_sdhci_driver, NULL, NULL);
998 SDHCI_DEPEND(sdhci_fsl);
999
1000 #ifndef MMCCAM
1001 MMC_DECLARE_BRIDGE(sdhci_fsl);
1002 #endif
1003