xref: /freebsd/sys/dev/rtwn/rtl8821a/r21a_reg.h (revision 55141f2c8991b2a6adbf30bb0fe3e6cbc303f06d)
1 /*-
2  * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  */
26 
27 #ifndef R21A_REG_H
28 #define R21A_REG_H
29 
30 #include <dev/rtwn/rtl8812a/r12a_reg.h>
31 
32 /*
33  * MAC registers.
34  */
35 /* Tx DMA Configuration. */
36 #define R21A_DWBCN0_CTRL		R92C_TDECTRL
37 #define R21A_DWBCN1_CTRL		0x228
38 
39 /* Bits for R92C_MAC_PHY_CTRL. */
40 #define R21A_MAC_PHY_CRYSTALCAP_M	0x00fff000
41 #define R21A_MAC_PHY_CRYSTALCAP_S	12
42 
43 /* Bits for R21A_DWBCN1_CTRL. */
44 #define R21A_DWBCN1_CTRL_SEL_EN		0x00020000
45 #define R21A_DWBCN1_CTRL_SEL_BCN1	0x00100000
46 
47 #endif	/* R21A_REG_H */
48