1 /*- 2 * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_wlan.h" 31 32 #include <sys/param.h> 33 #include <sys/lock.h> 34 #include <sys/mutex.h> 35 #include <sys/mbuf.h> 36 #include <sys/kernel.h> 37 #include <sys/socket.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/queue.h> 41 #include <sys/taskqueue.h> 42 #include <sys/bus.h> 43 #include <sys/endian.h> 44 #include <sys/linker.h> 45 46 #include <net/if.h> 47 #include <net/ethernet.h> 48 #include <net/if_media.h> 49 50 #include <net80211/ieee80211_var.h> 51 #include <net80211/ieee80211_radiotap.h> 52 53 #include <dev/rtwn/if_rtwnreg.h> 54 #include <dev/rtwn/if_rtwnvar.h> 55 56 #include <dev/rtwn/if_rtwn_debug.h> 57 58 #include <dev/rtwn/rtl8192c/r92c.h> 59 60 #include <dev/rtwn/rtl8812a/r12a.h> 61 #include <dev/rtwn/rtl8812a/r12a_priv.h> 62 #include <dev/rtwn/rtl8812a/r12a_reg.h> 63 #include <dev/rtwn/rtl8812a/r12a_var.h> 64 65 66 int 67 r12a_check_condition(struct rtwn_softc *sc, const uint8_t cond[]) 68 { 69 struct r12a_softc *rs = sc->sc_priv; 70 uint8_t mask[4]; 71 int i, j, nmasks; 72 73 RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, 74 "%s: condition byte 0: %02X; ext PA/LNA: %d/%d (2 GHz), " 75 "%d/%d (5 GHz)\n", __func__, cond[0], rs->ext_pa_2g, 76 rs->ext_lna_2g, rs->ext_pa_5g, rs->ext_lna_5g); 77 78 if (cond[0] == 0) 79 return (1); 80 81 if (!rs->ext_pa_2g && !rs->ext_lna_2g && 82 !rs->ext_pa_5g && !rs->ext_lna_5g) 83 return (0); 84 85 nmasks = 0; 86 if (rs->ext_pa_2g) { 87 mask[nmasks] = R12A_COND_GPA; 88 mask[nmasks] |= R12A_COND_TYPE(rs->type_pa_2g); 89 nmasks++; 90 } 91 if (rs->ext_pa_5g) { 92 mask[nmasks] = R12A_COND_APA; 93 mask[nmasks] |= R12A_COND_TYPE(rs->type_pa_5g); 94 nmasks++; 95 } 96 if (rs->ext_lna_2g) { 97 mask[nmasks] = R12A_COND_GLNA; 98 mask[nmasks] |= R12A_COND_TYPE(rs->type_lna_2g); 99 nmasks++; 100 } 101 if (rs->ext_lna_5g) { 102 mask[nmasks] = R12A_COND_ALNA; 103 mask[nmasks] |= R12A_COND_TYPE(rs->type_lna_5g); 104 nmasks++; 105 } 106 107 for (i = 0; i < RTWN_MAX_CONDITIONS && cond[i] != 0; i++) 108 for (j = 0; j < nmasks; j++) 109 if ((cond[i] & mask[j]) == mask[j]) 110 return (1); 111 112 return (0); 113 } 114 115 int 116 r12a_set_page_size(struct rtwn_softc *sc) 117 { 118 return (rtwn_setbits_1(sc, R92C_PBP, R92C_PBP_PSTX_M, 119 R92C_PBP_512 << R92C_PBP_PSTX_S) == 0); 120 } 121 122 void 123 r12a_init_edca(struct rtwn_softc *sc) 124 { 125 r92c_init_edca(sc); 126 127 /* 80 MHz clock */ 128 rtwn_write_1(sc, R92C_USTIME_TSF, 0x50); 129 rtwn_write_1(sc, R92C_USTIME_EDCA, 0x50); 130 } 131 132 void 133 r12a_init_bb(struct rtwn_softc *sc) 134 { 135 int i, j; 136 137 rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, 0, R92C_SYS_FUNC_EN_USBA); 138 139 /* Enable BB and RF. */ 140 rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, 0, 141 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST); 142 143 /* PathA RF Power On. */ 144 rtwn_write_1(sc, R92C_RF_CTRL, 145 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 146 147 /* PathB RF Power On. */ 148 rtwn_write_1(sc, R12A_RF_B_CTRL, 149 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 150 151 /* Write BB initialization values. */ 152 for (i = 0; i < sc->bb_size; i++) { 153 const struct rtwn_bb_prog *bb_prog = &sc->bb_prog[i]; 154 155 while (!rtwn_check_condition(sc, bb_prog->cond)) { 156 KASSERT(bb_prog->next != NULL, 157 ("%s: wrong condition value (i %d)\n", 158 __func__, i)); 159 bb_prog = bb_prog->next; 160 } 161 162 for (j = 0; j < bb_prog->count; j++) { 163 RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, 164 "BB: reg 0x%03x, val 0x%08x\n", 165 bb_prog->reg[j], bb_prog->val[j]); 166 167 rtwn_bb_write(sc, bb_prog->reg[j], bb_prog->val[j]); 168 rtwn_delay(sc, 1); 169 } 170 } 171 172 /* XXX meshpoint mode? */ 173 174 /* Write AGC values. */ 175 for (i = 0; i < sc->agc_size; i++) { 176 const struct rtwn_agc_prog *agc_prog = &sc->agc_prog[i]; 177 178 while (!rtwn_check_condition(sc, agc_prog->cond)) { 179 KASSERT(agc_prog->next != NULL, 180 ("%s: wrong condition value (2) (i %d)\n", 181 __func__, i)); 182 agc_prog = agc_prog->next; 183 } 184 185 for (j = 0; j < agc_prog->count; j++) { 186 RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, 187 "AGC: val 0x%08x\n", agc_prog->val[j]); 188 189 rtwn_bb_write(sc, 0x81c, agc_prog->val[j]); 190 rtwn_delay(sc, 1); 191 } 192 } 193 194 for (i = 0; i < sc->nrxchains; i++) { 195 rtwn_bb_write(sc, R12A_INITIAL_GAIN(i), 0x22); 196 rtwn_delay(sc, 1); 197 rtwn_bb_write(sc, R12A_INITIAL_GAIN(i), 0x20); 198 rtwn_delay(sc, 1); 199 } 200 201 rtwn_r12a_crystalcap_write(sc); 202 203 if (rtwn_bb_read(sc, R12A_CCK_RPT_FORMAT) & R12A_CCK_RPT_FORMAT_HIPWR) 204 sc->sc_flags |= RTWN_FLAG_CCK_HIPWR; 205 } 206 207 void 208 r12a_init_rf(struct rtwn_softc *sc) 209 { 210 int chain, i; 211 212 for (chain = 0, i = 0; chain < sc->nrxchains; chain++, i++) { 213 /* Write RF initialization values for this chain. */ 214 i += r92c_init_rf_chain(sc, &sc->rf_prog[i], chain); 215 } 216 } 217 218 void 219 r12a_crystalcap_write(struct rtwn_softc *sc) 220 { 221 struct r12a_softc *rs = sc->sc_priv; 222 uint32_t reg; 223 uint8_t val; 224 225 val = rs->crystalcap & 0x3f; 226 reg = rtwn_bb_read(sc, R92C_MAC_PHY_CTRL); 227 reg = RW(reg, R12A_MAC_PHY_CRYSTALCAP, val | (val << 6)); 228 rtwn_bb_write(sc, R92C_MAC_PHY_CTRL, reg); 229 } 230 231 static void 232 r12a_rf_init_workaround(struct rtwn_softc *sc) 233 { 234 235 rtwn_write_1(sc, R92C_RF_CTRL, 236 R92C_RF_CTRL_EN | R92C_RF_CTRL_SDMRSTB); 237 rtwn_write_1(sc, R92C_RF_CTRL, 238 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | 239 R92C_RF_CTRL_SDMRSTB); 240 rtwn_write_1(sc, R12A_RF_B_CTRL, 241 R92C_RF_CTRL_EN | R92C_RF_CTRL_SDMRSTB); 242 rtwn_write_1(sc, R12A_RF_B_CTRL, 243 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | 244 R92C_RF_CTRL_SDMRSTB); 245 } 246 247 int 248 r12a_power_on(struct rtwn_softc *sc) 249 { 250 #define RTWN_CHK(res) do { \ 251 if (res != 0) \ 252 return (EIO); \ 253 } while(0) 254 int ntries; 255 256 r12a_rf_init_workaround(sc); 257 258 /* Force PWM mode. */ 259 RTWN_CHK(rtwn_setbits_1(sc, R92C_SPS0_CTRL + 1, 0, 0x01)); 260 261 /* Turn off ZCD. */ 262 RTWN_CHK(rtwn_setbits_2(sc, 0x014, 0x0180, 0)); 263 264 /* Enable LDO normal mode. */ 265 RTWN_CHK(rtwn_setbits_1(sc, R92C_LPLDO_CTRL, R92C_LPLDO_CTRL_SLEEP, 266 0)); 267 268 /* GPIO 0...7 input mode. */ 269 RTWN_CHK(rtwn_write_1(sc, R92C_GPIO_IOSEL, 0)); 270 271 /* GPIO 11...8 input mode. */ 272 RTWN_CHK(rtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 0)); 273 274 /* Enable WL suspend. */ 275 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 276 R92C_APS_FSMCO_AFSM_HSUS, 0, 1)); 277 278 /* Enable 8051. */ 279 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN, 280 0, R92C_SYS_FUNC_EN_CPUEN, 1)); 281 282 /* Disable SW LPS. */ 283 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 284 R92C_APS_FSMCO_APFM_RSM, 0, 1)); 285 286 /* Wait for power ready bit. */ 287 for (ntries = 0; ntries < 5000; ntries++) { 288 if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 289 break; 290 rtwn_delay(sc, 10); 291 } 292 if (ntries == 5000) { 293 device_printf(sc->sc_dev, 294 "timeout waiting for chip power up\n"); 295 return (ETIMEDOUT); 296 } 297 298 /* Disable WL suspend. */ 299 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 300 R92C_APS_FSMCO_AFSM_HSUS, 0, 1)); 301 302 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, 303 R92C_APS_FSMCO_APFM_ONMAC, 1)); 304 for (ntries = 0; ntries < 5000; ntries++) { 305 if (!(rtwn_read_2(sc, R92C_APS_FSMCO) & 306 R92C_APS_FSMCO_APFM_ONMAC)) 307 break; 308 rtwn_delay(sc, 10); 309 } 310 if (ntries == 5000) 311 return (ETIMEDOUT); 312 313 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 314 RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0x0000)); 315 RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0, 316 R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN | 317 R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN | 318 R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN | 319 ((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) | 320 R92C_CR_CALTMR_EN)); 321 322 return (0); 323 } 324 325 void 326 r12a_power_off(struct rtwn_softc *sc) 327 { 328 struct r12a_softc *rs = sc->sc_priv; 329 int error, ntries; 330 331 /* Stop Rx. */ 332 error = rtwn_write_1(sc, R92C_CR, 0); 333 if (error == ENXIO) /* hardware gone */ 334 return; 335 336 /* Move card to Low Power state. */ 337 /* Block all Tx queues. */ 338 rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 339 340 for (ntries = 0; ntries < 10; ntries++) { 341 /* Should be zero if no packet is transmitting. */ 342 if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0) 343 break; 344 345 rtwn_delay(sc, 5000); 346 } 347 if (ntries == 10) { 348 device_printf(sc->sc_dev, "%s: failed to block Tx queues\n", 349 __func__); 350 return; 351 } 352 353 /* Turn off 3-wire. */ 354 rtwn_write_1(sc, R12A_HSSI_PARAM1(0), 0x04); 355 rtwn_write_1(sc, R12A_HSSI_PARAM1(1), 0x04); 356 357 /* CCK and OFDM are disabled, and clock are gated. */ 358 rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0); 359 360 rtwn_delay(sc, 1); 361 362 /* Reset whole BB. */ 363 rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0); 364 365 /* Reset MAC TRX. */ 366 rtwn_write_1(sc, R92C_CR, 367 R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN); 368 369 /* check if removed later. (?) */ 370 rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1); 371 372 /* Respond TxOK to scheduler */ 373 rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, R92C_DUAL_TSF_RST_TXOK); 374 375 /* If firmware in ram code, do reset. */ 376 #ifndef RTWN_WITHOUT_UCODE 377 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 378 r12a_fw_reset(sc, RTWN_FW_RESET_SHUTDOWN); 379 #endif 380 381 /* Reset MCU. */ 382 rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_CPUEN, 383 0, 1); 384 rtwn_write_1(sc, R92C_MCUFWDL, 0); 385 386 /* Move card to Disabled state. */ 387 /* Turn off 3-wire. */ 388 rtwn_write_1(sc, R12A_HSSI_PARAM1(0), 0x04); 389 rtwn_write_1(sc, R12A_HSSI_PARAM1(1), 0x04); 390 391 /* Reset BB, close RF. */ 392 rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0); 393 394 rtwn_delay(sc, 1); 395 396 /* SPS PWM mode. */ 397 rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0xff, 398 R92C_APS_FSMCO_SOP_RCK | R92C_APS_FSMCO_SOP_ABG, 3); 399 400 /* ANA clock = 500k. */ 401 rtwn_setbits_1(sc, R92C_SYS_CLKR, R92C_SYS_CLKR_ANA8M, 0); 402 403 /* Turn off MAC by HW state machine */ 404 rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_APFM_OFF, 405 1); 406 for (ntries = 0; ntries < 10; ntries++) { 407 /* Wait until it will be disabled. */ 408 if ((rtwn_read_2(sc, R92C_APS_FSMCO) & 409 R92C_APS_FSMCO_APFM_OFF) == 0) 410 break; 411 412 rtwn_delay(sc, 5000); 413 } 414 if (ntries == 10) { 415 device_printf(sc->sc_dev, "%s: could not turn off MAC\n", 416 __func__); 417 return; 418 } 419 420 /* Reset 8051. */ 421 rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_CPUEN, 422 0, 1); 423 424 /* Fill the default value of host_CPU handshake field. */ 425 rtwn_write_1(sc, R92C_MCUFWDL, 426 R92C_MCUFWDL_EN | R92C_MCUFWDL_CHKSUM_RPT); 427 428 rtwn_setbits_1(sc, R92C_GPIO_IO_SEL, 0xf0, 0xc0); 429 430 /* GPIO 11 input mode, 10...8 output mode. */ 431 rtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 0x07); 432 433 /* GPIO 7...0, output = input */ 434 rtwn_write_1(sc, R92C_GPIO_OUT, 0); 435 436 /* GPIO 7...0 output mode. */ 437 rtwn_write_1(sc, R92C_GPIO_IOSEL, 0xff); 438 439 rtwn_write_1(sc, R92C_GPIO_MOD, 0); 440 441 /* Turn on ZCD. */ 442 rtwn_setbits_2(sc, 0x014, 0, 0x0180); 443 444 /* Force PFM mode. */ 445 rtwn_setbits_1(sc, R92C_SPS0_CTRL + 1, 0x01, 0); 446 447 /* LDO sleep mode. */ 448 rtwn_setbits_1(sc, R92C_LPLDO_CTRL, 0, R92C_LPLDO_CTRL_SLEEP); 449 450 /* ANA clock = 500k. */ 451 rtwn_setbits_1(sc, R92C_SYS_CLKR, R92C_SYS_CLKR_ANA8M, 0); 452 453 /* SOP option to disable BG/MB. */ 454 rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0xff, 455 R92C_APS_FSMCO_SOP_RCK, 3); 456 457 /* Disable RFC_0. */ 458 rtwn_setbits_1(sc, R92C_RF_CTRL, R92C_RF_CTRL_RSTB, 0); 459 460 /* Disable RFC_1. */ 461 rtwn_setbits_1(sc, R12A_RF_B_CTRL, R92C_RF_CTRL_RSTB, 0); 462 463 /* Enable WL suspend. */ 464 rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_AFSM_HSUS, 465 1); 466 467 rs->rs_flags &= ~R12A_IQK_RUNNING; 468 } 469 470 void 471 r12a_init_intr(struct rtwn_softc *sc) 472 { 473 rtwn_write_4(sc, R88E_HIMR, 0); 474 rtwn_write_4(sc, R88E_HIMRE, 0); 475 } 476 477 void 478 r12a_init_antsel(struct rtwn_softc *sc) 479 { 480 uint32_t reg; 481 482 rtwn_write_1(sc, R92C_LEDCFG2, 0x82); 483 rtwn_bb_setbits(sc, R92C_FPGA0_RFPARAM(0), 0, 0x2000); 484 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0)); 485 sc->sc_ant = MS(reg, R92C_FPGA0_RFIFACEOE0_ANT); 486 } 487