1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * Copyright (c) 2012 Stefan Sperling <stsp@openbsd.org> 6 * Copyright (c) 2020 Henri Hennebert <hlh@restart.be> 7 * Copyright (c) 2020 Gary Jennejohn <gj@freebsd.org> 8 * Copyright (c) 2020 Jesper Schmitz Mouridsen <jsm@FreeBSD.org> 9 * All rights reserved. 10 * 11 * Patch from: 12 * - Lutz Bichler <Lutz.Bichler@gmail.com> 13 * 14 * Base on OpenBSD /sys/dev/pci/rtsx_pci.c & /dev/ic/rtsx.c 15 * on Linux /drivers/mmc/host/rtsx_pci_sdmmc.c, 16 * /include/linux/rtsx_pci.h & 17 * /drivers/misc/cardreader/rtsx_pcr.c 18 * on NetBSD /sys/dev/ic/rtsx.c 19 * 20 * Permission to use, copy, modify, and distribute this software for any 21 * purpose with or without fee is hereby granted, provided that the above 22 * copyright notice and this permission notice appear in all copies. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 #include <sys/param.h> 41 #include <sys/module.h> 42 #include <sys/systm.h> /* For FreeBSD 11 */ 43 #include <sys/types.h> /* For FreeBSD 11 */ 44 #include <sys/errno.h> 45 #include <sys/kernel.h> 46 #include <sys/bus.h> 47 #include <sys/endian.h> 48 #include <machine/bus.h> 49 #include <sys/mutex.h> 50 #include <sys/malloc.h> 51 #include <sys/rman.h> 52 #include <sys/queue.h> 53 #include <sys/taskqueue.h> 54 #include <sys/sysctl.h> 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/mmc/bridge.h> 58 #include <dev/mmc/mmcreg.h> 59 #include <dev/mmc/mmcbrvar.h> 60 #include <machine/_inttypes.h> 61 62 #include "opt_mmccam.h" 63 64 #ifdef MMCCAM 65 #include <cam/cam.h> 66 #include <cam/cam_ccb.h> 67 #include <cam/cam_debug.h> 68 #include <cam/cam_sim.h> 69 #include <cam/cam_xpt_sim.h> 70 #include <cam/mmc/mmc_sim.h> 71 #include "mmc_sim_if.h" 72 #endif /* MMCCAM */ 73 74 #include "rtsxreg.h" 75 76 /* The softc holds our per-instance data. */ 77 struct rtsx_softc { 78 struct mtx rtsx_mtx; /* device mutex */ 79 device_t rtsx_dev; /* device */ 80 uint16_t rtsx_flags; /* device flags */ 81 uint16_t rtsx_device_id; /* device ID */ 82 device_t rtsx_mmc_dev; /* device of mmc bus */ 83 uint32_t rtsx_intr_enabled; /* enabled interrupts */ 84 uint32_t rtsx_intr_status; /* soft interrupt status */ 85 int rtsx_irq_res_id; /* bus IRQ resource id */ 86 struct resource *rtsx_irq_res; /* bus IRQ resource */ 87 void *rtsx_irq_cookie; /* bus IRQ resource cookie */ 88 struct callout rtsx_timeout_callout; /* callout for timeout */ 89 int rtsx_timeout_cmd; /* interrupt timeout for setup commands */ 90 int rtsx_timeout_io; /* interrupt timeout for I/O commands */ 91 void (*rtsx_intr_trans_ok)(struct rtsx_softc *sc); 92 /* function to call if transfer succeed */ 93 void (*rtsx_intr_trans_ko)(struct rtsx_softc *sc); 94 /* function to call if transfer fail */ 95 96 struct timeout_task 97 rtsx_card_insert_task; /* card insert delayed task */ 98 struct task rtsx_card_remove_task; /* card remove task */ 99 100 int rtsx_res_id; /* bus memory resource id */ 101 struct resource *rtsx_res; /* bus memory resource */ 102 int rtsx_res_type; /* bus memory resource type */ 103 bus_space_tag_t rtsx_btag; /* host register set tag */ 104 bus_space_handle_t rtsx_bhandle; /* host register set handle */ 105 106 bus_dma_tag_t rtsx_cmd_dma_tag; /* DMA tag for command transfer */ 107 bus_dmamap_t rtsx_cmd_dmamap; /* DMA map for command transfer */ 108 void *rtsx_cmd_dmamem; /* DMA mem for command transfer */ 109 bus_addr_t rtsx_cmd_buffer; /* device visible address of the DMA segment */ 110 int rtsx_cmd_index; /* index in rtsx_cmd_buffer */ 111 112 bus_dma_tag_t rtsx_data_dma_tag; /* DMA tag for data transfer */ 113 bus_dmamap_t rtsx_data_dmamap; /* DMA map for data transfer */ 114 void *rtsx_data_dmamem; /* DMA mem for data transfer */ 115 bus_addr_t rtsx_data_buffer; /* device visible address of the DMA segment */ 116 117 #ifdef MMCCAM 118 union ccb *rtsx_ccb; /* CAM control block */ 119 struct mmc_sim rtsx_mmc_sim; /* CAM generic sim */ 120 struct mmc_request rtsx_cam_req; /* CAM MMC request */ 121 #endif /* MMCCAM */ 122 123 struct mmc_request *rtsx_req; /* MMC request */ 124 struct mmc_host rtsx_host; /* host parameters */ 125 int rtsx_pcie_cap; /* PCIe capability offset */ 126 int8_t rtsx_bus_busy; /* bus busy status */ 127 int8_t rtsx_ios_bus_width; /* current host.ios.bus_width */ 128 int32_t rtsx_ios_clock; /* current host.ios.clock */ 129 int8_t rtsx_ios_power_mode; /* current host.ios.power mode */ 130 int8_t rtsx_ios_timing; /* current host.ios.timing */ 131 int8_t rtsx_ios_vccq; /* current host.ios.vccq */ 132 uint8_t rtsx_read_only; /* card read only status */ 133 uint8_t rtsx_inversion; /* inversion of card detection and read only status */ 134 uint8_t rtsx_force_timing; /* force bus_timing_uhs_sdr50 */ 135 uint8_t rtsx_debug; /* print debugging */ 136 #ifdef MMCCAM 137 uint8_t rtsx_cam_status; /* CAM status - 1 if card in use */ 138 #endif /* MMCCAM */ 139 uint64_t rtsx_read_count; /* count of read operations */ 140 uint64_t rtsx_write_count; /* count of write operations */ 141 bool rtsx_discovery_mode; /* are we in discovery mode? */ 142 bool rtsx_tuning_mode; /* are we tuning */ 143 bool rtsx_double_clk; /* double clock freqency */ 144 bool rtsx_vpclk; /* voltage at Pulse-width Modulation(PWM) clock? */ 145 uint8_t rtsx_ssc_depth; /* Spread spectrum clocking depth */ 146 uint8_t rtsx_card_drive_sel; /* value for RTSX_CARD_DRIVE_SEL */ 147 uint8_t rtsx_sd30_drive_sel_3v3;/* value for RTSX_SD30_DRIVE_SEL */ 148 }; 149 150 /* rtsx_flags values */ 151 #define RTSX_F_DEFAULT 0x0000 152 #define RTSX_F_CARD_PRESENT 0x0001 153 #define RTSX_F_SDIO_SUPPORT 0x0002 154 #define RTSX_F_VERSION_A 0x0004 155 #define RTSX_F_VERSION_B 0x0008 156 #define RTSX_F_VERSION_C 0x0010 157 #define RTSX_F_VERSION_D 0x0020 158 #define RTSX_F_8411B_QFN48 0x0040 159 #define RTSX_F_REVERSE_SOCKET 0x0080 160 161 #define RTSX_REALTEK 0x10ec 162 #define RTSX_RTS5209 0x5209 163 #define RTSX_RTS5227 0x5227 164 #define RTSX_RTS5229 0x5229 165 #define RTSX_RTS522A 0x522a 166 #define RTSX_RTS525A 0x525a 167 #define RTSX_RTS5249 0x5249 168 #define RTSX_RTL8402 0x5286 169 #define RTSX_RTL8411 0x5289 170 #define RTSX_RTL8411B 0x5287 171 172 #define RTSX_VERSION "2.1c" 173 174 static const struct rtsx_device { 175 uint16_t vendor_id; 176 uint16_t device_id; 177 const char *desc; 178 } rtsx_devices[] = { 179 { RTSX_REALTEK, RTSX_RTS5209, RTSX_VERSION " Realtek RTS5209 PCIe MMC/SD Card Reader"}, 180 { RTSX_REALTEK, RTSX_RTS5227, RTSX_VERSION " Realtek RTS5227 PCIe MMC/SD Card Reader"}, 181 { RTSX_REALTEK, RTSX_RTS5229, RTSX_VERSION " Realtek RTS5229 PCIe MMC/SD Card Reader"}, 182 { RTSX_REALTEK, RTSX_RTS522A, RTSX_VERSION " Realtek RTS522A PCIe MMC/SD Card Reader"}, 183 { RTSX_REALTEK, RTSX_RTS525A, RTSX_VERSION " Realtek RTS525A PCIe MMC/SD Card Reader"}, 184 { RTSX_REALTEK, RTSX_RTS5249, RTSX_VERSION " Realtek RTS5249 PCIe MMC/SD Card Reader"}, 185 { RTSX_REALTEK, RTSX_RTL8402, RTSX_VERSION " Realtek RTL8402 PCIe MMC/SD Card Reader"}, 186 { RTSX_REALTEK, RTSX_RTL8411, RTSX_VERSION " Realtek RTL8411 PCIe MMC/SD Card Reader"}, 187 { RTSX_REALTEK, RTSX_RTL8411B, RTSX_VERSION " Realtek RTL8411B PCIe MMC/SD Card Reader"}, 188 { 0, 0, NULL} 189 }; 190 191 /* See `kenv | grep smbios.system` */ 192 static const struct rtsx_inversion_model { 193 char *maker; 194 char *family; 195 char *product; 196 } rtsx_inversion_models[] = { 197 { "LENOVO", "ThinkPad T470p", "20J7S0PM00"}, 198 { NULL, NULL, NULL} 199 }; 200 201 static int rtsx_dma_alloc(struct rtsx_softc *sc); 202 static void rtsx_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 203 static void rtsx_dma_free(struct rtsx_softc *sc); 204 static void rtsx_intr(void *arg); 205 static void rtsx_handle_card_present(struct rtsx_softc *sc); 206 static void rtsx_card_task(void *arg, int pending __unused); 207 static bool rtsx_is_card_present(struct rtsx_softc *sc); 208 static int rtsx_init(struct rtsx_softc *sc); 209 static int rtsx_map_sd_drive(int index); 210 static int rtsx_rts5227_fill_driving(struct rtsx_softc *sc); 211 static int rtsx_rts5249_fill_driving(struct rtsx_softc *sc); 212 static int rtsx_read(struct rtsx_softc *, uint16_t, uint8_t *); 213 static int rtsx_read_cfg(struct rtsx_softc *sc, uint8_t func, uint16_t addr, uint32_t *val); 214 static int rtsx_write(struct rtsx_softc *sc, uint16_t addr, uint8_t mask, uint8_t val); 215 static int rtsx_read_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t *val); 216 static int rtsx_write_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t val); 217 static int rtsx_bus_power_off(struct rtsx_softc *sc); 218 static int rtsx_bus_power_on(struct rtsx_softc *sc); 219 static int rtsx_set_bus_width(struct rtsx_softc *sc, enum mmc_bus_width width); 220 static int rtsx_set_sd_timing(struct rtsx_softc *sc, enum mmc_bus_timing timing); 221 static int rtsx_set_sd_clock(struct rtsx_softc *sc, uint32_t freq); 222 static int rtsx_stop_sd_clock(struct rtsx_softc *sc); 223 static int rtsx_switch_sd_clock(struct rtsx_softc *sc, uint8_t clk, uint8_t n, uint8_t div, uint8_t mcu); 224 #ifndef MMCCAM 225 static void rtsx_sd_change_tx_phase(struct rtsx_softc *sc, uint8_t sample_point); 226 static void rtsx_sd_change_rx_phase(struct rtsx_softc *sc, uint8_t sample_point); 227 static void rtsx_sd_tuning_rx_phase(struct rtsx_softc *sc, uint32_t *phase_map); 228 static int rtsx_sd_tuning_rx_cmd(struct rtsx_softc *sc, uint8_t sample_point); 229 static int rtsx_sd_tuning_rx_cmd_wait(struct rtsx_softc *sc, struct mmc_command *cmd); 230 static void rtsx_sd_tuning_rx_cmd_wakeup(struct rtsx_softc *sc); 231 static void rtsx_sd_wait_data_idle(struct rtsx_softc *sc); 232 static uint8_t rtsx_sd_search_final_rx_phase(struct rtsx_softc *sc, uint32_t phase_map); 233 static int rtsx_sd_get_rx_phase_len(uint32_t phase_map, int start_bit); 234 #endif /* !MMCCAM */ 235 #if 0 /* For led */ 236 static int rtsx_led_enable(struct rtsx_softc *sc); 237 static int rtsx_led_disable(struct rtsx_softc *sc); 238 #endif /* For led */ 239 static uint8_t rtsx_response_type(uint16_t mmc_rsp); 240 static void rtsx_init_cmd(struct rtsx_softc *sc, struct mmc_command *cmd); 241 static void rtsx_push_cmd(struct rtsx_softc *sc, uint8_t cmd, uint16_t reg, 242 uint8_t mask, uint8_t data); 243 static void rtsx_set_cmd_data_len(struct rtsx_softc *sc, uint16_t block_cnt, uint16_t byte_cnt); 244 static void rtsx_send_cmd(struct rtsx_softc *sc); 245 static void rtsx_ret_resp(struct rtsx_softc *sc); 246 static void rtsx_set_resp(struct rtsx_softc *sc, struct mmc_command *cmd); 247 static void rtsx_stop_cmd(struct rtsx_softc *sc); 248 static void rtsx_clear_error(struct rtsx_softc *sc); 249 static void rtsx_req_done(struct rtsx_softc *sc); 250 static int rtsx_send_req(struct rtsx_softc *sc, struct mmc_command *cmd); 251 static int rtsx_xfer_short(struct rtsx_softc *sc, struct mmc_command *cmd); 252 static void rtsx_ask_ppbuf_part1(struct rtsx_softc *sc); 253 static void rtsx_get_ppbuf_part1(struct rtsx_softc *sc); 254 static void rtsx_get_ppbuf_part2(struct rtsx_softc *sc); 255 static void rtsx_put_ppbuf_part1(struct rtsx_softc *sc); 256 static void rtsx_put_ppbuf_part2(struct rtsx_softc *sc); 257 static void rtsx_write_ppbuf(struct rtsx_softc *sc); 258 static int rtsx_xfer(struct rtsx_softc *sc, struct mmc_command *cmd); 259 static void rtsx_xfer_begin(struct rtsx_softc *sc); 260 static void rtsx_xfer_start(struct rtsx_softc *sc); 261 static void rtsx_xfer_finish(struct rtsx_softc *sc); 262 static void rtsx_timeout(void *arg); 263 264 #ifdef MMCCAM 265 static int rtsx_get_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts); 266 static int rtsx_set_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts); 267 static int rtsx_cam_request(device_t dev, union ccb *ccb); 268 #endif /* MMCCAM */ 269 270 static int rtsx_read_ivar(device_t bus, device_t child, int which, uintptr_t *result); 271 static int rtsx_write_ivar(device_t bus, device_t child, int which, uintptr_t value); 272 273 static int rtsx_mmcbr_update_ios(device_t bus, device_t child __unused); 274 static int rtsx_mmcbr_switch_vccq(device_t bus, device_t child __unused); 275 static int rtsx_mmcbr_request(device_t bus, device_t child __unused, struct mmc_request *req); 276 #ifndef MMCCAM 277 static int rtsx_mmcbr_tune(device_t bus, device_t child __unused, bool hs400 __unused); 278 static int rtsx_mmcbr_retune(device_t bus, device_t child __unused, bool reset __unused); 279 static int rtsx_mmcbr_get_ro(device_t bus, device_t child __unused); 280 static int rtsx_mmcbr_acquire_host(device_t bus, device_t child __unused); 281 static int rtsx_mmcbr_release_host(device_t bus, device_t child __unused); 282 #endif /* !MMCCAM */ 283 284 static int rtsx_probe(device_t dev); 285 static int rtsx_attach(device_t dev); 286 static int rtsx_detach(device_t dev); 287 static int rtsx_shutdown(device_t dev); 288 static int rtsx_suspend(device_t dev); 289 static int rtsx_resume(device_t dev); 290 291 #define RTSX_LOCK_INIT(_sc) mtx_init(&(_sc)->rtsx_mtx, \ 292 device_get_nameunit(sc->rtsx_dev), "rtsx", MTX_DEF) 293 #define RTSX_LOCK(_sc) mtx_lock(&(_sc)->rtsx_mtx) 294 #define RTSX_UNLOCK(_sc) mtx_unlock(&(_sc)->rtsx_mtx) 295 #define RTSX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rtsx_mtx) 296 297 #define RTSX_SDCLK_OFF 0 298 #define RTSX_SDCLK_250KHZ 250000 299 #define RTSX_SDCLK_400KHZ 400000 300 #define RTSX_SDCLK_25MHZ 25000000 301 #define RTSX_SDCLK_50MHZ 50000000 302 #define RTSX_SDCLK_100MHZ 100000000 303 #define RTSX_SDCLK_208MHZ 208000000 304 305 #define RTSX_MIN_DIV_N 80 306 #define RTSX_MAX_DIV_N 208 307 308 #define RTSX_MAX_DATA_BLKLEN 512 309 310 #define RTSX_DMA_ALIGN 4 311 #define RTSX_HOSTCMD_MAX 256 312 #define RTSX_DMA_CMD_BIFSIZE (sizeof(uint32_t) * RTSX_HOSTCMD_MAX) 313 #define RTSX_DMA_DATA_BUFSIZE MAXPHYS 314 315 #define ISSET(t, f) ((t) & (f)) 316 317 #define READ4(sc, reg) \ 318 (bus_space_read_4((sc)->rtsx_btag, (sc)->rtsx_bhandle, (reg))) 319 #define WRITE4(sc, reg, val) \ 320 (bus_space_write_4((sc)->rtsx_btag, (sc)->rtsx_bhandle, (reg), (val))) 321 322 #define RTSX_READ(sc, reg, val) \ 323 do { \ 324 int err = rtsx_read((sc), (reg), (val)); \ 325 if (err) \ 326 return (err); \ 327 } while (0) 328 329 #define RTSX_WRITE(sc, reg, val) \ 330 do { \ 331 int err = rtsx_write((sc), (reg), 0xff, (val)); \ 332 if (err) \ 333 return (err); \ 334 } while (0) 335 #define RTSX_CLR(sc, reg, bits) \ 336 do { \ 337 int err = rtsx_write((sc), (reg), (bits), 0); \ 338 if (err) \ 339 return (err); \ 340 } while (0) 341 342 #define RTSX_SET(sc, reg, bits) \ 343 do { \ 344 int err = rtsx_write((sc), (reg), (bits), 0xff);\ 345 if (err) \ 346 return (err); \ 347 } while (0) 348 349 #define RTSX_BITOP(sc, reg, mask, bits) \ 350 do { \ 351 int err = rtsx_write((sc), (reg), (mask), (bits)); \ 352 if (err) \ 353 return (err); \ 354 } while (0) 355 356 /* 357 * We use two DMA buffers: a command buffer and a data buffer. 358 * 359 * The command buffer contains a command queue for the host controller, 360 * which describes SD/MMC commands to run, and other parameters. The chip 361 * runs the command queue when a special bit in the RTSX_HCBAR register is 362 * set and signals completion with the RTSX_TRANS_OK_INT interrupt. 363 * Each command is encoded as a 4 byte sequence containing command number 364 * (read, write, or check a host controller register), a register address, 365 * and a data bit-mask and value. 366 * SD/MMC commands which do not transfer any data from/to the card only use 367 * the command buffer. 368 * 369 * The data buffer is used for transfer longer than 512. Data transfer is 370 * controlled via the RTSX_HDBAR register and completion is signalled by 371 * the RTSX_TRANS_OK_INT interrupt. 372 * 373 * The chip is unable to perform DMA above 4GB. 374 */ 375 376 /* 377 * Main commands in the usual seqence used: 378 * 379 * CMD0 Go idle state 380 * CMD8 Send interface condition 381 * CMD55 Application Command for next ACMD 382 * ACMD41 Send Operation Conditions Register (OCR: voltage profile of the card) 383 * CMD2 Send Card Identification (CID) Register 384 * CMD3 Send relative address 385 * CMD9 Send Card Specific Data (CSD) 386 * CMD13 Send status (32 bits - bit 25: card password protected) 387 * CMD7 Select card (before Get card SCR) 388 * ACMD51 Send SCR (SD CARD Configuration Register - [51:48]: Bus widths supported) 389 * CMD6 SD switch function 390 * ACMD13 Send SD status (512 bits) 391 * ACMD42 Set/Clear card detect 392 * ACMD6 Set bus width 393 * CMD19 Send tuning block 394 * CMD12 Stop transmission 395 * 396 * CMD17 Read single block (<=512) 397 * CMD18 Read multiple blocks (>512) 398 * CMD24 Write single block (<=512) 399 * CMD25 Write multiple blocks (>512) 400 * 401 * CMD52 IO R/W direct 402 * CMD5 Send Operation Conditions 403 */ 404 405 static int 406 rtsx_dma_alloc(struct rtsx_softc *sc) 407 { 408 int error = 0; 409 410 error = bus_dma_tag_create(bus_get_dma_tag(sc->rtsx_dev), /* inherit from parent */ 411 RTSX_DMA_ALIGN, 0, /* alignment, boundary */ 412 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 413 BUS_SPACE_MAXADDR, /* highaddr */ 414 NULL, NULL, /* filter, filterarg */ 415 RTSX_DMA_CMD_BIFSIZE, 1, /* maxsize, nsegments */ 416 RTSX_DMA_CMD_BIFSIZE, /* maxsegsize */ 417 0, /* flags */ 418 NULL, NULL, /* lockfunc, lockarg */ 419 &sc->rtsx_cmd_dma_tag); 420 if (error) { 421 device_printf(sc->rtsx_dev, 422 "Can't create cmd parent DMA tag\n"); 423 return (error); 424 } 425 error = bus_dmamem_alloc(sc->rtsx_cmd_dma_tag, /* DMA tag */ 426 &sc->rtsx_cmd_dmamem, /* will hold the KVA pointer */ 427 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, /* flags */ 428 &sc->rtsx_cmd_dmamap); /* DMA map */ 429 if (error) { 430 device_printf(sc->rtsx_dev, 431 "Can't create DMA map for command transfer\n"); 432 goto destroy_cmd_dma_tag; 433 434 } 435 error = bus_dmamap_load(sc->rtsx_cmd_dma_tag, /* DMA tag */ 436 sc->rtsx_cmd_dmamap, /* DMA map */ 437 sc->rtsx_cmd_dmamem, /* KVA pointer to be mapped */ 438 RTSX_DMA_CMD_BIFSIZE, /* size of buffer */ 439 rtsx_dmamap_cb, /* callback */ 440 &sc->rtsx_cmd_buffer, /* first arg of callback */ 441 0); /* flags */ 442 if (error || sc->rtsx_cmd_buffer == 0) { 443 device_printf(sc->rtsx_dev, 444 "Can't load DMA memory for command transfer\n"); 445 error = (error) ? error : EFAULT; 446 goto destroy_cmd_dmamem_alloc; 447 } 448 449 error = bus_dma_tag_create(bus_get_dma_tag(sc->rtsx_dev), /* inherit from parent */ 450 RTSX_DMA_DATA_BUFSIZE, 0, /* alignment, boundary */ 451 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 452 BUS_SPACE_MAXADDR, /* highaddr */ 453 NULL, NULL, /* filter, filterarg */ 454 RTSX_DMA_DATA_BUFSIZE, 1, /* maxsize, nsegments */ 455 RTSX_DMA_DATA_BUFSIZE, /* maxsegsize */ 456 0, /* flags */ 457 NULL, NULL, /* lockfunc, lockarg */ 458 &sc->rtsx_data_dma_tag); 459 if (error) { 460 device_printf(sc->rtsx_dev, 461 "Can't create data parent DMA tag\n"); 462 goto destroy_cmd_dmamap_load; 463 } 464 error = bus_dmamem_alloc(sc->rtsx_data_dma_tag, /* DMA tag */ 465 &sc->rtsx_data_dmamem, /* will hold the KVA pointer */ 466 BUS_DMA_WAITOK | BUS_DMA_ZERO, /* flags */ 467 &sc->rtsx_data_dmamap); /* DMA map */ 468 if (error) { 469 device_printf(sc->rtsx_dev, 470 "Can't create DMA map for data transfer\n"); 471 goto destroy_data_dma_tag; 472 } 473 error = bus_dmamap_load(sc->rtsx_data_dma_tag, /* DMA tag */ 474 sc->rtsx_data_dmamap, /* DMA map */ 475 sc->rtsx_data_dmamem, /* KVA pointer to be mapped */ 476 RTSX_DMA_DATA_BUFSIZE, /* size of buffer */ 477 rtsx_dmamap_cb, /* callback */ 478 &sc->rtsx_data_buffer, /* first arg of callback */ 479 0); /* flags */ 480 if (error || sc->rtsx_data_buffer == 0) { 481 device_printf(sc->rtsx_dev, 482 "Can't load DMA memory for data transfer\n"); 483 error = (error) ? error : EFAULT; 484 goto destroy_data_dmamem_alloc; 485 } 486 return (error); 487 488 destroy_data_dmamem_alloc: 489 bus_dmamem_free(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamem, sc->rtsx_data_dmamap); 490 destroy_data_dma_tag: 491 bus_dma_tag_destroy(sc->rtsx_data_dma_tag); 492 destroy_cmd_dmamap_load: 493 bus_dmamap_unload(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap); 494 destroy_cmd_dmamem_alloc: 495 bus_dmamem_free(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamem, sc->rtsx_cmd_dmamap); 496 destroy_cmd_dma_tag: 497 bus_dma_tag_destroy(sc->rtsx_cmd_dma_tag); 498 499 return (error); 500 } 501 502 static void 503 rtsx_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 504 { 505 if (error) { 506 printf("rtsx_dmamap_cb: error %d\n", error); 507 return; 508 } 509 *(bus_addr_t *)arg = segs[0].ds_addr; 510 } 511 512 static void 513 rtsx_dma_free(struct rtsx_softc *sc) 514 { 515 if (sc->rtsx_cmd_dma_tag != NULL) { 516 if (sc->rtsx_cmd_dmamap != NULL) 517 bus_dmamap_unload(sc->rtsx_cmd_dma_tag, 518 sc->rtsx_cmd_dmamap); 519 if (sc->rtsx_cmd_dmamem != NULL) 520 bus_dmamem_free(sc->rtsx_cmd_dma_tag, 521 sc->rtsx_cmd_dmamem, 522 sc->rtsx_cmd_dmamap); 523 sc->rtsx_cmd_dmamap = NULL; 524 sc->rtsx_cmd_dmamem = NULL; 525 sc->rtsx_cmd_buffer = 0; 526 bus_dma_tag_destroy(sc->rtsx_cmd_dma_tag); 527 sc->rtsx_cmd_dma_tag = NULL; 528 } 529 if (sc->rtsx_data_dma_tag != NULL) { 530 if (sc->rtsx_data_dmamap != NULL) 531 bus_dmamap_unload(sc->rtsx_data_dma_tag, 532 sc->rtsx_data_dmamap); 533 if (sc->rtsx_data_dmamem != NULL) 534 bus_dmamem_free(sc->rtsx_data_dma_tag, 535 sc->rtsx_data_dmamem, 536 sc->rtsx_data_dmamap); 537 sc->rtsx_data_dmamap = NULL; 538 sc->rtsx_data_dmamem = NULL; 539 sc->rtsx_data_buffer = 0; 540 bus_dma_tag_destroy(sc->rtsx_data_dma_tag); 541 sc->rtsx_data_dma_tag = NULL; 542 } 543 } 544 545 static void 546 rtsx_intr(void *arg) 547 { 548 struct rtsx_softc *sc = arg; 549 uint32_t enabled; 550 uint32_t status; 551 552 RTSX_LOCK(sc); 553 554 enabled = sc->rtsx_intr_enabled; 555 status = READ4(sc, RTSX_BIPR); /* read Bus Interrupt Pending Register */ 556 sc->rtsx_intr_status = status; 557 558 if (bootverbose) 559 device_printf(sc->rtsx_dev, "Interrupt handler - enabled: 0x%08x, status: 0x%08x\n", enabled, status); 560 561 /* Ack interrupts. */ 562 WRITE4(sc, RTSX_BIPR, status); 563 564 if (((enabled & status) == 0) || status == 0xffffffff) { 565 device_printf(sc->rtsx_dev, "Spurious interrupt - enabled: 0x%08x, status: 0x%08x\n", enabled, status); 566 RTSX_UNLOCK(sc); 567 return; 568 } 569 570 /* Detect write protect. */ 571 if (status & RTSX_SD_WRITE_PROTECT) 572 sc->rtsx_read_only = 1; 573 else 574 sc->rtsx_read_only = 0; 575 576 /* Start task to handle SD card status change (from dwmmc.c). */ 577 if (status & RTSX_SD_INT) { 578 device_printf(sc->rtsx_dev, "Interrupt card inserted/removed\n"); 579 rtsx_handle_card_present(sc); 580 } 581 582 if (sc->rtsx_req == NULL) { 583 RTSX_UNLOCK(sc); 584 return; 585 } 586 587 if (status & RTSX_TRANS_OK_INT) { 588 sc->rtsx_req->cmd->error = MMC_ERR_NONE; 589 if (sc->rtsx_intr_trans_ok != NULL) 590 sc->rtsx_intr_trans_ok(sc); 591 } else if (status & RTSX_TRANS_FAIL_INT) { 592 uint8_t stat1; 593 sc->rtsx_req->cmd->error = MMC_ERR_FAILED; 594 if (rtsx_read(sc, RTSX_SD_STAT1, &stat1) == 0 && 595 (stat1 & RTSX_SD_CRC_ERR)) { 596 device_printf(sc->rtsx_dev, "CRC error\n"); 597 sc->rtsx_req->cmd->error = MMC_ERR_BADCRC; 598 } 599 if (!sc->rtsx_tuning_mode) 600 device_printf(sc->rtsx_dev, "Transfer fail - status: 0x%08x\n", status); 601 rtsx_stop_cmd(sc); 602 if (sc->rtsx_intr_trans_ko != NULL) 603 sc->rtsx_intr_trans_ko(sc); 604 } 605 606 RTSX_UNLOCK(sc); 607 } 608 609 /* 610 * Function called from the IRQ handler (from dwmmc.c). 611 */ 612 static void 613 rtsx_handle_card_present(struct rtsx_softc *sc) 614 { 615 bool was_present; 616 bool is_present; 617 618 #ifdef MMCCAM 619 was_present = sc->rtsx_cam_status; 620 #else /* !MMCCAM */ 621 was_present = sc->rtsx_mmc_dev != NULL; 622 #endif /* MMCCAM */ 623 is_present = rtsx_is_card_present(sc); 624 if (is_present) 625 device_printf(sc->rtsx_dev, "Card present\n"); 626 else 627 device_printf(sc->rtsx_dev, "Card absent\n"); 628 629 if (!was_present && is_present) { 630 /* 631 * The delay is to debounce the card insert 632 * (sometimes the card detect pin stabilizes 633 * before the other pins have made good contact). 634 */ 635 taskqueue_enqueue_timeout(taskqueue_swi_giant, 636 &sc->rtsx_card_insert_task, -hz); 637 } else if (was_present && !is_present) { 638 taskqueue_enqueue(taskqueue_swi_giant, &sc->rtsx_card_remove_task); 639 } 640 } 641 642 /* 643 * This function is called at startup. 644 */ 645 static void 646 rtsx_card_task(void *arg, int pending __unused) 647 { 648 struct rtsx_softc *sc = arg; 649 650 if (rtsx_is_card_present(sc)) { 651 sc->rtsx_flags |= RTSX_F_CARD_PRESENT; 652 /* Card is present, attach if necessary. */ 653 #ifdef MMCCAM 654 if (sc->rtsx_cam_status == 0) { 655 #else /* !MMCCAM */ 656 if (sc->rtsx_mmc_dev == NULL) { 657 #endif /* MMCCAM */ 658 if (bootverbose) 659 device_printf(sc->rtsx_dev, "Card inserted\n"); 660 661 sc->rtsx_read_count = sc->rtsx_write_count = 0; 662 #ifdef MMCCAM 663 sc->rtsx_cam_status = 1; 664 mmc_cam_sim_discover(&sc->rtsx_mmc_sim); 665 #else /* !MMCCAM */ 666 RTSX_LOCK(sc); 667 sc->rtsx_mmc_dev = device_add_child(sc->rtsx_dev, "mmc", -1); 668 RTSX_UNLOCK(sc); 669 if (sc->rtsx_mmc_dev == NULL) { 670 device_printf(sc->rtsx_dev, "Adding MMC bus failed\n"); 671 } else { 672 device_set_ivars(sc->rtsx_mmc_dev, sc); 673 device_probe_and_attach(sc->rtsx_mmc_dev); 674 } 675 #endif /* MMCCAM */ 676 } 677 } else { 678 sc->rtsx_flags &= ~RTSX_F_CARD_PRESENT; 679 /* Card isn't present, detach if necessary. */ 680 #ifdef MMCCAM 681 if (sc->rtsx_cam_status != 0) { 682 #else /* !MMCCAM */ 683 if (sc->rtsx_mmc_dev != NULL) { 684 #endif /* MMCCAM */ 685 if (bootverbose) 686 device_printf(sc->rtsx_dev, "Card removed\n"); 687 688 if (sc->rtsx_debug) 689 device_printf(sc->rtsx_dev, "Read count: %" PRIu64 ", write count: %" PRIu64 "\n", 690 sc->rtsx_read_count, sc->rtsx_write_count); 691 #ifdef MMCCAM 692 sc->rtsx_cam_status = 0; 693 mmc_cam_sim_discover(&sc->rtsx_mmc_sim); 694 #else /* !MMCCAM */ 695 if (device_delete_child(sc->rtsx_dev, sc->rtsx_mmc_dev)) 696 device_printf(sc->rtsx_dev, "Detaching MMC bus failed\n"); 697 sc->rtsx_mmc_dev = NULL; 698 #endif /* MMCCAM */ 699 } 700 } 701 } 702 703 static bool 704 rtsx_is_card_present(struct rtsx_softc *sc) 705 { 706 uint32_t status; 707 708 status = READ4(sc, RTSX_BIPR); 709 if (sc->rtsx_inversion == 0) 710 return (status & RTSX_SD_EXIST); 711 else 712 return !(status & RTSX_SD_EXIST); 713 } 714 715 static int 716 rtsx_init(struct rtsx_softc *sc) 717 { 718 bool rtsx_init_debug = false; 719 uint8_t version; 720 uint8_t val; 721 int error; 722 723 sc->rtsx_host.host_ocr = RTSX_SUPPORTED_VOLTAGE; 724 sc->rtsx_host.f_min = RTSX_SDCLK_250KHZ; 725 sc->rtsx_host.f_max = RTSX_SDCLK_208MHZ; 726 sc->rtsx_host.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_HSPEED | 727 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 728 729 sc->rtsx_host.caps |= MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104; 730 if (sc->rtsx_device_id == RTSX_RTS5209) 731 sc->rtsx_host.caps |= MMC_CAP_8_BIT_DATA; 732 pci_find_cap(sc->rtsx_dev, PCIY_EXPRESS, &(sc->rtsx_pcie_cap)); 733 734 /* 735 * Check IC version. 736 */ 737 switch (sc->rtsx_device_id) { 738 case RTSX_RTS5229: 739 /* Read IC version from dummy register. */ 740 RTSX_READ(sc, RTSX_DUMMY_REG, &version); 741 if ((version & 0x0F) == RTSX_IC_VERSION_C) 742 sc->rtsx_flags |= RTSX_F_VERSION_C; 743 break; 744 case RTSX_RTS522A: 745 /* Read IC version from dummy register. */ 746 RTSX_READ(sc, RTSX_DUMMY_REG, &version); 747 if ((version & 0x0F) == RTSX_IC_VERSION_A) 748 sc->rtsx_flags |= RTSX_F_VERSION_A; 749 break; 750 case RTSX_RTS525A: 751 /* Read IC version from dummy register. */ 752 RTSX_READ(sc, RTSX_DUMMY_REG, &version); 753 if ((version & 0x0F) == RTSX_IC_VERSION_A) 754 sc->rtsx_flags |= RTSX_F_VERSION_A; 755 break; 756 case RTSX_RTL8411B: 757 RTSX_READ(sc, RTSX_RTL8411B_PACKAGE, &version); 758 if (version & RTSX_RTL8411B_QFN48) 759 sc->rtsx_flags |= RTSX_F_8411B_QFN48; 760 break; 761 } 762 763 /* 764 * Fetch vendor settings. 765 */ 766 /* 767 * Normally OEMs will set vendor setting to the config space 768 * of Realtek card reader in BIOS stage. This statement reads 769 * the setting and configure the internal registers according 770 * to it, to improve card reader's compatibility condition. 771 */ 772 sc->rtsx_card_drive_sel = RTSX_CARD_DRIVE_DEFAULT; 773 switch (sc->rtsx_device_id) { 774 uint32_t reg; 775 uint32_t reg1; 776 uint8_t reg3; 777 case RTSX_RTS5209: 778 sc->rtsx_card_drive_sel = RTSX_RTS5209_CARD_DRIVE_DEFAULT; 779 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D; 780 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4); 781 if (!(reg & 0x80)) { 782 sc->rtsx_card_drive_sel = (reg >> 8) & 0x3F; 783 sc->rtsx_sd30_drive_sel_3v3 = reg & 0x07; 784 } else if (bootverbose || rtsx_init_debug) { 785 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 786 } 787 if (bootverbose || rtsx_init_debug) 788 device_printf(sc->rtsx_dev, "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n", 789 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3); 790 break; 791 case RTSX_RTS5227: 792 case RTSX_RTS522A: 793 sc->rtsx_sd30_drive_sel_3v3 = RTSX_CFG_DRIVER_TYPE_B; 794 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 795 if (!(reg & 0x1000000)) { 796 sc->rtsx_card_drive_sel &= 0x3F; 797 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6; 798 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4); 799 sc->rtsx_sd30_drive_sel_3v3 = (reg >> 5) & 0x03; 800 if (reg & 0x4000) 801 sc->rtsx_flags |= RTSX_F_REVERSE_SOCKET; 802 } else if (bootverbose || rtsx_init_debug) { 803 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 804 } 805 if (bootverbose || rtsx_init_debug) 806 device_printf(sc->rtsx_dev, 807 "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x, reverse_socket is %s\n", 808 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3, 809 (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) ? "true" : "false"); 810 break; 811 case RTSX_RTS5229: 812 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D; 813 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 814 if (!(reg & 0x1000000)) { 815 sc->rtsx_card_drive_sel &= 0x3F; 816 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6; 817 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4); 818 sc->rtsx_sd30_drive_sel_3v3 = rtsx_map_sd_drive((reg >> 5) & 0x03); 819 } else if (bootverbose || rtsx_init_debug) { 820 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 821 } 822 if (bootverbose || rtsx_init_debug) 823 device_printf(sc->rtsx_dev, "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n", 824 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3); 825 break; 826 case RTSX_RTS525A: 827 case RTSX_RTS5249: 828 sc->rtsx_sd30_drive_sel_3v3 = RTSX_CFG_DRIVER_TYPE_B; 829 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 830 if ((reg & 0x1000000)) { 831 sc->rtsx_card_drive_sel &= 0x3F; 832 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6; 833 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4); 834 sc->rtsx_sd30_drive_sel_3v3 = (reg >> 5) & 0x03; 835 if (reg & 0x4000) 836 sc->rtsx_flags |= RTSX_F_REVERSE_SOCKET; 837 } else if (bootverbose || rtsx_init_debug) { 838 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 839 } 840 if (bootverbose || rtsx_init_debug) 841 device_printf(sc->rtsx_dev, 842 "card_drive_sel = 0x%02x, sd30_drive_sel_3v3: 0x%02x, reverse_socket is %s\n", 843 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3, 844 (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) ? "true" : "false"); 845 break; 846 case RTSX_RTL8402: 847 case RTSX_RTL8411: 848 sc->rtsx_card_drive_sel = RTSX_RTL8411_CARD_DRIVE_DEFAULT; 849 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D; 850 reg1 = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 851 if (reg1 & 0x1000000) { 852 sc->rtsx_card_drive_sel &= 0x3F; 853 sc->rtsx_card_drive_sel |= ((reg1 >> 25) & 0x01) << 6; 854 reg3 = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG3, 1); 855 sc->rtsx_sd30_drive_sel_3v3 = (reg3 >> 5) & 0x07; 856 } else if (bootverbose || rtsx_init_debug) { 857 device_printf(sc->rtsx_dev, "pci_read_config() error - reg1: 0x%08x\n", reg1); 858 } 859 if (bootverbose || rtsx_init_debug) 860 device_printf(sc->rtsx_dev, 861 "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n", 862 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3); 863 break; 864 case RTSX_RTL8411B: 865 sc->rtsx_card_drive_sel = RTSX_RTL8411_CARD_DRIVE_DEFAULT; 866 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D; 867 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 868 if (!(reg & 0x1000000)) { 869 sc->rtsx_sd30_drive_sel_3v3 = rtsx_map_sd_drive(reg & 0x03); 870 } else if (bootverbose || rtsx_init_debug) { 871 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 872 } 873 if (bootverbose || rtsx_init_debug) 874 device_printf(sc->rtsx_dev, 875 "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n", 876 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3); 877 break; 878 } 879 880 if (bootverbose || rtsx_init_debug) 881 device_printf(sc->rtsx_dev, "rtsx_init() rtsx_flags: 0x%04x\n", sc->rtsx_flags); 882 883 /* Enable interrupts. */ 884 sc->rtsx_intr_enabled = RTSX_TRANS_OK_INT_EN | RTSX_TRANS_FAIL_INT_EN | RTSX_SD_INT_EN | RTSX_MS_INT_EN; 885 WRITE4(sc, RTSX_BIER, sc->rtsx_intr_enabled); 886 887 /* Power on SSC clock. */ 888 RTSX_CLR(sc, RTSX_FPDCTL, RTSX_SSC_POWER_DOWN); 889 /* Wait SSC power stable. */ 890 DELAY(200); 891 892 /* Disable ASPM */ 893 val = pci_read_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_LINK_CTL, 1); 894 pci_write_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_LINK_CTL, val & 0xfc, 1); 895 896 /* 897 * Optimize phy. 898 */ 899 switch (sc->rtsx_device_id) { 900 case RTSX_RTS5209: 901 /* Some magic numbers from Linux driver. */ 902 if ((error = rtsx_write_phy(sc, 0x00, 0xB966))) 903 return (error); 904 break; 905 case RTSX_RTS5227: 906 RTSX_CLR(sc, RTSX_PM_CTRL3, RTSX_D3_DELINK_MODE_EN); 907 908 /* Optimize RX sensitivity. */ 909 if ((error = rtsx_write_phy(sc, 0x00, 0xBA42))) 910 return (error); 911 break; 912 case RTSX_RTS5229: 913 /* Optimize RX sensitivity. */ 914 if ((error = rtsx_write_phy(sc, 0x00, 0xBA42))) 915 return (error); 916 break; 917 case RTSX_RTS522A: 918 RTSX_CLR(sc, RTSX_RTS522A_PM_CTRL3, RTSX_D3_DELINK_MODE_EN); 919 if (sc->rtsx_flags & RTSX_F_VERSION_A) { 920 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR2, RTSX_PHY_RCR2_INIT_27S))) 921 return (error); 922 } 923 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR1, RTSX_PHY_RCR1_INIT_27S))) 924 return (error); 925 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD0, RTSX_PHY_FLD0_INIT_27S))) 926 return (error); 927 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD3, RTSX_PHY_FLD3_INIT_27S))) 928 return (error); 929 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD4, RTSX_PHY_FLD4_INIT_27S))) 930 return (error); 931 break; 932 case RTSX_RTS525A: 933 if ((error = rtsx_write_phy(sc, RTSX__PHY_FLD0, 934 RTSX__PHY_FLD0_CLK_REQ_20C | RTSX__PHY_FLD0_RX_IDLE_EN | 935 RTSX__PHY_FLD0_BIT_ERR_RSTN | RTSX__PHY_FLD0_BER_COUNT | 936 RTSX__PHY_FLD0_BER_TIMER | RTSX__PHY_FLD0_CHECK_EN))) 937 return (error); 938 if ((error = rtsx_write_phy(sc, RTSX__PHY_ANA03, 939 RTSX__PHY_ANA03_TIMER_MAX | RTSX__PHY_ANA03_OOBS_DEB_EN | 940 RTSX__PHY_CMU_DEBUG_EN))) 941 return (error); 942 if (sc->rtsx_flags & RTSX_F_VERSION_A) 943 if ((error = rtsx_write_phy(sc, RTSX__PHY_REV0, 944 RTSX__PHY_REV0_FILTER_OUT | RTSX__PHY_REV0_CDR_BYPASS_PFD | 945 RTSX__PHY_REV0_CDR_RX_IDLE_BYPASS))) 946 return (error); 947 break; 948 case RTSX_RTS5249: 949 RTSX_CLR(sc, RTSX_PM_CTRL3, RTSX_D3_DELINK_MODE_EN); 950 if ((error = rtsx_write_phy(sc, RTSX_PHY_REV, 951 RTSX_PHY_REV_RESV | RTSX_PHY_REV_RXIDLE_LATCHED | 952 RTSX_PHY_REV_P1_EN | RTSX_PHY_REV_RXIDLE_EN | 953 RTSX_PHY_REV_CLKREQ_TX_EN | RTSX_PHY_REV_RX_PWST | 954 RTSX_PHY_REV_CLKREQ_DT_1_0 | RTSX_PHY_REV_STOP_CLKRD | 955 RTSX_PHY_REV_STOP_CLKWR))) 956 return (error); 957 DELAY(1000); 958 if ((error = rtsx_write_phy(sc, RTSX_PHY_BPCR, 959 RTSX_PHY_BPCR_IBRXSEL | RTSX_PHY_BPCR_IBTXSEL | 960 RTSX_PHY_BPCR_IB_FILTER | RTSX_PHY_BPCR_CMIRROR_EN))) 961 return (error); 962 if ((error = rtsx_write_phy(sc, RTSX_PHY_PCR, 963 RTSX_PHY_PCR_FORCE_CODE | RTSX_PHY_PCR_OOBS_CALI_50 | 964 RTSX_PHY_PCR_OOBS_VCM_08 | RTSX_PHY_PCR_OOBS_SEN_90 | 965 RTSX_PHY_PCR_RSSI_EN | RTSX_PHY_PCR_RX10K))) 966 return (error); 967 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR2, 968 RTSX_PHY_RCR2_EMPHASE_EN | RTSX_PHY_RCR2_NADJR | 969 RTSX_PHY_RCR2_CDR_SR_2 | RTSX_PHY_RCR2_FREQSEL_12 | 970 RTSX_PHY_RCR2_CDR_SC_12P | RTSX_PHY_RCR2_CALIB_LATE))) 971 return (error); 972 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD4, 973 RTSX_PHY_FLD4_FLDEN_SEL | RTSX_PHY_FLD4_REQ_REF | 974 RTSX_PHY_FLD4_RXAMP_OFF | RTSX_PHY_FLD4_REQ_ADDA | 975 RTSX_PHY_FLD4_BER_COUNT | RTSX_PHY_FLD4_BER_TIMER | 976 RTSX_PHY_FLD4_BER_CHK_EN))) 977 return (error); 978 if ((error = rtsx_write_phy(sc, RTSX_PHY_RDR, 979 RTSX_PHY_RDR_RXDSEL_1_9 | RTSX_PHY_SSC_AUTO_PWD))) 980 return (error); 981 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR1, 982 RTSX_PHY_RCR1_ADP_TIME_4 | RTSX_PHY_RCR1_VCO_COARSE))) 983 return (error); 984 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD3, 985 RTSX_PHY_FLD3_TIMER_4 | RTSX_PHY_FLD3_TIMER_6 | 986 RTSX_PHY_FLD3_RXDELINK))) 987 return (error); 988 if ((error = rtsx_write_phy(sc, RTSX_PHY_TUNE, 989 RTSX_PHY_TUNE_TUNEREF_1_0 | RTSX_PHY_TUNE_VBGSEL_1252 | 990 RTSX_PHY_TUNE_SDBUS_33 | RTSX_PHY_TUNE_TUNED18 | 991 RTSX_PHY_TUNE_TUNED12 | RTSX_PHY_TUNE_TUNEA12))) 992 return (error); 993 break; 994 } 995 996 /* Set mcu_cnt to 7 to ensure data can be sampled properly. */ 997 RTSX_BITOP(sc, RTSX_CLK_DIV, 0x07, 0x07); 998 999 /* Disable sleep mode. */ 1000 RTSX_CLR(sc, RTSX_HOST_SLEEP_STATE, 1001 RTSX_HOST_ENTER_S1 | RTSX_HOST_ENTER_S3); 1002 1003 /* Disable card clock. */ 1004 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL); 1005 1006 /* Reset delink mode. */ 1007 RTSX_CLR(sc, RTSX_CHANGE_LINK_STATE, 1008 RTSX_FORCE_RST_CORE_EN | RTSX_NON_STICKY_RST_N_DBG); 1009 1010 /* Card driving select. */ 1011 RTSX_WRITE(sc, RTSX_CARD_DRIVE_SEL, sc->rtsx_card_drive_sel); 1012 1013 /* Enable SSC clock. */ 1014 RTSX_WRITE(sc, RTSX_SSC_CTL1, RTSX_SSC_8X_EN | RTSX_SSC_SEL_4M); 1015 RTSX_WRITE(sc, RTSX_SSC_CTL2, 0x12); 1016 1017 /* Disable cd_pwr_save. */ 1018 RTSX_BITOP(sc, RTSX_CHANGE_LINK_STATE, 0x16, RTSX_MAC_PHY_RST_N_DBG); 1019 1020 /* Clear Link Ready Interrupt. */ 1021 RTSX_BITOP(sc, RTSX_IRQSTAT0, RTSX_LINK_READY_INT, RTSX_LINK_READY_INT); 1022 1023 /* Enlarge the estimation window of PERST# glitch 1024 * to reduce the chance of invalid card interrupt. */ 1025 RTSX_WRITE(sc, RTSX_PERST_GLITCH_WIDTH, 0x80); 1026 1027 /* Set RC oscillator to 400K. */ 1028 RTSX_CLR(sc, RTSX_RCCTL, RTSX_RCCTL_F_2M); 1029 1030 /* Enable interrupt write-clear (default is read-clear). */ 1031 RTSX_CLR(sc, RTSX_NFTS_TX_CTRL, RTSX_INT_READ_CLR); 1032 1033 if (sc->rtsx_device_id == RTSX_RTS525A) 1034 RTSX_BITOP(sc, RTSX_PM_CLK_FORCE_CTL, 1, 1); 1035 1036 /* OC power down. */ 1037 RTSX_BITOP(sc, RTSX_FPDCTL, RTSX_SD_OC_POWER_DOWN, RTSX_SD_OC_POWER_DOWN); 1038 1039 /* Enable clk_request_n to enable clock power management */ 1040 pci_write_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_LINK_CTL + 1, 1, 1); 1041 1042 /* Enter L1 when host tx idle */ 1043 pci_write_config(sc->rtsx_dev, 0x70F, 0x5B, 1); 1044 1045 /* 1046 * Specific extra init. 1047 */ 1048 switch (sc->rtsx_device_id) { 1049 uint16_t cap; 1050 case RTSX_RTS5209: 1051 /* Turn off LED. */ 1052 RTSX_WRITE(sc, RTSX_CARD_GPIO, 0x03); 1053 /* Reset ASPM state to default value. */ 1054 RTSX_CLR(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK); 1055 /* Force CLKREQ# PIN to drive 0 to request clock. */ 1056 RTSX_BITOP(sc, RTSX_PETXCFG, 0x08, 0x08); 1057 /* Configure GPIO as output. */ 1058 RTSX_WRITE(sc, RTSX_CARD_GPIO_DIR, 0x03); 1059 /* Configure driving. */ 1060 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3); 1061 break; 1062 case RTSX_RTS5227: 1063 /* Configure GPIO as output. */ 1064 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1065 /* Reset ASPM state to default value. */ 1066 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1067 /* Switch LDO3318 source from DV33 to 3V3. */ 1068 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1069 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1070 /* Set default OLT blink period. */ 1071 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1072 /* Configure LTR. */ 1073 cap = pci_read_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_DEVICE_CTL2, 2); 1074 if (cap & PCIEM_CTL2_LTR_ENABLE) 1075 RTSX_WRITE(sc, RTSX_LTR_CTL, 0xa3); 1076 /* Configure OBFF. */ 1077 RTSX_BITOP(sc, RTSX_OBFF_CFG, RTSX_OBFF_EN_MASK, RTSX_OBFF_ENABLE); 1078 /* Configure driving. */ 1079 if ((error = rtsx_rts5227_fill_driving(sc))) 1080 return (error); 1081 /* Configure force_clock_req. */ 1082 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1083 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0xB8); 1084 else 1085 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0x88); 1086 RTSX_CLR(sc, RTSX_PM_CTRL3, RTSX_D3_DELINK_MODE_EN); 1087 /*!!! Added for reboot after Windows. */ 1088 RTSX_BITOP(sc, RTSX_PM_CTRL3, RTSX_PM_WAKE_EN, RTSX_PM_WAKE_EN); 1089 break; 1090 case RTSX_RTS5229: 1091 /* Configure GPIO as output. */ 1092 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1093 /* Reset ASPM state to default value. */ 1094 /* With this reset: dd if=/dev/random of=/dev/mmcsd0 encounter a timeout. */ 1095 //!!! RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1096 /* Force CLKREQ# PIN to drive 0 to request clock. */ 1097 RTSX_BITOP(sc, RTSX_PETXCFG, 0x08, 0x08); 1098 /* Switch LDO3318 source from DV33 to card_3v3. */ 1099 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1100 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1101 /* Set default OLT blink period. */ 1102 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1103 /* Configure driving. */ 1104 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3); 1105 break; 1106 case RTSX_RTS522A: 1107 /* Add specific init from RTS5227. */ 1108 /* Configure GPIO as output. */ 1109 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1110 /* Reset ASPM state to default value. */ 1111 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1112 /* Switch LDO3318 source from DV33 to 3V3. */ 1113 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1114 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1115 /* Set default OLT blink period. */ 1116 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1117 /* Configure LTR. */ 1118 cap = pci_read_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_DEVICE_CTL2, 2); 1119 if (cap & PCIEM_CTL2_LTR_ENABLE) 1120 RTSX_WRITE(sc, RTSX_LTR_CTL, 0xa3); 1121 /* Configure OBFF. */ 1122 RTSX_BITOP(sc, RTSX_OBFF_CFG, RTSX_OBFF_EN_MASK, RTSX_OBFF_ENABLE); 1123 /* Configure driving. */ 1124 if ((error = rtsx_rts5227_fill_driving(sc))) 1125 return (error); 1126 /* Configure force_clock_req. */ 1127 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1128 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0xB8); 1129 else 1130 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0x88); 1131 RTSX_CLR(sc, RTSX_RTS522A_PM_CTRL3, 0x10); 1132 1133 /* specific for RTS522A. */ 1134 RTSX_BITOP(sc, RTSX_FUNC_FORCE_CTL, 1135 RTSX_FUNC_FORCE_UPME_XMT_DBG, RTSX_FUNC_FORCE_UPME_XMT_DBG); 1136 RTSX_BITOP(sc, RTSX_PCLK_CTL, 0x04, 0x04); 1137 RTSX_BITOP(sc, RTSX_PM_EVENT_DEBUG, 1138 RTSX_PME_DEBUG_0, RTSX_PME_DEBUG_0); 1139 RTSX_WRITE(sc, RTSX_PM_CLK_FORCE_CTL, 0x11); 1140 break; 1141 case RTSX_RTS525A: 1142 /* Add specific init from RTS5249. */ 1143 /* Rest L1SUB Config. */ 1144 RTSX_CLR(sc, RTSX_L1SUB_CONFIG3, 0xff); 1145 /* Configure GPIO as output. */ 1146 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1147 /* Reset ASPM state to default value. */ 1148 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1149 /* Switch LDO3318 source from DV33 to 3V3. */ 1150 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1151 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1152 /* Set default OLT blink period. */ 1153 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1154 /* Configure driving. */ 1155 if ((error = rtsx_rts5249_fill_driving(sc))) 1156 return (error); 1157 /* Configure force_clock_req. */ 1158 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1159 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0xB0); 1160 else 1161 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0x80); 1162 1163 /* Specifc for RTS525A. */ 1164 RTSX_BITOP(sc, RTSX_PCLK_CTL, RTSX_PCLK_MODE_SEL, RTSX_PCLK_MODE_SEL); 1165 if (sc->rtsx_flags & RTSX_F_VERSION_A) { 1166 RTSX_WRITE(sc, RTSX_L1SUB_CONFIG2, RTSX_L1SUB_AUTO_CFG); 1167 RTSX_BITOP(sc, RTSX_RREF_CFG, 1168 RTSX_RREF_VBGSEL_MASK, RTSX_RREF_VBGSEL_1V25); 1169 RTSX_BITOP(sc, RTSX_LDO_VIO_CFG, 1170 RTSX_LDO_VIO_TUNE_MASK, RTSX_LDO_VIO_1V7); 1171 RTSX_BITOP(sc, RTSX_LDO_DV12S_CFG, 1172 RTSX_LDO_D12_TUNE_MASK, RTSX_LDO_D12_TUNE_DF); 1173 RTSX_BITOP(sc, RTSX_LDO_AV12S_CFG, 1174 RTSX_LDO_AV12S_TUNE_MASK, RTSX_LDO_AV12S_TUNE_DF); 1175 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG0, 1176 RTSX_LDO_VCC_LMTVTH_MASK, RTSX_LDO_VCC_LMTVTH_2A); 1177 RTSX_BITOP(sc, RTSX_OOBS_CONFIG, 1178 RTSX_OOBS_AUTOK_DIS | RTSX_OOBS_VAL_MASK, 0x89); 1179 } 1180 break; 1181 case RTSX_RTS5249: 1182 /* Rest L1SUB Config. */ 1183 RTSX_CLR(sc, RTSX_L1SUB_CONFIG3, 0xff); 1184 /* Configure GPIO as output. */ 1185 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1186 /* Reset ASPM state to default value. */ 1187 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1188 /* Switch LDO3318 source from DV33 to 3V3. */ 1189 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1190 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1191 /* Set default OLT blink period. */ 1192 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1193 /* Configure driving. */ 1194 if ((error = rtsx_rts5249_fill_driving(sc))) 1195 return (error); 1196 /* Configure force_clock_req. */ 1197 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1198 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0xB0); 1199 else 1200 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0x80); 1201 break; 1202 case RTSX_RTL8402: 1203 case RTSX_RTL8411: 1204 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3); 1205 RTSX_BITOP(sc, RTSX_CARD_PAD_CTL, RTSX_CD_DISABLE_MASK | RTSX_CD_AUTO_DISABLE, 1206 RTSX_CD_ENABLE); 1207 break; 1208 case RTSX_RTL8411B: 1209 if (sc->rtsx_flags & RTSX_F_8411B_QFN48) 1210 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf5); 1211 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3); 1212 /* Enable SD interrupt. */ 1213 RTSX_BITOP(sc, RTSX_CARD_PAD_CTL, RTSX_CD_DISABLE_MASK | RTSX_CD_AUTO_DISABLE, 1214 RTSX_CD_ENABLE); 1215 /* Clear hw_pfm_en to disable hardware PFM mode. */ 1216 RTSX_BITOP(sc, RTSX_FUNC_FORCE_CTL, 0x06, 0x00); 1217 break; 1218 } 1219 1220 /*!!! Added for reboot after Windows. */ 1221 rtsx_bus_power_off(sc); 1222 rtsx_set_sd_timing(sc, bus_timing_normal); 1223 rtsx_set_sd_clock(sc, 0); 1224 /*!!! Added for reboot after Windows. */ 1225 1226 return (0); 1227 } 1228 1229 static int 1230 rtsx_map_sd_drive(int index) 1231 { 1232 uint8_t sd_drive[4] = 1233 { 1234 0x01, /* Type D */ 1235 0x02, /* Type C */ 1236 0x05, /* Type A */ 1237 0x03 /* Type B */ 1238 }; 1239 return (sd_drive[index]); 1240 } 1241 1242 /* For voltage 3v3. */ 1243 static int 1244 rtsx_rts5227_fill_driving(struct rtsx_softc *sc) 1245 { 1246 u_char driving_3v3[4][3] = { 1247 {0x13, 0x13, 0x13}, 1248 {0x96, 0x96, 0x96}, 1249 {0x7F, 0x7F, 0x7F}, 1250 {0x96, 0x96, 0x96}, 1251 }; 1252 RTSX_WRITE(sc, RTSX_SD30_CLK_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][0]); 1253 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][1]); 1254 RTSX_WRITE(sc, RTSX_SD30_DAT_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][2]); 1255 1256 return (0); 1257 } 1258 1259 /* For voltage 3v3. */ 1260 static int 1261 rtsx_rts5249_fill_driving(struct rtsx_softc *sc) 1262 { 1263 u_char driving_3v3[4][3] = { 1264 {0x11, 0x11, 0x18}, 1265 {0x55, 0x55, 0x5C}, 1266 {0xFF, 0xFF, 0xFF}, 1267 {0x96, 0x96, 0x96}, 1268 }; 1269 RTSX_WRITE(sc, RTSX_SD30_CLK_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][0]); 1270 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][1]); 1271 RTSX_WRITE(sc, RTSX_SD30_DAT_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][2]); 1272 1273 return (0); 1274 } 1275 1276 static int 1277 rtsx_read(struct rtsx_softc *sc, uint16_t addr, uint8_t *val) 1278 { 1279 int tries = 1024; 1280 uint32_t reg; 1281 1282 WRITE4(sc, RTSX_HAIMR, RTSX_HAIMR_BUSY | 1283 (uint32_t)((addr & 0x3FFF) << 16)); 1284 1285 while (tries--) { 1286 reg = READ4(sc, RTSX_HAIMR); 1287 if (!(reg & RTSX_HAIMR_BUSY)) 1288 break; 1289 } 1290 *val = (reg & 0xff); 1291 1292 return ((tries == 0) ? ETIMEDOUT : 0); 1293 } 1294 1295 static int 1296 rtsx_read_cfg(struct rtsx_softc *sc, uint8_t func, uint16_t addr, uint32_t *val) 1297 { 1298 int tries = 1024; 1299 uint8_t data0, data1, data2, data3, rwctl; 1300 1301 RTSX_WRITE(sc, RTSX_CFGADDR0, addr); 1302 RTSX_WRITE(sc, RTSX_CFGADDR1, addr >> 8); 1303 RTSX_WRITE(sc, RTSX_CFGRWCTL, RTSX_CFG_BUSY | (func & 0x03 << 4)); 1304 1305 while (tries--) { 1306 RTSX_READ(sc, RTSX_CFGRWCTL, &rwctl); 1307 if (!(rwctl & RTSX_CFG_BUSY)) 1308 break; 1309 } 1310 1311 if (tries == 0) 1312 return (ETIMEDOUT); 1313 1314 RTSX_READ(sc, RTSX_CFGDATA0, &data0); 1315 RTSX_READ(sc, RTSX_CFGDATA1, &data1); 1316 RTSX_READ(sc, RTSX_CFGDATA2, &data2); 1317 RTSX_READ(sc, RTSX_CFGDATA3, &data3); 1318 1319 *val = (data3 << 24) | (data2 << 16) | (data1 << 8) | data0; 1320 1321 return (0); 1322 } 1323 1324 static int 1325 rtsx_write(struct rtsx_softc *sc, uint16_t addr, uint8_t mask, uint8_t val) 1326 { 1327 int tries = 1024; 1328 uint32_t reg; 1329 1330 WRITE4(sc, RTSX_HAIMR, 1331 RTSX_HAIMR_BUSY | RTSX_HAIMR_WRITE | 1332 (uint32_t)(((addr & 0x3FFF) << 16) | 1333 (mask << 8) | val)); 1334 1335 while (tries--) { 1336 reg = READ4(sc, RTSX_HAIMR); 1337 if (!(reg & RTSX_HAIMR_BUSY)) { 1338 if (val != (reg & 0xff)) 1339 return (EIO); 1340 return (0); 1341 } 1342 } 1343 1344 return (ETIMEDOUT); 1345 } 1346 1347 static int 1348 rtsx_read_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t *val) 1349 { 1350 int tries = 100000; 1351 uint8_t data0, data1, rwctl; 1352 1353 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr); 1354 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY | RTSX_PHY_READ); 1355 1356 while (tries--) { 1357 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl); 1358 if (!(rwctl & RTSX_PHY_BUSY)) 1359 break; 1360 } 1361 if (tries == 0) 1362 return (ETIMEDOUT); 1363 1364 RTSX_READ(sc, RTSX_PHY_DATA0, &data0); 1365 RTSX_READ(sc, RTSX_PHY_DATA1, &data1); 1366 *val = data1 << 8 | data0; 1367 1368 return (0); 1369 } 1370 1371 static int 1372 rtsx_write_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t val) 1373 { 1374 int tries = 100000; 1375 uint8_t rwctl; 1376 1377 RTSX_WRITE(sc, RTSX_PHY_DATA0, val); 1378 RTSX_WRITE(sc, RTSX_PHY_DATA1, val >> 8); 1379 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr); 1380 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY | RTSX_PHY_WRITE); 1381 1382 while (tries--) { 1383 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl); 1384 if (!(rwctl & RTSX_PHY_BUSY)) 1385 break; 1386 } 1387 1388 return ((tries == 0) ? ETIMEDOUT : 0); 1389 } 1390 1391 /* 1392 * Notice that the meaning of RTSX_PWR_GATE_CTRL changes between RTS5209 and 1393 * RTS5229. In RTS5209 it is a mask of disabled power gates, while in RTS5229 1394 * it is a mask of *enabled* gates. 1395 */ 1396 static int 1397 rtsx_bus_power_off(struct rtsx_softc *sc) 1398 { 1399 if (bootverbose || sc->rtsx_debug) 1400 device_printf(sc->rtsx_dev, "rtsx_bus_power_off()\n"); 1401 1402 /* Disable SD clock. */ 1403 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_SD_CLK_EN); 1404 1405 /* Disable SD output. */ 1406 RTSX_CLR(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN); 1407 1408 /* Turn off power. */ 1409 switch (sc->rtsx_device_id) { 1410 case RTSX_RTS5209: 1411 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK | RTSX_PMOS_STRG_MASK, 1412 RTSX_SD_PWR_OFF | RTSX_PMOS_STRG_400mA); 1413 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_OFF); 1414 break; 1415 case RTSX_RTS5227: 1416 case RTSX_RTS5229: 1417 case RTSX_RTS522A: 1418 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK | RTSX_PMOS_STRG_MASK, 1419 RTSX_SD_PWR_OFF | RTSX_PMOS_STRG_400mA); 1420 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK); 1421 break; 1422 case RTSX_RTL8402: 1423 case RTSX_RTL8411: 1424 case RTSX_RTL8411B: 1425 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1426 RTSX_BPP_POWER_OFF); 1427 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB, 1428 RTSX_BPP_LDO_SUSPEND); 1429 break; 1430 default: 1431 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK); 1432 RTSX_SET(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_OFF); 1433 RTSX_CLR(sc, RTSX_CARD_PWR_CTL, RTSX_PMOS_STRG_800mA); 1434 break; 1435 } 1436 1437 /* Disable pull control. */ 1438 switch (sc->rtsx_device_id) { 1439 case RTSX_RTS5209: 1440 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_DISABLE12); 1441 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 1442 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3); 1443 break; 1444 case RTSX_RTS5227: 1445 case RTSX_RTS522A: 1446 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 1447 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3); 1448 break; 1449 case RTSX_RTS5229: 1450 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 1451 if (sc->rtsx_flags & RTSX_F_VERSION_C) 1452 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3_TYPE_C); 1453 else 1454 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3); 1455 break; 1456 case RTSX_RTS525A: 1457 case RTSX_RTS5249: 1458 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x66); 1459 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 1460 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3); 1461 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x55); 1462 break; 1463 case RTSX_RTL8402: 1464 case RTSX_RTL8411: 1465 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x65); 1466 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x55); 1467 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0x95); 1468 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x09); 1469 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x05); 1470 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x04); 1471 break; 1472 case RTSX_RTL8411B: 1473 if (sc->rtsx_flags & RTSX_F_8411B_QFN48) { 1474 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x55); 1475 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf5); 1476 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15); 1477 } else { 1478 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x65); 1479 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x55); 1480 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xd5); 1481 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x59); 1482 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x55); 1483 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15); 1484 } 1485 break; 1486 } 1487 1488 return (0); 1489 } 1490 1491 static int 1492 rtsx_bus_power_on(struct rtsx_softc *sc) 1493 { 1494 if (bootverbose || sc->rtsx_debug) 1495 device_printf(sc->rtsx_dev, "rtsx_bus_power_on()\n"); 1496 1497 /* Select SD card. */ 1498 RTSX_BITOP(sc, RTSX_CARD_SELECT, 0x07, RTSX_SD_MOD_SEL); 1499 RTSX_BITOP(sc, RTSX_CARD_SHARE_MODE, RTSX_CARD_SHARE_MASK, RTSX_CARD_SHARE_48_SD); 1500 1501 /* Enable SD clock. */ 1502 RTSX_BITOP(sc, RTSX_CARD_CLK_EN, RTSX_SD_CLK_EN, RTSX_SD_CLK_EN); 1503 1504 /* Enable pull control. */ 1505 switch (sc->rtsx_device_id) { 1506 case RTSX_RTS5209: 1507 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_ENABLE12); 1508 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 1509 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3); 1510 break; 1511 case RTSX_RTS5227: 1512 case RTSX_RTS522A: 1513 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 1514 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3); 1515 break; 1516 case RTSX_RTS5229: 1517 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 1518 if (sc->rtsx_flags & RTSX_F_VERSION_C) 1519 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3_TYPE_C); 1520 else 1521 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3); 1522 break; 1523 case RTSX_RTS525A: 1524 case RTSX_RTS5249: 1525 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x66); 1526 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 1527 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3); 1528 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0xaa); 1529 break; 1530 case RTSX_RTL8402: 1531 case RTSX_RTL8411: 1532 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0xaa); 1533 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa); 1534 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xa9); 1535 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x09); 1536 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x09); 1537 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x04); 1538 break; 1539 case RTSX_RTL8411B: 1540 if (sc->rtsx_flags & RTSX_F_8411B_QFN48) { 1541 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa); 1542 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf9); 1543 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x19); 1544 } else { 1545 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0xaa); 1546 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa); 1547 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xd9); 1548 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x59); 1549 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x55); 1550 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15); 1551 } 1552 break; 1553 } 1554 1555 /* 1556 * To avoid a current peak, enable card power in two phases 1557 * with a delay in between. 1558 */ 1559 switch (sc->rtsx_device_id) { 1560 case RTSX_RTS5209: 1561 /* Partial power. */ 1562 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON); 1563 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC2); 1564 1565 DELAY(200); 1566 1567 /* Full power. */ 1568 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON); 1569 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_ON); 1570 break; 1571 case RTSX_RTS5227: 1572 case RTSX_RTS522A: 1573 /* Partial power. */ 1574 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON); 1575 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC1); 1576 1577 DELAY(20000); 1578 1579 /* Full power. */ 1580 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON); 1581 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, 1582 RTSX_LDO3318_VCC1 | RTSX_LDO3318_VCC2); 1583 RTSX_BITOP(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN, RTSX_SD_OUTPUT_EN); 1584 RTSX_BITOP(sc, RTSX_CARD_OE, RTSX_MS_OUTPUT_EN, RTSX_MS_OUTPUT_EN); 1585 break; 1586 case RTSX_RTS5229: 1587 /* Partial power. */ 1588 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON); 1589 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC1); 1590 1591 DELAY(200); 1592 1593 /* Full power. */ 1594 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON); 1595 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, 1596 RTSX_LDO3318_VCC1 | RTSX_LDO3318_VCC2); 1597 break; 1598 case RTSX_RTS525A: 1599 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG1, RTSX_LDO_VCC_TUNE_MASK, RTSX_LDO_VCC_3V3); 1600 case RTSX_RTS5249: 1601 /* Partial power. */ 1602 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON); 1603 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC1); 1604 1605 DELAY(5000); 1606 1607 /* Full power. */ 1608 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON); 1609 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, 1610 RTSX_LDO3318_VCC1 | RTSX_LDO3318_VCC2); 1611 break; 1612 case RTSX_RTL8402: 1613 case RTSX_RTL8411: 1614 case RTSX_RTL8411B: 1615 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1616 RTSX_BPP_POWER_5_PERCENT_ON); 1617 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB, 1618 RTSX_BPP_LDO_SUSPEND); 1619 DELAY(150); 1620 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1621 RTSX_BPP_POWER_10_PERCENT_ON); 1622 DELAY(150); 1623 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1624 RTSX_BPP_POWER_15_PERCENT_ON); 1625 DELAY(150); 1626 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1627 RTSX_BPP_POWER_ON); 1628 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB, 1629 RTSX_BPP_LDO_ON); 1630 break; 1631 } 1632 1633 /* Enable SD card output. */ 1634 RTSX_WRITE(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN); 1635 1636 DELAY(200); 1637 1638 return (0); 1639 } 1640 1641 /* 1642 * Set but width. 1643 */ 1644 static int 1645 rtsx_set_bus_width(struct rtsx_softc *sc, enum mmc_bus_width width) 1646 { 1647 uint32_t bus_width; 1648 1649 switch (width) { 1650 case bus_width_1: 1651 bus_width = RTSX_BUS_WIDTH_1; 1652 break; 1653 case bus_width_4: 1654 bus_width = RTSX_BUS_WIDTH_4; 1655 break; 1656 case bus_width_8: 1657 bus_width = RTSX_BUS_WIDTH_8; 1658 break; 1659 default: 1660 return (MMC_ERR_INVALID); 1661 } 1662 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_BUS_WIDTH_MASK, bus_width); 1663 1664 if (bootverbose || sc->rtsx_debug) { 1665 char *busw[] = { 1666 "1 bit", 1667 "4 bits", 1668 "8 bits" 1669 }; 1670 device_printf(sc->rtsx_dev, "Setting bus width to %s\n", busw[bus_width]); 1671 } 1672 return (0); 1673 } 1674 1675 static int 1676 rtsx_set_sd_timing(struct rtsx_softc *sc, enum mmc_bus_timing timing) 1677 { 1678 if (timing == bus_timing_hs && sc->rtsx_force_timing) { 1679 timing = bus_timing_uhs_sdr50; 1680 sc->rtsx_ios_timing = timing; 1681 } 1682 1683 if (bootverbose || sc->rtsx_debug) 1684 device_printf(sc->rtsx_dev, "rtsx_set_sd_timing(%u)\n", timing); 1685 1686 switch (timing) { 1687 case bus_timing_uhs_sdr50: 1688 case bus_timing_uhs_sdr104: 1689 sc->rtsx_double_clk = false; 1690 sc->rtsx_vpclk = true; 1691 RTSX_BITOP(sc, RTSX_SD_CFG1, 0x0c | RTSX_SD_ASYNC_FIFO_NOT_RST, 1692 RTSX_SD30_MODE | RTSX_SD_ASYNC_FIFO_NOT_RST); 1693 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ); 1694 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 1695 RTSX_CRC_VAR_CLK0 | RTSX_SD30_FIX_CLK | RTSX_SAMPLE_VAR_CLK1); 1696 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1697 break; 1698 case bus_timing_hs: 1699 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK, RTSX_SD20_MODE); 1700 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ); 1701 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 1702 RTSX_CRC_FIX_CLK | RTSX_SD30_VAR_CLK0 | RTSX_SAMPLE_VAR_CLK1); 1703 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1704 1705 RTSX_BITOP(sc, RTSX_SD_PUSH_POINT_CTL, 1706 RTSX_SD20_TX_SEL_MASK, RTSX_SD20_TX_14_AHEAD); 1707 RTSX_BITOP(sc, RTSX_SD_SAMPLE_POINT_CTL, 1708 RTSX_SD20_RX_SEL_MASK, RTSX_SD20_RX_14_DELAY); 1709 break; 1710 default: 1711 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK, RTSX_SD20_MODE); 1712 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ); 1713 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 1714 RTSX_CRC_FIX_CLK | RTSX_SD30_VAR_CLK0 | RTSX_SAMPLE_VAR_CLK1); 1715 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1716 1717 RTSX_WRITE(sc, RTSX_SD_PUSH_POINT_CTL, RTSX_SD20_TX_NEG_EDGE); 1718 RTSX_BITOP(sc, RTSX_SD_SAMPLE_POINT_CTL, 1719 RTSX_SD20_RX_SEL_MASK, RTSX_SD20_RX_POS_EDGE); 1720 break; 1721 } 1722 1723 return (0); 1724 } 1725 1726 /* 1727 * Set or change SDCLK frequency or disable the SD clock. 1728 * Return zero on success. 1729 */ 1730 static int 1731 rtsx_set_sd_clock(struct rtsx_softc *sc, uint32_t freq) 1732 { 1733 uint8_t clk; 1734 uint8_t clk_divider, n, div, mcu; 1735 int error = 0; 1736 1737 if (bootverbose || sc->rtsx_debug) 1738 device_printf(sc->rtsx_dev, "rtsx_set_sd_clock(%u)\n", freq); 1739 1740 if (freq == RTSX_SDCLK_OFF) { 1741 error = rtsx_stop_sd_clock(sc); 1742 return error; 1743 } 1744 1745 sc->rtsx_ssc_depth = RTSX_SSC_DEPTH_500K; 1746 sc->rtsx_discovery_mode = (freq <= 1000000) ? true : false; 1747 1748 if (sc->rtsx_discovery_mode) { 1749 /* We use 250k(around) here, in discovery stage. */ 1750 clk_divider = RTSX_CLK_DIVIDE_128; 1751 freq = 30000000; 1752 } else { 1753 clk_divider = RTSX_CLK_DIVIDE_0; 1754 } 1755 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, clk_divider); 1756 1757 freq /= 1000000; 1758 if (sc->rtsx_discovery_mode || !sc->rtsx_double_clk) 1759 clk = freq; 1760 else 1761 clk = freq * 2; 1762 1763 switch (sc->rtsx_device_id) { 1764 case RTSX_RTL8402: 1765 case RTSX_RTL8411: 1766 case RTSX_RTL8411B: 1767 n = clk * 4 / 5 - 2; 1768 break; 1769 default: 1770 n = clk - 2; 1771 break; 1772 } 1773 if ((clk <= 2) || (n > RTSX_MAX_DIV_N)) 1774 return (MMC_ERR_INVALID); 1775 1776 mcu = 125 / clk + 3; 1777 if (mcu > 15) 1778 mcu = 15; 1779 1780 /* Make sure that the SSC clock div_n is not less than RTSX_MIN_DIV_N. */ 1781 div = RTSX_CLK_DIV_1; 1782 while ((n < RTSX_MIN_DIV_N) && (div < RTSX_CLK_DIV_8)) { 1783 switch (sc->rtsx_device_id) { 1784 case RTSX_RTL8402: 1785 case RTSX_RTL8411: 1786 case RTSX_RTL8411B: 1787 n = (((n + 2) * 5 / 4) * 2) * 4 / 5 - 2; 1788 break; 1789 default: 1790 n = (n + 2) * 2 - 2; 1791 break; 1792 } 1793 div++; 1794 } 1795 1796 if (sc->rtsx_double_clk && sc->rtsx_ssc_depth > 1) 1797 sc->rtsx_ssc_depth -= 1; 1798 1799 if (div > RTSX_CLK_DIV_1) { 1800 if (sc->rtsx_ssc_depth > (div - 1)) 1801 sc->rtsx_ssc_depth -= (div - 1); 1802 else 1803 sc->rtsx_ssc_depth = RTSX_SSC_DEPTH_4M; 1804 } 1805 1806 /* Enable SD clock. */ 1807 error = rtsx_switch_sd_clock(sc, clk, n, div, mcu); 1808 1809 return (error); 1810 } 1811 1812 static int 1813 rtsx_stop_sd_clock(struct rtsx_softc *sc) 1814 { 1815 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL); 1816 RTSX_SET(sc, RTSX_SD_BUS_STAT, RTSX_SD_CLK_FORCE_STOP); 1817 1818 return (0); 1819 } 1820 1821 static int 1822 rtsx_switch_sd_clock(struct rtsx_softc *sc, uint8_t clk, uint8_t n, uint8_t div, uint8_t mcu) 1823 { 1824 if (bootverbose || sc->rtsx_debug) { 1825 device_printf(sc->rtsx_dev, "rtsx_switch_sd_clock() - discovery-mode is %s, ssc_depth: %d\n", 1826 (sc->rtsx_discovery_mode) ? "true" : "false", sc->rtsx_ssc_depth); 1827 device_printf(sc->rtsx_dev, "rtsx_switch_sd_clock() - clk: %d, n: %d, div: %d, mcu: %d\n", 1828 clk, n, div, mcu); 1829 } 1830 1831 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ); 1832 RTSX_WRITE(sc, RTSX_CLK_DIV, (div << 4) | mcu); 1833 RTSX_CLR(sc, RTSX_SSC_CTL1, RTSX_RSTB); 1834 RTSX_BITOP(sc, RTSX_SSC_CTL2, RTSX_SSC_DEPTH_MASK, sc->rtsx_ssc_depth); 1835 RTSX_WRITE(sc, RTSX_SSC_DIV_N_0, n); 1836 RTSX_BITOP(sc, RTSX_SSC_CTL1, RTSX_RSTB, RTSX_RSTB); 1837 if (sc->rtsx_vpclk) { 1838 RTSX_CLR(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET); 1839 RTSX_BITOP(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET, RTSX_PHASE_NOT_RESET); 1840 } 1841 1842 /* Wait SSC clock stable. */ 1843 DELAY(200); 1844 1845 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1846 1847 return (0); 1848 } 1849 1850 #ifndef MMCCAM 1851 static void 1852 rtsx_sd_change_tx_phase(struct rtsx_softc *sc, uint8_t sample_point) 1853 { 1854 if (bootverbose || sc->rtsx_debug) 1855 device_printf(sc->rtsx_dev, "rtsx_sd_change_tx_phase() - sample_point: %d\n", sample_point); 1856 1857 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, RTSX_CHANGE_CLK); 1858 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_SELECT_MASK, sample_point); 1859 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET, 0); 1860 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET, RTSX_PHASE_NOT_RESET); 1861 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, 0); 1862 rtsx_write(sc, RTSX_SD_CFG1, RTSX_SD_ASYNC_FIFO_NOT_RST, 0); 1863 } 1864 1865 static void 1866 rtsx_sd_change_rx_phase(struct rtsx_softc *sc, uint8_t sample_point) 1867 { 1868 if (bootverbose || sc->rtsx_debug == 2) 1869 device_printf(sc->rtsx_dev, "rtsx_sd_change_rx_phase() - sample_point: %d\n", sample_point); 1870 1871 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, RTSX_CHANGE_CLK); 1872 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_SELECT_MASK, sample_point); 1873 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_NOT_RESET, 0); 1874 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_NOT_RESET, RTSX_PHASE_NOT_RESET); 1875 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, 0); 1876 rtsx_write(sc, RTSX_SD_CFG1, RTSX_SD_ASYNC_FIFO_NOT_RST, 0); 1877 } 1878 1879 static void 1880 rtsx_sd_tuning_rx_phase(struct rtsx_softc *sc, uint32_t *phase_map) 1881 { 1882 uint32_t raw_phase_map = 0; 1883 int i; 1884 int error; 1885 1886 for (i = 0; i < RTSX_RX_PHASE_MAX; i++) { 1887 error = rtsx_sd_tuning_rx_cmd(sc, (uint8_t)i); 1888 if (error == 0) 1889 raw_phase_map |= 1 << i; 1890 } 1891 if (phase_map != NULL) 1892 *phase_map = raw_phase_map; 1893 } 1894 1895 static int 1896 rtsx_sd_tuning_rx_cmd(struct rtsx_softc *sc, uint8_t sample_point) 1897 { 1898 struct mmc_request req = {}; 1899 struct mmc_command cmd = {}; 1900 int error = 0; 1901 1902 cmd.opcode = MMC_SEND_TUNING_BLOCK; 1903 cmd.arg = 0; 1904 req.cmd = &cmd; 1905 1906 RTSX_LOCK(sc); 1907 1908 sc->rtsx_req = &req; 1909 1910 rtsx_sd_change_rx_phase(sc, sample_point); 1911 1912 rtsx_write(sc, RTSX_SD_CFG3, RTSX_SD_RSP_80CLK_TIMEOUT_EN, 1913 RTSX_SD_RSP_80CLK_TIMEOUT_EN); 1914 1915 rtsx_init_cmd(sc, &cmd); 1916 rtsx_set_cmd_data_len(sc, 1, 0x40); 1917 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, 1918 RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC16 | 1919 RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_CHECK_CRC7 | RTSX_SD_RSP_LEN_6); 1920 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 1921 0xff, RTSX_TM_AUTO_TUNING | RTSX_SD_TRANSFER_START); 1922 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 1923 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 1924 1925 /* Set interrupt post processing */ 1926 sc->rtsx_intr_trans_ok = rtsx_sd_tuning_rx_cmd_wakeup; 1927 sc->rtsx_intr_trans_ko = rtsx_sd_tuning_rx_cmd_wakeup; 1928 1929 /* Run the command queue. */ 1930 rtsx_send_cmd(sc); 1931 1932 error = rtsx_sd_tuning_rx_cmd_wait(sc, &cmd); 1933 1934 if (error) { 1935 if (bootverbose || sc->rtsx_debug == 2) 1936 device_printf(sc->rtsx_dev, "rtsx_sd_tuning_rx_cmd() - error: %d\n", error); 1937 rtsx_sd_wait_data_idle(sc); 1938 rtsx_clear_error(sc); 1939 } 1940 rtsx_write(sc, RTSX_SD_CFG3, RTSX_SD_RSP_80CLK_TIMEOUT_EN, 0); 1941 1942 sc->rtsx_req = NULL; 1943 1944 RTSX_UNLOCK(sc); 1945 1946 return (error); 1947 } 1948 1949 static int 1950 rtsx_sd_tuning_rx_cmd_wait(struct rtsx_softc *sc, struct mmc_command *cmd) 1951 { 1952 int status; 1953 int mask = RTSX_TRANS_OK_INT | RTSX_TRANS_FAIL_INT; 1954 1955 status = sc->rtsx_intr_status & mask; 1956 while (status == 0) { 1957 if (msleep(&sc->rtsx_intr_status, &sc->rtsx_mtx, 0, "rtsxintr", sc->rtsx_timeout_cmd) == EWOULDBLOCK) { 1958 cmd->error = MMC_ERR_TIMEOUT; 1959 return (MMC_ERR_TIMEOUT); 1960 } 1961 status = sc->rtsx_intr_status & mask; 1962 } 1963 return (cmd->error); 1964 } 1965 1966 static void 1967 rtsx_sd_tuning_rx_cmd_wakeup(struct rtsx_softc *sc) 1968 { 1969 wakeup(&sc->rtsx_intr_status); 1970 } 1971 1972 static void 1973 rtsx_sd_wait_data_idle(struct rtsx_softc *sc) 1974 { 1975 int i; 1976 uint8_t val; 1977 1978 for (i = 0; i < 100; i++) { 1979 rtsx_read(sc, RTSX_SD_DATA_STATE, &val); 1980 if (val & RTSX_SD_DATA_IDLE) 1981 return; 1982 DELAY(100); 1983 } 1984 } 1985 1986 static uint8_t 1987 rtsx_sd_search_final_rx_phase(struct rtsx_softc *sc, uint32_t phase_map) 1988 { 1989 int start = 0, len = 0; 1990 int start_final = 0, len_final = 0; 1991 uint8_t final_phase = 0xff; 1992 1993 while (start < RTSX_RX_PHASE_MAX) { 1994 len = rtsx_sd_get_rx_phase_len(phase_map, start); 1995 if (len_final < len) { 1996 start_final = start; 1997 len_final = len; 1998 } 1999 start += len ? len : 1; 2000 } 2001 2002 final_phase = (start_final + len_final / 2) % RTSX_RX_PHASE_MAX; 2003 2004 if (bootverbose || sc->rtsx_debug) 2005 device_printf(sc->rtsx_dev, 2006 "rtsx_sd_search_final_rx_phase() - phase_map: %x, start_final: %d, len_final: %d, final_phase: %d\n", 2007 phase_map, start_final, len_final, final_phase); 2008 2009 return final_phase; 2010 } 2011 2012 static int 2013 rtsx_sd_get_rx_phase_len(uint32_t phase_map, int start_bit) 2014 { 2015 int i; 2016 2017 for (i = 0; i < RTSX_RX_PHASE_MAX; i++) { 2018 if ((phase_map & (1 << (start_bit + i) % RTSX_RX_PHASE_MAX)) == 0) 2019 return i; 2020 } 2021 return RTSX_RX_PHASE_MAX; 2022 } 2023 #endif /* !MMCCAM */ 2024 2025 #if 0 /* For led */ 2026 static int 2027 rtsx_led_enable(struct rtsx_softc *sc) 2028 { 2029 switch (sc->rtsx_device_id) { 2030 case RTSX_RTS5209: 2031 RTSX_CLR(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF); 2032 RTSX_WRITE(sc, RTSX_CARD_AUTO_BLINK, 2033 RTSX_LED_BLINK_EN | RTSX_LED_BLINK_SPEED); 2034 break; 2035 case RTSX_RTL8411B: 2036 RTSX_CLR(sc, RTSX_GPIO_CTL, 0x01); 2037 RTSX_WRITE(sc, RTSX_CARD_AUTO_BLINK, 2038 RTSX_LED_BLINK_EN | RTSX_LED_BLINK_SPEED); 2039 break; 2040 default: 2041 RTSX_SET(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 2042 RTSX_SET(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK); 2043 break; 2044 } 2045 2046 return (0); 2047 } 2048 2049 static int 2050 rtsx_led_disable(struct rtsx_softc *sc) 2051 { 2052 switch (sc->rtsx_device_id) { 2053 case RTSX_RTS5209: 2054 RTSX_CLR(sc, RTSX_CARD_AUTO_BLINK, RTSX_LED_BLINK_EN); 2055 RTSX_WRITE(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF); 2056 break; 2057 case RTSX_RTL8411B: 2058 RTSX_CLR(sc, RTSX_CARD_AUTO_BLINK, RTSX_LED_BLINK_EN); 2059 RTSX_SET(sc, RTSX_GPIO_CTL, 0x01); 2060 break; 2061 default: 2062 RTSX_CLR(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK); 2063 RTSX_CLR(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 2064 break; 2065 } 2066 2067 return (0); 2068 } 2069 #endif /* For led */ 2070 2071 static uint8_t 2072 rtsx_response_type(uint16_t mmc_rsp) 2073 { 2074 int i; 2075 struct rsp_type { 2076 uint16_t mmc_rsp; 2077 uint8_t rtsx_rsp; 2078 } rsp_types[] = { 2079 { MMC_RSP_NONE, RTSX_SD_RSP_TYPE_R0 }, 2080 { MMC_RSP_R1, RTSX_SD_RSP_TYPE_R1 }, 2081 { MMC_RSP_R1B, RTSX_SD_RSP_TYPE_R1B }, 2082 { MMC_RSP_R2, RTSX_SD_RSP_TYPE_R2 }, 2083 { MMC_RSP_R3, RTSX_SD_RSP_TYPE_R3 }, 2084 { MMC_RSP_R4, RTSX_SD_RSP_TYPE_R4 }, 2085 { MMC_RSP_R5, RTSX_SD_RSP_TYPE_R5 }, 2086 { MMC_RSP_R6, RTSX_SD_RSP_TYPE_R6 }, 2087 { MMC_RSP_R7, RTSX_SD_RSP_TYPE_R7 } 2088 }; 2089 2090 for (i = 0; i < nitems(rsp_types); i++) { 2091 if (mmc_rsp == rsp_types[i].mmc_rsp) 2092 return (rsp_types[i].rtsx_rsp); 2093 } 2094 2095 return (0); 2096 } 2097 2098 /* 2099 * Init command buffer with SD command index and argument. 2100 */ 2101 static void 2102 rtsx_init_cmd(struct rtsx_softc *sc, struct mmc_command *cmd) 2103 { 2104 sc->rtsx_cmd_index = 0; 2105 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD0, 2106 0xff, RTSX_SD_CMD_START | cmd->opcode); 2107 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD1, 2108 0xff, cmd->arg >> 24); 2109 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD2, 2110 0xff, cmd->arg >> 16); 2111 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD3, 2112 0xff, cmd->arg >> 8); 2113 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD4, 2114 0xff, cmd->arg); 2115 } 2116 2117 /* 2118 * Append a properly encoded host command to the host command buffer. 2119 */ 2120 static void 2121 rtsx_push_cmd(struct rtsx_softc *sc, uint8_t cmd, uint16_t reg, 2122 uint8_t mask, uint8_t data) 2123 { 2124 KASSERT(sc->rtsx_cmd_index < RTSX_HOSTCMD_MAX, 2125 ("rtsx: Too many host commands (%d)\n", sc->rtsx_cmd_index)); 2126 2127 uint32_t *cmd_buffer = (uint32_t *)(sc->rtsx_cmd_dmamem); 2128 cmd_buffer[sc->rtsx_cmd_index++] = 2129 htole32((uint32_t)(cmd & 0x3) << 30) | 2130 ((uint32_t)(reg & 0x3fff) << 16) | 2131 ((uint32_t)(mask) << 8) | 2132 ((uint32_t)data); 2133 } 2134 2135 /* 2136 * Queue commands to configure data transfer size. 2137 */ 2138 static void 2139 rtsx_set_cmd_data_len(struct rtsx_softc *sc, uint16_t block_cnt, uint16_t byte_cnt) 2140 { 2141 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_L, 2142 0xff, block_cnt & 0xff); 2143 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_H, 2144 0xff, block_cnt >> 8); 2145 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_L, 2146 0xff, byte_cnt & 0xff); 2147 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_H, 2148 0xff, byte_cnt >> 8); 2149 } 2150 2151 /* 2152 * Run the command queue. 2153 */ 2154 static void 2155 rtsx_send_cmd(struct rtsx_softc *sc) 2156 { 2157 if (bootverbose) 2158 device_printf(sc->rtsx_dev, "rtsx_send_cmd()\n"); 2159 2160 sc->rtsx_intr_status = 0; 2161 2162 /* Sync command DMA buffer. */ 2163 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_PREREAD); 2164 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_PREWRITE); 2165 2166 /* Tell the chip where the command buffer is and run the commands. */ 2167 WRITE4(sc, RTSX_HCBAR, (uint32_t)sc->rtsx_cmd_buffer); 2168 WRITE4(sc, RTSX_HCBCTLR, 2169 ((sc->rtsx_cmd_index * 4) & 0x00ffffff) | RTSX_START_CMD | RTSX_HW_AUTO_RSP); 2170 } 2171 2172 /* 2173 * Stop previous command. 2174 */ 2175 static void 2176 rtsx_stop_cmd(struct rtsx_softc *sc) 2177 { 2178 /* Stop command transfer. */ 2179 WRITE4(sc, RTSX_HCBCTLR, RTSX_STOP_CMD); 2180 2181 /* Stop DMA transfer. */ 2182 WRITE4(sc, RTSX_HDBCTLR, RTSX_STOP_DMA); 2183 2184 rtsx_write(sc, RTSX_DMACTL, RTSX_DMA_RST, RTSX_DMA_RST); 2185 2186 rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH); 2187 } 2188 2189 /* 2190 * Clear error. 2191 */ 2192 static void 2193 rtsx_clear_error(struct rtsx_softc *sc) 2194 { 2195 /* Clear error. */ 2196 rtsx_write(sc, RTSX_CARD_STOP, RTSX_SD_STOP | RTSX_SD_CLR_ERR, 2197 RTSX_SD_STOP | RTSX_SD_CLR_ERR); 2198 } 2199 2200 /* 2201 * Signal end of request to mmc/mmcsd. 2202 */ 2203 static void 2204 rtsx_req_done(struct rtsx_softc *sc) 2205 { 2206 #ifdef MMCCAM 2207 union ccb *ccb; 2208 #endif /* MMCCAM */ 2209 struct mmc_request *req; 2210 2211 req = sc->rtsx_req; 2212 if (req->cmd->error == MMC_ERR_NONE) { 2213 if (req->cmd->opcode == MMC_READ_SINGLE_BLOCK || 2214 req->cmd->opcode == MMC_READ_MULTIPLE_BLOCK) 2215 sc->rtsx_read_count++; 2216 else if (req->cmd->opcode == MMC_WRITE_BLOCK || 2217 req->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK) 2218 sc->rtsx_write_count++; 2219 } else { 2220 rtsx_clear_error(sc); 2221 } 2222 callout_stop(&sc->rtsx_timeout_callout); 2223 sc->rtsx_req = NULL; 2224 #ifdef MMCCAM 2225 ccb = sc->rtsx_ccb; 2226 sc->rtsx_ccb = NULL; 2227 ccb->ccb_h.status = (req->cmd->error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); 2228 xpt_done(ccb); 2229 #else /* !MMCCAM */ 2230 req->done(req); 2231 #endif /* MMCCAM */ 2232 } 2233 2234 /* 2235 * Send request. 2236 */ 2237 static int 2238 rtsx_send_req(struct rtsx_softc *sc, struct mmc_command *cmd) 2239 { 2240 uint8_t rsp_type; 2241 uint16_t reg; 2242 2243 if (bootverbose) 2244 device_printf(sc->rtsx_dev, "rtsx_send_req() - CMD%d\n", cmd->opcode); 2245 2246 /* Convert response type. */ 2247 rsp_type = rtsx_response_type(cmd->flags & MMC_RSP_MASK); 2248 if (rsp_type == 0) { 2249 device_printf(sc->rtsx_dev, "Unknown rsp_type: 0x%lx\n", (cmd->flags & MMC_RSP_MASK)); 2250 cmd->error = MMC_ERR_INVALID; 2251 return (MMC_ERR_INVALID); 2252 } 2253 2254 rtsx_init_cmd(sc, cmd); 2255 2256 /* Queue command to set response type. */ 2257 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, rsp_type); 2258 2259 /* Use the ping-pong buffer (cmd buffer) for commands which do not transfer data. */ 2260 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 2261 0x01, RTSX_PINGPONG_BUFFER); 2262 2263 /* Queue commands to perform SD transfer. */ 2264 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 2265 0xff, RTSX_TM_CMD_RSP | RTSX_SD_TRANSFER_START); 2266 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2267 RTSX_SD_TRANSFER_END|RTSX_SD_STAT_IDLE, 2268 RTSX_SD_TRANSFER_END|RTSX_SD_STAT_IDLE); 2269 2270 /* If needed queue commands to read back card status response. */ 2271 if (rsp_type == RTSX_SD_RSP_TYPE_R2) { 2272 /* Read data from ping-pong buffer. */ 2273 for (reg = RTSX_PPBUF_BASE2; reg < RTSX_PPBUF_BASE2 + 16; reg++) 2274 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg, 0, 0); 2275 } else if (rsp_type != RTSX_SD_RSP_TYPE_R0) { 2276 /* Read data from SD_CMDx registers. */ 2277 for (reg = RTSX_SD_CMD0; reg <= RTSX_SD_CMD4; reg++) 2278 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg, 0, 0); 2279 } 2280 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, RTSX_SD_STAT1, 0, 0); 2281 2282 /* Set transfer OK function. */ 2283 if (sc->rtsx_intr_trans_ok == NULL) 2284 sc->rtsx_intr_trans_ok = rtsx_ret_resp; 2285 2286 /* Run the command queue. */ 2287 rtsx_send_cmd(sc); 2288 2289 return (0); 2290 } 2291 2292 /* 2293 * Return response of previous command (case cmd->data == NULL) and complete resquest. 2294 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2295 */ 2296 static void 2297 rtsx_ret_resp(struct rtsx_softc *sc) 2298 { 2299 struct mmc_command *cmd; 2300 2301 cmd = sc->rtsx_req->cmd; 2302 rtsx_set_resp(sc, cmd); 2303 rtsx_req_done(sc); 2304 } 2305 2306 /* 2307 * Set response of previous command. 2308 */ 2309 static void 2310 rtsx_set_resp(struct rtsx_softc *sc, struct mmc_command *cmd) 2311 { 2312 uint8_t rsp_type; 2313 2314 rsp_type = rtsx_response_type(cmd->flags & MMC_RSP_MASK); 2315 2316 /* Sync command DMA buffer. */ 2317 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTREAD); 2318 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTWRITE); 2319 2320 /* Copy card response into mmc response buffer. */ 2321 if (ISSET(cmd->flags, MMC_RSP_PRESENT)) { 2322 uint32_t *cmd_buffer = (uint32_t *)(sc->rtsx_cmd_dmamem); 2323 2324 if (bootverbose) { 2325 device_printf(sc->rtsx_dev, "cmd_buffer: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", 2326 cmd_buffer[0], cmd_buffer[1], cmd_buffer[2], cmd_buffer[3], cmd_buffer[4]); 2327 } 2328 2329 if (rsp_type == RTSX_SD_RSP_TYPE_R2) { 2330 /* First byte is CHECK_REG_CMD return value, skip it. */ 2331 unsigned char *ptr = (unsigned char *)cmd_buffer + 1; 2332 int i; 2333 2334 /* 2335 * The controller offloads the last byte {CRC-7, end bit 1} 2336 * of response type R2. Assign dummy CRC, 0, and end bit to this 2337 * byte (ptr[16], goes into the LSB of resp[3] later). 2338 */ 2339 ptr[16] = 0x01; 2340 /* The second byte is the status of response, skip it. */ 2341 for (i = 0; i < 4; i++) 2342 cmd->resp[i] = be32dec(ptr + 1 + i * 4); 2343 } else { 2344 /* 2345 * First byte is CHECK_REG_CMD return value, second 2346 * one is the command op code -- we skip those. 2347 */ 2348 cmd->resp[0] = 2349 ((be32toh(cmd_buffer[0]) & 0x0000ffff) << 16) | 2350 ((be32toh(cmd_buffer[1]) & 0xffff0000) >> 16); 2351 } 2352 2353 if (bootverbose) 2354 device_printf(sc->rtsx_dev, "cmd->resp: 0x%08x 0x%08x 0x%08x 0x%08x\n", 2355 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); 2356 } 2357 } 2358 2359 /* 2360 * Use the ping-pong buffer (cmd buffer) for transfer <= 512 bytes. 2361 */ 2362 static int 2363 rtsx_xfer_short(struct rtsx_softc *sc, struct mmc_command *cmd) 2364 { 2365 int read; 2366 2367 if (cmd->data == NULL || cmd->data->len == 0) { 2368 cmd->error = MMC_ERR_INVALID; 2369 return (MMC_ERR_INVALID); 2370 } 2371 cmd->data->xfer_len = (cmd->data->len > RTSX_MAX_DATA_BLKLEN) ? 2372 RTSX_MAX_DATA_BLKLEN : cmd->data->len; 2373 2374 read = ISSET(cmd->data->flags, MMC_DATA_READ); 2375 2376 if (bootverbose) 2377 device_printf(sc->rtsx_dev, "rtsx_xfer_short() - %s xfer: %ld bytes with block size %ld\n", 2378 read ? "Read" : "Write", 2379 (unsigned long)cmd->data->len, (unsigned long)cmd->data->xfer_len); 2380 2381 if (cmd->data->len > 512) { 2382 device_printf(sc->rtsx_dev, "rtsx_xfer_short() - length too large: %ld > 512\n", 2383 (unsigned long)cmd->data->len); 2384 cmd->error = MMC_ERR_INVALID; 2385 return (MMC_ERR_INVALID); 2386 } 2387 2388 if (read) { 2389 if (sc->rtsx_discovery_mode) 2390 rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, RTSX_CLK_DIVIDE_0); 2391 2392 rtsx_init_cmd(sc, cmd); 2393 2394 /* Queue commands to configure data transfer size. */ 2395 rtsx_set_cmd_data_len(sc, cmd->data->len / cmd->data->xfer_len, cmd->data->xfer_len); 2396 2397 /* From Linux: rtsx_pci_sdmmc.c sd_read_data(). */ 2398 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, 2399 RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC16 | 2400 RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_CHECK_CRC7 | RTSX_SD_RSP_LEN_6); 2401 2402 /* Use the ping-pong buffer (cmd buffer). */ 2403 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 2404 0x01, RTSX_PINGPONG_BUFFER); 2405 2406 /* Queue commands to perform SD transfer. */ 2407 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 2408 0xff, RTSX_TM_NORMAL_READ | RTSX_SD_TRANSFER_START); 2409 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2410 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 2411 2412 /* Set transfer OK function. */ 2413 sc->rtsx_intr_trans_ok = rtsx_ask_ppbuf_part1; 2414 2415 /* Run the command queue. */ 2416 rtsx_send_cmd(sc); 2417 } else { 2418 /* Set transfer OK function. */ 2419 sc->rtsx_intr_trans_ok = rtsx_put_ppbuf_part1; 2420 2421 /* Run the command queue. */ 2422 rtsx_send_req(sc, cmd); 2423 } 2424 2425 return (0); 2426 } 2427 2428 /* 2429 * Use the ping-pong buffer (cmd buffer) for the transfer - first part <= 256 bytes. 2430 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2431 */ 2432 static void 2433 rtsx_ask_ppbuf_part1(struct rtsx_softc *sc) 2434 { 2435 struct mmc_command *cmd; 2436 uint16_t reg = RTSX_PPBUF_BASE2; 2437 int len; 2438 int i; 2439 2440 cmd = sc->rtsx_req->cmd; 2441 len = (cmd->data->len > RTSX_HOSTCMD_MAX) ? RTSX_HOSTCMD_MAX : cmd->data->len; 2442 2443 sc->rtsx_cmd_index = 0; 2444 for (i = 0; i < len; i++) { 2445 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg++, 0, 0); 2446 } 2447 2448 /* Set transfer OK function. */ 2449 sc->rtsx_intr_trans_ok = rtsx_get_ppbuf_part1; 2450 2451 /* Run the command queue. */ 2452 rtsx_send_cmd(sc); 2453 } 2454 2455 /* 2456 * Get the data from the ping-pong buffer (cmd buffer) - first part <= 256 bytes. 2457 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2458 */ 2459 static void 2460 rtsx_get_ppbuf_part1(struct rtsx_softc *sc) 2461 { 2462 struct mmc_command *cmd; 2463 uint8_t *ptr; 2464 int len; 2465 2466 cmd = sc->rtsx_req->cmd; 2467 ptr = cmd->data->data; 2468 len = (cmd->data->len > RTSX_HOSTCMD_MAX) ? RTSX_HOSTCMD_MAX : cmd->data->len; 2469 2470 /* Sync command DMA buffer. */ 2471 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTREAD); 2472 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTWRITE); 2473 2474 memcpy(ptr, sc->rtsx_cmd_dmamem, len); 2475 2476 len = (cmd->data->len > RTSX_HOSTCMD_MAX) ? cmd->data->len - RTSX_HOSTCMD_MAX : 0; 2477 2478 /* Use the ping-pong buffer (cmd buffer) for the transfer - second part > 256 bytes. */ 2479 if (len > 0) { 2480 uint16_t reg = RTSX_PPBUF_BASE2 + RTSX_HOSTCMD_MAX; 2481 int i; 2482 2483 sc->rtsx_cmd_index = 0; 2484 for (i = 0; i < len; i++) { 2485 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg++, 0, 0); 2486 } 2487 2488 /* Set transfer OK function. */ 2489 sc->rtsx_intr_trans_ok = rtsx_get_ppbuf_part2; 2490 2491 /* Run the command queue. */ 2492 rtsx_send_cmd(sc); 2493 } else { 2494 if (bootverbose && cmd->opcode == ACMD_SEND_SCR) { 2495 uint8_t *ptr = cmd->data->data; 2496 device_printf(sc->rtsx_dev, "SCR: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n", 2497 ptr[0], ptr[1], ptr[2], ptr[3], 2498 ptr[4], ptr[5], ptr[6], ptr[7]); 2499 } 2500 2501 if (sc->rtsx_discovery_mode) 2502 rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, RTSX_CLK_DIVIDE_128); 2503 2504 rtsx_req_done(sc); 2505 } 2506 } 2507 2508 /* 2509 * Get the data from the ping-pong buffer (cmd buffer) - second part > 256 bytes. 2510 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2511 */ 2512 static void 2513 rtsx_get_ppbuf_part2(struct rtsx_softc *sc) 2514 { 2515 struct mmc_command *cmd; 2516 uint8_t *ptr; 2517 int len; 2518 2519 cmd = sc->rtsx_req->cmd; 2520 ptr = cmd->data->data; 2521 ptr += RTSX_HOSTCMD_MAX; 2522 len = cmd->data->len - RTSX_HOSTCMD_MAX; 2523 2524 /* Sync command DMA buffer. */ 2525 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTREAD); 2526 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTWRITE); 2527 2528 memcpy(ptr, sc->rtsx_cmd_dmamem, len); 2529 2530 if (sc->rtsx_discovery_mode) 2531 rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, RTSX_CLK_DIVIDE_128); 2532 2533 rtsx_req_done(sc); 2534 } 2535 2536 /* 2537 * Use the ping-pong buffer (cmd buffer) for transfer - first part <= 256 bytes. 2538 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2539 */ 2540 static void 2541 rtsx_put_ppbuf_part1(struct rtsx_softc *sc) 2542 { 2543 struct mmc_command *cmd; 2544 uint16_t reg = RTSX_PPBUF_BASE2; 2545 uint8_t *ptr; 2546 int len; 2547 int i; 2548 2549 cmd = sc->rtsx_req->cmd; 2550 ptr = cmd->data->data; 2551 len = (cmd->data->len > RTSX_HOSTCMD_MAX) ? RTSX_HOSTCMD_MAX : cmd->data->len; 2552 2553 rtsx_set_resp(sc, cmd); 2554 2555 sc->rtsx_cmd_index = 0; 2556 for (i = 0; i < len; i++) { 2557 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, reg++, 0xff, *ptr); 2558 ptr++; 2559 } 2560 2561 /* Set transfer OK function. */ 2562 if (cmd->data->len > RTSX_HOSTCMD_MAX) 2563 sc->rtsx_intr_trans_ok = rtsx_put_ppbuf_part2; 2564 else 2565 sc->rtsx_intr_trans_ok = rtsx_write_ppbuf; 2566 2567 /* Run the command queue. */ 2568 rtsx_send_cmd(sc); 2569 } 2570 2571 /* 2572 * Use the ping-pong buffer (cmd buffer) for transfer - second part > 256 bytes. 2573 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2574 */ 2575 static void 2576 rtsx_put_ppbuf_part2(struct rtsx_softc *sc) 2577 { 2578 struct mmc_command *cmd; 2579 uint16_t reg = RTSX_PPBUF_BASE2 + RTSX_HOSTCMD_MAX; 2580 uint8_t *ptr; 2581 int len; 2582 int i; 2583 2584 cmd = sc->rtsx_req->cmd; 2585 ptr = cmd->data->data; 2586 ptr += RTSX_HOSTCMD_MAX; 2587 len = cmd->data->len - RTSX_HOSTCMD_MAX; 2588 2589 sc->rtsx_cmd_index = 0; 2590 for (i = 0; i < len; i++) { 2591 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, reg++, 0xff, *ptr); 2592 ptr++; 2593 } 2594 2595 /* Set transfer OK function. */ 2596 sc->rtsx_intr_trans_ok = rtsx_write_ppbuf; 2597 2598 /* Run the command queue. */ 2599 rtsx_send_cmd(sc); 2600 } 2601 2602 /* 2603 * Write the data previously given via the ping-pong buffer on the card. 2604 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2605 */ 2606 static void 2607 rtsx_write_ppbuf(struct rtsx_softc *sc) 2608 { 2609 struct mmc_command *cmd; 2610 2611 cmd = sc->rtsx_req->cmd; 2612 2613 sc->rtsx_cmd_index = 0; 2614 2615 /* Queue commands to configure data transfer size. */ 2616 rtsx_set_cmd_data_len(sc, cmd->data->len / cmd->data->xfer_len, cmd->data->xfer_len); 2617 2618 /* From Linux: rtsx_pci_sdmmc.c sd_write_data(). */ 2619 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, 2620 RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC16 | 2621 RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_CHECK_CRC7 | RTSX_SD_RSP_LEN_0); 2622 2623 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 0xff, 2624 RTSX_TM_AUTO_WRITE3 | RTSX_SD_TRANSFER_START); 2625 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2626 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 2627 2628 /* Set transfer OK function. */ 2629 sc->rtsx_intr_trans_ok = rtsx_req_done; 2630 2631 /* Run the command queue. */ 2632 rtsx_send_cmd(sc); 2633 } 2634 2635 /* 2636 * Use the data buffer for transfer > 512 bytes. 2637 */ 2638 static int 2639 rtsx_xfer(struct rtsx_softc *sc, struct mmc_command *cmd) 2640 { 2641 int read = ISSET(cmd->data->flags, MMC_DATA_READ); 2642 2643 cmd->data->xfer_len = (cmd->data->len > RTSX_MAX_DATA_BLKLEN) ? 2644 RTSX_MAX_DATA_BLKLEN : cmd->data->len; 2645 2646 if (bootverbose) 2647 device_printf(sc->rtsx_dev, "rtsx_xfer() - %s xfer: %ld bytes with block size %ld\n", 2648 read ? "Read" : "Write", 2649 (unsigned long)cmd->data->len, (unsigned long)cmd->data->xfer_len); 2650 2651 if (cmd->data->len > RTSX_DMA_DATA_BUFSIZE) { 2652 device_printf(sc->rtsx_dev, "rtsx_xfer() length too large: %ld > %d\n", 2653 (unsigned long)cmd->data->len, RTSX_DMA_DATA_BUFSIZE); 2654 cmd->error = MMC_ERR_INVALID; 2655 return (MMC_ERR_INVALID); 2656 } 2657 2658 if (!read) { 2659 /* Set transfer OK function. */ 2660 sc->rtsx_intr_trans_ok = rtsx_xfer_begin; 2661 2662 /* Run the command queue. */ 2663 rtsx_send_req(sc, cmd); 2664 } else { 2665 rtsx_xfer_start(sc); 2666 } 2667 2668 return (0); 2669 } 2670 2671 /* 2672 * Get request response and start dma data transfer (write command). 2673 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2674 */ 2675 static void 2676 rtsx_xfer_begin(struct rtsx_softc *sc) 2677 { 2678 struct mmc_command *cmd; 2679 2680 cmd = sc->rtsx_req->cmd; 2681 2682 if (bootverbose) 2683 device_printf(sc->rtsx_dev, "rtsx_xfer_begin() - CMD%d\n", cmd->opcode); 2684 2685 rtsx_set_resp(sc, cmd); 2686 rtsx_xfer_start(sc); 2687 } 2688 2689 /* 2690 * Start dma data transfer. 2691 */ 2692 static void 2693 rtsx_xfer_start(struct rtsx_softc *sc) 2694 { 2695 struct mmc_command *cmd; 2696 int read; 2697 uint8_t cfg2; 2698 int dma_dir; 2699 int tmode; 2700 2701 cmd = sc->rtsx_req->cmd; 2702 read = ISSET(cmd->data->flags, MMC_DATA_READ); 2703 2704 /* Configure DMA transfer mode parameters. */ 2705 if (cmd->opcode == MMC_READ_MULTIPLE_BLOCK) 2706 cfg2 = RTSX_SD_CHECK_CRC16 | RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_RSP_LEN_6; 2707 else 2708 cfg2 = RTSX_SD_CHECK_CRC16 | RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_RSP_LEN_0; 2709 if (read) { 2710 dma_dir = RTSX_DMA_DIR_FROM_CARD; 2711 /* 2712 * Use transfer mode AUTO_READ1, which assume we not 2713 * already send the read command and don't need to send 2714 * CMD 12 manually after read. 2715 */ 2716 tmode = RTSX_TM_AUTO_READ1; 2717 cfg2 |= RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC7; 2718 2719 rtsx_init_cmd(sc, cmd); 2720 } else { 2721 dma_dir = RTSX_DMA_DIR_TO_CARD; 2722 /* 2723 * Use transfer mode AUTO_WRITE3, wich assumes we've already 2724 * sent the write command and gotten the response, and will 2725 * send CMD 12 manually after writing. 2726 */ 2727 tmode = RTSX_TM_AUTO_WRITE3; 2728 cfg2 |= RTSX_SD_NO_CALCULATE_CRC7 | RTSX_SD_NO_CHECK_CRC7; 2729 2730 sc->rtsx_cmd_index = 0; 2731 } 2732 2733 /* Queue commands to configure data transfer size. */ 2734 rtsx_set_cmd_data_len(sc, cmd->data->len / cmd->data->xfer_len, cmd->data->xfer_len); 2735 2736 /* Configure DMA controller. */ 2737 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_IRQSTAT0, 2738 RTSX_DMA_DONE_INT, RTSX_DMA_DONE_INT); 2739 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC3, 2740 0xff, cmd->data->len >> 24); 2741 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC2, 2742 0xff, cmd->data->len >> 16); 2743 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC1, 2744 0xff, cmd->data->len >> 8); 2745 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC0, 2746 0xff, cmd->data->len); 2747 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMACTL, 2748 RTSX_DMA_EN | RTSX_DMA_DIR | RTSX_DMA_PACK_SIZE_MASK, 2749 RTSX_DMA_EN | dma_dir | RTSX_DMA_512); 2750 2751 /* Use the DMA ring buffer for commands which transfer data. */ 2752 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 2753 0x01, RTSX_RING_BUFFER); 2754 2755 /* Queue command to set response type. */ 2756 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, cfg2); 2757 2758 /* Queue commands to perform SD transfer. */ 2759 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 2760 0xff, tmode | RTSX_SD_TRANSFER_START); 2761 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2762 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 2763 2764 /* Run the command queue. */ 2765 rtsx_send_cmd(sc); 2766 2767 if (!read) 2768 memcpy(sc->rtsx_data_dmamem, cmd->data->data, cmd->data->len); 2769 2770 /* Sync data DMA buffer. */ 2771 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_PREREAD); 2772 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_PREWRITE); 2773 2774 /* Set transfer OK function. */ 2775 sc->rtsx_intr_trans_ok = rtsx_xfer_finish; 2776 2777 /* Tell the chip where the data buffer is and run the transfer. */ 2778 WRITE4(sc, RTSX_HDBAR, sc->rtsx_data_buffer); 2779 WRITE4(sc, RTSX_HDBCTLR, RTSX_TRIG_DMA | (read ? RTSX_DMA_READ : 0) | 2780 (cmd->data->len & 0x00ffffff)); 2781 } 2782 2783 /* 2784 * Finish dma data transfer. 2785 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2786 */ 2787 static void 2788 rtsx_xfer_finish(struct rtsx_softc *sc) 2789 { 2790 struct mmc_command *cmd; 2791 int read; 2792 2793 cmd = sc->rtsx_req->cmd; 2794 2795 if (bootverbose) 2796 device_printf(sc->rtsx_dev, "rtsx_xfer_finish() - CMD%d\n", cmd->opcode); 2797 2798 read = ISSET(cmd->data->flags, MMC_DATA_READ); 2799 2800 /* Sync data DMA buffer. */ 2801 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_POSTREAD); 2802 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_POSTWRITE); 2803 2804 if (read) { 2805 memcpy(cmd->data->data, sc->rtsx_data_dmamem, cmd->data->len); 2806 rtsx_req_done(sc); 2807 } else { 2808 /* Send CMD12 after AUTO_WRITE3 (see mmcsd_rw() in mmcsd.c) */ 2809 /* and complete request. */ 2810 sc->rtsx_intr_trans_ok = NULL; 2811 rtsx_send_req(sc, sc->rtsx_req->stop); 2812 } 2813 } 2814 2815 /* 2816 * Manage request timeout. 2817 */ 2818 static void 2819 rtsx_timeout(void *arg) 2820 { 2821 struct rtsx_softc *sc; 2822 2823 sc = (struct rtsx_softc *)arg; 2824 if (sc->rtsx_req != NULL) { 2825 device_printf(sc->rtsx_dev, "Controller timeout for CMD%u\n", 2826 sc->rtsx_req->cmd->opcode); 2827 sc->rtsx_req->cmd->error = MMC_ERR_TIMEOUT; 2828 rtsx_stop_cmd(sc); 2829 rtsx_req_done(sc); 2830 } else { 2831 device_printf(sc->rtsx_dev, "Controller timeout!\n"); 2832 } 2833 } 2834 2835 #ifdef MMCCAM 2836 static int 2837 rtsx_get_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts) 2838 { 2839 struct rtsx_softc *sc; 2840 2841 sc = device_get_softc(dev); 2842 2843 cts->host_ocr = sc->rtsx_host.host_ocr; 2844 cts->host_f_min = sc->rtsx_host.f_min; 2845 cts->host_f_max = sc->rtsx_host.f_max; 2846 cts->host_caps = sc->rtsx_host.caps; 2847 cts->host_max_data = RTSX_DMA_DATA_BUFSIZE / MMC_SECTOR_SIZE; 2848 memcpy(&cts->ios, &sc->rtsx_host.ios, sizeof(struct mmc_ios)); 2849 2850 return (0); 2851 } 2852 2853 /* 2854 * Apply settings and return status accordingly. 2855 */ 2856 static int 2857 rtsx_set_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts) 2858 { 2859 struct rtsx_softc *sc; 2860 struct mmc_ios *ios; 2861 struct mmc_ios *new_ios; 2862 2863 sc = device_get_softc(dev); 2864 2865 ios = &sc->rtsx_host.ios; 2866 new_ios = &cts->ios; 2867 2868 /* Update only requested fields */ 2869 if (cts->ios_valid & MMC_CLK) { 2870 ios->clock = new_ios->clock; 2871 sc->rtsx_ios_clock = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 2872 if (bootverbose || sc->rtsx_debug) 2873 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - clock: %u\n", ios->clock); 2874 } 2875 if (cts->ios_valid & MMC_VDD) { 2876 ios->vdd = new_ios->vdd; 2877 if (bootverbose || sc->rtsx_debug) 2878 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - vdd: %d\n", ios->vdd); 2879 } 2880 if (cts->ios_valid & MMC_CS) { 2881 ios->chip_select = new_ios->chip_select; 2882 if (bootverbose || sc->rtsx_debug) 2883 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - chip_select: %d\n", ios->chip_select); 2884 } 2885 if (cts->ios_valid & MMC_BW) { 2886 ios->bus_width = new_ios->bus_width; 2887 sc->rtsx_ios_bus_width = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 2888 if (bootverbose || sc->rtsx_debug) 2889 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - bus width: %d\n", ios->bus_width); 2890 } 2891 if (cts->ios_valid & MMC_PM) { 2892 ios->power_mode = new_ios->power_mode; 2893 sc->rtsx_ios_power_mode = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 2894 if (bootverbose || sc->rtsx_debug) 2895 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - power mode: %d\n", ios->power_mode); 2896 } 2897 if (cts->ios_valid & MMC_BT) { 2898 ios->timing = new_ios->timing; 2899 sc->rtsx_ios_timing = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 2900 if (bootverbose || sc->rtsx_debug) 2901 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - timing: %d\n", ios->timing); 2902 } 2903 if (cts->ios_valid & MMC_BM) { 2904 ios->bus_mode = new_ios->bus_mode; 2905 if (bootverbose || sc->rtsx_debug) 2906 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - bus mode: %d\n", ios->bus_mode); 2907 } 2908 #if __FreeBSD_version >= 1300000 2909 if (cts->ios_valid & MMC_VCCQ) { 2910 ios->vccq = new_ios->vccq; 2911 sc->rtsx_ios_vccq = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 2912 if (bootverbose || sc->rtsx_debug) 2913 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - vccq: %d\n", ios->vccq); 2914 } 2915 #endif /* __FreeBSD_version >= 1300000 */ 2916 if (rtsx_mmcbr_update_ios(sc->rtsx_dev, NULL) == 0) 2917 return (CAM_REQ_CMP); 2918 else 2919 return (CAM_REQ_CMP_ERR); 2920 } 2921 2922 /* 2923 * Build a request and run it. 2924 */ 2925 static int 2926 rtsx_cam_request(device_t dev, union ccb *ccb) 2927 { 2928 struct rtsx_softc *sc; 2929 2930 sc = device_get_softc(dev); 2931 2932 RTSX_LOCK(sc); 2933 if (sc->rtsx_ccb != NULL) { 2934 RTSX_UNLOCK(sc); 2935 return (CAM_BUSY); 2936 } 2937 sc->rtsx_ccb = ccb; 2938 sc->rtsx_cam_req.cmd = &ccb->mmcio.cmd; 2939 sc->rtsx_cam_req.stop = &ccb->mmcio.stop; 2940 RTSX_UNLOCK(sc); 2941 2942 rtsx_mmcbr_request(sc->rtsx_dev, NULL, &sc->rtsx_cam_req); 2943 return (0); 2944 } 2945 #endif /* MMCCAM */ 2946 2947 static int 2948 rtsx_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 2949 { 2950 struct rtsx_softc *sc; 2951 2952 sc = device_get_softc(bus); 2953 switch (which) { 2954 case MMCBR_IVAR_BUS_MODE: /* ivar 0 - 1 = opendrain, 2 = pushpull */ 2955 *result = sc->rtsx_host.ios.bus_mode; 2956 break; 2957 case MMCBR_IVAR_BUS_WIDTH: /* ivar 1 - 0 = 1b 2 = 4b, 3 = 8b */ 2958 *result = sc->rtsx_host.ios.bus_width; 2959 break; 2960 case MMCBR_IVAR_CHIP_SELECT: /* ivar 2 - O = dontcare, 1 = cs_high, 2 = cs_low */ 2961 *result = sc->rtsx_host.ios.chip_select; 2962 break; 2963 case MMCBR_IVAR_CLOCK: /* ivar 3 - clock in Hz */ 2964 *result = sc->rtsx_host.ios.clock; 2965 break; 2966 case MMCBR_IVAR_F_MIN: /* ivar 4 */ 2967 *result = sc->rtsx_host.f_min; 2968 break; 2969 case MMCBR_IVAR_F_MAX: /* ivar 5 */ 2970 *result = sc->rtsx_host.f_max; 2971 break; 2972 case MMCBR_IVAR_HOST_OCR: /* ivar 6 - host operation conditions register */ 2973 *result = sc->rtsx_host.host_ocr; 2974 break; 2975 case MMCBR_IVAR_MODE: /* ivar 7 - 0 = mode_mmc, 1 = mode_sd */ 2976 *result = sc->rtsx_host.mode; 2977 break; 2978 case MMCBR_IVAR_OCR: /* ivar 8 - operation conditions register */ 2979 *result = sc->rtsx_host.ocr; 2980 break; 2981 case MMCBR_IVAR_POWER_MODE: /* ivar 9 - 0 = off, 1 = up, 2 = on */ 2982 *result = sc->rtsx_host.ios.power_mode; 2983 break; 2984 case MMCBR_IVAR_VDD: /* ivar 11 - voltage power pin */ 2985 *result = sc->rtsx_host.ios.vdd; 2986 break; 2987 case MMCBR_IVAR_VCCQ: /* ivar 12 - signaling: 0 = 1.20V, 1 = 1.80V, 2 = 3.30V */ 2988 *result = sc->rtsx_host.ios.vccq; 2989 break; 2990 case MMCBR_IVAR_CAPS: /* ivar 13 */ 2991 *result = sc->rtsx_host.caps; 2992 break; 2993 case MMCBR_IVAR_TIMING: /* ivar 14 - 0 = normal, 1 = timing_hs, ... */ 2994 *result = sc->rtsx_host.ios.timing; 2995 break; 2996 case MMCBR_IVAR_MAX_DATA: /* ivar 15 */ 2997 *result = RTSX_DMA_DATA_BUFSIZE / MMC_SECTOR_SIZE; 2998 break; 2999 case MMCBR_IVAR_RETUNE_REQ: /* ivar 10 */ 3000 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: /* ivar 16 */ 3001 default: 3002 return (EINVAL); 3003 } 3004 3005 if (bootverbose) 3006 device_printf(bus, "Read ivar #%d, value %#x / #%d\n", 3007 which, *(int *)result, *(int *)result); 3008 3009 return (0); 3010 } 3011 3012 static int 3013 rtsx_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 3014 { 3015 struct rtsx_softc *sc; 3016 3017 if (bootverbose) 3018 device_printf(bus, "Write ivar #%d, value %#x / #%d\n", 3019 which, (int)value, (int)value); 3020 3021 sc = device_get_softc(bus); 3022 switch (which) { 3023 case MMCBR_IVAR_BUS_MODE: /* ivar 0 - 1 = opendrain, 2 = pushpull */ 3024 sc->rtsx_host.ios.bus_mode = value; 3025 break; 3026 case MMCBR_IVAR_BUS_WIDTH: /* ivar 1 - 0 = 1b 2 = 4b, 3 = 8b */ 3027 sc->rtsx_host.ios.bus_width = value; 3028 sc->rtsx_ios_bus_width = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */ 3029 break; 3030 case MMCBR_IVAR_CHIP_SELECT: /* ivar 2 - O = dontcare, 1 = cs_high, 2 = cs_low */ 3031 sc->rtsx_host.ios.chip_select = value; 3032 break; 3033 case MMCBR_IVAR_CLOCK: /* ivar 3 - clock in Hz */ 3034 sc->rtsx_host.ios.clock = value; 3035 sc->rtsx_ios_clock = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */ 3036 break; 3037 case MMCBR_IVAR_MODE: /* ivar 7 - 0 = mode_mmc, 1 = mode_sd */ 3038 sc->rtsx_host.mode = value; 3039 break; 3040 case MMCBR_IVAR_OCR: /* ivar 8 - operation conditions register */ 3041 sc->rtsx_host.ocr = value; 3042 break; 3043 case MMCBR_IVAR_POWER_MODE: /* ivar 9 - 0 = off, 1 = up, 2 = on */ 3044 sc->rtsx_host.ios.power_mode = value; 3045 sc->rtsx_ios_power_mode = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */ 3046 break; 3047 case MMCBR_IVAR_VDD: /* ivar 11 - voltage power pin */ 3048 sc->rtsx_host.ios.vdd = value; 3049 break; 3050 case MMCBR_IVAR_VCCQ: /* ivar 12 - signaling: 0 = 1.20V, 1 = 1.80V, 2 = 3.30V */ 3051 sc->rtsx_host.ios.vccq = value; 3052 sc->rtsx_ios_vccq = value; /* rtsx_mmcbr_switch_vccq() will be called by mmc.c (MMCCAM undef). */ 3053 break; 3054 case MMCBR_IVAR_TIMING: /* ivar 14 - 0 = normal, 1 = timing_hs, ... */ 3055 sc->rtsx_host.ios.timing = value; 3056 sc->rtsx_ios_timing = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */ 3057 break; 3058 /* These are read-only. */ 3059 case MMCBR_IVAR_F_MIN: /* ivar 4 */ 3060 case MMCBR_IVAR_F_MAX: /* ivar 5 */ 3061 case MMCBR_IVAR_HOST_OCR: /* ivar 6 - host operation conditions register */ 3062 case MMCBR_IVAR_RETUNE_REQ: /* ivar 10 */ 3063 case MMCBR_IVAR_CAPS: /* ivar 13 */ 3064 case MMCBR_IVAR_MAX_DATA: /* ivar 15 */ 3065 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: /* ivar 16 */ 3066 default: 3067 return (EINVAL); 3068 } 3069 3070 return (0); 3071 } 3072 3073 static int 3074 rtsx_mmcbr_update_ios(device_t bus, device_t child__unused) 3075 { 3076 struct rtsx_softc *sc; 3077 struct mmc_ios *ios; 3078 int error; 3079 3080 sc = device_get_softc(bus); 3081 ios = &sc->rtsx_host.ios; 3082 3083 if (bootverbose) 3084 device_printf(bus, "rtsx_mmcbr_update_ios()\n"); 3085 3086 /* if MMCBR_IVAR_BUS_WIDTH updated. */ 3087 if (sc->rtsx_ios_bus_width < 0) { 3088 sc->rtsx_ios_bus_width = ios->bus_width; 3089 if ((error = rtsx_set_bus_width(sc, ios->bus_width))) 3090 return (error); 3091 } 3092 3093 /* if MMCBR_IVAR_POWER_MODE updated. */ 3094 if (sc->rtsx_ios_power_mode < 0) { 3095 sc->rtsx_ios_power_mode = ios->power_mode; 3096 switch (ios->power_mode) { 3097 case power_off: 3098 if ((error = rtsx_bus_power_off(sc))) 3099 return (error); 3100 break; 3101 case power_up: 3102 if ((error = rtsx_bus_power_on(sc))) 3103 return (error); 3104 break; 3105 case power_on: 3106 if ((error = rtsx_bus_power_on(sc))) 3107 return (error); 3108 break; 3109 } 3110 } 3111 3112 sc->rtsx_double_clk = true; 3113 sc->rtsx_vpclk = false; 3114 3115 /* if MMCBR_IVAR_TIMING updated. */ 3116 if (sc->rtsx_ios_timing < 0) { 3117 sc->rtsx_ios_timing = ios->timing; 3118 if ((error = rtsx_set_sd_timing(sc, ios->timing))) 3119 return (error); 3120 } 3121 3122 /* if MMCBR_IVAR_CLOCK updated, must be after rtsx_set_sd_timing() */ 3123 if (sc->rtsx_ios_clock < 0) { 3124 sc->rtsx_ios_clock = ios->clock; 3125 if ((error = rtsx_set_sd_clock(sc, ios->clock))) 3126 return (error); 3127 } 3128 3129 /* if MMCCAM and vccq updated */ 3130 if (sc->rtsx_ios_vccq < 0) { 3131 sc->rtsx_ios_vccq = ios->vccq; 3132 if ((error = rtsx_mmcbr_switch_vccq(sc->rtsx_dev, NULL))) 3133 return (error); 3134 } 3135 3136 return (0); 3137 } 3138 3139 /* 3140 * Set output stage logic power voltage. 3141 */ 3142 static int 3143 rtsx_mmcbr_switch_vccq(device_t bus, device_t child __unused) 3144 { 3145 struct rtsx_softc *sc; 3146 int vccq = 0; 3147 int error; 3148 3149 sc = device_get_softc(bus); 3150 3151 switch (sc->rtsx_host.ios.vccq) { 3152 case vccq_120: 3153 vccq = 120; 3154 break; 3155 case vccq_180: 3156 vccq = 180; 3157 break; 3158 case vccq_330: 3159 vccq = 330; 3160 break; 3161 }; 3162 /* It seems it is always vccq_330. */ 3163 if (vccq == 330) { 3164 switch (sc->rtsx_device_id) { 3165 uint16_t val; 3166 case RTSX_RTS5227: 3167 if ((error = rtsx_write_phy(sc, 0x08, 0x4FE4))) 3168 return (error); 3169 if ((error = rtsx_rts5227_fill_driving(sc))) 3170 return (error); 3171 break; 3172 case RTSX_RTS5209: 3173 case RTSX_RTS5229: 3174 RTSX_BITOP(sc, RTSX_SD30_CMD_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_MASK, sc->rtsx_sd30_drive_sel_3v3); 3175 if ((error = rtsx_write_phy(sc, 0x08, 0x4FE4))) 3176 return (error); 3177 break; 3178 case RTSX_RTS522A: 3179 if ((error = rtsx_write_phy(sc, 0x08, 0x57E4))) 3180 return (error); 3181 if ((error = rtsx_rts5227_fill_driving(sc))) 3182 return (error); 3183 break; 3184 case RTSX_RTS525A: 3185 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_LDO_D3318_MASK, RTSX_LDO_D3318_33V); 3186 RTSX_BITOP(sc, RTSX_SD_PAD_CTL, RTSX_SD_IO_USING_1V8, 0); 3187 if ((error = rtsx_rts5249_fill_driving(sc))) 3188 return (error); 3189 break; 3190 case RTSX_RTS5249: 3191 if ((error = rtsx_read_phy(sc, RTSX_PHY_TUNE, &val))) 3192 return (error); 3193 if ((error = rtsx_write_phy(sc, RTSX_PHY_TUNE, 3194 (val & RTSX_PHY_TUNE_VOLTAGE_MASK) | RTSX_PHY_TUNE_VOLTAGE_3V3))) 3195 return (error); 3196 if ((error = rtsx_rts5249_fill_driving(sc))) 3197 return (error); 3198 break; 3199 case RTSX_RTL8402: 3200 RTSX_BITOP(sc, RTSX_SD30_CMD_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_MASK, sc->rtsx_sd30_drive_sel_3v3); 3201 RTSX_BITOP(sc, RTSX_LDO_CTL, 3202 (RTSX_BPP_ASIC_MASK << RTSX_BPP_SHIFT_8402) | RTSX_BPP_PAD_MASK, 3203 (RTSX_BPP_ASIC_3V3 << RTSX_BPP_SHIFT_8402) | RTSX_BPP_PAD_3V3); 3204 break; 3205 case RTSX_RTL8411: 3206 case RTSX_RTL8411B: 3207 RTSX_BITOP(sc, RTSX_SD30_CMD_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_MASK, sc->rtsx_sd30_drive_sel_3v3); 3208 RTSX_BITOP(sc, RTSX_LDO_CTL, 3209 (RTSX_BPP_ASIC_MASK << RTSX_BPP_SHIFT_8411) | RTSX_BPP_PAD_MASK, 3210 (RTSX_BPP_ASIC_3V3 << RTSX_BPP_SHIFT_8411) | RTSX_BPP_PAD_3V3); 3211 break; 3212 } 3213 DELAY(300); 3214 } 3215 3216 if (bootverbose || sc->rtsx_debug) 3217 device_printf(sc->rtsx_dev, "rtsx_mmcbr_switch_vccq(%d)\n", vccq); 3218 3219 return (0); 3220 } 3221 3222 #ifndef MMCCAM 3223 /* 3224 * Tune card if bus_timing_uhs_sdr50. 3225 */ 3226 static int 3227 rtsx_mmcbr_tune(device_t bus, device_t child __unused, bool hs400) 3228 { 3229 struct rtsx_softc *sc; 3230 uint32_t raw_phase_map[RTSX_RX_TUNING_CNT] = {0}; 3231 uint32_t phase_map; 3232 uint8_t final_phase; 3233 int i; 3234 3235 sc = device_get_softc(bus); 3236 3237 if (bootverbose || sc->rtsx_debug) 3238 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - hs400 is %s\n", 3239 (hs400) ? "true" : "false"); 3240 3241 if (sc->rtsx_ios_timing != bus_timing_uhs_sdr50) 3242 return (0); 3243 3244 sc->rtsx_tuning_mode = true; 3245 3246 switch (sc->rtsx_device_id) { 3247 case RTSX_RTS5209: 3248 case RTSX_RTS5227: 3249 rtsx_sd_change_tx_phase(sc, 27); 3250 break; 3251 case RTSX_RTS522A: 3252 rtsx_sd_change_tx_phase(sc, 20); 3253 break; 3254 case RTSX_RTS5229: 3255 rtsx_sd_change_tx_phase(sc, 27); 3256 break; 3257 case RTSX_RTS525A: 3258 case RTSX_RTS5249: 3259 rtsx_sd_change_tx_phase(sc, 29); 3260 break; 3261 case RTSX_RTL8402: 3262 case RTSX_RTL8411: 3263 case RTSX_RTL8411B: 3264 rtsx_sd_change_tx_phase(sc, 7); 3265 break; 3266 } 3267 3268 /* trying rx tuning for bus_timing_uhs_sdr50. */ 3269 for (i = 0; i < RTSX_RX_TUNING_CNT; i++) { 3270 rtsx_sd_tuning_rx_phase(sc, &(raw_phase_map[i])); 3271 if (raw_phase_map[i] == 0) 3272 break; 3273 } 3274 3275 phase_map = 0xffffffff; 3276 for (i = 0; i < RTSX_RX_TUNING_CNT; i++) { 3277 if (bootverbose || sc->rtsx_debug) 3278 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - RX raw_phase_map[%d]: 0x%08x\n", 3279 i, raw_phase_map[i]); 3280 phase_map &= raw_phase_map[i]; 3281 } 3282 if (bootverbose || sc->rtsx_debug) 3283 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - RX phase_map: 0x%08x\n", phase_map); 3284 3285 if (phase_map) { 3286 final_phase = rtsx_sd_search_final_rx_phase(sc, phase_map); 3287 if (final_phase != 0xff) { 3288 if (sc->rtsx_debug == 1) { 3289 sc->rtsx_debug = 2; 3290 rtsx_sd_change_rx_phase(sc, final_phase); 3291 sc->rtsx_debug = 1; 3292 } else { 3293 rtsx_sd_change_rx_phase(sc, final_phase); 3294 } 3295 } 3296 } 3297 3298 sc->rtsx_tuning_mode = false; 3299 3300 return (0); 3301 } 3302 3303 static int 3304 rtsx_mmcbr_retune(device_t bus, device_t child __unused, bool reset __unused) 3305 { 3306 struct rtsx_softc *sc; 3307 3308 sc = device_get_softc(bus); 3309 3310 if (bootverbose) 3311 device_printf(sc->rtsx_dev, "rtsx_mmcbr_retune()\n"); 3312 3313 return (0); 3314 } 3315 #endif /* !MMCCAM */ 3316 3317 static int 3318 rtsx_mmcbr_request(device_t bus, device_t child __unused, struct mmc_request *req) 3319 { 3320 struct rtsx_softc *sc; 3321 struct mmc_command *cmd; 3322 int timeout; 3323 int error; 3324 3325 sc = device_get_softc(bus); 3326 3327 RTSX_LOCK(sc); 3328 if (sc->rtsx_req != NULL) { 3329 RTSX_UNLOCK(sc); 3330 return (EBUSY); 3331 } 3332 sc->rtsx_req = req; 3333 cmd = req->cmd; 3334 cmd->error = error = MMC_ERR_NONE; 3335 sc->rtsx_intr_status = 0; 3336 sc->rtsx_intr_trans_ok = NULL; 3337 sc->rtsx_intr_trans_ko = rtsx_req_done; 3338 3339 if (bootverbose) 3340 device_printf(sc->rtsx_dev, "rtsx_mmcbr_request(CMD%u arg %#x, flags %#x, dlen %u, dflags %#x)\n", 3341 cmd->opcode, cmd->arg, cmd->flags, 3342 cmd->data != NULL ? (unsigned int)cmd->data->len : 0, 3343 cmd->data != NULL ? cmd->data->flags : 0); 3344 3345 /* Check if card present. */ 3346 if (!ISSET(sc->rtsx_flags, RTSX_F_CARD_PRESENT)) { 3347 cmd->error = error = MMC_ERR_FAILED; 3348 goto end; 3349 } 3350 3351 /* Refuse SDIO probe if the chip doesn't support SDIO. */ 3352 if (cmd->opcode == IO_SEND_OP_COND && 3353 !ISSET(sc->rtsx_flags, RTSX_F_SDIO_SUPPORT)) { 3354 cmd->error = error = MMC_ERR_INVALID; 3355 goto end; 3356 } 3357 3358 /* Return MMC_ERR_TIMEOUT for SD_IO_RW_DIRECT and IO_SEND_OP_COND. */ 3359 if (cmd->opcode == SD_IO_RW_DIRECT || cmd->opcode == IO_SEND_OP_COND) { 3360 cmd->error = error = MMC_ERR_TIMEOUT; 3361 goto end; 3362 } 3363 3364 /* Select SD card. */ 3365 RTSX_BITOP(sc, RTSX_CARD_SELECT, 0x07, RTSX_SD_MOD_SEL); 3366 RTSX_BITOP(sc, RTSX_CARD_SHARE_MODE, RTSX_CARD_SHARE_MASK, RTSX_CARD_SHARE_48_SD); 3367 3368 if (cmd->data == NULL) { 3369 DELAY(200); 3370 timeout = sc->rtsx_timeout_cmd; 3371 error = rtsx_send_req(sc, cmd); 3372 } else if (cmd->data->len <= 512) { 3373 timeout = sc->rtsx_timeout_io; 3374 error = rtsx_xfer_short(sc, cmd); 3375 } else { 3376 timeout = sc->rtsx_timeout_io; 3377 error = rtsx_xfer(sc, cmd); 3378 } 3379 end: 3380 if (error == MMC_ERR_NONE) { 3381 callout_reset(&sc->rtsx_timeout_callout, timeout * hz, rtsx_timeout, sc); 3382 } else { 3383 rtsx_req_done(sc); 3384 } 3385 RTSX_UNLOCK(sc); 3386 3387 return (error); 3388 } 3389 3390 #ifndef MMCCAM 3391 static int 3392 rtsx_mmcbr_get_ro(device_t bus, device_t child __unused) 3393 { 3394 struct rtsx_softc *sc; 3395 3396 sc = device_get_softc(bus); 3397 3398 if (sc->rtsx_inversion == 0) 3399 return (sc->rtsx_read_only); 3400 else 3401 return !(sc->rtsx_read_only); 3402 } 3403 3404 static int 3405 rtsx_mmcbr_acquire_host(device_t bus, device_t child __unused) 3406 { 3407 struct rtsx_softc *sc; 3408 3409 if (bootverbose) 3410 device_printf(bus, "rtsx_mmcbr_acquire_host()\n"); 3411 3412 sc = device_get_softc(bus); 3413 RTSX_LOCK(sc); 3414 while (sc->rtsx_bus_busy) 3415 msleep(&sc->rtsx_bus_busy, &sc->rtsx_mtx, 0, "rtsxah", 0); 3416 sc->rtsx_bus_busy++; 3417 RTSX_UNLOCK(sc); 3418 3419 return (0); 3420 } 3421 3422 static int 3423 rtsx_mmcbr_release_host(device_t bus, device_t child __unused) 3424 { 3425 struct rtsx_softc *sc; 3426 3427 if (bootverbose) 3428 device_printf(bus, "rtsx_mmcbr_release_host()\n"); 3429 3430 sc = device_get_softc(bus); 3431 RTSX_LOCK(sc); 3432 sc->rtsx_bus_busy--; 3433 wakeup(&sc->rtsx_bus_busy); 3434 RTSX_UNLOCK(sc); 3435 3436 return (0); 3437 } 3438 #endif /* !MMCCAM */ 3439 3440 /* 3441 * 3442 * PCI Support Functions 3443 * 3444 */ 3445 3446 /* 3447 * Compare the device ID (chip) of this device against the IDs that this driver 3448 * supports. If there is a match, set the description and return success. 3449 */ 3450 static int 3451 rtsx_probe(device_t dev) 3452 { 3453 struct rtsx_softc *sc; 3454 uint16_t vendor_id; 3455 uint16_t device_id; 3456 int i; 3457 int result; 3458 3459 vendor_id = pci_get_vendor(dev); 3460 device_id = pci_get_device(dev); 3461 3462 result = ENXIO; 3463 for (i = 0; rtsx_devices[i].vendor_id != 0; i++) { 3464 if (rtsx_devices[i].vendor_id == vendor_id && 3465 rtsx_devices[i].device_id == device_id) { 3466 device_set_desc(dev, rtsx_devices[i].desc); 3467 sc = device_get_softc(dev); 3468 sc->rtsx_device_id = device_id; 3469 result = BUS_PROBE_DEFAULT; 3470 break; 3471 } 3472 } 3473 3474 return (result); 3475 } 3476 3477 /* 3478 * Attach function is only called if the probe is successful. 3479 */ 3480 static int 3481 rtsx_attach(device_t dev) 3482 { 3483 struct rtsx_softc *sc = device_get_softc(dev); 3484 struct sysctl_ctx_list *ctx; 3485 struct sysctl_oid_list *tree; 3486 int msi_count = 1; 3487 uint32_t sdio_cfg; 3488 int error; 3489 char *maker; 3490 char *family; 3491 char *product; 3492 int i; 3493 3494 if (bootverbose) 3495 device_printf(dev, "Attach - Vendor ID: 0x%x - Device ID: 0x%x\n", 3496 pci_get_vendor(dev), pci_get_device(dev)); 3497 3498 sc->rtsx_dev = dev; 3499 sc->rtsx_req = NULL; 3500 sc->rtsx_timeout_cmd = 1; 3501 sc->rtsx_timeout_io = 10; 3502 sc->rtsx_read_only = 0; 3503 sc->rtsx_inversion = 0; 3504 sc->rtsx_force_timing = 0; 3505 sc->rtsx_debug = 0; 3506 sc->rtsx_read_count = 0; 3507 sc->rtsx_write_count = 0; 3508 3509 maker = kern_getenv("smbios.system.maker"); 3510 family = kern_getenv("smbios.system.family"); 3511 product = kern_getenv("smbios.system.product"); 3512 for (i = 0; rtsx_inversion_models[i].maker != NULL; i++) { 3513 if (strcmp(rtsx_inversion_models[i].maker, maker) == 0 && 3514 strcmp(rtsx_inversion_models[i].family, family) == 0 && 3515 strcmp(rtsx_inversion_models[i].product, product) == 0) { 3516 device_printf(dev, "Inversion activated for %s/%s/%s, see BUG in rtsx(4)\n", maker, family, product); 3517 device_printf(dev, "If a card is detected without an SD card present," 3518 " add dev.rtsx.0.inversion=0 in loader.conf(5)\n"); 3519 sc->rtsx_inversion = 1; 3520 } 3521 } 3522 3523 RTSX_LOCK_INIT(sc); 3524 3525 ctx = device_get_sysctl_ctx(dev); 3526 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 3527 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "timeout_io", CTLFLAG_RW, 3528 &sc->rtsx_timeout_io, 0, "Request timeout for I/O commands in seconds"); 3529 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "timeout_cmd", CTLFLAG_RW, 3530 &sc->rtsx_timeout_cmd, 0, "Request timeout for setup commands in seconds"); 3531 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "read_only", CTLFLAG_RD, 3532 &sc->rtsx_read_only, 0, "Card is write protected"); 3533 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "inversion", CTLFLAG_RWTUN, 3534 &sc->rtsx_inversion, 0, "Inversion of card detection and read only status"); 3535 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "force_timing", CTLFLAG_RW, 3536 &sc->rtsx_force_timing, 0, "Force bus_timing_uhs_sdr50"); 3537 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "debug", CTLFLAG_RWTUN, 3538 &sc->rtsx_debug, 0, "Debugging flag"); 3539 SYSCTL_ADD_U64(ctx, tree, OID_AUTO, "read_count", CTLFLAG_RD | CTLFLAG_STATS, 3540 &sc->rtsx_read_count, 0, "Count of read operations"); 3541 SYSCTL_ADD_U64(ctx, tree, OID_AUTO, "write_count", CTLFLAG_RD | CTLFLAG_STATS, 3542 &sc->rtsx_write_count, 0, "Count of write operations"); 3543 3544 if (bootverbose || sc->rtsx_debug) 3545 device_printf(dev, "We are running with inversion: %d\n", sc->rtsx_inversion); 3546 3547 /* Allocate IRQ. */ 3548 sc->rtsx_irq_res_id = 0; 3549 if (pci_alloc_msi(dev, &msi_count) == 0) 3550 sc->rtsx_irq_res_id = 1; 3551 sc->rtsx_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->rtsx_irq_res_id, 3552 RF_ACTIVE | (sc->rtsx_irq_res_id != 0 ? 0 : RF_SHAREABLE)); 3553 if (sc->rtsx_irq_res == NULL) { 3554 device_printf(dev, "Can't allocate IRQ resources for %d\n", sc->rtsx_irq_res_id); 3555 pci_release_msi(dev); 3556 return (ENXIO); 3557 } 3558 3559 callout_init_mtx(&sc->rtsx_timeout_callout, &sc->rtsx_mtx, 0); 3560 3561 /* Allocate memory resource. */ 3562 if (sc->rtsx_device_id == RTSX_RTS525A) 3563 sc->rtsx_res_id = PCIR_BAR(1); 3564 else 3565 sc->rtsx_res_id = PCIR_BAR(0); 3566 sc->rtsx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rtsx_res_id, RF_ACTIVE); 3567 if (sc->rtsx_res == NULL) { 3568 device_printf(dev, "Can't allocate memory resource for %d\n", sc->rtsx_res_id); 3569 goto destroy_rtsx_irq_res; 3570 } 3571 3572 if (bootverbose) 3573 device_printf(dev, "rtsx_irq_res_id: %d, rtsx_res_id: %d\n", 3574 sc->rtsx_irq_res_id, sc->rtsx_res_id); 3575 3576 sc->rtsx_btag = rman_get_bustag(sc->rtsx_res); 3577 sc->rtsx_bhandle = rman_get_bushandle(sc->rtsx_res); 3578 3579 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &sc->rtsx_card_insert_task, 0, 3580 rtsx_card_task, sc); 3581 TASK_INIT(&sc->rtsx_card_remove_task, 0, rtsx_card_task, sc); 3582 3583 /* Allocate two DMA buffers: a command buffer and a data buffer. */ 3584 error = rtsx_dma_alloc(sc); 3585 if (error) 3586 goto destroy_rtsx_irq_res; 3587 3588 /* Activate the interrupt. */ 3589 error = bus_setup_intr(dev, sc->rtsx_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 3590 NULL, rtsx_intr, sc, &sc->rtsx_irq_cookie); 3591 if (error) { 3592 device_printf(dev, "Can't set up irq [0x%x]!\n", error); 3593 goto destroy_rtsx_res; 3594 } 3595 pci_enable_busmaster(dev); 3596 3597 if (rtsx_read_cfg(sc, 0, RTSX_SDIOCFG_REG, &sdio_cfg) == 0) { 3598 if ((sdio_cfg & RTSX_SDIOCFG_SDIO_ONLY) || 3599 (sdio_cfg & RTSX_SDIOCFG_HAVE_SDIO)) 3600 sc->rtsx_flags |= RTSX_F_SDIO_SUPPORT; 3601 } 3602 3603 #ifdef MMCCAM 3604 sc->rtsx_ccb = NULL; 3605 sc->rtsx_cam_status = 0; 3606 3607 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "cam_status", CTLFLAG_RD, 3608 &sc->rtsx_cam_status, 0, "driver cam card present"); 3609 3610 if (mmc_cam_sim_alloc(dev, "rtsx_mmc", &sc->rtsx_mmc_sim) != 0) { 3611 device_printf(dev, "Can't allocate CAM SIM\n"); 3612 goto destroy_rtsx_irq; 3613 } 3614 #endif /* MMCCAM */ 3615 3616 /* Initialize device. */ 3617 if (rtsx_init(sc)) { 3618 device_printf(dev, "Error during rtsx_init()\n"); 3619 goto destroy_rtsx_irq; 3620 } 3621 3622 /* 3623 * Schedule a card detection as we won't get an interrupt 3624 * if the card is inserted when we attach. We wait a quarter 3625 * of a second to allow for a "spontaneous" interrupt which may 3626 * change the card presence state. This delay avoid a panic 3627 * on some configuration (e.g. Lenovo T540p). 3628 */ 3629 DELAY(250000); 3630 if (rtsx_is_card_present(sc)) 3631 device_printf(sc->rtsx_dev, "A card is detected\n"); 3632 else 3633 device_printf(sc->rtsx_dev, "No card is detected\n"); 3634 rtsx_card_task(sc, 0); 3635 3636 if (bootverbose) 3637 device_printf(dev, "Device attached\n"); 3638 3639 return (0); 3640 3641 destroy_rtsx_irq: 3642 bus_teardown_intr(dev, sc->rtsx_irq_res, sc->rtsx_irq_cookie); 3643 destroy_rtsx_res: 3644 bus_release_resource(dev, SYS_RES_MEMORY, sc->rtsx_res_id, 3645 sc->rtsx_res); 3646 rtsx_dma_free(sc); 3647 destroy_rtsx_irq_res: 3648 callout_drain(&sc->rtsx_timeout_callout); 3649 bus_release_resource(dev, SYS_RES_IRQ, sc->rtsx_irq_res_id, 3650 sc->rtsx_irq_res); 3651 pci_release_msi(dev); 3652 RTSX_LOCK_DESTROY(sc); 3653 3654 return (ENXIO); 3655 } 3656 3657 static int 3658 rtsx_detach(device_t dev) 3659 { 3660 struct rtsx_softc *sc = device_get_softc(dev); 3661 int error; 3662 3663 if (bootverbose) 3664 device_printf(dev, "Detach - Vendor ID: 0x%x - Device ID: 0x%x\n", 3665 pci_get_vendor(dev), pci_get_device(dev)); 3666 3667 /* Disable interrupts. */ 3668 sc->rtsx_intr_enabled = 0; 3669 WRITE4(sc, RTSX_BIER, sc->rtsx_intr_enabled); 3670 3671 /* Stop device. */ 3672 error = device_delete_children(sc->rtsx_dev); 3673 sc->rtsx_mmc_dev = NULL; 3674 if (error) 3675 return (error); 3676 3677 taskqueue_drain_timeout(taskqueue_swi_giant, &sc->rtsx_card_insert_task); 3678 taskqueue_drain(taskqueue_swi_giant, &sc->rtsx_card_remove_task); 3679 3680 /* Teardown the state in our softc created in our attach routine. */ 3681 rtsx_dma_free(sc); 3682 if (sc->rtsx_res != NULL) 3683 bus_release_resource(dev, SYS_RES_MEMORY, sc->rtsx_res_id, 3684 sc->rtsx_res); 3685 if (sc->rtsx_irq_cookie != NULL) 3686 bus_teardown_intr(dev, sc->rtsx_irq_res, sc->rtsx_irq_cookie); 3687 if (sc->rtsx_irq_res != NULL) { 3688 callout_drain(&sc->rtsx_timeout_callout); 3689 bus_release_resource(dev, SYS_RES_IRQ, sc->rtsx_irq_res_id, 3690 sc->rtsx_irq_res); 3691 pci_release_msi(dev); 3692 } 3693 RTSX_LOCK_DESTROY(sc); 3694 #ifdef MMCCAM 3695 mmc_cam_sim_free(&sc->rtsx_mmc_sim); 3696 #endif /* MMCCAM */ 3697 3698 return (0); 3699 } 3700 3701 static int 3702 rtsx_shutdown(device_t dev) 3703 { 3704 if (bootverbose) 3705 device_printf(dev, "Shutdown\n"); 3706 3707 rtsx_detach(dev); 3708 3709 return (0); 3710 } 3711 3712 /* 3713 * Device suspend routine. 3714 */ 3715 static int 3716 rtsx_suspend(device_t dev) 3717 { 3718 struct rtsx_softc *sc = device_get_softc(dev); 3719 3720 device_printf(dev, "Suspend\n"); 3721 3722 #ifdef MMCCAM 3723 if (sc->rtsx_ccb != NULL) { 3724 device_printf(dev, "Request in progress: CMD%u, rtsr_intr_status: 0x%08x\n", 3725 sc->rtsx_ccb->mmcio.cmd.opcode, sc->rtsx_intr_status); 3726 } 3727 #else /* !MMCCAM */ 3728 if (sc->rtsx_req != NULL) { 3729 device_printf(dev, "Request in progress: CMD%u, rtsr_intr_status: 0x%08x\n", 3730 sc->rtsx_req->cmd->opcode, sc->rtsx_intr_status); 3731 } 3732 #endif /* MMCCAM */ 3733 3734 bus_generic_suspend(dev); 3735 3736 return (0); 3737 } 3738 3739 /* 3740 * Device resume routine. 3741 */ 3742 static int 3743 rtsx_resume(device_t dev) 3744 { 3745 device_printf(dev, "Resume\n"); 3746 3747 bus_generic_resume(dev); 3748 3749 return (0); 3750 } 3751 3752 static device_method_t rtsx_methods[] = { 3753 /* Device interface */ 3754 DEVMETHOD(device_probe, rtsx_probe), 3755 DEVMETHOD(device_attach, rtsx_attach), 3756 DEVMETHOD(device_detach, rtsx_detach), 3757 DEVMETHOD(device_shutdown, rtsx_shutdown), 3758 DEVMETHOD(device_suspend, rtsx_suspend), 3759 DEVMETHOD(device_resume, rtsx_resume), 3760 3761 /* Bus interface */ 3762 DEVMETHOD(bus_read_ivar, rtsx_read_ivar), 3763 DEVMETHOD(bus_write_ivar, rtsx_write_ivar), 3764 3765 #ifndef MMCCAM 3766 /* MMC bridge interface */ 3767 DEVMETHOD(mmcbr_update_ios, rtsx_mmcbr_update_ios), 3768 DEVMETHOD(mmcbr_switch_vccq, rtsx_mmcbr_switch_vccq), 3769 DEVMETHOD(mmcbr_tune, rtsx_mmcbr_tune), 3770 DEVMETHOD(mmcbr_retune, rtsx_mmcbr_retune), 3771 DEVMETHOD(mmcbr_request, rtsx_mmcbr_request), 3772 DEVMETHOD(mmcbr_get_ro, rtsx_mmcbr_get_ro), 3773 DEVMETHOD(mmcbr_acquire_host, rtsx_mmcbr_acquire_host), 3774 DEVMETHOD(mmcbr_release_host, rtsx_mmcbr_release_host), 3775 #endif /* !MMCCAM */ 3776 3777 #ifdef MMCCAM 3778 /* MMCCAM interface */ 3779 DEVMETHOD(mmc_sim_get_tran_settings, rtsx_get_tran_settings), 3780 DEVMETHOD(mmc_sim_set_tran_settings, rtsx_set_tran_settings), 3781 DEVMETHOD(mmc_sim_cam_request, rtsx_cam_request), 3782 #endif /* MMCCAM */ 3783 3784 DEVMETHOD_END 3785 }; 3786 3787 static devclass_t rtsx_devclass; 3788 3789 DEFINE_CLASS_0(rtsx, rtsx_driver, rtsx_methods, sizeof(struct rtsx_softc)); 3790 DRIVER_MODULE(rtsx, pci, rtsx_driver, rtsx_devclass, NULL, NULL); 3791 #ifndef MMCCAM 3792 MMC_DECLARE_BRIDGE(rtsx); 3793 #endif /* !MMCCAM */ 3794