1 /*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #ifdef HAVE_KERNEL_OPTION_HEADERS 112 #include "opt_device_polling.h" 113 #endif 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/module.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/lock.h> 125 #include <sys/mutex.h> 126 #include <sys/sysctl.h> 127 #include <sys/taskqueue.h> 128 129 #include <net/if.h> 130 #include <net/if_arp.h> 131 #include <net/ethernet.h> 132 #include <net/if_dl.h> 133 #include <net/if_media.h> 134 #include <net/if_types.h> 135 #include <net/if_vlan_var.h> 136 137 #include <net/bpf.h> 138 139 #include <machine/bus.h> 140 #include <machine/resource.h> 141 #include <sys/bus.h> 142 #include <sys/rman.h> 143 144 #include <dev/mii/mii.h> 145 #include <dev/mii/miivar.h> 146 147 #include <dev/pci/pcireg.h> 148 #include <dev/pci/pcivar.h> 149 150 #include <pci/if_rlreg.h> 151 152 MODULE_DEPEND(re, pci, 1, 1, 1); 153 MODULE_DEPEND(re, ether, 1, 1, 1); 154 MODULE_DEPEND(re, miibus, 1, 1, 1); 155 156 /* "device miibus" required. See GENERIC if you get errors here. */ 157 #include "miibus_if.h" 158 159 /* Tunables. */ 160 static int intr_filter = 0; 161 TUNABLE_INT("hw.re.intr_filter", &intr_filter); 162 static int msi_disable = 0; 163 TUNABLE_INT("hw.re.msi_disable", &msi_disable); 164 static int msix_disable = 0; 165 TUNABLE_INT("hw.re.msix_disable", &msix_disable); 166 static int prefer_iomap = 0; 167 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 168 169 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 170 171 /* 172 * Various supported device vendors/types and their names. 173 */ 174 static const struct rl_type const re_devs[] = { 175 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 176 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 177 { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0, 178 "D-Link DGE-530(T) Gigabit Ethernet Adapter" }, 179 { RT_VENDORID, RT_DEVICEID_8139, 0, 180 "RealTek 8139C+ 10/100BaseTX" }, 181 { RT_VENDORID, RT_DEVICEID_8101E, 0, 182 "RealTek 810xE PCIe 10/100baseTX" }, 183 { RT_VENDORID, RT_DEVICEID_8168, 0, 184 "RealTek 8168/8111 B/C/CP/D/DP/E/F PCIe Gigabit Ethernet" }, 185 { RT_VENDORID, RT_DEVICEID_8169, 0, 186 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 187 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 188 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 189 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 190 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 191 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 192 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 193 { USR_VENDORID, USR_DEVICEID_997902, 0, 194 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 195 }; 196 197 static const struct rl_hwrev const re_hwrevs[] = { 198 { RL_HWREV_8139, RL_8139, "", RL_MTU }, 199 { RL_HWREV_8139A, RL_8139, "A", RL_MTU }, 200 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU }, 201 { RL_HWREV_8139B, RL_8139, "B", RL_MTU }, 202 { RL_HWREV_8130, RL_8139, "8130", RL_MTU }, 203 { RL_HWREV_8139C, RL_8139, "C", RL_MTU }, 204 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU }, 205 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU }, 206 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU }, 207 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU }, 208 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU }, 209 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU }, 210 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU }, 211 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 212 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU }, 213 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 214 { RL_HWREV_8100, RL_8139, "8100", RL_MTU }, 215 { RL_HWREV_8101, RL_8139, "8101", RL_MTU }, 216 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU }, 217 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU }, 218 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU }, 219 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU }, 220 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU }, 221 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU }, 222 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU }, 223 { RL_HWREV_8402, RL_8169, "8402", RL_MTU }, 224 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU }, 225 { RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU }, 226 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU }, 227 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU }, 228 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 229 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 230 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K }, 231 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K }, 232 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K }, 233 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K}, 234 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K}, 235 { RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K}, 236 { RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K}, 237 { 0, 0, NULL, 0 } 238 }; 239 240 static int re_probe (device_t); 241 static int re_attach (device_t); 242 static int re_detach (device_t); 243 244 static int re_encap (struct rl_softc *, struct mbuf **); 245 246 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 247 static int re_allocmem (device_t, struct rl_softc *); 248 static __inline void re_discard_rxbuf 249 (struct rl_softc *, int); 250 static int re_newbuf (struct rl_softc *, int); 251 static int re_jumbo_newbuf (struct rl_softc *, int); 252 static int re_rx_list_init (struct rl_softc *); 253 static int re_jrx_list_init (struct rl_softc *); 254 static int re_tx_list_init (struct rl_softc *); 255 #ifdef RE_FIXUP_RX 256 static __inline void re_fixup_rx 257 (struct mbuf *); 258 #endif 259 static int re_rxeof (struct rl_softc *, int *); 260 static void re_txeof (struct rl_softc *); 261 #ifdef DEVICE_POLLING 262 static int re_poll (struct ifnet *, enum poll_cmd, int); 263 static int re_poll_locked (struct ifnet *, enum poll_cmd, int); 264 #endif 265 static int re_intr (void *); 266 static void re_intr_msi (void *); 267 static void re_tick (void *); 268 static void re_int_task (void *, int); 269 static void re_start (struct ifnet *); 270 static void re_start_locked (struct ifnet *); 271 static int re_ioctl (struct ifnet *, u_long, caddr_t); 272 static void re_init (void *); 273 static void re_init_locked (struct rl_softc *); 274 static void re_stop (struct rl_softc *); 275 static void re_watchdog (struct rl_softc *); 276 static int re_suspend (device_t); 277 static int re_resume (device_t); 278 static int re_shutdown (device_t); 279 static int re_ifmedia_upd (struct ifnet *); 280 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 281 282 static void re_eeprom_putbyte (struct rl_softc *, int); 283 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 284 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 285 static int re_gmii_readreg (device_t, int, int); 286 static int re_gmii_writereg (device_t, int, int, int); 287 288 static int re_miibus_readreg (device_t, int, int); 289 static int re_miibus_writereg (device_t, int, int, int); 290 static void re_miibus_statchg (device_t); 291 292 static void re_set_jumbo (struct rl_softc *, int); 293 static void re_set_rxmode (struct rl_softc *); 294 static void re_reset (struct rl_softc *); 295 static void re_setwol (struct rl_softc *); 296 static void re_clrwol (struct rl_softc *); 297 static void re_set_linkspeed (struct rl_softc *); 298 299 #ifdef DEV_NETMAP /* see ixgbe.c for details */ 300 #include <dev/netmap/if_re_netmap.h> 301 #endif /* !DEV_NETMAP */ 302 303 #ifdef RE_DIAG 304 static int re_diag (struct rl_softc *); 305 #endif 306 307 static void re_add_sysctls (struct rl_softc *); 308 static int re_sysctl_stats (SYSCTL_HANDLER_ARGS); 309 static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int); 310 static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS); 311 312 static device_method_t re_methods[] = { 313 /* Device interface */ 314 DEVMETHOD(device_probe, re_probe), 315 DEVMETHOD(device_attach, re_attach), 316 DEVMETHOD(device_detach, re_detach), 317 DEVMETHOD(device_suspend, re_suspend), 318 DEVMETHOD(device_resume, re_resume), 319 DEVMETHOD(device_shutdown, re_shutdown), 320 321 /* MII interface */ 322 DEVMETHOD(miibus_readreg, re_miibus_readreg), 323 DEVMETHOD(miibus_writereg, re_miibus_writereg), 324 DEVMETHOD(miibus_statchg, re_miibus_statchg), 325 326 DEVMETHOD_END 327 }; 328 329 static driver_t re_driver = { 330 "re", 331 re_methods, 332 sizeof(struct rl_softc) 333 }; 334 335 static devclass_t re_devclass; 336 337 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 338 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 339 340 #define EE_SET(x) \ 341 CSR_WRITE_1(sc, RL_EECMD, \ 342 CSR_READ_1(sc, RL_EECMD) | x) 343 344 #define EE_CLR(x) \ 345 CSR_WRITE_1(sc, RL_EECMD, \ 346 CSR_READ_1(sc, RL_EECMD) & ~x) 347 348 /* 349 * Send a read command and address to the EEPROM, check for ACK. 350 */ 351 static void 352 re_eeprom_putbyte(struct rl_softc *sc, int addr) 353 { 354 int d, i; 355 356 d = addr | (RL_9346_READ << sc->rl_eewidth); 357 358 /* 359 * Feed in each bit and strobe the clock. 360 */ 361 362 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 363 if (d & i) { 364 EE_SET(RL_EE_DATAIN); 365 } else { 366 EE_CLR(RL_EE_DATAIN); 367 } 368 DELAY(100); 369 EE_SET(RL_EE_CLK); 370 DELAY(150); 371 EE_CLR(RL_EE_CLK); 372 DELAY(100); 373 } 374 } 375 376 /* 377 * Read a word of data stored in the EEPROM at address 'addr.' 378 */ 379 static void 380 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 381 { 382 int i; 383 u_int16_t word = 0; 384 385 /* 386 * Send address of word we want to read. 387 */ 388 re_eeprom_putbyte(sc, addr); 389 390 /* 391 * Start reading bits from EEPROM. 392 */ 393 for (i = 0x8000; i; i >>= 1) { 394 EE_SET(RL_EE_CLK); 395 DELAY(100); 396 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 397 word |= i; 398 EE_CLR(RL_EE_CLK); 399 DELAY(100); 400 } 401 402 *dest = word; 403 } 404 405 /* 406 * Read a sequence of words from the EEPROM. 407 */ 408 static void 409 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 410 { 411 int i; 412 u_int16_t word = 0, *ptr; 413 414 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 415 416 DELAY(100); 417 418 for (i = 0; i < cnt; i++) { 419 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 420 re_eeprom_getword(sc, off + i, &word); 421 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 422 ptr = (u_int16_t *)(dest + (i * 2)); 423 *ptr = word; 424 } 425 426 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 427 } 428 429 static int 430 re_gmii_readreg(device_t dev, int phy, int reg) 431 { 432 struct rl_softc *sc; 433 u_int32_t rval; 434 int i; 435 436 sc = device_get_softc(dev); 437 438 /* Let the rgephy driver read the GMEDIASTAT register */ 439 440 if (reg == RL_GMEDIASTAT) { 441 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 442 return (rval); 443 } 444 445 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 446 447 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 448 rval = CSR_READ_4(sc, RL_PHYAR); 449 if (rval & RL_PHYAR_BUSY) 450 break; 451 DELAY(25); 452 } 453 454 if (i == RL_PHY_TIMEOUT) { 455 device_printf(sc->rl_dev, "PHY read failed\n"); 456 return (0); 457 } 458 459 /* 460 * Controller requires a 20us delay to process next MDIO request. 461 */ 462 DELAY(20); 463 464 return (rval & RL_PHYAR_PHYDATA); 465 } 466 467 static int 468 re_gmii_writereg(device_t dev, int phy, int reg, int data) 469 { 470 struct rl_softc *sc; 471 u_int32_t rval; 472 int i; 473 474 sc = device_get_softc(dev); 475 476 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 477 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 478 479 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 480 rval = CSR_READ_4(sc, RL_PHYAR); 481 if (!(rval & RL_PHYAR_BUSY)) 482 break; 483 DELAY(25); 484 } 485 486 if (i == RL_PHY_TIMEOUT) { 487 device_printf(sc->rl_dev, "PHY write failed\n"); 488 return (0); 489 } 490 491 /* 492 * Controller requires a 20us delay to process next MDIO request. 493 */ 494 DELAY(20); 495 496 return (0); 497 } 498 499 static int 500 re_miibus_readreg(device_t dev, int phy, int reg) 501 { 502 struct rl_softc *sc; 503 u_int16_t rval = 0; 504 u_int16_t re8139_reg = 0; 505 506 sc = device_get_softc(dev); 507 508 if (sc->rl_type == RL_8169) { 509 rval = re_gmii_readreg(dev, phy, reg); 510 return (rval); 511 } 512 513 switch (reg) { 514 case MII_BMCR: 515 re8139_reg = RL_BMCR; 516 break; 517 case MII_BMSR: 518 re8139_reg = RL_BMSR; 519 break; 520 case MII_ANAR: 521 re8139_reg = RL_ANAR; 522 break; 523 case MII_ANER: 524 re8139_reg = RL_ANER; 525 break; 526 case MII_ANLPAR: 527 re8139_reg = RL_LPAR; 528 break; 529 case MII_PHYIDR1: 530 case MII_PHYIDR2: 531 return (0); 532 /* 533 * Allow the rlphy driver to read the media status 534 * register. If we have a link partner which does not 535 * support NWAY, this is the register which will tell 536 * us the results of parallel detection. 537 */ 538 case RL_MEDIASTAT: 539 rval = CSR_READ_1(sc, RL_MEDIASTAT); 540 return (rval); 541 default: 542 device_printf(sc->rl_dev, "bad phy register\n"); 543 return (0); 544 } 545 rval = CSR_READ_2(sc, re8139_reg); 546 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 547 /* 8139C+ has different bit layout. */ 548 rval &= ~(BMCR_LOOP | BMCR_ISO); 549 } 550 return (rval); 551 } 552 553 static int 554 re_miibus_writereg(device_t dev, int phy, int reg, int data) 555 { 556 struct rl_softc *sc; 557 u_int16_t re8139_reg = 0; 558 int rval = 0; 559 560 sc = device_get_softc(dev); 561 562 if (sc->rl_type == RL_8169) { 563 rval = re_gmii_writereg(dev, phy, reg, data); 564 return (rval); 565 } 566 567 switch (reg) { 568 case MII_BMCR: 569 re8139_reg = RL_BMCR; 570 if (sc->rl_type == RL_8139CPLUS) { 571 /* 8139C+ has different bit layout. */ 572 data &= ~(BMCR_LOOP | BMCR_ISO); 573 } 574 break; 575 case MII_BMSR: 576 re8139_reg = RL_BMSR; 577 break; 578 case MII_ANAR: 579 re8139_reg = RL_ANAR; 580 break; 581 case MII_ANER: 582 re8139_reg = RL_ANER; 583 break; 584 case MII_ANLPAR: 585 re8139_reg = RL_LPAR; 586 break; 587 case MII_PHYIDR1: 588 case MII_PHYIDR2: 589 return (0); 590 break; 591 default: 592 device_printf(sc->rl_dev, "bad phy register\n"); 593 return (0); 594 } 595 CSR_WRITE_2(sc, re8139_reg, data); 596 return (0); 597 } 598 599 static void 600 re_miibus_statchg(device_t dev) 601 { 602 struct rl_softc *sc; 603 struct ifnet *ifp; 604 struct mii_data *mii; 605 606 sc = device_get_softc(dev); 607 mii = device_get_softc(sc->rl_miibus); 608 ifp = sc->rl_ifp; 609 if (mii == NULL || ifp == NULL || 610 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 611 return; 612 613 sc->rl_flags &= ~RL_FLAG_LINK; 614 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 615 (IFM_ACTIVE | IFM_AVALID)) { 616 switch (IFM_SUBTYPE(mii->mii_media_active)) { 617 case IFM_10_T: 618 case IFM_100_TX: 619 sc->rl_flags |= RL_FLAG_LINK; 620 break; 621 case IFM_1000_T: 622 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 623 break; 624 sc->rl_flags |= RL_FLAG_LINK; 625 break; 626 default: 627 break; 628 } 629 } 630 /* 631 * RealTek controllers does not provide any interface to 632 * Tx/Rx MACs for resolved speed, duplex and flow-control 633 * parameters. 634 */ 635 } 636 637 /* 638 * Set the RX configuration and 64-bit multicast hash filter. 639 */ 640 static void 641 re_set_rxmode(struct rl_softc *sc) 642 { 643 struct ifnet *ifp; 644 struct ifmultiaddr *ifma; 645 uint32_t hashes[2] = { 0, 0 }; 646 uint32_t h, rxfilt; 647 648 RL_LOCK_ASSERT(sc); 649 650 ifp = sc->rl_ifp; 651 652 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 653 654 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 655 if (ifp->if_flags & IFF_PROMISC) 656 rxfilt |= RL_RXCFG_RX_ALLPHYS; 657 /* 658 * Unlike other hardwares, we have to explicitly set 659 * RL_RXCFG_RX_MULTI to receive multicast frames in 660 * promiscuous mode. 661 */ 662 rxfilt |= RL_RXCFG_RX_MULTI; 663 hashes[0] = hashes[1] = 0xffffffff; 664 goto done; 665 } 666 667 if_maddr_rlock(ifp); 668 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 669 if (ifma->ifma_addr->sa_family != AF_LINK) 670 continue; 671 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 672 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 673 if (h < 32) 674 hashes[0] |= (1 << h); 675 else 676 hashes[1] |= (1 << (h - 32)); 677 } 678 if_maddr_runlock(ifp); 679 680 if (hashes[0] != 0 || hashes[1] != 0) { 681 /* 682 * For some unfathomable reason, RealTek decided to 683 * reverse the order of the multicast hash registers 684 * in the PCI Express parts. This means we have to 685 * write the hash pattern in reverse order for those 686 * devices. 687 */ 688 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 689 h = bswap32(hashes[0]); 690 hashes[0] = bswap32(hashes[1]); 691 hashes[1] = h; 692 } 693 rxfilt |= RL_RXCFG_RX_MULTI; 694 } 695 696 done: 697 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 698 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 699 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 700 } 701 702 static void 703 re_reset(struct rl_softc *sc) 704 { 705 int i; 706 707 RL_LOCK_ASSERT(sc); 708 709 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 710 711 for (i = 0; i < RL_TIMEOUT; i++) { 712 DELAY(10); 713 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 714 break; 715 } 716 if (i == RL_TIMEOUT) 717 device_printf(sc->rl_dev, "reset never completed!\n"); 718 719 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 720 CSR_WRITE_1(sc, 0x82, 1); 721 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S) 722 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 723 } 724 725 #ifdef RE_DIAG 726 727 /* 728 * The following routine is designed to test for a defect on some 729 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 730 * lines connected to the bus, however for a 32-bit only card, they 731 * should be pulled high. The result of this defect is that the 732 * NIC will not work right if you plug it into a 64-bit slot: DMA 733 * operations will be done with 64-bit transfers, which will fail 734 * because the 64-bit data lines aren't connected. 735 * 736 * There's no way to work around this (short of talking a soldering 737 * iron to the board), however we can detect it. The method we use 738 * here is to put the NIC into digital loopback mode, set the receiver 739 * to promiscuous mode, and then try to send a frame. We then compare 740 * the frame data we sent to what was received. If the data matches, 741 * then the NIC is working correctly, otherwise we know the user has 742 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 743 * slot. In the latter case, there's no way the NIC can work correctly, 744 * so we print out a message on the console and abort the device attach. 745 */ 746 747 static int 748 re_diag(struct rl_softc *sc) 749 { 750 struct ifnet *ifp = sc->rl_ifp; 751 struct mbuf *m0; 752 struct ether_header *eh; 753 struct rl_desc *cur_rx; 754 u_int16_t status; 755 u_int32_t rxstat; 756 int total_len, i, error = 0, phyaddr; 757 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 758 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 759 760 /* Allocate a single mbuf */ 761 MGETHDR(m0, M_DONTWAIT, MT_DATA); 762 if (m0 == NULL) 763 return (ENOBUFS); 764 765 RL_LOCK(sc); 766 767 /* 768 * Initialize the NIC in test mode. This sets the chip up 769 * so that it can send and receive frames, but performs the 770 * following special functions: 771 * - Puts receiver in promiscuous mode 772 * - Enables digital loopback mode 773 * - Leaves interrupts turned off 774 */ 775 776 ifp->if_flags |= IFF_PROMISC; 777 sc->rl_testmode = 1; 778 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 779 re_init_locked(sc); 780 sc->rl_flags |= RL_FLAG_LINK; 781 if (sc->rl_type == RL_8169) 782 phyaddr = 1; 783 else 784 phyaddr = 0; 785 786 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 787 for (i = 0; i < RL_TIMEOUT; i++) { 788 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 789 if (!(status & BMCR_RESET)) 790 break; 791 } 792 793 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 794 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 795 796 DELAY(100000); 797 798 /* Put some data in the mbuf */ 799 800 eh = mtod(m0, struct ether_header *); 801 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 802 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 803 eh->ether_type = htons(ETHERTYPE_IP); 804 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 805 806 /* 807 * Queue the packet, start transmission. 808 * Note: IF_HANDOFF() ultimately calls re_start() for us. 809 */ 810 811 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 812 RL_UNLOCK(sc); 813 /* XXX: re_diag must not be called when in ALTQ mode */ 814 IF_HANDOFF(&ifp->if_snd, m0, ifp); 815 RL_LOCK(sc); 816 m0 = NULL; 817 818 /* Wait for it to propagate through the chip */ 819 820 DELAY(100000); 821 for (i = 0; i < RL_TIMEOUT; i++) { 822 status = CSR_READ_2(sc, RL_ISR); 823 CSR_WRITE_2(sc, RL_ISR, status); 824 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 825 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 826 break; 827 DELAY(10); 828 } 829 830 if (i == RL_TIMEOUT) { 831 device_printf(sc->rl_dev, 832 "diagnostic failed, failed to receive packet in" 833 " loopback mode\n"); 834 error = EIO; 835 goto done; 836 } 837 838 /* 839 * The packet should have been dumped into the first 840 * entry in the RX DMA ring. Grab it from there. 841 */ 842 843 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 844 sc->rl_ldata.rl_rx_list_map, 845 BUS_DMASYNC_POSTREAD); 846 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 847 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 848 BUS_DMASYNC_POSTREAD); 849 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 850 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 851 852 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 853 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 854 eh = mtod(m0, struct ether_header *); 855 856 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 857 total_len = RL_RXBYTES(cur_rx); 858 rxstat = le32toh(cur_rx->rl_cmdstat); 859 860 if (total_len != ETHER_MIN_LEN) { 861 device_printf(sc->rl_dev, 862 "diagnostic failed, received short packet\n"); 863 error = EIO; 864 goto done; 865 } 866 867 /* Test that the received packet data matches what we sent. */ 868 869 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 870 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 871 ntohs(eh->ether_type) != ETHERTYPE_IP) { 872 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 873 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 874 dst, ":", src, ":", ETHERTYPE_IP); 875 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 876 eh->ether_dhost, ":", eh->ether_shost, ":", 877 ntohs(eh->ether_type)); 878 device_printf(sc->rl_dev, "You may have a defective 32-bit " 879 "NIC plugged into a 64-bit PCI slot.\n"); 880 device_printf(sc->rl_dev, "Please re-install the NIC in a " 881 "32-bit slot for proper operation.\n"); 882 device_printf(sc->rl_dev, "Read the re(4) man page for more " 883 "details.\n"); 884 error = EIO; 885 } 886 887 done: 888 /* Turn interface off, release resources */ 889 890 sc->rl_testmode = 0; 891 sc->rl_flags &= ~RL_FLAG_LINK; 892 ifp->if_flags &= ~IFF_PROMISC; 893 re_stop(sc); 894 if (m0 != NULL) 895 m_freem(m0); 896 897 RL_UNLOCK(sc); 898 899 return (error); 900 } 901 902 #endif 903 904 /* 905 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 906 * IDs against our list and return a device name if we find a match. 907 */ 908 static int 909 re_probe(device_t dev) 910 { 911 const struct rl_type *t; 912 uint16_t devid, vendor; 913 uint16_t revid, sdevid; 914 int i; 915 916 vendor = pci_get_vendor(dev); 917 devid = pci_get_device(dev); 918 revid = pci_get_revid(dev); 919 sdevid = pci_get_subdevice(dev); 920 921 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 922 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 923 /* 924 * Only attach to rev. 3 of the Linksys EG1032 adapter. 925 * Rev. 2 is supported by sk(4). 926 */ 927 return (ENXIO); 928 } 929 } 930 931 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 932 if (revid != 0x20) { 933 /* 8139, let rl(4) take care of this device. */ 934 return (ENXIO); 935 } 936 } 937 938 t = re_devs; 939 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 940 if (vendor == t->rl_vid && devid == t->rl_did) { 941 device_set_desc(dev, t->rl_name); 942 return (BUS_PROBE_DEFAULT); 943 } 944 } 945 946 return (ENXIO); 947 } 948 949 /* 950 * Map a single buffer address. 951 */ 952 953 static void 954 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 955 { 956 bus_addr_t *addr; 957 958 if (error) 959 return; 960 961 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 962 addr = arg; 963 *addr = segs->ds_addr; 964 } 965 966 static int 967 re_allocmem(device_t dev, struct rl_softc *sc) 968 { 969 bus_addr_t lowaddr; 970 bus_size_t rx_list_size, tx_list_size; 971 int error; 972 int i; 973 974 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 975 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 976 977 /* 978 * Allocate the parent bus DMA tag appropriate for PCI. 979 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 980 * register should be set. However some RealTek chips are known 981 * to be buggy on DAC handling, therefore disable DAC by limiting 982 * DMA address space to 32bit. PCIe variants of RealTek chips 983 * may not have the limitation. 984 */ 985 lowaddr = BUS_SPACE_MAXADDR; 986 if ((sc->rl_flags & RL_FLAG_PCIE) == 0) 987 lowaddr = BUS_SPACE_MAXADDR_32BIT; 988 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 989 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 990 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 991 NULL, NULL, &sc->rl_parent_tag); 992 if (error) { 993 device_printf(dev, "could not allocate parent DMA tag\n"); 994 return (error); 995 } 996 997 /* 998 * Allocate map for TX mbufs. 999 */ 1000 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 1001 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1002 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 1003 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 1004 if (error) { 1005 device_printf(dev, "could not allocate TX DMA tag\n"); 1006 return (error); 1007 } 1008 1009 /* 1010 * Allocate map for RX mbufs. 1011 */ 1012 1013 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1014 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 1015 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1016 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL, 1017 &sc->rl_ldata.rl_jrx_mtag); 1018 if (error) { 1019 device_printf(dev, 1020 "could not allocate jumbo RX DMA tag\n"); 1021 return (error); 1022 } 1023 } 1024 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1025 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1026 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1027 if (error) { 1028 device_printf(dev, "could not allocate RX DMA tag\n"); 1029 return (error); 1030 } 1031 1032 /* 1033 * Allocate map for TX descriptor list. 1034 */ 1035 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1036 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1037 NULL, tx_list_size, 1, tx_list_size, 0, 1038 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1039 if (error) { 1040 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1041 return (error); 1042 } 1043 1044 /* Allocate DMA'able memory for the TX ring */ 1045 1046 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1047 (void **)&sc->rl_ldata.rl_tx_list, 1048 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1049 &sc->rl_ldata.rl_tx_list_map); 1050 if (error) { 1051 device_printf(dev, "could not allocate TX DMA ring\n"); 1052 return (error); 1053 } 1054 1055 /* Load the map for the TX ring. */ 1056 1057 sc->rl_ldata.rl_tx_list_addr = 0; 1058 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1059 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1060 tx_list_size, re_dma_map_addr, 1061 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1062 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1063 device_printf(dev, "could not load TX DMA ring\n"); 1064 return (ENOMEM); 1065 } 1066 1067 /* Create DMA maps for TX buffers */ 1068 1069 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1070 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1071 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1072 if (error) { 1073 device_printf(dev, "could not create DMA map for TX\n"); 1074 return (error); 1075 } 1076 } 1077 1078 /* 1079 * Allocate map for RX descriptor list. 1080 */ 1081 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1082 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1083 NULL, rx_list_size, 1, rx_list_size, 0, 1084 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1085 if (error) { 1086 device_printf(dev, "could not create RX DMA ring tag\n"); 1087 return (error); 1088 } 1089 1090 /* Allocate DMA'able memory for the RX ring */ 1091 1092 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1093 (void **)&sc->rl_ldata.rl_rx_list, 1094 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1095 &sc->rl_ldata.rl_rx_list_map); 1096 if (error) { 1097 device_printf(dev, "could not allocate RX DMA ring\n"); 1098 return (error); 1099 } 1100 1101 /* Load the map for the RX ring. */ 1102 1103 sc->rl_ldata.rl_rx_list_addr = 0; 1104 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1105 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1106 rx_list_size, re_dma_map_addr, 1107 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1108 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1109 device_printf(dev, "could not load RX DMA ring\n"); 1110 return (ENOMEM); 1111 } 1112 1113 /* Create DMA maps for RX buffers */ 1114 1115 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1116 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1117 &sc->rl_ldata.rl_jrx_sparemap); 1118 if (error) { 1119 device_printf(dev, 1120 "could not create spare DMA map for jumbo RX\n"); 1121 return (error); 1122 } 1123 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1124 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1125 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1126 if (error) { 1127 device_printf(dev, 1128 "could not create DMA map for jumbo RX\n"); 1129 return (error); 1130 } 1131 } 1132 } 1133 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1134 &sc->rl_ldata.rl_rx_sparemap); 1135 if (error) { 1136 device_printf(dev, "could not create spare DMA map for RX\n"); 1137 return (error); 1138 } 1139 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1140 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1141 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1142 if (error) { 1143 device_printf(dev, "could not create DMA map for RX\n"); 1144 return (error); 1145 } 1146 } 1147 1148 /* Create DMA map for statistics. */ 1149 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0, 1150 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1151 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL, 1152 &sc->rl_ldata.rl_stag); 1153 if (error) { 1154 device_printf(dev, "could not create statistics DMA tag\n"); 1155 return (error); 1156 } 1157 /* Allocate DMA'able memory for statistics. */ 1158 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag, 1159 (void **)&sc->rl_ldata.rl_stats, 1160 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1161 &sc->rl_ldata.rl_smap); 1162 if (error) { 1163 device_printf(dev, 1164 "could not allocate statistics DMA memory\n"); 1165 return (error); 1166 } 1167 /* Load the map for statistics. */ 1168 sc->rl_ldata.rl_stats_addr = 0; 1169 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap, 1170 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr, 1171 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT); 1172 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) { 1173 device_printf(dev, "could not load statistics DMA memory\n"); 1174 return (ENOMEM); 1175 } 1176 1177 return (0); 1178 } 1179 1180 /* 1181 * Attach the interface. Allocate softc structures, do ifmedia 1182 * setup and ethernet/BPF attach. 1183 */ 1184 static int 1185 re_attach(device_t dev) 1186 { 1187 u_char eaddr[ETHER_ADDR_LEN]; 1188 u_int16_t as[ETHER_ADDR_LEN / 2]; 1189 struct rl_softc *sc; 1190 struct ifnet *ifp; 1191 const struct rl_hwrev *hw_rev; 1192 u_int32_t cap, ctl; 1193 int hwrev; 1194 u_int16_t devid, re_did = 0; 1195 int error = 0, i, phy, rid; 1196 int msic, msixc, reg; 1197 uint8_t cfg; 1198 1199 sc = device_get_softc(dev); 1200 sc->rl_dev = dev; 1201 1202 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1203 MTX_DEF); 1204 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1205 1206 /* 1207 * Map control/status registers. 1208 */ 1209 pci_enable_busmaster(dev); 1210 1211 devid = pci_get_device(dev); 1212 /* 1213 * Prefer memory space register mapping over IO space. 1214 * Because RTL8169SC does not seem to work when memory mapping 1215 * is used always activate io mapping. 1216 */ 1217 if (devid == RT_DEVICEID_8169SC) 1218 prefer_iomap = 1; 1219 if (prefer_iomap == 0) { 1220 sc->rl_res_id = PCIR_BAR(1); 1221 sc->rl_res_type = SYS_RES_MEMORY; 1222 /* RTL8168/8101E seems to use different BARs. */ 1223 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1224 sc->rl_res_id = PCIR_BAR(2); 1225 } else { 1226 sc->rl_res_id = PCIR_BAR(0); 1227 sc->rl_res_type = SYS_RES_IOPORT; 1228 } 1229 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1230 &sc->rl_res_id, RF_ACTIVE); 1231 if (sc->rl_res == NULL && prefer_iomap == 0) { 1232 sc->rl_res_id = PCIR_BAR(0); 1233 sc->rl_res_type = SYS_RES_IOPORT; 1234 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1235 &sc->rl_res_id, RF_ACTIVE); 1236 } 1237 if (sc->rl_res == NULL) { 1238 device_printf(dev, "couldn't map ports/memory\n"); 1239 error = ENXIO; 1240 goto fail; 1241 } 1242 1243 sc->rl_btag = rman_get_bustag(sc->rl_res); 1244 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1245 1246 msic = pci_msi_count(dev); 1247 msixc = pci_msix_count(dev); 1248 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 1249 sc->rl_flags |= RL_FLAG_PCIE; 1250 sc->rl_expcap = reg; 1251 } 1252 if (bootverbose) { 1253 device_printf(dev, "MSI count : %d\n", msic); 1254 device_printf(dev, "MSI-X count : %d\n", msixc); 1255 } 1256 if (msix_disable > 0) 1257 msixc = 0; 1258 if (msi_disable > 0) 1259 msic = 0; 1260 /* Prefer MSI-X to MSI. */ 1261 if (msixc > 0) { 1262 msixc = 1; 1263 rid = PCIR_BAR(4); 1264 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1265 &rid, RF_ACTIVE); 1266 if (sc->rl_res_pba == NULL) { 1267 device_printf(sc->rl_dev, 1268 "could not allocate MSI-X PBA resource\n"); 1269 } 1270 if (sc->rl_res_pba != NULL && 1271 pci_alloc_msix(dev, &msixc) == 0) { 1272 if (msixc == 1) { 1273 device_printf(dev, "Using %d MSI-X message\n", 1274 msixc); 1275 sc->rl_flags |= RL_FLAG_MSIX; 1276 } else 1277 pci_release_msi(dev); 1278 } 1279 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) { 1280 if (sc->rl_res_pba != NULL) 1281 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1282 sc->rl_res_pba); 1283 sc->rl_res_pba = NULL; 1284 msixc = 0; 1285 } 1286 } 1287 /* Prefer MSI to INTx. */ 1288 if (msixc == 0 && msic > 0) { 1289 msic = 1; 1290 if (pci_alloc_msi(dev, &msic) == 0) { 1291 if (msic == RL_MSI_MESSAGES) { 1292 device_printf(dev, "Using %d MSI message\n", 1293 msic); 1294 sc->rl_flags |= RL_FLAG_MSI; 1295 /* Explicitly set MSI enable bit. */ 1296 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1297 cfg = CSR_READ_1(sc, RL_CFG2); 1298 cfg |= RL_CFG2_MSI; 1299 CSR_WRITE_1(sc, RL_CFG2, cfg); 1300 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1301 } else 1302 pci_release_msi(dev); 1303 } 1304 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1305 msic = 0; 1306 } 1307 1308 /* Allocate interrupt */ 1309 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) { 1310 rid = 0; 1311 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1312 RF_SHAREABLE | RF_ACTIVE); 1313 if (sc->rl_irq[0] == NULL) { 1314 device_printf(dev, "couldn't allocate IRQ resources\n"); 1315 error = ENXIO; 1316 goto fail; 1317 } 1318 } else { 1319 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1320 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1321 SYS_RES_IRQ, &rid, RF_ACTIVE); 1322 if (sc->rl_irq[i] == NULL) { 1323 device_printf(dev, 1324 "couldn't llocate IRQ resources for " 1325 "message %d\n", rid); 1326 error = ENXIO; 1327 goto fail; 1328 } 1329 } 1330 } 1331 1332 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1333 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1334 cfg = CSR_READ_1(sc, RL_CFG2); 1335 if ((cfg & RL_CFG2_MSI) != 0) { 1336 device_printf(dev, "turning off MSI enable bit.\n"); 1337 cfg &= ~RL_CFG2_MSI; 1338 CSR_WRITE_1(sc, RL_CFG2, cfg); 1339 } 1340 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1341 } 1342 1343 /* Disable ASPM L0S/L1. */ 1344 if (sc->rl_expcap != 0) { 1345 cap = pci_read_config(dev, sc->rl_expcap + 1346 PCIR_EXPRESS_LINK_CAP, 2); 1347 if ((cap & PCIM_LINK_CAP_ASPM) != 0) { 1348 ctl = pci_read_config(dev, sc->rl_expcap + 1349 PCIR_EXPRESS_LINK_CTL, 2); 1350 if ((ctl & 0x0003) != 0) { 1351 ctl &= ~0x0003; 1352 pci_write_config(dev, sc->rl_expcap + 1353 PCIR_EXPRESS_LINK_CTL, ctl, 2); 1354 device_printf(dev, "ASPM disabled\n"); 1355 } 1356 } else 1357 device_printf(dev, "no ASPM capability\n"); 1358 } 1359 1360 hw_rev = re_hwrevs; 1361 hwrev = CSR_READ_4(sc, RL_TXCFG); 1362 switch (hwrev & 0x70000000) { 1363 case 0x00000000: 1364 case 0x10000000: 1365 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1366 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1367 break; 1368 default: 1369 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1370 hwrev &= RL_TXCFG_HWREV; 1371 break; 1372 } 1373 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1374 while (hw_rev->rl_desc != NULL) { 1375 if (hw_rev->rl_rev == hwrev) { 1376 sc->rl_type = hw_rev->rl_type; 1377 sc->rl_hwrev = hw_rev; 1378 break; 1379 } 1380 hw_rev++; 1381 } 1382 if (hw_rev->rl_desc == NULL) { 1383 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1384 error = ENXIO; 1385 goto fail; 1386 } 1387 1388 switch (hw_rev->rl_rev) { 1389 case RL_HWREV_8139CPLUS: 1390 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD; 1391 break; 1392 case RL_HWREV_8100E: 1393 case RL_HWREV_8101E: 1394 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER; 1395 break; 1396 case RL_HWREV_8102E: 1397 case RL_HWREV_8102EL: 1398 case RL_HWREV_8102EL_SPIN1: 1399 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1400 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1401 RL_FLAG_AUTOPAD; 1402 break; 1403 case RL_HWREV_8103E: 1404 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1405 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1406 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP; 1407 break; 1408 case RL_HWREV_8401E: 1409 case RL_HWREV_8105E: 1410 case RL_HWREV_8105E_SPIN1: 1411 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1412 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1413 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 1414 break; 1415 case RL_HWREV_8402: 1416 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1417 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1418 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | 1419 RL_FLAG_CMDSTOP_WAIT_TXQ; 1420 break; 1421 case RL_HWREV_8168B_SPIN1: 1422 case RL_HWREV_8168B_SPIN2: 1423 sc->rl_flags |= RL_FLAG_WOLRXENB; 1424 /* FALLTHROUGH */ 1425 case RL_HWREV_8168B_SPIN3: 1426 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1427 break; 1428 case RL_HWREV_8168C_SPIN2: 1429 sc->rl_flags |= RL_FLAG_MACSLEEP; 1430 /* FALLTHROUGH */ 1431 case RL_HWREV_8168C: 1432 if ((hwrev & 0x00700000) == 0x00200000) 1433 sc->rl_flags |= RL_FLAG_MACSLEEP; 1434 /* FALLTHROUGH */ 1435 case RL_HWREV_8168CP: 1436 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1437 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1438 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1439 break; 1440 case RL_HWREV_8168D: 1441 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1442 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1443 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1444 RL_FLAG_WOL_MANLINK; 1445 break; 1446 case RL_HWREV_8168DP: 1447 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1448 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD | 1449 RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK; 1450 break; 1451 case RL_HWREV_8168E: 1452 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1453 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1454 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1455 RL_FLAG_WOL_MANLINK; 1456 break; 1457 case RL_HWREV_8168E_VL: 1458 case RL_HWREV_8168F: 1459 case RL_HWREV_8411: 1460 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1461 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1462 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1463 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK; 1464 break; 1465 case RL_HWREV_8169_8110SB: 1466 case RL_HWREV_8169_8110SBL: 1467 case RL_HWREV_8169_8110SC: 1468 case RL_HWREV_8169_8110SCE: 1469 sc->rl_flags |= RL_FLAG_PHYWAKE; 1470 /* FALLTHROUGH */ 1471 case RL_HWREV_8169: 1472 case RL_HWREV_8169S: 1473 case RL_HWREV_8110S: 1474 sc->rl_flags |= RL_FLAG_MACRESET; 1475 break; 1476 default: 1477 break; 1478 } 1479 1480 if (sc->rl_hwrev->rl_rev == RL_HWREV_8139CPLUS) { 1481 sc->rl_cfg0 = RL_8139_CFG0; 1482 sc->rl_cfg1 = RL_8139_CFG1; 1483 sc->rl_cfg2 = 0; 1484 sc->rl_cfg3 = RL_8139_CFG3; 1485 sc->rl_cfg4 = RL_8139_CFG4; 1486 sc->rl_cfg5 = RL_8139_CFG5; 1487 } else { 1488 sc->rl_cfg0 = RL_CFG0; 1489 sc->rl_cfg1 = RL_CFG1; 1490 sc->rl_cfg2 = RL_CFG2; 1491 sc->rl_cfg3 = RL_CFG3; 1492 sc->rl_cfg4 = RL_CFG4; 1493 sc->rl_cfg5 = RL_CFG5; 1494 } 1495 1496 /* Reset the adapter. */ 1497 RL_LOCK(sc); 1498 re_reset(sc); 1499 RL_UNLOCK(sc); 1500 1501 /* Enable PME. */ 1502 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1503 cfg = CSR_READ_1(sc, sc->rl_cfg1); 1504 cfg |= RL_CFG1_PME; 1505 CSR_WRITE_1(sc, sc->rl_cfg1, cfg); 1506 cfg = CSR_READ_1(sc, sc->rl_cfg5); 1507 cfg &= RL_CFG5_PME_STS; 1508 CSR_WRITE_1(sc, sc->rl_cfg5, cfg); 1509 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1510 1511 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1512 /* 1513 * XXX Should have a better way to extract station 1514 * address from EEPROM. 1515 */ 1516 for (i = 0; i < ETHER_ADDR_LEN; i++) 1517 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1518 } else { 1519 sc->rl_eewidth = RL_9356_ADDR_LEN; 1520 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1521 if (re_did != 0x8129) 1522 sc->rl_eewidth = RL_9346_ADDR_LEN; 1523 1524 /* 1525 * Get station address from the EEPROM. 1526 */ 1527 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1528 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1529 as[i] = le16toh(as[i]); 1530 bcopy(as, eaddr, ETHER_ADDR_LEN); 1531 } 1532 1533 if (sc->rl_type == RL_8169) { 1534 /* Set RX length mask and number of descriptors. */ 1535 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1536 sc->rl_txstart = RL_GTXSTART; 1537 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1538 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1539 } else { 1540 /* Set RX length mask and number of descriptors. */ 1541 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1542 sc->rl_txstart = RL_TXSTART; 1543 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1544 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1545 } 1546 1547 error = re_allocmem(dev, sc); 1548 if (error) 1549 goto fail; 1550 re_add_sysctls(sc); 1551 1552 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1553 if (ifp == NULL) { 1554 device_printf(dev, "can not if_alloc()\n"); 1555 error = ENOSPC; 1556 goto fail; 1557 } 1558 1559 /* Take controller out of deep sleep mode. */ 1560 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1561 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1562 CSR_WRITE_1(sc, RL_GPIO, 1563 CSR_READ_1(sc, RL_GPIO) | 0x01); 1564 else 1565 CSR_WRITE_1(sc, RL_GPIO, 1566 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1567 } 1568 1569 /* Take PHY out of power down mode. */ 1570 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) { 1571 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80); 1572 if (hw_rev->rl_rev == RL_HWREV_8401E) 1573 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08); 1574 } 1575 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1576 re_gmii_writereg(dev, 1, 0x1f, 0); 1577 re_gmii_writereg(dev, 1, 0x0e, 0); 1578 } 1579 1580 ifp->if_softc = sc; 1581 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1582 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1583 ifp->if_ioctl = re_ioctl; 1584 ifp->if_start = re_start; 1585 /* 1586 * RTL8168/8111C generates wrong IP checksummed frame if the 1587 * packet has IP options so disable TX IP checksum offloading. 1588 */ 1589 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C || 1590 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2) 1591 ifp->if_hwassist = CSUM_TCP | CSUM_UDP; 1592 else 1593 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 1594 ifp->if_hwassist |= CSUM_TSO; 1595 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1596 ifp->if_capenable = ifp->if_capabilities; 1597 ifp->if_init = re_init; 1598 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1599 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1600 IFQ_SET_READY(&ifp->if_snd); 1601 1602 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1603 1604 #define RE_PHYAD_INTERNAL 0 1605 1606 /* Do MII setup. */ 1607 phy = RE_PHYAD_INTERNAL; 1608 if (sc->rl_type == RL_8169) 1609 phy = 1; 1610 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd, 1611 re_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, MIIF_DOPAUSE); 1612 if (error != 0) { 1613 device_printf(dev, "attaching PHYs failed\n"); 1614 goto fail; 1615 } 1616 1617 /* 1618 * Call MI attach routine. 1619 */ 1620 ether_ifattach(ifp, eaddr); 1621 1622 /* VLAN capability setup */ 1623 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1624 if (ifp->if_capabilities & IFCAP_HWCSUM) 1625 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1626 /* Enable WOL if PM is supported. */ 1627 if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0) 1628 ifp->if_capabilities |= IFCAP_WOL; 1629 ifp->if_capenable = ifp->if_capabilities; 1630 ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST); 1631 /* 1632 * Don't enable TSO by default. It is known to generate 1633 * corrupted TCP segments(bad TCP options) under certain 1634 * circumtances. 1635 */ 1636 ifp->if_hwassist &= ~CSUM_TSO; 1637 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 1638 #ifdef DEVICE_POLLING 1639 ifp->if_capabilities |= IFCAP_POLLING; 1640 #endif 1641 /* 1642 * Tell the upper layer(s) we support long frames. 1643 * Must appear after the call to ether_ifattach() because 1644 * ether_ifattach() sets ifi_hdrlen to the default value. 1645 */ 1646 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1647 1648 #ifdef DEV_NETMAP 1649 re_netmap_attach(sc); 1650 #endif /* DEV_NETMAP */ 1651 #ifdef RE_DIAG 1652 /* 1653 * Perform hardware diagnostic on the original RTL8169. 1654 * Some 32-bit cards were incorrectly wired and would 1655 * malfunction if plugged into a 64-bit slot. 1656 */ 1657 1658 if (hwrev == RL_HWREV_8169) { 1659 error = re_diag(sc); 1660 if (error) { 1661 device_printf(dev, 1662 "attach aborted due to hardware diag failure\n"); 1663 ether_ifdetach(ifp); 1664 goto fail; 1665 } 1666 } 1667 #endif 1668 1669 #ifdef RE_TX_MODERATION 1670 intr_filter = 1; 1671 #endif 1672 /* Hook interrupt last to avoid having to lock softc */ 1673 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 1674 intr_filter == 0) { 1675 error = bus_setup_intr(dev, sc->rl_irq[0], 1676 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc, 1677 &sc->rl_intrhand[0]); 1678 } else { 1679 error = bus_setup_intr(dev, sc->rl_irq[0], 1680 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1681 &sc->rl_intrhand[0]); 1682 } 1683 if (error) { 1684 device_printf(dev, "couldn't set up irq\n"); 1685 ether_ifdetach(ifp); 1686 } 1687 1688 fail: 1689 1690 if (error) 1691 re_detach(dev); 1692 1693 return (error); 1694 } 1695 1696 /* 1697 * Shutdown hardware and free up resources. This can be called any 1698 * time after the mutex has been initialized. It is called in both 1699 * the error case in attach and the normal detach case so it needs 1700 * to be careful about only freeing resources that have actually been 1701 * allocated. 1702 */ 1703 static int 1704 re_detach(device_t dev) 1705 { 1706 struct rl_softc *sc; 1707 struct ifnet *ifp; 1708 int i, rid; 1709 1710 sc = device_get_softc(dev); 1711 ifp = sc->rl_ifp; 1712 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1713 1714 /* These should only be active if attach succeeded */ 1715 if (device_is_attached(dev)) { 1716 #ifdef DEVICE_POLLING 1717 if (ifp->if_capenable & IFCAP_POLLING) 1718 ether_poll_deregister(ifp); 1719 #endif 1720 RL_LOCK(sc); 1721 #if 0 1722 sc->suspended = 1; 1723 #endif 1724 re_stop(sc); 1725 RL_UNLOCK(sc); 1726 callout_drain(&sc->rl_stat_callout); 1727 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1728 /* 1729 * Force off the IFF_UP flag here, in case someone 1730 * still had a BPF descriptor attached to this 1731 * interface. If they do, ether_ifdetach() will cause 1732 * the BPF code to try and clear the promisc mode 1733 * flag, which will bubble down to re_ioctl(), 1734 * which will try to call re_init() again. This will 1735 * turn the NIC back on and restart the MII ticker, 1736 * which will panic the system when the kernel tries 1737 * to invoke the re_tick() function that isn't there 1738 * anymore. 1739 */ 1740 ifp->if_flags &= ~IFF_UP; 1741 ether_ifdetach(ifp); 1742 } 1743 if (sc->rl_miibus) 1744 device_delete_child(dev, sc->rl_miibus); 1745 bus_generic_detach(dev); 1746 1747 /* 1748 * The rest is resource deallocation, so we should already be 1749 * stopped here. 1750 */ 1751 1752 if (sc->rl_intrhand[0] != NULL) { 1753 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]); 1754 sc->rl_intrhand[0] = NULL; 1755 } 1756 if (ifp != NULL) { 1757 #ifdef DEV_NETMAP 1758 netmap_detach(ifp); 1759 #endif /* DEV_NETMAP */ 1760 if_free(ifp); 1761 } 1762 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 1763 rid = 0; 1764 else 1765 rid = 1; 1766 if (sc->rl_irq[0] != NULL) { 1767 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]); 1768 sc->rl_irq[0] = NULL; 1769 } 1770 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0) 1771 pci_release_msi(dev); 1772 if (sc->rl_res_pba) { 1773 rid = PCIR_BAR(4); 1774 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba); 1775 } 1776 if (sc->rl_res) 1777 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1778 sc->rl_res); 1779 1780 /* Unload and free the RX DMA ring memory and map */ 1781 1782 if (sc->rl_ldata.rl_rx_list_tag) { 1783 if (sc->rl_ldata.rl_rx_list_map) 1784 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1785 sc->rl_ldata.rl_rx_list_map); 1786 if (sc->rl_ldata.rl_rx_list_map && sc->rl_ldata.rl_rx_list) 1787 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1788 sc->rl_ldata.rl_rx_list, 1789 sc->rl_ldata.rl_rx_list_map); 1790 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1791 } 1792 1793 /* Unload and free the TX DMA ring memory and map */ 1794 1795 if (sc->rl_ldata.rl_tx_list_tag) { 1796 if (sc->rl_ldata.rl_tx_list_map) 1797 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1798 sc->rl_ldata.rl_tx_list_map); 1799 if (sc->rl_ldata.rl_tx_list_map && sc->rl_ldata.rl_tx_list) 1800 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1801 sc->rl_ldata.rl_tx_list, 1802 sc->rl_ldata.rl_tx_list_map); 1803 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1804 } 1805 1806 /* Destroy all the RX and TX buffer maps */ 1807 1808 if (sc->rl_ldata.rl_tx_mtag) { 1809 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1810 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap) 1811 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1812 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1813 } 1814 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1815 } 1816 if (sc->rl_ldata.rl_rx_mtag) { 1817 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1818 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap) 1819 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1820 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1821 } 1822 if (sc->rl_ldata.rl_rx_sparemap) 1823 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1824 sc->rl_ldata.rl_rx_sparemap); 1825 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1826 } 1827 if (sc->rl_ldata.rl_jrx_mtag) { 1828 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1829 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap) 1830 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1831 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1832 } 1833 if (sc->rl_ldata.rl_jrx_sparemap) 1834 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1835 sc->rl_ldata.rl_jrx_sparemap); 1836 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag); 1837 } 1838 /* Unload and free the stats buffer and map */ 1839 1840 if (sc->rl_ldata.rl_stag) { 1841 if (sc->rl_ldata.rl_smap) 1842 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1843 sc->rl_ldata.rl_smap); 1844 if (sc->rl_ldata.rl_smap && sc->rl_ldata.rl_stats) 1845 bus_dmamem_free(sc->rl_ldata.rl_stag, 1846 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap); 1847 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1848 } 1849 1850 if (sc->rl_parent_tag) 1851 bus_dma_tag_destroy(sc->rl_parent_tag); 1852 1853 mtx_destroy(&sc->rl_mtx); 1854 1855 return (0); 1856 } 1857 1858 static __inline void 1859 re_discard_rxbuf(struct rl_softc *sc, int idx) 1860 { 1861 struct rl_desc *desc; 1862 struct rl_rxdesc *rxd; 1863 uint32_t cmdstat; 1864 1865 if (sc->rl_ifp->if_mtu > RL_MTU && 1866 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 1867 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1868 else 1869 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1870 desc = &sc->rl_ldata.rl_rx_list[idx]; 1871 desc->rl_vlanctl = 0; 1872 cmdstat = rxd->rx_size; 1873 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1874 cmdstat |= RL_RDESC_CMD_EOR; 1875 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1876 } 1877 1878 static int 1879 re_newbuf(struct rl_softc *sc, int idx) 1880 { 1881 struct mbuf *m; 1882 struct rl_rxdesc *rxd; 1883 bus_dma_segment_t segs[1]; 1884 bus_dmamap_t map; 1885 struct rl_desc *desc; 1886 uint32_t cmdstat; 1887 int error, nsegs; 1888 1889 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1890 if (m == NULL) 1891 return (ENOBUFS); 1892 1893 m->m_len = m->m_pkthdr.len = MCLBYTES; 1894 #ifdef RE_FIXUP_RX 1895 /* 1896 * This is part of an evil trick to deal with non-x86 platforms. 1897 * The RealTek chip requires RX buffers to be aligned on 64-bit 1898 * boundaries, but that will hose non-x86 machines. To get around 1899 * this, we leave some empty space at the start of each buffer 1900 * and for non-x86 hosts, we copy the buffer back six bytes 1901 * to achieve word alignment. This is slightly more efficient 1902 * than allocating a new buffer, copying the contents, and 1903 * discarding the old buffer. 1904 */ 1905 m_adj(m, RE_ETHER_ALIGN); 1906 #endif 1907 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1908 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1909 if (error != 0) { 1910 m_freem(m); 1911 return (ENOBUFS); 1912 } 1913 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1914 1915 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1916 if (rxd->rx_m != NULL) { 1917 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1918 BUS_DMASYNC_POSTREAD); 1919 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1920 } 1921 1922 rxd->rx_m = m; 1923 map = rxd->rx_dmamap; 1924 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1925 rxd->rx_size = segs[0].ds_len; 1926 sc->rl_ldata.rl_rx_sparemap = map; 1927 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1928 BUS_DMASYNC_PREREAD); 1929 1930 desc = &sc->rl_ldata.rl_rx_list[idx]; 1931 desc->rl_vlanctl = 0; 1932 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1933 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1934 cmdstat = segs[0].ds_len; 1935 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1936 cmdstat |= RL_RDESC_CMD_EOR; 1937 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1938 1939 return (0); 1940 } 1941 1942 static int 1943 re_jumbo_newbuf(struct rl_softc *sc, int idx) 1944 { 1945 struct mbuf *m; 1946 struct rl_rxdesc *rxd; 1947 bus_dma_segment_t segs[1]; 1948 bus_dmamap_t map; 1949 struct rl_desc *desc; 1950 uint32_t cmdstat; 1951 int error, nsegs; 1952 1953 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1954 if (m == NULL) 1955 return (ENOBUFS); 1956 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1957 #ifdef RE_FIXUP_RX 1958 m_adj(m, RE_ETHER_ALIGN); 1959 #endif 1960 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag, 1961 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1962 if (error != 0) { 1963 m_freem(m); 1964 return (ENOBUFS); 1965 } 1966 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1967 1968 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1969 if (rxd->rx_m != NULL) { 1970 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 1971 BUS_DMASYNC_POSTREAD); 1972 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap); 1973 } 1974 1975 rxd->rx_m = m; 1976 map = rxd->rx_dmamap; 1977 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap; 1978 rxd->rx_size = segs[0].ds_len; 1979 sc->rl_ldata.rl_jrx_sparemap = map; 1980 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 1981 BUS_DMASYNC_PREREAD); 1982 1983 desc = &sc->rl_ldata.rl_rx_list[idx]; 1984 desc->rl_vlanctl = 0; 1985 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1986 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1987 cmdstat = segs[0].ds_len; 1988 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1989 cmdstat |= RL_RDESC_CMD_EOR; 1990 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1991 1992 return (0); 1993 } 1994 1995 #ifdef RE_FIXUP_RX 1996 static __inline void 1997 re_fixup_rx(struct mbuf *m) 1998 { 1999 int i; 2000 uint16_t *src, *dst; 2001 2002 src = mtod(m, uint16_t *); 2003 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 2004 2005 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2006 *dst++ = *src++; 2007 2008 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 2009 } 2010 #endif 2011 2012 static int 2013 re_tx_list_init(struct rl_softc *sc) 2014 { 2015 struct rl_desc *desc; 2016 int i; 2017 2018 RL_LOCK_ASSERT(sc); 2019 2020 bzero(sc->rl_ldata.rl_tx_list, 2021 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 2022 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 2023 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 2024 #ifdef DEV_NETMAP 2025 re_netmap_tx_init(sc); 2026 #endif /* DEV_NETMAP */ 2027 /* Set EOR. */ 2028 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 2029 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 2030 2031 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2032 sc->rl_ldata.rl_tx_list_map, 2033 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2034 2035 sc->rl_ldata.rl_tx_prodidx = 0; 2036 sc->rl_ldata.rl_tx_considx = 0; 2037 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 2038 2039 return (0); 2040 } 2041 2042 static int 2043 re_rx_list_init(struct rl_softc *sc) 2044 { 2045 int error, i; 2046 2047 bzero(sc->rl_ldata.rl_rx_list, 2048 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2049 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2050 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 2051 if ((error = re_newbuf(sc, i)) != 0) 2052 return (error); 2053 } 2054 #ifdef DEV_NETMAP 2055 re_netmap_rx_init(sc); 2056 #endif /* DEV_NETMAP */ 2057 2058 /* Flush the RX descriptors */ 2059 2060 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2061 sc->rl_ldata.rl_rx_list_map, 2062 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2063 2064 sc->rl_ldata.rl_rx_prodidx = 0; 2065 sc->rl_head = sc->rl_tail = NULL; 2066 sc->rl_int_rx_act = 0; 2067 2068 return (0); 2069 } 2070 2071 static int 2072 re_jrx_list_init(struct rl_softc *sc) 2073 { 2074 int error, i; 2075 2076 bzero(sc->rl_ldata.rl_rx_list, 2077 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2078 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2079 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL; 2080 if ((error = re_jumbo_newbuf(sc, i)) != 0) 2081 return (error); 2082 } 2083 2084 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2085 sc->rl_ldata.rl_rx_list_map, 2086 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2087 2088 sc->rl_ldata.rl_rx_prodidx = 0; 2089 sc->rl_head = sc->rl_tail = NULL; 2090 sc->rl_int_rx_act = 0; 2091 2092 return (0); 2093 } 2094 2095 /* 2096 * RX handler for C+ and 8169. For the gigE chips, we support 2097 * the reception of jumbo frames that have been fragmented 2098 * across multiple 2K mbuf cluster buffers. 2099 */ 2100 static int 2101 re_rxeof(struct rl_softc *sc, int *rx_npktsp) 2102 { 2103 struct mbuf *m; 2104 struct ifnet *ifp; 2105 int i, rxerr, total_len; 2106 struct rl_desc *cur_rx; 2107 u_int32_t rxstat, rxvlan; 2108 int jumbo, maxpkt = 16, rx_npkts = 0; 2109 2110 RL_LOCK_ASSERT(sc); 2111 2112 ifp = sc->rl_ifp; 2113 #ifdef DEV_NETMAP 2114 if (ifp->if_capenable & IFCAP_NETMAP) { 2115 NA(ifp)->rx_rings[0].nr_kflags |= NKR_PENDINTR; 2116 selwakeuppri(&NA(ifp)->rx_rings[0].si, PI_NET); 2117 return 0; 2118 } 2119 #endif /* DEV_NETMAP */ 2120 if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 2121 jumbo = 1; 2122 else 2123 jumbo = 0; 2124 2125 /* Invalidate the descriptor memory */ 2126 2127 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2128 sc->rl_ldata.rl_rx_list_map, 2129 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2130 2131 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 2132 i = RL_RX_DESC_NXT(sc, i)) { 2133 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2134 break; 2135 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 2136 rxstat = le32toh(cur_rx->rl_cmdstat); 2137 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 2138 break; 2139 total_len = rxstat & sc->rl_rxlenmask; 2140 rxvlan = le32toh(cur_rx->rl_vlanctl); 2141 if (jumbo != 0) 2142 m = sc->rl_ldata.rl_jrx_desc[i].rx_m; 2143 else 2144 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 2145 2146 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 2147 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) != 2148 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) { 2149 /* 2150 * RTL8168C or later controllers do not 2151 * support multi-fragment packet. 2152 */ 2153 re_discard_rxbuf(sc, i); 2154 continue; 2155 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) { 2156 if (re_newbuf(sc, i) != 0) { 2157 /* 2158 * If this is part of a multi-fragment packet, 2159 * discard all the pieces. 2160 */ 2161 if (sc->rl_head != NULL) { 2162 m_freem(sc->rl_head); 2163 sc->rl_head = sc->rl_tail = NULL; 2164 } 2165 re_discard_rxbuf(sc, i); 2166 continue; 2167 } 2168 m->m_len = RE_RX_DESC_BUFLEN; 2169 if (sc->rl_head == NULL) 2170 sc->rl_head = sc->rl_tail = m; 2171 else { 2172 m->m_flags &= ~M_PKTHDR; 2173 sc->rl_tail->m_next = m; 2174 sc->rl_tail = m; 2175 } 2176 continue; 2177 } 2178 2179 /* 2180 * NOTE: for the 8139C+, the frame length field 2181 * is always 12 bits in size, but for the gigE chips, 2182 * it is 13 bits (since the max RX frame length is 16K). 2183 * Unfortunately, all 32 bits in the status word 2184 * were already used, so to make room for the extra 2185 * length bit, RealTek took out the 'frame alignment 2186 * error' bit and shifted the other status bits 2187 * over one slot. The OWN, EOR, FS and LS bits are 2188 * still in the same places. We have already extracted 2189 * the frame length and checked the OWN bit, so rather 2190 * than using an alternate bit mapping, we shift the 2191 * status bits one space to the right so we can evaluate 2192 * them using the 8169 status as though it was in the 2193 * same format as that of the 8139C+. 2194 */ 2195 if (sc->rl_type == RL_8169) 2196 rxstat >>= 1; 2197 2198 /* 2199 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 2200 * set, but if CRC is clear, it will still be a valid frame. 2201 */ 2202 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) { 2203 rxerr = 1; 2204 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 && 2205 total_len > 8191 && 2206 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT) 2207 rxerr = 0; 2208 if (rxerr != 0) { 2209 ifp->if_ierrors++; 2210 /* 2211 * If this is part of a multi-fragment packet, 2212 * discard all the pieces. 2213 */ 2214 if (sc->rl_head != NULL) { 2215 m_freem(sc->rl_head); 2216 sc->rl_head = sc->rl_tail = NULL; 2217 } 2218 re_discard_rxbuf(sc, i); 2219 continue; 2220 } 2221 } 2222 2223 /* 2224 * If allocating a replacement mbuf fails, 2225 * reload the current one. 2226 */ 2227 if (jumbo != 0) 2228 rxerr = re_jumbo_newbuf(sc, i); 2229 else 2230 rxerr = re_newbuf(sc, i); 2231 if (rxerr != 0) { 2232 ifp->if_iqdrops++; 2233 if (sc->rl_head != NULL) { 2234 m_freem(sc->rl_head); 2235 sc->rl_head = sc->rl_tail = NULL; 2236 } 2237 re_discard_rxbuf(sc, i); 2238 continue; 2239 } 2240 2241 if (sc->rl_head != NULL) { 2242 if (jumbo != 0) 2243 m->m_len = total_len; 2244 else { 2245 m->m_len = total_len % RE_RX_DESC_BUFLEN; 2246 if (m->m_len == 0) 2247 m->m_len = RE_RX_DESC_BUFLEN; 2248 } 2249 /* 2250 * Special case: if there's 4 bytes or less 2251 * in this buffer, the mbuf can be discarded: 2252 * the last 4 bytes is the CRC, which we don't 2253 * care about anyway. 2254 */ 2255 if (m->m_len <= ETHER_CRC_LEN) { 2256 sc->rl_tail->m_len -= 2257 (ETHER_CRC_LEN - m->m_len); 2258 m_freem(m); 2259 } else { 2260 m->m_len -= ETHER_CRC_LEN; 2261 m->m_flags &= ~M_PKTHDR; 2262 sc->rl_tail->m_next = m; 2263 } 2264 m = sc->rl_head; 2265 sc->rl_head = sc->rl_tail = NULL; 2266 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 2267 } else 2268 m->m_pkthdr.len = m->m_len = 2269 (total_len - ETHER_CRC_LEN); 2270 2271 #ifdef RE_FIXUP_RX 2272 re_fixup_rx(m); 2273 #endif 2274 ifp->if_ipackets++; 2275 m->m_pkthdr.rcvif = ifp; 2276 2277 /* Do RX checksumming if enabled */ 2278 2279 if (ifp->if_capenable & IFCAP_RXCSUM) { 2280 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2281 /* Check IP header checksum */ 2282 if (rxstat & RL_RDESC_STAT_PROTOID) 2283 m->m_pkthdr.csum_flags |= 2284 CSUM_IP_CHECKED; 2285 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 2286 m->m_pkthdr.csum_flags |= 2287 CSUM_IP_VALID; 2288 2289 /* Check TCP/UDP checksum */ 2290 if ((RL_TCPPKT(rxstat) && 2291 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2292 (RL_UDPPKT(rxstat) && 2293 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2294 m->m_pkthdr.csum_flags |= 2295 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2296 m->m_pkthdr.csum_data = 0xffff; 2297 } 2298 } else { 2299 /* 2300 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 2301 */ 2302 if ((rxstat & RL_RDESC_STAT_PROTOID) && 2303 (rxvlan & RL_RDESC_IPV4)) 2304 m->m_pkthdr.csum_flags |= 2305 CSUM_IP_CHECKED; 2306 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 2307 (rxvlan & RL_RDESC_IPV4)) 2308 m->m_pkthdr.csum_flags |= 2309 CSUM_IP_VALID; 2310 if (((rxstat & RL_RDESC_STAT_TCP) && 2311 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2312 ((rxstat & RL_RDESC_STAT_UDP) && 2313 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2314 m->m_pkthdr.csum_flags |= 2315 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2316 m->m_pkthdr.csum_data = 0xffff; 2317 } 2318 } 2319 } 2320 maxpkt--; 2321 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 2322 m->m_pkthdr.ether_vtag = 2323 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 2324 m->m_flags |= M_VLANTAG; 2325 } 2326 RL_UNLOCK(sc); 2327 (*ifp->if_input)(ifp, m); 2328 RL_LOCK(sc); 2329 rx_npkts++; 2330 } 2331 2332 /* Flush the RX DMA ring */ 2333 2334 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2335 sc->rl_ldata.rl_rx_list_map, 2336 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2337 2338 sc->rl_ldata.rl_rx_prodidx = i; 2339 2340 if (rx_npktsp != NULL) 2341 *rx_npktsp = rx_npkts; 2342 if (maxpkt) 2343 return (EAGAIN); 2344 2345 return (0); 2346 } 2347 2348 static void 2349 re_txeof(struct rl_softc *sc) 2350 { 2351 struct ifnet *ifp; 2352 struct rl_txdesc *txd; 2353 u_int32_t txstat; 2354 int cons; 2355 2356 cons = sc->rl_ldata.rl_tx_considx; 2357 if (cons == sc->rl_ldata.rl_tx_prodidx) 2358 return; 2359 2360 ifp = sc->rl_ifp; 2361 #ifdef DEV_NETMAP 2362 if (ifp->if_capenable & IFCAP_NETMAP) { 2363 selwakeuppri(&NA(ifp)->tx_rings[0].si, PI_NET); 2364 return; 2365 } 2366 #endif /* DEV_NETMAP */ 2367 /* Invalidate the TX descriptor list */ 2368 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2369 sc->rl_ldata.rl_tx_list_map, 2370 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2371 2372 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2373 cons = RL_TX_DESC_NXT(sc, cons)) { 2374 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2375 if (txstat & RL_TDESC_STAT_OWN) 2376 break; 2377 /* 2378 * We only stash mbufs in the last descriptor 2379 * in a fragment chain, which also happens to 2380 * be the only place where the TX status bits 2381 * are valid. 2382 */ 2383 if (txstat & RL_TDESC_CMD_EOF) { 2384 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2385 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2386 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2387 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2388 txd->tx_dmamap); 2389 KASSERT(txd->tx_m != NULL, 2390 ("%s: freeing NULL mbufs!", __func__)); 2391 m_freem(txd->tx_m); 2392 txd->tx_m = NULL; 2393 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2394 RL_TDESC_STAT_COLCNT)) 2395 ifp->if_collisions++; 2396 if (txstat & RL_TDESC_STAT_TXERRSUM) 2397 ifp->if_oerrors++; 2398 else 2399 ifp->if_opackets++; 2400 } 2401 sc->rl_ldata.rl_tx_free++; 2402 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2403 } 2404 sc->rl_ldata.rl_tx_considx = cons; 2405 2406 /* No changes made to the TX ring, so no flush needed */ 2407 2408 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2409 #ifdef RE_TX_MODERATION 2410 /* 2411 * If not all descriptors have been reaped yet, reload 2412 * the timer so that we will eventually get another 2413 * interrupt that will cause us to re-enter this routine. 2414 * This is done in case the transmitter has gone idle. 2415 */ 2416 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2417 #endif 2418 } else 2419 sc->rl_watchdog_timer = 0; 2420 } 2421 2422 static void 2423 re_tick(void *xsc) 2424 { 2425 struct rl_softc *sc; 2426 struct mii_data *mii; 2427 2428 sc = xsc; 2429 2430 RL_LOCK_ASSERT(sc); 2431 2432 mii = device_get_softc(sc->rl_miibus); 2433 mii_tick(mii); 2434 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2435 re_miibus_statchg(sc->rl_dev); 2436 /* 2437 * Reclaim transmitted frames here. Technically it is not 2438 * necessary to do here but it ensures periodic reclamation 2439 * regardless of Tx completion interrupt which seems to be 2440 * lost on PCIe based controllers under certain situations. 2441 */ 2442 re_txeof(sc); 2443 re_watchdog(sc); 2444 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2445 } 2446 2447 #ifdef DEVICE_POLLING 2448 static int 2449 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2450 { 2451 struct rl_softc *sc = ifp->if_softc; 2452 int rx_npkts = 0; 2453 2454 RL_LOCK(sc); 2455 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2456 rx_npkts = re_poll_locked(ifp, cmd, count); 2457 RL_UNLOCK(sc); 2458 return (rx_npkts); 2459 } 2460 2461 static int 2462 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2463 { 2464 struct rl_softc *sc = ifp->if_softc; 2465 int rx_npkts; 2466 2467 RL_LOCK_ASSERT(sc); 2468 2469 sc->rxcycles = count; 2470 re_rxeof(sc, &rx_npkts); 2471 re_txeof(sc); 2472 2473 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2474 re_start_locked(ifp); 2475 2476 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2477 u_int16_t status; 2478 2479 status = CSR_READ_2(sc, RL_ISR); 2480 if (status == 0xffff) 2481 return (rx_npkts); 2482 if (status) 2483 CSR_WRITE_2(sc, RL_ISR, status); 2484 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2485 (sc->rl_flags & RL_FLAG_PCIE)) 2486 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2487 2488 /* 2489 * XXX check behaviour on receiver stalls. 2490 */ 2491 2492 if (status & RL_ISR_SYSTEM_ERR) { 2493 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2494 re_init_locked(sc); 2495 } 2496 } 2497 return (rx_npkts); 2498 } 2499 #endif /* DEVICE_POLLING */ 2500 2501 static int 2502 re_intr(void *arg) 2503 { 2504 struct rl_softc *sc; 2505 uint16_t status; 2506 2507 sc = arg; 2508 2509 status = CSR_READ_2(sc, RL_ISR); 2510 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2511 return (FILTER_STRAY); 2512 CSR_WRITE_2(sc, RL_IMR, 0); 2513 2514 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2515 2516 return (FILTER_HANDLED); 2517 } 2518 2519 static void 2520 re_int_task(void *arg, int npending) 2521 { 2522 struct rl_softc *sc; 2523 struct ifnet *ifp; 2524 u_int16_t status; 2525 int rval = 0; 2526 2527 sc = arg; 2528 ifp = sc->rl_ifp; 2529 2530 RL_LOCK(sc); 2531 2532 status = CSR_READ_2(sc, RL_ISR); 2533 CSR_WRITE_2(sc, RL_ISR, status); 2534 2535 if (sc->suspended || 2536 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2537 RL_UNLOCK(sc); 2538 return; 2539 } 2540 2541 #ifdef DEVICE_POLLING 2542 if (ifp->if_capenable & IFCAP_POLLING) { 2543 RL_UNLOCK(sc); 2544 return; 2545 } 2546 #endif 2547 2548 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2549 rval = re_rxeof(sc, NULL); 2550 2551 /* 2552 * Some chips will ignore a second TX request issued 2553 * while an existing transmission is in progress. If 2554 * the transmitter goes idle but there are still 2555 * packets waiting to be sent, we need to restart the 2556 * channel here to flush them out. This only seems to 2557 * be required with the PCIe devices. 2558 */ 2559 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2560 (sc->rl_flags & RL_FLAG_PCIE)) 2561 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2562 if (status & ( 2563 #ifdef RE_TX_MODERATION 2564 RL_ISR_TIMEOUT_EXPIRED| 2565 #else 2566 RL_ISR_TX_OK| 2567 #endif 2568 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2569 re_txeof(sc); 2570 2571 if (status & RL_ISR_SYSTEM_ERR) { 2572 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2573 re_init_locked(sc); 2574 } 2575 2576 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2577 re_start_locked(ifp); 2578 2579 RL_UNLOCK(sc); 2580 2581 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2582 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2583 return; 2584 } 2585 2586 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2587 } 2588 2589 static void 2590 re_intr_msi(void *xsc) 2591 { 2592 struct rl_softc *sc; 2593 struct ifnet *ifp; 2594 uint16_t intrs, status; 2595 2596 sc = xsc; 2597 RL_LOCK(sc); 2598 2599 ifp = sc->rl_ifp; 2600 #ifdef DEVICE_POLLING 2601 if (ifp->if_capenable & IFCAP_POLLING) { 2602 RL_UNLOCK(sc); 2603 return; 2604 } 2605 #endif 2606 /* Disable interrupts. */ 2607 CSR_WRITE_2(sc, RL_IMR, 0); 2608 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2609 RL_UNLOCK(sc); 2610 return; 2611 } 2612 2613 intrs = RL_INTRS_CPLUS; 2614 status = CSR_READ_2(sc, RL_ISR); 2615 CSR_WRITE_2(sc, RL_ISR, status); 2616 if (sc->rl_int_rx_act > 0) { 2617 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2618 RL_ISR_RX_OVERRUN); 2619 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2620 RL_ISR_RX_OVERRUN); 2621 } 2622 2623 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR | 2624 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) { 2625 re_rxeof(sc, NULL); 2626 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2627 if (sc->rl_int_rx_mod != 0 && 2628 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR | 2629 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) { 2630 /* Rearm one-shot timer. */ 2631 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2632 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | 2633 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN); 2634 sc->rl_int_rx_act = 1; 2635 } else { 2636 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR | 2637 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN; 2638 sc->rl_int_rx_act = 0; 2639 } 2640 } 2641 } 2642 2643 /* 2644 * Some chips will ignore a second TX request issued 2645 * while an existing transmission is in progress. If 2646 * the transmitter goes idle but there are still 2647 * packets waiting to be sent, we need to restart the 2648 * channel here to flush them out. This only seems to 2649 * be required with the PCIe devices. 2650 */ 2651 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2652 (sc->rl_flags & RL_FLAG_PCIE)) 2653 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2654 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL)) 2655 re_txeof(sc); 2656 2657 if (status & RL_ISR_SYSTEM_ERR) { 2658 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2659 re_init_locked(sc); 2660 } 2661 2662 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2663 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2664 re_start_locked(ifp); 2665 CSR_WRITE_2(sc, RL_IMR, intrs); 2666 } 2667 RL_UNLOCK(sc); 2668 } 2669 2670 static int 2671 re_encap(struct rl_softc *sc, struct mbuf **m_head) 2672 { 2673 struct rl_txdesc *txd, *txd_last; 2674 bus_dma_segment_t segs[RL_NTXSEGS]; 2675 bus_dmamap_t map; 2676 struct mbuf *m_new; 2677 struct rl_desc *desc; 2678 int nsegs, prod; 2679 int i, error, ei, si; 2680 int padlen; 2681 uint32_t cmdstat, csum_flags, vlanctl; 2682 2683 RL_LOCK_ASSERT(sc); 2684 M_ASSERTPKTHDR((*m_head)); 2685 2686 /* 2687 * With some of the RealTek chips, using the checksum offload 2688 * support in conjunction with the autopadding feature results 2689 * in the transmission of corrupt frames. For example, if we 2690 * need to send a really small IP fragment that's less than 60 2691 * bytes in size, and IP header checksumming is enabled, the 2692 * resulting ethernet frame that appears on the wire will 2693 * have garbled payload. To work around this, if TX IP checksum 2694 * offload is enabled, we always manually pad short frames out 2695 * to the minimum ethernet frame size. 2696 */ 2697 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 2698 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2699 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2700 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2701 if (M_WRITABLE(*m_head) == 0) { 2702 /* Get a writable copy. */ 2703 m_new = m_dup(*m_head, M_DONTWAIT); 2704 m_freem(*m_head); 2705 if (m_new == NULL) { 2706 *m_head = NULL; 2707 return (ENOBUFS); 2708 } 2709 *m_head = m_new; 2710 } 2711 if ((*m_head)->m_next != NULL || 2712 M_TRAILINGSPACE(*m_head) < padlen) { 2713 m_new = m_defrag(*m_head, M_DONTWAIT); 2714 if (m_new == NULL) { 2715 m_freem(*m_head); 2716 *m_head = NULL; 2717 return (ENOBUFS); 2718 } 2719 } else 2720 m_new = *m_head; 2721 2722 /* 2723 * Manually pad short frames, and zero the pad space 2724 * to avoid leaking data. 2725 */ 2726 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2727 m_new->m_pkthdr.len += padlen; 2728 m_new->m_len = m_new->m_pkthdr.len; 2729 *m_head = m_new; 2730 } 2731 2732 prod = sc->rl_ldata.rl_tx_prodidx; 2733 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2734 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2735 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2736 if (error == EFBIG) { 2737 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2738 if (m_new == NULL) { 2739 m_freem(*m_head); 2740 *m_head = NULL; 2741 return (ENOBUFS); 2742 } 2743 *m_head = m_new; 2744 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2745 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2746 if (error != 0) { 2747 m_freem(*m_head); 2748 *m_head = NULL; 2749 return (error); 2750 } 2751 } else if (error != 0) 2752 return (error); 2753 if (nsegs == 0) { 2754 m_freem(*m_head); 2755 *m_head = NULL; 2756 return (EIO); 2757 } 2758 2759 /* Check for number of available descriptors. */ 2760 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2761 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2762 return (ENOBUFS); 2763 } 2764 2765 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2766 BUS_DMASYNC_PREWRITE); 2767 2768 /* 2769 * Set up checksum offload. Note: checksum offload bits must 2770 * appear in all descriptors of a multi-descriptor transmit 2771 * attempt. This is according to testing done with an 8169 2772 * chip. This is a requirement. 2773 */ 2774 vlanctl = 0; 2775 csum_flags = 0; 2776 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2777 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) { 2778 csum_flags |= RL_TDESC_CMD_LGSEND; 2779 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2780 RL_TDESC_CMD_MSSVALV2_SHIFT); 2781 } else { 2782 csum_flags |= RL_TDESC_CMD_LGSEND | 2783 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2784 RL_TDESC_CMD_MSSVAL_SHIFT); 2785 } 2786 } else { 2787 /* 2788 * Unconditionally enable IP checksum if TCP or UDP 2789 * checksum is required. Otherwise, TCP/UDP checksum 2790 * does't make effects. 2791 */ 2792 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2793 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2794 csum_flags |= RL_TDESC_CMD_IPCSUM; 2795 if (((*m_head)->m_pkthdr.csum_flags & 2796 CSUM_TCP) != 0) 2797 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2798 if (((*m_head)->m_pkthdr.csum_flags & 2799 CSUM_UDP) != 0) 2800 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2801 } else { 2802 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2803 if (((*m_head)->m_pkthdr.csum_flags & 2804 CSUM_TCP) != 0) 2805 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2806 if (((*m_head)->m_pkthdr.csum_flags & 2807 CSUM_UDP) != 0) 2808 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2809 } 2810 } 2811 } 2812 2813 /* 2814 * Set up hardware VLAN tagging. Note: vlan tag info must 2815 * appear in all descriptors of a multi-descriptor 2816 * transmission attempt. 2817 */ 2818 if ((*m_head)->m_flags & M_VLANTAG) 2819 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2820 RL_TDESC_VLANCTL_TAG; 2821 2822 si = prod; 2823 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2824 desc = &sc->rl_ldata.rl_tx_list[prod]; 2825 desc->rl_vlanctl = htole32(vlanctl); 2826 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2827 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2828 cmdstat = segs[i].ds_len; 2829 if (i != 0) 2830 cmdstat |= RL_TDESC_CMD_OWN; 2831 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2832 cmdstat |= RL_TDESC_CMD_EOR; 2833 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2834 sc->rl_ldata.rl_tx_free--; 2835 } 2836 /* Update producer index. */ 2837 sc->rl_ldata.rl_tx_prodidx = prod; 2838 2839 /* Set EOF on the last descriptor. */ 2840 ei = RL_TX_DESC_PRV(sc, prod); 2841 desc = &sc->rl_ldata.rl_tx_list[ei]; 2842 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2843 2844 desc = &sc->rl_ldata.rl_tx_list[si]; 2845 /* Set SOF and transfer ownership of packet to the chip. */ 2846 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2847 2848 /* 2849 * Insure that the map for this transmission 2850 * is placed at the array index of the last descriptor 2851 * in this chain. (Swap last and first dmamaps.) 2852 */ 2853 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2854 map = txd->tx_dmamap; 2855 txd->tx_dmamap = txd_last->tx_dmamap; 2856 txd_last->tx_dmamap = map; 2857 txd_last->tx_m = *m_head; 2858 2859 return (0); 2860 } 2861 2862 static void 2863 re_start(struct ifnet *ifp) 2864 { 2865 struct rl_softc *sc; 2866 2867 sc = ifp->if_softc; 2868 RL_LOCK(sc); 2869 re_start_locked(ifp); 2870 RL_UNLOCK(sc); 2871 } 2872 2873 /* 2874 * Main transmit routine for C+ and gigE NICs. 2875 */ 2876 static void 2877 re_start_locked(struct ifnet *ifp) 2878 { 2879 struct rl_softc *sc; 2880 struct mbuf *m_head; 2881 int queued; 2882 2883 sc = ifp->if_softc; 2884 2885 #ifdef DEV_NETMAP 2886 /* XXX is this necessary ? */ 2887 if (ifp->if_capenable & IFCAP_NETMAP) { 2888 struct netmap_kring *kring = &NA(ifp)->tx_rings[0]; 2889 if (sc->rl_ldata.rl_tx_prodidx != kring->nr_hwcur) { 2890 /* kick the tx unit */ 2891 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2892 #ifdef RE_TX_MODERATION 2893 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2894 #endif 2895 sc->rl_watchdog_timer = 5; 2896 } 2897 return; 2898 } 2899 #endif /* DEV_NETMAP */ 2900 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2901 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 2902 return; 2903 2904 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2905 sc->rl_ldata.rl_tx_free > 1;) { 2906 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2907 if (m_head == NULL) 2908 break; 2909 2910 if (re_encap(sc, &m_head) != 0) { 2911 if (m_head == NULL) 2912 break; 2913 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2914 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2915 break; 2916 } 2917 2918 /* 2919 * If there's a BPF listener, bounce a copy of this frame 2920 * to him. 2921 */ 2922 ETHER_BPF_MTAP(ifp, m_head); 2923 2924 queued++; 2925 } 2926 2927 if (queued == 0) { 2928 #ifdef RE_TX_MODERATION 2929 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2930 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2931 #endif 2932 return; 2933 } 2934 2935 /* Flush the TX descriptors */ 2936 2937 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2938 sc->rl_ldata.rl_tx_list_map, 2939 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2940 2941 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2942 2943 #ifdef RE_TX_MODERATION 2944 /* 2945 * Use the countdown timer for interrupt moderation. 2946 * 'TX done' interrupts are disabled. Instead, we reset the 2947 * countdown timer, which will begin counting until it hits 2948 * the value in the TIMERINT register, and then trigger an 2949 * interrupt. Each time we write to the TIMERCNT register, 2950 * the timer count is reset to 0. 2951 */ 2952 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2953 #endif 2954 2955 /* 2956 * Set a timeout in case the chip goes out to lunch. 2957 */ 2958 sc->rl_watchdog_timer = 5; 2959 } 2960 2961 static void 2962 re_set_jumbo(struct rl_softc *sc, int jumbo) 2963 { 2964 2965 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) { 2966 pci_set_max_read_req(sc->rl_dev, 4096); 2967 return; 2968 } 2969 2970 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2971 if (jumbo != 0) { 2972 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) | 2973 RL_CFG3_JUMBO_EN0); 2974 switch (sc->rl_hwrev->rl_rev) { 2975 case RL_HWREV_8168DP: 2976 break; 2977 case RL_HWREV_8168E: 2978 CSR_WRITE_1(sc, sc->rl_cfg4, 2979 CSR_READ_1(sc, sc->rl_cfg4) | 0x01); 2980 break; 2981 default: 2982 CSR_WRITE_1(sc, sc->rl_cfg4, 2983 CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1); 2984 } 2985 } else { 2986 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) & 2987 ~RL_CFG3_JUMBO_EN0); 2988 switch (sc->rl_hwrev->rl_rev) { 2989 case RL_HWREV_8168DP: 2990 break; 2991 case RL_HWREV_8168E: 2992 CSR_WRITE_1(sc, sc->rl_cfg4, 2993 CSR_READ_1(sc, sc->rl_cfg4) & ~0x01); 2994 break; 2995 default: 2996 CSR_WRITE_1(sc, sc->rl_cfg4, 2997 CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1); 2998 } 2999 } 3000 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3001 3002 switch (sc->rl_hwrev->rl_rev) { 3003 case RL_HWREV_8168DP: 3004 pci_set_max_read_req(sc->rl_dev, 4096); 3005 break; 3006 default: 3007 if (jumbo != 0) 3008 pci_set_max_read_req(sc->rl_dev, 512); 3009 else 3010 pci_set_max_read_req(sc->rl_dev, 4096); 3011 } 3012 } 3013 3014 static void 3015 re_init(void *xsc) 3016 { 3017 struct rl_softc *sc = xsc; 3018 3019 RL_LOCK(sc); 3020 re_init_locked(sc); 3021 RL_UNLOCK(sc); 3022 } 3023 3024 static void 3025 re_init_locked(struct rl_softc *sc) 3026 { 3027 struct ifnet *ifp = sc->rl_ifp; 3028 struct mii_data *mii; 3029 uint32_t reg; 3030 uint16_t cfg; 3031 union { 3032 uint32_t align_dummy; 3033 u_char eaddr[ETHER_ADDR_LEN]; 3034 } eaddr; 3035 3036 RL_LOCK_ASSERT(sc); 3037 3038 mii = device_get_softc(sc->rl_miibus); 3039 3040 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3041 return; 3042 3043 /* 3044 * Cancel pending I/O and free all RX/TX buffers. 3045 */ 3046 re_stop(sc); 3047 3048 /* Put controller into known state. */ 3049 re_reset(sc); 3050 3051 /* 3052 * For C+ mode, initialize the RX descriptors and mbufs. 3053 */ 3054 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3055 if (ifp->if_mtu > RL_MTU) { 3056 if (re_jrx_list_init(sc) != 0) { 3057 device_printf(sc->rl_dev, 3058 "no memory for jumbo RX buffers\n"); 3059 re_stop(sc); 3060 return; 3061 } 3062 /* Disable checksum offloading for jumbo frames. */ 3063 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4); 3064 ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO); 3065 } else { 3066 if (re_rx_list_init(sc) != 0) { 3067 device_printf(sc->rl_dev, 3068 "no memory for RX buffers\n"); 3069 re_stop(sc); 3070 return; 3071 } 3072 } 3073 re_set_jumbo(sc, ifp->if_mtu > RL_MTU); 3074 } else { 3075 if (re_rx_list_init(sc) != 0) { 3076 device_printf(sc->rl_dev, "no memory for RX buffers\n"); 3077 re_stop(sc); 3078 return; 3079 } 3080 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3081 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) { 3082 if (ifp->if_mtu > RL_MTU) 3083 pci_set_max_read_req(sc->rl_dev, 512); 3084 else 3085 pci_set_max_read_req(sc->rl_dev, 4096); 3086 } 3087 } 3088 re_tx_list_init(sc); 3089 3090 /* 3091 * Enable C+ RX and TX mode, as well as VLAN stripping and 3092 * RX checksum offload. We must configure the C+ register 3093 * before all others. 3094 */ 3095 cfg = RL_CPLUSCMD_PCI_MRW; 3096 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3097 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 3098 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3099 cfg |= RL_CPLUSCMD_VLANSTRIP; 3100 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 3101 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 3102 /* XXX magic. */ 3103 cfg |= 0x0001; 3104 } else 3105 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 3106 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 3107 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC || 3108 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) { 3109 reg = 0x000fff00; 3110 if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0) 3111 reg |= 0x000000ff; 3112 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) 3113 reg |= 0x00f00000; 3114 CSR_WRITE_4(sc, 0x7c, reg); 3115 /* Disable interrupt mitigation. */ 3116 CSR_WRITE_2(sc, 0xe2, 0); 3117 } 3118 /* 3119 * Disable TSO if interface MTU size is greater than MSS 3120 * allowed in controller. 3121 */ 3122 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 3123 ifp->if_capenable &= ~IFCAP_TSO4; 3124 ifp->if_hwassist &= ~CSUM_TSO; 3125 } 3126 3127 /* 3128 * Init our MAC address. Even though the chipset 3129 * documentation doesn't mention it, we need to enter "Config 3130 * register write enable" mode to modify the ID registers. 3131 */ 3132 /* Copy MAC address on stack to align. */ 3133 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 3134 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3135 CSR_WRITE_4(sc, RL_IDR0, 3136 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 3137 CSR_WRITE_4(sc, RL_IDR4, 3138 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 3139 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3140 3141 /* 3142 * Load the addresses of the RX and TX lists into the chip. 3143 */ 3144 3145 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 3146 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 3147 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 3148 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 3149 3150 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 3151 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 3152 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 3153 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 3154 3155 /* 3156 * Enable transmit and receive. 3157 */ 3158 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 3159 3160 /* 3161 * Set the initial TX configuration. 3162 */ 3163 if (sc->rl_testmode) { 3164 if (sc->rl_type == RL_8169) 3165 CSR_WRITE_4(sc, RL_TXCFG, 3166 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 3167 else 3168 CSR_WRITE_4(sc, RL_TXCFG, 3169 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 3170 } else 3171 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 3172 3173 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 3174 3175 /* 3176 * Set the initial RX configuration. 3177 */ 3178 re_set_rxmode(sc); 3179 3180 /* Configure interrupt moderation. */ 3181 if (sc->rl_type == RL_8169) { 3182 /* Magic from vendor. */ 3183 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100); 3184 } 3185 3186 #ifdef DEVICE_POLLING 3187 /* 3188 * Disable interrupts if we are polling. 3189 */ 3190 if (ifp->if_capenable & IFCAP_POLLING) 3191 CSR_WRITE_2(sc, RL_IMR, 0); 3192 else /* otherwise ... */ 3193 #endif 3194 3195 /* 3196 * Enable interrupts. 3197 */ 3198 if (sc->rl_testmode) 3199 CSR_WRITE_2(sc, RL_IMR, 0); 3200 else 3201 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3202 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 3203 3204 /* Set initial TX threshold */ 3205 sc->rl_txthresh = RL_TX_THRESH_INIT; 3206 3207 /* Start RX/TX process. */ 3208 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 3209 #ifdef notdef 3210 /* Enable receiver and transmitter. */ 3211 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 3212 #endif 3213 3214 /* 3215 * Initialize the timer interrupt register so that 3216 * a timer interrupt will be generated once the timer 3217 * reaches a certain number of ticks. The timer is 3218 * reloaded on each transmit. 3219 */ 3220 #ifdef RE_TX_MODERATION 3221 /* 3222 * Use timer interrupt register to moderate TX interrupt 3223 * moderation, which dramatically improves TX frame rate. 3224 */ 3225 if (sc->rl_type == RL_8169) 3226 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 3227 else 3228 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 3229 #else 3230 /* 3231 * Use timer interrupt register to moderate RX interrupt 3232 * moderation. 3233 */ 3234 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 3235 intr_filter == 0) { 3236 if (sc->rl_type == RL_8169) 3237 CSR_WRITE_4(sc, RL_TIMERINT_8169, 3238 RL_USECS(sc->rl_int_rx_mod)); 3239 } else { 3240 if (sc->rl_type == RL_8169) 3241 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0)); 3242 } 3243 #endif 3244 3245 /* 3246 * For 8169 gigE NICs, set the max allowed RX packet 3247 * size so we can receive jumbo frames. 3248 */ 3249 if (sc->rl_type == RL_8169) { 3250 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3251 /* 3252 * For controllers that use new jumbo frame scheme, 3253 * set maximum size of jumbo frame depedning on 3254 * controller revisions. 3255 */ 3256 if (ifp->if_mtu > RL_MTU) 3257 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3258 sc->rl_hwrev->rl_max_mtu + 3259 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN + 3260 ETHER_CRC_LEN); 3261 else 3262 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3263 RE_RX_DESC_BUFLEN); 3264 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3265 sc->rl_hwrev->rl_max_mtu == RL_MTU) { 3266 /* RTL810x has no jumbo frame support. */ 3267 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN); 3268 } else 3269 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 3270 } 3271 3272 if (sc->rl_testmode) 3273 return; 3274 3275 CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) | 3276 RL_CFG1_DRVLOAD); 3277 3278 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3279 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3280 3281 sc->rl_flags &= ~RL_FLAG_LINK; 3282 mii_mediachg(mii); 3283 3284 sc->rl_watchdog_timer = 0; 3285 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 3286 } 3287 3288 /* 3289 * Set media options. 3290 */ 3291 static int 3292 re_ifmedia_upd(struct ifnet *ifp) 3293 { 3294 struct rl_softc *sc; 3295 struct mii_data *mii; 3296 int error; 3297 3298 sc = ifp->if_softc; 3299 mii = device_get_softc(sc->rl_miibus); 3300 RL_LOCK(sc); 3301 error = mii_mediachg(mii); 3302 RL_UNLOCK(sc); 3303 3304 return (error); 3305 } 3306 3307 /* 3308 * Report current media status. 3309 */ 3310 static void 3311 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3312 { 3313 struct rl_softc *sc; 3314 struct mii_data *mii; 3315 3316 sc = ifp->if_softc; 3317 mii = device_get_softc(sc->rl_miibus); 3318 3319 RL_LOCK(sc); 3320 mii_pollstat(mii); 3321 ifmr->ifm_active = mii->mii_media_active; 3322 ifmr->ifm_status = mii->mii_media_status; 3323 RL_UNLOCK(sc); 3324 } 3325 3326 static int 3327 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3328 { 3329 struct rl_softc *sc = ifp->if_softc; 3330 struct ifreq *ifr = (struct ifreq *) data; 3331 struct mii_data *mii; 3332 uint32_t rev; 3333 int error = 0; 3334 3335 switch (command) { 3336 case SIOCSIFMTU: 3337 if (ifr->ifr_mtu < ETHERMIN || 3338 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu) { 3339 error = EINVAL; 3340 break; 3341 } 3342 RL_LOCK(sc); 3343 if (ifp->if_mtu != ifr->ifr_mtu) { 3344 ifp->if_mtu = ifr->ifr_mtu; 3345 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3346 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3347 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3348 re_init_locked(sc); 3349 } 3350 if (ifp->if_mtu > RL_TSO_MTU && 3351 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3352 ifp->if_capenable &= ~(IFCAP_TSO4 | 3353 IFCAP_VLAN_HWTSO); 3354 ifp->if_hwassist &= ~CSUM_TSO; 3355 } 3356 VLAN_CAPABILITIES(ifp); 3357 } 3358 RL_UNLOCK(sc); 3359 break; 3360 case SIOCSIFFLAGS: 3361 RL_LOCK(sc); 3362 if ((ifp->if_flags & IFF_UP) != 0) { 3363 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3364 if (((ifp->if_flags ^ sc->rl_if_flags) 3365 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3366 re_set_rxmode(sc); 3367 } else 3368 re_init_locked(sc); 3369 } else { 3370 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3371 re_stop(sc); 3372 } 3373 sc->rl_if_flags = ifp->if_flags; 3374 RL_UNLOCK(sc); 3375 break; 3376 case SIOCADDMULTI: 3377 case SIOCDELMULTI: 3378 RL_LOCK(sc); 3379 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3380 re_set_rxmode(sc); 3381 RL_UNLOCK(sc); 3382 break; 3383 case SIOCGIFMEDIA: 3384 case SIOCSIFMEDIA: 3385 mii = device_get_softc(sc->rl_miibus); 3386 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3387 break; 3388 case SIOCSIFCAP: 3389 { 3390 int mask, reinit; 3391 3392 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3393 reinit = 0; 3394 #ifdef DEVICE_POLLING 3395 if (mask & IFCAP_POLLING) { 3396 if (ifr->ifr_reqcap & IFCAP_POLLING) { 3397 error = ether_poll_register(re_poll, ifp); 3398 if (error) 3399 return (error); 3400 RL_LOCK(sc); 3401 /* Disable interrupts */ 3402 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3403 ifp->if_capenable |= IFCAP_POLLING; 3404 RL_UNLOCK(sc); 3405 } else { 3406 error = ether_poll_deregister(ifp); 3407 /* Enable interrupts. */ 3408 RL_LOCK(sc); 3409 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3410 ifp->if_capenable &= ~IFCAP_POLLING; 3411 RL_UNLOCK(sc); 3412 } 3413 } 3414 #endif /* DEVICE_POLLING */ 3415 RL_LOCK(sc); 3416 if ((mask & IFCAP_TXCSUM) != 0 && 3417 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3418 ifp->if_capenable ^= IFCAP_TXCSUM; 3419 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) { 3420 rev = sc->rl_hwrev->rl_rev; 3421 if (rev == RL_HWREV_8168C || 3422 rev == RL_HWREV_8168C_SPIN2) 3423 ifp->if_hwassist |= CSUM_TCP | CSUM_UDP; 3424 else 3425 ifp->if_hwassist |= RE_CSUM_FEATURES; 3426 } else 3427 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 3428 reinit = 1; 3429 } 3430 if ((mask & IFCAP_RXCSUM) != 0 && 3431 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 3432 ifp->if_capenable ^= IFCAP_RXCSUM; 3433 reinit = 1; 3434 } 3435 if ((mask & IFCAP_TSO4) != 0 && 3436 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 3437 ifp->if_capenable ^= IFCAP_TSO4; 3438 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 3439 ifp->if_hwassist |= CSUM_TSO; 3440 else 3441 ifp->if_hwassist &= ~CSUM_TSO; 3442 if (ifp->if_mtu > RL_TSO_MTU && 3443 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3444 ifp->if_capenable &= ~IFCAP_TSO4; 3445 ifp->if_hwassist &= ~CSUM_TSO; 3446 } 3447 } 3448 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3449 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 3450 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3451 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3452 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 3453 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3454 /* TSO over VLAN requires VLAN hardware tagging. */ 3455 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 3456 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 3457 reinit = 1; 3458 } 3459 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3460 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 | 3461 IFCAP_VLAN_HWTSO)) != 0) 3462 reinit = 1; 3463 if ((mask & IFCAP_WOL) != 0 && 3464 (ifp->if_capabilities & IFCAP_WOL) != 0) { 3465 if ((mask & IFCAP_WOL_UCAST) != 0) 3466 ifp->if_capenable ^= IFCAP_WOL_UCAST; 3467 if ((mask & IFCAP_WOL_MCAST) != 0) 3468 ifp->if_capenable ^= IFCAP_WOL_MCAST; 3469 if ((mask & IFCAP_WOL_MAGIC) != 0) 3470 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3471 } 3472 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) { 3473 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3474 re_init_locked(sc); 3475 } 3476 RL_UNLOCK(sc); 3477 VLAN_CAPABILITIES(ifp); 3478 } 3479 break; 3480 default: 3481 error = ether_ioctl(ifp, command, data); 3482 break; 3483 } 3484 3485 return (error); 3486 } 3487 3488 static void 3489 re_watchdog(struct rl_softc *sc) 3490 { 3491 struct ifnet *ifp; 3492 3493 RL_LOCK_ASSERT(sc); 3494 3495 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 3496 return; 3497 3498 ifp = sc->rl_ifp; 3499 re_txeof(sc); 3500 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 3501 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 3502 "-- recovering\n"); 3503 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3504 re_start_locked(ifp); 3505 return; 3506 } 3507 3508 if_printf(ifp, "watchdog timeout\n"); 3509 ifp->if_oerrors++; 3510 3511 re_rxeof(sc, NULL); 3512 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3513 re_init_locked(sc); 3514 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3515 re_start_locked(ifp); 3516 } 3517 3518 /* 3519 * Stop the adapter and free any mbufs allocated to the 3520 * RX and TX lists. 3521 */ 3522 static void 3523 re_stop(struct rl_softc *sc) 3524 { 3525 int i; 3526 struct ifnet *ifp; 3527 struct rl_txdesc *txd; 3528 struct rl_rxdesc *rxd; 3529 3530 RL_LOCK_ASSERT(sc); 3531 3532 ifp = sc->rl_ifp; 3533 3534 sc->rl_watchdog_timer = 0; 3535 callout_stop(&sc->rl_stat_callout); 3536 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3537 3538 /* 3539 * Disable accepting frames to put RX MAC into idle state. 3540 * Otherwise it's possible to get frames while stop command 3541 * execution is in progress and controller can DMA the frame 3542 * to already freed RX buffer during that period. 3543 */ 3544 CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) & 3545 ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI | 3546 RL_RXCFG_RX_BROAD)); 3547 3548 if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) { 3549 for (i = RL_TIMEOUT; i > 0; i--) { 3550 if ((CSR_READ_1(sc, sc->rl_txstart) & 3551 RL_TXSTART_START) == 0) 3552 break; 3553 DELAY(20); 3554 } 3555 if (i == 0) 3556 device_printf(sc->rl_dev, 3557 "stopping TX poll timed out!\n"); 3558 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3559 } else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) { 3560 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 3561 RL_CMD_RX_ENB); 3562 if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) { 3563 for (i = RL_TIMEOUT; i > 0; i--) { 3564 if ((CSR_READ_4(sc, RL_TXCFG) & 3565 RL_TXCFG_QUEUE_EMPTY) != 0) 3566 break; 3567 DELAY(100); 3568 } 3569 if (i == 0) 3570 device_printf(sc->rl_dev, 3571 "stopping TXQ timed out!\n"); 3572 } 3573 } else 3574 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3575 DELAY(1000); 3576 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3577 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 3578 3579 if (sc->rl_head != NULL) { 3580 m_freem(sc->rl_head); 3581 sc->rl_head = sc->rl_tail = NULL; 3582 } 3583 3584 /* Free the TX list buffers. */ 3585 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 3586 txd = &sc->rl_ldata.rl_tx_desc[i]; 3587 if (txd->tx_m != NULL) { 3588 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3589 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3590 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 3591 txd->tx_dmamap); 3592 m_freem(txd->tx_m); 3593 txd->tx_m = NULL; 3594 } 3595 } 3596 3597 /* Free the RX list buffers. */ 3598 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3599 rxd = &sc->rl_ldata.rl_rx_desc[i]; 3600 if (rxd->rx_m != NULL) { 3601 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 3602 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3603 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 3604 rxd->rx_dmamap); 3605 m_freem(rxd->rx_m); 3606 rxd->rx_m = NULL; 3607 } 3608 } 3609 3610 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3611 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3612 rxd = &sc->rl_ldata.rl_jrx_desc[i]; 3613 if (rxd->rx_m != NULL) { 3614 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, 3615 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3616 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, 3617 rxd->rx_dmamap); 3618 m_freem(rxd->rx_m); 3619 rxd->rx_m = NULL; 3620 } 3621 } 3622 } 3623 } 3624 3625 /* 3626 * Device suspend routine. Stop the interface and save some PCI 3627 * settings in case the BIOS doesn't restore them properly on 3628 * resume. 3629 */ 3630 static int 3631 re_suspend(device_t dev) 3632 { 3633 struct rl_softc *sc; 3634 3635 sc = device_get_softc(dev); 3636 3637 RL_LOCK(sc); 3638 re_stop(sc); 3639 re_setwol(sc); 3640 sc->suspended = 1; 3641 RL_UNLOCK(sc); 3642 3643 return (0); 3644 } 3645 3646 /* 3647 * Device resume routine. Restore some PCI settings in case the BIOS 3648 * doesn't, re-enable busmastering, and restart the interface if 3649 * appropriate. 3650 */ 3651 static int 3652 re_resume(device_t dev) 3653 { 3654 struct rl_softc *sc; 3655 struct ifnet *ifp; 3656 3657 sc = device_get_softc(dev); 3658 3659 RL_LOCK(sc); 3660 3661 ifp = sc->rl_ifp; 3662 /* Take controller out of sleep mode. */ 3663 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3664 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3665 CSR_WRITE_1(sc, RL_GPIO, 3666 CSR_READ_1(sc, RL_GPIO) | 0x01); 3667 } 3668 3669 /* 3670 * Clear WOL matching such that normal Rx filtering 3671 * wouldn't interfere with WOL patterns. 3672 */ 3673 re_clrwol(sc); 3674 3675 /* reinitialize interface if necessary */ 3676 if (ifp->if_flags & IFF_UP) 3677 re_init_locked(sc); 3678 3679 sc->suspended = 0; 3680 RL_UNLOCK(sc); 3681 3682 return (0); 3683 } 3684 3685 /* 3686 * Stop all chip I/O so that the kernel's probe routines don't 3687 * get confused by errant DMAs when rebooting. 3688 */ 3689 static int 3690 re_shutdown(device_t dev) 3691 { 3692 struct rl_softc *sc; 3693 3694 sc = device_get_softc(dev); 3695 3696 RL_LOCK(sc); 3697 re_stop(sc); 3698 /* 3699 * Mark interface as down since otherwise we will panic if 3700 * interrupt comes in later on, which can happen in some 3701 * cases. 3702 */ 3703 sc->rl_ifp->if_flags &= ~IFF_UP; 3704 re_setwol(sc); 3705 RL_UNLOCK(sc); 3706 3707 return (0); 3708 } 3709 3710 static void 3711 re_set_linkspeed(struct rl_softc *sc) 3712 { 3713 struct mii_softc *miisc; 3714 struct mii_data *mii; 3715 int aneg, i, phyno; 3716 3717 RL_LOCK_ASSERT(sc); 3718 3719 mii = device_get_softc(sc->rl_miibus); 3720 mii_pollstat(mii); 3721 aneg = 0; 3722 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 3723 (IFM_ACTIVE | IFM_AVALID)) { 3724 switch IFM_SUBTYPE(mii->mii_media_active) { 3725 case IFM_10_T: 3726 case IFM_100_TX: 3727 return; 3728 case IFM_1000_T: 3729 aneg++; 3730 break; 3731 default: 3732 break; 3733 } 3734 } 3735 miisc = LIST_FIRST(&mii->mii_phys); 3736 phyno = miisc->mii_phy; 3737 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3738 PHY_RESET(miisc); 3739 re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0); 3740 re_miibus_writereg(sc->rl_dev, phyno, 3741 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 3742 re_miibus_writereg(sc->rl_dev, phyno, 3743 MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 3744 DELAY(1000); 3745 if (aneg != 0) { 3746 /* 3747 * Poll link state until re(4) get a 10/100Mbps link. 3748 */ 3749 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 3750 mii_pollstat(mii); 3751 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 3752 == (IFM_ACTIVE | IFM_AVALID)) { 3753 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3754 case IFM_10_T: 3755 case IFM_100_TX: 3756 return; 3757 default: 3758 break; 3759 } 3760 } 3761 RL_UNLOCK(sc); 3762 pause("relnk", hz); 3763 RL_LOCK(sc); 3764 } 3765 if (i == MII_ANEGTICKS_GIGE) 3766 device_printf(sc->rl_dev, 3767 "establishing a link failed, WOL may not work!"); 3768 } 3769 /* 3770 * No link, force MAC to have 100Mbps, full-duplex link. 3771 * MAC does not require reprogramming on resolved speed/duplex, 3772 * so this is just for completeness. 3773 */ 3774 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 3775 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 3776 } 3777 3778 static void 3779 re_setwol(struct rl_softc *sc) 3780 { 3781 struct ifnet *ifp; 3782 int pmc; 3783 uint16_t pmstat; 3784 uint8_t v; 3785 3786 RL_LOCK_ASSERT(sc); 3787 3788 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3789 return; 3790 3791 ifp = sc->rl_ifp; 3792 /* Put controller into sleep mode. */ 3793 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3794 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3795 CSR_WRITE_1(sc, RL_GPIO, 3796 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3797 } 3798 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 3799 re_set_rxmode(sc); 3800 if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0) 3801 re_set_linkspeed(sc); 3802 if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3803 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3804 } 3805 /* Enable config register write. */ 3806 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3807 3808 /* Enable PME. */ 3809 v = CSR_READ_1(sc, sc->rl_cfg1); 3810 v &= ~RL_CFG1_PME; 3811 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3812 v |= RL_CFG1_PME; 3813 CSR_WRITE_1(sc, sc->rl_cfg1, v); 3814 3815 v = CSR_READ_1(sc, sc->rl_cfg3); 3816 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3817 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3818 v |= RL_CFG3_WOL_MAGIC; 3819 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3820 3821 v = CSR_READ_1(sc, sc->rl_cfg5); 3822 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST | 3823 RL_CFG5_WOL_LANWAKE); 3824 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3825 v |= RL_CFG5_WOL_UCAST; 3826 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3827 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3828 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3829 v |= RL_CFG5_WOL_LANWAKE; 3830 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3831 3832 /* Config register write done. */ 3833 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3834 3835 if ((ifp->if_capenable & IFCAP_WOL) == 0 && 3836 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 3837 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80); 3838 /* 3839 * It seems that hardware resets its link speed to 100Mbps in 3840 * power down mode so switching to 100Mbps in driver is not 3841 * needed. 3842 */ 3843 3844 /* Request PME if WOL is requested. */ 3845 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3846 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3847 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3848 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3849 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3850 } 3851 3852 static void 3853 re_clrwol(struct rl_softc *sc) 3854 { 3855 int pmc; 3856 uint8_t v; 3857 3858 RL_LOCK_ASSERT(sc); 3859 3860 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3861 return; 3862 3863 /* Enable config register write. */ 3864 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3865 3866 v = CSR_READ_1(sc, sc->rl_cfg3); 3867 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3868 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3869 3870 /* Config register write done. */ 3871 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3872 3873 v = CSR_READ_1(sc, sc->rl_cfg5); 3874 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3875 v &= ~RL_CFG5_WOL_LANWAKE; 3876 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3877 } 3878 3879 static void 3880 re_add_sysctls(struct rl_softc *sc) 3881 { 3882 struct sysctl_ctx_list *ctx; 3883 struct sysctl_oid_list *children; 3884 int error; 3885 3886 ctx = device_get_sysctl_ctx(sc->rl_dev); 3887 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev)); 3888 3889 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats", 3890 CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I", 3891 "Statistics Information"); 3892 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 3893 return; 3894 3895 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod", 3896 CTLTYPE_INT | CTLFLAG_RW, &sc->rl_int_rx_mod, 0, 3897 sysctl_hw_re_int_mod, "I", "re RX interrupt moderation"); 3898 /* Pull in device tunables. */ 3899 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3900 error = resource_int_value(device_get_name(sc->rl_dev), 3901 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod); 3902 if (error == 0) { 3903 if (sc->rl_int_rx_mod < RL_TIMER_MIN || 3904 sc->rl_int_rx_mod > RL_TIMER_MAX) { 3905 device_printf(sc->rl_dev, "int_rx_mod value out of " 3906 "range; using default: %d\n", 3907 RL_TIMER_DEFAULT); 3908 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3909 } 3910 } 3911 3912 } 3913 3914 static int 3915 re_sysctl_stats(SYSCTL_HANDLER_ARGS) 3916 { 3917 struct rl_softc *sc; 3918 struct rl_stats *stats; 3919 int error, i, result; 3920 3921 result = -1; 3922 error = sysctl_handle_int(oidp, &result, 0, req); 3923 if (error || req->newptr == NULL) 3924 return (error); 3925 3926 if (result == 1) { 3927 sc = (struct rl_softc *)arg1; 3928 RL_LOCK(sc); 3929 if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3930 RL_UNLOCK(sc); 3931 goto done; 3932 } 3933 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3934 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD); 3935 CSR_WRITE_4(sc, RL_DUMPSTATS_HI, 3936 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr)); 3937 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3938 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr)); 3939 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3940 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr | 3941 RL_DUMPSTATS_START)); 3942 for (i = RL_TIMEOUT; i > 0; i--) { 3943 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) & 3944 RL_DUMPSTATS_START) == 0) 3945 break; 3946 DELAY(1000); 3947 } 3948 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3949 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD); 3950 RL_UNLOCK(sc); 3951 if (i == 0) { 3952 device_printf(sc->rl_dev, 3953 "DUMP statistics request timedout\n"); 3954 return (ETIMEDOUT); 3955 } 3956 done: 3957 stats = sc->rl_ldata.rl_stats; 3958 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev)); 3959 printf("Tx frames : %ju\n", 3960 (uintmax_t)le64toh(stats->rl_tx_pkts)); 3961 printf("Rx frames : %ju\n", 3962 (uintmax_t)le64toh(stats->rl_rx_pkts)); 3963 printf("Tx errors : %ju\n", 3964 (uintmax_t)le64toh(stats->rl_tx_errs)); 3965 printf("Rx errors : %u\n", 3966 le32toh(stats->rl_rx_errs)); 3967 printf("Rx missed frames : %u\n", 3968 (uint32_t)le16toh(stats->rl_missed_pkts)); 3969 printf("Rx frame alignment errs : %u\n", 3970 (uint32_t)le16toh(stats->rl_rx_framealign_errs)); 3971 printf("Tx single collisions : %u\n", 3972 le32toh(stats->rl_tx_onecoll)); 3973 printf("Tx multiple collisions : %u\n", 3974 le32toh(stats->rl_tx_multicolls)); 3975 printf("Rx unicast frames : %ju\n", 3976 (uintmax_t)le64toh(stats->rl_rx_ucasts)); 3977 printf("Rx broadcast frames : %ju\n", 3978 (uintmax_t)le64toh(stats->rl_rx_bcasts)); 3979 printf("Rx multicast frames : %u\n", 3980 le32toh(stats->rl_rx_mcasts)); 3981 printf("Tx aborts : %u\n", 3982 (uint32_t)le16toh(stats->rl_tx_aborts)); 3983 printf("Tx underruns : %u\n", 3984 (uint32_t)le16toh(stats->rl_rx_underruns)); 3985 } 3986 3987 return (error); 3988 } 3989 3990 static int 3991 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3992 { 3993 int error, value; 3994 3995 if (arg1 == NULL) 3996 return (EINVAL); 3997 value = *(int *)arg1; 3998 error = sysctl_handle_int(oidp, &value, 0, req); 3999 if (error || req->newptr == NULL) 4000 return (error); 4001 if (value < low || value > high) 4002 return (EINVAL); 4003 *(int *)arg1 = value; 4004 4005 return (0); 4006 } 4007 4008 static int 4009 sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS) 4010 { 4011 4012 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN, 4013 RL_TIMER_MAX)); 4014 } 4015