1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013-2016 Qlogic Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * File: ql_hw.c 32 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. 33 * Content: Contains Hardware dependent functions 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 #include "ql_os.h" 40 #include "ql_hw.h" 41 #include "ql_def.h" 42 #include "ql_inline.h" 43 #include "ql_ver.h" 44 #include "ql_glbl.h" 45 #include "ql_dbg.h" 46 #include "ql_minidump.h" 47 48 /* 49 * Static Functions 50 */ 51 52 static void qla_del_rcv_cntxt(qla_host_t *ha); 53 static int qla_init_rcv_cntxt(qla_host_t *ha); 54 static int qla_del_xmt_cntxt(qla_host_t *ha); 55 static int qla_init_xmt_cntxt(qla_host_t *ha); 56 static int qla_mbx_cmd(qla_host_t *ha, uint32_t *h_mbox, uint32_t n_hmbox, 57 uint32_t *fw_mbox, uint32_t n_fwmbox, uint32_t no_pause); 58 static int qla_config_intr_cntxt(qla_host_t *ha, uint32_t start_idx, 59 uint32_t num_intrs, uint32_t create); 60 static int qla_config_rss(qla_host_t *ha, uint16_t cntxt_id); 61 static int qla_config_intr_coalesce(qla_host_t *ha, uint16_t cntxt_id, 62 int tenable, int rcv); 63 static int qla_set_mac_rcv_mode(qla_host_t *ha, uint32_t mode); 64 static int qla_link_event_req(qla_host_t *ha, uint16_t cntxt_id); 65 66 static int qla_tx_tso(qla_host_t *ha, struct mbuf *mp, q80_tx_cmd_t *tx_cmd, 67 uint8_t *hdr); 68 static int qla_hw_add_all_mcast(qla_host_t *ha); 69 static int qla_add_rcv_rings(qla_host_t *ha, uint32_t sds_idx, uint32_t nsds); 70 71 static int qla_init_nic_func(qla_host_t *ha); 72 static int qla_stop_nic_func(qla_host_t *ha); 73 static int qla_query_fw_dcbx_caps(qla_host_t *ha); 74 static int qla_set_port_config(qla_host_t *ha, uint32_t cfg_bits); 75 static int qla_get_port_config(qla_host_t *ha, uint32_t *cfg_bits); 76 static int qla_set_cam_search_mode(qla_host_t *ha, uint32_t search_mode); 77 static int qla_get_cam_search_mode(qla_host_t *ha); 78 79 static void ql_minidump_free(qla_host_t *ha); 80 81 #ifdef QL_DBG 82 83 static void 84 qla_stop_pegs(qla_host_t *ha) 85 { 86 uint32_t val = 1; 87 88 ql_rdwr_indreg32(ha, Q8_CRB_PEG_0, &val, 0); 89 ql_rdwr_indreg32(ha, Q8_CRB_PEG_1, &val, 0); 90 ql_rdwr_indreg32(ha, Q8_CRB_PEG_2, &val, 0); 91 ql_rdwr_indreg32(ha, Q8_CRB_PEG_3, &val, 0); 92 ql_rdwr_indreg32(ha, Q8_CRB_PEG_4, &val, 0); 93 device_printf(ha->pci_dev, "%s PEGS HALTED!!!!!\n", __func__); 94 } 95 96 static int 97 qla_sysctl_stop_pegs(SYSCTL_HANDLER_ARGS) 98 { 99 int err, ret = 0; 100 qla_host_t *ha; 101 102 err = sysctl_handle_int(oidp, &ret, 0, req); 103 104 if (err || !req->newptr) 105 return (err); 106 107 if (ret == 1) { 108 ha = (qla_host_t *)arg1; 109 if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) == 0) { 110 qla_stop_pegs(ha); 111 QLA_UNLOCK(ha, __func__); 112 } 113 } 114 115 return err; 116 } 117 #endif /* #ifdef QL_DBG */ 118 119 static int 120 qla_validate_set_port_cfg_bit(uint32_t bits) 121 { 122 if ((bits & 0xF) > 1) 123 return (-1); 124 125 if (((bits >> 4) & 0xF) > 2) 126 return (-1); 127 128 if (((bits >> 8) & 0xF) > 2) 129 return (-1); 130 131 return (0); 132 } 133 134 static int 135 qla_sysctl_port_cfg(SYSCTL_HANDLER_ARGS) 136 { 137 int err, ret = 0; 138 qla_host_t *ha; 139 uint32_t cfg_bits; 140 141 err = sysctl_handle_int(oidp, &ret, 0, req); 142 143 if (err || !req->newptr) 144 return (err); 145 146 ha = (qla_host_t *)arg1; 147 148 if ((qla_validate_set_port_cfg_bit((uint32_t)ret) == 0)) { 149 err = qla_get_port_config(ha, &cfg_bits); 150 151 if (err) 152 goto qla_sysctl_set_port_cfg_exit; 153 154 if (ret & 0x1) { 155 cfg_bits |= Q8_PORT_CFG_BITS_DCBX_ENABLE; 156 } else { 157 cfg_bits &= ~Q8_PORT_CFG_BITS_DCBX_ENABLE; 158 } 159 160 ret = ret >> 4; 161 cfg_bits &= ~Q8_PORT_CFG_BITS_PAUSE_CFG_MASK; 162 163 if ((ret & 0xF) == 0) { 164 cfg_bits |= Q8_PORT_CFG_BITS_PAUSE_DISABLED; 165 } else if ((ret & 0xF) == 1){ 166 cfg_bits |= Q8_PORT_CFG_BITS_PAUSE_STD; 167 } else { 168 cfg_bits |= Q8_PORT_CFG_BITS_PAUSE_PPM; 169 } 170 171 ret = ret >> 4; 172 cfg_bits &= ~Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK; 173 174 if (ret == 0) { 175 cfg_bits |= Q8_PORT_CFG_BITS_STDPAUSE_XMT_RCV; 176 } else if (ret == 1){ 177 cfg_bits |= Q8_PORT_CFG_BITS_STDPAUSE_XMT; 178 } else { 179 cfg_bits |= Q8_PORT_CFG_BITS_STDPAUSE_RCV; 180 } 181 182 if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) == 0) { 183 err = qla_set_port_config(ha, cfg_bits); 184 QLA_UNLOCK(ha, __func__); 185 } else { 186 device_printf(ha->pci_dev, "%s: failed\n", __func__); 187 } 188 } else { 189 if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) == 0) { 190 err = qla_get_port_config(ha, &cfg_bits); 191 QLA_UNLOCK(ha, __func__); 192 } else { 193 device_printf(ha->pci_dev, "%s: failed\n", __func__); 194 } 195 } 196 197 qla_sysctl_set_port_cfg_exit: 198 return err; 199 } 200 201 static int 202 qla_sysctl_set_cam_search_mode(SYSCTL_HANDLER_ARGS) 203 { 204 int err, ret = 0; 205 qla_host_t *ha; 206 207 err = sysctl_handle_int(oidp, &ret, 0, req); 208 209 if (err || !req->newptr) 210 return (err); 211 212 ha = (qla_host_t *)arg1; 213 214 if ((ret == Q8_HW_CONFIG_CAM_SEARCH_MODE_INTERNAL) || 215 (ret == Q8_HW_CONFIG_CAM_SEARCH_MODE_AUTO)) { 216 if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) == 0) { 217 err = qla_set_cam_search_mode(ha, (uint32_t)ret); 218 QLA_UNLOCK(ha, __func__); 219 } else { 220 device_printf(ha->pci_dev, "%s: failed\n", __func__); 221 } 222 223 } else { 224 device_printf(ha->pci_dev, "%s: ret = %d\n", __func__, ret); 225 } 226 227 return (err); 228 } 229 230 static int 231 qla_sysctl_get_cam_search_mode(SYSCTL_HANDLER_ARGS) 232 { 233 int err, ret = 0; 234 qla_host_t *ha; 235 236 err = sysctl_handle_int(oidp, &ret, 0, req); 237 238 if (err || !req->newptr) 239 return (err); 240 241 ha = (qla_host_t *)arg1; 242 if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) == 0) { 243 err = qla_get_cam_search_mode(ha); 244 QLA_UNLOCK(ha, __func__); 245 } else { 246 device_printf(ha->pci_dev, "%s: failed\n", __func__); 247 } 248 249 return (err); 250 } 251 252 static void 253 qlnx_add_hw_mac_stats_sysctls(qla_host_t *ha) 254 { 255 struct sysctl_ctx_list *ctx; 256 struct sysctl_oid_list *children; 257 struct sysctl_oid *ctx_oid; 258 259 ctx = device_get_sysctl_ctx(ha->pci_dev); 260 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev)); 261 262 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_hw_mac", 263 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "stats_hw_mac"); 264 children = SYSCTL_CHILDREN(ctx_oid); 265 266 SYSCTL_ADD_QUAD(ctx, children, 267 OID_AUTO, "xmt_frames", 268 CTLFLAG_RD, &ha->hw.mac.xmt_frames, 269 "xmt_frames"); 270 271 SYSCTL_ADD_QUAD(ctx, children, 272 OID_AUTO, "xmt_bytes", 273 CTLFLAG_RD, &ha->hw.mac.xmt_bytes, 274 "xmt_frames"); 275 276 SYSCTL_ADD_QUAD(ctx, children, 277 OID_AUTO, "xmt_mcast_pkts", 278 CTLFLAG_RD, &ha->hw.mac.xmt_mcast_pkts, 279 "xmt_mcast_pkts"); 280 281 SYSCTL_ADD_QUAD(ctx, children, 282 OID_AUTO, "xmt_bcast_pkts", 283 CTLFLAG_RD, &ha->hw.mac.xmt_bcast_pkts, 284 "xmt_bcast_pkts"); 285 286 SYSCTL_ADD_QUAD(ctx, children, 287 OID_AUTO, "xmt_pause_frames", 288 CTLFLAG_RD, &ha->hw.mac.xmt_pause_frames, 289 "xmt_pause_frames"); 290 291 SYSCTL_ADD_QUAD(ctx, children, 292 OID_AUTO, "xmt_cntrl_pkts", 293 CTLFLAG_RD, &ha->hw.mac.xmt_cntrl_pkts, 294 "xmt_cntrl_pkts"); 295 296 SYSCTL_ADD_QUAD(ctx, children, 297 OID_AUTO, "xmt_pkt_lt_64bytes", 298 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_64bytes, 299 "xmt_pkt_lt_64bytes"); 300 301 SYSCTL_ADD_QUAD(ctx, children, 302 OID_AUTO, "xmt_pkt_lt_127bytes", 303 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_127bytes, 304 "xmt_pkt_lt_127bytes"); 305 306 SYSCTL_ADD_QUAD(ctx, children, 307 OID_AUTO, "xmt_pkt_lt_255bytes", 308 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_255bytes, 309 "xmt_pkt_lt_255bytes"); 310 311 SYSCTL_ADD_QUAD(ctx, children, 312 OID_AUTO, "xmt_pkt_lt_511bytes", 313 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_511bytes, 314 "xmt_pkt_lt_511bytes"); 315 316 SYSCTL_ADD_QUAD(ctx, children, 317 OID_AUTO, "xmt_pkt_lt_1023bytes", 318 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_1023bytes, 319 "xmt_pkt_lt_1023bytes"); 320 321 SYSCTL_ADD_QUAD(ctx, children, 322 OID_AUTO, "xmt_pkt_lt_1518bytes", 323 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_1518bytes, 324 "xmt_pkt_lt_1518bytes"); 325 326 SYSCTL_ADD_QUAD(ctx, children, 327 OID_AUTO, "xmt_pkt_gt_1518bytes", 328 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_gt_1518bytes, 329 "xmt_pkt_gt_1518bytes"); 330 331 SYSCTL_ADD_QUAD(ctx, children, 332 OID_AUTO, "rcv_frames", 333 CTLFLAG_RD, &ha->hw.mac.rcv_frames, 334 "rcv_frames"); 335 336 SYSCTL_ADD_QUAD(ctx, children, 337 OID_AUTO, "rcv_bytes", 338 CTLFLAG_RD, &ha->hw.mac.rcv_bytes, 339 "rcv_bytes"); 340 341 SYSCTL_ADD_QUAD(ctx, children, 342 OID_AUTO, "rcv_mcast_pkts", 343 CTLFLAG_RD, &ha->hw.mac.rcv_mcast_pkts, 344 "rcv_mcast_pkts"); 345 346 SYSCTL_ADD_QUAD(ctx, children, 347 OID_AUTO, "rcv_bcast_pkts", 348 CTLFLAG_RD, &ha->hw.mac.rcv_bcast_pkts, 349 "rcv_bcast_pkts"); 350 351 SYSCTL_ADD_QUAD(ctx, children, 352 OID_AUTO, "rcv_pause_frames", 353 CTLFLAG_RD, &ha->hw.mac.rcv_pause_frames, 354 "rcv_pause_frames"); 355 356 SYSCTL_ADD_QUAD(ctx, children, 357 OID_AUTO, "rcv_cntrl_pkts", 358 CTLFLAG_RD, &ha->hw.mac.rcv_cntrl_pkts, 359 "rcv_cntrl_pkts"); 360 361 SYSCTL_ADD_QUAD(ctx, children, 362 OID_AUTO, "rcv_pkt_lt_64bytes", 363 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_64bytes, 364 "rcv_pkt_lt_64bytes"); 365 366 SYSCTL_ADD_QUAD(ctx, children, 367 OID_AUTO, "rcv_pkt_lt_127bytes", 368 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_127bytes, 369 "rcv_pkt_lt_127bytes"); 370 371 SYSCTL_ADD_QUAD(ctx, children, 372 OID_AUTO, "rcv_pkt_lt_255bytes", 373 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_255bytes, 374 "rcv_pkt_lt_255bytes"); 375 376 SYSCTL_ADD_QUAD(ctx, children, 377 OID_AUTO, "rcv_pkt_lt_511bytes", 378 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_511bytes, 379 "rcv_pkt_lt_511bytes"); 380 381 SYSCTL_ADD_QUAD(ctx, children, 382 OID_AUTO, "rcv_pkt_lt_1023bytes", 383 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_1023bytes, 384 "rcv_pkt_lt_1023bytes"); 385 386 SYSCTL_ADD_QUAD(ctx, children, 387 OID_AUTO, "rcv_pkt_lt_1518bytes", 388 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_1518bytes, 389 "rcv_pkt_lt_1518bytes"); 390 391 SYSCTL_ADD_QUAD(ctx, children, 392 OID_AUTO, "rcv_pkt_gt_1518bytes", 393 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_gt_1518bytes, 394 "rcv_pkt_gt_1518bytes"); 395 396 SYSCTL_ADD_QUAD(ctx, children, 397 OID_AUTO, "rcv_len_error", 398 CTLFLAG_RD, &ha->hw.mac.rcv_len_error, 399 "rcv_len_error"); 400 401 SYSCTL_ADD_QUAD(ctx, children, 402 OID_AUTO, "rcv_len_small", 403 CTLFLAG_RD, &ha->hw.mac.rcv_len_small, 404 "rcv_len_small"); 405 406 SYSCTL_ADD_QUAD(ctx, children, 407 OID_AUTO, "rcv_len_large", 408 CTLFLAG_RD, &ha->hw.mac.rcv_len_large, 409 "rcv_len_large"); 410 411 SYSCTL_ADD_QUAD(ctx, children, 412 OID_AUTO, "rcv_jabber", 413 CTLFLAG_RD, &ha->hw.mac.rcv_jabber, 414 "rcv_jabber"); 415 416 SYSCTL_ADD_QUAD(ctx, children, 417 OID_AUTO, "rcv_dropped", 418 CTLFLAG_RD, &ha->hw.mac.rcv_dropped, 419 "rcv_dropped"); 420 421 SYSCTL_ADD_QUAD(ctx, children, 422 OID_AUTO, "fcs_error", 423 CTLFLAG_RD, &ha->hw.mac.fcs_error, 424 "fcs_error"); 425 426 SYSCTL_ADD_QUAD(ctx, children, 427 OID_AUTO, "align_error", 428 CTLFLAG_RD, &ha->hw.mac.align_error, 429 "align_error"); 430 431 SYSCTL_ADD_QUAD(ctx, children, 432 OID_AUTO, "eswitched_frames", 433 CTLFLAG_RD, &ha->hw.mac.eswitched_frames, 434 "eswitched_frames"); 435 436 SYSCTL_ADD_QUAD(ctx, children, 437 OID_AUTO, "eswitched_bytes", 438 CTLFLAG_RD, &ha->hw.mac.eswitched_bytes, 439 "eswitched_bytes"); 440 441 SYSCTL_ADD_QUAD(ctx, children, 442 OID_AUTO, "eswitched_mcast_frames", 443 CTLFLAG_RD, &ha->hw.mac.eswitched_mcast_frames, 444 "eswitched_mcast_frames"); 445 446 SYSCTL_ADD_QUAD(ctx, children, 447 OID_AUTO, "eswitched_bcast_frames", 448 CTLFLAG_RD, &ha->hw.mac.eswitched_bcast_frames, 449 "eswitched_bcast_frames"); 450 451 SYSCTL_ADD_QUAD(ctx, children, 452 OID_AUTO, "eswitched_ucast_frames", 453 CTLFLAG_RD, &ha->hw.mac.eswitched_ucast_frames, 454 "eswitched_ucast_frames"); 455 456 SYSCTL_ADD_QUAD(ctx, children, 457 OID_AUTO, "eswitched_err_free_frames", 458 CTLFLAG_RD, &ha->hw.mac.eswitched_err_free_frames, 459 "eswitched_err_free_frames"); 460 461 SYSCTL_ADD_QUAD(ctx, children, 462 OID_AUTO, "eswitched_err_free_bytes", 463 CTLFLAG_RD, &ha->hw.mac.eswitched_err_free_bytes, 464 "eswitched_err_free_bytes"); 465 466 return; 467 } 468 469 static void 470 qlnx_add_hw_rcv_stats_sysctls(qla_host_t *ha) 471 { 472 struct sysctl_ctx_list *ctx; 473 struct sysctl_oid_list *children; 474 struct sysctl_oid *ctx_oid; 475 476 ctx = device_get_sysctl_ctx(ha->pci_dev); 477 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev)); 478 479 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_hw_rcv", 480 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "stats_hw_rcv"); 481 children = SYSCTL_CHILDREN(ctx_oid); 482 483 SYSCTL_ADD_QUAD(ctx, children, 484 OID_AUTO, "total_bytes", 485 CTLFLAG_RD, &ha->hw.rcv.total_bytes, 486 "total_bytes"); 487 488 SYSCTL_ADD_QUAD(ctx, children, 489 OID_AUTO, "total_pkts", 490 CTLFLAG_RD, &ha->hw.rcv.total_pkts, 491 "total_pkts"); 492 493 SYSCTL_ADD_QUAD(ctx, children, 494 OID_AUTO, "lro_pkt_count", 495 CTLFLAG_RD, &ha->hw.rcv.lro_pkt_count, 496 "lro_pkt_count"); 497 498 SYSCTL_ADD_QUAD(ctx, children, 499 OID_AUTO, "sw_pkt_count", 500 CTLFLAG_RD, &ha->hw.rcv.sw_pkt_count, 501 "sw_pkt_count"); 502 503 SYSCTL_ADD_QUAD(ctx, children, 504 OID_AUTO, "ip_chksum_err", 505 CTLFLAG_RD, &ha->hw.rcv.ip_chksum_err, 506 "ip_chksum_err"); 507 508 SYSCTL_ADD_QUAD(ctx, children, 509 OID_AUTO, "pkts_wo_acntxts", 510 CTLFLAG_RD, &ha->hw.rcv.pkts_wo_acntxts, 511 "pkts_wo_acntxts"); 512 513 SYSCTL_ADD_QUAD(ctx, children, 514 OID_AUTO, "pkts_dropped_no_sds_card", 515 CTLFLAG_RD, &ha->hw.rcv.pkts_dropped_no_sds_card, 516 "pkts_dropped_no_sds_card"); 517 518 SYSCTL_ADD_QUAD(ctx, children, 519 OID_AUTO, "pkts_dropped_no_sds_host", 520 CTLFLAG_RD, &ha->hw.rcv.pkts_dropped_no_sds_host, 521 "pkts_dropped_no_sds_host"); 522 523 SYSCTL_ADD_QUAD(ctx, children, 524 OID_AUTO, "oversized_pkts", 525 CTLFLAG_RD, &ha->hw.rcv.oversized_pkts, 526 "oversized_pkts"); 527 528 SYSCTL_ADD_QUAD(ctx, children, 529 OID_AUTO, "pkts_dropped_no_rds", 530 CTLFLAG_RD, &ha->hw.rcv.pkts_dropped_no_rds, 531 "pkts_dropped_no_rds"); 532 533 SYSCTL_ADD_QUAD(ctx, children, 534 OID_AUTO, "unxpctd_mcast_pkts", 535 CTLFLAG_RD, &ha->hw.rcv.unxpctd_mcast_pkts, 536 "unxpctd_mcast_pkts"); 537 538 SYSCTL_ADD_QUAD(ctx, children, 539 OID_AUTO, "re1_fbq_error", 540 CTLFLAG_RD, &ha->hw.rcv.re1_fbq_error, 541 "re1_fbq_error"); 542 543 SYSCTL_ADD_QUAD(ctx, children, 544 OID_AUTO, "invalid_mac_addr", 545 CTLFLAG_RD, &ha->hw.rcv.invalid_mac_addr, 546 "invalid_mac_addr"); 547 548 SYSCTL_ADD_QUAD(ctx, children, 549 OID_AUTO, "rds_prime_trys", 550 CTLFLAG_RD, &ha->hw.rcv.rds_prime_trys, 551 "rds_prime_trys"); 552 553 SYSCTL_ADD_QUAD(ctx, children, 554 OID_AUTO, "rds_prime_success", 555 CTLFLAG_RD, &ha->hw.rcv.rds_prime_success, 556 "rds_prime_success"); 557 558 SYSCTL_ADD_QUAD(ctx, children, 559 OID_AUTO, "lro_flows_added", 560 CTLFLAG_RD, &ha->hw.rcv.lro_flows_added, 561 "lro_flows_added"); 562 563 SYSCTL_ADD_QUAD(ctx, children, 564 OID_AUTO, "lro_flows_deleted", 565 CTLFLAG_RD, &ha->hw.rcv.lro_flows_deleted, 566 "lro_flows_deleted"); 567 568 SYSCTL_ADD_QUAD(ctx, children, 569 OID_AUTO, "lro_flows_active", 570 CTLFLAG_RD, &ha->hw.rcv.lro_flows_active, 571 "lro_flows_active"); 572 573 SYSCTL_ADD_QUAD(ctx, children, 574 OID_AUTO, "pkts_droped_unknown", 575 CTLFLAG_RD, &ha->hw.rcv.pkts_droped_unknown, 576 "pkts_droped_unknown"); 577 578 SYSCTL_ADD_QUAD(ctx, children, 579 OID_AUTO, "pkts_cnt_oversized", 580 CTLFLAG_RD, &ha->hw.rcv.pkts_cnt_oversized, 581 "pkts_cnt_oversized"); 582 583 return; 584 } 585 586 static void 587 qlnx_add_hw_xmt_stats_sysctls(qla_host_t *ha) 588 { 589 struct sysctl_ctx_list *ctx; 590 struct sysctl_oid_list *children; 591 struct sysctl_oid_list *node_children; 592 struct sysctl_oid *ctx_oid; 593 int i; 594 uint8_t name_str[16]; 595 596 ctx = device_get_sysctl_ctx(ha->pci_dev); 597 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev)); 598 599 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_hw_xmt", 600 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "stats_hw_xmt"); 601 children = SYSCTL_CHILDREN(ctx_oid); 602 603 for (i = 0; i < ha->hw.num_tx_rings; i++) { 604 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str))); 605 snprintf(name_str, sizeof(name_str), "%d", i); 606 607 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name_str, 608 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, name_str); 609 node_children = SYSCTL_CHILDREN(ctx_oid); 610 611 /* Tx Related */ 612 613 SYSCTL_ADD_QUAD(ctx, node_children, 614 OID_AUTO, "total_bytes", 615 CTLFLAG_RD, &ha->hw.xmt[i].total_bytes, 616 "total_bytes"); 617 618 SYSCTL_ADD_QUAD(ctx, node_children, 619 OID_AUTO, "total_pkts", 620 CTLFLAG_RD, &ha->hw.xmt[i].total_pkts, 621 "total_pkts"); 622 623 SYSCTL_ADD_QUAD(ctx, node_children, 624 OID_AUTO, "errors", 625 CTLFLAG_RD, &ha->hw.xmt[i].errors, 626 "errors"); 627 628 SYSCTL_ADD_QUAD(ctx, node_children, 629 OID_AUTO, "pkts_dropped", 630 CTLFLAG_RD, &ha->hw.xmt[i].pkts_dropped, 631 "pkts_dropped"); 632 633 SYSCTL_ADD_QUAD(ctx, node_children, 634 OID_AUTO, "switch_pkts", 635 CTLFLAG_RD, &ha->hw.xmt[i].switch_pkts, 636 "switch_pkts"); 637 638 SYSCTL_ADD_QUAD(ctx, node_children, 639 OID_AUTO, "num_buffers", 640 CTLFLAG_RD, &ha->hw.xmt[i].num_buffers, 641 "num_buffers"); 642 } 643 644 return; 645 } 646 647 static void 648 qlnx_add_hw_mbx_cmpl_stats_sysctls(qla_host_t *ha) 649 { 650 struct sysctl_ctx_list *ctx; 651 struct sysctl_oid_list *node_children; 652 653 ctx = device_get_sysctl_ctx(ha->pci_dev); 654 node_children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev)); 655 656 SYSCTL_ADD_QUAD(ctx, node_children, 657 OID_AUTO, "mbx_completion_time_lt_200ms", 658 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[0], 659 "mbx_completion_time_lt_200ms"); 660 661 SYSCTL_ADD_QUAD(ctx, node_children, 662 OID_AUTO, "mbx_completion_time_200ms_400ms", 663 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[1], 664 "mbx_completion_time_200ms_400ms"); 665 666 SYSCTL_ADD_QUAD(ctx, node_children, 667 OID_AUTO, "mbx_completion_time_400ms_600ms", 668 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[2], 669 "mbx_completion_time_400ms_600ms"); 670 671 SYSCTL_ADD_QUAD(ctx, node_children, 672 OID_AUTO, "mbx_completion_time_600ms_800ms", 673 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[3], 674 "mbx_completion_time_600ms_800ms"); 675 676 SYSCTL_ADD_QUAD(ctx, node_children, 677 OID_AUTO, "mbx_completion_time_800ms_1000ms", 678 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[4], 679 "mbx_completion_time_800ms_1000ms"); 680 681 SYSCTL_ADD_QUAD(ctx, node_children, 682 OID_AUTO, "mbx_completion_time_1000ms_1200ms", 683 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[5], 684 "mbx_completion_time_1000ms_1200ms"); 685 686 SYSCTL_ADD_QUAD(ctx, node_children, 687 OID_AUTO, "mbx_completion_time_1200ms_1400ms", 688 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[6], 689 "mbx_completion_time_1200ms_1400ms"); 690 691 SYSCTL_ADD_QUAD(ctx, node_children, 692 OID_AUTO, "mbx_completion_time_1400ms_1600ms", 693 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[7], 694 "mbx_completion_time_1400ms_1600ms"); 695 696 SYSCTL_ADD_QUAD(ctx, node_children, 697 OID_AUTO, "mbx_completion_time_1600ms_1800ms", 698 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[8], 699 "mbx_completion_time_1600ms_1800ms"); 700 701 SYSCTL_ADD_QUAD(ctx, node_children, 702 OID_AUTO, "mbx_completion_time_1800ms_2000ms", 703 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[9], 704 "mbx_completion_time_1800ms_2000ms"); 705 706 SYSCTL_ADD_QUAD(ctx, node_children, 707 OID_AUTO, "mbx_completion_time_2000ms_2200ms", 708 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[10], 709 "mbx_completion_time_2000ms_2200ms"); 710 711 SYSCTL_ADD_QUAD(ctx, node_children, 712 OID_AUTO, "mbx_completion_time_2200ms_2400ms", 713 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[11], 714 "mbx_completion_time_2200ms_2400ms"); 715 716 SYSCTL_ADD_QUAD(ctx, node_children, 717 OID_AUTO, "mbx_completion_time_2400ms_2600ms", 718 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[12], 719 "mbx_completion_time_2400ms_2600ms"); 720 721 SYSCTL_ADD_QUAD(ctx, node_children, 722 OID_AUTO, "mbx_completion_time_2600ms_2800ms", 723 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[13], 724 "mbx_completion_time_2600ms_2800ms"); 725 726 SYSCTL_ADD_QUAD(ctx, node_children, 727 OID_AUTO, "mbx_completion_time_2800ms_3000ms", 728 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[14], 729 "mbx_completion_time_2800ms_3000ms"); 730 731 SYSCTL_ADD_QUAD(ctx, node_children, 732 OID_AUTO, "mbx_completion_time_3000ms_4000ms", 733 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[15], 734 "mbx_completion_time_3000ms_4000ms"); 735 736 SYSCTL_ADD_QUAD(ctx, node_children, 737 OID_AUTO, "mbx_completion_time_4000ms_5000ms", 738 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[16], 739 "mbx_completion_time_4000ms_5000ms"); 740 741 SYSCTL_ADD_QUAD(ctx, node_children, 742 OID_AUTO, "mbx_completion_host_mbx_cntrl_timeout", 743 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[17], 744 "mbx_completion_host_mbx_cntrl_timeout"); 745 746 SYSCTL_ADD_QUAD(ctx, node_children, 747 OID_AUTO, "mbx_completion_fw_mbx_cntrl_timeout", 748 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[18], 749 "mbx_completion_fw_mbx_cntrl_timeout"); 750 return; 751 } 752 753 static void 754 qlnx_add_hw_stats_sysctls(qla_host_t *ha) 755 { 756 qlnx_add_hw_mac_stats_sysctls(ha); 757 qlnx_add_hw_rcv_stats_sysctls(ha); 758 qlnx_add_hw_xmt_stats_sysctls(ha); 759 qlnx_add_hw_mbx_cmpl_stats_sysctls(ha); 760 761 return; 762 } 763 764 static void 765 qlnx_add_drvr_sds_stats(qla_host_t *ha) 766 { 767 struct sysctl_ctx_list *ctx; 768 struct sysctl_oid_list *children; 769 struct sysctl_oid_list *node_children; 770 struct sysctl_oid *ctx_oid; 771 int i; 772 uint8_t name_str[16]; 773 774 ctx = device_get_sysctl_ctx(ha->pci_dev); 775 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev)); 776 777 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_drvr_sds", 778 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "stats_drvr_sds"); 779 children = SYSCTL_CHILDREN(ctx_oid); 780 781 for (i = 0; i < ha->hw.num_sds_rings; i++) { 782 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str))); 783 snprintf(name_str, sizeof(name_str), "%d", i); 784 785 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name_str, 786 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, name_str); 787 node_children = SYSCTL_CHILDREN(ctx_oid); 788 789 SYSCTL_ADD_QUAD(ctx, node_children, 790 OID_AUTO, "intr_count", 791 CTLFLAG_RD, &ha->hw.sds[i].intr_count, 792 "intr_count"); 793 794 SYSCTL_ADD_UINT(ctx, node_children, 795 OID_AUTO, "rx_free", 796 CTLFLAG_RD, &ha->hw.sds[i].rx_free, 797 ha->hw.sds[i].rx_free, "rx_free"); 798 } 799 800 return; 801 } 802 static void 803 qlnx_add_drvr_rds_stats(qla_host_t *ha) 804 { 805 struct sysctl_ctx_list *ctx; 806 struct sysctl_oid_list *children; 807 struct sysctl_oid_list *node_children; 808 struct sysctl_oid *ctx_oid; 809 int i; 810 uint8_t name_str[16]; 811 812 ctx = device_get_sysctl_ctx(ha->pci_dev); 813 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev)); 814 815 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_drvr_rds", 816 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "stats_drvr_rds"); 817 children = SYSCTL_CHILDREN(ctx_oid); 818 819 for (i = 0; i < ha->hw.num_rds_rings; i++) { 820 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str))); 821 snprintf(name_str, sizeof(name_str), "%d", i); 822 823 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name_str, 824 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, name_str); 825 node_children = SYSCTL_CHILDREN(ctx_oid); 826 827 SYSCTL_ADD_QUAD(ctx, node_children, 828 OID_AUTO, "count", 829 CTLFLAG_RD, &ha->hw.rds[i].count, 830 "count"); 831 832 SYSCTL_ADD_QUAD(ctx, node_children, 833 OID_AUTO, "lro_pkt_count", 834 CTLFLAG_RD, &ha->hw.rds[i].lro_pkt_count, 835 "lro_pkt_count"); 836 837 SYSCTL_ADD_QUAD(ctx, node_children, 838 OID_AUTO, "lro_bytes", 839 CTLFLAG_RD, &ha->hw.rds[i].lro_bytes, 840 "lro_bytes"); 841 } 842 843 return; 844 } 845 846 static void 847 qlnx_add_drvr_tx_stats(qla_host_t *ha) 848 { 849 struct sysctl_ctx_list *ctx; 850 struct sysctl_oid_list *children; 851 struct sysctl_oid_list *node_children; 852 struct sysctl_oid *ctx_oid; 853 int i; 854 uint8_t name_str[16]; 855 856 ctx = device_get_sysctl_ctx(ha->pci_dev); 857 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev)); 858 859 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_drvr_xmt", 860 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "stats_drvr_xmt"); 861 children = SYSCTL_CHILDREN(ctx_oid); 862 863 for (i = 0; i < ha->hw.num_tx_rings; i++) { 864 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str))); 865 snprintf(name_str, sizeof(name_str), "%d", i); 866 867 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name_str, 868 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, name_str); 869 node_children = SYSCTL_CHILDREN(ctx_oid); 870 871 SYSCTL_ADD_QUAD(ctx, node_children, 872 OID_AUTO, "count", 873 CTLFLAG_RD, &ha->tx_ring[i].count, 874 "count"); 875 876 #ifdef QL_ENABLE_ISCSI_TLV 877 SYSCTL_ADD_QUAD(ctx, node_children, 878 OID_AUTO, "iscsi_pkt_count", 879 CTLFLAG_RD, &ha->tx_ring[i].iscsi_pkt_count, 880 "iscsi_pkt_count"); 881 #endif /* #ifdef QL_ENABLE_ISCSI_TLV */ 882 } 883 884 return; 885 } 886 887 static void 888 qlnx_add_drvr_stats_sysctls(qla_host_t *ha) 889 { 890 qlnx_add_drvr_sds_stats(ha); 891 qlnx_add_drvr_rds_stats(ha); 892 qlnx_add_drvr_tx_stats(ha); 893 return; 894 } 895 896 /* 897 * Name: ql_hw_add_sysctls 898 * Function: Add P3Plus specific sysctls 899 */ 900 void 901 ql_hw_add_sysctls(qla_host_t *ha) 902 { 903 device_t dev; 904 905 dev = ha->pci_dev; 906 907 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 908 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 909 OID_AUTO, "num_rds_rings", CTLFLAG_RD, &ha->hw.num_rds_rings, 910 ha->hw.num_rds_rings, "Number of Rcv Descriptor Rings"); 911 912 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 913 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 914 OID_AUTO, "num_sds_rings", CTLFLAG_RD, &ha->hw.num_sds_rings, 915 ha->hw.num_sds_rings, "Number of Status Descriptor Rings"); 916 917 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 918 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 919 OID_AUTO, "num_tx_rings", CTLFLAG_RD, &ha->hw.num_tx_rings, 920 ha->hw.num_tx_rings, "Number of Transmit Rings"); 921 922 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 923 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 924 OID_AUTO, "tx_ring_index", CTLFLAG_RW, &ha->txr_idx, 925 ha->txr_idx, "Tx Ring Used"); 926 927 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 928 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 929 OID_AUTO, "max_tx_segs", CTLFLAG_RD, &ha->hw.max_tx_segs, 930 ha->hw.max_tx_segs, "Max # of Segments in a non-TSO pkt"); 931 932 ha->hw.sds_cidx_thres = 32; 933 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 934 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 935 OID_AUTO, "sds_cidx_thres", CTLFLAG_RW, &ha->hw.sds_cidx_thres, 936 ha->hw.sds_cidx_thres, 937 "Number of SDS entries to process before updating" 938 " SDS Ring Consumer Index"); 939 940 ha->hw.rds_pidx_thres = 32; 941 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 942 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 943 OID_AUTO, "rds_pidx_thres", CTLFLAG_RW, &ha->hw.rds_pidx_thres, 944 ha->hw.rds_pidx_thres, 945 "Number of Rcv Rings Entries to post before updating" 946 " RDS Ring Producer Index"); 947 948 ha->hw.rcv_intr_coalesce = (3 << 16) | 256; 949 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 950 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 951 OID_AUTO, "rcv_intr_coalesce", CTLFLAG_RW, 952 &ha->hw.rcv_intr_coalesce, 953 ha->hw.rcv_intr_coalesce, 954 "Rcv Intr Coalescing Parameters\n" 955 "\tbits 15:0 max packets\n" 956 "\tbits 31:16 max micro-seconds to wait\n" 957 "\tplease run\n" 958 "\tifconfig <if> down && ifconfig <if> up\n" 959 "\tto take effect \n"); 960 961 ha->hw.xmt_intr_coalesce = (64 << 16) | 64; 962 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 963 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 964 OID_AUTO, "xmt_intr_coalesce", CTLFLAG_RW, 965 &ha->hw.xmt_intr_coalesce, 966 ha->hw.xmt_intr_coalesce, 967 "Xmt Intr Coalescing Parameters\n" 968 "\tbits 15:0 max packets\n" 969 "\tbits 31:16 max micro-seconds to wait\n" 970 "\tplease run\n" 971 "\tifconfig <if> down && ifconfig <if> up\n" 972 "\tto take effect \n"); 973 974 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 975 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 976 "port_cfg", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 977 (void *)ha, 0, qla_sysctl_port_cfg, "I", 978 "Set Port Configuration if values below " 979 "otherwise Get Port Configuration\n" 980 "\tBits 0-3 ; 1 = DCBX Enable; 0 = DCBX Disable\n" 981 "\tBits 4-7 : 0 = no pause; 1 = std ; 2 = ppm \n" 982 "\tBits 8-11: std pause cfg; 0 = xmt and rcv;" 983 " 1 = xmt only; 2 = rcv only;\n"); 984 985 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 986 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 987 "set_cam_search_mode", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 988 (void *)ha, 0, qla_sysctl_set_cam_search_mode, "I", 989 "Set CAM Search Mode" 990 "\t 1 = search mode internal\n" 991 "\t 2 = search mode auto\n"); 992 993 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 994 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 995 "get_cam_search_mode", 996 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, (void *)ha, 0, 997 qla_sysctl_get_cam_search_mode, "I", 998 "Get CAM Search Mode" 999 "\t 1 = search mode internal\n" 1000 "\t 2 = search mode auto\n"); 1001 1002 ha->hw.enable_9kb = 1; 1003 1004 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 1005 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1006 OID_AUTO, "enable_9kb", CTLFLAG_RW, &ha->hw.enable_9kb, 1007 ha->hw.enable_9kb, "Enable 9Kbyte Buffers when MTU = 9000"); 1008 1009 ha->hw.enable_hw_lro = 1; 1010 1011 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 1012 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1013 OID_AUTO, "enable_hw_lro", CTLFLAG_RW, &ha->hw.enable_hw_lro, 1014 ha->hw.enable_hw_lro, "Enable Hardware LRO; Default is true \n" 1015 "\t 1 : Hardware LRO if LRO is enabled\n" 1016 "\t 0 : Software LRO if LRO is enabled\n" 1017 "\t Any change requires ifconfig down/up to take effect\n" 1018 "\t Note that LRO may be turned off/on via ifconfig\n"); 1019 1020 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 1021 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1022 OID_AUTO, "sp_log_index", CTLFLAG_RW, &ha->hw.sp_log_index, 1023 ha->hw.sp_log_index, "sp_log_index"); 1024 1025 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 1026 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1027 OID_AUTO, "sp_log_stop", CTLFLAG_RW, &ha->hw.sp_log_stop, 1028 ha->hw.sp_log_stop, "sp_log_stop"); 1029 1030 ha->hw.sp_log_stop_events = 0; 1031 1032 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 1033 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1034 OID_AUTO, "sp_log_stop_events", CTLFLAG_RW, 1035 &ha->hw.sp_log_stop_events, 1036 ha->hw.sp_log_stop_events, "Slow path event log is stopped" 1037 " when OR of the following events occur \n" 1038 "\t 0x01 : Heart beat Failure\n" 1039 "\t 0x02 : Temperature Failure\n" 1040 "\t 0x04 : HW Initialization Failure\n" 1041 "\t 0x08 : Interface Initialization Failure\n" 1042 "\t 0x10 : Error Recovery Failure\n"); 1043 1044 ha->hw.mdump_active = 0; 1045 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 1046 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1047 OID_AUTO, "minidump_active", CTLFLAG_RW, &ha->hw.mdump_active, 1048 ha->hw.mdump_active, 1049 "Minidump retrieval is Active"); 1050 1051 ha->hw.mdump_done = 0; 1052 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 1053 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1054 OID_AUTO, "mdump_done", CTLFLAG_RW, 1055 &ha->hw.mdump_done, ha->hw.mdump_done, 1056 "Minidump has been done and available for retrieval"); 1057 1058 ha->hw.mdump_capture_mask = 0xF; 1059 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 1060 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1061 OID_AUTO, "minidump_capture_mask", CTLFLAG_RW, 1062 &ha->hw.mdump_capture_mask, ha->hw.mdump_capture_mask, 1063 "Minidump capture mask"); 1064 #ifdef QL_DBG 1065 1066 ha->err_inject = 0; 1067 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 1068 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1069 OID_AUTO, "err_inject", 1070 CTLFLAG_RW, &ha->err_inject, ha->err_inject, 1071 "Error to be injected\n" 1072 "\t\t\t 0: No Errors\n" 1073 "\t\t\t 1: rcv: rxb struct invalid\n" 1074 "\t\t\t 2: rcv: mp == NULL\n" 1075 "\t\t\t 3: lro: rxb struct invalid\n" 1076 "\t\t\t 4: lro: mp == NULL\n" 1077 "\t\t\t 5: rcv: num handles invalid\n" 1078 "\t\t\t 6: reg: indirect reg rd_wr failure\n" 1079 "\t\t\t 7: ocm: offchip memory rd_wr failure\n" 1080 "\t\t\t 8: mbx: mailbox command failure\n" 1081 "\t\t\t 9: heartbeat failure\n" 1082 "\t\t\t A: temperature failure\n" 1083 "\t\t\t 11: m_getcl or m_getjcl failure\n" 1084 "\t\t\t 13: Invalid Descriptor Count in SGL Receive\n" 1085 "\t\t\t 14: Invalid Descriptor Count in LRO Receive\n" 1086 "\t\t\t 15: peer port error recovery failure\n" 1087 "\t\t\t 16: tx_buf[next_prod_index].mbuf != NULL\n" ); 1088 1089 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1090 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 1091 "peg_stop", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1092 (void *)ha, 0, qla_sysctl_stop_pegs, "I", "Peg Stop"); 1093 1094 #endif /* #ifdef QL_DBG */ 1095 1096 ha->hw.user_pri_nic = 0; 1097 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 1098 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1099 OID_AUTO, "user_pri_nic", CTLFLAG_RW, &ha->hw.user_pri_nic, 1100 ha->hw.user_pri_nic, 1101 "VLAN Tag User Priority for Normal Ethernet Packets"); 1102 1103 ha->hw.user_pri_iscsi = 4; 1104 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 1105 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1106 OID_AUTO, "user_pri_iscsi", CTLFLAG_RW, &ha->hw.user_pri_iscsi, 1107 ha->hw.user_pri_iscsi, 1108 "VLAN Tag User Priority for iSCSI Packets"); 1109 1110 qlnx_add_hw_stats_sysctls(ha); 1111 qlnx_add_drvr_stats_sysctls(ha); 1112 1113 return; 1114 } 1115 1116 void 1117 ql_hw_link_status(qla_host_t *ha) 1118 { 1119 device_printf(ha->pci_dev, "cable_oui\t\t 0x%08x\n", ha->hw.cable_oui); 1120 1121 if (ha->hw.link_up) { 1122 device_printf(ha->pci_dev, "link Up\n"); 1123 } else { 1124 device_printf(ha->pci_dev, "link Down\n"); 1125 } 1126 1127 if (ha->hw.fduplex) { 1128 device_printf(ha->pci_dev, "Full Duplex\n"); 1129 } else { 1130 device_printf(ha->pci_dev, "Half Duplex\n"); 1131 } 1132 1133 if (ha->hw.autoneg) { 1134 device_printf(ha->pci_dev, "Auto Negotiation Enabled\n"); 1135 } else { 1136 device_printf(ha->pci_dev, "Auto Negotiation Disabled\n"); 1137 } 1138 1139 switch (ha->hw.link_speed) { 1140 case 0x710: 1141 device_printf(ha->pci_dev, "link speed\t\t 10Gps\n"); 1142 break; 1143 1144 case 0x3E8: 1145 device_printf(ha->pci_dev, "link speed\t\t 1Gps\n"); 1146 break; 1147 1148 case 0x64: 1149 device_printf(ha->pci_dev, "link speed\t\t 100Mbps\n"); 1150 break; 1151 1152 default: 1153 device_printf(ha->pci_dev, "link speed\t\t Unknown\n"); 1154 break; 1155 } 1156 1157 switch (ha->hw.module_type) { 1158 case 0x01: 1159 device_printf(ha->pci_dev, "Module Type 10GBase-LRM\n"); 1160 break; 1161 1162 case 0x02: 1163 device_printf(ha->pci_dev, "Module Type 10GBase-LR\n"); 1164 break; 1165 1166 case 0x03: 1167 device_printf(ha->pci_dev, "Module Type 10GBase-SR\n"); 1168 break; 1169 1170 case 0x04: 1171 device_printf(ha->pci_dev, 1172 "Module Type 10GE Passive Copper(Compliant)[%d m]\n", 1173 ha->hw.cable_length); 1174 break; 1175 1176 case 0x05: 1177 device_printf(ha->pci_dev, "Module Type 10GE Active" 1178 " Limiting Copper(Compliant)[%d m]\n", 1179 ha->hw.cable_length); 1180 break; 1181 1182 case 0x06: 1183 device_printf(ha->pci_dev, 1184 "Module Type 10GE Passive Copper" 1185 " (Legacy, Best Effort)[%d m]\n", 1186 ha->hw.cable_length); 1187 break; 1188 1189 case 0x07: 1190 device_printf(ha->pci_dev, "Module Type 1000Base-SX\n"); 1191 break; 1192 1193 case 0x08: 1194 device_printf(ha->pci_dev, "Module Type 1000Base-LX\n"); 1195 break; 1196 1197 case 0x09: 1198 device_printf(ha->pci_dev, "Module Type 1000Base-CX\n"); 1199 break; 1200 1201 case 0x0A: 1202 device_printf(ha->pci_dev, "Module Type 1000Base-T\n"); 1203 break; 1204 1205 case 0x0B: 1206 device_printf(ha->pci_dev, "Module Type 1GE Passive Copper" 1207 "(Legacy, Best Effort)\n"); 1208 break; 1209 1210 default: 1211 device_printf(ha->pci_dev, "Unknown Module Type 0x%x\n", 1212 ha->hw.module_type); 1213 break; 1214 } 1215 1216 if (ha->hw.link_faults == 1) 1217 device_printf(ha->pci_dev, "SFP Power Fault\n"); 1218 } 1219 1220 /* 1221 * Name: ql_free_dma 1222 * Function: Frees the DMA'able memory allocated in ql_alloc_dma() 1223 */ 1224 void 1225 ql_free_dma(qla_host_t *ha) 1226 { 1227 uint32_t i; 1228 1229 if (ha->hw.dma_buf.flags.sds_ring) { 1230 for (i = 0; i < ha->hw.num_sds_rings; i++) { 1231 ql_free_dmabuf(ha, &ha->hw.dma_buf.sds_ring[i]); 1232 } 1233 ha->hw.dma_buf.flags.sds_ring = 0; 1234 } 1235 1236 if (ha->hw.dma_buf.flags.rds_ring) { 1237 for (i = 0; i < ha->hw.num_rds_rings; i++) { 1238 ql_free_dmabuf(ha, &ha->hw.dma_buf.rds_ring[i]); 1239 } 1240 ha->hw.dma_buf.flags.rds_ring = 0; 1241 } 1242 1243 if (ha->hw.dma_buf.flags.tx_ring) { 1244 ql_free_dmabuf(ha, &ha->hw.dma_buf.tx_ring); 1245 ha->hw.dma_buf.flags.tx_ring = 0; 1246 } 1247 ql_minidump_free(ha); 1248 } 1249 1250 /* 1251 * Name: ql_alloc_dma 1252 * Function: Allocates DMA'able memory for Tx/Rx Rings, Tx/Rx Contexts. 1253 */ 1254 int 1255 ql_alloc_dma(qla_host_t *ha) 1256 { 1257 device_t dev; 1258 uint32_t i, j, size, tx_ring_size; 1259 qla_hw_t *hw; 1260 qla_hw_tx_cntxt_t *tx_cntxt; 1261 uint8_t *vaddr; 1262 bus_addr_t paddr; 1263 1264 dev = ha->pci_dev; 1265 1266 QL_DPRINT2(ha, (dev, "%s: enter\n", __func__)); 1267 1268 hw = &ha->hw; 1269 /* 1270 * Allocate Transmit Ring 1271 */ 1272 tx_ring_size = (sizeof(q80_tx_cmd_t) * NUM_TX_DESCRIPTORS); 1273 size = (tx_ring_size * ha->hw.num_tx_rings); 1274 1275 hw->dma_buf.tx_ring.alignment = 8; 1276 hw->dma_buf.tx_ring.size = size + PAGE_SIZE; 1277 1278 if (ql_alloc_dmabuf(ha, &hw->dma_buf.tx_ring)) { 1279 device_printf(dev, "%s: tx ring alloc failed\n", __func__); 1280 goto ql_alloc_dma_exit; 1281 } 1282 1283 vaddr = (uint8_t *)hw->dma_buf.tx_ring.dma_b; 1284 paddr = hw->dma_buf.tx_ring.dma_addr; 1285 1286 for (i = 0; i < ha->hw.num_tx_rings; i++) { 1287 tx_cntxt = (qla_hw_tx_cntxt_t *)&hw->tx_cntxt[i]; 1288 1289 tx_cntxt->tx_ring_base = (q80_tx_cmd_t *)vaddr; 1290 tx_cntxt->tx_ring_paddr = paddr; 1291 1292 vaddr += tx_ring_size; 1293 paddr += tx_ring_size; 1294 } 1295 1296 for (i = 0; i < ha->hw.num_tx_rings; i++) { 1297 tx_cntxt = (qla_hw_tx_cntxt_t *)&hw->tx_cntxt[i]; 1298 1299 tx_cntxt->tx_cons = (uint32_t *)vaddr; 1300 tx_cntxt->tx_cons_paddr = paddr; 1301 1302 vaddr += sizeof (uint32_t); 1303 paddr += sizeof (uint32_t); 1304 } 1305 1306 ha->hw.dma_buf.flags.tx_ring = 1; 1307 1308 QL_DPRINT2(ha, (dev, "%s: tx_ring phys %p virt %p\n", 1309 __func__, (void *)(hw->dma_buf.tx_ring.dma_addr), 1310 hw->dma_buf.tx_ring.dma_b)); 1311 /* 1312 * Allocate Receive Descriptor Rings 1313 */ 1314 1315 for (i = 0; i < hw->num_rds_rings; i++) { 1316 hw->dma_buf.rds_ring[i].alignment = 8; 1317 hw->dma_buf.rds_ring[i].size = 1318 (sizeof(q80_recv_desc_t)) * NUM_RX_DESCRIPTORS; 1319 1320 if (ql_alloc_dmabuf(ha, &hw->dma_buf.rds_ring[i])) { 1321 device_printf(dev, "%s: rds ring[%d] alloc failed\n", 1322 __func__, i); 1323 1324 for (j = 0; j < i; j++) 1325 ql_free_dmabuf(ha, &hw->dma_buf.rds_ring[j]); 1326 1327 goto ql_alloc_dma_exit; 1328 } 1329 QL_DPRINT4(ha, (dev, "%s: rx_ring[%d] phys %p virt %p\n", 1330 __func__, i, (void *)(hw->dma_buf.rds_ring[i].dma_addr), 1331 hw->dma_buf.rds_ring[i].dma_b)); 1332 } 1333 1334 hw->dma_buf.flags.rds_ring = 1; 1335 1336 /* 1337 * Allocate Status Descriptor Rings 1338 */ 1339 1340 for (i = 0; i < hw->num_sds_rings; i++) { 1341 hw->dma_buf.sds_ring[i].alignment = 8; 1342 hw->dma_buf.sds_ring[i].size = 1343 (sizeof(q80_stat_desc_t)) * NUM_STATUS_DESCRIPTORS; 1344 1345 if (ql_alloc_dmabuf(ha, &hw->dma_buf.sds_ring[i])) { 1346 device_printf(dev, "%s: sds ring alloc failed\n", 1347 __func__); 1348 1349 for (j = 0; j < i; j++) 1350 ql_free_dmabuf(ha, &hw->dma_buf.sds_ring[j]); 1351 1352 goto ql_alloc_dma_exit; 1353 } 1354 QL_DPRINT4(ha, (dev, "%s: sds_ring[%d] phys %p virt %p\n", 1355 __func__, i, 1356 (void *)(hw->dma_buf.sds_ring[i].dma_addr), 1357 hw->dma_buf.sds_ring[i].dma_b)); 1358 } 1359 for (i = 0; i < hw->num_sds_rings; i++) { 1360 hw->sds[i].sds_ring_base = 1361 (q80_stat_desc_t *)hw->dma_buf.sds_ring[i].dma_b; 1362 } 1363 1364 hw->dma_buf.flags.sds_ring = 1; 1365 1366 return 0; 1367 1368 ql_alloc_dma_exit: 1369 ql_free_dma(ha); 1370 return -1; 1371 } 1372 1373 #define Q8_MBX_MSEC_DELAY 5000 1374 1375 static int 1376 qla_mbx_cmd(qla_host_t *ha, uint32_t *h_mbox, uint32_t n_hmbox, 1377 uint32_t *fw_mbox, uint32_t n_fwmbox, uint32_t no_pause) 1378 { 1379 uint32_t i; 1380 uint32_t data; 1381 int ret = 0; 1382 uint64_t start_usecs; 1383 uint64_t end_usecs; 1384 uint64_t msecs_200; 1385 1386 ql_sp_log(ha, 0, 5, no_pause, h_mbox[0], h_mbox[1], h_mbox[2], h_mbox[3]); 1387 1388 if (ha->offline || ha->qla_initiate_recovery) { 1389 ql_sp_log(ha, 1, 2, ha->offline, ha->qla_initiate_recovery, 0, 0, 0); 1390 goto exit_qla_mbx_cmd; 1391 } 1392 1393 if (((ha->err_inject & 0xFFFF) == INJCT_MBX_CMD_FAILURE) && 1394 (((ha->err_inject & ~0xFFFF) == ((h_mbox[0] & 0xFFFF) << 16))|| 1395 !(ha->err_inject & ~0xFFFF))) { 1396 ret = -3; 1397 QL_INITIATE_RECOVERY(ha); 1398 goto exit_qla_mbx_cmd; 1399 } 1400 1401 start_usecs = qla_get_usec_timestamp(); 1402 1403 if (no_pause) 1404 i = 1000; 1405 else 1406 i = Q8_MBX_MSEC_DELAY; 1407 1408 while (i) { 1409 if (ha->qla_initiate_recovery) { 1410 ql_sp_log(ha, 2, 1, ha->qla_initiate_recovery, 0, 0, 0, 0); 1411 return (-1); 1412 } 1413 1414 data = READ_REG32(ha, Q8_HOST_MBOX_CNTRL); 1415 if (data == 0) 1416 break; 1417 if (no_pause) { 1418 DELAY(1000); 1419 } else { 1420 qla_mdelay(__func__, 1); 1421 } 1422 i--; 1423 } 1424 1425 if (i == 0) { 1426 device_printf(ha->pci_dev, "%s: host_mbx_cntrl 0x%08x\n", 1427 __func__, data); 1428 ql_sp_log(ha, 3, 1, data, 0, 0, 0, 0); 1429 ret = -1; 1430 ha->hw.mbx_comp_msecs[(Q8_MBX_COMP_MSECS - 2)]++; 1431 QL_INITIATE_RECOVERY(ha); 1432 goto exit_qla_mbx_cmd; 1433 } 1434 1435 for (i = 0; i < n_hmbox; i++) { 1436 WRITE_REG32(ha, (Q8_HOST_MBOX0 + (i << 2)), *h_mbox); 1437 h_mbox++; 1438 } 1439 1440 WRITE_REG32(ha, Q8_HOST_MBOX_CNTRL, 0x1); 1441 1442 i = Q8_MBX_MSEC_DELAY; 1443 while (i) { 1444 if (ha->qla_initiate_recovery) { 1445 ql_sp_log(ha, 4, 1, ha->qla_initiate_recovery, 0, 0, 0, 0); 1446 return (-1); 1447 } 1448 1449 data = READ_REG32(ha, Q8_FW_MBOX_CNTRL); 1450 1451 if ((data & 0x3) == 1) { 1452 data = READ_REG32(ha, Q8_FW_MBOX0); 1453 if ((data & 0xF000) != 0x8000) 1454 break; 1455 } 1456 if (no_pause) { 1457 DELAY(1000); 1458 } else { 1459 qla_mdelay(__func__, 1); 1460 } 1461 i--; 1462 } 1463 if (i == 0) { 1464 device_printf(ha->pci_dev, "%s: fw_mbx_cntrl 0x%08x\n", 1465 __func__, data); 1466 ql_sp_log(ha, 5, 1, data, 0, 0, 0, 0); 1467 ret = -2; 1468 ha->hw.mbx_comp_msecs[(Q8_MBX_COMP_MSECS - 1)]++; 1469 QL_INITIATE_RECOVERY(ha); 1470 goto exit_qla_mbx_cmd; 1471 } 1472 1473 for (i = 0; i < n_fwmbox; i++) { 1474 if (ha->qla_initiate_recovery) { 1475 ql_sp_log(ha, 6, 1, ha->qla_initiate_recovery, 0, 0, 0, 0); 1476 return (-1); 1477 } 1478 1479 *fw_mbox++ = READ_REG32(ha, (Q8_FW_MBOX0 + (i << 2))); 1480 } 1481 1482 WRITE_REG32(ha, Q8_FW_MBOX_CNTRL, 0x0); 1483 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0); 1484 1485 end_usecs = qla_get_usec_timestamp(); 1486 1487 if (end_usecs > start_usecs) { 1488 msecs_200 = (end_usecs - start_usecs)/(1000 * 200); 1489 1490 if (msecs_200 < 15) 1491 ha->hw.mbx_comp_msecs[msecs_200]++; 1492 else if (msecs_200 < 20) 1493 ha->hw.mbx_comp_msecs[15]++; 1494 else { 1495 device_printf(ha->pci_dev, "%s: [%ld, %ld] %ld\n", __func__, 1496 start_usecs, end_usecs, msecs_200); 1497 ha->hw.mbx_comp_msecs[16]++; 1498 } 1499 } 1500 ql_sp_log(ha, 7, 5, fw_mbox[0], fw_mbox[1], fw_mbox[2], fw_mbox[3], fw_mbox[4]); 1501 1502 exit_qla_mbx_cmd: 1503 return (ret); 1504 } 1505 1506 int 1507 qla_get_nic_partition(qla_host_t *ha, uint32_t *supports_9kb, 1508 uint32_t *num_rcvq) 1509 { 1510 uint32_t *mbox, err; 1511 device_t dev = ha->pci_dev; 1512 1513 bzero(ha->hw.mbox, (sizeof (uint32_t) * Q8_NUM_MBOX)); 1514 1515 mbox = ha->hw.mbox; 1516 1517 mbox[0] = Q8_MBX_GET_NIC_PARTITION | (0x2 << 16) | (0x2 << 29); 1518 1519 if (qla_mbx_cmd(ha, mbox, 2, mbox, 19, 0)) { 1520 device_printf(dev, "%s: failed0\n", __func__); 1521 return (-1); 1522 } 1523 err = mbox[0] >> 25; 1524 1525 if (supports_9kb != NULL) { 1526 if (mbox[16] & 0x80) /* bit 7 of mbox 16 */ 1527 *supports_9kb = 1; 1528 else 1529 *supports_9kb = 0; 1530 } 1531 1532 if (num_rcvq != NULL) 1533 *num_rcvq = ((mbox[6] >> 16) & 0xFFFF); 1534 1535 if ((err != 1) && (err != 0)) { 1536 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 1537 return (-1); 1538 } 1539 return 0; 1540 } 1541 1542 static int 1543 qla_config_intr_cntxt(qla_host_t *ha, uint32_t start_idx, uint32_t num_intrs, 1544 uint32_t create) 1545 { 1546 uint32_t i, err; 1547 device_t dev = ha->pci_dev; 1548 q80_config_intr_t *c_intr; 1549 q80_config_intr_rsp_t *c_intr_rsp; 1550 1551 c_intr = (q80_config_intr_t *)ha->hw.mbox; 1552 bzero(c_intr, (sizeof (q80_config_intr_t))); 1553 1554 c_intr->opcode = Q8_MBX_CONFIG_INTR; 1555 1556 c_intr->count_version = (sizeof (q80_config_intr_t) >> 2); 1557 c_intr->count_version |= Q8_MBX_CMD_VERSION; 1558 1559 c_intr->nentries = num_intrs; 1560 1561 for (i = 0; i < num_intrs; i++) { 1562 if (create) { 1563 c_intr->intr[i].cmd_type = Q8_MBX_CONFIG_INTR_CREATE; 1564 c_intr->intr[i].msix_index = start_idx + 1 + i; 1565 } else { 1566 c_intr->intr[i].cmd_type = Q8_MBX_CONFIG_INTR_DELETE; 1567 c_intr->intr[i].msix_index = 1568 ha->hw.intr_id[(start_idx + i)]; 1569 } 1570 1571 c_intr->intr[i].cmd_type |= Q8_MBX_CONFIG_INTR_TYPE_MSI_X; 1572 } 1573 1574 if (qla_mbx_cmd(ha, (uint32_t *)c_intr, 1575 (sizeof (q80_config_intr_t) >> 2), 1576 ha->hw.mbox, (sizeof (q80_config_intr_rsp_t) >> 2), 0)) { 1577 device_printf(dev, "%s: %s failed0\n", __func__, 1578 (create ? "create" : "delete")); 1579 return (-1); 1580 } 1581 1582 c_intr_rsp = (q80_config_intr_rsp_t *)ha->hw.mbox; 1583 1584 err = Q8_MBX_RSP_STATUS(c_intr_rsp->regcnt_status); 1585 1586 if (err) { 1587 device_printf(dev, "%s: %s failed1 [0x%08x, %d]\n", __func__, 1588 (create ? "create" : "delete"), err, c_intr_rsp->nentries); 1589 1590 for (i = 0; i < c_intr_rsp->nentries; i++) { 1591 device_printf(dev, "%s: [%d]:[0x%x 0x%x 0x%x]\n", 1592 __func__, i, 1593 c_intr_rsp->intr[i].status, 1594 c_intr_rsp->intr[i].intr_id, 1595 c_intr_rsp->intr[i].intr_src); 1596 } 1597 1598 return (-1); 1599 } 1600 1601 for (i = 0; ((i < num_intrs) && create); i++) { 1602 if (!c_intr_rsp->intr[i].status) { 1603 ha->hw.intr_id[(start_idx + i)] = 1604 c_intr_rsp->intr[i].intr_id; 1605 ha->hw.intr_src[(start_idx + i)] = 1606 c_intr_rsp->intr[i].intr_src; 1607 } 1608 } 1609 1610 return (0); 1611 } 1612 1613 /* 1614 * Name: qla_config_rss 1615 * Function: Configure RSS for the context/interface. 1616 */ 1617 static const uint64_t rss_key[] = { 0xbeac01fa6a42b73bULL, 1618 0x8030f20c77cb2da3ULL, 1619 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL, 1620 0x255b0ec26d5a56daULL }; 1621 1622 static int 1623 qla_config_rss(qla_host_t *ha, uint16_t cntxt_id) 1624 { 1625 q80_config_rss_t *c_rss; 1626 q80_config_rss_rsp_t *c_rss_rsp; 1627 uint32_t err, i; 1628 device_t dev = ha->pci_dev; 1629 1630 c_rss = (q80_config_rss_t *)ha->hw.mbox; 1631 bzero(c_rss, (sizeof (q80_config_rss_t))); 1632 1633 c_rss->opcode = Q8_MBX_CONFIG_RSS; 1634 1635 c_rss->count_version = (sizeof (q80_config_rss_t) >> 2); 1636 c_rss->count_version |= Q8_MBX_CMD_VERSION; 1637 1638 c_rss->hash_type = (Q8_MBX_RSS_HASH_TYPE_IPV4_TCP_IP | 1639 Q8_MBX_RSS_HASH_TYPE_IPV6_TCP_IP); 1640 //c_rss->hash_type = (Q8_MBX_RSS_HASH_TYPE_IPV4_TCP | 1641 // Q8_MBX_RSS_HASH_TYPE_IPV6_TCP); 1642 1643 c_rss->flags = Q8_MBX_RSS_FLAGS_ENABLE_RSS; 1644 c_rss->flags |= Q8_MBX_RSS_FLAGS_USE_IND_TABLE; 1645 1646 c_rss->indtbl_mask = Q8_MBX_RSS_INDTBL_MASK; 1647 1648 c_rss->indtbl_mask |= Q8_MBX_RSS_FLAGS_MULTI_RSS_VALID; 1649 c_rss->flags |= Q8_MBX_RSS_FLAGS_TYPE_CRSS; 1650 1651 c_rss->cntxt_id = cntxt_id; 1652 1653 for (i = 0; i < 5; i++) { 1654 c_rss->rss_key[i] = rss_key[i]; 1655 } 1656 1657 if (qla_mbx_cmd(ha, (uint32_t *)c_rss, 1658 (sizeof (q80_config_rss_t) >> 2), 1659 ha->hw.mbox, (sizeof(q80_config_rss_rsp_t) >> 2), 0)) { 1660 device_printf(dev, "%s: failed0\n", __func__); 1661 return (-1); 1662 } 1663 c_rss_rsp = (q80_config_rss_rsp_t *)ha->hw.mbox; 1664 1665 err = Q8_MBX_RSP_STATUS(c_rss_rsp->regcnt_status); 1666 1667 if (err) { 1668 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 1669 return (-1); 1670 } 1671 return 0; 1672 } 1673 1674 static int 1675 qla_set_rss_ind_table(qla_host_t *ha, uint32_t start_idx, uint32_t count, 1676 uint16_t cntxt_id, uint8_t *ind_table) 1677 { 1678 q80_config_rss_ind_table_t *c_rss_ind; 1679 q80_config_rss_ind_table_rsp_t *c_rss_ind_rsp; 1680 uint32_t err; 1681 device_t dev = ha->pci_dev; 1682 1683 if ((count > Q8_RSS_IND_TBL_SIZE) || 1684 ((start_idx + count - 1) > Q8_RSS_IND_TBL_MAX_IDX)) { 1685 device_printf(dev, "%s: illegal count [%d, %d]\n", __func__, 1686 start_idx, count); 1687 return (-1); 1688 } 1689 1690 c_rss_ind = (q80_config_rss_ind_table_t *)ha->hw.mbox; 1691 bzero(c_rss_ind, sizeof (q80_config_rss_ind_table_t)); 1692 1693 c_rss_ind->opcode = Q8_MBX_CONFIG_RSS_TABLE; 1694 c_rss_ind->count_version = (sizeof (q80_config_rss_ind_table_t) >> 2); 1695 c_rss_ind->count_version |= Q8_MBX_CMD_VERSION; 1696 1697 c_rss_ind->start_idx = start_idx; 1698 c_rss_ind->end_idx = start_idx + count - 1; 1699 c_rss_ind->cntxt_id = cntxt_id; 1700 bcopy(ind_table, c_rss_ind->ind_table, count); 1701 1702 if (qla_mbx_cmd(ha, (uint32_t *)c_rss_ind, 1703 (sizeof (q80_config_rss_ind_table_t) >> 2), ha->hw.mbox, 1704 (sizeof(q80_config_rss_ind_table_rsp_t) >> 2), 0)) { 1705 device_printf(dev, "%s: failed0\n", __func__); 1706 return (-1); 1707 } 1708 1709 c_rss_ind_rsp = (q80_config_rss_ind_table_rsp_t *)ha->hw.mbox; 1710 err = Q8_MBX_RSP_STATUS(c_rss_ind_rsp->regcnt_status); 1711 1712 if (err) { 1713 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 1714 return (-1); 1715 } 1716 return 0; 1717 } 1718 1719 /* 1720 * Name: qla_config_intr_coalesce 1721 * Function: Configure Interrupt Coalescing. 1722 */ 1723 static int 1724 qla_config_intr_coalesce(qla_host_t *ha, uint16_t cntxt_id, int tenable, 1725 int rcv) 1726 { 1727 q80_config_intr_coalesc_t *intrc; 1728 q80_config_intr_coalesc_rsp_t *intrc_rsp; 1729 uint32_t err, i; 1730 device_t dev = ha->pci_dev; 1731 1732 intrc = (q80_config_intr_coalesc_t *)ha->hw.mbox; 1733 bzero(intrc, (sizeof (q80_config_intr_coalesc_t))); 1734 1735 intrc->opcode = Q8_MBX_CONFIG_INTR_COALESCE; 1736 intrc->count_version = (sizeof (q80_config_intr_coalesc_t) >> 2); 1737 intrc->count_version |= Q8_MBX_CMD_VERSION; 1738 1739 if (rcv) { 1740 intrc->flags = Q8_MBX_INTRC_FLAGS_RCV; 1741 intrc->max_pkts = ha->hw.rcv_intr_coalesce & 0xFFFF; 1742 intrc->max_mswait = (ha->hw.rcv_intr_coalesce >> 16) & 0xFFFF; 1743 } else { 1744 intrc->flags = Q8_MBX_INTRC_FLAGS_XMT; 1745 intrc->max_pkts = ha->hw.xmt_intr_coalesce & 0xFFFF; 1746 intrc->max_mswait = (ha->hw.xmt_intr_coalesce >> 16) & 0xFFFF; 1747 } 1748 1749 intrc->cntxt_id = cntxt_id; 1750 1751 if (tenable) { 1752 intrc->flags |= Q8_MBX_INTRC_FLAGS_PERIODIC; 1753 intrc->timer_type = Q8_MBX_INTRC_TIMER_PERIODIC; 1754 1755 for (i = 0; i < ha->hw.num_sds_rings; i++) { 1756 intrc->sds_ring_mask |= (1 << i); 1757 } 1758 intrc->ms_timeout = 1000; 1759 } 1760 1761 if (qla_mbx_cmd(ha, (uint32_t *)intrc, 1762 (sizeof (q80_config_intr_coalesc_t) >> 2), 1763 ha->hw.mbox, (sizeof(q80_config_intr_coalesc_rsp_t) >> 2), 0)) { 1764 device_printf(dev, "%s: failed0\n", __func__); 1765 return (-1); 1766 } 1767 intrc_rsp = (q80_config_intr_coalesc_rsp_t *)ha->hw.mbox; 1768 1769 err = Q8_MBX_RSP_STATUS(intrc_rsp->regcnt_status); 1770 1771 if (err) { 1772 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 1773 return (-1); 1774 } 1775 1776 return 0; 1777 } 1778 1779 /* 1780 * Name: qla_config_mac_addr 1781 * Function: binds a MAC address to the context/interface. 1782 * Can be unicast, multicast or broadcast. 1783 */ 1784 static int 1785 qla_config_mac_addr(qla_host_t *ha, uint8_t *mac_addr, uint32_t add_mac, 1786 uint32_t num_mac) 1787 { 1788 q80_config_mac_addr_t *cmac; 1789 q80_config_mac_addr_rsp_t *cmac_rsp; 1790 uint32_t err; 1791 device_t dev = ha->pci_dev; 1792 int i; 1793 uint8_t *mac_cpy = mac_addr; 1794 1795 if (num_mac > Q8_MAX_MAC_ADDRS) { 1796 device_printf(dev, "%s: %s num_mac [0x%x] > Q8_MAX_MAC_ADDRS\n", 1797 __func__, (add_mac ? "Add" : "Del"), num_mac); 1798 return (-1); 1799 } 1800 1801 cmac = (q80_config_mac_addr_t *)ha->hw.mbox; 1802 bzero(cmac, (sizeof (q80_config_mac_addr_t))); 1803 1804 cmac->opcode = Q8_MBX_CONFIG_MAC_ADDR; 1805 cmac->count_version = sizeof (q80_config_mac_addr_t) >> 2; 1806 cmac->count_version |= Q8_MBX_CMD_VERSION; 1807 1808 if (add_mac) 1809 cmac->cmd = Q8_MBX_CMAC_CMD_ADD_MAC_ADDR; 1810 else 1811 cmac->cmd = Q8_MBX_CMAC_CMD_DEL_MAC_ADDR; 1812 1813 cmac->cmd |= Q8_MBX_CMAC_CMD_CAM_INGRESS; 1814 1815 cmac->nmac_entries = num_mac; 1816 cmac->cntxt_id = ha->hw.rcv_cntxt_id; 1817 1818 for (i = 0; i < num_mac; i++) { 1819 bcopy(mac_addr, cmac->mac_addr[i].addr, Q8_ETHER_ADDR_LEN); 1820 mac_addr = mac_addr + ETHER_ADDR_LEN; 1821 } 1822 1823 if (qla_mbx_cmd(ha, (uint32_t *)cmac, 1824 (sizeof (q80_config_mac_addr_t) >> 2), 1825 ha->hw.mbox, (sizeof(q80_config_mac_addr_rsp_t) >> 2), 1)) { 1826 device_printf(dev, "%s: %s failed0\n", __func__, 1827 (add_mac ? "Add" : "Del")); 1828 return (-1); 1829 } 1830 cmac_rsp = (q80_config_mac_addr_rsp_t *)ha->hw.mbox; 1831 1832 err = Q8_MBX_RSP_STATUS(cmac_rsp->regcnt_status); 1833 1834 if (err) { 1835 device_printf(dev, "%s: %s failed1 [0x%08x]\n", __func__, 1836 (add_mac ? "Add" : "Del"), err); 1837 for (i = 0; i < num_mac; i++) { 1838 device_printf(dev, "%s: %02x:%02x:%02x:%02x:%02x:%02x\n", 1839 __func__, mac_cpy[0], mac_cpy[1], mac_cpy[2], 1840 mac_cpy[3], mac_cpy[4], mac_cpy[5]); 1841 mac_cpy += ETHER_ADDR_LEN; 1842 } 1843 return (-1); 1844 } 1845 1846 return 0; 1847 } 1848 1849 /* 1850 * Name: qla_set_mac_rcv_mode 1851 * Function: Enable/Disable AllMulticast and Promiscous Modes. 1852 */ 1853 static int 1854 qla_set_mac_rcv_mode(qla_host_t *ha, uint32_t mode) 1855 { 1856 q80_config_mac_rcv_mode_t *rcv_mode; 1857 uint32_t err; 1858 q80_config_mac_rcv_mode_rsp_t *rcv_mode_rsp; 1859 device_t dev = ha->pci_dev; 1860 1861 rcv_mode = (q80_config_mac_rcv_mode_t *)ha->hw.mbox; 1862 bzero(rcv_mode, (sizeof (q80_config_mac_rcv_mode_t))); 1863 1864 rcv_mode->opcode = Q8_MBX_CONFIG_MAC_RX_MODE; 1865 rcv_mode->count_version = sizeof (q80_config_mac_rcv_mode_t) >> 2; 1866 rcv_mode->count_version |= Q8_MBX_CMD_VERSION; 1867 1868 rcv_mode->mode = mode; 1869 1870 rcv_mode->cntxt_id = ha->hw.rcv_cntxt_id; 1871 1872 if (qla_mbx_cmd(ha, (uint32_t *)rcv_mode, 1873 (sizeof (q80_config_mac_rcv_mode_t) >> 2), 1874 ha->hw.mbox, (sizeof(q80_config_mac_rcv_mode_rsp_t) >> 2), 1)) { 1875 device_printf(dev, "%s: failed0\n", __func__); 1876 return (-1); 1877 } 1878 rcv_mode_rsp = (q80_config_mac_rcv_mode_rsp_t *)ha->hw.mbox; 1879 1880 err = Q8_MBX_RSP_STATUS(rcv_mode_rsp->regcnt_status); 1881 1882 if (err) { 1883 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 1884 return (-1); 1885 } 1886 1887 return 0; 1888 } 1889 1890 int 1891 ql_set_promisc(qla_host_t *ha) 1892 { 1893 int ret; 1894 1895 ha->hw.mac_rcv_mode |= Q8_MBX_MAC_RCV_PROMISC_ENABLE; 1896 ret = qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode); 1897 return (ret); 1898 } 1899 1900 void 1901 qla_reset_promisc(qla_host_t *ha) 1902 { 1903 ha->hw.mac_rcv_mode &= ~Q8_MBX_MAC_RCV_PROMISC_ENABLE; 1904 (void)qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode); 1905 } 1906 1907 int 1908 ql_set_allmulti(qla_host_t *ha) 1909 { 1910 int ret; 1911 1912 ha->hw.mac_rcv_mode |= Q8_MBX_MAC_ALL_MULTI_ENABLE; 1913 ret = qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode); 1914 return (ret); 1915 } 1916 1917 void 1918 qla_reset_allmulti(qla_host_t *ha) 1919 { 1920 ha->hw.mac_rcv_mode &= ~Q8_MBX_MAC_ALL_MULTI_ENABLE; 1921 (void)qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode); 1922 } 1923 1924 /* 1925 * Name: ql_set_max_mtu 1926 * Function: 1927 * Sets the maximum transfer unit size for the specified rcv context. 1928 */ 1929 int 1930 ql_set_max_mtu(qla_host_t *ha, uint32_t mtu, uint16_t cntxt_id) 1931 { 1932 device_t dev; 1933 q80_set_max_mtu_t *max_mtu; 1934 q80_set_max_mtu_rsp_t *max_mtu_rsp; 1935 uint32_t err; 1936 1937 dev = ha->pci_dev; 1938 1939 max_mtu = (q80_set_max_mtu_t *)ha->hw.mbox; 1940 bzero(max_mtu, (sizeof (q80_set_max_mtu_t))); 1941 1942 max_mtu->opcode = Q8_MBX_SET_MAX_MTU; 1943 max_mtu->count_version = (sizeof (q80_set_max_mtu_t) >> 2); 1944 max_mtu->count_version |= Q8_MBX_CMD_VERSION; 1945 1946 max_mtu->cntxt_id = cntxt_id; 1947 max_mtu->mtu = mtu; 1948 1949 if (qla_mbx_cmd(ha, (uint32_t *)max_mtu, 1950 (sizeof (q80_set_max_mtu_t) >> 2), 1951 ha->hw.mbox, (sizeof (q80_set_max_mtu_rsp_t) >> 2), 1)) { 1952 device_printf(dev, "%s: failed\n", __func__); 1953 return -1; 1954 } 1955 1956 max_mtu_rsp = (q80_set_max_mtu_rsp_t *)ha->hw.mbox; 1957 1958 err = Q8_MBX_RSP_STATUS(max_mtu_rsp->regcnt_status); 1959 1960 if (err) { 1961 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 1962 } 1963 1964 return 0; 1965 } 1966 1967 static int 1968 qla_link_event_req(qla_host_t *ha, uint16_t cntxt_id) 1969 { 1970 device_t dev; 1971 q80_link_event_t *lnk; 1972 q80_link_event_rsp_t *lnk_rsp; 1973 uint32_t err; 1974 1975 dev = ha->pci_dev; 1976 1977 lnk = (q80_link_event_t *)ha->hw.mbox; 1978 bzero(lnk, (sizeof (q80_link_event_t))); 1979 1980 lnk->opcode = Q8_MBX_LINK_EVENT_REQ; 1981 lnk->count_version = (sizeof (q80_link_event_t) >> 2); 1982 lnk->count_version |= Q8_MBX_CMD_VERSION; 1983 1984 lnk->cntxt_id = cntxt_id; 1985 lnk->cmd = Q8_LINK_EVENT_CMD_ENABLE_ASYNC; 1986 1987 if (qla_mbx_cmd(ha, (uint32_t *)lnk, (sizeof (q80_link_event_t) >> 2), 1988 ha->hw.mbox, (sizeof (q80_link_event_rsp_t) >> 2), 0)) { 1989 device_printf(dev, "%s: failed\n", __func__); 1990 return -1; 1991 } 1992 1993 lnk_rsp = (q80_link_event_rsp_t *)ha->hw.mbox; 1994 1995 err = Q8_MBX_RSP_STATUS(lnk_rsp->regcnt_status); 1996 1997 if (err) { 1998 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 1999 } 2000 2001 return 0; 2002 } 2003 2004 static int 2005 qla_config_fw_lro(qla_host_t *ha, uint16_t cntxt_id) 2006 { 2007 device_t dev; 2008 q80_config_fw_lro_t *fw_lro; 2009 q80_config_fw_lro_rsp_t *fw_lro_rsp; 2010 uint32_t err; 2011 2012 dev = ha->pci_dev; 2013 2014 fw_lro = (q80_config_fw_lro_t *)ha->hw.mbox; 2015 bzero(fw_lro, sizeof(q80_config_fw_lro_t)); 2016 2017 fw_lro->opcode = Q8_MBX_CONFIG_FW_LRO; 2018 fw_lro->count_version = (sizeof (q80_config_fw_lro_t) >> 2); 2019 fw_lro->count_version |= Q8_MBX_CMD_VERSION; 2020 2021 fw_lro->flags |= Q8_MBX_FW_LRO_IPV4 | Q8_MBX_FW_LRO_IPV4_WO_DST_IP_CHK; 2022 fw_lro->flags |= Q8_MBX_FW_LRO_IPV6 | Q8_MBX_FW_LRO_IPV6_WO_DST_IP_CHK; 2023 2024 fw_lro->cntxt_id = cntxt_id; 2025 2026 if (qla_mbx_cmd(ha, (uint32_t *)fw_lro, 2027 (sizeof (q80_config_fw_lro_t) >> 2), 2028 ha->hw.mbox, (sizeof (q80_config_fw_lro_rsp_t) >> 2), 0)) { 2029 device_printf(dev, "%s: failed\n", __func__); 2030 return -1; 2031 } 2032 2033 fw_lro_rsp = (q80_config_fw_lro_rsp_t *)ha->hw.mbox; 2034 2035 err = Q8_MBX_RSP_STATUS(fw_lro_rsp->regcnt_status); 2036 2037 if (err) { 2038 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 2039 } 2040 2041 return 0; 2042 } 2043 2044 static int 2045 qla_set_cam_search_mode(qla_host_t *ha, uint32_t search_mode) 2046 { 2047 device_t dev; 2048 q80_hw_config_t *hw_config; 2049 q80_hw_config_rsp_t *hw_config_rsp; 2050 uint32_t err; 2051 2052 dev = ha->pci_dev; 2053 2054 hw_config = (q80_hw_config_t *)ha->hw.mbox; 2055 bzero(hw_config, sizeof (q80_hw_config_t)); 2056 2057 hw_config->opcode = Q8_MBX_HW_CONFIG; 2058 hw_config->count_version = Q8_HW_CONFIG_SET_CAM_SEARCH_MODE_COUNT; 2059 hw_config->count_version |= Q8_MBX_CMD_VERSION; 2060 2061 hw_config->cmd = Q8_HW_CONFIG_SET_CAM_SEARCH_MODE; 2062 2063 hw_config->u.set_cam_search_mode.mode = search_mode; 2064 2065 if (qla_mbx_cmd(ha, (uint32_t *)hw_config, 2066 (sizeof (q80_hw_config_t) >> 2), 2067 ha->hw.mbox, (sizeof (q80_hw_config_rsp_t) >> 2), 0)) { 2068 device_printf(dev, "%s: failed\n", __func__); 2069 return -1; 2070 } 2071 hw_config_rsp = (q80_hw_config_rsp_t *)ha->hw.mbox; 2072 2073 err = Q8_MBX_RSP_STATUS(hw_config_rsp->regcnt_status); 2074 2075 if (err) { 2076 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 2077 } 2078 2079 return 0; 2080 } 2081 2082 static int 2083 qla_get_cam_search_mode(qla_host_t *ha) 2084 { 2085 device_t dev; 2086 q80_hw_config_t *hw_config; 2087 q80_hw_config_rsp_t *hw_config_rsp; 2088 uint32_t err; 2089 2090 dev = ha->pci_dev; 2091 2092 hw_config = (q80_hw_config_t *)ha->hw.mbox; 2093 bzero(hw_config, sizeof (q80_hw_config_t)); 2094 2095 hw_config->opcode = Q8_MBX_HW_CONFIG; 2096 hw_config->count_version = Q8_HW_CONFIG_GET_CAM_SEARCH_MODE_COUNT; 2097 hw_config->count_version |= Q8_MBX_CMD_VERSION; 2098 2099 hw_config->cmd = Q8_HW_CONFIG_GET_CAM_SEARCH_MODE; 2100 2101 if (qla_mbx_cmd(ha, (uint32_t *)hw_config, 2102 (sizeof (q80_hw_config_t) >> 2), 2103 ha->hw.mbox, (sizeof (q80_hw_config_rsp_t) >> 2), 0)) { 2104 device_printf(dev, "%s: failed\n", __func__); 2105 return -1; 2106 } 2107 hw_config_rsp = (q80_hw_config_rsp_t *)ha->hw.mbox; 2108 2109 err = Q8_MBX_RSP_STATUS(hw_config_rsp->regcnt_status); 2110 2111 if (err) { 2112 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 2113 } else { 2114 device_printf(dev, "%s: cam search mode [0x%08x]\n", __func__, 2115 hw_config_rsp->u.get_cam_search_mode.mode); 2116 } 2117 2118 return 0; 2119 } 2120 2121 static int 2122 qla_get_hw_stats(qla_host_t *ha, uint32_t cmd, uint32_t rsp_size) 2123 { 2124 device_t dev; 2125 q80_get_stats_t *stat; 2126 q80_get_stats_rsp_t *stat_rsp; 2127 uint32_t err; 2128 2129 dev = ha->pci_dev; 2130 2131 stat = (q80_get_stats_t *)ha->hw.mbox; 2132 bzero(stat, (sizeof (q80_get_stats_t))); 2133 2134 stat->opcode = Q8_MBX_GET_STATS; 2135 stat->count_version = 2; 2136 stat->count_version |= Q8_MBX_CMD_VERSION; 2137 2138 stat->cmd = cmd; 2139 2140 if (qla_mbx_cmd(ha, (uint32_t *)stat, 2, 2141 ha->hw.mbox, (rsp_size >> 2), 0)) { 2142 device_printf(dev, "%s: failed\n", __func__); 2143 return -1; 2144 } 2145 2146 stat_rsp = (q80_get_stats_rsp_t *)ha->hw.mbox; 2147 2148 err = Q8_MBX_RSP_STATUS(stat_rsp->regcnt_status); 2149 2150 if (err) { 2151 return -1; 2152 } 2153 2154 return 0; 2155 } 2156 2157 void 2158 ql_get_stats(qla_host_t *ha) 2159 { 2160 q80_get_stats_rsp_t *stat_rsp; 2161 q80_mac_stats_t *mstat; 2162 q80_xmt_stats_t *xstat; 2163 q80_rcv_stats_t *rstat; 2164 uint32_t cmd; 2165 int i; 2166 if_t ifp = ha->ifp; 2167 2168 if (ifp == NULL) 2169 return; 2170 2171 if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) != 0) { 2172 device_printf(ha->pci_dev, "%s: failed\n", __func__); 2173 return; 2174 } 2175 2176 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 2177 QLA_UNLOCK(ha, __func__); 2178 return; 2179 } 2180 2181 stat_rsp = (q80_get_stats_rsp_t *)ha->hw.mbox; 2182 /* 2183 * Get MAC Statistics 2184 */ 2185 cmd = Q8_GET_STATS_CMD_TYPE_MAC; 2186 // cmd |= Q8_GET_STATS_CMD_CLEAR; 2187 2188 cmd |= ((ha->pci_func & 0x1) << 16); 2189 2190 if (ha->qla_watchdog_pause || (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) || 2191 ha->offline) 2192 goto ql_get_stats_exit; 2193 2194 if (qla_get_hw_stats(ha, cmd, sizeof (q80_get_stats_rsp_t)) == 0) { 2195 mstat = (q80_mac_stats_t *)&stat_rsp->u.mac; 2196 bcopy(mstat, &ha->hw.mac, sizeof(q80_mac_stats_t)); 2197 } else { 2198 device_printf(ha->pci_dev, "%s: mac failed [0x%08x]\n", 2199 __func__, ha->hw.mbox[0]); 2200 } 2201 /* 2202 * Get RCV Statistics 2203 */ 2204 cmd = Q8_GET_STATS_CMD_RCV | Q8_GET_STATS_CMD_TYPE_CNTXT; 2205 // cmd |= Q8_GET_STATS_CMD_CLEAR; 2206 cmd |= (ha->hw.rcv_cntxt_id << 16); 2207 2208 if (ha->qla_watchdog_pause || (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) || 2209 ha->offline) 2210 goto ql_get_stats_exit; 2211 2212 if (qla_get_hw_stats(ha, cmd, sizeof (q80_get_stats_rsp_t)) == 0) { 2213 rstat = (q80_rcv_stats_t *)&stat_rsp->u.rcv; 2214 bcopy(rstat, &ha->hw.rcv, sizeof(q80_rcv_stats_t)); 2215 } else { 2216 device_printf(ha->pci_dev, "%s: rcv failed [0x%08x]\n", 2217 __func__, ha->hw.mbox[0]); 2218 } 2219 2220 if (ha->qla_watchdog_pause || (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) || 2221 ha->offline) 2222 goto ql_get_stats_exit; 2223 /* 2224 * Get XMT Statistics 2225 */ 2226 for (i = 0 ; (i < ha->hw.num_tx_rings); i++) { 2227 if (ha->qla_watchdog_pause || 2228 (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) || 2229 ha->offline) 2230 goto ql_get_stats_exit; 2231 2232 cmd = Q8_GET_STATS_CMD_XMT | Q8_GET_STATS_CMD_TYPE_CNTXT; 2233 // cmd |= Q8_GET_STATS_CMD_CLEAR; 2234 cmd |= (ha->hw.tx_cntxt[i].tx_cntxt_id << 16); 2235 2236 if (qla_get_hw_stats(ha, cmd, sizeof(q80_get_stats_rsp_t)) 2237 == 0) { 2238 xstat = (q80_xmt_stats_t *)&stat_rsp->u.xmt; 2239 bcopy(xstat, &ha->hw.xmt[i], sizeof(q80_xmt_stats_t)); 2240 } else { 2241 device_printf(ha->pci_dev, "%s: xmt failed [0x%08x]\n", 2242 __func__, ha->hw.mbox[0]); 2243 } 2244 } 2245 2246 ql_get_stats_exit: 2247 QLA_UNLOCK(ha, __func__); 2248 2249 return; 2250 } 2251 2252 /* 2253 * Name: qla_tx_tso 2254 * Function: Checks if the packet to be transmitted is a candidate for 2255 * Large TCP Segment Offload. If yes, the appropriate fields in the Tx 2256 * Ring Structure are plugged in. 2257 */ 2258 static int 2259 qla_tx_tso(qla_host_t *ha, struct mbuf *mp, q80_tx_cmd_t *tx_cmd, uint8_t *hdr) 2260 { 2261 struct ether_vlan_header *eh; 2262 struct ip *ip = NULL; 2263 struct ip6_hdr *ip6 = NULL; 2264 struct tcphdr *th = NULL; 2265 uint32_t ehdrlen, hdrlen, ip_hlen, tcp_hlen, tcp_opt_off; 2266 uint16_t etype, opcode, offload = 1; 2267 2268 eh = mtod(mp, struct ether_vlan_header *); 2269 2270 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2271 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2272 etype = ntohs(eh->evl_proto); 2273 } else { 2274 ehdrlen = ETHER_HDR_LEN; 2275 etype = ntohs(eh->evl_encap_proto); 2276 } 2277 2278 hdrlen = 0; 2279 2280 switch (etype) { 2281 case ETHERTYPE_IP: 2282 2283 tcp_opt_off = ehdrlen + sizeof(struct ip) + 2284 sizeof(struct tcphdr); 2285 2286 if (mp->m_len < tcp_opt_off) { 2287 m_copydata(mp, 0, tcp_opt_off, hdr); 2288 ip = (struct ip *)(hdr + ehdrlen); 2289 } else { 2290 ip = (struct ip *)(mp->m_data + ehdrlen); 2291 } 2292 2293 ip_hlen = ip->ip_hl << 2; 2294 opcode = Q8_TX_CMD_OP_XMT_TCP_LSO; 2295 2296 2297 if ((ip->ip_p != IPPROTO_TCP) || 2298 (ip_hlen != sizeof (struct ip))){ 2299 /* IP Options are not supported */ 2300 2301 offload = 0; 2302 } else 2303 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 2304 2305 break; 2306 2307 case ETHERTYPE_IPV6: 2308 2309 tcp_opt_off = ehdrlen + sizeof(struct ip6_hdr) + 2310 sizeof (struct tcphdr); 2311 2312 if (mp->m_len < tcp_opt_off) { 2313 m_copydata(mp, 0, tcp_opt_off, hdr); 2314 ip6 = (struct ip6_hdr *)(hdr + ehdrlen); 2315 } else { 2316 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen); 2317 } 2318 2319 ip_hlen = sizeof(struct ip6_hdr); 2320 opcode = Q8_TX_CMD_OP_XMT_TCP_LSO_IPV6; 2321 2322 if (ip6->ip6_nxt != IPPROTO_TCP) { 2323 //device_printf(dev, "%s: ipv6\n", __func__); 2324 offload = 0; 2325 } else 2326 th = (struct tcphdr *)((caddr_t)ip6 + ip_hlen); 2327 break; 2328 2329 default: 2330 QL_DPRINT8(ha, (ha->pci_dev, "%s: type!=ip\n", __func__)); 2331 offload = 0; 2332 break; 2333 } 2334 2335 if (!offload) 2336 return (-1); 2337 2338 tcp_hlen = th->th_off << 2; 2339 hdrlen = ehdrlen + ip_hlen + tcp_hlen; 2340 2341 if (mp->m_len < hdrlen) { 2342 if (mp->m_len < tcp_opt_off) { 2343 if (tcp_hlen > sizeof(struct tcphdr)) { 2344 m_copydata(mp, tcp_opt_off, 2345 (tcp_hlen - sizeof(struct tcphdr)), 2346 &hdr[tcp_opt_off]); 2347 } 2348 } else { 2349 m_copydata(mp, 0, hdrlen, hdr); 2350 } 2351 } 2352 2353 tx_cmd->mss = mp->m_pkthdr.tso_segsz; 2354 2355 tx_cmd->flags_opcode = opcode ; 2356 tx_cmd->tcp_hdr_off = ip_hlen + ehdrlen; 2357 tx_cmd->total_hdr_len = hdrlen; 2358 2359 /* Check for Multicast least significant bit of MSB == 1 */ 2360 if (eh->evl_dhost[0] & 0x01) { 2361 tx_cmd->flags_opcode |= Q8_TX_CMD_FLAGS_MULTICAST; 2362 } 2363 2364 if (mp->m_len < hdrlen) { 2365 printf("%d\n", hdrlen); 2366 return (1); 2367 } 2368 2369 return (0); 2370 } 2371 2372 /* 2373 * Name: qla_tx_chksum 2374 * Function: Checks if the packet to be transmitted is a candidate for 2375 * TCP/UDP Checksum offload. If yes, the appropriate fields in the Tx 2376 * Ring Structure are plugged in. 2377 */ 2378 static int 2379 qla_tx_chksum(qla_host_t *ha, struct mbuf *mp, uint32_t *op_code, 2380 uint32_t *tcp_hdr_off) 2381 { 2382 struct ether_vlan_header *eh; 2383 struct ip *ip; 2384 struct ip6_hdr *ip6; 2385 uint32_t ehdrlen, ip_hlen; 2386 uint16_t etype, opcode, offload = 1; 2387 uint8_t buf[sizeof(struct ip6_hdr)]; 2388 2389 *op_code = 0; 2390 2391 if ((mp->m_pkthdr.csum_flags & 2392 (CSUM_TCP|CSUM_UDP|CSUM_TCP_IPV6 | CSUM_UDP_IPV6)) == 0) 2393 return (-1); 2394 2395 eh = mtod(mp, struct ether_vlan_header *); 2396 2397 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2398 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2399 etype = ntohs(eh->evl_proto); 2400 } else { 2401 ehdrlen = ETHER_HDR_LEN; 2402 etype = ntohs(eh->evl_encap_proto); 2403 } 2404 2405 2406 switch (etype) { 2407 case ETHERTYPE_IP: 2408 ip = (struct ip *)(mp->m_data + ehdrlen); 2409 2410 ip_hlen = sizeof (struct ip); 2411 2412 if (mp->m_len < (ehdrlen + ip_hlen)) { 2413 m_copydata(mp, ehdrlen, sizeof(struct ip), buf); 2414 ip = (struct ip *)buf; 2415 } 2416 2417 if (ip->ip_p == IPPROTO_TCP) 2418 opcode = Q8_TX_CMD_OP_XMT_TCP_CHKSUM; 2419 else if (ip->ip_p == IPPROTO_UDP) 2420 opcode = Q8_TX_CMD_OP_XMT_UDP_CHKSUM; 2421 else { 2422 //device_printf(dev, "%s: ipv4\n", __func__); 2423 offload = 0; 2424 } 2425 break; 2426 2427 case ETHERTYPE_IPV6: 2428 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen); 2429 2430 ip_hlen = sizeof(struct ip6_hdr); 2431 2432 if (mp->m_len < (ehdrlen + ip_hlen)) { 2433 m_copydata(mp, ehdrlen, sizeof (struct ip6_hdr), 2434 buf); 2435 ip6 = (struct ip6_hdr *)buf; 2436 } 2437 2438 if (ip6->ip6_nxt == IPPROTO_TCP) 2439 opcode = Q8_TX_CMD_OP_XMT_TCP_CHKSUM_IPV6; 2440 else if (ip6->ip6_nxt == IPPROTO_UDP) 2441 opcode = Q8_TX_CMD_OP_XMT_UDP_CHKSUM_IPV6; 2442 else { 2443 //device_printf(dev, "%s: ipv6\n", __func__); 2444 offload = 0; 2445 } 2446 break; 2447 2448 default: 2449 offload = 0; 2450 break; 2451 } 2452 if (!offload) 2453 return (-1); 2454 2455 *op_code = opcode; 2456 *tcp_hdr_off = (ip_hlen + ehdrlen); 2457 2458 return (0); 2459 } 2460 2461 #define QLA_TX_MIN_FREE 2 2462 /* 2463 * Name: ql_hw_send 2464 * Function: Transmits a packet. It first checks if the packet is a 2465 * candidate for Large TCP Segment Offload and then for UDP/TCP checksum 2466 * offload. If either of these creteria are not met, it is transmitted 2467 * as a regular ethernet frame. 2468 */ 2469 int 2470 ql_hw_send(qla_host_t *ha, bus_dma_segment_t *segs, int nsegs, 2471 uint32_t tx_idx, struct mbuf *mp, uint32_t txr_idx, uint32_t iscsi_pdu) 2472 { 2473 struct ether_vlan_header *eh; 2474 qla_hw_t *hw = &ha->hw; 2475 q80_tx_cmd_t *tx_cmd, tso_cmd; 2476 bus_dma_segment_t *c_seg; 2477 uint32_t num_tx_cmds, hdr_len = 0; 2478 uint32_t total_length = 0, bytes, tx_cmd_count = 0, txr_next; 2479 device_t dev; 2480 int i, ret; 2481 uint8_t *src = NULL, *dst = NULL; 2482 uint8_t frame_hdr[QL_FRAME_HDR_SIZE]; 2483 uint32_t op_code = 0; 2484 uint32_t tcp_hdr_off = 0; 2485 2486 dev = ha->pci_dev; 2487 2488 /* 2489 * Always make sure there is atleast one empty slot in the tx_ring 2490 * tx_ring is considered full when there only one entry available 2491 */ 2492 num_tx_cmds = (nsegs + (Q8_TX_CMD_MAX_SEGMENTS - 1)) >> 2; 2493 2494 total_length = mp->m_pkthdr.len; 2495 if (total_length > QLA_MAX_TSO_FRAME_SIZE) { 2496 device_printf(dev, "%s: total length exceeds maxlen(%d)\n", 2497 __func__, total_length); 2498 return (EINVAL); 2499 } 2500 eh = mtod(mp, struct ether_vlan_header *); 2501 2502 if (mp->m_pkthdr.csum_flags & CSUM_TSO) { 2503 bzero((void *)&tso_cmd, sizeof(q80_tx_cmd_t)); 2504 2505 src = frame_hdr; 2506 ret = qla_tx_tso(ha, mp, &tso_cmd, src); 2507 2508 if (!(ret & ~1)) { 2509 /* find the additional tx_cmd descriptors required */ 2510 2511 if (mp->m_flags & M_VLANTAG) 2512 tso_cmd.total_hdr_len += ETHER_VLAN_ENCAP_LEN; 2513 2514 hdr_len = tso_cmd.total_hdr_len; 2515 2516 bytes = sizeof(q80_tx_cmd_t) - Q8_TX_CMD_TSO_ALIGN; 2517 bytes = QL_MIN(bytes, hdr_len); 2518 2519 num_tx_cmds++; 2520 hdr_len -= bytes; 2521 2522 while (hdr_len) { 2523 bytes = QL_MIN((sizeof(q80_tx_cmd_t)), hdr_len); 2524 hdr_len -= bytes; 2525 num_tx_cmds++; 2526 } 2527 hdr_len = tso_cmd.total_hdr_len; 2528 2529 if (ret == 0) 2530 src = (uint8_t *)eh; 2531 } else 2532 return (EINVAL); 2533 } else { 2534 (void)qla_tx_chksum(ha, mp, &op_code, &tcp_hdr_off); 2535 } 2536 2537 if (hw->tx_cntxt[txr_idx].txr_free <= (num_tx_cmds + QLA_TX_MIN_FREE)) { 2538 ql_hw_tx_done_locked(ha, txr_idx); 2539 if (hw->tx_cntxt[txr_idx].txr_free <= 2540 (num_tx_cmds + QLA_TX_MIN_FREE)) { 2541 QL_DPRINT8(ha, (dev, "%s: (hw->txr_free <= " 2542 "(num_tx_cmds + QLA_TX_MIN_FREE))\n", 2543 __func__)); 2544 return (-1); 2545 } 2546 } 2547 2548 for (i = 0; i < num_tx_cmds; i++) { 2549 int j; 2550 2551 j = (tx_idx+i) & (NUM_TX_DESCRIPTORS - 1); 2552 2553 if (NULL != ha->tx_ring[txr_idx].tx_buf[j].m_head) { 2554 QL_ASSERT(ha, 0, \ 2555 ("%s [%d]: txr_idx = %d tx_idx = %d mbuf = %p\n",\ 2556 __func__, __LINE__, txr_idx, j,\ 2557 ha->tx_ring[txr_idx].tx_buf[j].m_head)); 2558 return (EINVAL); 2559 } 2560 } 2561 2562 tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[tx_idx]; 2563 2564 if (!(mp->m_pkthdr.csum_flags & CSUM_TSO)) { 2565 if (nsegs > ha->hw.max_tx_segs) 2566 ha->hw.max_tx_segs = nsegs; 2567 2568 bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t)); 2569 2570 if (op_code) { 2571 tx_cmd->flags_opcode = op_code; 2572 tx_cmd->tcp_hdr_off = tcp_hdr_off; 2573 2574 } else { 2575 tx_cmd->flags_opcode = Q8_TX_CMD_OP_XMT_ETHER; 2576 } 2577 } else { 2578 bcopy(&tso_cmd, tx_cmd, sizeof(q80_tx_cmd_t)); 2579 ha->tx_tso_frames++; 2580 } 2581 2582 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2583 tx_cmd->flags_opcode |= Q8_TX_CMD_FLAGS_VLAN_TAGGED; 2584 2585 if (iscsi_pdu) 2586 eh->evl_tag |= ha->hw.user_pri_iscsi << 13; 2587 2588 } else if (mp->m_flags & M_VLANTAG) { 2589 if (hdr_len) { /* TSO */ 2590 tx_cmd->flags_opcode |= (Q8_TX_CMD_FLAGS_VLAN_TAGGED | 2591 Q8_TX_CMD_FLAGS_HW_VLAN_ID); 2592 tx_cmd->tcp_hdr_off += ETHER_VLAN_ENCAP_LEN; 2593 } else 2594 tx_cmd->flags_opcode |= Q8_TX_CMD_FLAGS_HW_VLAN_ID; 2595 2596 ha->hw_vlan_tx_frames++; 2597 tx_cmd->vlan_tci = mp->m_pkthdr.ether_vtag; 2598 2599 if (iscsi_pdu) { 2600 tx_cmd->vlan_tci |= ha->hw.user_pri_iscsi << 13; 2601 mp->m_pkthdr.ether_vtag = tx_cmd->vlan_tci; 2602 } 2603 } 2604 2605 tx_cmd->n_bufs = (uint8_t)nsegs; 2606 tx_cmd->data_len_lo = (uint8_t)(total_length & 0xFF); 2607 tx_cmd->data_len_hi = qla_host_to_le16(((uint16_t)(total_length >> 8))); 2608 tx_cmd->cntxtid = Q8_TX_CMD_PORT_CNXTID(ha->pci_func); 2609 2610 c_seg = segs; 2611 2612 while (1) { 2613 for (i = 0; ((i < Q8_TX_CMD_MAX_SEGMENTS) && nsegs); i++) { 2614 switch (i) { 2615 case 0: 2616 tx_cmd->buf1_addr = c_seg->ds_addr; 2617 tx_cmd->buf1_len = c_seg->ds_len; 2618 break; 2619 2620 case 1: 2621 tx_cmd->buf2_addr = c_seg->ds_addr; 2622 tx_cmd->buf2_len = c_seg->ds_len; 2623 break; 2624 2625 case 2: 2626 tx_cmd->buf3_addr = c_seg->ds_addr; 2627 tx_cmd->buf3_len = c_seg->ds_len; 2628 break; 2629 2630 case 3: 2631 tx_cmd->buf4_addr = c_seg->ds_addr; 2632 tx_cmd->buf4_len = c_seg->ds_len; 2633 break; 2634 } 2635 2636 c_seg++; 2637 nsegs--; 2638 } 2639 2640 txr_next = hw->tx_cntxt[txr_idx].txr_next = 2641 (hw->tx_cntxt[txr_idx].txr_next + 1) & 2642 (NUM_TX_DESCRIPTORS - 1); 2643 tx_cmd_count++; 2644 2645 if (!nsegs) 2646 break; 2647 2648 tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[txr_next]; 2649 bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t)); 2650 } 2651 2652 if (mp->m_pkthdr.csum_flags & CSUM_TSO) { 2653 /* TSO : Copy the header in the following tx cmd descriptors */ 2654 2655 txr_next = hw->tx_cntxt[txr_idx].txr_next; 2656 2657 tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[txr_next]; 2658 bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t)); 2659 2660 bytes = sizeof(q80_tx_cmd_t) - Q8_TX_CMD_TSO_ALIGN; 2661 bytes = QL_MIN(bytes, hdr_len); 2662 2663 dst = (uint8_t *)tx_cmd + Q8_TX_CMD_TSO_ALIGN; 2664 2665 if (mp->m_flags & M_VLANTAG) { 2666 /* first copy the src/dst MAC addresses */ 2667 bcopy(src, dst, (ETHER_ADDR_LEN * 2)); 2668 dst += (ETHER_ADDR_LEN * 2); 2669 src += (ETHER_ADDR_LEN * 2); 2670 2671 *((uint16_t *)dst) = htons(ETHERTYPE_VLAN); 2672 dst += 2; 2673 *((uint16_t *)dst) = htons(mp->m_pkthdr.ether_vtag); 2674 dst += 2; 2675 2676 /* bytes left in src header */ 2677 hdr_len -= ((ETHER_ADDR_LEN * 2) + 2678 ETHER_VLAN_ENCAP_LEN); 2679 2680 /* bytes left in TxCmd Entry */ 2681 bytes -= ((ETHER_ADDR_LEN * 2) + ETHER_VLAN_ENCAP_LEN); 2682 2683 bcopy(src, dst, bytes); 2684 src += bytes; 2685 hdr_len -= bytes; 2686 } else { 2687 bcopy(src, dst, bytes); 2688 src += bytes; 2689 hdr_len -= bytes; 2690 } 2691 2692 txr_next = hw->tx_cntxt[txr_idx].txr_next = 2693 (hw->tx_cntxt[txr_idx].txr_next + 1) & 2694 (NUM_TX_DESCRIPTORS - 1); 2695 tx_cmd_count++; 2696 2697 while (hdr_len) { 2698 tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[txr_next]; 2699 bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t)); 2700 2701 bytes = QL_MIN((sizeof(q80_tx_cmd_t)), hdr_len); 2702 2703 bcopy(src, tx_cmd, bytes); 2704 src += bytes; 2705 hdr_len -= bytes; 2706 2707 txr_next = hw->tx_cntxt[txr_idx].txr_next = 2708 (hw->tx_cntxt[txr_idx].txr_next + 1) & 2709 (NUM_TX_DESCRIPTORS - 1); 2710 tx_cmd_count++; 2711 } 2712 } 2713 2714 hw->tx_cntxt[txr_idx].txr_free = 2715 hw->tx_cntxt[txr_idx].txr_free - tx_cmd_count; 2716 2717 QL_UPDATE_TX_PRODUCER_INDEX(ha, hw->tx_cntxt[txr_idx].txr_next,\ 2718 txr_idx); 2719 QL_DPRINT8(ha, (dev, "%s: return\n", __func__)); 2720 2721 return (0); 2722 } 2723 2724 #define Q8_CONFIG_IND_TBL_SIZE 32 /* < Q8_RSS_IND_TBL_SIZE and power of 2 */ 2725 static int 2726 qla_config_rss_ind_table(qla_host_t *ha) 2727 { 2728 uint32_t i, count; 2729 uint8_t rss_ind_tbl[Q8_CONFIG_IND_TBL_SIZE]; 2730 2731 for (i = 0; i < Q8_CONFIG_IND_TBL_SIZE; i++) { 2732 rss_ind_tbl[i] = i % ha->hw.num_sds_rings; 2733 } 2734 2735 for (i = 0; i <= Q8_RSS_IND_TBL_MAX_IDX ; 2736 i = i + Q8_CONFIG_IND_TBL_SIZE) { 2737 if ((i + Q8_CONFIG_IND_TBL_SIZE) > Q8_RSS_IND_TBL_MAX_IDX) { 2738 count = Q8_RSS_IND_TBL_MAX_IDX - i + 1; 2739 } else { 2740 count = Q8_CONFIG_IND_TBL_SIZE; 2741 } 2742 2743 if (qla_set_rss_ind_table(ha, i, count, ha->hw.rcv_cntxt_id, 2744 rss_ind_tbl)) 2745 return (-1); 2746 } 2747 2748 return (0); 2749 } 2750 2751 static int 2752 qla_config_soft_lro(qla_host_t *ha) 2753 { 2754 #if defined(INET) || defined(INET6) 2755 int i; 2756 qla_hw_t *hw = &ha->hw; 2757 struct lro_ctrl *lro; 2758 2759 for (i = 0; i < hw->num_sds_rings; i++) { 2760 lro = &hw->sds[i].lro; 2761 2762 bzero(lro, sizeof(struct lro_ctrl)); 2763 2764 if (tcp_lro_init_args(lro, ha->ifp, 0, NUM_RX_DESCRIPTORS)) { 2765 device_printf(ha->pci_dev, 2766 "%s: tcp_lro_init_args [%d] failed\n", 2767 __func__, i); 2768 return (-1); 2769 } 2770 2771 lro->ifp = ha->ifp; 2772 } 2773 2774 QL_DPRINT2(ha, (ha->pci_dev, "%s: LRO initialized\n", __func__)); 2775 #endif 2776 return (0); 2777 } 2778 2779 static void 2780 qla_drain_soft_lro(qla_host_t *ha) 2781 { 2782 #if defined(INET) || defined(INET6) 2783 int i; 2784 qla_hw_t *hw = &ha->hw; 2785 struct lro_ctrl *lro; 2786 2787 for (i = 0; i < hw->num_sds_rings; i++) { 2788 lro = &hw->sds[i].lro; 2789 2790 tcp_lro_flush_all(lro); 2791 } 2792 #endif 2793 2794 return; 2795 } 2796 2797 static void 2798 qla_free_soft_lro(qla_host_t *ha) 2799 { 2800 #if defined(INET) || defined(INET6) 2801 int i; 2802 qla_hw_t *hw = &ha->hw; 2803 struct lro_ctrl *lro; 2804 2805 for (i = 0; i < hw->num_sds_rings; i++) { 2806 lro = &hw->sds[i].lro; 2807 tcp_lro_free(lro); 2808 } 2809 #endif 2810 2811 return; 2812 } 2813 2814 /* 2815 * Name: ql_del_hw_if 2816 * Function: Destroys the hardware specific entities corresponding to an 2817 * Ethernet Interface 2818 */ 2819 void 2820 ql_del_hw_if(qla_host_t *ha) 2821 { 2822 uint32_t i; 2823 uint32_t num_msix; 2824 2825 (void)qla_stop_nic_func(ha); 2826 2827 qla_del_rcv_cntxt(ha); 2828 2829 if(qla_del_xmt_cntxt(ha)) 2830 goto ql_del_hw_if_exit; 2831 2832 if (ha->hw.flags.init_intr_cnxt) { 2833 for (i = 0; i < ha->hw.num_sds_rings; ) { 2834 if ((i + Q8_MAX_INTR_VECTORS) < ha->hw.num_sds_rings) 2835 num_msix = Q8_MAX_INTR_VECTORS; 2836 else 2837 num_msix = ha->hw.num_sds_rings - i; 2838 2839 if (qla_config_intr_cntxt(ha, i, num_msix, 0)) 2840 break; 2841 2842 i += num_msix; 2843 } 2844 2845 ha->hw.flags.init_intr_cnxt = 0; 2846 } 2847 2848 ql_del_hw_if_exit: 2849 if (ha->hw.enable_soft_lro) { 2850 qla_drain_soft_lro(ha); 2851 qla_free_soft_lro(ha); 2852 } 2853 2854 return; 2855 } 2856 2857 void 2858 qla_confirm_9kb_enable(qla_host_t *ha) 2859 { 2860 // uint32_t supports_9kb = 0; 2861 2862 ha->hw.mbx_intr_mask_offset = READ_REG32(ha, Q8_MBOX_INT_MASK_MSIX); 2863 2864 /* Use MSI-X vector 0; Enable Firmware Mailbox Interrupt */ 2865 WRITE_REG32(ha, Q8_MBOX_INT_ENABLE, BIT_2); 2866 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0); 2867 2868 #if 0 2869 qla_get_nic_partition(ha, &supports_9kb, NULL); 2870 2871 if (!supports_9kb) 2872 #endif 2873 ha->hw.enable_9kb = 0; 2874 2875 return; 2876 } 2877 2878 /* 2879 * Name: ql_init_hw_if 2880 * Function: Creates the hardware specific entities corresponding to an 2881 * Ethernet Interface - Transmit and Receive Contexts. Sets the MAC Address 2882 * corresponding to the interface. Enables LRO if allowed. 2883 */ 2884 int 2885 ql_init_hw_if(qla_host_t *ha) 2886 { 2887 uint32_t i; 2888 uint8_t bcast_mac[6]; 2889 qla_rdesc_t *rdesc; 2890 uint32_t num_msix; 2891 2892 for (i = 0; i < ha->hw.num_sds_rings; i++) { 2893 bzero(ha->hw.dma_buf.sds_ring[i].dma_b, 2894 ha->hw.dma_buf.sds_ring[i].size); 2895 } 2896 2897 for (i = 0; i < ha->hw.num_sds_rings; ) { 2898 if ((i + Q8_MAX_INTR_VECTORS) < ha->hw.num_sds_rings) 2899 num_msix = Q8_MAX_INTR_VECTORS; 2900 else 2901 num_msix = ha->hw.num_sds_rings - i; 2902 2903 if (qla_config_intr_cntxt(ha, i, num_msix, 1)) { 2904 if (i > 0) { 2905 num_msix = i; 2906 2907 for (i = 0; i < num_msix; ) { 2908 qla_config_intr_cntxt(ha, i, 2909 Q8_MAX_INTR_VECTORS, 0); 2910 i += Q8_MAX_INTR_VECTORS; 2911 } 2912 } 2913 return (-1); 2914 } 2915 2916 i = i + num_msix; 2917 } 2918 2919 ha->hw.flags.init_intr_cnxt = 1; 2920 2921 /* 2922 * Create Receive Context 2923 */ 2924 if (qla_init_rcv_cntxt(ha)) { 2925 return (-1); 2926 } 2927 2928 for (i = 0; i < ha->hw.num_rds_rings; i++) { 2929 rdesc = &ha->hw.rds[i]; 2930 rdesc->rx_next = NUM_RX_DESCRIPTORS - 2; 2931 rdesc->rx_in = 0; 2932 /* Update the RDS Producer Indices */ 2933 QL_UPDATE_RDS_PRODUCER_INDEX(ha, rdesc->prod_std,\ 2934 rdesc->rx_next); 2935 } 2936 2937 /* 2938 * Create Transmit Context 2939 */ 2940 if (qla_init_xmt_cntxt(ha)) { 2941 qla_del_rcv_cntxt(ha); 2942 return (-1); 2943 } 2944 ha->hw.max_tx_segs = 0; 2945 2946 if (qla_config_mac_addr(ha, ha->hw.mac_addr, 1, 1)) 2947 return(-1); 2948 2949 ha->hw.flags.unicast_mac = 1; 2950 2951 bcast_mac[0] = 0xFF; bcast_mac[1] = 0xFF; bcast_mac[2] = 0xFF; 2952 bcast_mac[3] = 0xFF; bcast_mac[4] = 0xFF; bcast_mac[5] = 0xFF; 2953 2954 if (qla_config_mac_addr(ha, bcast_mac, 1, 1)) 2955 return (-1); 2956 2957 ha->hw.flags.bcast_mac = 1; 2958 2959 /* 2960 * program any cached multicast addresses 2961 */ 2962 if (qla_hw_add_all_mcast(ha)) 2963 return (-1); 2964 2965 if (ql_set_max_mtu(ha, ha->max_frame_size, ha->hw.rcv_cntxt_id)) 2966 return (-1); 2967 2968 if (qla_config_rss(ha, ha->hw.rcv_cntxt_id)) 2969 return (-1); 2970 2971 if (qla_config_rss_ind_table(ha)) 2972 return (-1); 2973 2974 if (qla_config_intr_coalesce(ha, ha->hw.rcv_cntxt_id, 0, 1)) 2975 return (-1); 2976 2977 if (qla_link_event_req(ha, ha->hw.rcv_cntxt_id)) 2978 return (-1); 2979 2980 if (if_getcapenable(ha->ifp) & IFCAP_LRO) { 2981 if (ha->hw.enable_hw_lro) { 2982 ha->hw.enable_soft_lro = 0; 2983 2984 if (qla_config_fw_lro(ha, ha->hw.rcv_cntxt_id)) 2985 return (-1); 2986 } else { 2987 ha->hw.enable_soft_lro = 1; 2988 2989 if (qla_config_soft_lro(ha)) 2990 return (-1); 2991 } 2992 } 2993 2994 if (qla_init_nic_func(ha)) 2995 return (-1); 2996 2997 if (qla_query_fw_dcbx_caps(ha)) 2998 return (-1); 2999 3000 for (i = 0; i < ha->hw.num_sds_rings; i++) 3001 QL_ENABLE_INTERRUPTS(ha, i); 3002 3003 return (0); 3004 } 3005 3006 static int 3007 qla_map_sds_to_rds(qla_host_t *ha, uint32_t start_idx, uint32_t num_idx) 3008 { 3009 device_t dev = ha->pci_dev; 3010 q80_rq_map_sds_to_rds_t *map_rings; 3011 q80_rsp_map_sds_to_rds_t *map_rings_rsp; 3012 uint32_t i, err; 3013 qla_hw_t *hw = &ha->hw; 3014 3015 map_rings = (q80_rq_map_sds_to_rds_t *)ha->hw.mbox; 3016 bzero(map_rings, sizeof(q80_rq_map_sds_to_rds_t)); 3017 3018 map_rings->opcode = Q8_MBX_MAP_SDS_TO_RDS; 3019 map_rings->count_version = (sizeof (q80_rq_map_sds_to_rds_t) >> 2); 3020 map_rings->count_version |= Q8_MBX_CMD_VERSION; 3021 3022 map_rings->cntxt_id = hw->rcv_cntxt_id; 3023 map_rings->num_rings = num_idx; 3024 3025 for (i = 0; i < num_idx; i++) { 3026 map_rings->sds_rds[i].sds_ring = i + start_idx; 3027 map_rings->sds_rds[i].rds_ring = i + start_idx; 3028 } 3029 3030 if (qla_mbx_cmd(ha, (uint32_t *)map_rings, 3031 (sizeof (q80_rq_map_sds_to_rds_t) >> 2), 3032 ha->hw.mbox, (sizeof(q80_rsp_add_rcv_rings_t) >> 2), 0)) { 3033 device_printf(dev, "%s: failed0\n", __func__); 3034 return (-1); 3035 } 3036 3037 map_rings_rsp = (q80_rsp_map_sds_to_rds_t *)ha->hw.mbox; 3038 3039 err = Q8_MBX_RSP_STATUS(map_rings_rsp->regcnt_status); 3040 3041 if (err) { 3042 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 3043 return (-1); 3044 } 3045 3046 return (0); 3047 } 3048 3049 /* 3050 * Name: qla_init_rcv_cntxt 3051 * Function: Creates the Receive Context. 3052 */ 3053 static int 3054 qla_init_rcv_cntxt(qla_host_t *ha) 3055 { 3056 q80_rq_rcv_cntxt_t *rcntxt; 3057 q80_rsp_rcv_cntxt_t *rcntxt_rsp; 3058 q80_stat_desc_t *sdesc; 3059 int i, j; 3060 qla_hw_t *hw = &ha->hw; 3061 device_t dev; 3062 uint32_t err; 3063 uint32_t rcntxt_sds_rings; 3064 uint32_t rcntxt_rds_rings; 3065 uint32_t max_idx; 3066 3067 dev = ha->pci_dev; 3068 3069 /* 3070 * Create Receive Context 3071 */ 3072 3073 for (i = 0; i < hw->num_sds_rings; i++) { 3074 sdesc = (q80_stat_desc_t *)&hw->sds[i].sds_ring_base[0]; 3075 3076 for (j = 0; j < NUM_STATUS_DESCRIPTORS; j++) { 3077 sdesc->data[0] = 1ULL; 3078 sdesc->data[1] = 1ULL; 3079 } 3080 } 3081 3082 rcntxt_sds_rings = hw->num_sds_rings; 3083 if (hw->num_sds_rings > MAX_RCNTXT_SDS_RINGS) 3084 rcntxt_sds_rings = MAX_RCNTXT_SDS_RINGS; 3085 3086 rcntxt_rds_rings = hw->num_rds_rings; 3087 3088 if (hw->num_rds_rings > MAX_RDS_RING_SETS) 3089 rcntxt_rds_rings = MAX_RDS_RING_SETS; 3090 3091 rcntxt = (q80_rq_rcv_cntxt_t *)ha->hw.mbox; 3092 bzero(rcntxt, (sizeof (q80_rq_rcv_cntxt_t))); 3093 3094 rcntxt->opcode = Q8_MBX_CREATE_RX_CNTXT; 3095 rcntxt->count_version = (sizeof (q80_rq_rcv_cntxt_t) >> 2); 3096 rcntxt->count_version |= Q8_MBX_CMD_VERSION; 3097 3098 rcntxt->cap0 = Q8_RCV_CNTXT_CAP0_BASEFW | 3099 Q8_RCV_CNTXT_CAP0_LRO | 3100 Q8_RCV_CNTXT_CAP0_HW_LRO | 3101 Q8_RCV_CNTXT_CAP0_RSS | 3102 Q8_RCV_CNTXT_CAP0_SGL_LRO; 3103 3104 if (ha->hw.enable_9kb) 3105 rcntxt->cap0 |= Q8_RCV_CNTXT_CAP0_SINGLE_JUMBO; 3106 else 3107 rcntxt->cap0 |= Q8_RCV_CNTXT_CAP0_SGL_JUMBO; 3108 3109 if (ha->hw.num_rds_rings > 1) { 3110 rcntxt->nrds_sets_rings = rcntxt_rds_rings | (1 << 5); 3111 rcntxt->cap0 |= Q8_RCV_CNTXT_CAP0_MULTI_RDS; 3112 } else 3113 rcntxt->nrds_sets_rings = 0x1 | (1 << 5); 3114 3115 rcntxt->nsds_rings = rcntxt_sds_rings; 3116 3117 rcntxt->rds_producer_mode = Q8_RCV_CNTXT_RDS_PROD_MODE_UNIQUE; 3118 3119 rcntxt->rcv_vpid = 0; 3120 3121 for (i = 0; i < rcntxt_sds_rings; i++) { 3122 rcntxt->sds[i].paddr = 3123 qla_host_to_le64(hw->dma_buf.sds_ring[i].dma_addr); 3124 rcntxt->sds[i].size = 3125 qla_host_to_le32(NUM_STATUS_DESCRIPTORS); 3126 rcntxt->sds[i].intr_id = qla_host_to_le16(hw->intr_id[i]); 3127 rcntxt->sds[i].intr_src_bit = qla_host_to_le16(0); 3128 } 3129 3130 for (i = 0; i < rcntxt_rds_rings; i++) { 3131 rcntxt->rds[i].paddr_std = 3132 qla_host_to_le64(hw->dma_buf.rds_ring[i].dma_addr); 3133 3134 if (ha->hw.enable_9kb) 3135 rcntxt->rds[i].std_bsize = 3136 qla_host_to_le64(MJUM9BYTES); 3137 else 3138 rcntxt->rds[i].std_bsize = qla_host_to_le64(MCLBYTES); 3139 3140 rcntxt->rds[i].std_nentries = 3141 qla_host_to_le32(NUM_RX_DESCRIPTORS); 3142 } 3143 3144 if (qla_mbx_cmd(ha, (uint32_t *)rcntxt, 3145 (sizeof (q80_rq_rcv_cntxt_t) >> 2), 3146 ha->hw.mbox, (sizeof(q80_rsp_rcv_cntxt_t) >> 2), 0)) { 3147 device_printf(dev, "%s: failed0\n", __func__); 3148 return (-1); 3149 } 3150 3151 rcntxt_rsp = (q80_rsp_rcv_cntxt_t *)ha->hw.mbox; 3152 3153 err = Q8_MBX_RSP_STATUS(rcntxt_rsp->regcnt_status); 3154 3155 if (err) { 3156 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 3157 return (-1); 3158 } 3159 3160 for (i = 0; i < rcntxt_sds_rings; i++) { 3161 hw->sds[i].sds_consumer = rcntxt_rsp->sds_cons[i]; 3162 } 3163 3164 for (i = 0; i < rcntxt_rds_rings; i++) { 3165 hw->rds[i].prod_std = rcntxt_rsp->rds[i].prod_std; 3166 } 3167 3168 hw->rcv_cntxt_id = rcntxt_rsp->cntxt_id; 3169 3170 ha->hw.flags.init_rx_cnxt = 1; 3171 3172 if (hw->num_sds_rings > MAX_RCNTXT_SDS_RINGS) { 3173 for (i = MAX_RCNTXT_SDS_RINGS; i < hw->num_sds_rings;) { 3174 if ((i + MAX_RCNTXT_SDS_RINGS) < hw->num_sds_rings) 3175 max_idx = MAX_RCNTXT_SDS_RINGS; 3176 else 3177 max_idx = hw->num_sds_rings - i; 3178 3179 err = qla_add_rcv_rings(ha, i, max_idx); 3180 if (err) 3181 return -1; 3182 3183 i += max_idx; 3184 } 3185 } 3186 3187 if (hw->num_rds_rings > 1) { 3188 for (i = 0; i < hw->num_rds_rings; ) { 3189 if ((i + MAX_SDS_TO_RDS_MAP) < hw->num_rds_rings) 3190 max_idx = MAX_SDS_TO_RDS_MAP; 3191 else 3192 max_idx = hw->num_rds_rings - i; 3193 3194 err = qla_map_sds_to_rds(ha, i, max_idx); 3195 if (err) 3196 return -1; 3197 3198 i += max_idx; 3199 } 3200 } 3201 3202 return (0); 3203 } 3204 3205 static int 3206 qla_add_rcv_rings(qla_host_t *ha, uint32_t sds_idx, uint32_t nsds) 3207 { 3208 device_t dev = ha->pci_dev; 3209 q80_rq_add_rcv_rings_t *add_rcv; 3210 q80_rsp_add_rcv_rings_t *add_rcv_rsp; 3211 uint32_t i,j, err; 3212 qla_hw_t *hw = &ha->hw; 3213 3214 add_rcv = (q80_rq_add_rcv_rings_t *)ha->hw.mbox; 3215 bzero(add_rcv, sizeof (q80_rq_add_rcv_rings_t)); 3216 3217 add_rcv->opcode = Q8_MBX_ADD_RX_RINGS; 3218 add_rcv->count_version = (sizeof (q80_rq_add_rcv_rings_t) >> 2); 3219 add_rcv->count_version |= Q8_MBX_CMD_VERSION; 3220 3221 add_rcv->nrds_sets_rings = nsds | (1 << 5); 3222 add_rcv->nsds_rings = nsds; 3223 add_rcv->cntxt_id = hw->rcv_cntxt_id; 3224 3225 for (i = 0; i < nsds; i++) { 3226 j = i + sds_idx; 3227 3228 add_rcv->sds[i].paddr = 3229 qla_host_to_le64(hw->dma_buf.sds_ring[j].dma_addr); 3230 3231 add_rcv->sds[i].size = 3232 qla_host_to_le32(NUM_STATUS_DESCRIPTORS); 3233 3234 add_rcv->sds[i].intr_id = qla_host_to_le16(hw->intr_id[j]); 3235 add_rcv->sds[i].intr_src_bit = qla_host_to_le16(0); 3236 } 3237 3238 for (i = 0; (i < nsds); i++) { 3239 j = i + sds_idx; 3240 3241 add_rcv->rds[i].paddr_std = 3242 qla_host_to_le64(hw->dma_buf.rds_ring[j].dma_addr); 3243 3244 if (ha->hw.enable_9kb) 3245 add_rcv->rds[i].std_bsize = 3246 qla_host_to_le64(MJUM9BYTES); 3247 else 3248 add_rcv->rds[i].std_bsize = qla_host_to_le64(MCLBYTES); 3249 3250 add_rcv->rds[i].std_nentries = 3251 qla_host_to_le32(NUM_RX_DESCRIPTORS); 3252 } 3253 3254 if (qla_mbx_cmd(ha, (uint32_t *)add_rcv, 3255 (sizeof (q80_rq_add_rcv_rings_t) >> 2), 3256 ha->hw.mbox, (sizeof(q80_rsp_add_rcv_rings_t) >> 2), 0)) { 3257 device_printf(dev, "%s: failed0\n", __func__); 3258 return (-1); 3259 } 3260 3261 add_rcv_rsp = (q80_rsp_add_rcv_rings_t *)ha->hw.mbox; 3262 3263 err = Q8_MBX_RSP_STATUS(add_rcv_rsp->regcnt_status); 3264 3265 if (err) { 3266 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 3267 return (-1); 3268 } 3269 3270 for (i = 0; i < nsds; i++) { 3271 hw->sds[(i + sds_idx)].sds_consumer = add_rcv_rsp->sds_cons[i]; 3272 } 3273 3274 for (i = 0; i < nsds; i++) { 3275 hw->rds[(i + sds_idx)].prod_std = add_rcv_rsp->rds[i].prod_std; 3276 } 3277 3278 return (0); 3279 } 3280 3281 /* 3282 * Name: qla_del_rcv_cntxt 3283 * Function: Destroys the Receive Context. 3284 */ 3285 static void 3286 qla_del_rcv_cntxt(qla_host_t *ha) 3287 { 3288 device_t dev = ha->pci_dev; 3289 q80_rcv_cntxt_destroy_t *rcntxt; 3290 q80_rcv_cntxt_destroy_rsp_t *rcntxt_rsp; 3291 uint32_t err; 3292 uint8_t bcast_mac[6]; 3293 3294 if (!ha->hw.flags.init_rx_cnxt) 3295 return; 3296 3297 if (qla_hw_del_all_mcast(ha)) 3298 return; 3299 3300 if (ha->hw.flags.bcast_mac) { 3301 bcast_mac[0] = 0xFF; bcast_mac[1] = 0xFF; bcast_mac[2] = 0xFF; 3302 bcast_mac[3] = 0xFF; bcast_mac[4] = 0xFF; bcast_mac[5] = 0xFF; 3303 3304 if (qla_config_mac_addr(ha, bcast_mac, 0, 1)) 3305 return; 3306 ha->hw.flags.bcast_mac = 0; 3307 } 3308 3309 if (ha->hw.flags.unicast_mac) { 3310 if (qla_config_mac_addr(ha, ha->hw.mac_addr, 0, 1)) 3311 return; 3312 ha->hw.flags.unicast_mac = 0; 3313 } 3314 3315 rcntxt = (q80_rcv_cntxt_destroy_t *)ha->hw.mbox; 3316 bzero(rcntxt, (sizeof (q80_rcv_cntxt_destroy_t))); 3317 3318 rcntxt->opcode = Q8_MBX_DESTROY_RX_CNTXT; 3319 rcntxt->count_version = (sizeof (q80_rcv_cntxt_destroy_t) >> 2); 3320 rcntxt->count_version |= Q8_MBX_CMD_VERSION; 3321 3322 rcntxt->cntxt_id = ha->hw.rcv_cntxt_id; 3323 3324 if (qla_mbx_cmd(ha, (uint32_t *)rcntxt, 3325 (sizeof (q80_rcv_cntxt_destroy_t) >> 2), 3326 ha->hw.mbox, (sizeof(q80_rcv_cntxt_destroy_rsp_t) >> 2), 0)) { 3327 device_printf(dev, "%s: failed0\n", __func__); 3328 return; 3329 } 3330 rcntxt_rsp = (q80_rcv_cntxt_destroy_rsp_t *)ha->hw.mbox; 3331 3332 err = Q8_MBX_RSP_STATUS(rcntxt_rsp->regcnt_status); 3333 3334 if (err) { 3335 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 3336 } 3337 3338 ha->hw.flags.init_rx_cnxt = 0; 3339 return; 3340 } 3341 3342 /* 3343 * Name: qla_init_xmt_cntxt 3344 * Function: Creates the Transmit Context. 3345 */ 3346 static int 3347 qla_init_xmt_cntxt_i(qla_host_t *ha, uint32_t txr_idx) 3348 { 3349 device_t dev; 3350 qla_hw_t *hw = &ha->hw; 3351 q80_rq_tx_cntxt_t *tcntxt; 3352 q80_rsp_tx_cntxt_t *tcntxt_rsp; 3353 uint32_t err; 3354 qla_hw_tx_cntxt_t *hw_tx_cntxt; 3355 uint32_t intr_idx; 3356 3357 hw_tx_cntxt = &hw->tx_cntxt[txr_idx]; 3358 3359 dev = ha->pci_dev; 3360 3361 /* 3362 * Create Transmit Context 3363 */ 3364 tcntxt = (q80_rq_tx_cntxt_t *)ha->hw.mbox; 3365 bzero(tcntxt, (sizeof (q80_rq_tx_cntxt_t))); 3366 3367 tcntxt->opcode = Q8_MBX_CREATE_TX_CNTXT; 3368 tcntxt->count_version = (sizeof (q80_rq_tx_cntxt_t) >> 2); 3369 tcntxt->count_version |= Q8_MBX_CMD_VERSION; 3370 3371 intr_idx = txr_idx; 3372 3373 #ifdef QL_ENABLE_ISCSI_TLV 3374 3375 tcntxt->cap0 = Q8_TX_CNTXT_CAP0_BASEFW | Q8_TX_CNTXT_CAP0_LSO | 3376 Q8_TX_CNTXT_CAP0_TC; 3377 3378 if (txr_idx >= (ha->hw.num_tx_rings >> 1)) { 3379 tcntxt->traffic_class = 1; 3380 } 3381 3382 intr_idx = txr_idx % (ha->hw.num_tx_rings >> 1); 3383 3384 #else 3385 tcntxt->cap0 = Q8_TX_CNTXT_CAP0_BASEFW | Q8_TX_CNTXT_CAP0_LSO; 3386 3387 #endif /* #ifdef QL_ENABLE_ISCSI_TLV */ 3388 3389 tcntxt->ntx_rings = 1; 3390 3391 tcntxt->tx_ring[0].paddr = 3392 qla_host_to_le64(hw_tx_cntxt->tx_ring_paddr); 3393 tcntxt->tx_ring[0].tx_consumer = 3394 qla_host_to_le64(hw_tx_cntxt->tx_cons_paddr); 3395 tcntxt->tx_ring[0].nentries = qla_host_to_le16(NUM_TX_DESCRIPTORS); 3396 3397 tcntxt->tx_ring[0].intr_id = qla_host_to_le16(hw->intr_id[intr_idx]); 3398 tcntxt->tx_ring[0].intr_src_bit = qla_host_to_le16(0); 3399 3400 hw_tx_cntxt->txr_free = NUM_TX_DESCRIPTORS; 3401 hw_tx_cntxt->txr_next = hw_tx_cntxt->txr_comp = 0; 3402 *(hw_tx_cntxt->tx_cons) = 0; 3403 3404 if (qla_mbx_cmd(ha, (uint32_t *)tcntxt, 3405 (sizeof (q80_rq_tx_cntxt_t) >> 2), 3406 ha->hw.mbox, 3407 (sizeof(q80_rsp_tx_cntxt_t) >> 2), 0)) { 3408 device_printf(dev, "%s: failed0\n", __func__); 3409 return (-1); 3410 } 3411 tcntxt_rsp = (q80_rsp_tx_cntxt_t *)ha->hw.mbox; 3412 3413 err = Q8_MBX_RSP_STATUS(tcntxt_rsp->regcnt_status); 3414 3415 if (err) { 3416 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 3417 return -1; 3418 } 3419 3420 hw_tx_cntxt->tx_prod_reg = tcntxt_rsp->tx_ring[0].prod_index; 3421 hw_tx_cntxt->tx_cntxt_id = tcntxt_rsp->tx_ring[0].cntxt_id; 3422 3423 if (qla_config_intr_coalesce(ha, hw_tx_cntxt->tx_cntxt_id, 0, 0)) 3424 return (-1); 3425 3426 return (0); 3427 } 3428 3429 /* 3430 * Name: qla_del_xmt_cntxt 3431 * Function: Destroys the Transmit Context. 3432 */ 3433 static int 3434 qla_del_xmt_cntxt_i(qla_host_t *ha, uint32_t txr_idx) 3435 { 3436 device_t dev = ha->pci_dev; 3437 q80_tx_cntxt_destroy_t *tcntxt; 3438 q80_tx_cntxt_destroy_rsp_t *tcntxt_rsp; 3439 uint32_t err; 3440 3441 tcntxt = (q80_tx_cntxt_destroy_t *)ha->hw.mbox; 3442 bzero(tcntxt, (sizeof (q80_tx_cntxt_destroy_t))); 3443 3444 tcntxt->opcode = Q8_MBX_DESTROY_TX_CNTXT; 3445 tcntxt->count_version = (sizeof (q80_tx_cntxt_destroy_t) >> 2); 3446 tcntxt->count_version |= Q8_MBX_CMD_VERSION; 3447 3448 tcntxt->cntxt_id = ha->hw.tx_cntxt[txr_idx].tx_cntxt_id; 3449 3450 if (qla_mbx_cmd(ha, (uint32_t *)tcntxt, 3451 (sizeof (q80_tx_cntxt_destroy_t) >> 2), 3452 ha->hw.mbox, (sizeof (q80_tx_cntxt_destroy_rsp_t) >> 2), 0)) { 3453 device_printf(dev, "%s: failed0\n", __func__); 3454 return (-1); 3455 } 3456 tcntxt_rsp = (q80_tx_cntxt_destroy_rsp_t *)ha->hw.mbox; 3457 3458 err = Q8_MBX_RSP_STATUS(tcntxt_rsp->regcnt_status); 3459 3460 if (err) { 3461 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 3462 return (-1); 3463 } 3464 3465 return (0); 3466 } 3467 static int 3468 qla_del_xmt_cntxt(qla_host_t *ha) 3469 { 3470 uint32_t i; 3471 int ret = 0; 3472 3473 if (!ha->hw.flags.init_tx_cnxt) 3474 return (ret); 3475 3476 for (i = 0; i < ha->hw.num_tx_rings; i++) { 3477 if ((ret = qla_del_xmt_cntxt_i(ha, i)) != 0) 3478 break; 3479 } 3480 ha->hw.flags.init_tx_cnxt = 0; 3481 3482 return (ret); 3483 } 3484 3485 static int 3486 qla_init_xmt_cntxt(qla_host_t *ha) 3487 { 3488 uint32_t i, j; 3489 3490 for (i = 0; i < ha->hw.num_tx_rings; i++) { 3491 if (qla_init_xmt_cntxt_i(ha, i) != 0) { 3492 for (j = 0; j < i; j++) { 3493 if (qla_del_xmt_cntxt_i(ha, j)) 3494 break; 3495 } 3496 return (-1); 3497 } 3498 } 3499 ha->hw.flags.init_tx_cnxt = 1; 3500 return (0); 3501 } 3502 3503 static int 3504 qla_hw_all_mcast(qla_host_t *ha, uint32_t add_mcast) 3505 { 3506 int i, nmcast; 3507 uint32_t count = 0; 3508 uint8_t *mcast; 3509 3510 nmcast = ha->hw.nmcast; 3511 3512 QL_DPRINT2(ha, (ha->pci_dev, 3513 "%s:[0x%x] enter nmcast = %d \n", __func__, add_mcast, nmcast)); 3514 3515 mcast = ha->hw.mac_addr_arr; 3516 memset(mcast, 0, (Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN)); 3517 3518 for (i = 0 ; ((i < Q8_MAX_NUM_MULTICAST_ADDRS) && nmcast); i++) { 3519 if ((ha->hw.mcast[i].addr[0] != 0) || 3520 (ha->hw.mcast[i].addr[1] != 0) || 3521 (ha->hw.mcast[i].addr[2] != 0) || 3522 (ha->hw.mcast[i].addr[3] != 0) || 3523 (ha->hw.mcast[i].addr[4] != 0) || 3524 (ha->hw.mcast[i].addr[5] != 0)) { 3525 bcopy(ha->hw.mcast[i].addr, mcast, ETHER_ADDR_LEN); 3526 mcast = mcast + ETHER_ADDR_LEN; 3527 count++; 3528 3529 device_printf(ha->pci_dev, 3530 "%s: %x:%x:%x:%x:%x:%x \n", 3531 __func__, ha->hw.mcast[i].addr[0], 3532 ha->hw.mcast[i].addr[1], ha->hw.mcast[i].addr[2], 3533 ha->hw.mcast[i].addr[3], ha->hw.mcast[i].addr[4], 3534 ha->hw.mcast[i].addr[5]); 3535 3536 if (count == Q8_MAX_MAC_ADDRS) { 3537 if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr, 3538 add_mcast, count)) { 3539 device_printf(ha->pci_dev, 3540 "%s: failed\n", __func__); 3541 return (-1); 3542 } 3543 3544 count = 0; 3545 mcast = ha->hw.mac_addr_arr; 3546 memset(mcast, 0, 3547 (Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN)); 3548 } 3549 3550 nmcast--; 3551 } 3552 } 3553 3554 if (count) { 3555 if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr, add_mcast, 3556 count)) { 3557 device_printf(ha->pci_dev, "%s: failed\n", __func__); 3558 return (-1); 3559 } 3560 } 3561 QL_DPRINT2(ha, (ha->pci_dev, 3562 "%s:[0x%x] exit nmcast = %d \n", __func__, add_mcast, nmcast)); 3563 3564 return 0; 3565 } 3566 3567 static int 3568 qla_hw_add_all_mcast(qla_host_t *ha) 3569 { 3570 int ret; 3571 3572 ret = qla_hw_all_mcast(ha, 1); 3573 3574 return (ret); 3575 } 3576 3577 int 3578 qla_hw_del_all_mcast(qla_host_t *ha) 3579 { 3580 int ret; 3581 3582 ret = qla_hw_all_mcast(ha, 0); 3583 3584 bzero(ha->hw.mcast, (sizeof (qla_mcast_t) * Q8_MAX_NUM_MULTICAST_ADDRS)); 3585 ha->hw.nmcast = 0; 3586 3587 return (ret); 3588 } 3589 3590 static int 3591 qla_hw_mac_addr_present(qla_host_t *ha, uint8_t *mta) 3592 { 3593 int i; 3594 3595 for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) { 3596 if (QL_MAC_CMP(ha->hw.mcast[i].addr, mta) == 0) 3597 return (0); /* its been already added */ 3598 } 3599 return (-1); 3600 } 3601 3602 static int 3603 qla_hw_add_mcast(qla_host_t *ha, uint8_t *mta, uint32_t nmcast) 3604 { 3605 int i; 3606 3607 for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) { 3608 if ((ha->hw.mcast[i].addr[0] == 0) && 3609 (ha->hw.mcast[i].addr[1] == 0) && 3610 (ha->hw.mcast[i].addr[2] == 0) && 3611 (ha->hw.mcast[i].addr[3] == 0) && 3612 (ha->hw.mcast[i].addr[4] == 0) && 3613 (ha->hw.mcast[i].addr[5] == 0)) { 3614 bcopy(mta, ha->hw.mcast[i].addr, Q8_MAC_ADDR_LEN); 3615 ha->hw.nmcast++; 3616 3617 mta = mta + ETHER_ADDR_LEN; 3618 nmcast--; 3619 3620 if (nmcast == 0) 3621 break; 3622 } 3623 } 3624 return 0; 3625 } 3626 3627 static int 3628 qla_hw_del_mcast(qla_host_t *ha, uint8_t *mta, uint32_t nmcast) 3629 { 3630 int i; 3631 3632 for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) { 3633 if (QL_MAC_CMP(ha->hw.mcast[i].addr, mta) == 0) { 3634 ha->hw.mcast[i].addr[0] = 0; 3635 ha->hw.mcast[i].addr[1] = 0; 3636 ha->hw.mcast[i].addr[2] = 0; 3637 ha->hw.mcast[i].addr[3] = 0; 3638 ha->hw.mcast[i].addr[4] = 0; 3639 ha->hw.mcast[i].addr[5] = 0; 3640 3641 ha->hw.nmcast--; 3642 3643 mta = mta + ETHER_ADDR_LEN; 3644 nmcast--; 3645 3646 if (nmcast == 0) 3647 break; 3648 } 3649 } 3650 return 0; 3651 } 3652 3653 /* 3654 * Name: ql_hw_set_multi 3655 * Function: Sets the Multicast Addresses provided by the host O.S into the 3656 * hardware (for the given interface) 3657 */ 3658 int 3659 ql_hw_set_multi(qla_host_t *ha, uint8_t *mcast_addr, uint32_t mcnt, 3660 uint32_t add_mac) 3661 { 3662 uint8_t *mta = mcast_addr; 3663 int i; 3664 int ret = 0; 3665 uint32_t count = 0; 3666 uint8_t *mcast; 3667 3668 mcast = ha->hw.mac_addr_arr; 3669 memset(mcast, 0, (Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN)); 3670 3671 for (i = 0; i < mcnt; i++) { 3672 if (mta[0] || mta[1] || mta[2] || mta[3] || mta[4] || mta[5]) { 3673 if (add_mac) { 3674 if (qla_hw_mac_addr_present(ha, mta) != 0) { 3675 bcopy(mta, mcast, ETHER_ADDR_LEN); 3676 mcast = mcast + ETHER_ADDR_LEN; 3677 count++; 3678 } 3679 } else { 3680 if (qla_hw_mac_addr_present(ha, mta) == 0) { 3681 bcopy(mta, mcast, ETHER_ADDR_LEN); 3682 mcast = mcast + ETHER_ADDR_LEN; 3683 count++; 3684 } 3685 } 3686 } 3687 if (count == Q8_MAX_MAC_ADDRS) { 3688 if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr, 3689 add_mac, count)) { 3690 device_printf(ha->pci_dev, "%s: failed\n", 3691 __func__); 3692 return (-1); 3693 } 3694 3695 if (add_mac) { 3696 qla_hw_add_mcast(ha, ha->hw.mac_addr_arr, 3697 count); 3698 } else { 3699 qla_hw_del_mcast(ha, ha->hw.mac_addr_arr, 3700 count); 3701 } 3702 3703 count = 0; 3704 mcast = ha->hw.mac_addr_arr; 3705 memset(mcast, 0, (Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN)); 3706 } 3707 3708 mta += Q8_MAC_ADDR_LEN; 3709 } 3710 3711 if (count) { 3712 if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr, add_mac, 3713 count)) { 3714 device_printf(ha->pci_dev, "%s: failed\n", __func__); 3715 return (-1); 3716 } 3717 if (add_mac) { 3718 qla_hw_add_mcast(ha, ha->hw.mac_addr_arr, count); 3719 } else { 3720 qla_hw_del_mcast(ha, ha->hw.mac_addr_arr, count); 3721 } 3722 } 3723 3724 return (ret); 3725 } 3726 3727 /* 3728 * Name: ql_hw_tx_done_locked 3729 * Function: Handle Transmit Completions 3730 */ 3731 void 3732 ql_hw_tx_done_locked(qla_host_t *ha, uint32_t txr_idx) 3733 { 3734 qla_tx_buf_t *txb; 3735 qla_hw_t *hw = &ha->hw; 3736 uint32_t comp_idx, comp_count = 0; 3737 qla_hw_tx_cntxt_t *hw_tx_cntxt; 3738 3739 hw_tx_cntxt = &hw->tx_cntxt[txr_idx]; 3740 3741 /* retrieve index of last entry in tx ring completed */ 3742 comp_idx = qla_le32_to_host(*(hw_tx_cntxt->tx_cons)); 3743 3744 while (comp_idx != hw_tx_cntxt->txr_comp) { 3745 txb = &ha->tx_ring[txr_idx].tx_buf[hw_tx_cntxt->txr_comp]; 3746 3747 hw_tx_cntxt->txr_comp++; 3748 if (hw_tx_cntxt->txr_comp == NUM_TX_DESCRIPTORS) 3749 hw_tx_cntxt->txr_comp = 0; 3750 3751 comp_count++; 3752 3753 if (txb->m_head) { 3754 if_inc_counter(ha->ifp, IFCOUNTER_OPACKETS, 1); 3755 3756 bus_dmamap_sync(ha->tx_tag, txb->map, 3757 BUS_DMASYNC_POSTWRITE); 3758 bus_dmamap_unload(ha->tx_tag, txb->map); 3759 m_freem(txb->m_head); 3760 3761 txb->m_head = NULL; 3762 } 3763 } 3764 3765 hw_tx_cntxt->txr_free += comp_count; 3766 3767 if (hw_tx_cntxt->txr_free > NUM_TX_DESCRIPTORS) 3768 device_printf(ha->pci_dev, "%s [%d]: txr_idx = %d txr_free = %d" 3769 "txr_next = %d txr_comp = %d\n", __func__, __LINE__, 3770 txr_idx, hw_tx_cntxt->txr_free, 3771 hw_tx_cntxt->txr_next, hw_tx_cntxt->txr_comp); 3772 3773 QL_ASSERT(ha, (hw_tx_cntxt->txr_free <= NUM_TX_DESCRIPTORS), \ 3774 ("%s [%d]: txr_idx = %d txr_free = %d txr_next = %d txr_comp = %d\n",\ 3775 __func__, __LINE__, txr_idx, hw_tx_cntxt->txr_free, \ 3776 hw_tx_cntxt->txr_next, hw_tx_cntxt->txr_comp)); 3777 3778 return; 3779 } 3780 3781 void 3782 ql_update_link_state(qla_host_t *ha) 3783 { 3784 uint32_t link_state = 0; 3785 uint32_t prev_link_state; 3786 3787 prev_link_state = ha->hw.link_up; 3788 3789 if (if_getdrvflags(ha->ifp) & IFF_DRV_RUNNING) { 3790 link_state = READ_REG32(ha, Q8_LINK_STATE); 3791 3792 if (ha->pci_func == 0) { 3793 link_state = (((link_state & 0xF) == 1)? 1 : 0); 3794 } else { 3795 link_state = ((((link_state >> 4)& 0xF) == 1)? 1 : 0); 3796 } 3797 } 3798 3799 atomic_store_rel_8(&ha->hw.link_up, (uint8_t)link_state); 3800 3801 if (prev_link_state != ha->hw.link_up) { 3802 if (ha->hw.link_up) { 3803 if_link_state_change(ha->ifp, LINK_STATE_UP); 3804 } else { 3805 if_link_state_change(ha->ifp, LINK_STATE_DOWN); 3806 } 3807 } 3808 return; 3809 } 3810 3811 int 3812 ql_hw_check_health(qla_host_t *ha) 3813 { 3814 uint32_t val; 3815 3816 ha->hw.health_count++; 3817 3818 if (ha->hw.health_count < 500) 3819 return 0; 3820 3821 ha->hw.health_count = 0; 3822 3823 val = READ_REG32(ha, Q8_ASIC_TEMPERATURE); 3824 3825 if (((val & 0xFFFF) == 2) || ((val & 0xFFFF) == 3) || 3826 (QL_ERR_INJECT(ha, INJCT_TEMPERATURE_FAILURE))) { 3827 device_printf(ha->pci_dev, "%s: Temperature Alert" 3828 " at ts_usecs %ld ts_reg = 0x%08x\n", 3829 __func__, qla_get_usec_timestamp(), val); 3830 3831 if (ha->hw.sp_log_stop_events & Q8_SP_LOG_STOP_TEMP_FAILURE) 3832 ha->hw.sp_log_stop = -1; 3833 3834 QL_INITIATE_RECOVERY(ha); 3835 return -1; 3836 } 3837 3838 val = READ_REG32(ha, Q8_FIRMWARE_HEARTBEAT); 3839 3840 if ((val != ha->hw.hbeat_value) && 3841 (!(QL_ERR_INJECT(ha, INJCT_HEARTBEAT_FAILURE)))) { 3842 ha->hw.hbeat_value = val; 3843 ha->hw.hbeat_failure = 0; 3844 return 0; 3845 } 3846 3847 ha->hw.hbeat_failure++; 3848 3849 if ((ha->dbg_level & 0x8000) && (ha->hw.hbeat_failure == 1)) 3850 device_printf(ha->pci_dev, "%s: Heartbeat Failue 1[0x%08x]\n", 3851 __func__, val); 3852 if (ha->hw.hbeat_failure < 2) /* we ignore the first failure */ 3853 return 0; 3854 else { 3855 uint32_t peg_halt_status1; 3856 uint32_t peg_halt_status2; 3857 3858 peg_halt_status1 = READ_REG32(ha, Q8_PEG_HALT_STATUS1); 3859 peg_halt_status2 = READ_REG32(ha, Q8_PEG_HALT_STATUS2); 3860 3861 device_printf(ha->pci_dev, 3862 "%s: Heartbeat Failue at ts_usecs = %ld " 3863 "fw_heart_beat = 0x%08x " 3864 "peg_halt_status1 = 0x%08x " 3865 "peg_halt_status2 = 0x%08x\n", 3866 __func__, qla_get_usec_timestamp(), val, 3867 peg_halt_status1, peg_halt_status2); 3868 3869 if (ha->hw.sp_log_stop_events & Q8_SP_LOG_STOP_HBEAT_FAILURE) 3870 ha->hw.sp_log_stop = -1; 3871 } 3872 QL_INITIATE_RECOVERY(ha); 3873 3874 return -1; 3875 } 3876 3877 static int 3878 qla_init_nic_func(qla_host_t *ha) 3879 { 3880 device_t dev; 3881 q80_init_nic_func_t *init_nic; 3882 q80_init_nic_func_rsp_t *init_nic_rsp; 3883 uint32_t err; 3884 3885 dev = ha->pci_dev; 3886 3887 init_nic = (q80_init_nic_func_t *)ha->hw.mbox; 3888 bzero(init_nic, sizeof(q80_init_nic_func_t)); 3889 3890 init_nic->opcode = Q8_MBX_INIT_NIC_FUNC; 3891 init_nic->count_version = (sizeof (q80_init_nic_func_t) >> 2); 3892 init_nic->count_version |= Q8_MBX_CMD_VERSION; 3893 3894 init_nic->options = Q8_INIT_NIC_REG_DCBX_CHNG_AEN; 3895 init_nic->options |= Q8_INIT_NIC_REG_SFP_CHNG_AEN; 3896 init_nic->options |= Q8_INIT_NIC_REG_IDC_AEN; 3897 3898 //qla_dump_buf8(ha, __func__, init_nic, sizeof (q80_init_nic_func_t)); 3899 if (qla_mbx_cmd(ha, (uint32_t *)init_nic, 3900 (sizeof (q80_init_nic_func_t) >> 2), 3901 ha->hw.mbox, (sizeof (q80_init_nic_func_rsp_t) >> 2), 0)) { 3902 device_printf(dev, "%s: failed\n", __func__); 3903 return -1; 3904 } 3905 3906 init_nic_rsp = (q80_init_nic_func_rsp_t *)ha->hw.mbox; 3907 // qla_dump_buf8(ha, __func__, init_nic_rsp, sizeof (q80_init_nic_func_rsp_t)); 3908 3909 err = Q8_MBX_RSP_STATUS(init_nic_rsp->regcnt_status); 3910 3911 if (err) { 3912 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 3913 } else { 3914 device_printf(dev, "%s: successful\n", __func__); 3915 } 3916 3917 return 0; 3918 } 3919 3920 static int 3921 qla_stop_nic_func(qla_host_t *ha) 3922 { 3923 device_t dev; 3924 q80_stop_nic_func_t *stop_nic; 3925 q80_stop_nic_func_rsp_t *stop_nic_rsp; 3926 uint32_t err; 3927 3928 dev = ha->pci_dev; 3929 3930 stop_nic = (q80_stop_nic_func_t *)ha->hw.mbox; 3931 bzero(stop_nic, sizeof(q80_stop_nic_func_t)); 3932 3933 stop_nic->opcode = Q8_MBX_STOP_NIC_FUNC; 3934 stop_nic->count_version = (sizeof (q80_stop_nic_func_t) >> 2); 3935 stop_nic->count_version |= Q8_MBX_CMD_VERSION; 3936 3937 stop_nic->options = Q8_STOP_NIC_DEREG_DCBX_CHNG_AEN; 3938 stop_nic->options |= Q8_STOP_NIC_DEREG_SFP_CHNG_AEN; 3939 3940 //qla_dump_buf8(ha, __func__, stop_nic, sizeof (q80_stop_nic_func_t)); 3941 if (qla_mbx_cmd(ha, (uint32_t *)stop_nic, 3942 (sizeof (q80_stop_nic_func_t) >> 2), 3943 ha->hw.mbox, (sizeof (q80_stop_nic_func_rsp_t) >> 2), 0)) { 3944 device_printf(dev, "%s: failed\n", __func__); 3945 return -1; 3946 } 3947 3948 stop_nic_rsp = (q80_stop_nic_func_rsp_t *)ha->hw.mbox; 3949 //qla_dump_buf8(ha, __func__, stop_nic_rsp, sizeof (q80_stop_nic_func_rsp_ t)); 3950 3951 err = Q8_MBX_RSP_STATUS(stop_nic_rsp->regcnt_status); 3952 3953 if (err) { 3954 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 3955 } 3956 3957 return 0; 3958 } 3959 3960 static int 3961 qla_query_fw_dcbx_caps(qla_host_t *ha) 3962 { 3963 device_t dev; 3964 q80_query_fw_dcbx_caps_t *fw_dcbx; 3965 q80_query_fw_dcbx_caps_rsp_t *fw_dcbx_rsp; 3966 uint32_t err; 3967 3968 dev = ha->pci_dev; 3969 3970 fw_dcbx = (q80_query_fw_dcbx_caps_t *)ha->hw.mbox; 3971 bzero(fw_dcbx, sizeof(q80_query_fw_dcbx_caps_t)); 3972 3973 fw_dcbx->opcode = Q8_MBX_GET_FW_DCBX_CAPS; 3974 fw_dcbx->count_version = (sizeof (q80_query_fw_dcbx_caps_t) >> 2); 3975 fw_dcbx->count_version |= Q8_MBX_CMD_VERSION; 3976 3977 ql_dump_buf8(ha, __func__, fw_dcbx, sizeof (q80_query_fw_dcbx_caps_t)); 3978 if (qla_mbx_cmd(ha, (uint32_t *)fw_dcbx, 3979 (sizeof (q80_query_fw_dcbx_caps_t) >> 2), 3980 ha->hw.mbox, (sizeof (q80_query_fw_dcbx_caps_rsp_t) >> 2), 0)) { 3981 device_printf(dev, "%s: failed\n", __func__); 3982 return -1; 3983 } 3984 3985 fw_dcbx_rsp = (q80_query_fw_dcbx_caps_rsp_t *)ha->hw.mbox; 3986 ql_dump_buf8(ha, __func__, fw_dcbx_rsp, 3987 sizeof (q80_query_fw_dcbx_caps_rsp_t)); 3988 3989 err = Q8_MBX_RSP_STATUS(fw_dcbx_rsp->regcnt_status); 3990 3991 if (err) { 3992 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 3993 } 3994 3995 return 0; 3996 } 3997 3998 static int 3999 qla_idc_ack(qla_host_t *ha, uint32_t aen_mb1, uint32_t aen_mb2, 4000 uint32_t aen_mb3, uint32_t aen_mb4) 4001 { 4002 device_t dev; 4003 q80_idc_ack_t *idc_ack; 4004 q80_idc_ack_rsp_t *idc_ack_rsp; 4005 uint32_t err; 4006 int count = 300; 4007 4008 dev = ha->pci_dev; 4009 4010 idc_ack = (q80_idc_ack_t *)ha->hw.mbox; 4011 bzero(idc_ack, sizeof(q80_idc_ack_t)); 4012 4013 idc_ack->opcode = Q8_MBX_IDC_ACK; 4014 idc_ack->count_version = (sizeof (q80_idc_ack_t) >> 2); 4015 idc_ack->count_version |= Q8_MBX_CMD_VERSION; 4016 4017 idc_ack->aen_mb1 = aen_mb1; 4018 idc_ack->aen_mb2 = aen_mb2; 4019 idc_ack->aen_mb3 = aen_mb3; 4020 idc_ack->aen_mb4 = aen_mb4; 4021 4022 ha->hw.imd_compl= 0; 4023 4024 if (qla_mbx_cmd(ha, (uint32_t *)idc_ack, 4025 (sizeof (q80_idc_ack_t) >> 2), 4026 ha->hw.mbox, (sizeof (q80_idc_ack_rsp_t) >> 2), 0)) { 4027 device_printf(dev, "%s: failed\n", __func__); 4028 return -1; 4029 } 4030 4031 idc_ack_rsp = (q80_idc_ack_rsp_t *)ha->hw.mbox; 4032 4033 err = Q8_MBX_RSP_STATUS(idc_ack_rsp->regcnt_status); 4034 4035 if (err) { 4036 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 4037 return(-1); 4038 } 4039 4040 while (count && !ha->hw.imd_compl) { 4041 qla_mdelay(__func__, 100); 4042 count--; 4043 } 4044 4045 if (!count) 4046 return -1; 4047 else 4048 device_printf(dev, "%s: count %d\n", __func__, count); 4049 4050 return (0); 4051 } 4052 4053 static int 4054 qla_set_port_config(qla_host_t *ha, uint32_t cfg_bits) 4055 { 4056 device_t dev; 4057 q80_set_port_cfg_t *pcfg; 4058 q80_set_port_cfg_rsp_t *pfg_rsp; 4059 uint32_t err; 4060 int count = 300; 4061 4062 dev = ha->pci_dev; 4063 4064 pcfg = (q80_set_port_cfg_t *)ha->hw.mbox; 4065 bzero(pcfg, sizeof(q80_set_port_cfg_t)); 4066 4067 pcfg->opcode = Q8_MBX_SET_PORT_CONFIG; 4068 pcfg->count_version = (sizeof (q80_set_port_cfg_t) >> 2); 4069 pcfg->count_version |= Q8_MBX_CMD_VERSION; 4070 4071 pcfg->cfg_bits = cfg_bits; 4072 4073 device_printf(dev, "%s: cfg_bits" 4074 " [STD_PAUSE_DIR, PAUSE_TYPE, DCBX]" 4075 " [0x%x, 0x%x, 0x%x]\n", __func__, 4076 ((cfg_bits & Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK)>>20), 4077 ((cfg_bits & Q8_PORT_CFG_BITS_PAUSE_CFG_MASK) >> 5), 4078 ((cfg_bits & Q8_PORT_CFG_BITS_DCBX_ENABLE) ? 1: 0)); 4079 4080 ha->hw.imd_compl= 0; 4081 4082 if (qla_mbx_cmd(ha, (uint32_t *)pcfg, 4083 (sizeof (q80_set_port_cfg_t) >> 2), 4084 ha->hw.mbox, (sizeof (q80_set_port_cfg_rsp_t) >> 2), 0)) { 4085 device_printf(dev, "%s: failed\n", __func__); 4086 return -1; 4087 } 4088 4089 pfg_rsp = (q80_set_port_cfg_rsp_t *)ha->hw.mbox; 4090 4091 err = Q8_MBX_RSP_STATUS(pfg_rsp->regcnt_status); 4092 4093 if (err == Q8_MBX_RSP_IDC_INTRMD_RSP) { 4094 while (count && !ha->hw.imd_compl) { 4095 qla_mdelay(__func__, 100); 4096 count--; 4097 } 4098 if (count) { 4099 device_printf(dev, "%s: count %d\n", __func__, count); 4100 4101 err = 0; 4102 } 4103 } 4104 4105 if (err) { 4106 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 4107 return(-1); 4108 } 4109 4110 return (0); 4111 } 4112 4113 static int 4114 qla_get_minidump_tmplt_size(qla_host_t *ha, uint32_t *size) 4115 { 4116 uint32_t err; 4117 device_t dev = ha->pci_dev; 4118 q80_config_md_templ_size_t *md_size; 4119 q80_config_md_templ_size_rsp_t *md_size_rsp; 4120 4121 #ifndef QL_LDFLASH_FW 4122 4123 ql_minidump_template_hdr_t *hdr; 4124 4125 hdr = (ql_minidump_template_hdr_t *)ql83xx_minidump; 4126 *size = hdr->size_of_template; 4127 return (0); 4128 4129 #endif /* #ifdef QL_LDFLASH_FW */ 4130 4131 md_size = (q80_config_md_templ_size_t *) ha->hw.mbox; 4132 bzero(md_size, sizeof(q80_config_md_templ_size_t)); 4133 4134 md_size->opcode = Q8_MBX_GET_MINIDUMP_TMPLT_SIZE; 4135 md_size->count_version = (sizeof (q80_config_md_templ_size_t) >> 2); 4136 md_size->count_version |= Q8_MBX_CMD_VERSION; 4137 4138 if (qla_mbx_cmd(ha, (uint32_t *) md_size, 4139 (sizeof(q80_config_md_templ_size_t) >> 2), ha->hw.mbox, 4140 (sizeof(q80_config_md_templ_size_rsp_t) >> 2), 0)) { 4141 device_printf(dev, "%s: failed\n", __func__); 4142 4143 return (-1); 4144 } 4145 4146 md_size_rsp = (q80_config_md_templ_size_rsp_t *) ha->hw.mbox; 4147 4148 err = Q8_MBX_RSP_STATUS(md_size_rsp->regcnt_status); 4149 4150 if (err) { 4151 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 4152 return(-1); 4153 } 4154 4155 *size = md_size_rsp->templ_size; 4156 4157 return (0); 4158 } 4159 4160 static int 4161 qla_get_port_config(qla_host_t *ha, uint32_t *cfg_bits) 4162 { 4163 device_t dev; 4164 q80_get_port_cfg_t *pcfg; 4165 q80_get_port_cfg_rsp_t *pcfg_rsp; 4166 uint32_t err; 4167 4168 dev = ha->pci_dev; 4169 4170 pcfg = (q80_get_port_cfg_t *)ha->hw.mbox; 4171 bzero(pcfg, sizeof(q80_get_port_cfg_t)); 4172 4173 pcfg->opcode = Q8_MBX_GET_PORT_CONFIG; 4174 pcfg->count_version = (sizeof (q80_get_port_cfg_t) >> 2); 4175 pcfg->count_version |= Q8_MBX_CMD_VERSION; 4176 4177 if (qla_mbx_cmd(ha, (uint32_t *)pcfg, 4178 (sizeof (q80_get_port_cfg_t) >> 2), 4179 ha->hw.mbox, (sizeof (q80_get_port_cfg_rsp_t) >> 2), 0)) { 4180 device_printf(dev, "%s: failed\n", __func__); 4181 return -1; 4182 } 4183 4184 pcfg_rsp = (q80_get_port_cfg_rsp_t *)ha->hw.mbox; 4185 4186 err = Q8_MBX_RSP_STATUS(pcfg_rsp->regcnt_status); 4187 4188 if (err) { 4189 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 4190 return(-1); 4191 } 4192 4193 device_printf(dev, "%s: [cfg_bits, port type]" 4194 " [0x%08x, 0x%02x] [STD_PAUSE_DIR, PAUSE_TYPE, DCBX]" 4195 " [0x%x, 0x%x, 0x%x]\n", __func__, 4196 pcfg_rsp->cfg_bits, pcfg_rsp->phys_port_type, 4197 ((pcfg_rsp->cfg_bits & Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK)>>20), 4198 ((pcfg_rsp->cfg_bits & Q8_PORT_CFG_BITS_PAUSE_CFG_MASK) >> 5), 4199 ((pcfg_rsp->cfg_bits & Q8_PORT_CFG_BITS_DCBX_ENABLE) ? 1: 0) 4200 ); 4201 4202 *cfg_bits = pcfg_rsp->cfg_bits; 4203 4204 return (0); 4205 } 4206 4207 int 4208 ql_iscsi_pdu(qla_host_t *ha, struct mbuf *mp) 4209 { 4210 struct ether_vlan_header *eh; 4211 uint16_t etype; 4212 struct ip *ip = NULL; 4213 struct ip6_hdr *ip6 = NULL; 4214 struct tcphdr *th = NULL; 4215 uint32_t hdrlen; 4216 uint32_t offset; 4217 uint8_t buf[sizeof(struct ip6_hdr)]; 4218 4219 eh = mtod(mp, struct ether_vlan_header *); 4220 4221 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 4222 hdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 4223 etype = ntohs(eh->evl_proto); 4224 } else { 4225 hdrlen = ETHER_HDR_LEN; 4226 etype = ntohs(eh->evl_encap_proto); 4227 } 4228 4229 if (etype == ETHERTYPE_IP) { 4230 offset = (hdrlen + sizeof (struct ip)); 4231 4232 if (mp->m_len >= offset) { 4233 ip = (struct ip *)(mp->m_data + hdrlen); 4234 } else { 4235 m_copydata(mp, hdrlen, sizeof (struct ip), buf); 4236 ip = (struct ip *)buf; 4237 } 4238 4239 if (ip->ip_p == IPPROTO_TCP) { 4240 hdrlen += ip->ip_hl << 2; 4241 offset = hdrlen + 4; 4242 4243 if (mp->m_len >= offset) { 4244 th = (struct tcphdr *)(mp->m_data + hdrlen); 4245 } else { 4246 m_copydata(mp, hdrlen, 4, buf); 4247 th = (struct tcphdr *)buf; 4248 } 4249 } 4250 4251 } else if (etype == ETHERTYPE_IPV6) { 4252 offset = (hdrlen + sizeof (struct ip6_hdr)); 4253 4254 if (mp->m_len >= offset) { 4255 ip6 = (struct ip6_hdr *)(mp->m_data + hdrlen); 4256 } else { 4257 m_copydata(mp, hdrlen, sizeof (struct ip6_hdr), buf); 4258 ip6 = (struct ip6_hdr *)buf; 4259 } 4260 4261 if (ip6->ip6_nxt == IPPROTO_TCP) { 4262 hdrlen += sizeof(struct ip6_hdr); 4263 offset = hdrlen + 4; 4264 4265 if (mp->m_len >= offset) { 4266 th = (struct tcphdr *)(mp->m_data + hdrlen); 4267 } else { 4268 m_copydata(mp, hdrlen, 4, buf); 4269 th = (struct tcphdr *)buf; 4270 } 4271 } 4272 } 4273 4274 if (th != NULL) { 4275 if ((th->th_sport == htons(3260)) || 4276 (th->th_dport == htons(3260))) 4277 return 0; 4278 } 4279 return (-1); 4280 } 4281 4282 void 4283 qla_hw_async_event(qla_host_t *ha) 4284 { 4285 switch (ha->hw.aen_mb0) { 4286 case 0x8101: 4287 (void)qla_idc_ack(ha, ha->hw.aen_mb1, ha->hw.aen_mb2, 4288 ha->hw.aen_mb3, ha->hw.aen_mb4); 4289 4290 break; 4291 4292 default: 4293 break; 4294 } 4295 4296 return; 4297 } 4298 4299 #ifdef QL_LDFLASH_FW 4300 static int 4301 ql_get_minidump_template(qla_host_t *ha) 4302 { 4303 uint32_t err; 4304 device_t dev = ha->pci_dev; 4305 q80_config_md_templ_cmd_t *md_templ; 4306 q80_config_md_templ_cmd_rsp_t *md_templ_rsp; 4307 4308 md_templ = (q80_config_md_templ_cmd_t *) ha->hw.mbox; 4309 bzero(md_templ, (sizeof (q80_config_md_templ_cmd_t))); 4310 4311 md_templ->opcode = Q8_MBX_GET_MINIDUMP_TMPLT; 4312 md_templ->count_version = ( sizeof(q80_config_md_templ_cmd_t) >> 2); 4313 md_templ->count_version |= Q8_MBX_CMD_VERSION; 4314 4315 md_templ->buf_addr = ha->hw.dma_buf.minidump.dma_addr; 4316 md_templ->buff_size = ha->hw.dma_buf.minidump.size; 4317 4318 if (qla_mbx_cmd(ha, (uint32_t *) md_templ, 4319 (sizeof(q80_config_md_templ_cmd_t) >> 2), 4320 ha->hw.mbox, 4321 (sizeof(q80_config_md_templ_cmd_rsp_t) >> 2), 0)) { 4322 device_printf(dev, "%s: failed\n", __func__); 4323 4324 return (-1); 4325 } 4326 4327 md_templ_rsp = (q80_config_md_templ_cmd_rsp_t *) ha->hw.mbox; 4328 4329 err = Q8_MBX_RSP_STATUS(md_templ_rsp->regcnt_status); 4330 4331 if (err) { 4332 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 4333 return (-1); 4334 } 4335 4336 return (0); 4337 4338 } 4339 #endif /* #ifdef QL_LDFLASH_FW */ 4340 4341 /* 4342 * Minidump related functionality 4343 */ 4344 4345 static int ql_parse_template(qla_host_t *ha); 4346 4347 static uint32_t ql_rdcrb(qla_host_t *ha, 4348 ql_minidump_entry_rdcrb_t *crb_entry, 4349 uint32_t * data_buff); 4350 4351 static uint32_t ql_pollrd(qla_host_t *ha, 4352 ql_minidump_entry_pollrd_t *entry, 4353 uint32_t * data_buff); 4354 4355 static uint32_t ql_pollrd_modify_write(qla_host_t *ha, 4356 ql_minidump_entry_rd_modify_wr_with_poll_t *entry, 4357 uint32_t *data_buff); 4358 4359 static uint32_t ql_L2Cache(qla_host_t *ha, 4360 ql_minidump_entry_cache_t *cacheEntry, 4361 uint32_t * data_buff); 4362 4363 static uint32_t ql_L1Cache(qla_host_t *ha, 4364 ql_minidump_entry_cache_t *cacheEntry, 4365 uint32_t *data_buff); 4366 4367 static uint32_t ql_rdocm(qla_host_t *ha, 4368 ql_minidump_entry_rdocm_t *ocmEntry, 4369 uint32_t *data_buff); 4370 4371 static uint32_t ql_rdmem(qla_host_t *ha, 4372 ql_minidump_entry_rdmem_t *mem_entry, 4373 uint32_t *data_buff); 4374 4375 static uint32_t ql_rdrom(qla_host_t *ha, 4376 ql_minidump_entry_rdrom_t *romEntry, 4377 uint32_t *data_buff); 4378 4379 static uint32_t ql_rdmux(qla_host_t *ha, 4380 ql_minidump_entry_mux_t *muxEntry, 4381 uint32_t *data_buff); 4382 4383 static uint32_t ql_rdmux2(qla_host_t *ha, 4384 ql_minidump_entry_mux2_t *muxEntry, 4385 uint32_t *data_buff); 4386 4387 static uint32_t ql_rdqueue(qla_host_t *ha, 4388 ql_minidump_entry_queue_t *queueEntry, 4389 uint32_t *data_buff); 4390 4391 static uint32_t ql_cntrl(qla_host_t *ha, 4392 ql_minidump_template_hdr_t *template_hdr, 4393 ql_minidump_entry_cntrl_t *crbEntry); 4394 4395 static uint32_t 4396 ql_minidump_size(qla_host_t *ha) 4397 { 4398 uint32_t i, k; 4399 uint32_t size = 0; 4400 ql_minidump_template_hdr_t *hdr; 4401 4402 hdr = (ql_minidump_template_hdr_t *)ha->hw.dma_buf.minidump.dma_b; 4403 4404 i = 0x2; 4405 4406 for (k = 1; k < QL_DBG_CAP_SIZE_ARRAY_LEN; k++) { 4407 if (i & ha->hw.mdump_capture_mask) 4408 size += hdr->capture_size_array[k]; 4409 i = i << 1; 4410 } 4411 return (size); 4412 } 4413 4414 static void 4415 ql_free_minidump_buffer(qla_host_t *ha) 4416 { 4417 if (ha->hw.mdump_buffer != NULL) { 4418 free(ha->hw.mdump_buffer, M_QLA83XXBUF); 4419 ha->hw.mdump_buffer = NULL; 4420 ha->hw.mdump_buffer_size = 0; 4421 } 4422 return; 4423 } 4424 4425 static int 4426 ql_alloc_minidump_buffer(qla_host_t *ha) 4427 { 4428 ha->hw.mdump_buffer_size = ql_minidump_size(ha); 4429 4430 if (!ha->hw.mdump_buffer_size) 4431 return (-1); 4432 4433 ha->hw.mdump_buffer = malloc(ha->hw.mdump_buffer_size, M_QLA83XXBUF, 4434 M_NOWAIT); 4435 4436 if (ha->hw.mdump_buffer == NULL) 4437 return (-1); 4438 4439 return (0); 4440 } 4441 4442 static void 4443 ql_free_minidump_template_buffer(qla_host_t *ha) 4444 { 4445 if (ha->hw.mdump_template != NULL) { 4446 free(ha->hw.mdump_template, M_QLA83XXBUF); 4447 ha->hw.mdump_template = NULL; 4448 ha->hw.mdump_template_size = 0; 4449 } 4450 return; 4451 } 4452 4453 static int 4454 ql_alloc_minidump_template_buffer(qla_host_t *ha) 4455 { 4456 ha->hw.mdump_template_size = ha->hw.dma_buf.minidump.size; 4457 4458 ha->hw.mdump_template = malloc(ha->hw.mdump_template_size, 4459 M_QLA83XXBUF, M_NOWAIT); 4460 4461 if (ha->hw.mdump_template == NULL) 4462 return (-1); 4463 4464 return (0); 4465 } 4466 4467 static int 4468 ql_alloc_minidump_buffers(qla_host_t *ha) 4469 { 4470 int ret; 4471 4472 ret = ql_alloc_minidump_template_buffer(ha); 4473 4474 if (ret) 4475 return (ret); 4476 4477 ret = ql_alloc_minidump_buffer(ha); 4478 4479 if (ret) 4480 ql_free_minidump_template_buffer(ha); 4481 4482 return (ret); 4483 } 4484 4485 static uint32_t 4486 ql_validate_minidump_checksum(qla_host_t *ha) 4487 { 4488 uint64_t sum = 0; 4489 int count; 4490 uint32_t *template_buff; 4491 4492 count = ha->hw.dma_buf.minidump.size / sizeof (uint32_t); 4493 template_buff = ha->hw.dma_buf.minidump.dma_b; 4494 4495 while (count-- > 0) { 4496 sum += *template_buff++; 4497 } 4498 4499 while (sum >> 32) { 4500 sum = (sum & 0xFFFFFFFF) + (sum >> 32); 4501 } 4502 4503 return (~sum); 4504 } 4505 4506 int 4507 ql_minidump_init(qla_host_t *ha) 4508 { 4509 int ret = 0; 4510 uint32_t template_size = 0; 4511 device_t dev = ha->pci_dev; 4512 4513 /* 4514 * Get Minidump Template Size 4515 */ 4516 ret = qla_get_minidump_tmplt_size(ha, &template_size); 4517 4518 if (ret || (template_size == 0)) { 4519 device_printf(dev, "%s: failed [%d, %d]\n", __func__, ret, 4520 template_size); 4521 return (-1); 4522 } 4523 4524 /* 4525 * Allocate Memory for Minidump Template 4526 */ 4527 4528 ha->hw.dma_buf.minidump.alignment = 8; 4529 ha->hw.dma_buf.minidump.size = template_size; 4530 4531 #ifdef QL_LDFLASH_FW 4532 if (ql_alloc_dmabuf(ha, &ha->hw.dma_buf.minidump)) { 4533 device_printf(dev, "%s: minidump dma alloc failed\n", __func__); 4534 4535 return (-1); 4536 } 4537 ha->hw.dma_buf.flags.minidump = 1; 4538 4539 /* 4540 * Retrieve Minidump Template 4541 */ 4542 ret = ql_get_minidump_template(ha); 4543 #else 4544 ha->hw.dma_buf.minidump.dma_b = ql83xx_minidump; 4545 4546 #endif /* #ifdef QL_LDFLASH_FW */ 4547 4548 if (ret == 0) { 4549 ret = ql_validate_minidump_checksum(ha); 4550 4551 if (ret == 0) { 4552 ret = ql_alloc_minidump_buffers(ha); 4553 4554 if (ret == 0) 4555 ha->hw.mdump_init = 1; 4556 else 4557 device_printf(dev, 4558 "%s: ql_alloc_minidump_buffers" 4559 " failed\n", __func__); 4560 } else { 4561 device_printf(dev, "%s: ql_validate_minidump_checksum" 4562 " failed\n", __func__); 4563 } 4564 } else { 4565 device_printf(dev, "%s: ql_get_minidump_template failed\n", 4566 __func__); 4567 } 4568 4569 if (ret) 4570 ql_minidump_free(ha); 4571 4572 return (ret); 4573 } 4574 4575 static void 4576 ql_minidump_free(qla_host_t *ha) 4577 { 4578 ha->hw.mdump_init = 0; 4579 if (ha->hw.dma_buf.flags.minidump) { 4580 ha->hw.dma_buf.flags.minidump = 0; 4581 ql_free_dmabuf(ha, &ha->hw.dma_buf.minidump); 4582 } 4583 4584 ql_free_minidump_template_buffer(ha); 4585 ql_free_minidump_buffer(ha); 4586 4587 return; 4588 } 4589 4590 void 4591 ql_minidump(qla_host_t *ha) 4592 { 4593 if (!ha->hw.mdump_init) 4594 return; 4595 4596 if (ha->hw.mdump_done) 4597 return; 4598 ha->hw.mdump_usec_ts = qla_get_usec_timestamp(); 4599 ha->hw.mdump_start_seq_index = ql_stop_sequence(ha); 4600 4601 bzero(ha->hw.mdump_buffer, ha->hw.mdump_buffer_size); 4602 bzero(ha->hw.mdump_template, ha->hw.mdump_template_size); 4603 4604 bcopy(ha->hw.dma_buf.minidump.dma_b, ha->hw.mdump_template, 4605 ha->hw.mdump_template_size); 4606 4607 ql_parse_template(ha); 4608 4609 ql_start_sequence(ha, ha->hw.mdump_start_seq_index); 4610 4611 ha->hw.mdump_done = 1; 4612 4613 return; 4614 } 4615 4616 /* 4617 * helper routines 4618 */ 4619 static void 4620 ql_entry_err_chk(ql_minidump_entry_t *entry, uint32_t esize) 4621 { 4622 if (esize != entry->hdr.entry_capture_size) { 4623 entry->hdr.entry_capture_size = esize; 4624 entry->hdr.driver_flags |= QL_DBG_SIZE_ERR_FLAG; 4625 } 4626 return; 4627 } 4628 4629 static int 4630 ql_parse_template(qla_host_t *ha) 4631 { 4632 uint32_t num_of_entries, buff_level, e_cnt, esize; 4633 uint32_t rv = 0; 4634 char *dump_buff, *dbuff; 4635 int sane_start = 0, sane_end = 0; 4636 ql_minidump_template_hdr_t *template_hdr; 4637 ql_minidump_entry_t *entry; 4638 uint32_t capture_mask; 4639 uint32_t dump_size; 4640 4641 /* Setup parameters */ 4642 template_hdr = (ql_minidump_template_hdr_t *)ha->hw.mdump_template; 4643 4644 if (template_hdr->entry_type == TLHDR) 4645 sane_start = 1; 4646 4647 dump_buff = (char *) ha->hw.mdump_buffer; 4648 4649 num_of_entries = template_hdr->num_of_entries; 4650 4651 entry = (ql_minidump_entry_t *) ((char *)template_hdr 4652 + template_hdr->first_entry_offset ); 4653 4654 template_hdr->saved_state_array[QL_OCM0_ADDR_INDX] = 4655 template_hdr->ocm_window_array[ha->pci_func]; 4656 template_hdr->saved_state_array[QL_PCIE_FUNC_INDX] = ha->pci_func; 4657 4658 capture_mask = ha->hw.mdump_capture_mask; 4659 dump_size = ha->hw.mdump_buffer_size; 4660 4661 template_hdr->driver_capture_mask = capture_mask; 4662 4663 QL_DPRINT80(ha, (ha->pci_dev, 4664 "%s: sane_start = %d num_of_entries = %d " 4665 "capture_mask = 0x%x dump_size = %d \n", 4666 __func__, sane_start, num_of_entries, capture_mask, dump_size)); 4667 4668 for (buff_level = 0, e_cnt = 0; e_cnt < num_of_entries; e_cnt++) { 4669 /* 4670 * If the capture_mask of the entry does not match capture mask 4671 * skip the entry after marking the driver_flags indicator. 4672 */ 4673 4674 if (!(entry->hdr.entry_capture_mask & capture_mask)) { 4675 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG; 4676 entry = (ql_minidump_entry_t *) ((char *) entry 4677 + entry->hdr.entry_size); 4678 continue; 4679 } 4680 4681 /* 4682 * This is ONLY needed in implementations where 4683 * the capture buffer allocated is too small to capture 4684 * all of the required entries for a given capture mask. 4685 * We need to empty the buffer contents to a file 4686 * if possible, before processing the next entry 4687 * If the buff_full_flag is set, no further capture will happen 4688 * and all remaining non-control entries will be skipped. 4689 */ 4690 if (entry->hdr.entry_capture_size != 0) { 4691 if ((buff_level + entry->hdr.entry_capture_size) > 4692 dump_size) { 4693 /* Try to recover by emptying buffer to file */ 4694 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG; 4695 entry = (ql_minidump_entry_t *) ((char *) entry 4696 + entry->hdr.entry_size); 4697 continue; 4698 } 4699 } 4700 4701 /* 4702 * Decode the entry type and process it accordingly 4703 */ 4704 4705 switch (entry->hdr.entry_type) { 4706 case RDNOP: 4707 break; 4708 4709 case RDEND: 4710 sane_end++; 4711 break; 4712 4713 case RDCRB: 4714 dbuff = dump_buff + buff_level; 4715 esize = ql_rdcrb(ha, (void *)entry, (void *)dbuff); 4716 ql_entry_err_chk(entry, esize); 4717 buff_level += esize; 4718 break; 4719 4720 case POLLRD: 4721 dbuff = dump_buff + buff_level; 4722 esize = ql_pollrd(ha, (void *)entry, (void *)dbuff); 4723 ql_entry_err_chk(entry, esize); 4724 buff_level += esize; 4725 break; 4726 4727 case POLLRDMWR: 4728 dbuff = dump_buff + buff_level; 4729 esize = ql_pollrd_modify_write(ha, (void *)entry, 4730 (void *)dbuff); 4731 ql_entry_err_chk(entry, esize); 4732 buff_level += esize; 4733 break; 4734 4735 case L2ITG: 4736 case L2DTG: 4737 case L2DAT: 4738 case L2INS: 4739 dbuff = dump_buff + buff_level; 4740 esize = ql_L2Cache(ha, (void *)entry, (void *)dbuff); 4741 if (esize == -1) { 4742 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG; 4743 } else { 4744 ql_entry_err_chk(entry, esize); 4745 buff_level += esize; 4746 } 4747 break; 4748 4749 case L1DAT: 4750 case L1INS: 4751 dbuff = dump_buff + buff_level; 4752 esize = ql_L1Cache(ha, (void *)entry, (void *)dbuff); 4753 ql_entry_err_chk(entry, esize); 4754 buff_level += esize; 4755 break; 4756 4757 case RDOCM: 4758 dbuff = dump_buff + buff_level; 4759 esize = ql_rdocm(ha, (void *)entry, (void *)dbuff); 4760 ql_entry_err_chk(entry, esize); 4761 buff_level += esize; 4762 break; 4763 4764 case RDMEM: 4765 dbuff = dump_buff + buff_level; 4766 esize = ql_rdmem(ha, (void *)entry, (void *)dbuff); 4767 ql_entry_err_chk(entry, esize); 4768 buff_level += esize; 4769 break; 4770 4771 case BOARD: 4772 case RDROM: 4773 dbuff = dump_buff + buff_level; 4774 esize = ql_rdrom(ha, (void *)entry, (void *)dbuff); 4775 ql_entry_err_chk(entry, esize); 4776 buff_level += esize; 4777 break; 4778 4779 case RDMUX: 4780 dbuff = dump_buff + buff_level; 4781 esize = ql_rdmux(ha, (void *)entry, (void *)dbuff); 4782 ql_entry_err_chk(entry, esize); 4783 buff_level += esize; 4784 break; 4785 4786 case RDMUX2: 4787 dbuff = dump_buff + buff_level; 4788 esize = ql_rdmux2(ha, (void *)entry, (void *)dbuff); 4789 ql_entry_err_chk(entry, esize); 4790 buff_level += esize; 4791 break; 4792 4793 case QUEUE: 4794 dbuff = dump_buff + buff_level; 4795 esize = ql_rdqueue(ha, (void *)entry, (void *)dbuff); 4796 ql_entry_err_chk(entry, esize); 4797 buff_level += esize; 4798 break; 4799 4800 case CNTRL: 4801 if ((rv = ql_cntrl(ha, template_hdr, (void *)entry))) { 4802 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG; 4803 } 4804 break; 4805 default: 4806 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG; 4807 break; 4808 } 4809 /* next entry in the template */ 4810 entry = (ql_minidump_entry_t *) ((char *) entry 4811 + entry->hdr.entry_size); 4812 } 4813 4814 if (!sane_start || (sane_end > 1)) { 4815 device_printf(ha->pci_dev, 4816 "\n%s: Template configuration error. Check Template\n", 4817 __func__); 4818 } 4819 4820 QL_DPRINT80(ha, (ha->pci_dev, "%s: Minidump num of entries = %d\n", 4821 __func__, template_hdr->num_of_entries)); 4822 4823 return 0; 4824 } 4825 4826 /* 4827 * Read CRB operation. 4828 */ 4829 static uint32_t 4830 ql_rdcrb(qla_host_t *ha, ql_minidump_entry_rdcrb_t * crb_entry, 4831 uint32_t * data_buff) 4832 { 4833 int loop_cnt; 4834 int ret; 4835 uint32_t op_count, addr, stride, value = 0; 4836 4837 addr = crb_entry->addr; 4838 op_count = crb_entry->op_count; 4839 stride = crb_entry->addr_stride; 4840 4841 for (loop_cnt = 0; loop_cnt < op_count; loop_cnt++) { 4842 ret = ql_rdwr_indreg32(ha, addr, &value, 1); 4843 4844 if (ret) 4845 return (0); 4846 4847 *data_buff++ = addr; 4848 *data_buff++ = value; 4849 addr = addr + stride; 4850 } 4851 4852 /* 4853 * for testing purpose we return amount of data written 4854 */ 4855 return (op_count * (2 * sizeof(uint32_t))); 4856 } 4857 4858 /* 4859 * Handle L2 Cache. 4860 */ 4861 4862 static uint32_t 4863 ql_L2Cache(qla_host_t *ha, ql_minidump_entry_cache_t *cacheEntry, 4864 uint32_t * data_buff) 4865 { 4866 int i, k; 4867 int loop_cnt; 4868 int ret; 4869 4870 uint32_t read_value; 4871 uint32_t addr, read_addr, cntrl_addr, tag_reg_addr, cntl_value_w; 4872 uint32_t tag_value, read_cnt; 4873 volatile uint8_t cntl_value_r; 4874 long timeout; 4875 uint32_t data; 4876 4877 loop_cnt = cacheEntry->op_count; 4878 4879 read_addr = cacheEntry->read_addr; 4880 cntrl_addr = cacheEntry->control_addr; 4881 cntl_value_w = (uint32_t) cacheEntry->write_value; 4882 4883 tag_reg_addr = cacheEntry->tag_reg_addr; 4884 4885 tag_value = cacheEntry->init_tag_value; 4886 read_cnt = cacheEntry->read_addr_cnt; 4887 4888 for (i = 0; i < loop_cnt; i++) { 4889 ret = ql_rdwr_indreg32(ha, tag_reg_addr, &tag_value, 0); 4890 if (ret) 4891 return (0); 4892 4893 if (cacheEntry->write_value != 0) { 4894 4895 ret = ql_rdwr_indreg32(ha, cntrl_addr, 4896 &cntl_value_w, 0); 4897 if (ret) 4898 return (0); 4899 } 4900 4901 if (cacheEntry->poll_mask != 0) { 4902 4903 timeout = cacheEntry->poll_wait; 4904 4905 ret = ql_rdwr_indreg32(ha, cntrl_addr, &data, 1); 4906 if (ret) 4907 return (0); 4908 4909 cntl_value_r = (uint8_t)data; 4910 4911 while ((cntl_value_r & cacheEntry->poll_mask) != 0) { 4912 if (timeout) { 4913 qla_mdelay(__func__, 1); 4914 timeout--; 4915 } else 4916 break; 4917 4918 ret = ql_rdwr_indreg32(ha, cntrl_addr, 4919 &data, 1); 4920 if (ret) 4921 return (0); 4922 4923 cntl_value_r = (uint8_t)data; 4924 } 4925 if (!timeout) { 4926 /* Report timeout error. 4927 * core dump capture failed 4928 * Skip remaining entries. 4929 * Write buffer out to file 4930 * Use driver specific fields in template header 4931 * to report this error. 4932 */ 4933 return (-1); 4934 } 4935 } 4936 4937 addr = read_addr; 4938 for (k = 0; k < read_cnt; k++) { 4939 ret = ql_rdwr_indreg32(ha, addr, &read_value, 1); 4940 if (ret) 4941 return (0); 4942 4943 *data_buff++ = read_value; 4944 addr += cacheEntry->read_addr_stride; 4945 } 4946 4947 tag_value += cacheEntry->tag_value_stride; 4948 } 4949 4950 return (read_cnt * loop_cnt * sizeof(uint32_t)); 4951 } 4952 4953 /* 4954 * Handle L1 Cache. 4955 */ 4956 4957 static uint32_t 4958 ql_L1Cache(qla_host_t *ha, 4959 ql_minidump_entry_cache_t *cacheEntry, 4960 uint32_t *data_buff) 4961 { 4962 int ret; 4963 int i, k; 4964 int loop_cnt; 4965 4966 uint32_t read_value; 4967 uint32_t addr, read_addr, cntrl_addr, tag_reg_addr; 4968 uint32_t tag_value, read_cnt; 4969 uint32_t cntl_value_w; 4970 4971 loop_cnt = cacheEntry->op_count; 4972 4973 read_addr = cacheEntry->read_addr; 4974 cntrl_addr = cacheEntry->control_addr; 4975 cntl_value_w = (uint32_t) cacheEntry->write_value; 4976 4977 tag_reg_addr = cacheEntry->tag_reg_addr; 4978 4979 tag_value = cacheEntry->init_tag_value; 4980 read_cnt = cacheEntry->read_addr_cnt; 4981 4982 for (i = 0; i < loop_cnt; i++) { 4983 ret = ql_rdwr_indreg32(ha, tag_reg_addr, &tag_value, 0); 4984 if (ret) 4985 return (0); 4986 4987 ret = ql_rdwr_indreg32(ha, cntrl_addr, &cntl_value_w, 0); 4988 if (ret) 4989 return (0); 4990 4991 addr = read_addr; 4992 for (k = 0; k < read_cnt; k++) { 4993 ret = ql_rdwr_indreg32(ha, addr, &read_value, 1); 4994 if (ret) 4995 return (0); 4996 4997 *data_buff++ = read_value; 4998 addr += cacheEntry->read_addr_stride; 4999 } 5000 5001 tag_value += cacheEntry->tag_value_stride; 5002 } 5003 5004 return (read_cnt * loop_cnt * sizeof(uint32_t)); 5005 } 5006 5007 /* 5008 * Reading OCM memory 5009 */ 5010 5011 static uint32_t 5012 ql_rdocm(qla_host_t *ha, 5013 ql_minidump_entry_rdocm_t *ocmEntry, 5014 uint32_t *data_buff) 5015 { 5016 int i, loop_cnt; 5017 volatile uint32_t addr; 5018 volatile uint32_t value; 5019 5020 addr = ocmEntry->read_addr; 5021 loop_cnt = ocmEntry->op_count; 5022 5023 for (i = 0; i < loop_cnt; i++) { 5024 value = READ_REG32(ha, addr); 5025 *data_buff++ = value; 5026 addr += ocmEntry->read_addr_stride; 5027 } 5028 return (loop_cnt * sizeof(value)); 5029 } 5030 5031 /* 5032 * Read memory 5033 */ 5034 5035 static uint32_t 5036 ql_rdmem(qla_host_t *ha, 5037 ql_minidump_entry_rdmem_t *mem_entry, 5038 uint32_t *data_buff) 5039 { 5040 int ret; 5041 int i, loop_cnt; 5042 volatile uint32_t addr; 5043 q80_offchip_mem_val_t val; 5044 5045 addr = mem_entry->read_addr; 5046 5047 /* size in bytes / 16 */ 5048 loop_cnt = mem_entry->read_data_size / (sizeof(uint32_t) * 4); 5049 5050 for (i = 0; i < loop_cnt; i++) { 5051 ret = ql_rdwr_offchip_mem(ha, (addr & 0x0ffffffff), &val, 1); 5052 if (ret) 5053 return (0); 5054 5055 *data_buff++ = val.data_lo; 5056 *data_buff++ = val.data_hi; 5057 *data_buff++ = val.data_ulo; 5058 *data_buff++ = val.data_uhi; 5059 5060 addr += (sizeof(uint32_t) * 4); 5061 } 5062 5063 return (loop_cnt * (sizeof(uint32_t) * 4)); 5064 } 5065 5066 /* 5067 * Read Rom 5068 */ 5069 5070 static uint32_t 5071 ql_rdrom(qla_host_t *ha, 5072 ql_minidump_entry_rdrom_t *romEntry, 5073 uint32_t *data_buff) 5074 { 5075 int ret; 5076 int i, loop_cnt; 5077 uint32_t addr; 5078 uint32_t value; 5079 5080 addr = romEntry->read_addr; 5081 loop_cnt = romEntry->read_data_size; /* This is size in bytes */ 5082 loop_cnt /= sizeof(value); 5083 5084 for (i = 0; i < loop_cnt; i++) { 5085 ret = ql_rd_flash32(ha, addr, &value); 5086 if (ret) 5087 return (0); 5088 5089 *data_buff++ = value; 5090 addr += sizeof(value); 5091 } 5092 5093 return (loop_cnt * sizeof(value)); 5094 } 5095 5096 /* 5097 * Read MUX data 5098 */ 5099 5100 static uint32_t 5101 ql_rdmux(qla_host_t *ha, 5102 ql_minidump_entry_mux_t *muxEntry, 5103 uint32_t *data_buff) 5104 { 5105 int ret; 5106 int loop_cnt; 5107 uint32_t read_value, sel_value; 5108 uint32_t read_addr, select_addr; 5109 5110 select_addr = muxEntry->select_addr; 5111 sel_value = muxEntry->select_value; 5112 read_addr = muxEntry->read_addr; 5113 5114 for (loop_cnt = 0; loop_cnt < muxEntry->op_count; loop_cnt++) { 5115 ret = ql_rdwr_indreg32(ha, select_addr, &sel_value, 0); 5116 if (ret) 5117 return (0); 5118 5119 ret = ql_rdwr_indreg32(ha, read_addr, &read_value, 1); 5120 if (ret) 5121 return (0); 5122 5123 *data_buff++ = sel_value; 5124 *data_buff++ = read_value; 5125 5126 sel_value += muxEntry->select_value_stride; 5127 } 5128 5129 return (loop_cnt * (2 * sizeof(uint32_t))); 5130 } 5131 5132 static uint32_t 5133 ql_rdmux2(qla_host_t *ha, 5134 ql_minidump_entry_mux2_t *muxEntry, 5135 uint32_t *data_buff) 5136 { 5137 int ret; 5138 int loop_cnt; 5139 5140 uint32_t select_addr_1, select_addr_2; 5141 uint32_t select_value_1, select_value_2; 5142 uint32_t select_value_count, select_value_mask; 5143 uint32_t read_addr, read_value; 5144 5145 select_addr_1 = muxEntry->select_addr_1; 5146 select_addr_2 = muxEntry->select_addr_2; 5147 select_value_1 = muxEntry->select_value_1; 5148 select_value_2 = muxEntry->select_value_2; 5149 select_value_count = muxEntry->select_value_count; 5150 select_value_mask = muxEntry->select_value_mask; 5151 5152 read_addr = muxEntry->read_addr; 5153 5154 for (loop_cnt = 0; loop_cnt < select_value_count; loop_cnt++) { 5155 uint32_t temp_sel_val; 5156 5157 ret = ql_rdwr_indreg32(ha, select_addr_1, &select_value_1, 0); 5158 if (ret) 5159 return (0); 5160 5161 temp_sel_val = select_value_1 & select_value_mask; 5162 5163 ret = ql_rdwr_indreg32(ha, select_addr_2, &temp_sel_val, 0); 5164 if (ret) 5165 return (0); 5166 5167 ret = ql_rdwr_indreg32(ha, read_addr, &read_value, 1); 5168 if (ret) 5169 return (0); 5170 5171 *data_buff++ = temp_sel_val; 5172 *data_buff++ = read_value; 5173 5174 ret = ql_rdwr_indreg32(ha, select_addr_1, &select_value_2, 0); 5175 if (ret) 5176 return (0); 5177 5178 temp_sel_val = select_value_2 & select_value_mask; 5179 5180 ret = ql_rdwr_indreg32(ha, select_addr_2, &temp_sel_val, 0); 5181 if (ret) 5182 return (0); 5183 5184 ret = ql_rdwr_indreg32(ha, read_addr, &read_value, 1); 5185 if (ret) 5186 return (0); 5187 5188 *data_buff++ = temp_sel_val; 5189 *data_buff++ = read_value; 5190 5191 select_value_1 += muxEntry->select_value_stride; 5192 select_value_2 += muxEntry->select_value_stride; 5193 } 5194 5195 return (loop_cnt * (4 * sizeof(uint32_t))); 5196 } 5197 5198 /* 5199 * Handling Queue State Reads. 5200 */ 5201 5202 static uint32_t 5203 ql_rdqueue(qla_host_t *ha, 5204 ql_minidump_entry_queue_t *queueEntry, 5205 uint32_t *data_buff) 5206 { 5207 int ret; 5208 int loop_cnt, k; 5209 uint32_t read_value; 5210 uint32_t read_addr, read_stride, select_addr; 5211 uint32_t queue_id, read_cnt; 5212 5213 read_cnt = queueEntry->read_addr_cnt; 5214 read_stride = queueEntry->read_addr_stride; 5215 select_addr = queueEntry->select_addr; 5216 5217 for (loop_cnt = 0, queue_id = 0; loop_cnt < queueEntry->op_count; 5218 loop_cnt++) { 5219 ret = ql_rdwr_indreg32(ha, select_addr, &queue_id, 0); 5220 if (ret) 5221 return (0); 5222 5223 read_addr = queueEntry->read_addr; 5224 5225 for (k = 0; k < read_cnt; k++) { 5226 ret = ql_rdwr_indreg32(ha, read_addr, &read_value, 1); 5227 if (ret) 5228 return (0); 5229 5230 *data_buff++ = read_value; 5231 read_addr += read_stride; 5232 } 5233 5234 queue_id += queueEntry->queue_id_stride; 5235 } 5236 5237 return (loop_cnt * (read_cnt * sizeof(uint32_t))); 5238 } 5239 5240 /* 5241 * Handling control entries. 5242 */ 5243 5244 static uint32_t 5245 ql_cntrl(qla_host_t *ha, 5246 ql_minidump_template_hdr_t *template_hdr, 5247 ql_minidump_entry_cntrl_t *crbEntry) 5248 { 5249 int ret; 5250 int count; 5251 uint32_t opcode, read_value, addr, entry_addr; 5252 long timeout; 5253 5254 entry_addr = crbEntry->addr; 5255 5256 for (count = 0; count < crbEntry->op_count; count++) { 5257 opcode = crbEntry->opcode; 5258 5259 if (opcode & QL_DBG_OPCODE_WR) { 5260 ret = ql_rdwr_indreg32(ha, entry_addr, 5261 &crbEntry->value_1, 0); 5262 if (ret) 5263 return (0); 5264 5265 opcode &= ~QL_DBG_OPCODE_WR; 5266 } 5267 5268 if (opcode & QL_DBG_OPCODE_RW) { 5269 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 1); 5270 if (ret) 5271 return (0); 5272 5273 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 0); 5274 if (ret) 5275 return (0); 5276 5277 opcode &= ~QL_DBG_OPCODE_RW; 5278 } 5279 5280 if (opcode & QL_DBG_OPCODE_AND) { 5281 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 1); 5282 if (ret) 5283 return (0); 5284 5285 read_value &= crbEntry->value_2; 5286 opcode &= ~QL_DBG_OPCODE_AND; 5287 5288 if (opcode & QL_DBG_OPCODE_OR) { 5289 read_value |= crbEntry->value_3; 5290 opcode &= ~QL_DBG_OPCODE_OR; 5291 } 5292 5293 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 0); 5294 if (ret) 5295 return (0); 5296 } 5297 5298 if (opcode & QL_DBG_OPCODE_OR) { 5299 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 1); 5300 if (ret) 5301 return (0); 5302 5303 read_value |= crbEntry->value_3; 5304 5305 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 0); 5306 if (ret) 5307 return (0); 5308 5309 opcode &= ~QL_DBG_OPCODE_OR; 5310 } 5311 5312 if (opcode & QL_DBG_OPCODE_POLL) { 5313 opcode &= ~QL_DBG_OPCODE_POLL; 5314 timeout = crbEntry->poll_timeout; 5315 addr = entry_addr; 5316 5317 ret = ql_rdwr_indreg32(ha, addr, &read_value, 1); 5318 if (ret) 5319 return (0); 5320 5321 while ((read_value & crbEntry->value_2) 5322 != crbEntry->value_1) { 5323 if (timeout) { 5324 qla_mdelay(__func__, 1); 5325 timeout--; 5326 } else 5327 break; 5328 5329 ret = ql_rdwr_indreg32(ha, addr, 5330 &read_value, 1); 5331 if (ret) 5332 return (0); 5333 } 5334 5335 if (!timeout) { 5336 /* 5337 * Report timeout error. 5338 * core dump capture failed 5339 * Skip remaining entries. 5340 * Write buffer out to file 5341 * Use driver specific fields in template header 5342 * to report this error. 5343 */ 5344 return (-1); 5345 } 5346 } 5347 5348 if (opcode & QL_DBG_OPCODE_RDSTATE) { 5349 /* 5350 * decide which address to use. 5351 */ 5352 if (crbEntry->state_index_a) { 5353 addr = template_hdr->saved_state_array[ 5354 crbEntry-> state_index_a]; 5355 } else { 5356 addr = entry_addr; 5357 } 5358 5359 ret = ql_rdwr_indreg32(ha, addr, &read_value, 1); 5360 if (ret) 5361 return (0); 5362 5363 template_hdr->saved_state_array[crbEntry->state_index_v] 5364 = read_value; 5365 opcode &= ~QL_DBG_OPCODE_RDSTATE; 5366 } 5367 5368 if (opcode & QL_DBG_OPCODE_WRSTATE) { 5369 /* 5370 * decide which value to use. 5371 */ 5372 if (crbEntry->state_index_v) { 5373 read_value = template_hdr->saved_state_array[ 5374 crbEntry->state_index_v]; 5375 } else { 5376 read_value = crbEntry->value_1; 5377 } 5378 /* 5379 * decide which address to use. 5380 */ 5381 if (crbEntry->state_index_a) { 5382 addr = template_hdr->saved_state_array[ 5383 crbEntry-> state_index_a]; 5384 } else { 5385 addr = entry_addr; 5386 } 5387 5388 ret = ql_rdwr_indreg32(ha, addr, &read_value, 0); 5389 if (ret) 5390 return (0); 5391 5392 opcode &= ~QL_DBG_OPCODE_WRSTATE; 5393 } 5394 5395 if (opcode & QL_DBG_OPCODE_MDSTATE) { 5396 /* Read value from saved state using index */ 5397 read_value = template_hdr->saved_state_array[ 5398 crbEntry->state_index_v]; 5399 5400 read_value <<= crbEntry->shl; /*Shift left operation */ 5401 read_value >>= crbEntry->shr; /*Shift right operation */ 5402 5403 if (crbEntry->value_2) { 5404 /* check if AND mask is provided */ 5405 read_value &= crbEntry->value_2; 5406 } 5407 5408 read_value |= crbEntry->value_3; /* OR operation */ 5409 read_value += crbEntry->value_1; /* increment op */ 5410 5411 /* Write value back to state area. */ 5412 5413 template_hdr->saved_state_array[crbEntry->state_index_v] 5414 = read_value; 5415 opcode &= ~QL_DBG_OPCODE_MDSTATE; 5416 } 5417 5418 entry_addr += crbEntry->addr_stride; 5419 } 5420 5421 return (0); 5422 } 5423 5424 /* 5425 * Handling rd poll entry. 5426 */ 5427 5428 static uint32_t 5429 ql_pollrd(qla_host_t *ha, ql_minidump_entry_pollrd_t *entry, 5430 uint32_t *data_buff) 5431 { 5432 int ret; 5433 int loop_cnt; 5434 uint32_t op_count, select_addr, select_value_stride, select_value; 5435 uint32_t read_addr, poll, mask, data; 5436 uint32_t wait_count = 0; 5437 5438 select_addr = entry->select_addr; 5439 read_addr = entry->read_addr; 5440 select_value = entry->select_value; 5441 select_value_stride = entry->select_value_stride; 5442 op_count = entry->op_count; 5443 poll = entry->poll; 5444 mask = entry->mask; 5445 5446 for (loop_cnt = 0; loop_cnt < op_count; loop_cnt++) { 5447 ret = ql_rdwr_indreg32(ha, select_addr, &select_value, 0); 5448 if (ret) 5449 return (0); 5450 5451 wait_count = 0; 5452 5453 while (wait_count < poll) { 5454 uint32_t temp; 5455 5456 ret = ql_rdwr_indreg32(ha, select_addr, &temp, 1); 5457 if (ret) 5458 return (0); 5459 5460 if ( (temp & mask) != 0 ) { 5461 break; 5462 } 5463 wait_count++; 5464 } 5465 5466 if (wait_count == poll) { 5467 device_printf(ha->pci_dev, 5468 "%s: Error in processing entry\n", __func__); 5469 device_printf(ha->pci_dev, 5470 "%s: wait_count <0x%x> poll <0x%x>\n", 5471 __func__, wait_count, poll); 5472 return 0; 5473 } 5474 5475 ret = ql_rdwr_indreg32(ha, read_addr, &data, 1); 5476 if (ret) 5477 return (0); 5478 5479 *data_buff++ = select_value; 5480 *data_buff++ = data; 5481 select_value = select_value + select_value_stride; 5482 } 5483 5484 /* 5485 * for testing purpose we return amount of data written 5486 */ 5487 return (loop_cnt * (2 * sizeof(uint32_t))); 5488 } 5489 5490 /* 5491 * Handling rd modify write poll entry. 5492 */ 5493 5494 static uint32_t 5495 ql_pollrd_modify_write(qla_host_t *ha, 5496 ql_minidump_entry_rd_modify_wr_with_poll_t *entry, 5497 uint32_t *data_buff) 5498 { 5499 int ret; 5500 uint32_t addr_1, addr_2, value_1, value_2, data; 5501 uint32_t poll, mask, modify_mask; 5502 uint32_t wait_count = 0; 5503 5504 addr_1 = entry->addr_1; 5505 addr_2 = entry->addr_2; 5506 value_1 = entry->value_1; 5507 value_2 = entry->value_2; 5508 5509 poll = entry->poll; 5510 mask = entry->mask; 5511 modify_mask = entry->modify_mask; 5512 5513 ret = ql_rdwr_indreg32(ha, addr_1, &value_1, 0); 5514 if (ret) 5515 return (0); 5516 5517 wait_count = 0; 5518 while (wait_count < poll) { 5519 uint32_t temp; 5520 5521 ret = ql_rdwr_indreg32(ha, addr_1, &temp, 1); 5522 if (ret) 5523 return (0); 5524 5525 if ( (temp & mask) != 0 ) { 5526 break; 5527 } 5528 wait_count++; 5529 } 5530 5531 if (wait_count == poll) { 5532 device_printf(ha->pci_dev, "%s Error in processing entry\n", 5533 __func__); 5534 } else { 5535 ret = ql_rdwr_indreg32(ha, addr_2, &data, 1); 5536 if (ret) 5537 return (0); 5538 5539 data = (data & modify_mask); 5540 5541 ret = ql_rdwr_indreg32(ha, addr_2, &data, 0); 5542 if (ret) 5543 return (0); 5544 5545 ret = ql_rdwr_indreg32(ha, addr_1, &value_2, 0); 5546 if (ret) 5547 return (0); 5548 5549 /* Poll again */ 5550 wait_count = 0; 5551 while (wait_count < poll) { 5552 uint32_t temp; 5553 5554 ret = ql_rdwr_indreg32(ha, addr_1, &temp, 1); 5555 if (ret) 5556 return (0); 5557 5558 if ( (temp & mask) != 0 ) { 5559 break; 5560 } 5561 wait_count++; 5562 } 5563 *data_buff++ = addr_2; 5564 *data_buff++ = data; 5565 } 5566 5567 /* 5568 * for testing purpose we return amount of data written 5569 */ 5570 return (2 * sizeof(uint32_t)); 5571 } 5572