1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 32 #ifndef _PCICS_REG_DRIVER_H 33 #define _PCICS_REG_DRIVER_H 34 35 /* offset of configuration space in the pci core register */ 36 #ifndef __EXTRACT__LINUX__ 37 #define PCICFG_OFFSET 0x2000 38 #endif 39 #define PCICFG_VENDOR_ID_OFFSET 0x00 40 #define PCICFG_DEVICE_ID_OFFSET 0x02 41 #define PCICFG_COMMAND_OFFSET 0x04 42 #define PCICFG_COMMAND_IO_SPACE (1<<0) 43 #define PCICFG_COMMAND_MEM_SPACE (1<<1) 44 #define PCICFG_COMMAND_BUS_MASTER (1<<2) 45 #define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3) 46 #define PCICFG_COMMAND_MWI_CYCLES (1<<4) 47 #define PCICFG_COMMAND_VGA_SNOOP (1<<5) 48 #define PCICFG_COMMAND_PERR_ENA (1<<6) 49 #define PCICFG_COMMAND_STEPPING (1<<7) 50 #define PCICFG_COMMAND_SERR_ENA (1<<8) 51 #define PCICFG_COMMAND_FAST_B2B (1<<9) 52 #define PCICFG_COMMAND_INT_DISABLE (1<<10) 53 #define PCICFG_COMMAND_RESERVED (0x1f<<11) 54 #define PCICFG_STATUS_OFFSET 0x06 55 #define PCICFG_REVISION_ID_OFFSET 0x08 56 #define PCICFG_REVESION_ID_MASK 0xff 57 #define PCICFG_REVESION_ID_ERROR_VAL 0xff 58 #define PCICFG_CACHE_LINE_SIZE 0x0c 59 #define PCICFG_LATENCY_TIMER 0x0d 60 #define PCICFG_HEADER_TYPE 0x0e 61 #define PCICFG_HEADER_TYPE_NORMAL 0 62 #define PCICFG_HEADER_TYPE_BRIDGE 1 63 #define PCICFG_HEADER_TYPE_CARDBUS 2 64 #define PCICFG_BAR_1_LOW 0x10 65 #define PCICFG_BAR_1_HIGH 0x14 66 #define PCICFG_BAR_2_LOW 0x18 67 #define PCICFG_BAR_2_HIGH 0x1c 68 #define PCICFG_BAR_3_LOW 0x20 69 #define PCICFG_BAR_3_HIGH 0x24 70 #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c 71 #define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e 72 #define PCICFG_INT_LINE 0x3c 73 #define PCICFG_INT_PIN 0x3d 74 #define PCICFG_PM_CAPABILITY 0x48 75 #define PCICFG_PM_CAPABILITY_VERSION (0x3<<16) 76 #define PCICFG_PM_CAPABILITY_CLOCK (1<<19) 77 #define PCICFG_PM_CAPABILITY_RESERVED (1<<20) 78 #define PCICFG_PM_CAPABILITY_DSI (1<<21) 79 #define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22) 80 #define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25) 81 #define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26) 82 #define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27) 83 #define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28) 84 #define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29) 85 #define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30) 86 #define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31) 87 #define PCICFG_PM_CSR_OFFSET 0x4c 88 #define PCICFG_PM_CSR_STATE (0x3<<0) 89 #define PCICFG_PM_CSR_PME_ENABLE (1<<8) 90 #define PCICFG_PM_CSR_PME_STATUS (1<<15) 91 #define PCICFG_MSI_CAP_ID_OFFSET 0x58 92 #define PCICFG_MSI_CONTROL_ENABLE (0x1<<16) 93 #define PCICFG_MSI_CONTROL_MCAP (0x7<<17) 94 #define PCICFG_MSI_CONTROL_MENA (0x7<<20) 95 #define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23) 96 #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24) 97 #define PCICFG_GRC_ADDRESS 0x78 98 #define PCICFG_GRC_DATA 0x80 99 #define PCICFG_ME_REGISTER 0x98 100 #define PCICFG_MSIX_CAP_ID_OFFSET 0xa0 101 #define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16) 102 #define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27) 103 #define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30) 104 #define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31) 105 106 #define PCICFG_DEVICE_CONTROL 0xb4 107 #define PCICFG_DEVICE_CONTROL_NP_TRANSACTION_PEND (1<<21) 108 #define PCICFG_DEVICE_STATUS 0xb6 109 #define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0) 110 #define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1) 111 #define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2) 112 #define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3) 113 #define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4) 114 #define PCICFG_DEVICE_STATUS_NO_PEND (1<<5) 115 #define PCICFG_LINK_CONTROL 0xbc 116 #define PCICFG_DEVICE_STATUS_CONTROL_2 (0xd4) 117 #define PCICFG_DEVICE_STATUS_CONTROL_2_ATOMIC_REQ_ENABLE (1<<6) 118 119 /* config_2 offset */ 120 #define GRC_CONFIG_2_SIZE_REG 0x408 121 #define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) 122 #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) 123 #define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) 124 #define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) 125 #define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) 126 #define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) 127 #define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) 128 #define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) 129 #define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) 130 #define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) 131 #define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) 132 #define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) 133 #define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) 134 #define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) 135 #define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) 136 #define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) 137 #define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) 138 #define PCI_CONFIG_2_BAR1_64ENA (1L<<4) 139 #define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) 140 #define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) 141 #define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) 142 #define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) 143 #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) 144 #define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8) 145 #define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8) 146 #define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8) 147 #define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8) 148 #define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8) 149 #define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8) 150 #define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8) 151 #define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8) 152 #define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8) 153 #define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8) 154 #define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8) 155 #define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8) 156 #define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8) 157 #define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8) 158 #define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8) 159 #define PCI_CONFIG_2_BAR_PREFETCH (1L<<16) 160 #define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17) 161 162 /* config_3 offset */ 163 #define GRC_CONFIG_3_SIZE_REG 0x40c 164 #define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) 165 #define PCI_CONFIG_3_FORCE_PME (1L<<24) 166 #define PCI_CONFIG_3_PME_STATUS (1L<<25) 167 #define PCI_CONFIG_3_PME_ENABLE (1L<<26) 168 #define PCI_CONFIG_3_PM_STATE (0x3L<<27) 169 #define PCI_CONFIG_3_VAUX_PRESET (1L<<30) 170 #define PCI_CONFIG_3_PCI_POWER (1L<<31) 171 172 #define GRC_REG_DEVICE_CONTROL 0x4d8 173 174 /* When VF Enable is cleared(after it was previously set), 175 * this register will read a value of 1, indicating that all the 176 * VFs that belong to this PF should be flushed. 177 * Software should clear this bit within 1 second of VF Enable 178 * being set by writing a 1 to it, so that VFs are visible to the system 179 * again.WC 180 */ 181 #define PCIE_SRIOV_DISABLE_IN_PROGRESS (1 << 29) 182 183 /* When FLR is initiated, this register will read a value of 1 indicating 184 * that the Function is in FLR state. Func can be brought out of FLR state 185 * either bywriting 1 to this register (at least 50 ms after FLR was 186 * initiated),or it can also be cleared automatically after 55 ms if 187 * auto_clear bit in private reg space is set. This bit also exists in 188 * VF register space WC 189 */ 190 #define PCIE_FLR_IN_PROGRESS (1 << 27) 191 192 #define GRC_BAR2_CONFIG 0x4e0 193 #define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0) 194 #define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0) 195 #define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0) 196 #define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0) 197 #define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0) 198 #define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0) 199 #define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0) 200 #define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0) 201 #define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0) 202 #define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0) 203 #define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0) 204 #define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0) 205 #define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0) 206 #define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0) 207 #define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0) 208 #define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0) 209 #define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0) 210 #define PCI_CONFIG_2_BAR2_64ENA (1L<<4) 211 212 #define GRC_BAR3_CONFIG 0x4f4 213 #define PCI_CONFIG_2_BAR3_SIZE (0xfL<<0) 214 #define PCI_CONFIG_2_BAR3_SIZE_DISABLED (0L<<0) 215 #define PCI_CONFIG_2_BAR3_SIZE_64K (1L<<0) 216 #define PCI_CONFIG_2_BAR3_SIZE_128K (2L<<0) 217 #define PCI_CONFIG_2_BAR3_SIZE_256K (3L<<0) 218 #define PCI_CONFIG_2_BAR3_SIZE_512K (4L<<0) 219 #define PCI_CONFIG_2_BAR3_SIZE_1M (5L<<0) 220 #define PCI_CONFIG_2_BAR3_SIZE_2M (6L<<0) 221 #define PCI_CONFIG_2_BAR3_SIZE_4M (7L<<0) 222 #define PCI_CONFIG_2_BAR3_SIZE_8M (8L<<0) 223 #define PCI_CONFIG_2_BAR3_SIZE_16M (9L<<0) 224 #define PCI_CONFIG_2_BAR3_SIZE_32M (10L<<0) 225 #define PCI_CONFIG_2_BAR3_SIZE_64M (11L<<0) 226 #define PCI_CONFIG_2_BAR3_SIZE_128M (12L<<0) 227 #define PCI_CONFIG_2_BAR3_SIZE_256M (13L<<0) 228 #define PCI_CONFIG_2_BAR3_SIZE_512M (14L<<0) 229 #define PCI_CONFIG_2_BAR3_SIZE_1G (15L<<0) 230 #define PCI_CONFIG_2_BAR3_64ENA (1L<<4) 231 #define PCI_PM_DATA_A 0x410 232 #define PCI_PM_DATA_B 0x414 233 #define PCI_ID_VAL1 0x434 234 #define PCI_ID_VAL2 0x438 235 #define PCI_ID_VAL3 0x43c 236 #define PCI_ID_VAL3_REVISION_ID_ERROR (0xffL<<24) 237 #define GRC_CONFIG_REG_VF_BAR_REG_1 0x608 238 #define GRC_CONFIG_REG_VF_BAR_REG_BAR0_SIZE 0xf 239 #define GRC_CONFIG_REG_VF_MSIX_CONTROL 0x61C 240 241 /* This field resides in VF only and does not exist in PF. 242 * This register controls the read value of the MSIX_CONTROL[10:0] register 243 * in the VF configuration space. A value of "00000000011" indicates 244 * a table size of 4. The value is controlled by IOV_MSIX_TBL_SIZ 245 * define in version.v 246 */ 247 #define GRC_CR_VF_MSIX_CTRL_VF_MSIX_TBL_SIZE_MASK 0x3F 248 #ifndef __EXTRACT__LINUX__ 249 #define GRC_CONFIG_REG_PF_INIT_VF 0x624 250 251 /* First VF_NUM for PF is encoded in this register. 252 * The number of VFs assigned to a PF is assumed to be a multiple of 8. 253 * Software should program these bits based on Total Number of VFs programmed 254 * for each PF. 255 * Since registers from 0x000-0x7ff are spilt across functions, each PF will 256 * have the same location for the same 4 bits 257 */ 258 #define GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK 0xff 259 #endif 260 #define PXPCS_TL_CONTROL_5 0x814 261 #define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN (1 << 29) /*WC*/ 262 #define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN (1 << 28) /*WC*/ 263 #define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN (1 << 27) /*WC*/ 264 #define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN (1 << 26) /*WC*/ 265 #define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR (1 << 25) /*WC*/ 266 #define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW (1 << 24) /*WC*/ 267 #define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN (1 << 23) /*RO*/ 268 #define PXPCS_TL_CONTROL_5_DL_ERR_ATTN (1 << 22) /*RO*/ 269 #define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE (1 << 21) /*WC*/ 270 #define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG (1 << 20) /*WC*/ 271 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1 (1 << 19) /*WC*/ 272 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 (1 << 18) /*WC*/ 273 #define PXPCS_TL_CONTROL_5_ERR_ECRC1 (1 << 17) /*WC*/ 274 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1 (1 << 16) /*WC*/ 275 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1 (1 << 15) /*WC*/ 276 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1 (1 << 14) /*WC*/ 277 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1 (1 << 13) /*WC*/ 278 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1 (1 << 12) /*WC*/ 279 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1 (1 << 11) /*WC*/ 280 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1 (1 << 10) /*WC*/ 281 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT (1 << 9) /*WC*/ 282 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT (1 << 8) /*WC*/ 283 #define PXPCS_TL_CONTROL_5_ERR_ECRC (1 << 7) /*WC*/ 284 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP (1 << 6) /*WC*/ 285 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW (1 << 5) /*WC*/ 286 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL (1 << 4) /*WC*/ 287 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT (1 << 3) /*WC*/ 288 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT (1 << 2) /*WC*/ 289 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL (1 << 1) /*WC*/ 290 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP (1 << 0) /*WC*/ 291 #define PXPCS_TL_FUNC345_STAT 0x854 292 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4 (1 << 29) /* WC */ 293 294 /*Unsupported Request Error Status in function4, if set, generate 295 *pcie_err_attn output when this error is seen. WC 296 */ 297 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 (1 << 28) 298 299 /*ECRC Error TLP Status Status in function 4, if set, 300 *generate pcie_err_attn output when this error is seen..WC 301 */ 302 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC4 (1 << 27) 303 304 /*Malformed TLP Status Status in function 4, if set, 305 *generate pcie_err_attn output when this error is seen..WC 306 */ 307 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4 (1 << 26) 308 309 /*Receiver Overflow Status Status in function 4, if set, 310 *generate pcie_err_attn output when this error is seen..WC 311 */ 312 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4 (1 << 25) 313 314 /*Unexpected Completion Status Status in function 4, if set, 315 *generate pcie_err_attn output when this error is seen..WC 316 */ 317 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4 (1 << 24) 318 319 /* Receive UR Statusin function 4. If set, generate pcie_err_attn output 320 * when this error is seen. WC 321 */ 322 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4 (1 << 23) 323 324 /* Completer Timeout Status Status in function 4, if set, 325 * generate pcie_err_attn output when this error is seen..WC 326 */ 327 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4 (1 << 22) 328 329 /* Flow Control Protocol Error Status Status in function 4, 330 * if set, generate pcie_err_attn output when this error is seen. 331 * WC 332 */ 333 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4 (1 << 21) 334 335 /* Poisoned Error Status Status in function 4, if set, generate 336 * pcie_err_attn output when this error is seen..WC 337 */ 338 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4 (1 << 20) 339 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3 (1 << 19) /* WC */ 340 341 /* Unsupported Request Error Status in function3, if set, generate 342 * pcie_err_attn output when this error is seen..WC 343 */ 344 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 (1 << 18) 345 346 /* ECRC Error TLP Status Status in function 3, if set, generate 347 * pcie_err_attn output when this error is seen.. WC 348 */ 349 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC3 (1 << 17) 350 351 /* Malformed TLP Status Status in function 3, if set, generate 352 * pcie_err_attn output when this error is seen..WC 353 */ 354 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3 (1 << 16) 355 356 /* Receiver Overflow Status Status in function 3, if set, generate 357 * pcie_err_attn output when this error is seen..WC 358 */ 359 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3 (1 << 15) 360 361 /* Unexpected Completion Status Status in function 3, if set, generate 362 * pcie_err_attn output when this error is seen. WC 363 */ 364 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3 (1 << 14) 365 366 /* Receive UR Statusin function 3. If set, generate pcie_err_attn output 367 * when this error is seen. WC 368 */ 369 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3 (1 << 13) 370 371 /* Completer Timeout Status Status in function 3, if set, generate 372 * pcie_err_attn output when this error is seen..WC 373 */ 374 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3 (1 << 12) 375 376 /* Flow Control Protocol Error Status Status in function 3, if set, 377 * generate pcie_err_attn output when this error is seen..WC 378 */ 379 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3 (1 << 11) 380 381 /* Poisoned Error Status Status in function 3, if set, generate 382 * pcie_err_attn output when this error is seen..WC 383 */ 384 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3 (1 << 10) 385 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2 (1 << 9) /* WC */ 386 387 /* Unsupported Request Error Status for Function 2, if set, 388 * generate pcie_err_attn output when this error is seen. WC 389 */ 390 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2 (1 << 8) 391 392 /* ECRC Error TLP Status Status for Function 2, if set, generate 393 * pcie_err_attn output when this error is seen..WC 394 */ 395 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC2 (1 << 7) 396 397 /* Malformed TLP Status Status for Function 2, if set, generate 398 * pcie_err_attn output when this error is seen.. WC 399 */ 400 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2 (1 << 6) 401 402 /* Receiver Overflow Status Status for Function 2, if set, generate 403 * pcie_err_attn output when this error is seen.. WC 404 */ 405 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2 (1 << 5) 406 407 /* Unexpected Completion Status Status for Function 2, if set, generate 408 * pcie_err_attn output when this error is seen. WC 409 */ 410 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2 (1 << 4) 411 412 /* Receive UR Statusfor Function 2. If set, generate pcie_err_attn output 413 * when this error is seen. WC 414 */ 415 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2 (1 << 3) 416 417 /* Completer Timeout Status Status for Function 2, if set, generate 418 * pcie_err_attn output when this error is seen. WC 419 */ 420 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2 (1 << 2) 421 422 /* Flow Control Protocol Error Status Status for Function 2, if set, 423 * generate pcie_err_attn output when this error is seen. WC 424 */ 425 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2 (1 << 1) 426 427 /* Poisoned Error Status Status for Function 2, if set, generate 428 * pcie_err_attn output when this error is seen.. WC 429 */ 430 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2 (1 << 0) 431 #define PXPCS_TL_FUNC678_STAT 0x85C 432 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7 (1 << 29) /* WC */ 433 434 /* Unsupported Request Error Status in function7, if set, generate 435 * pcie_err_attn output when this error is seen. WC 436 */ 437 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 (1 << 28) 438 439 /* ECRC Error TLP Status Status in function 7, if set, generate 440 * pcie_err_attn output when this error is seen.. WC 441 */ 442 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC7 (1 << 27) 443 444 /* Malformed TLP Status Status in function 7, if set, generate 445 * pcie_err_attn output when this error is seen.. WC 446 */ 447 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7 (1 << 26) 448 449 /* Receiver Overflow Status Status in function 7, if set, generate 450 * pcie_err_attn output when this error is seen.. WC 451 */ 452 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7 (1 << 25) 453 454 /* Unexpected Completion Status Status in function 7, if set, generate 455 * pcie_err_attn output when this error is seen. WC 456 */ 457 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7 (1 << 24) 458 459 /* Receive UR Statusin function 7. If set, generate pcie_err_attn 460 * output when this error is seen. WC 461 */ 462 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7 (1 << 23) 463 464 /* Completer Timeout Status Status in function 7, if set, generate 465 * pcie_err_attn output when this error is seen. WC 466 */ 467 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7 (1 << 22) 468 469 /* Flow Control Protocol Error Status Status in function 7, if set, 470 * generate pcie_err_attn output when this error is seen. WC 471 */ 472 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7 (1 << 21) 473 474 /* Poisoned Error Status Status in function 7, if set, 475 * generate pcie_err_attn output when this error is seen.. WC 476 */ 477 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7 (1 << 20) 478 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6 (1 << 19) /* WC */ 479 480 /* Unsupported Request Error Status in function6, if set, generate 481 * pcie_err_attn output when this error is seen. WC 482 */ 483 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 (1 << 18) 484 485 /* ECRC Error TLP Status Status in function 6, if set, generate 486 * pcie_err_attn output when this error is seen.. WC 487 */ 488 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC6 (1 << 17) 489 490 /* Malformed TLP Status Status in function 6, if set, generate 491 * pcie_err_attn output when this error is seen.. WC 492 */ 493 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6 (1 << 16) 494 495 /* Receiver Overflow Status Status in function 6, if set, generate 496 * pcie_err_attn output when this error is seen.. WC 497 */ 498 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6 (1 << 15) 499 500 /* Unexpected Completion Status Status in function 6, if set, 501 * generate pcie_err_attn output when this error is seen. WC 502 */ 503 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6 (1 << 14) 504 505 /* Receive UR Statusin function 6. If set, generate pcie_err_attn 506 * output when this error is seen. WC 507 */ 508 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6 (1 << 13) 509 510 /* Completer Timeout Status Status in function 6, if set, generate 511 * pcie_err_attn output when this error is seen. WC 512 */ 513 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6 (1 << 12) 514 515 /* Flow Control Protocol Error Status Status in function 6, if set, 516 * generate pcie_err_attn output when this error is seen. WC 517 */ 518 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6 (1 << 11) 519 520 /* Poisoned Error Status Status in function 6, if set, generate 521 * pcie_err_attn output when this error is seen.. WC 522 */ 523 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6 (1 << 10) 524 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5 (1 << 9) /* WC */ 525 526 /* Unsupported Request Error Status for Function 5, if set, 527 * generate pcie_err_attn output when this error is seen. WC 528 */ 529 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5 (1 << 8) 530 531 /* ECRC Error TLP Status Status for Function 5, if set, generate 532 * pcie_err_attn output when this error is seen.. WC 533 */ 534 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC5 (1 << 7) 535 536 /* Malformed TLP Status Status for Function 5, if set, generate 537 * pcie_err_attn output when this error is seen.. WC 538 */ 539 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5 (1 << 6) 540 541 /* Receiver Overflow Status Status for Function 5, if set, generate 542 * pcie_err_attn output when this error is seen.. WC 543 */ 544 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5 (1 << 5) 545 546 /* Unexpected Completion Status Status for Function 5, if set, generate 547 * pcie_err_attn output when this error is seen. WC 548 */ 549 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5 (1 << 4) 550 551 /* Receive UR Statusfor Function 5. If set, generate pcie_err_attn output 552 * when this error is seen. WC 553 */ 554 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5 (1 << 3) 555 556 /* Completer Timeout Status Status for Function 5, if set, generate 557 * pcie_err_attn output when this error is seen. WC 558 */ 559 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5 (1 << 2) 560 561 /* Flow Control Protocol Error Status Status for Function 5, if set, 562 * generate pcie_err_attn output when this error is seen. WC 563 */ 564 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5 (1 << 1) 565 566 /* Poisoned Error Status Status for Function 5, if set, 567 * generate pcie_err_attn output when this error is seen.. WC 568 */ 569 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5 (1 << 0) 570 571 /* PCI CAPABILITIES 572 */ 573 574 #define PCI_CAP_PCIE 0x10 /*PCIe capability ID*/ 575 576 #define PCIE_DEV_CAPS 0x04 577 #ifndef PCIE_DEV_CAPS_FLR_CAPABILITY 578 #define PCIE_DEV_CAPS_FLR_CAPABILITY (1 << 28) 579 #endif 580 581 #define PCIE_DEV_CTRL 0x08 582 #define PCIE_DEV_CTRL_FLR 0x8000 583 584 #define PCIE_DEV_STATUS 0x0A 585 #ifndef PCIE_DEV_STATUS_PENDING_TRANSACTION 586 #define PCIE_DEV_STATUS_PENDING_TRANSACTION (1 << 5) 587 #endif 588 589 #ifndef PCI_CAPABILITY_LIST 590 /* Ofset of first capability list entry */ 591 #define PCI_CAPABILITY_LIST 0x34 592 #endif 593 594 #define PCI_CAPABILITY_LIST_MASK 0xff 595 596 #ifndef PCI_CB_CAPABILITY_LIST 597 #define PCI_CB_CAPABILITY_LIST 0x14 598 #endif 599 600 #if (defined(__LINUX)) || (defined(PCI_CAP_LIST_ID)) 601 #define PCI_CAP_LIST_ID_DEF 602 #endif 603 #if (defined(__LINUX)) || (defined(PCI_CAP_LIST_NEXT)) 604 #define PCI_CAP_LIST_NEXT_DEF 605 #endif 606 #if (defined(__LINUX)) || (defined(PCI_STATUS)) 607 #define PCI_STATUS_DEF 608 #endif 609 #if (defined(__LINUX)) || (defined(PCI_STATUS_CAP_LIST)) 610 #define PCI_STATUS_CAP_LIST_DEF 611 #endif 612 613 #ifndef PCI_CAP_LIST_ID_DEF 614 #define PCI_CAP_LIST_ID 0x0 /* Capability ID */ 615 #endif 616 617 #define PCI_CAP_LIST_ID_MASK 0xff 618 619 #ifndef PCI_CAP_LIST_NEXT_DEF 620 /* Next capability in the list */ 621 #define PCI_CAP_LIST_NEXT 0x1 622 #endif 623 624 #define PCI_CAP_LIST_NEXT_MASK 0xff 625 626 #ifndef PCI_STATUS_DEF 627 #define PCI_STATUS 0x6 /* 16 bits */ 628 #endif 629 #ifndef PCI_STATUS_CAP_LIST_DEF 630 /* Support Capability List */ 631 #define PCI_STATUS_CAP_LIST 0x10 632 #endif 633 634 #ifndef PCI_SRIOV_CAP 635 636 /* Some PCI Config defines... need to put this in a better location... */ 637 #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ 638 #define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */ 639 #define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */ 640 #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ 641 #define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ 642 #define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */ 643 #define PCI_SRIOV_CTRL_VFM 0x02 /* VF Migration Enable */ 644 #define PCI_SRIOV_CTRL_INTR 0x04 /* VF Migration Interrupt Enable */ 645 #define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */ 646 #define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */ 647 #define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */ 648 #define PCI_SRIOV_STATUS_VFM 0x01 /* VF Migration Status */ 649 #define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */ 650 #define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */ 651 #define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */ 652 #define PCI_SRIOV_FUNC_LINK 0x12 /* Function Dependency Link */ 653 #define PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */ 654 #define PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */ 655 #define PCI_SRIOV_VF_DID 0x1a /* VF Device ID */ 656 #define PCI_SRIOV_SUP_PGSIZE 0x1c /* Supported Page Sizes */ 657 #define PCI_SRIOV_SYS_PGSIZE 0x20 /* System Page Size */ 658 659 #endif 660 661 #ifndef PCI_CAP_ID_EXP 662 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 663 #endif 664 #ifndef PCI_EXP_DEVCTL 665 #define PCI_EXP_DEVCTL 8 /* Device Control */ 666 #endif 667 #ifndef PCI_EXP_DEVCTL_RELAX_EN 668 #define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */ 669 #endif 670 671 #endif 672