1 /*- 2 * Copyright (c) 2018 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by BAE Systems, the University of Cambridge 6 * Computer Laboratory, and Memorial University under DARPA/AFRL contract 7 * FA8650-15-C-7558 ("CADETS"), as part of the DARPA Transparent Computing 8 * (TC) research program. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/kthread.h> 36 #include <sys/rman.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <machine/bus.h> 40 41 #include <dev/ofw/ofw_bus.h> 42 #include <dev/ofw/ofw_bus_subr.h> 43 44 #include "qcom_gcc_var.h" 45 #include "qcom_gcc_msm8916.h" 46 47 #define GCC_QDSS_BCR 0x29000 48 #define GCC_QDSS_BCR_BLK_ARES (1 << 0) /* Async software reset. */ 49 #define GCC_QDSS_CFG_AHB_CBCR 0x29008 50 #define AHB_CBCR_CLK_ENABLE (1 << 0) /* AHB clk branch ctrl */ 51 #define GCC_QDSS_ETR_USB_CBCR 0x29028 52 #define ETR_USB_CBCR_CLK_ENABLE (1 << 0) /* ETR USB clk branch ctrl */ 53 #define GCC_QDSS_DAP_CBCR 0x29084 54 #define DAP_CBCR_CLK_ENABLE (1 << 0) /* DAP clk branch ctrl */ 55 56 /* 57 * Qualcomm Debug Subsystem (QDSS) 58 * block enabling routine. 59 */ 60 static void 61 qcom_msm8916_qdss_enable(struct qcom_gcc_softc *sc) 62 { 63 64 /* Put QDSS block to reset */ 65 bus_write_4(sc->reg, GCC_QDSS_BCR, GCC_QDSS_BCR_BLK_ARES); 66 67 /* Enable AHB clock branch */ 68 bus_write_4(sc->reg, GCC_QDSS_CFG_AHB_CBCR, AHB_CBCR_CLK_ENABLE); 69 70 /* Enable DAP clock branch */ 71 bus_write_4(sc->reg, GCC_QDSS_DAP_CBCR, DAP_CBCR_CLK_ENABLE); 72 73 /* Enable ETR USB clock branch */ 74 bus_write_4(sc->reg, GCC_QDSS_ETR_USB_CBCR, ETR_USB_CBCR_CLK_ENABLE); 75 76 /* Out of reset */ 77 bus_write_4(sc->reg, GCC_QDSS_BCR, 0); 78 } 79 80 void 81 qcom_gcc_msm8916_clock_setup(struct qcom_gcc_softc *sc) 82 { 83 qcom_msm8916_qdss_enable(sc); 84 } 85