1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2026 Adrian Chadd <adrian@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* Driver for Qualcomm clock/reset trees */ 29 30 #include <sys/param.h> 31 #include <sys/kernel.h> 32 #include <sys/malloc.h> 33 #include <sys/module.h> 34 #include <sys/sglist.h> 35 #include <sys/random.h> 36 #include <sys/stdatomic.h> 37 #include <sys/mutex.h> 38 39 #include <machine/bus.h> 40 #include <machine/resource.h> 41 #include <sys/bus.h> 42 #include <sys/rman.h> 43 44 #include <dev/fdt/fdt_common.h> 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 48 #include <dev/hwreset/hwreset.h> 49 50 #include "clkdev_if.h" 51 #include "hwreset_if.h" 52 53 #include "qcom_gcc_var.h" 54 #include "qcom_gcc_ipq4018.h" 55 #include "qcom_gcc_msm8916.h" 56 57 static int qcom_gcc_modevent(module_t, int, void *); 58 59 static int qcom_gcc_probe(device_t); 60 static int qcom_gcc_attach(device_t); 61 static int qcom_gcc_detach(device_t); 62 63 struct qcom_gcc_chipset_list_entry { 64 const char *ofw; 65 const char *desc; 66 qcom_gcc_chipset_t chipset; 67 }; 68 69 static struct qcom_gcc_chipset_list_entry qcom_gcc_chipset_list[] = { 70 { "qcom,gcc-ipq4019", "Qualcomm IPQ4018 Clock/Reset Controller", 71 QCOM_GCC_CHIPSET_IPQ4018 }, 72 { "qcom,gcc-msm8916", "Qualcomm MSM8916 Clock/Reset Controller", 73 QCOM_GCC_CHIPSET_MSM8916 }, 74 { NULL, NULL, 0 }, 75 }; 76 77 static int 78 qcom_gcc_modevent(module_t mod, int type, void *unused) 79 { 80 int error; 81 82 switch (type) { 83 case MOD_LOAD: 84 case MOD_QUIESCE: 85 case MOD_UNLOAD: 86 case MOD_SHUTDOWN: 87 error = 0; 88 break; 89 default: 90 error = EOPNOTSUPP; 91 break; 92 } 93 94 return (error); 95 } 96 97 static int 98 qcom_gcc_probe(device_t dev) 99 { 100 struct qcom_gcc_softc *sc; 101 int i; 102 103 sc = device_get_softc(dev); 104 105 if (! ofw_bus_status_okay(dev)) 106 return (ENXIO); 107 108 for (i = 0; qcom_gcc_chipset_list[i].ofw != NULL; i++) { 109 const struct qcom_gcc_chipset_list_entry *ce; 110 111 ce = &qcom_gcc_chipset_list[i]; 112 if (ofw_bus_is_compatible(dev, ce->ofw) == 0) 113 continue; 114 device_set_desc(dev, ce->desc); 115 sc->sc_chipset = ce->chipset; 116 return (0); 117 } 118 119 return (ENXIO); 120 } 121 122 static int 123 qcom_gcc_attach(device_t dev) 124 { 125 struct qcom_gcc_softc *sc; 126 size_t mem_sz; 127 128 sc = device_get_softc(dev); 129 130 /* Found a compatible device! */ 131 sc->dev = dev; 132 133 /* 134 * Setup the hardware callbacks, before any further initialisation 135 * is performed. 136 */ 137 switch (sc->sc_chipset) { 138 case QCOM_GCC_CHIPSET_IPQ4018: 139 qcom_gcc_ipq4018_hwreset_init(sc); 140 mem_sz = 0x60000; 141 break; 142 case QCOM_GCC_CHIPSET_MSM8916: 143 qcom_gcc_msm8916_hwreset_init(sc); 144 mem_sz = 0x0; 145 break; 146 case QCOM_GCC_CHIPSET_NONE: 147 device_printf(dev, "Invalid chipset (%d)\n", sc->sc_chipset); 148 return (ENXIO); 149 } 150 151 sc->reg_rid = 0; 152 153 if (mem_sz != 0) 154 sc->reg = bus_alloc_resource_anywhere(dev, SYS_RES_MEMORY, 155 &sc->reg_rid, mem_sz, RF_ACTIVE); 156 else 157 sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 158 &sc->reg_rid, RF_ACTIVE); 159 160 if (sc->reg == NULL) { 161 device_printf(dev, "Couldn't allocate memory resource!\n"); 162 return (ENXIO); 163 } 164 165 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); 166 167 /* 168 * Register as a reset provider. 169 */ 170 hwreset_register_ofw_provider(dev); 171 172 /* 173 * Setup and register as a clock provider. 174 */ 175 switch (sc->sc_chipset) { 176 case QCOM_GCC_CHIPSET_IPQ4018: 177 qcom_gcc_ipq4018_clock_setup(sc); 178 break; 179 case QCOM_GCC_CHIPSET_MSM8916: 180 qcom_gcc_msm8916_clock_setup(sc); 181 break; 182 case QCOM_GCC_CHIPSET_NONE: 183 device_printf(dev, "Invalid chipset (%d)\n", sc->sc_chipset); 184 return (ENXIO); 185 } 186 187 return (0); 188 } 189 190 static int 191 qcom_gcc_detach(device_t dev) 192 { 193 struct qcom_gcc_softc *sc; 194 195 sc = device_get_softc(dev); 196 197 /* 198 * TBD - deregistering reset/clock resources. 199 */ 200 201 if (sc->reg != NULL) { 202 bus_release_resource(sc->dev, SYS_RES_MEMORY, 203 sc->reg_rid, sc->reg); 204 } 205 return (0); 206 } 207 208 static device_method_t qcom_gcc_methods[] = { 209 /* Device methods. */ 210 DEVMETHOD(device_probe, qcom_gcc_probe), 211 DEVMETHOD(device_attach, qcom_gcc_attach), 212 DEVMETHOD(device_detach, qcom_gcc_detach), 213 214 /* Reset interface */ 215 DEVMETHOD(hwreset_assert, qcom_gcc_hwreset_assert), 216 DEVMETHOD(hwreset_is_asserted, qcom_gcc_hwreset_is_asserted), 217 218 /* Clock interface */ 219 DEVMETHOD(clkdev_read_4, qcom_gcc_clock_read), 220 DEVMETHOD(clkdev_write_4, qcom_gcc_clock_write), 221 DEVMETHOD(clkdev_modify_4, qcom_gcc_clock_modify), 222 DEVMETHOD(clkdev_device_lock, qcom_gcc_clock_lock), 223 DEVMETHOD(clkdev_device_unlock, qcom_gcc_clock_unlock), 224 225 DEVMETHOD_END 226 }; 227 228 static driver_t qcom_gcc_driver = { 229 "qcom_gcc", 230 qcom_gcc_methods, 231 sizeof(struct qcom_gcc_softc) 232 }; 233 234 EARLY_DRIVER_MODULE(qcom_gcc, simplebus, qcom_gcc_driver, 235 qcom_gcc_modevent, NULL, BUS_PASS_CPU + BUS_PASS_ORDER_EARLY); 236 EARLY_DRIVER_MODULE(qcom_gcc, ofwbus, qcom_gcc_driver, 237 qcom_gcc_modevent, NULL, BUS_PASS_CPU + BUS_PASS_ORDER_EARLY); 238 MODULE_VERSION(qcom_gcc, 1); 239