1 /*- 2 * Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 #include <sys/param.h> 27 #include <sys/systm.h> 28 #include <sys/bus.h> 29 #include <sys/lock.h> 30 #include <sys/mutex.h> 31 #include <sys/rman.h> 32 #include <machine/bus.h> 33 34 #include <dev/clk/clk.h> 35 #include <dev/clk/clk_div.h> 36 #include <dev/clk/clk_fixed.h> 37 #include <dev/clk/clk_mux.h> 38 39 #include "qcom_clk_fepll.h" 40 41 #include "clkdev_if.h" 42 43 #if 0 44 #define DPRINTF(dev, msg...) device_printf(dev, "cpufreq_dt: " msg); 45 #else 46 #define DPRINTF(dev, msg...) 47 #endif 48 49 /* 50 * This is the top-level PLL clock on the IPQ4018/IPQ4019. 51 * It's a fixed PLL clock that feeds a bunch of divisors into 52 * downstrem FEPLL* and DDR clocks. 53 * 54 * Now, on Linux the clock code creates multiple instances of this 55 * with an inbuilt divisor. Here instead there'll be a single 56 * instance of the FEPLL, and then normal divisors will feed into 57 * the multiple PLL nodes. 58 */ 59 60 struct qcom_clk_fepll_sc { 61 struct clknode *clknode; 62 uint32_t offset; 63 uint32_t fdbkdiv_shift; /* FDBKDIV base */ 64 uint32_t fdbkdiv_width; /* FDBKDIV width */ 65 uint32_t refclkdiv_shift; /* REFCLKDIV base */ 66 uint32_t refclkdiv_width; /* REFCLKDIV width */ 67 }; 68 69 static int 70 qcom_clk_fepll_recalc(struct clknode *clk, uint64_t *freq) 71 { 72 struct qcom_clk_fepll_sc *sc; 73 uint64_t vco, parent_rate; 74 uint32_t reg, fdbkdiv, refclkdiv; 75 76 sc = clknode_get_softc(clk); 77 78 if (freq == NULL || *freq == 0) { 79 device_printf(clknode_get_device(sc->clknode), 80 "%s: called; NULL or 0 frequency\n", 81 __func__); 82 return (ENXIO); 83 } 84 85 parent_rate = *freq; 86 87 CLKDEV_DEVICE_LOCK(clknode_get_device(sc->clknode)); 88 CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->offset, ®); 89 CLKDEV_DEVICE_UNLOCK(clknode_get_device(sc->clknode)); 90 91 fdbkdiv = (reg >> sc->fdbkdiv_shift) & 92 ((1U << sc->fdbkdiv_width) - 1); 93 refclkdiv = (reg >> sc->refclkdiv_shift) & 94 ((1U << sc->refclkdiv_width) - 1); 95 96 vco = parent_rate / refclkdiv; 97 vco = vco * 2; 98 vco = vco * fdbkdiv; 99 100 *freq = vco; 101 return (0); 102 } 103 104 static int 105 qcom_clk_fepll_init(struct clknode *clk, device_t dev) 106 { 107 108 /* 109 * There's only a single parent here for an FEPLL, so just set it 110 * to 0; the caller doesn't need to supply it. 111 */ 112 clknode_init_parent_idx(clk, 0); 113 114 return (0); 115 } 116 117 static clknode_method_t qcom_clk_fepll_methods[] = { 118 /* Device interface */ 119 CLKNODEMETHOD(clknode_init, qcom_clk_fepll_init), 120 CLKNODEMETHOD(clknode_recalc_freq, qcom_clk_fepll_recalc), 121 CLKNODEMETHOD_END 122 }; 123 124 DEFINE_CLASS_1(qcom_clk_fepll, qcom_clk_fepll_class, qcom_clk_fepll_methods, 125 sizeof(struct qcom_clk_fepll_sc), clknode_class); 126 127 int 128 qcom_clk_fepll_register(struct clkdom *clkdom, 129 struct qcom_clk_fepll_def *clkdef) 130 { 131 struct clknode *clk; 132 struct qcom_clk_fepll_sc *sc; 133 134 clk = clknode_create(clkdom, &qcom_clk_fepll_class, &clkdef->clkdef); 135 if (clk == NULL) 136 return (1); 137 138 sc = clknode_get_softc(clk); 139 sc->clknode = clk; 140 141 sc->offset = clkdef->offset; 142 sc->fdbkdiv_shift = clkdef->fdbkdiv_shift; 143 sc->fdbkdiv_width = clkdef->fdbkdiv_width; 144 sc->refclkdiv_shift = clkdef->refclkdiv_shift; 145 sc->refclkdiv_width = clkdef->refclkdiv_width; 146 147 clknode_register(clkdom, clk); 148 149 return (0); 150 } 151