1 /*-
2 * Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 #include <sys/param.h>
27 #include <sys/systm.h>
28 #include <sys/bus.h>
29 #include <sys/lock.h>
30 #include <sys/mutex.h>
31 #include <sys/rman.h>
32 #include <machine/bus.h>
33
34 #include <dev/clk/clk.h>
35 #include <dev/clk/clk_div.h>
36 #include <dev/clk/clk_fixed.h>
37 #include <dev/clk/clk_mux.h>
38
39 #include "qcom_clk_branch2.h"
40 #include "qcom_clk_branch2_reg.h"
41
42 #include "clkdev_if.h"
43
44 /*
45 * This is a combination gate/status and dynamic hardware clock gating with
46 * voting.
47 */
48
49 #if 0
50 #define DPRINTF(dev, msg...) device_printf(dev, msg);
51 #else
52 #define DPRINTF(dev, msg...)
53 #endif
54
55 struct qcom_clk_branch2_sc {
56 struct clknode *clknode;
57 uint32_t flags;
58 uint32_t enable_offset;
59 uint32_t enable_shift;
60 uint32_t hwcg_reg;
61 uint32_t hwcg_bit;
62 uint32_t halt_reg;
63 uint32_t halt_check_type;
64 bool halt_check_voted;
65 };
66 #if 0
67 static bool
68 qcom_clk_branch2_get_gate_locked(struct qcom_clk_branch2_sc *sc)
69 {
70 uint32_t reg;
71
72 CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->enable_offset,
73 ®);
74
75 DPRINTF(clknode_get_device(sc->clknode),
76 "%s: offset=0x%x, reg=0x%x\n", __func__,
77 sc->enable_offset, reg);
78
79 return (!! (reg & (1U << sc->enable_shift)));
80 }
81 #endif
82
83 static int
qcom_clk_branch2_init(struct clknode * clk,device_t dev)84 qcom_clk_branch2_init(struct clknode *clk, device_t dev)
85 {
86
87 clknode_init_parent_idx(clk, 0);
88
89 return (0);
90 }
91
92 static bool
qcom_clk_branch2_in_hwcg_mode_locked(struct qcom_clk_branch2_sc * sc)93 qcom_clk_branch2_in_hwcg_mode_locked(struct qcom_clk_branch2_sc *sc)
94 {
95 uint32_t reg;
96
97 if (sc->hwcg_reg == 0)
98 return (false);
99
100 CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->hwcg_reg,
101 ®);
102
103 return (!! (reg & (1U << sc->hwcg_bit)));
104 }
105
106 static bool
qcom_clk_branch2_check_halt_locked(struct qcom_clk_branch2_sc * sc,bool enable)107 qcom_clk_branch2_check_halt_locked(struct qcom_clk_branch2_sc *sc, bool enable)
108 {
109 uint32_t reg;
110
111 CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->halt_reg, ®);
112
113 if (enable) {
114 /*
115 * The upstream Linux code is .. unfortunate.
116 *
117 * Here it says "return true if BRANCH_CLK_OFF is not set,
118 * or if the status field = FSM_STATUS_ON AND
119 * the clk_off field is 0.
120 *
121 * Which .. is weird, because I can't currently see
122 * how we'd ever need to check FSM_STATUS_ON - the only
123 * valid check for the FSM status also requires clk_off=0.
124 */
125 return !! ((reg & QCOM_CLK_BRANCH2_CLK_OFF) == 0);
126 } else {
127 return !! (reg & QCOM_CLK_BRANCH2_CLK_OFF);
128 }
129 }
130
131 /*
132 * Check if the given type/voted flag match what is configured.
133 */
134 static bool
qcom_clk_branch2_halt_check_type(struct qcom_clk_branch2_sc * sc,uint32_t type,bool voted)135 qcom_clk_branch2_halt_check_type(struct qcom_clk_branch2_sc *sc,
136 uint32_t type, bool voted)
137 {
138 return ((sc->halt_check_type == type) &&
139 (sc->halt_check_voted == voted));
140 }
141
142 static bool
qcom_clk_branch2_wait_locked(struct qcom_clk_branch2_sc * sc,bool enable)143 qcom_clk_branch2_wait_locked(struct qcom_clk_branch2_sc *sc, bool enable)
144 {
145
146 if (qcom_clk_branch2_halt_check_type(sc,
147 QCOM_CLK_BRANCH2_BRANCH_HALT_SKIP, false))
148 return (true);
149 if (qcom_clk_branch2_in_hwcg_mode_locked(sc))
150 return (true);
151
152 if ((qcom_clk_branch2_halt_check_type(sc,
153 QCOM_CLK_BRANCH2_BRANCH_HALT_DELAY, false)) ||
154 (enable == false && sc->halt_check_voted)) {
155 DELAY(10);
156 return (true);
157 }
158
159 if ((qcom_clk_branch2_halt_check_type(sc,
160 QCOM_CLK_BRANCH2_BRANCH_HALT_INVERTED, false)) ||
161 (qcom_clk_branch2_halt_check_type(sc,
162 QCOM_CLK_BRANCH2_BRANCH_HALT, false)) ||
163 (enable && sc->halt_check_voted)) {
164 int count;
165
166 for (count = 0; count < 200; count++) {
167 if (qcom_clk_branch2_check_halt_locked(sc, enable))
168 return (true);
169 DELAY(1);
170 }
171 DPRINTF(clknode_get_device(sc->clknode),
172 "%s: enable stuck (%d)!\n", __func__, enable);
173 return (false);
174 }
175
176 /* Default */
177 return (true);
178 }
179
180 static int
qcom_clk_branch2_set_gate(struct clknode * clk,bool enable)181 qcom_clk_branch2_set_gate(struct clknode *clk, bool enable)
182 {
183 struct qcom_clk_branch2_sc *sc;
184 uint32_t reg;
185
186 sc = clknode_get_softc(clk);
187
188 DPRINTF(clknode_get_device(sc->clknode), "%s: called\n", __func__);
189
190 if (sc->enable_offset == 0) {
191 DPRINTF(clknode_get_device(sc->clknode),
192 "%s: no enable_offset", __func__);
193 return (ENXIO);
194 }
195
196 DPRINTF(clknode_get_device(sc->clknode),
197 "%s: called; enable=%d\n", __func__, enable);
198
199 CLKDEV_DEVICE_LOCK(clknode_get_device(sc->clknode));
200 CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->enable_offset,
201 ®);
202 if (enable) {
203 reg |= (1U << sc->enable_shift);
204 } else {
205 reg &= ~(1U << sc->enable_shift);
206 }
207 CLKDEV_WRITE_4(clknode_get_device(sc->clknode), sc->enable_offset,
208 reg);
209
210 /*
211 * Now wait for the clock branch to update!
212 */
213 if (! qcom_clk_branch2_wait_locked(sc, enable)) {
214 CLKDEV_DEVICE_UNLOCK(clknode_get_device(sc->clknode));
215 DPRINTF(clknode_get_device(sc->clknode),
216 "%s: failed to wait!\n", __func__);
217 return (ENXIO);
218 }
219
220 CLKDEV_DEVICE_UNLOCK(clknode_get_device(sc->clknode));
221
222 return (0);
223 }
224
225 static int
qcom_clk_branch2_set_freq(struct clknode * clk,uint64_t fin,uint64_t * fout,int flags,int * stop)226 qcom_clk_branch2_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout,
227 int flags, int *stop)
228 {
229 struct qcom_clk_branch2_sc *sc;
230
231 sc = clknode_get_softc(clk);
232
233 /* We only support what our parent clock is currently set as */
234 *fout = fin;
235
236 /* .. and stop here if we don't have SET_RATE_PARENT */
237 if (sc->flags & QCOM_CLK_BRANCH2_FLAGS_SET_RATE_PARENT)
238 *stop = 0;
239 else
240 *stop = 1;
241 return (0);
242 }
243
244
245 static clknode_method_t qcom_clk_branch2_methods[] = {
246 /* Device interface */
247 CLKNODEMETHOD(clknode_init, qcom_clk_branch2_init),
248 CLKNODEMETHOD(clknode_set_gate, qcom_clk_branch2_set_gate),
249 CLKNODEMETHOD(clknode_set_freq, qcom_clk_branch2_set_freq),
250 CLKNODEMETHOD_END
251 };
252
253 DEFINE_CLASS_1(qcom_clk_branch2, qcom_clk_branch2_class,
254 qcom_clk_branch2_methods, sizeof(struct qcom_clk_branch2_sc),
255 clknode_class);
256
257 int
qcom_clk_branch2_register(struct clkdom * clkdom,struct qcom_clk_branch2_def * clkdef)258 qcom_clk_branch2_register(struct clkdom *clkdom,
259 struct qcom_clk_branch2_def *clkdef)
260 {
261 struct clknode *clk;
262 struct qcom_clk_branch2_sc *sc;
263
264 if (clkdef->flags & QCOM_CLK_BRANCH2_FLAGS_CRITICAL)
265 clkdef->clkdef.flags |= CLK_NODE_CANNOT_STOP;
266
267 clk = clknode_create(clkdom, &qcom_clk_branch2_class,
268 &clkdef->clkdef);
269 if (clk == NULL)
270 return (1);
271
272 sc = clknode_get_softc(clk);
273 sc->clknode = clk;
274
275 sc->enable_offset = clkdef->enable_offset;
276 sc->enable_shift = clkdef->enable_shift;
277 sc->halt_reg = clkdef->halt_reg;
278 sc->hwcg_reg = clkdef->hwcg_reg;
279 sc->hwcg_bit = clkdef->hwcg_bit;
280 sc->halt_check_type = clkdef->halt_check_type;
281 sc->halt_check_voted = clkdef->halt_check_voted;
282 sc->flags = clkdef->flags;
283
284 clknode_register(clkdom, clk);
285
286 return (0);
287 }
288