1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 /* $FreeBSD$ */ 4 #ifndef _ICP_QAT_FW_H_ 5 #define _ICP_QAT_FW_H_ 6 #include <sys/types.h> 7 #include "icp_qat_hw.h" 8 9 #define QAT_FIELD_SET(flags, val, bitpos, mask) \ 10 { \ 11 (flags) = (((flags) & (~((mask) << (bitpos)))) | \ 12 (((val) & (mask)) << (bitpos))); \ 13 } 14 15 #define QAT_FIELD_GET(flags, bitpos, mask) (((flags) >> (bitpos)) & (mask)) 16 17 #define ICP_QAT_FW_REQ_DEFAULT_SZ 128 18 #define ICP_QAT_FW_RESP_DEFAULT_SZ 32 19 #define ICP_QAT_FW_COMN_ONE_BYTE_SHIFT 8 20 #define ICP_QAT_FW_COMN_SINGLE_BYTE_MASK 0xFF 21 #define ICP_QAT_FW_NUM_LONGWORDS_1 1 22 #define ICP_QAT_FW_NUM_LONGWORDS_2 2 23 #define ICP_QAT_FW_NUM_LONGWORDS_3 3 24 #define ICP_QAT_FW_NUM_LONGWORDS_4 4 25 #define ICP_QAT_FW_NUM_LONGWORDS_5 5 26 #define ICP_QAT_FW_NUM_LONGWORDS_6 6 27 #define ICP_QAT_FW_NUM_LONGWORDS_7 7 28 #define ICP_QAT_FW_NUM_LONGWORDS_10 10 29 #define ICP_QAT_FW_NUM_LONGWORDS_13 13 30 #define ICP_QAT_FW_NULL_REQ_SERV_ID 1 31 32 enum icp_qat_fw_comn_resp_serv_id { 33 ICP_QAT_FW_COMN_RESP_SERV_NULL, 34 ICP_QAT_FW_COMN_RESP_SERV_CPM_FW, 35 ICP_QAT_FW_COMN_RESP_SERV_DELIMITER 36 }; 37 38 enum icp_qat_fw_comn_request_id { 39 ICP_QAT_FW_COMN_REQ_NULL = 0, 40 ICP_QAT_FW_COMN_REQ_CPM_FW_PKE = 3, 41 ICP_QAT_FW_COMN_REQ_CPM_FW_LA = 4, 42 ICP_QAT_FW_COMN_REQ_CPM_FW_DMA = 7, 43 ICP_QAT_FW_COMN_REQ_CPM_FW_COMP = 9, 44 ICP_QAT_FW_COMN_REQ_DELIMITER 45 }; 46 47 struct icp_qat_fw_comn_req_hdr_cd_pars { 48 union { 49 struct { 50 uint64_t content_desc_addr; 51 uint16_t content_desc_resrvd1; 52 uint8_t content_desc_params_sz; 53 uint8_t content_desc_hdr_resrvd2; 54 uint32_t content_desc_resrvd3; 55 } s; 56 struct { 57 uint32_t serv_specif_fields[4]; 58 } s1; 59 } u; 60 }; 61 62 struct icp_qat_fw_comn_req_mid { 63 uint64_t opaque_data; 64 uint64_t src_data_addr; 65 uint64_t dest_data_addr; 66 uint32_t src_length; 67 uint32_t dst_length; 68 }; 69 70 struct icp_qat_fw_comn_req_cd_ctrl { 71 uint32_t content_desc_ctrl_lw[ICP_QAT_FW_NUM_LONGWORDS_5]; 72 }; 73 74 struct icp_qat_fw_comn_req_hdr { 75 uint8_t resrvd1; 76 uint8_t service_cmd_id; 77 uint8_t service_type; 78 uint8_t hdr_flags; 79 uint16_t serv_specif_flags; 80 uint16_t comn_req_flags; 81 }; 82 83 struct icp_qat_fw_comn_req_rqpars { 84 uint32_t serv_specif_rqpars_lw[ICP_QAT_FW_NUM_LONGWORDS_13]; 85 }; 86 87 struct icp_qat_fw_comn_req { 88 struct icp_qat_fw_comn_req_hdr comn_hdr; 89 struct icp_qat_fw_comn_req_hdr_cd_pars cd_pars; 90 struct icp_qat_fw_comn_req_mid comn_mid; 91 struct icp_qat_fw_comn_req_rqpars serv_specif_rqpars; 92 struct icp_qat_fw_comn_req_cd_ctrl cd_ctrl; 93 }; 94 95 struct icp_qat_fw_comn_error { 96 uint8_t xlat_err_code; 97 uint8_t cmp_err_code; 98 }; 99 100 struct icp_qat_fw_comn_resp_hdr { 101 uint8_t resrvd1; 102 uint8_t service_id; 103 uint8_t response_type; 104 uint8_t hdr_flags; 105 struct icp_qat_fw_comn_error comn_error; 106 uint8_t comn_status; 107 uint8_t cmd_id; 108 }; 109 110 struct icp_qat_fw_comn_resp { 111 struct icp_qat_fw_comn_resp_hdr comn_hdr; 112 uint64_t opaque_data; 113 uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_4]; 114 }; 115 116 #define ICP_QAT_FW_COMN_REQ_FLAG_SET 1 117 #define ICP_QAT_FW_COMN_REQ_FLAG_CLR 0 118 #define ICP_QAT_FW_COMN_VALID_FLAG_BITPOS 7 119 #define ICP_QAT_FW_COMN_VALID_FLAG_MASK 0x1 120 #define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK 0x7F 121 122 #define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \ 123 icp_qat_fw_comn_req_hdr_t.service_type 124 125 #define ICP_QAT_FW_COMN_OV_SRV_TYPE_SET(icp_qat_fw_comn_req_hdr_t, val) \ 126 icp_qat_fw_comn_req_hdr_t.service_type = val 127 128 #define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_GET(icp_qat_fw_comn_req_hdr_t) \ 129 icp_qat_fw_comn_req_hdr_t.service_cmd_id 130 131 #define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_SET(icp_qat_fw_comn_req_hdr_t, val) \ 132 icp_qat_fw_comn_req_hdr_t.service_cmd_id = val 133 134 #define ICP_QAT_FW_COMN_HDR_VALID_FLAG_GET(hdr_t) \ 135 ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_t.hdr_flags) 136 137 #define ICP_QAT_FW_COMN_HDR_VALID_FLAG_SET(hdr_t, val) \ 138 ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val) 139 140 #define ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_flags) \ 141 QAT_FIELD_GET(hdr_flags, \ 142 ICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \ 143 ICP_QAT_FW_COMN_VALID_FLAG_MASK) 144 145 #define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_GET(hdr_flags) \ 146 (hdr_flags & ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK) 147 148 #define ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val) \ 149 QAT_FIELD_SET((hdr_t.hdr_flags), \ 150 (val), \ 151 ICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \ 152 ICP_QAT_FW_COMN_VALID_FLAG_MASK) 153 154 #define ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(valid) \ 155 (((valid)&ICP_QAT_FW_COMN_VALID_FLAG_MASK) \ 156 << ICP_QAT_FW_COMN_VALID_FLAG_BITPOS) 157 158 #define QAT_COMN_PTR_TYPE_BITPOS 0 159 #define QAT_COMN_PTR_TYPE_MASK 0x1 160 #define QAT_COMN_CD_FLD_TYPE_BITPOS 1 161 #define QAT_COMN_CD_FLD_TYPE_MASK 0x1 162 #define QAT_COMN_PTR_TYPE_FLAT 0x0 163 #define QAT_COMN_PTR_TYPE_SGL 0x1 164 #define QAT_COMN_CD_FLD_TYPE_64BIT_ADR 0x0 165 #define QAT_COMN_CD_FLD_TYPE_16BYTE_DATA 0x1 166 167 #define ICP_QAT_FW_COMN_FLAGS_BUILD(cdt, ptr) \ 168 ((((cdt)&QAT_COMN_CD_FLD_TYPE_MASK) << QAT_COMN_CD_FLD_TYPE_BITPOS) | \ 169 (((ptr)&QAT_COMN_PTR_TYPE_MASK) << QAT_COMN_PTR_TYPE_BITPOS)) 170 171 #define ICP_QAT_FW_COMN_PTR_TYPE_GET(flags) \ 172 QAT_FIELD_GET(flags, QAT_COMN_PTR_TYPE_BITPOS, QAT_COMN_PTR_TYPE_MASK) 173 174 #define ICP_QAT_FW_COMN_CD_FLD_TYPE_GET(flags) \ 175 QAT_FIELD_GET(flags, \ 176 QAT_COMN_CD_FLD_TYPE_BITPOS, \ 177 QAT_COMN_CD_FLD_TYPE_MASK) 178 179 #define ICP_QAT_FW_COMN_PTR_TYPE_SET(flags, val) \ 180 QAT_FIELD_SET(flags, \ 181 val, \ 182 QAT_COMN_PTR_TYPE_BITPOS, \ 183 QAT_COMN_PTR_TYPE_MASK) 184 185 #define ICP_QAT_FW_COMN_CD_FLD_TYPE_SET(flags, val) \ 186 QAT_FIELD_SET(flags, \ 187 val, \ 188 QAT_COMN_CD_FLD_TYPE_BITPOS, \ 189 QAT_COMN_CD_FLD_TYPE_MASK) 190 191 #define ICP_QAT_FW_COMN_NEXT_ID_BITPOS 4 192 #define ICP_QAT_FW_COMN_NEXT_ID_MASK 0xF0 193 #define ICP_QAT_FW_COMN_CURR_ID_BITPOS 0 194 #define ICP_QAT_FW_COMN_CURR_ID_MASK 0x0F 195 196 #define ICP_QAT_FW_COMN_NEXT_ID_GET(cd_ctrl_hdr_t) \ 197 ((((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_NEXT_ID_MASK) >> \ 198 (ICP_QAT_FW_COMN_NEXT_ID_BITPOS)) 199 200 #define ICP_QAT_FW_COMN_NEXT_ID_SET(cd_ctrl_hdr_t, val) \ 201 { \ 202 ((cd_ctrl_hdr_t)->next_curr_id) = \ 203 ((((cd_ctrl_hdr_t)->next_curr_id) & \ 204 ICP_QAT_FW_COMN_CURR_ID_MASK) | \ 205 ((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) & \ 206 ICP_QAT_FW_COMN_NEXT_ID_MASK)); \ 207 } 208 209 #define ICP_QAT_FW_COMN_CURR_ID_GET(cd_ctrl_hdr_t) \ 210 (((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_CURR_ID_MASK) 211 212 #define ICP_QAT_FW_COMN_CURR_ID_SET(cd_ctrl_hdr_t, val) \ 213 { \ 214 ((cd_ctrl_hdr_t)->next_curr_id) = \ 215 ((((cd_ctrl_hdr_t)->next_curr_id) & \ 216 ICP_QAT_FW_COMN_NEXT_ID_MASK) | \ 217 ((val)&ICP_QAT_FW_COMN_CURR_ID_MASK)); \ 218 } 219 220 #define QAT_COMN_RESP_CRYPTO_STATUS_BITPOS 7 221 #define QAT_COMN_RESP_CRYPTO_STATUS_MASK 0x1 222 #define QAT_COMN_RESP_PKE_STATUS_BITPOS 6 223 #define QAT_COMN_RESP_PKE_STATUS_MASK 0x1 224 #define QAT_COMN_RESP_CMP_STATUS_BITPOS 5 225 #define QAT_COMN_RESP_CMP_STATUS_MASK 0x1 226 #define QAT_COMN_RESP_XLAT_STATUS_BITPOS 4 227 #define QAT_COMN_RESP_XLAT_STATUS_MASK 0x1 228 #define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS 3 229 #define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK 0x1 230 231 #define ICP_QAT_FW_COMN_RESP_STATUS_BUILD(crypto, comp, xlat, eolb) \ 232 ((((crypto)&QAT_COMN_RESP_CRYPTO_STATUS_MASK) \ 233 << QAT_COMN_RESP_CRYPTO_STATUS_BITPOS) | \ 234 (((comp)&QAT_COMN_RESP_CMP_STATUS_MASK) \ 235 << QAT_COMN_RESP_CMP_STATUS_BITPOS) | \ 236 (((xlat)&QAT_COMN_RESP_XLAT_STATUS_MASK) \ 237 << QAT_COMN_RESP_XLAT_STATUS_BITPOS) | \ 238 (((eolb)&QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK) \ 239 << QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS)) 240 241 #define ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(status) \ 242 QAT_FIELD_GET(status, \ 243 QAT_COMN_RESP_CRYPTO_STATUS_BITPOS, \ 244 QAT_COMN_RESP_CRYPTO_STATUS_MASK) 245 246 #define ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(status) \ 247 QAT_FIELD_GET(status, \ 248 QAT_COMN_RESP_CMP_STATUS_BITPOS, \ 249 QAT_COMN_RESP_CMP_STATUS_MASK) 250 251 #define ICP_QAT_FW_COMN_RESP_XLAT_STAT_GET(status) \ 252 QAT_FIELD_GET(status, \ 253 QAT_COMN_RESP_XLAT_STATUS_BITPOS, \ 254 QAT_COMN_RESP_XLAT_STATUS_MASK) 255 256 #define ICP_QAT_FW_COMN_RESP_CMP_END_OF_LAST_BLK_FLAG_GET(status) \ 257 QAT_FIELD_GET(status, \ 258 QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS, \ 259 QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK) 260 261 #define ICP_QAT_FW_COMN_STATUS_FLAG_OK 0 262 #define ICP_QAT_FW_COMN_STATUS_FLAG_ERROR 1 263 #define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_CLR 0 264 #define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_SET 1 265 #define ERR_CODE_NO_ERROR 0 266 #define ERR_CODE_INVALID_BLOCK_TYPE -1 267 #define ERR_CODE_NO_MATCH_ONES_COMP -2 268 #define ERR_CODE_TOO_MANY_LEN_OR_DIS -3 269 #define ERR_CODE_INCOMPLETE_LEN -4 270 #define ERR_CODE_RPT_LEN_NO_FIRST_LEN -5 271 #define ERR_CODE_RPT_GT_SPEC_LEN -6 272 #define ERR_CODE_INV_LIT_LEN_CODE_LEN -7 273 #define ERR_CODE_INV_DIS_CODE_LEN -8 274 #define ERR_CODE_INV_LIT_LEN_DIS_IN_BLK -9 275 #define ERR_CODE_DIS_TOO_FAR_BACK -10 276 #define ERR_CODE_OVERFLOW_ERROR -11 277 #define ERR_CODE_SOFT_ERROR -12 278 #define ERR_CODE_FATAL_ERROR -13 279 #define ERR_CODE_SSM_ERROR -14 280 #define ERR_CODE_ENDPOINT_ERROR -15 281 282 enum icp_qat_fw_slice { 283 ICP_QAT_FW_SLICE_NULL = 0, 284 ICP_QAT_FW_SLICE_CIPHER = 1, 285 ICP_QAT_FW_SLICE_AUTH = 2, 286 ICP_QAT_FW_SLICE_DRAM_RD = 3, 287 ICP_QAT_FW_SLICE_DRAM_WR = 4, 288 ICP_QAT_FW_SLICE_COMP = 5, 289 ICP_QAT_FW_SLICE_XLAT = 6, 290 ICP_QAT_FW_SLICE_DELIMITER 291 }; 292 #endif 293