1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 * 30 */ 31 32 #ifndef _PCIVAR_H_ 33 #define _PCIVAR_H_ 34 35 #include <sys/queue.h> 36 #include <sys/eventhandler.h> 37 38 /* some PCI bus constants */ 39 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 40 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 41 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 42 43 typedef uint64_t pci_addr_t; 44 45 /* Config registers for PCI-PCI and PCI-Cardbus bridges. */ 46 struct pcicfg_bridge { 47 uint8_t br_seclat; 48 uint8_t br_subbus; 49 uint8_t br_secbus; 50 uint8_t br_pribus; 51 uint16_t br_control; 52 }; 53 54 /* Interesting values for PCI power management */ 55 struct pcicfg_pp { 56 uint16_t pp_cap; /* PCI power management capabilities */ 57 uint8_t pp_status; /* conf. space addr. of PM control/status reg */ 58 uint8_t pp_bse; /* conf. space addr. of PM BSE reg */ 59 uint8_t pp_data; /* conf. space addr. of PM data reg */ 60 }; 61 62 struct pci_map { 63 pci_addr_t pm_value; /* Raw BAR value */ 64 pci_addr_t pm_size; 65 uint16_t pm_reg; 66 STAILQ_ENTRY(pci_map) pm_link; 67 }; 68 69 struct vpd_readonly { 70 char keyword[2]; 71 char *value; 72 int len; 73 }; 74 75 struct vpd_write { 76 char keyword[2]; 77 char *value; 78 int start; 79 int len; 80 }; 81 82 struct pcicfg_vpd { 83 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */ 84 char vpd_cached; 85 char *vpd_ident; /* string identifier */ 86 int vpd_rocnt; 87 struct vpd_readonly *vpd_ros; 88 int vpd_wcnt; 89 struct vpd_write *vpd_w; 90 }; 91 92 /* Interesting values for PCI MSI */ 93 struct pcicfg_msi { 94 uint16_t msi_ctrl; /* Message Control */ 95 uint8_t msi_location; /* Offset of MSI capability registers. */ 96 uint8_t msi_msgnum; /* Number of messages */ 97 int msi_alloc; /* Number of allocated messages. */ 98 uint64_t msi_addr; /* Contents of address register. */ 99 uint16_t msi_data; /* Contents of data register. */ 100 u_int msi_handlers; 101 }; 102 103 /* Interesting values for PCI MSI-X */ 104 struct msix_vector { 105 uint64_t mv_address; /* Contents of address register. */ 106 uint32_t mv_data; /* Contents of data register. */ 107 int mv_irq; 108 }; 109 110 struct msix_table_entry { 111 u_int mte_vector; /* 1-based index into msix_vectors array. */ 112 u_int mte_handlers; 113 }; 114 115 struct pcicfg_msix { 116 uint16_t msix_ctrl; /* Message Control */ 117 uint16_t msix_msgnum; /* Number of messages */ 118 uint8_t msix_location; /* Offset of MSI-X capability registers. */ 119 uint8_t msix_table_bar; /* BAR containing vector table. */ 120 uint8_t msix_pba_bar; /* BAR containing PBA. */ 121 uint32_t msix_table_offset; 122 uint32_t msix_pba_offset; 123 int msix_alloc; /* Number of allocated vectors. */ 124 int msix_table_len; /* Length of virtual table. */ 125 struct msix_table_entry *msix_table; /* Virtual table. */ 126 struct msix_vector *msix_vectors; /* Array of allocated vectors. */ 127 struct resource *msix_table_res; /* Resource containing vector table. */ 128 struct resource *msix_pba_res; /* Resource containing PBA. */ 129 }; 130 131 /* Interesting values for HyperTransport */ 132 struct pcicfg_ht { 133 uint8_t ht_slave; /* Non-zero if device is an HT slave. */ 134 uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */ 135 uint16_t ht_msictrl; /* MSI mapping control */ 136 uint64_t ht_msiaddr; /* MSI mapping base address */ 137 }; 138 139 /* Interesting values for PCI-express */ 140 struct pcicfg_pcie { 141 uint8_t pcie_location; /* Offset of PCI-e capability registers. */ 142 uint8_t pcie_type; /* Device type. */ 143 uint16_t pcie_flags; /* Device capabilities register. */ 144 uint16_t pcie_device_ctl; /* Device control register. */ 145 uint16_t pcie_link_ctl; /* Link control register. */ 146 uint16_t pcie_slot_ctl; /* Slot control register. */ 147 uint16_t pcie_root_ctl; /* Root control register. */ 148 uint16_t pcie_device_ctl2; /* Second device control register. */ 149 uint16_t pcie_link_ctl2; /* Second link control register. */ 150 uint16_t pcie_slot_ctl2; /* Second slot control register. */ 151 }; 152 153 struct pcicfg_pcix { 154 uint16_t pcix_command; 155 uint8_t pcix_location; /* Offset of PCI-X capability registers. */ 156 }; 157 158 struct pcicfg_vf { 159 int index; 160 }; 161 162 struct pci_ea_entry { 163 int eae_bei; 164 uint32_t eae_flags; 165 uint64_t eae_base; 166 uint64_t eae_max_offset; 167 uint32_t eae_cfg_offset; 168 STAILQ_ENTRY(pci_ea_entry) eae_link; 169 }; 170 171 struct pcicfg_ea { 172 int ea_location; /* Structure offset in Configuration Header */ 173 STAILQ_HEAD(, pci_ea_entry) ea_entries; /* EA entries */ 174 }; 175 176 #define PCICFG_VF 0x0001 /* Device is an SR-IOV Virtual Function */ 177 178 /* config header information common to all header types */ 179 typedef struct pcicfg { 180 device_t dev; /* device which owns this */ 181 182 STAILQ_HEAD(, pci_map) maps; /* BARs */ 183 184 uint16_t subvendor; /* card vendor ID */ 185 uint16_t subdevice; /* card device ID, assigned by card vendor */ 186 uint16_t vendor; /* chip vendor ID */ 187 uint16_t device; /* chip device ID, assigned by chip vendor */ 188 189 uint16_t cmdreg; /* disable/enable chip and PCI options */ 190 uint16_t statreg; /* supported PCI features and error state */ 191 192 uint8_t baseclass; /* chip PCI class */ 193 uint8_t subclass; /* chip PCI subclass */ 194 uint8_t progif; /* chip PCI programming interface */ 195 uint8_t revid; /* chip revision ID */ 196 197 uint8_t hdrtype; /* chip config header type */ 198 uint8_t cachelnsz; /* cache line size in 4byte units */ 199 uint8_t intpin; /* PCI interrupt pin */ 200 uint8_t intline; /* interrupt line (IRQ for PC arch) */ 201 202 uint8_t mingnt; /* min. useful bus grant time in 250ns units */ 203 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 204 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */ 205 206 uint8_t mfdev; /* multi-function device (from hdrtype reg) */ 207 uint8_t nummaps; /* actual number of PCI maps used */ 208 209 uint32_t domain; /* PCI domain */ 210 uint8_t bus; /* config space bus address */ 211 uint8_t slot; /* config space slot address */ 212 uint8_t func; /* config space function number */ 213 214 uint32_t flags; /* flags defined above */ 215 216 struct pcicfg_bridge bridge; /* Bridges */ 217 struct pcicfg_pp pp; /* Power management */ 218 struct pcicfg_vpd vpd; /* Vital product data */ 219 struct pcicfg_msi msi; /* PCI MSI */ 220 struct pcicfg_msix msix; /* PCI MSI-X */ 221 struct pcicfg_ht ht; /* HyperTransport */ 222 struct pcicfg_pcie pcie; /* PCI Express */ 223 struct pcicfg_pcix pcix; /* PCI-X */ 224 struct pcicfg_iov *iov; /* SR-IOV */ 225 struct pcicfg_vf vf; /* SR-IOV Virtual Function */ 226 struct pcicfg_ea ea; /* Enhanced Allocation */ 227 } pcicfgregs; 228 229 /* additional type 1 device config header information (PCI to PCI bridge) */ 230 231 typedef struct { 232 pci_addr_t pmembase; /* base address of prefetchable memory */ 233 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 234 uint32_t membase; /* base address of memory window */ 235 uint32_t memlimit; /* topmost address of memory window */ 236 uint32_t iobase; /* base address of port window */ 237 uint32_t iolimit; /* topmost address of port window */ 238 uint16_t secstat; /* secondary bus status register */ 239 uint16_t bridgectl; /* bridge control register */ 240 uint8_t seclat; /* CardBus latency timer */ 241 } pcih1cfgregs; 242 243 /* additional type 2 device config header information (CardBus bridge) */ 244 245 typedef struct { 246 uint32_t membase0; /* base address of memory window */ 247 uint32_t memlimit0; /* topmost address of memory window */ 248 uint32_t membase1; /* base address of memory window */ 249 uint32_t memlimit1; /* topmost address of memory window */ 250 uint32_t iobase0; /* base address of port window */ 251 uint32_t iolimit0; /* topmost address of port window */ 252 uint32_t iobase1; /* base address of port window */ 253 uint32_t iolimit1; /* topmost address of port window */ 254 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 255 uint16_t secstat; /* secondary bus status register */ 256 uint16_t bridgectl; /* bridge control register */ 257 uint8_t seclat; /* CardBus latency timer */ 258 } pcih2cfgregs; 259 260 extern uint32_t pci_numdevs; 261 262 /* Only if the prerequisites are present */ 263 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 264 struct pci_devinfo { 265 STAILQ_ENTRY(pci_devinfo) pci_links; 266 struct resource_list resources; 267 pcicfgregs cfg; 268 struct pci_conf conf; 269 }; 270 #endif 271 272 #ifdef _SYS_BUS_H_ 273 274 #include "pci_if.h" 275 276 enum pci_device_ivars { 277 PCI_IVAR_SUBVENDOR, 278 PCI_IVAR_SUBDEVICE, 279 PCI_IVAR_VENDOR, 280 PCI_IVAR_DEVICE, 281 PCI_IVAR_DEVID, 282 PCI_IVAR_CLASS, 283 PCI_IVAR_SUBCLASS, 284 PCI_IVAR_PROGIF, 285 PCI_IVAR_REVID, 286 PCI_IVAR_INTPIN, 287 PCI_IVAR_IRQ, 288 PCI_IVAR_DOMAIN, 289 PCI_IVAR_BUS, 290 PCI_IVAR_SLOT, 291 PCI_IVAR_FUNCTION, 292 PCI_IVAR_ETHADDR, 293 PCI_IVAR_CMDREG, 294 PCI_IVAR_CACHELNSZ, 295 PCI_IVAR_MINGNT, 296 PCI_IVAR_MAXLAT, 297 PCI_IVAR_LATTIMER 298 }; 299 300 /* 301 * Simplified accessors for pci devices 302 */ 303 #define PCI_ACCESSOR(var, ivar, type) \ 304 __BUS_ACCESSOR(pci, var, PCI, ivar, type) 305 306 PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t) 307 PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t) 308 PCI_ACCESSOR(vendor, VENDOR, uint16_t) 309 PCI_ACCESSOR(device, DEVICE, uint16_t) 310 PCI_ACCESSOR(devid, DEVID, uint32_t) 311 PCI_ACCESSOR(class, CLASS, uint8_t) 312 PCI_ACCESSOR(subclass, SUBCLASS, uint8_t) 313 PCI_ACCESSOR(progif, PROGIF, uint8_t) 314 PCI_ACCESSOR(revid, REVID, uint8_t) 315 PCI_ACCESSOR(intpin, INTPIN, uint8_t) 316 PCI_ACCESSOR(irq, IRQ, uint8_t) 317 PCI_ACCESSOR(domain, DOMAIN, uint32_t) 318 PCI_ACCESSOR(bus, BUS, uint8_t) 319 PCI_ACCESSOR(slot, SLOT, uint8_t) 320 PCI_ACCESSOR(function, FUNCTION, uint8_t) 321 PCI_ACCESSOR(ether, ETHADDR, uint8_t *) 322 PCI_ACCESSOR(cmdreg, CMDREG, uint8_t) 323 PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t) 324 PCI_ACCESSOR(mingnt, MINGNT, uint8_t) 325 PCI_ACCESSOR(maxlat, MAXLAT, uint8_t) 326 PCI_ACCESSOR(lattimer, LATTIMER, uint8_t) 327 328 #undef PCI_ACCESSOR 329 330 /* 331 * Operations on configuration space. 332 */ 333 static __inline uint32_t 334 pci_read_config(device_t dev, int reg, int width) 335 { 336 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 337 } 338 339 static __inline void 340 pci_write_config(device_t dev, int reg, uint32_t val, int width) 341 { 342 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 343 } 344 345 /* 346 * Ivars for pci bridges. 347 */ 348 349 /*typedef enum pci_device_ivars pcib_device_ivars;*/ 350 enum pcib_device_ivars { 351 PCIB_IVAR_DOMAIN, 352 PCIB_IVAR_BUS 353 }; 354 355 #define PCIB_ACCESSOR(var, ivar, type) \ 356 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type) 357 358 PCIB_ACCESSOR(domain, DOMAIN, uint32_t) 359 PCIB_ACCESSOR(bus, BUS, uint32_t) 360 361 #undef PCIB_ACCESSOR 362 363 /* 364 * PCI interrupt validation. Invalid interrupt values such as 0 or 128 365 * on i386 or other platforms should be mapped out in the MD pcireadconf 366 * code and not here, since the only MI invalid IRQ is 255. 367 */ 368 #define PCI_INVALID_IRQ 255 369 #define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ) 370 371 /* 372 * Convenience functions. 373 * 374 * These should be used in preference to manually manipulating 375 * configuration space. 376 */ 377 static __inline int 378 pci_enable_busmaster(device_t dev) 379 { 380 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev)); 381 } 382 383 static __inline int 384 pci_disable_busmaster(device_t dev) 385 { 386 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev)); 387 } 388 389 static __inline int 390 pci_enable_io(device_t dev, int space) 391 { 392 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space)); 393 } 394 395 static __inline int 396 pci_disable_io(device_t dev, int space) 397 { 398 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space)); 399 } 400 401 static __inline int 402 pci_get_vpd_ident(device_t dev, const char **identptr) 403 { 404 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr)); 405 } 406 407 static __inline int 408 pci_get_vpd_readonly(device_t dev, const char *kw, const char **vptr) 409 { 410 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, vptr)); 411 } 412 413 /* 414 * Check if the address range falls within the VGA defined address range(s) 415 */ 416 static __inline int 417 pci_is_vga_ioport_range(rman_res_t start, rman_res_t end) 418 { 419 420 return (((start >= 0x3b0 && end <= 0x3bb) || 421 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0); 422 } 423 424 static __inline int 425 pci_is_vga_memory_range(rman_res_t start, rman_res_t end) 426 { 427 428 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0); 429 } 430 431 /* 432 * PCI power states are as defined by ACPI: 433 * 434 * D0 State in which device is on and running. It is receiving full 435 * power from the system and delivering full functionality to the user. 436 * D1 Class-specific low-power state in which device context may or may not 437 * be lost. Buses in D1 cannot do anything to the bus that would force 438 * devices on that bus to lose context. 439 * D2 Class-specific low-power state in which device context may or may 440 * not be lost. Attains greater power savings than D1. Buses in D2 441 * can cause devices on that bus to lose some context. Devices in D2 442 * must be prepared for the bus to be in D2 or higher. 443 * D3 State in which the device is off and not running. Device context is 444 * lost. Power can be removed from the device. 445 */ 446 #define PCI_POWERSTATE_D0 0 447 #define PCI_POWERSTATE_D1 1 448 #define PCI_POWERSTATE_D2 2 449 #define PCI_POWERSTATE_D3 3 450 #define PCI_POWERSTATE_UNKNOWN -1 451 452 static __inline int 453 pci_set_powerstate(device_t dev, int state) 454 { 455 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 456 } 457 458 static __inline int 459 pci_get_powerstate(device_t dev) 460 { 461 return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 462 } 463 464 static __inline int 465 pci_find_cap(device_t dev, int capability, int *capreg) 466 { 467 return (PCI_FIND_CAP(device_get_parent(dev), dev, capability, capreg)); 468 } 469 470 static __inline int 471 pci_find_next_cap(device_t dev, int capability, int start, int *capreg) 472 { 473 return (PCI_FIND_NEXT_CAP(device_get_parent(dev), dev, capability, start, 474 capreg)); 475 } 476 477 static __inline int 478 pci_find_extcap(device_t dev, int capability, int *capreg) 479 { 480 return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg)); 481 } 482 483 static __inline int 484 pci_find_next_extcap(device_t dev, int capability, int start, int *capreg) 485 { 486 return (PCI_FIND_NEXT_EXTCAP(device_get_parent(dev), dev, capability, 487 start, capreg)); 488 } 489 490 static __inline int 491 pci_find_htcap(device_t dev, int capability, int *capreg) 492 { 493 return (PCI_FIND_HTCAP(device_get_parent(dev), dev, capability, capreg)); 494 } 495 496 static __inline int 497 pci_find_next_htcap(device_t dev, int capability, int start, int *capreg) 498 { 499 return (PCI_FIND_NEXT_HTCAP(device_get_parent(dev), dev, capability, 500 start, capreg)); 501 } 502 503 static __inline int 504 pci_alloc_msi(device_t dev, int *count) 505 { 506 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count)); 507 } 508 509 static __inline int 510 pci_alloc_msix(device_t dev, int *count) 511 { 512 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count)); 513 } 514 515 static __inline void 516 pci_enable_msi(device_t dev, uint64_t address, uint16_t data) 517 { 518 PCI_ENABLE_MSI(device_get_parent(dev), dev, address, data); 519 } 520 521 static __inline void 522 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data) 523 { 524 PCI_ENABLE_MSIX(device_get_parent(dev), dev, index, address, data); 525 } 526 527 static __inline void 528 pci_disable_msi(device_t dev) 529 { 530 PCI_DISABLE_MSI(device_get_parent(dev), dev); 531 } 532 533 static __inline int 534 pci_remap_msix(device_t dev, int count, const u_int *vectors) 535 { 536 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors)); 537 } 538 539 static __inline int 540 pci_release_msi(device_t dev) 541 { 542 return (PCI_RELEASE_MSI(device_get_parent(dev), dev)); 543 } 544 545 static __inline int 546 pci_msi_count(device_t dev) 547 { 548 return (PCI_MSI_COUNT(device_get_parent(dev), dev)); 549 } 550 551 static __inline int 552 pci_msix_count(device_t dev) 553 { 554 return (PCI_MSIX_COUNT(device_get_parent(dev), dev)); 555 } 556 557 static __inline int 558 pci_msix_pba_bar(device_t dev) 559 { 560 return (PCI_MSIX_PBA_BAR(device_get_parent(dev), dev)); 561 } 562 563 static __inline int 564 pci_msix_table_bar(device_t dev) 565 { 566 return (PCI_MSIX_TABLE_BAR(device_get_parent(dev), dev)); 567 } 568 569 static __inline int 570 pci_get_id(device_t dev, enum pci_id_type type, uintptr_t *id) 571 { 572 return (PCI_GET_ID(device_get_parent(dev), dev, type, id)); 573 } 574 575 /* 576 * This is the deprecated interface, there is no way to tell the difference 577 * between a failure and a valid value that happens to be the same as the 578 * failure value. 579 */ 580 static __inline uint16_t 581 pci_get_rid(device_t dev) 582 { 583 uintptr_t rid; 584 585 if (pci_get_id(dev, PCI_ID_RID, &rid) != 0) 586 return (0); 587 588 return (rid); 589 } 590 591 static __inline void 592 pci_child_added(device_t dev) 593 { 594 595 return (PCI_CHILD_ADDED(device_get_parent(dev), dev)); 596 } 597 598 device_t pci_find_bsf(uint8_t, uint8_t, uint8_t); 599 device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t); 600 device_t pci_find_device(uint16_t, uint16_t); 601 device_t pci_find_class(uint8_t class, uint8_t subclass); 602 603 /* Can be used by drivers to manage the MSI-X table. */ 604 int pci_pending_msix(device_t dev, u_int index); 605 606 int pci_msi_device_blacklisted(device_t dev); 607 int pci_msix_device_blacklisted(device_t dev); 608 609 void pci_ht_map_msi(device_t dev, uint64_t addr); 610 611 device_t pci_find_pcie_root_port(device_t dev); 612 int pci_get_max_payload(device_t dev); 613 int pci_get_max_read_req(device_t dev); 614 void pci_restore_state(device_t dev); 615 void pci_save_state(device_t dev); 616 int pci_set_max_read_req(device_t dev, int size); 617 uint32_t pcie_read_config(device_t dev, int reg, int width); 618 void pcie_write_config(device_t dev, int reg, uint32_t value, int width); 619 uint32_t pcie_adjust_config(device_t dev, int reg, uint32_t mask, 620 uint32_t value, int width); 621 bool pcie_flr(device_t dev, u_int max_delay, bool force); 622 int pcie_get_max_completion_timeout(device_t dev); 623 bool pcie_wait_for_pending_transactions(device_t dev, u_int max_delay); 624 625 #ifdef BUS_SPACE_MAXADDR 626 #if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 627 #define PCI_DMA_BOUNDARY 0x100000000 628 #else 629 #define PCI_DMA_BOUNDARY 0 630 #endif 631 #endif 632 633 #endif /* _SYS_BUS_H_ */ 634 635 /* 636 * cdev switch for control device, initialised in generic PCI code 637 */ 638 extern struct cdevsw pcicdev; 639 640 /* 641 * List of all PCI devices, generation count for the list. 642 */ 643 STAILQ_HEAD(devlist, pci_devinfo); 644 645 extern struct devlist pci_devq; 646 extern uint32_t pci_generation; 647 648 struct pci_map *pci_find_bar(device_t dev, int reg); 649 int pci_bar_enabled(device_t dev, struct pci_map *pm); 650 struct pcicfg_vpd *pci_fetch_vpd_list(device_t dev); 651 652 #define VGA_PCI_BIOS_SHADOW_ADDR 0xC0000 653 #define VGA_PCI_BIOS_SHADOW_SIZE 131072 654 655 int vga_pci_is_boot_display(device_t dev); 656 void * vga_pci_map_bios(device_t dev, size_t *size); 657 void vga_pci_unmap_bios(device_t dev, void *bios); 658 int vga_pci_repost(device_t dev); 659 660 /** 661 * Global eventhandlers invoked when PCI devices are added or removed 662 * from the system. 663 */ 664 typedef void (*pci_event_fn)(void *arg, device_t dev); 665 EVENTHANDLER_DECLARE(pci_add_device, pci_event_fn); 666 EVENTHANDLER_DECLARE(pci_delete_device, pci_event_fn); 667 668 #endif /* _PCIVAR_H_ */ 669