1 /*- 2 * Copyright (c) 2013-2015 Sandvine Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_bus.h" 31 32 #include <sys/param.h> 33 #include <sys/conf.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/fcntl.h> 38 #include <sys/ioccom.h> 39 #include <sys/iov.h> 40 #include <sys/linker.h> 41 #include <sys/lock.h> 42 #include <sys/malloc.h> 43 #include <sys/module.h> 44 #include <sys/mutex.h> 45 #include <sys/pciio.h> 46 #include <sys/queue.h> 47 #include <sys/rman.h> 48 #include <sys/sysctl.h> 49 50 #include <machine/bus.h> 51 #include <machine/stdarg.h> 52 53 #include <sys/nv.h> 54 #include <sys/iov_schema.h> 55 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pci_iov.h> 59 #include <dev/pci/pci_private.h> 60 #include <dev/pci/pci_iov_private.h> 61 #include <dev/pci/schema_private.h> 62 63 #include "pcib_if.h" 64 65 static MALLOC_DEFINE(M_SRIOV, "sr_iov", "PCI SR-IOV allocations"); 66 67 static d_ioctl_t pci_iov_ioctl; 68 69 static struct cdevsw iov_cdevsw = { 70 .d_version = D_VERSION, 71 .d_name = "iov", 72 .d_ioctl = pci_iov_ioctl 73 }; 74 75 SYSCTL_DECL(_hw_pci); 76 77 /* 78 * The maximum amount of memory we will allocate for user configuration of an 79 * SR-IOV device. 1MB ought to be enough for anyone, but leave this 80 * configurable just in case. 81 */ 82 static u_long pci_iov_max_config = 1024 * 1024; 83 SYSCTL_ULONG(_hw_pci, OID_AUTO, iov_max_config, CTLFLAG_RWTUN, 84 &pci_iov_max_config, 0, "Maximum allowed size of SR-IOV configuration."); 85 86 87 #define IOV_READ(d, r, w) \ 88 pci_read_config((d)->cfg.dev, (d)->cfg.iov->iov_pos + r, w) 89 90 #define IOV_WRITE(d, r, v, w) \ 91 pci_write_config((d)->cfg.dev, (d)->cfg.iov->iov_pos + r, v, w) 92 93 static nvlist_t *pci_iov_build_schema(nvlist_t **pf_schema, 94 nvlist_t **vf_schema); 95 static void pci_iov_build_pf_schema(nvlist_t *schema, 96 nvlist_t **driver_schema); 97 static void pci_iov_build_vf_schema(nvlist_t *schema, 98 nvlist_t **driver_schema); 99 static nvlist_t *pci_iov_get_pf_subsystem_schema(void); 100 static nvlist_t *pci_iov_get_vf_subsystem_schema(void); 101 102 int 103 pci_iov_attach_name(device_t dev, struct nvlist *pf_schema, 104 struct nvlist *vf_schema, const char *fmt, ...) 105 { 106 char buf[NAME_MAX + 1]; 107 va_list ap; 108 109 va_start(ap, fmt); 110 vsnprintf(buf, sizeof(buf), fmt, ap); 111 va_end(ap); 112 return (PCI_IOV_ATTACH(device_get_parent(dev), dev, pf_schema, 113 vf_schema, buf)); 114 } 115 116 int 117 pci_iov_attach_method(device_t bus, device_t dev, nvlist_t *pf_schema, 118 nvlist_t *vf_schema, const char *name) 119 { 120 device_t pcib; 121 struct pci_devinfo *dinfo; 122 struct pcicfg_iov *iov; 123 nvlist_t *schema; 124 uint32_t version; 125 int error; 126 int iov_pos; 127 128 dinfo = device_get_ivars(dev); 129 pcib = device_get_parent(bus); 130 schema = NULL; 131 132 error = pci_find_extcap(dev, PCIZ_SRIOV, &iov_pos); 133 134 if (error != 0) 135 return (error); 136 137 version = pci_read_config(dev, iov_pos, 4); 138 if (PCI_EXTCAP_VER(version) != 1) { 139 if (bootverbose) 140 device_printf(dev, 141 "Unsupported version of SR-IOV (%d) detected\n", 142 PCI_EXTCAP_VER(version)); 143 144 return (ENXIO); 145 } 146 147 iov = malloc(sizeof(*dinfo->cfg.iov), M_SRIOV, M_WAITOK | M_ZERO); 148 149 mtx_lock(&Giant); 150 if (dinfo->cfg.iov != NULL) { 151 error = EBUSY; 152 goto cleanup; 153 } 154 iov->iov_pos = iov_pos; 155 156 schema = pci_iov_build_schema(&pf_schema, &vf_schema); 157 if (schema == NULL) { 158 error = ENOMEM; 159 goto cleanup; 160 } 161 162 error = pci_iov_validate_schema(schema); 163 if (error != 0) 164 goto cleanup; 165 iov->iov_schema = schema; 166 167 iov->iov_cdev = make_dev(&iov_cdevsw, device_get_unit(dev), 168 UID_ROOT, GID_WHEEL, 0600, "iov/%s", name); 169 170 if (iov->iov_cdev == NULL) { 171 error = ENOMEM; 172 goto cleanup; 173 } 174 175 dinfo->cfg.iov = iov; 176 iov->iov_cdev->si_drv1 = dinfo; 177 mtx_unlock(&Giant); 178 179 return (0); 180 181 cleanup: 182 nvlist_destroy(schema); 183 nvlist_destroy(pf_schema); 184 nvlist_destroy(vf_schema); 185 free(iov, M_SRIOV); 186 mtx_unlock(&Giant); 187 return (error); 188 } 189 190 int 191 pci_iov_detach_method(device_t bus, device_t dev) 192 { 193 struct pci_devinfo *dinfo; 194 struct pcicfg_iov *iov; 195 196 mtx_lock(&Giant); 197 dinfo = device_get_ivars(dev); 198 iov = dinfo->cfg.iov; 199 200 if (iov == NULL) { 201 mtx_unlock(&Giant); 202 return (0); 203 } 204 205 if (iov->iov_num_vfs != 0 || iov->iov_flags & IOV_BUSY) { 206 mtx_unlock(&Giant); 207 return (EBUSY); 208 } 209 210 dinfo->cfg.iov = NULL; 211 212 if (iov->iov_cdev) { 213 destroy_dev(iov->iov_cdev); 214 iov->iov_cdev = NULL; 215 } 216 nvlist_destroy(iov->iov_schema); 217 218 free(iov, M_SRIOV); 219 mtx_unlock(&Giant); 220 221 return (0); 222 } 223 224 static nvlist_t * 225 pci_iov_build_schema(nvlist_t **pf, nvlist_t **vf) 226 { 227 nvlist_t *schema, *pf_driver, *vf_driver; 228 229 /* We always take ownership of the schemas. */ 230 pf_driver = *pf; 231 *pf = NULL; 232 vf_driver = *vf; 233 *vf = NULL; 234 235 schema = pci_iov_schema_alloc_node(); 236 if (schema == NULL) 237 goto cleanup; 238 239 pci_iov_build_pf_schema(schema, &pf_driver); 240 pci_iov_build_vf_schema(schema, &vf_driver); 241 242 if (nvlist_error(schema) != 0) 243 goto cleanup; 244 245 return (schema); 246 247 cleanup: 248 nvlist_destroy(schema); 249 nvlist_destroy(pf_driver); 250 nvlist_destroy(vf_driver); 251 return (NULL); 252 } 253 254 static void 255 pci_iov_build_pf_schema(nvlist_t *schema, nvlist_t **driver_schema) 256 { 257 nvlist_t *pf_schema, *iov_schema; 258 259 pf_schema = pci_iov_schema_alloc_node(); 260 if (pf_schema == NULL) { 261 nvlist_set_error(schema, ENOMEM); 262 return; 263 } 264 265 iov_schema = pci_iov_get_pf_subsystem_schema(); 266 267 /* 268 * Note that if either *driver_schema or iov_schema is NULL, then 269 * nvlist_move_nvlist will put the schema in the error state and 270 * SR-IOV will fail to initialize later, so we don't have to explicitly 271 * handle that case. 272 */ 273 nvlist_move_nvlist(pf_schema, DRIVER_CONFIG_NAME, *driver_schema); 274 nvlist_move_nvlist(pf_schema, IOV_CONFIG_NAME, iov_schema); 275 nvlist_move_nvlist(schema, PF_CONFIG_NAME, pf_schema); 276 *driver_schema = NULL; 277 } 278 279 static void 280 pci_iov_build_vf_schema(nvlist_t *schema, nvlist_t **driver_schema) 281 { 282 nvlist_t *vf_schema, *iov_schema; 283 284 vf_schema = pci_iov_schema_alloc_node(); 285 if (vf_schema == NULL) { 286 nvlist_set_error(schema, ENOMEM); 287 return; 288 } 289 290 iov_schema = pci_iov_get_vf_subsystem_schema(); 291 292 /* 293 * Note that if either *driver_schema or iov_schema is NULL, then 294 * nvlist_move_nvlist will put the schema in the error state and 295 * SR-IOV will fail to initialize later, so we don't have to explicitly 296 * handle that case. 297 */ 298 nvlist_move_nvlist(vf_schema, DRIVER_CONFIG_NAME, *driver_schema); 299 nvlist_move_nvlist(vf_schema, IOV_CONFIG_NAME, iov_schema); 300 nvlist_move_nvlist(schema, VF_SCHEMA_NAME, vf_schema); 301 *driver_schema = NULL; 302 } 303 304 static nvlist_t * 305 pci_iov_get_pf_subsystem_schema(void) 306 { 307 nvlist_t *pf; 308 309 pf = pci_iov_schema_alloc_node(); 310 if (pf == NULL) 311 return (NULL); 312 313 pci_iov_schema_add_uint16(pf, "num_vfs", IOV_SCHEMA_REQUIRED, -1); 314 pci_iov_schema_add_string(pf, "device", IOV_SCHEMA_REQUIRED, NULL); 315 316 return (pf); 317 } 318 319 static nvlist_t * 320 pci_iov_get_vf_subsystem_schema(void) 321 { 322 nvlist_t *vf; 323 324 vf = pci_iov_schema_alloc_node(); 325 if (vf == NULL) 326 return (NULL); 327 328 pci_iov_schema_add_bool(vf, "passthrough", IOV_SCHEMA_HASDEFAULT, 0); 329 330 return (vf); 331 } 332 333 static int 334 pci_iov_alloc_bar(struct pci_devinfo *dinfo, int bar, pci_addr_t bar_shift) 335 { 336 struct resource *res; 337 struct pcicfg_iov *iov; 338 device_t dev, bus; 339 rman_res_t start, end; 340 pci_addr_t bar_size; 341 int rid; 342 343 iov = dinfo->cfg.iov; 344 dev = dinfo->cfg.dev; 345 bus = device_get_parent(dev); 346 rid = iov->iov_pos + PCIR_SRIOV_BAR(bar); 347 bar_size = 1 << bar_shift; 348 349 res = pci_alloc_multi_resource(bus, dev, SYS_RES_MEMORY, &rid, 0, 350 ~0, 1, iov->iov_num_vfs, RF_ACTIVE); 351 352 if (res == NULL) 353 return (ENXIO); 354 355 iov->iov_bar[bar].res = res; 356 iov->iov_bar[bar].bar_size = bar_size; 357 iov->iov_bar[bar].bar_shift = bar_shift; 358 359 start = rman_get_start(res); 360 end = rman_get_end(res); 361 return (rman_manage_region(&iov->rman, start, end)); 362 } 363 364 static void 365 pci_iov_add_bars(struct pcicfg_iov *iov, struct pci_devinfo *dinfo) 366 { 367 struct pci_iov_bar *bar; 368 uint64_t bar_start; 369 int i; 370 371 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 372 bar = &iov->iov_bar[i]; 373 if (bar->res != NULL) { 374 bar_start = rman_get_start(bar->res) + 375 dinfo->cfg.vf.index * bar->bar_size; 376 377 pci_add_bar(dinfo->cfg.dev, PCIR_BAR(i), bar_start, 378 bar->bar_shift); 379 } 380 } 381 } 382 383 static int 384 pci_iov_parse_config(struct pcicfg_iov *iov, struct pci_iov_arg *arg, 385 nvlist_t **ret) 386 { 387 void *packed_config; 388 nvlist_t *config; 389 int error; 390 391 config = NULL; 392 packed_config = NULL; 393 394 if (arg->len > pci_iov_max_config) { 395 error = EMSGSIZE; 396 goto out; 397 } 398 399 packed_config = malloc(arg->len, M_SRIOV, M_WAITOK); 400 401 error = copyin(arg->config, packed_config, arg->len); 402 if (error != 0) 403 goto out; 404 405 config = nvlist_unpack(packed_config, arg->len, NV_FLAG_IGNORE_CASE); 406 if (config == NULL) { 407 error = EINVAL; 408 goto out; 409 } 410 411 error = pci_iov_schema_validate_config(iov->iov_schema, config); 412 if (error != 0) 413 goto out; 414 415 error = nvlist_error(config); 416 if (error != 0) 417 goto out; 418 419 *ret = config; 420 config = NULL; 421 422 out: 423 nvlist_destroy(config); 424 free(packed_config, M_SRIOV); 425 return (error); 426 } 427 428 /* 429 * Set the ARI_EN bit in the lowest-numbered PCI function with the SR-IOV 430 * capability. This bit is only writeable on the lowest-numbered PF but 431 * affects all PFs on the device. 432 */ 433 static int 434 pci_iov_set_ari(device_t bus) 435 { 436 device_t lowest; 437 device_t *devlist; 438 int i, error, devcount, lowest_func, lowest_pos, iov_pos, dev_func; 439 uint16_t iov_ctl; 440 441 /* If ARI is disabled on the downstream port there is nothing to do. */ 442 if (!PCIB_ARI_ENABLED(device_get_parent(bus))) 443 return (0); 444 445 error = device_get_children(bus, &devlist, &devcount); 446 447 if (error != 0) 448 return (error); 449 450 lowest = NULL; 451 for (i = 0; i < devcount; i++) { 452 if (pci_find_extcap(devlist[i], PCIZ_SRIOV, &iov_pos) == 0) { 453 dev_func = pci_get_function(devlist[i]); 454 if (lowest == NULL || dev_func < lowest_func) { 455 lowest = devlist[i]; 456 lowest_func = dev_func; 457 lowest_pos = iov_pos; 458 } 459 } 460 } 461 free(devlist, M_TEMP); 462 463 /* 464 * If we called this function some device must have the SR-IOV 465 * capability. 466 */ 467 KASSERT(lowest != NULL, 468 ("Could not find child of %s with SR-IOV capability", 469 device_get_nameunit(bus))); 470 471 iov_ctl = pci_read_config(lowest, lowest_pos + PCIR_SRIOV_CTL, 2); 472 iov_ctl |= PCIM_SRIOV_ARI_EN; 473 pci_write_config(lowest, lowest_pos + PCIR_SRIOV_CTL, iov_ctl, 2); 474 if ((pci_read_config(lowest, lowest_pos + PCIR_SRIOV_CTL, 2) & 475 PCIM_SRIOV_ARI_EN) == 0) { 476 device_printf(lowest, "failed to enable ARI\n"); 477 return (ENXIO); 478 } 479 return (0); 480 } 481 482 static int 483 pci_iov_config_page_size(struct pci_devinfo *dinfo) 484 { 485 uint32_t page_cap, page_size; 486 487 page_cap = IOV_READ(dinfo, PCIR_SRIOV_PAGE_CAP, 4); 488 489 /* 490 * If the system page size is less than the smallest SR-IOV page size 491 * then round up to the smallest SR-IOV page size. 492 */ 493 if (PAGE_SHIFT < PCI_SRIOV_BASE_PAGE_SHIFT) 494 page_size = (1 << 0); 495 else 496 page_size = (1 << (PAGE_SHIFT - PCI_SRIOV_BASE_PAGE_SHIFT)); 497 498 /* Check that the device supports the system page size. */ 499 if (!(page_size & page_cap)) 500 return (ENXIO); 501 502 IOV_WRITE(dinfo, PCIR_SRIOV_PAGE_SIZE, page_size, 4); 503 return (0); 504 } 505 506 static int 507 pci_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *config) 508 { 509 const nvlist_t *device, *driver_config; 510 511 device = nvlist_get_nvlist(config, PF_CONFIG_NAME); 512 driver_config = nvlist_get_nvlist(device, DRIVER_CONFIG_NAME); 513 return (PCI_IOV_INIT(dev, num_vfs, driver_config)); 514 } 515 516 static int 517 pci_iov_init_rman(device_t pf, struct pcicfg_iov *iov) 518 { 519 int error; 520 521 iov->rman.rm_start = 0; 522 iov->rman.rm_end = ~0; 523 iov->rman.rm_type = RMAN_ARRAY; 524 snprintf(iov->rman_name, sizeof(iov->rman_name), "%s VF I/O memory", 525 device_get_nameunit(pf)); 526 iov->rman.rm_descr = iov->rman_name; 527 528 error = rman_init(&iov->rman); 529 if (error != 0) 530 return (error); 531 532 iov->iov_flags |= IOV_RMAN_INITED; 533 return (0); 534 } 535 536 static int 537 pci_iov_alloc_bar_ea(struct pci_devinfo *dinfo, int bar) 538 { 539 struct pcicfg_iov *iov; 540 rman_res_t start, end; 541 struct resource *res; 542 struct resource_list *rl; 543 struct resource_list_entry *rle; 544 545 rl = &dinfo->resources; 546 iov = dinfo->cfg.iov; 547 548 rle = resource_list_find(rl, SYS_RES_MEMORY, 549 iov->iov_pos + PCIR_SRIOV_BAR(bar)); 550 if (rle == NULL) 551 rle = resource_list_find(rl, SYS_RES_IOPORT, 552 iov->iov_pos + PCIR_SRIOV_BAR(bar)); 553 if (rle == NULL) 554 return (ENXIO); 555 res = rle->res; 556 557 iov->iov_bar[bar].res = res; 558 iov->iov_bar[bar].bar_size = rman_get_size(res) / iov->iov_num_vfs; 559 iov->iov_bar[bar].bar_shift = pci_mapsize(iov->iov_bar[bar].bar_size); 560 561 start = rman_get_start(res); 562 end = rman_get_end(res); 563 564 return (rman_manage_region(&iov->rman, start, end)); 565 } 566 567 static int 568 pci_iov_setup_bars(struct pci_devinfo *dinfo) 569 { 570 device_t dev; 571 struct pcicfg_iov *iov; 572 pci_addr_t bar_value, testval; 573 int i, last_64, error; 574 575 iov = dinfo->cfg.iov; 576 dev = dinfo->cfg.dev; 577 last_64 = 0; 578 579 pci_add_resources_ea(device_get_parent(dev), dev, 1); 580 581 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 582 /* First, try to use BARs allocated with EA */ 583 error = pci_iov_alloc_bar_ea(dinfo, i); 584 if (error == 0) 585 continue; 586 587 /* Allocate legacy-BAR only if EA is not enabled */ 588 if (pci_ea_is_enabled(dev, iov->iov_pos + PCIR_SRIOV_BAR(i))) 589 continue; 590 591 /* 592 * If a PCI BAR is a 64-bit wide BAR, then it spans two 593 * consecutive registers. Therefore if the last BAR that 594 * we looked at was a 64-bit BAR, we need to skip this 595 * register as it's the second half of the last BAR. 596 */ 597 if (!last_64) { 598 pci_read_bar(dev, 599 iov->iov_pos + PCIR_SRIOV_BAR(i), 600 &bar_value, &testval, &last_64); 601 602 if (testval != 0) { 603 error = pci_iov_alloc_bar(dinfo, i, 604 pci_mapsize(testval)); 605 if (error != 0) 606 return (error); 607 } 608 } else 609 last_64 = 0; 610 } 611 612 return (0); 613 } 614 615 static void 616 pci_iov_enumerate_vfs(struct pci_devinfo *dinfo, const nvlist_t *config, 617 uint16_t first_rid, uint16_t rid_stride) 618 { 619 char device_name[VF_MAX_NAME]; 620 const nvlist_t *device, *driver_config, *iov_config; 621 device_t bus, dev, vf; 622 struct pcicfg_iov *iov; 623 struct pci_devinfo *vfinfo; 624 int i, error; 625 uint16_t vid, did, next_rid; 626 627 iov = dinfo->cfg.iov; 628 dev = dinfo->cfg.dev; 629 bus = device_get_parent(dev); 630 next_rid = first_rid; 631 vid = pci_get_vendor(dev); 632 did = IOV_READ(dinfo, PCIR_SRIOV_VF_DID, 2); 633 634 for (i = 0; i < iov->iov_num_vfs; i++, next_rid += rid_stride) { 635 snprintf(device_name, sizeof(device_name), VF_PREFIX"%d", i); 636 device = nvlist_get_nvlist(config, device_name); 637 iov_config = nvlist_get_nvlist(device, IOV_CONFIG_NAME); 638 driver_config = nvlist_get_nvlist(device, DRIVER_CONFIG_NAME); 639 640 vf = PCI_CREATE_IOV_CHILD(bus, dev, next_rid, vid, did); 641 if (vf == NULL) 642 break; 643 644 /* 645 * If we are creating passthrough devices then force the ppt 646 * driver to attach to prevent a VF driver from claiming the 647 * VFs. 648 */ 649 if (nvlist_get_bool(iov_config, "passthrough")) 650 device_set_devclass_fixed(vf, "ppt"); 651 652 vfinfo = device_get_ivars(vf); 653 654 vfinfo->cfg.iov = iov; 655 vfinfo->cfg.vf.index = i; 656 657 pci_iov_add_bars(iov, vfinfo); 658 659 error = PCI_IOV_ADD_VF(dev, i, driver_config); 660 if (error != 0) { 661 device_printf(dev, "Failed to add VF %d\n", i); 662 device_delete_child(bus, vf); 663 } 664 } 665 666 bus_generic_attach(bus); 667 } 668 669 static int 670 pci_iov_config(struct cdev *cdev, struct pci_iov_arg *arg) 671 { 672 device_t bus, dev; 673 struct pci_devinfo *dinfo; 674 struct pcicfg_iov *iov; 675 nvlist_t *config; 676 int i, error; 677 uint16_t rid_off, rid_stride; 678 uint16_t first_rid, last_rid; 679 uint16_t iov_ctl; 680 uint16_t num_vfs, total_vfs; 681 int iov_inited; 682 683 mtx_lock(&Giant); 684 dinfo = cdev->si_drv1; 685 iov = dinfo->cfg.iov; 686 dev = dinfo->cfg.dev; 687 bus = device_get_parent(dev); 688 iov_inited = 0; 689 config = NULL; 690 691 if ((iov->iov_flags & IOV_BUSY) || iov->iov_num_vfs != 0) { 692 mtx_unlock(&Giant); 693 return (EBUSY); 694 } 695 iov->iov_flags |= IOV_BUSY; 696 697 error = pci_iov_parse_config(iov, arg, &config); 698 if (error != 0) 699 goto out; 700 701 num_vfs = pci_iov_config_get_num_vfs(config); 702 total_vfs = IOV_READ(dinfo, PCIR_SRIOV_TOTAL_VFS, 2); 703 if (num_vfs > total_vfs) { 704 error = EINVAL; 705 goto out; 706 } 707 708 error = pci_iov_config_page_size(dinfo); 709 if (error != 0) 710 goto out; 711 712 error = pci_iov_set_ari(bus); 713 if (error != 0) 714 goto out; 715 716 error = pci_iov_init(dev, num_vfs, config); 717 if (error != 0) 718 goto out; 719 iov_inited = 1; 720 721 IOV_WRITE(dinfo, PCIR_SRIOV_NUM_VFS, num_vfs, 2); 722 723 rid_off = IOV_READ(dinfo, PCIR_SRIOV_VF_OFF, 2); 724 rid_stride = IOV_READ(dinfo, PCIR_SRIOV_VF_STRIDE, 2); 725 726 first_rid = pci_get_rid(dev) + rid_off; 727 last_rid = first_rid + (num_vfs - 1) * rid_stride; 728 729 /* We don't yet support allocating extra bus numbers for VFs. */ 730 if (pci_get_bus(dev) != PCI_RID2BUS(last_rid)) { 731 error = ENOSPC; 732 goto out; 733 } 734 735 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2); 736 iov_ctl &= ~(PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE); 737 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2); 738 739 error = pci_iov_init_rman(dev, iov); 740 if (error != 0) 741 goto out; 742 743 iov->iov_num_vfs = num_vfs; 744 745 error = pci_iov_setup_bars(dinfo); 746 if (error != 0) 747 goto out; 748 749 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2); 750 iov_ctl |= PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE; 751 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2); 752 753 /* Per specification, we must wait 100ms before accessing VFs. */ 754 pause("iov", roundup(hz, 10)); 755 pci_iov_enumerate_vfs(dinfo, config, first_rid, rid_stride); 756 757 nvlist_destroy(config); 758 iov->iov_flags &= ~IOV_BUSY; 759 mtx_unlock(&Giant); 760 761 return (0); 762 out: 763 if (iov_inited) 764 PCI_IOV_UNINIT(dev); 765 766 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 767 if (iov->iov_bar[i].res != NULL) { 768 pci_release_resource(bus, dev, SYS_RES_MEMORY, 769 iov->iov_pos + PCIR_SRIOV_BAR(i), 770 iov->iov_bar[i].res); 771 pci_delete_resource(bus, dev, SYS_RES_MEMORY, 772 iov->iov_pos + PCIR_SRIOV_BAR(i)); 773 iov->iov_bar[i].res = NULL; 774 } 775 } 776 777 if (iov->iov_flags & IOV_RMAN_INITED) { 778 rman_fini(&iov->rman); 779 iov->iov_flags &= ~IOV_RMAN_INITED; 780 } 781 782 nvlist_destroy(config); 783 iov->iov_num_vfs = 0; 784 iov->iov_flags &= ~IOV_BUSY; 785 mtx_unlock(&Giant); 786 return (error); 787 } 788 789 void 790 pci_iov_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 791 { 792 struct pcicfg_iov *iov; 793 794 iov = dinfo->cfg.iov; 795 796 IOV_WRITE(dinfo, PCIR_SRIOV_PAGE_SIZE, iov->iov_page_size, 4); 797 IOV_WRITE(dinfo, PCIR_SRIOV_NUM_VFS, iov->iov_num_vfs, 2); 798 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov->iov_ctl, 2); 799 } 800 801 void 802 pci_iov_cfg_save(device_t dev, struct pci_devinfo *dinfo) 803 { 804 struct pcicfg_iov *iov; 805 806 iov = dinfo->cfg.iov; 807 808 iov->iov_page_size = IOV_READ(dinfo, PCIR_SRIOV_PAGE_SIZE, 4); 809 iov->iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2); 810 } 811 812 /* Return true if child is a VF of the given PF. */ 813 static int 814 pci_iov_is_child_vf(struct pcicfg_iov *pf, device_t child) 815 { 816 struct pci_devinfo *vfinfo; 817 818 vfinfo = device_get_ivars(child); 819 820 if (!(vfinfo->cfg.flags & PCICFG_VF)) 821 return (0); 822 823 return (pf == vfinfo->cfg.iov); 824 } 825 826 static int 827 pci_iov_delete(struct cdev *cdev) 828 { 829 device_t bus, dev, vf, *devlist; 830 struct pci_devinfo *dinfo; 831 struct pcicfg_iov *iov; 832 int i, error, devcount; 833 uint32_t iov_ctl; 834 835 mtx_lock(&Giant); 836 dinfo = cdev->si_drv1; 837 iov = dinfo->cfg.iov; 838 dev = dinfo->cfg.dev; 839 bus = device_get_parent(dev); 840 devlist = NULL; 841 842 if (iov->iov_flags & IOV_BUSY) { 843 mtx_unlock(&Giant); 844 return (EBUSY); 845 } 846 847 if (iov->iov_num_vfs == 0) { 848 mtx_unlock(&Giant); 849 return (ECHILD); 850 } 851 852 iov->iov_flags |= IOV_BUSY; 853 854 error = device_get_children(bus, &devlist, &devcount); 855 856 if (error != 0) 857 goto out; 858 859 for (i = 0; i < devcount; i++) { 860 vf = devlist[i]; 861 862 if (!pci_iov_is_child_vf(iov, vf)) 863 continue; 864 865 error = device_detach(vf); 866 if (error != 0) { 867 device_printf(dev, 868 "Could not disable SR-IOV: failed to detach VF %s\n", 869 device_get_nameunit(vf)); 870 goto out; 871 } 872 } 873 874 for (i = 0; i < devcount; i++) { 875 vf = devlist[i]; 876 877 if (pci_iov_is_child_vf(iov, vf)) 878 device_delete_child(bus, vf); 879 } 880 PCI_IOV_UNINIT(dev); 881 882 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2); 883 iov_ctl &= ~(PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE); 884 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2); 885 IOV_WRITE(dinfo, PCIR_SRIOV_NUM_VFS, 0, 2); 886 887 iov->iov_num_vfs = 0; 888 889 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 890 if (iov->iov_bar[i].res != NULL) { 891 pci_release_resource(bus, dev, SYS_RES_MEMORY, 892 iov->iov_pos + PCIR_SRIOV_BAR(i), 893 iov->iov_bar[i].res); 894 pci_delete_resource(bus, dev, SYS_RES_MEMORY, 895 iov->iov_pos + PCIR_SRIOV_BAR(i)); 896 iov->iov_bar[i].res = NULL; 897 } 898 } 899 900 if (iov->iov_flags & IOV_RMAN_INITED) { 901 rman_fini(&iov->rman); 902 iov->iov_flags &= ~IOV_RMAN_INITED; 903 } 904 905 error = 0; 906 out: 907 free(devlist, M_TEMP); 908 iov->iov_flags &= ~IOV_BUSY; 909 mtx_unlock(&Giant); 910 return (error); 911 } 912 913 static int 914 pci_iov_get_schema_ioctl(struct cdev *cdev, struct pci_iov_schema *output) 915 { 916 struct pci_devinfo *dinfo; 917 void *packed; 918 size_t output_len, size; 919 int error; 920 921 packed = NULL; 922 923 mtx_lock(&Giant); 924 dinfo = cdev->si_drv1; 925 packed = nvlist_pack(dinfo->cfg.iov->iov_schema, &size); 926 mtx_unlock(&Giant); 927 928 if (packed == NULL) { 929 error = ENOMEM; 930 goto fail; 931 } 932 933 output_len = output->len; 934 output->len = size; 935 if (size <= output_len) { 936 error = copyout(packed, output->schema, size); 937 938 if (error != 0) 939 goto fail; 940 941 output->error = 0; 942 } else 943 /* 944 * If we return an error then the ioctl code won't copyout 945 * output back to userland, so we flag the error in the struct 946 * instead. 947 */ 948 output->error = EMSGSIZE; 949 950 error = 0; 951 952 fail: 953 free(packed, M_NVLIST); 954 955 return (error); 956 } 957 958 static int 959 pci_iov_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag, 960 struct thread *td) 961 { 962 963 switch (cmd) { 964 case IOV_CONFIG: 965 return (pci_iov_config(dev, (struct pci_iov_arg *)data)); 966 case IOV_DELETE: 967 return (pci_iov_delete(dev)); 968 case IOV_GET_SCHEMA: 969 return (pci_iov_get_schema_ioctl(dev, 970 (struct pci_iov_schema *)data)); 971 default: 972 return (EINVAL); 973 } 974 } 975 976 struct resource * 977 pci_vf_alloc_mem_resource(device_t dev, device_t child, int *rid, 978 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 979 { 980 struct pci_devinfo *dinfo; 981 struct pcicfg_iov *iov; 982 struct pci_map *map; 983 struct resource *res; 984 struct resource_list_entry *rle; 985 rman_res_t bar_start, bar_end; 986 pci_addr_t bar_length; 987 int error; 988 989 dinfo = device_get_ivars(child); 990 iov = dinfo->cfg.iov; 991 992 map = pci_find_bar(child, *rid); 993 if (map == NULL) 994 return (NULL); 995 996 bar_length = 1 << map->pm_size; 997 bar_start = map->pm_value; 998 bar_end = bar_start + bar_length - 1; 999 1000 /* Make sure that the resource fits the constraints. */ 1001 if (bar_start >= end || bar_end <= bar_start || count != 1) 1002 return (NULL); 1003 1004 /* Clamp the resource to the constraints if necessary. */ 1005 if (bar_start < start) 1006 bar_start = start; 1007 if (bar_end > end) 1008 bar_end = end; 1009 bar_length = bar_end - bar_start + 1; 1010 1011 res = rman_reserve_resource(&iov->rman, bar_start, bar_end, 1012 bar_length, flags, child); 1013 if (res == NULL) 1014 return (NULL); 1015 1016 rle = resource_list_add(&dinfo->resources, SYS_RES_MEMORY, *rid, 1017 bar_start, bar_end, 1); 1018 if (rle == NULL) { 1019 rman_release_resource(res); 1020 return (NULL); 1021 } 1022 1023 rman_set_rid(res, *rid); 1024 1025 if (flags & RF_ACTIVE) { 1026 error = bus_activate_resource(child, SYS_RES_MEMORY, *rid, res); 1027 if (error != 0) { 1028 resource_list_delete(&dinfo->resources, SYS_RES_MEMORY, 1029 *rid); 1030 rman_release_resource(res); 1031 return (NULL); 1032 } 1033 } 1034 rle->res = res; 1035 1036 return (res); 1037 } 1038 1039 int 1040 pci_vf_release_mem_resource(device_t dev, device_t child, int rid, 1041 struct resource *r) 1042 { 1043 struct pci_devinfo *dinfo; 1044 struct resource_list_entry *rle; 1045 int error; 1046 1047 dinfo = device_get_ivars(child); 1048 1049 if (rman_get_flags(r) & RF_ACTIVE) { 1050 error = bus_deactivate_resource(child, SYS_RES_MEMORY, rid, r); 1051 if (error != 0) 1052 return (error); 1053 } 1054 1055 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, rid); 1056 if (rle != NULL) { 1057 rle->res = NULL; 1058 resource_list_delete(&dinfo->resources, SYS_RES_MEMORY, 1059 rid); 1060 } 1061 1062 return (rman_release_resource(r)); 1063 } 1064 1065