1 /*- 2 * Copyright (c) 2015, 2020 Ruslan Bukin <br@bsdpad.com> 3 * Copyright (c) 2014 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * This software was developed by Semihalf under 7 * the sponsorship of the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* Generic ECAM PCIe driver */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include "opt_platform.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/malloc.h> 41 #include <sys/kernel.h> 42 #include <sys/rman.h> 43 #include <sys/module.h> 44 #include <sys/bus.h> 45 #include <sys/endian.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcib_private.h> 50 #include <dev/pci/pci_host_generic.h> 51 52 #include <machine/bus.h> 53 #include <machine/intr.h> 54 55 #include "pcib_if.h" 56 57 /* Forward prototypes */ 58 59 static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int slot, 60 u_int func, u_int reg, int bytes); 61 static void generic_pcie_write_config(device_t dev, u_int bus, u_int slot, 62 u_int func, u_int reg, uint32_t val, int bytes); 63 static int generic_pcie_maxslots(device_t dev); 64 static int generic_pcie_read_ivar(device_t dev, device_t child, int index, 65 uintptr_t *result); 66 static int generic_pcie_write_ivar(device_t dev, device_t child, int index, 67 uintptr_t value); 68 69 int 70 pci_host_generic_core_attach(device_t dev) 71 { 72 struct generic_pcie_core_softc *sc; 73 int error; 74 int rid; 75 76 sc = device_get_softc(dev); 77 sc->dev = dev; 78 79 /* Create the parent DMA tag to pass down the coherent flag */ 80 error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 81 1, 0, /* alignment, bounds */ 82 BUS_SPACE_MAXADDR, /* lowaddr */ 83 BUS_SPACE_MAXADDR, /* highaddr */ 84 NULL, NULL, /* filter, filterarg */ 85 BUS_SPACE_MAXSIZE, /* maxsize */ 86 BUS_SPACE_UNRESTRICTED, /* nsegments */ 87 BUS_SPACE_MAXSIZE, /* maxsegsize */ 88 sc->coherent ? BUS_DMA_COHERENT : 0, /* flags */ 89 NULL, NULL, /* lockfunc, lockarg */ 90 &sc->dmat); 91 if (error != 0) 92 return (error); 93 94 rid = 0; 95 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 96 if (sc->res == NULL) { 97 device_printf(dev, "could not map memory.\n"); 98 return (ENXIO); 99 } 100 101 sc->bst = rman_get_bustag(sc->res); 102 sc->bsh = rman_get_bushandle(sc->res); 103 104 sc->mem_rman.rm_type = RMAN_ARRAY; 105 sc->mem_rman.rm_descr = "PCIe Memory"; 106 sc->io_rman.rm_type = RMAN_ARRAY; 107 sc->io_rman.rm_descr = "PCIe IO window"; 108 109 /* Initialize rman and allocate memory regions */ 110 error = rman_init(&sc->mem_rman); 111 if (error) { 112 device_printf(dev, "rman_init() failed. error = %d\n", error); 113 return (error); 114 } 115 116 error = rman_init(&sc->io_rman); 117 if (error) { 118 device_printf(dev, "rman_init() failed. error = %d\n", error); 119 return (error); 120 } 121 122 return (0); 123 } 124 125 static uint32_t 126 generic_pcie_read_config(device_t dev, u_int bus, u_int slot, 127 u_int func, u_int reg, int bytes) 128 { 129 struct generic_pcie_core_softc *sc; 130 bus_space_handle_t h; 131 bus_space_tag_t t; 132 uint64_t offset; 133 uint32_t data; 134 135 sc = device_get_softc(dev); 136 if ((bus < sc->bus_start) || (bus > sc->bus_end)) 137 return (~0U); 138 if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) || 139 (reg > PCIE_REGMAX)) 140 return (~0U); 141 142 offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg); 143 t = sc->bst; 144 h = sc->bsh; 145 146 switch (bytes) { 147 case 1: 148 data = bus_space_read_1(t, h, offset); 149 break; 150 case 2: 151 data = le16toh(bus_space_read_2(t, h, offset)); 152 break; 153 case 4: 154 data = le32toh(bus_space_read_4(t, h, offset)); 155 break; 156 default: 157 return (~0U); 158 } 159 160 return (data); 161 } 162 163 static void 164 generic_pcie_write_config(device_t dev, u_int bus, u_int slot, 165 u_int func, u_int reg, uint32_t val, int bytes) 166 { 167 struct generic_pcie_core_softc *sc; 168 bus_space_handle_t h; 169 bus_space_tag_t t; 170 uint64_t offset; 171 172 sc = device_get_softc(dev); 173 if ((bus < sc->bus_start) || (bus > sc->bus_end)) 174 return; 175 if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) || 176 (reg > PCIE_REGMAX)) 177 return; 178 179 offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg); 180 181 t = sc->bst; 182 h = sc->bsh; 183 184 switch (bytes) { 185 case 1: 186 bus_space_write_1(t, h, offset, val); 187 break; 188 case 2: 189 bus_space_write_2(t, h, offset, htole16(val)); 190 break; 191 case 4: 192 bus_space_write_4(t, h, offset, htole32(val)); 193 break; 194 default: 195 return; 196 } 197 } 198 199 static int 200 generic_pcie_maxslots(device_t dev) 201 { 202 203 return (31); /* max slots per bus acc. to standard */ 204 } 205 206 static int 207 generic_pcie_read_ivar(device_t dev, device_t child, int index, 208 uintptr_t *result) 209 { 210 struct generic_pcie_core_softc *sc; 211 212 sc = device_get_softc(dev); 213 214 if (index == PCIB_IVAR_BUS) { 215 *result = sc->bus_start; 216 return (0); 217 218 } 219 220 if (index == PCIB_IVAR_DOMAIN) { 221 *result = sc->ecam; 222 return (0); 223 } 224 225 if (bootverbose) 226 device_printf(dev, "ERROR: Unknown index %d.\n", index); 227 return (ENOENT); 228 } 229 230 static int 231 generic_pcie_write_ivar(device_t dev, device_t child, int index, 232 uintptr_t value) 233 { 234 235 return (ENOENT); 236 } 237 238 static struct rman * 239 generic_pcie_rman(struct generic_pcie_core_softc *sc, int type) 240 { 241 242 switch (type) { 243 case SYS_RES_IOPORT: 244 return (&sc->io_rman); 245 case SYS_RES_MEMORY: 246 return (&sc->mem_rman); 247 default: 248 break; 249 } 250 251 return (NULL); 252 } 253 254 int 255 pci_host_generic_core_release_resource(device_t dev, device_t child, int type, 256 int rid, struct resource *res) 257 { 258 struct generic_pcie_core_softc *sc; 259 struct rman *rm; 260 261 sc = device_get_softc(dev); 262 263 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 264 if (type == PCI_RES_BUS) { 265 return (pci_domain_release_bus(sc->ecam, child, rid, res)); 266 } 267 #endif 268 269 rm = generic_pcie_rman(sc, type); 270 if (rm != NULL) { 271 KASSERT(rman_is_region_manager(res, rm), ("rman mismatch")); 272 rman_release_resource(res); 273 } 274 275 return (bus_generic_release_resource(dev, child, type, rid, res)); 276 } 277 278 struct resource * 279 pci_host_generic_core_alloc_resource(device_t dev, device_t child, int type, 280 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 281 { 282 struct generic_pcie_core_softc *sc; 283 struct resource *res; 284 struct rman *rm; 285 286 sc = device_get_softc(dev); 287 288 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 289 if (type == PCI_RES_BUS) { 290 return (pci_domain_alloc_bus(sc->ecam, child, rid, start, end, 291 count, flags)); 292 } 293 #endif 294 295 rm = generic_pcie_rman(sc, type); 296 if (rm == NULL) 297 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 298 type, rid, start, end, count, flags)); 299 300 if (bootverbose) { 301 device_printf(dev, 302 "rman_reserve_resource: start=%#jx, end=%#jx, count=%#jx\n", 303 start, end, count); 304 } 305 306 res = rman_reserve_resource(rm, start, end, count, flags, child); 307 if (res == NULL) 308 goto fail; 309 310 rman_set_rid(res, *rid); 311 312 if (flags & RF_ACTIVE) 313 if (bus_activate_resource(child, type, *rid, res)) { 314 rman_release_resource(res); 315 goto fail; 316 } 317 318 return (res); 319 320 fail: 321 device_printf(dev, "%s FAIL: type=%d, rid=%d, " 322 "start=%016jx, end=%016jx, count=%016jx, flags=%x\n", 323 __func__, type, *rid, start, end, count, flags); 324 325 return (NULL); 326 } 327 328 static int 329 generic_pcie_activate_resource(device_t dev, device_t child, int type, 330 int rid, struct resource *r) 331 { 332 struct generic_pcie_core_softc *sc; 333 uint64_t phys_base; 334 uint64_t pci_base; 335 uint64_t size; 336 int found; 337 int res; 338 int i; 339 340 sc = device_get_softc(dev); 341 342 if ((res = rman_activate_resource(r)) != 0) 343 return (res); 344 345 switch (type) { 346 case SYS_RES_IOPORT: 347 case SYS_RES_MEMORY: 348 found = 0; 349 for (i = 0; i < MAX_RANGES_TUPLES; i++) { 350 pci_base = sc->ranges[i].pci_base; 351 phys_base = sc->ranges[i].phys_base; 352 size = sc->ranges[i].size; 353 354 if ((rman_get_start(r) >= pci_base) && (rman_get_start(r) < (pci_base + size))) { 355 found = 1; 356 break; 357 } 358 } 359 if (found) { 360 rman_set_start(r, rman_get_start(r) - pci_base + phys_base); 361 rman_set_end(r, rman_get_end(r) - pci_base + phys_base); 362 res = BUS_ACTIVATE_RESOURCE(device_get_parent(dev), 363 child, type, rid, r); 364 } else { 365 device_printf(dev, 366 "Failed to activate %s resource\n", 367 type == SYS_RES_IOPORT ? "IOPORT" : "MEMORY"); 368 res = ENXIO; 369 } 370 break; 371 case SYS_RES_IRQ: 372 res = BUS_ACTIVATE_RESOURCE(device_get_parent(dev), child, 373 type, rid, r); 374 break; 375 default: 376 break; 377 } 378 379 return (res); 380 } 381 382 static int 383 generic_pcie_deactivate_resource(device_t dev, device_t child, int type, 384 int rid, struct resource *r) 385 { 386 int res; 387 388 if ((res = rman_deactivate_resource(r)) != 0) 389 return (res); 390 391 switch (type) { 392 case SYS_RES_IOPORT: 393 case SYS_RES_MEMORY: 394 case SYS_RES_IRQ: 395 res = BUS_DEACTIVATE_RESOURCE(device_get_parent(dev), child, 396 type, rid, r); 397 break; 398 default: 399 break; 400 } 401 402 return (res); 403 } 404 405 static int 406 generic_pcie_adjust_resource(device_t dev, device_t child, int type, 407 struct resource *res, rman_res_t start, rman_res_t end) 408 { 409 struct generic_pcie_core_softc *sc; 410 struct rman *rm; 411 412 sc = device_get_softc(dev); 413 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 414 if (type == PCI_RES_BUS) 415 return (pci_domain_adjust_bus(sc->ecam, child, res, start, 416 end)); 417 #endif 418 419 rm = generic_pcie_rman(sc, type); 420 if (rm != NULL) 421 return (rman_adjust_resource(res, start, end)); 422 return (bus_generic_adjust_resource(dev, child, type, res, start, end)); 423 } 424 425 static bus_dma_tag_t 426 generic_pcie_get_dma_tag(device_t dev, device_t child) 427 { 428 struct generic_pcie_core_softc *sc; 429 430 sc = device_get_softc(dev); 431 return (sc->dmat); 432 } 433 434 static device_method_t generic_pcie_methods[] = { 435 DEVMETHOD(device_attach, pci_host_generic_core_attach), 436 DEVMETHOD(bus_read_ivar, generic_pcie_read_ivar), 437 DEVMETHOD(bus_write_ivar, generic_pcie_write_ivar), 438 DEVMETHOD(bus_alloc_resource, pci_host_generic_core_alloc_resource), 439 DEVMETHOD(bus_adjust_resource, generic_pcie_adjust_resource), 440 DEVMETHOD(bus_activate_resource, generic_pcie_activate_resource), 441 DEVMETHOD(bus_deactivate_resource, generic_pcie_deactivate_resource), 442 DEVMETHOD(bus_release_resource, pci_host_generic_core_release_resource), 443 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 444 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 445 446 DEVMETHOD(bus_get_dma_tag, generic_pcie_get_dma_tag), 447 448 /* pcib interface */ 449 DEVMETHOD(pcib_maxslots, generic_pcie_maxslots), 450 DEVMETHOD(pcib_read_config, generic_pcie_read_config), 451 DEVMETHOD(pcib_write_config, generic_pcie_write_config), 452 453 DEVMETHOD_END 454 }; 455 456 DEFINE_CLASS_0(pcib, generic_pcie_core_driver, 457 generic_pcie_methods, sizeof(struct generic_pcie_core_softc)); 458