1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2019 Michal Meloun <mmel@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 /* Armada 8k DesignWare PCIe driver */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/devmap.h> 38 #include <sys/proc.h> 39 #include <sys/kernel.h> 40 #include <sys/malloc.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <sys/rman.h> 44 #include <sys/sysctl.h> 45 46 #include <machine/bus.h> 47 #include <machine/intr.h> 48 #include <machine/resource.h> 49 50 #include <dev/extres/clk/clk.h> 51 #include <dev/extres/phy/phy.h> 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 #include <dev/ofw/ofw_pci.h> 55 #include <dev/ofw/ofwpci.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcireg.h> 58 #include <dev/pci/pcib_private.h> 59 #include <dev/pci/pci_dw.h> 60 61 #include "pcib_if.h" 62 #include "pci_dw_if.h" 63 64 #define MV_GLOBAL_CONTROL_REG 0x8000 65 #define PCIE_APP_LTSSM_EN (1 << 2) 66 67 #define MV_GLOBAL_STATUS_REG 0x8008 68 #define MV_STATUS_RDLH_LINK_UP (1 << 1) 69 #define MV_STATUS_PHY_LINK_UP (1 << 9) 70 71 #define MV_INT_CAUSE1 0x801C 72 #define MV_INT_MASK1 0x8020 73 #define INT_A_ASSERT_MASK (1 << 9) 74 #define INT_B_ASSERT_MASK (1 << 10) 75 #define INT_C_ASSERT_MASK (1 << 11) 76 #define INT_D_ASSERT_MASK (1 << 12) 77 78 #define MV_INT_CAUSE2 0x8024 79 #define MV_INT_MASK2 0x8028 80 #define MV_ERR_INT_CAUSE 0x802C 81 #define MV_ERR_INT_MASK 0x8030 82 83 #define MV_ARCACHE_TRC_REG 0x8050 84 #define MV_AWCACHE_TRC_REG 0x8054 85 #define MV_ARUSER_REG 0x805C 86 #define MV_AWUSER_REG 0x8060 87 88 #define MV_MAX_LANES 8 89 struct pci_mv_softc { 90 struct pci_dw_softc dw_sc; 91 device_t dev; 92 phandle_t node; 93 struct resource *irq_res; 94 void *intr_cookie; 95 phy_t phy[MV_MAX_LANES]; 96 clk_t clk_core; 97 clk_t clk_reg; 98 }; 99 100 /* Compatible devices. */ 101 static struct ofw_compat_data compat_data[] = { 102 {"marvell,armada8k-pcie", 1}, 103 {NULL, 0}, 104 }; 105 106 static int 107 pci_mv_phy_init(struct pci_mv_softc *sc) 108 { 109 int i, rv; 110 111 for (i = 0; i < MV_MAX_LANES; i++) { 112 rv = phy_get_by_ofw_idx(sc->dev, sc->node, i, &(sc->phy[i])); 113 if (rv != 0 && rv != ENOENT) { 114 device_printf(sc->dev, "Cannot get phy[%d]\n", i); 115 /* XXX revert when phy driver will be implemented */ 116 #if 0 117 goto fail; 118 #else 119 continue; 120 #endif 121 } 122 if (sc->phy[i] == NULL) 123 continue; 124 rv = phy_enable(sc->phy[i]); 125 if (rv != 0) { 126 device_printf(sc->dev, "Cannot enable phy[%d]\n", i); 127 goto fail; 128 } 129 } 130 return (0); 131 132 fail: 133 for (i = 0; i < MV_MAX_LANES; i++) { 134 if (sc->phy[i] == NULL) 135 continue; 136 phy_release(sc->phy[i]); 137 } 138 139 return (rv); 140 } 141 142 static void 143 pci_mv_init(struct pci_mv_softc *sc) 144 { 145 uint32_t reg; 146 147 /* Set device configuration to RC */ 148 reg = pci_dw_dbi_rd4(sc->dev, MV_GLOBAL_CONTROL_REG); 149 reg &= ~0x000000F0; 150 reg |= 0x000000040; 151 pci_dw_dbi_wr4(sc->dev, MV_GLOBAL_CONTROL_REG, reg); 152 153 /* AxCache master transaction attribures */ 154 pci_dw_dbi_wr4(sc->dev, MV_ARCACHE_TRC_REG, 0x3511); 155 pci_dw_dbi_wr4(sc->dev, MV_AWCACHE_TRC_REG, 0x5311); 156 157 /* AxDomain master transaction attribures */ 158 pci_dw_dbi_wr4(sc->dev, MV_ARUSER_REG, 0x0002); 159 pci_dw_dbi_wr4(sc->dev, MV_AWUSER_REG, 0x0002); 160 161 /* Enable all INTx interrupt (virtuual) pins */ 162 reg = pci_dw_dbi_rd4(sc->dev, MV_INT_MASK1); 163 reg |= INT_A_ASSERT_MASK | INT_B_ASSERT_MASK | 164 INT_C_ASSERT_MASK | INT_D_ASSERT_MASK; 165 pci_dw_dbi_wr4(sc->dev, MV_INT_MASK1, reg); 166 167 /* Enable local interrupts */ 168 pci_dw_dbi_wr4(sc->dev, DW_MSI_INTR0_MASK, 0xFFFFFFFF); 169 pci_dw_dbi_wr4(sc->dev, MV_INT_MASK1, 0x0001FE00); 170 pci_dw_dbi_wr4(sc->dev, MV_INT_MASK2, 0x00000000); 171 pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE1, 0xFFFFFFFF); 172 pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE2, 0xFFFFFFFF); 173 174 /* Errors have own interrupt, not yet populated in DTt */ 175 pci_dw_dbi_wr4(sc->dev, MV_ERR_INT_MASK, 0); 176 } 177 178 static int pci_mv_intr(void *arg) 179 { 180 struct pci_mv_softc *sc = arg; 181 uint32_t cause1, cause2; 182 183 /* Ack all interrups */ 184 cause1 = pci_dw_dbi_rd4(sc->dev, MV_INT_CAUSE1); 185 cause2 = pci_dw_dbi_rd4(sc->dev, MV_INT_CAUSE2); 186 187 pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE1, cause1); 188 pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE2, cause2); 189 return (FILTER_HANDLED); 190 } 191 192 static int 193 pci_mv_get_link(device_t dev, bool *status) 194 { 195 uint32_t reg; 196 197 reg = pci_dw_dbi_rd4(dev, MV_GLOBAL_STATUS_REG); 198 if ((reg & (MV_STATUS_RDLH_LINK_UP | MV_STATUS_PHY_LINK_UP)) == 199 (MV_STATUS_RDLH_LINK_UP | MV_STATUS_PHY_LINK_UP)) 200 *status = true; 201 else 202 *status = false; 203 204 return (0); 205 } 206 207 static int 208 pci_mv_probe(device_t dev) 209 { 210 211 if (!ofw_bus_status_okay(dev)) 212 return (ENXIO); 213 214 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 215 return (ENXIO); 216 217 device_set_desc(dev, "Marvell Armada8K PCI-E Controller"); 218 return (BUS_PROBE_DEFAULT); 219 } 220 221 static int 222 pci_mv_attach(device_t dev) 223 { 224 struct resource_map_request req; 225 struct resource_map map; 226 struct pci_mv_softc *sc; 227 phandle_t node; 228 int rv; 229 int rid; 230 231 sc = device_get_softc(dev); 232 node = ofw_bus_get_node(dev); 233 sc->dev = dev; 234 sc->node = node; 235 236 rid = 0; 237 sc->dw_sc.dbi_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 238 RF_ACTIVE | RF_UNMAPPED); 239 if (sc->dw_sc.dbi_res == NULL) { 240 device_printf(dev, "Cannot allocate DBI memory\n"); 241 rv = ENXIO; 242 goto out; 243 } 244 245 resource_init_map_request(&req); 246 req.memattr = VM_MEMATTR_DEVICE_NP; 247 rv = bus_map_resource(dev, SYS_RES_MEMORY, sc->dw_sc.dbi_res, &req, 248 &map); 249 if (rv != 0) { 250 device_printf(dev, "could not map memory.\n"); 251 return (rv); 252 } 253 rman_set_mapping(sc->dw_sc.dbi_res, &map); 254 255 /* PCI interrupt */ 256 rid = 0; 257 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 258 RF_ACTIVE | RF_SHAREABLE); 259 if (sc->irq_res == NULL) { 260 device_printf(dev, "Cannot allocate IRQ resources\n"); 261 rv = ENXIO; 262 goto out; 263 } 264 265 /* Clocks */ 266 rv = clk_get_by_ofw_name(sc->dev, 0, "core", &sc->clk_core); 267 if (rv != 0) { 268 device_printf(sc->dev, "Cannot get 'core' clock\n"); 269 rv = ENXIO; 270 goto out; 271 } 272 273 rv = clk_get_by_ofw_name(sc->dev, 0, "reg", &sc->clk_reg); 274 if (rv != 0) { 275 device_printf(sc->dev, "Cannot get 'reg' clock\n"); 276 rv = ENXIO; 277 goto out; 278 } 279 280 rv = clk_enable(sc->clk_core); 281 if (rv != 0) { 282 device_printf(sc->dev, "Cannot enable 'core' clock\n"); 283 rv = ENXIO; 284 goto out; 285 } 286 287 rv = clk_enable(sc->clk_reg); 288 if (rv != 0) { 289 device_printf(sc->dev, "Cannot enable 'reg' clock\n"); 290 rv = ENXIO; 291 goto out; 292 } 293 294 rv = pci_mv_phy_init(sc); 295 if (rv) 296 goto out; 297 298 rv = pci_dw_init(dev); 299 if (rv != 0) 300 goto out; 301 302 pci_mv_init(sc); 303 304 /* Setup interrupt */ 305 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 306 pci_mv_intr, NULL, sc, &sc->intr_cookie)) { 307 device_printf(dev, "cannot setup interrupt handler\n"); 308 rv = ENXIO; 309 goto out; 310 } 311 312 return (bus_generic_attach(dev)); 313 out: 314 /* XXX Cleanup */ 315 return (rv); 316 } 317 318 static device_method_t pci_mv_methods[] = { 319 /* Device interface */ 320 DEVMETHOD(device_probe, pci_mv_probe), 321 DEVMETHOD(device_attach, pci_mv_attach), 322 323 DEVMETHOD(pci_dw_get_link, pci_mv_get_link), 324 325 DEVMETHOD_END 326 }; 327 328 DEFINE_CLASS_1(pcib, pci_mv_driver, pci_mv_methods, 329 sizeof(struct pci_mv_softc), pci_dw_driver); 330 DRIVER_MODULE( pci_mv, simplebus, pci_mv_driver, NULL, NULL); 331