1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2019 Michal Meloun <mmel@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 /* Base class for all Synopsys DesignWare PCI/PCIe drivers */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/devmap.h> 39 #include <sys/proc.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/malloc.h> 43 #include <sys/module.h> 44 #include <sys/mutex.h> 45 #include <sys/rman.h> 46 47 #include <machine/bus.h> 48 #include <machine/intr.h> 49 #include <machine/resource.h> 50 51 #include <dev/ofw/ofw_bus.h> 52 #include <dev/ofw/ofw_bus_subr.h> 53 #include <dev/ofw/ofw_pci.h> 54 #include <dev/ofw/ofwpci.h> 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcib_private.h> 58 #include <dev/pci/pci_dw.h> 59 60 #include "pcib_if.h" 61 #include "pci_dw_if.h" 62 63 #define DEBUG 64 #ifdef DEBUG 65 #define debugf(fmt, args...) do { printf(fmt,##args); } while (0) 66 #else 67 #define debugf(fmt, args...) 68 #endif 69 70 #define DBI_WR1(sc, reg, val) pci_dw_dbi_wr1((sc)->dev, reg, val) 71 #define DBI_WR2(sc, reg, val) pci_dw_dbi_wr2((sc)->dev, reg, val) 72 #define DBI_WR4(sc, reg, val) pci_dw_dbi_wr4((sc)->dev, reg, val) 73 #define DBI_RD1(sc, reg) pci_dw_dbi_rd1((sc)->dev, reg) 74 #define DBI_RD2(sc, reg) pci_dw_dbi_rd2((sc)->dev, reg) 75 #define DBI_RD4(sc, reg) pci_dw_dbi_rd4((sc)->dev, reg) 76 77 #define PCI_BUS_SHIFT 20 78 #define PCI_SLOT_SHIFT 15 79 #define PCI_FUNC_SHIFT 12 80 #define PCI_BUS_MASK 0xFF 81 #define PCI_SLOT_MASK 0x1F 82 #define PCI_FUNC_MASK 0x07 83 #define PCI_REG_MASK 0xFFF 84 85 86 #define IATU_CFG_BUS(bus) ((uint64_t)((bus) & 0xff) << 24) 87 #define IATU_CFG_SLOT(slot) ((uint64_t)((slot) & 0x1f) << 19) 88 #define IATU_CFG_FUNC(func) ((uint64_t)((func) & 0x07) << 16) 89 90 91 92 static uint32_t 93 pci_dw_dbi_read(device_t dev, u_int reg, int width) 94 { 95 struct pci_dw_softc *sc; 96 97 sc = device_get_softc(dev); 98 MPASS(sc->dbi_res != NULL); 99 100 switch (width) { 101 case 4: 102 return (bus_read_4(sc->dbi_res, reg)); 103 case 2: 104 return (bus_read_2(sc->dbi_res, reg)); 105 case 1: 106 return (bus_read_1(sc->dbi_res, reg)); 107 default: 108 device_printf(sc->dev, "Unsupported width: %d\n", width); 109 return (0xFFFFFFFF); 110 } 111 } 112 113 static void 114 pci_dw_dbi_write(device_t dev, u_int reg, uint32_t val, int width) 115 { 116 struct pci_dw_softc *sc; 117 118 sc = device_get_softc(dev); 119 MPASS(sc->dbi_res != NULL); 120 121 switch (width) { 122 case 4: 123 bus_write_4(sc->dbi_res, reg, val); 124 break; 125 case 2: 126 bus_write_2(sc->dbi_res, reg, val); 127 break; 128 case 1: 129 bus_write_1(sc->dbi_res, reg, val); 130 break; 131 default: 132 device_printf(sc->dev, "Unsupported width: %d\n", width); 133 break; 134 } 135 } 136 137 138 static void 139 pci_dw_dbi_protect(struct pci_dw_softc *sc, bool protect) 140 { 141 uint32_t reg; 142 143 reg = DBI_RD4(sc, DW_MISC_CONTROL_1); 144 if (protect) 145 reg &= ~DBI_RO_WR_EN; 146 else 147 reg |= DBI_RO_WR_EN; 148 DBI_WR4(sc, DW_MISC_CONTROL_1, reg); 149 } 150 151 static bool 152 pci_dw_check_dev(struct pci_dw_softc *sc, u_int bus, u_int slot, u_int func, 153 u_int reg) 154 { 155 bool status; 156 int rv; 157 158 if (bus < sc->bus_start || bus > sc->bus_end || slot > PCI_SLOTMAX || 159 func > PCI_FUNCMAX || reg > PCI_REGMAX) 160 return (false); 161 162 /* link is needed for access to all non-root busses */ 163 if (bus != sc->root_bus) { 164 rv = PCI_DW_GET_LINK(sc->dev, &status); 165 if (rv != 0 || !status) 166 return (false); 167 return (true); 168 } 169 170 /* we have only 1 device with 1 function root port */ 171 if (slot > 0 || func > 0) 172 return (false); 173 return (true); 174 } 175 176 /* Map one uoutbound ATU region */ 177 static int 178 pci_dw_map_out_atu(struct pci_dw_softc *sc, int idx, int type, 179 uint64_t pa, uint64_t pci_addr, uint32_t size) 180 { 181 uint32_t reg; 182 int i; 183 184 if (size == 0) 185 return (0); 186 187 DBI_WR4(sc, DW_IATU_VIEWPORT, IATU_REGION_INDEX(idx)); 188 DBI_WR4(sc, DW_IATU_LWR_BASE_ADDR, pa & 0xFFFFFFFF); 189 DBI_WR4(sc, DW_IATU_UPPER_BASE_ADDR, (pa >> 32) & 0xFFFFFFFF); 190 DBI_WR4(sc, DW_IATU_LIMIT_ADDR, (pa + size - 1) & 0xFFFFFFFF); 191 DBI_WR4(sc, DW_IATU_LWR_TARGET_ADDR, pci_addr & 0xFFFFFFFF); 192 DBI_WR4(sc, DW_IATU_UPPER_TARGET_ADDR, (pci_addr >> 32) & 0xFFFFFFFF); 193 DBI_WR4(sc, DW_IATU_CTRL1, IATU_CTRL1_TYPE(type)); 194 DBI_WR4(sc, DW_IATU_CTRL2, IATU_CTRL2_REGION_EN); 195 196 /* Wait until setup becomes valid */ 197 for (i = 10; i > 0; i--) { 198 reg = DBI_RD4(sc, DW_IATU_CTRL2); 199 if (reg & IATU_CTRL2_REGION_EN) 200 return (0); 201 DELAY(5); 202 } 203 device_printf(sc->dev, 204 "Cannot map outbound region(%d) in iATU\n", idx); 205 return (ETIMEDOUT); 206 } 207 208 static int 209 pci_dw_setup_hw(struct pci_dw_softc *sc) 210 { 211 uint32_t reg; 212 int rv; 213 214 pci_dw_dbi_protect(sc, false); 215 216 /* Setup config registers */ 217 DBI_WR1(sc, PCIR_CLASS, PCIC_BRIDGE); 218 DBI_WR1(sc, PCIR_SUBCLASS, PCIS_BRIDGE_PCI); 219 DBI_WR4(sc, PCIR_BAR(0), 4); 220 DBI_WR4(sc, PCIR_BAR(1), 0); 221 DBI_WR1(sc, PCIR_INTPIN, 1); 222 DBI_WR1(sc, PCIR_PRIBUS_1, sc->root_bus); 223 DBI_WR1(sc, PCIR_SECBUS_1, sc->sub_bus); 224 DBI_WR1(sc, PCIR_SUBBUS_1, sc->bus_end); 225 DBI_WR2(sc, PCIR_COMMAND, 226 PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | 227 PCIM_CMD_BUSMASTEREN | PCIM_CMD_SERRESPEN); 228 pci_dw_dbi_protect(sc, true); 229 230 /* Setup outbound memory window */ 231 rv = pci_dw_map_out_atu(sc, 0, IATU_CTRL1_TYPE_MEM, 232 sc->mem_range.host, sc->mem_range.pci, sc->mem_range.size); 233 if (rv != 0) 234 return (rv); 235 236 /* If we have enouht viewports ..*/ 237 if (sc->num_viewport >= 3) { 238 /* Setup outbound I/O window */ 239 rv = pci_dw_map_out_atu(sc, 0, IATU_CTRL1_TYPE_MEM, 240 sc->io_range.host, sc->io_range.pci, sc->io_range.size); 241 if (rv != 0) 242 return (rv); 243 } 244 /* XXX Should we handle also prefetch memory? */ 245 246 247 /* Adjust number of lanes */ 248 reg = DBI_RD4(sc, DW_PORT_LINK_CTRL); 249 reg &= ~PORT_LINK_CAPABLE(~0); 250 switch (sc->num_lanes) { 251 case 1: 252 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_1); 253 break; 254 case 2: 255 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_2); 256 break; 257 case 4: 258 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_4); 259 break; 260 case 8: 261 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_8); 262 break; 263 case 16: 264 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_16); 265 break; 266 case 32: 267 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_32); 268 break; 269 default: 270 device_printf(sc->dev, 271 "'num-lanes' property have invalid value: %d\n", 272 sc->num_lanes); 273 return (EINVAL); 274 } 275 DBI_WR4(sc, DW_PORT_LINK_CTRL, reg); 276 277 278 /* And link width */ 279 reg = DBI_RD4(sc, DW_GEN2_CTRL); 280 reg &= ~GEN2_CTRL_NUM_OF_LANES(~0); 281 switch (sc->num_lanes) { 282 case 1: 283 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_1); 284 break; 285 case 2: 286 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_2); 287 break; 288 case 4: 289 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_4); 290 break; 291 case 8: 292 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_8); 293 break; 294 case 16: 295 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_16); 296 break; 297 case 32: 298 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_32); 299 break; 300 } 301 DBI_WR4(sc, DW_GEN2_CTRL, reg); 302 303 reg = DBI_RD4(sc, DW_GEN2_CTRL); 304 reg |= DIRECT_SPEED_CHANGE; 305 DBI_WR4(sc, DW_GEN2_CTRL, reg); 306 307 308 return (0); 309 } 310 311 static int 312 pci_dw_decode_ranges(struct pci_dw_softc *sc, struct ofw_pci_range *ranges, 313 int nranges) 314 { 315 int i; 316 317 for (i = 0; i < nranges; i++) { 318 if ((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) == 319 OFW_PCI_PHYS_HI_SPACE_IO) { 320 if (sc->io_range.size != 0) { 321 device_printf(sc->dev, 322 "Duplicated IO range found in DT\n"); 323 return (ENXIO); 324 } 325 sc->io_range = ranges[i]; 326 } 327 if (((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) == 328 OFW_PCI_PHYS_HI_SPACE_MEM32)) { 329 if (ranges[i].pci_hi & OFW_PCI_PHYS_HI_PREFETCHABLE) { 330 if (sc->pref_mem_range.size != 0) { 331 device_printf(sc->dev, 332 "Duplicated memory range found " 333 "in DT\n"); 334 return (ENXIO); 335 } 336 sc->pref_mem_range = ranges[i]; 337 } else { 338 if (sc->mem_range.size != 0) { 339 device_printf(sc->dev, 340 "Duplicated memory range found " 341 "in DT\n"); 342 return (ENXIO); 343 } 344 sc->mem_range = ranges[i]; 345 } 346 } 347 } 348 if ((sc->io_range.size == 0) || (sc->mem_range.size == 0)) { 349 device_printf(sc->dev, 350 " Not all required ranges are found in DT\n"); 351 return (ENXIO); 352 } 353 return (0); 354 } 355 356 357 358 /*----------------------------------------------------------------------------- 359 * 360 * P C I B I N T E R F A C E 361 */ 362 363 static uint32_t 364 pci_dw_read_config(device_t dev, u_int bus, u_int slot, 365 u_int func, u_int reg, int bytes) 366 { 367 struct pci_dw_softc *sc; 368 struct resource *res; 369 uint32_t data; 370 uint64_t addr; 371 int type, rv; 372 373 sc = device_get_softc(dev); 374 375 if (!pci_dw_check_dev(sc, bus, slot, func, reg)) 376 return (0xFFFFFFFFU); 377 378 if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) || 379 (reg > PCI_REGMAX)) 380 return (0xFFFFFFFFU); 381 382 if (bus == sc->root_bus) { 383 res = (sc->dbi_res); 384 } else { 385 addr = IATU_CFG_BUS(bus) | IATU_CFG_SLOT(slot) | 386 IATU_CFG_FUNC(func); 387 if (bus == sc->sub_bus) 388 type = IATU_CTRL1_TYPE_CFG0; 389 else 390 type = IATU_CTRL1_TYPE_CFG1; 391 rv = pci_dw_map_out_atu(sc, 1, type, 392 sc->cfg_pa, addr, sc->cfg_size); 393 if (rv != 0) 394 return (0xFFFFFFFFU); 395 res = sc->cfg_res; 396 } 397 398 switch (bytes) { 399 case 1: 400 data = bus_read_1(res, reg); 401 break; 402 case 2: 403 data = bus_read_2(res, reg); 404 break; 405 case 4: 406 data = bus_read_4(res, reg); 407 break; 408 default: 409 data = 0xFFFFFFFFU; 410 } 411 412 return (data); 413 414 } 415 416 static void 417 pci_dw_write_config(device_t dev, u_int bus, u_int slot, 418 u_int func, u_int reg, uint32_t val, int bytes) 419 { 420 struct pci_dw_softc *sc; 421 struct resource *res; 422 uint64_t addr; 423 int type, rv; 424 425 sc = device_get_softc(dev); 426 if (!pci_dw_check_dev(sc, bus, slot, func, reg)) 427 return; 428 429 if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) || 430 (reg > PCI_REGMAX)) 431 return; 432 433 if (bus == sc->root_bus) { 434 res = (sc->dbi_res); 435 } else { 436 addr = IATU_CFG_BUS(bus) | IATU_CFG_SLOT(slot) | 437 IATU_CFG_FUNC(func); 438 if (bus == sc->sub_bus) 439 type = IATU_CTRL1_TYPE_CFG0; 440 else 441 type = IATU_CTRL1_TYPE_CFG1; 442 rv = pci_dw_map_out_atu(sc, 1, type, 443 sc->cfg_pa, addr, sc->cfg_size); 444 if (rv != 0) 445 return ; 446 res = sc->cfg_res; 447 } 448 449 450 switch (bytes) { 451 case 1: 452 bus_write_1(res, reg, val); 453 break; 454 case 2: 455 bus_write_2(res, reg, val); 456 break; 457 case 4: 458 bus_write_4(res, reg, val); 459 break; 460 default: 461 break; 462 } 463 } 464 465 static int 466 pci_dw_alloc_msi(device_t pci, device_t child, int count, 467 int maxcount, int *irqs) 468 { 469 phandle_t msi_parent; 470 int rv; 471 472 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 473 &msi_parent, NULL); 474 if (rv != 0) 475 return (rv); 476 477 return (intr_alloc_msi(pci, child, msi_parent, count, maxcount, 478 irqs)); 479 } 480 481 static int 482 pci_dw_release_msi(device_t pci, device_t child, int count, int *irqs) 483 { 484 phandle_t msi_parent; 485 int rv; 486 487 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 488 &msi_parent, NULL); 489 if (rv != 0) 490 return (rv); 491 return (intr_release_msi(pci, child, msi_parent, count, irqs)); 492 } 493 494 static int 495 pci_dw_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 496 uint32_t *data) 497 { 498 phandle_t msi_parent; 499 int rv; 500 501 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 502 &msi_parent, NULL); 503 if (rv != 0) 504 return (rv); 505 506 return (intr_map_msi(pci, child, msi_parent, irq, addr, data)); 507 } 508 509 static int 510 pci_dw_alloc_msix(device_t pci, device_t child, int *irq) 511 { 512 phandle_t msi_parent; 513 int rv; 514 515 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 516 &msi_parent, NULL); 517 if (rv != 0) 518 return (rv); 519 return (intr_alloc_msix(pci, child, msi_parent, irq)); 520 } 521 522 static int 523 pci_dw_release_msix(device_t pci, device_t child, int irq) 524 { 525 phandle_t msi_parent; 526 int rv; 527 528 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 529 &msi_parent, NULL); 530 if (rv != 0) 531 return (rv); 532 return (intr_release_msix(pci, child, msi_parent, irq)); 533 } 534 535 static int 536 pci_dw_get_id(device_t pci, device_t child, enum pci_id_type type, 537 uintptr_t *id) 538 { 539 phandle_t node; 540 int rv; 541 uint32_t rid; 542 uint16_t pci_rid; 543 544 if (type != PCI_ID_MSI) 545 return (pcib_get_id(pci, child, type, id)); 546 547 node = ofw_bus_get_node(pci); 548 pci_rid = pci_get_rid(child); 549 550 rv = ofw_bus_msimap(node, pci_rid, NULL, &rid); 551 if (rv != 0) 552 return (rv); 553 *id = rid; 554 555 return (0); 556 } 557 558 /*----------------------------------------------------------------------------- 559 * 560 * B U S / D E V I C E I N T E R F A C E 561 */ 562 static bus_dma_tag_t 563 pci_dw_get_dma_tag(device_t dev, device_t child) 564 { 565 struct pci_dw_softc *sc; 566 567 sc = device_get_softc(dev); 568 return (sc->dmat); 569 } 570 571 int 572 pci_dw_init(device_t dev) 573 { 574 struct pci_dw_softc *sc; 575 int rv, rid; 576 577 sc = device_get_softc(dev); 578 sc->dev = dev; 579 sc->node = ofw_bus_get_node(dev); 580 581 mtx_init(&sc->mtx, "pci_dw_mtx", NULL, MTX_DEF); 582 583 /* XXXn Should not be this configurable ? */ 584 sc->bus_start = 0; 585 sc->bus_end = 255; 586 sc->root_bus = 0; 587 sc->sub_bus = 1; 588 589 /* Read FDT properties */ 590 if (!sc->coherent) 591 sc->coherent = OF_hasprop(sc->node, "dma-coherent"); 592 593 rv = OF_getencprop(sc->node, "num-viewport", &sc->num_viewport, 594 sizeof(sc->num_viewport)); 595 if (rv != sizeof(sc->num_viewport)) 596 sc->num_viewport = 2; 597 598 rv = OF_getencprop(sc->node, "num-lanes", &sc->num_lanes, 599 sizeof(sc->num_viewport)); 600 if (rv != sizeof(sc->num_lanes)) 601 sc->num_lanes = 1; 602 if (sc->num_lanes != 1 && sc->num_lanes != 2 && 603 sc->num_lanes != 4 && sc->num_lanes != 8) { 604 device_printf(dev, 605 "invalid number of lanes: %d\n",sc->num_lanes); 606 sc->num_lanes = 0; 607 rv = ENXIO; 608 goto out; 609 } 610 611 rid = 0; 612 rv = ofw_bus_find_string_index(sc->node, "reg-names", "config", &rid); 613 if (rv != 0) { 614 device_printf(dev, "Cannot get config space memory\n"); 615 rv = ENXIO; 616 goto out; 617 } 618 sc->cfg_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 619 RF_ACTIVE); 620 if (sc->cfg_res == NULL) { 621 device_printf(dev, "Cannot allocate config space(rid: %d)\n", 622 rid); 623 rv = ENXIO; 624 goto out; 625 } 626 627 /* Fill up config region related variables */ 628 sc->cfg_size = rman_get_size(sc->cfg_res); 629 sc->cfg_pa = rman_get_start(sc->cfg_res) ; 630 631 if (bootverbose) 632 device_printf(dev, "Bus is%s cache-coherent\n", 633 sc->coherent ? "" : " not"); 634 rv = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 635 1, 0, /* alignment, bounds */ 636 BUS_SPACE_MAXADDR, /* lowaddr */ 637 BUS_SPACE_MAXADDR, /* highaddr */ 638 NULL, NULL, /* filter, filterarg */ 639 BUS_SPACE_MAXSIZE, /* maxsize */ 640 BUS_SPACE_UNRESTRICTED, /* nsegments */ 641 BUS_SPACE_MAXSIZE, /* maxsegsize */ 642 sc->coherent ? BUS_DMA_COHERENT : 0, /* flags */ 643 NULL, NULL, /* lockfunc, lockarg */ 644 &sc->dmat); 645 if (rv != 0) 646 goto out; 647 648 rv = ofw_pci_init(dev); 649 if (rv != 0) 650 goto out; 651 rv = pci_dw_decode_ranges(sc, sc->ofw_pci.sc_range, 652 sc->ofw_pci.sc_nrange); 653 if (rv != 0) 654 goto out; 655 656 rv = pci_dw_setup_hw(sc); 657 if (rv != 0) 658 goto out; 659 660 device_add_child(dev, "pci", -1); 661 662 return (bus_generic_attach(dev)); 663 out: 664 /* XXX Cleanup */ 665 return (rv); 666 } 667 668 static device_method_t pci_dw_methods[] = { 669 670 /* Bus interface */ 671 DEVMETHOD(bus_get_dma_tag, pci_dw_get_dma_tag), 672 673 /* pcib interface */ 674 DEVMETHOD(pcib_read_config, pci_dw_read_config), 675 DEVMETHOD(pcib_write_config, pci_dw_write_config), 676 DEVMETHOD(pcib_alloc_msi, pci_dw_alloc_msi), 677 DEVMETHOD(pcib_release_msi, pci_dw_release_msi), 678 DEVMETHOD(pcib_alloc_msix, pci_dw_alloc_msix), 679 DEVMETHOD(pcib_release_msix, pci_dw_release_msix), 680 DEVMETHOD(pcib_map_msi, pci_dw_map_msi), 681 DEVMETHOD(pcib_get_id, pci_dw_get_id), 682 683 /* OFW bus interface */ 684 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 685 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 686 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 687 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 688 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 689 690 /* PCI DW interface */ 691 DEVMETHOD(pci_dw_dbi_read, pci_dw_dbi_read), 692 DEVMETHOD(pci_dw_dbi_write, pci_dw_dbi_write), 693 DEVMETHOD_END 694 }; 695 696 DEFINE_CLASS_1(pcib, pci_dw_driver, pci_dw_methods, 697 sizeof(struct pci_dw_softc), ofw_pci_driver); 698