1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 5 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 6 * Copyright (c) 2000, BSDi 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice unmodified, this list of conditions, and the following 14 * disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include "opt_acpi.h" 35 #include "opt_bus.h" 36 37 #include <sys/param.h> 38 #include <sys/conf.h> 39 #include <sys/endian.h> 40 #include <sys/eventhandler.h> 41 #include <sys/fcntl.h> 42 #include <sys/kernel.h> 43 #include <sys/limits.h> 44 #include <sys/linker.h> 45 #include <sys/malloc.h> 46 #include <sys/module.h> 47 #include <sys/queue.h> 48 #include <sys/sysctl.h> 49 #include <sys/systm.h> 50 51 #include <vm/vm.h> 52 #include <vm/pmap.h> 53 #include <vm/vm_extern.h> 54 55 #include <sys/bus.h> 56 #include <machine/bus.h> 57 #include <sys/rman.h> 58 #include <machine/resource.h> 59 #include <machine/stdarg.h> 60 61 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 62 #include <machine/intr_machdep.h> 63 #endif 64 65 #include <sys/pciio.h> 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/pci_private.h> 69 70 #ifdef PCI_IOV 71 #include <sys/nv.h> 72 #include <dev/pci/pci_iov_private.h> 73 #endif 74 75 #include <dev/usb/controller/xhcireg.h> 76 #include <dev/usb/controller/ehcireg.h> 77 #include <dev/usb/controller/ohcireg.h> 78 #include <dev/usb/controller/uhcireg.h> 79 80 #include "pcib_if.h" 81 #include "pci_if.h" 82 83 #define PCIR_IS_BIOS(cfg, reg) \ 84 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \ 85 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1)) 86 87 static int pci_has_quirk(uint32_t devid, int quirk); 88 static pci_addr_t pci_mapbase(uint64_t mapreg); 89 static const char *pci_maptype(uint64_t mapreg); 90 static int pci_maprange(uint64_t mapreg); 91 static pci_addr_t pci_rombase(uint64_t mapreg); 92 static int pci_romsize(uint64_t testval); 93 static void pci_fixancient(pcicfgregs *cfg); 94 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...); 95 96 static int pci_porten(device_t dev); 97 static int pci_memen(device_t dev); 98 static void pci_assign_interrupt(device_t bus, device_t dev, 99 int force_route); 100 static int pci_add_map(device_t bus, device_t dev, int reg, 101 struct resource_list *rl, int force, int prefetch); 102 static int pci_probe(device_t dev); 103 static void pci_load_vendor_data(void); 104 static int pci_describe_parse_line(char **ptr, int *vendor, 105 int *device, char **desc); 106 static char *pci_describe_device(device_t dev); 107 static int pci_modevent(module_t mod, int what, void *arg); 108 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 109 pcicfgregs *cfg); 110 static void pci_read_cap(device_t pcib, pcicfgregs *cfg); 111 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 112 int reg, uint32_t *data); 113 #if 0 114 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 115 int reg, uint32_t data); 116 #endif 117 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 118 static void pci_mask_msix(device_t dev, u_int index); 119 static void pci_unmask_msix(device_t dev, u_int index); 120 static int pci_msi_blacklisted(void); 121 static int pci_msix_blacklisted(void); 122 static void pci_resume_msi(device_t dev); 123 static void pci_resume_msix(device_t dev); 124 static int pci_remap_intr_method(device_t bus, device_t dev, 125 u_int irq); 126 static void pci_hint_device_unit(device_t acdev, device_t child, 127 const char *name, int *unitp); 128 static int pci_reset_post(device_t dev, device_t child); 129 static int pci_reset_prepare(device_t dev, device_t child); 130 static int pci_reset_child(device_t dev, device_t child, 131 int flags); 132 133 static int pci_get_id_method(device_t dev, device_t child, 134 enum pci_id_type type, uintptr_t *rid); 135 136 static struct pci_devinfo * pci_fill_devinfo(device_t pcib, device_t bus, int d, 137 int b, int s, int f, uint16_t vid, uint16_t did); 138 139 static device_method_t pci_methods[] = { 140 /* Device interface */ 141 DEVMETHOD(device_probe, pci_probe), 142 DEVMETHOD(device_attach, pci_attach), 143 DEVMETHOD(device_detach, pci_detach), 144 DEVMETHOD(device_shutdown, bus_generic_shutdown), 145 DEVMETHOD(device_suspend, bus_generic_suspend), 146 DEVMETHOD(device_resume, pci_resume), 147 148 /* Bus interface */ 149 DEVMETHOD(bus_print_child, pci_print_child), 150 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 151 DEVMETHOD(bus_read_ivar, pci_read_ivar), 152 DEVMETHOD(bus_write_ivar, pci_write_ivar), 153 DEVMETHOD(bus_driver_added, pci_driver_added), 154 DEVMETHOD(bus_setup_intr, pci_setup_intr), 155 DEVMETHOD(bus_teardown_intr, pci_teardown_intr), 156 DEVMETHOD(bus_reset_prepare, pci_reset_prepare), 157 DEVMETHOD(bus_reset_post, pci_reset_post), 158 DEVMETHOD(bus_reset_child, pci_reset_child), 159 160 DEVMETHOD(bus_get_dma_tag, pci_get_dma_tag), 161 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 162 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 163 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 164 DEVMETHOD(bus_delete_resource, pci_delete_resource), 165 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 166 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 167 DEVMETHOD(bus_release_resource, pci_release_resource), 168 DEVMETHOD(bus_activate_resource, pci_activate_resource), 169 DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource), 170 DEVMETHOD(bus_child_deleted, pci_child_deleted), 171 DEVMETHOD(bus_child_detached, pci_child_detached), 172 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 173 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 174 DEVMETHOD(bus_hint_device_unit, pci_hint_device_unit), 175 DEVMETHOD(bus_remap_intr, pci_remap_intr_method), 176 DEVMETHOD(bus_suspend_child, pci_suspend_child), 177 DEVMETHOD(bus_resume_child, pci_resume_child), 178 DEVMETHOD(bus_rescan, pci_rescan_method), 179 180 /* PCI interface */ 181 DEVMETHOD(pci_read_config, pci_read_config_method), 182 DEVMETHOD(pci_write_config, pci_write_config_method), 183 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 184 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 185 DEVMETHOD(pci_enable_io, pci_enable_io_method), 186 DEVMETHOD(pci_disable_io, pci_disable_io_method), 187 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 188 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 189 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 190 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 191 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 192 DEVMETHOD(pci_find_cap, pci_find_cap_method), 193 DEVMETHOD(pci_find_next_cap, pci_find_next_cap_method), 194 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 195 DEVMETHOD(pci_find_next_extcap, pci_find_next_extcap_method), 196 DEVMETHOD(pci_find_htcap, pci_find_htcap_method), 197 DEVMETHOD(pci_find_next_htcap, pci_find_next_htcap_method), 198 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method), 199 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method), 200 DEVMETHOD(pci_enable_msi, pci_enable_msi_method), 201 DEVMETHOD(pci_enable_msix, pci_enable_msix_method), 202 DEVMETHOD(pci_disable_msi, pci_disable_msi_method), 203 DEVMETHOD(pci_remap_msix, pci_remap_msix_method), 204 DEVMETHOD(pci_release_msi, pci_release_msi_method), 205 DEVMETHOD(pci_msi_count, pci_msi_count_method), 206 DEVMETHOD(pci_msix_count, pci_msix_count_method), 207 DEVMETHOD(pci_msix_pba_bar, pci_msix_pba_bar_method), 208 DEVMETHOD(pci_msix_table_bar, pci_msix_table_bar_method), 209 DEVMETHOD(pci_get_id, pci_get_id_method), 210 DEVMETHOD(pci_alloc_devinfo, pci_alloc_devinfo_method), 211 DEVMETHOD(pci_child_added, pci_child_added_method), 212 #ifdef PCI_IOV 213 DEVMETHOD(pci_iov_attach, pci_iov_attach_method), 214 DEVMETHOD(pci_iov_detach, pci_iov_detach_method), 215 DEVMETHOD(pci_create_iov_child, pci_create_iov_child_method), 216 #endif 217 218 DEVMETHOD_END 219 }; 220 221 DEFINE_CLASS_0(pci, pci_driver, pci_methods, sizeof(struct pci_softc)); 222 223 static devclass_t pci_devclass; 224 EARLY_DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL, 225 BUS_PASS_BUS); 226 MODULE_VERSION(pci, 1); 227 228 static char *pci_vendordata; 229 static size_t pci_vendordata_size; 230 231 struct pci_quirk { 232 uint32_t devid; /* Vendor/device of the card */ 233 int type; 234 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 235 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */ 236 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */ 237 #define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */ 238 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */ 239 #define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */ 240 #define PCI_QUIRK_REALLOC_BAR 7 /* Can't allocate memory at the default address */ 241 int arg1; 242 int arg2; 243 }; 244 245 static const struct pci_quirk pci_quirks[] = { 246 /* The Intel 82371AB and 82443MX have a map register at offset 0x90. */ 247 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 248 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 249 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 250 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 251 252 /* 253 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge 254 * or the CMIC-SL (AKA ServerWorks GC_LE). 255 */ 256 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 257 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 258 259 /* 260 * MSI doesn't work on earlier Intel chipsets including 261 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855. 262 */ 263 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 264 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 265 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 266 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 267 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 268 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 269 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 270 271 /* 272 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX 273 * bridge. 274 */ 275 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 276 277 /* 278 * Some virtualization environments emulate an older chipset 279 * but support MSI just fine. QEMU uses the Intel 82440. 280 */ 281 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 }, 282 283 /* 284 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus 285 * controller depending on SoftPciRst register (PM_IO 0x55 [7]). 286 * It prevents us from attaching hpet(4) when the bit is unset. 287 * Note this quirk only affects SB600 revision A13 and earlier. 288 * For SB600 A21 and later, firmware must set the bit to hide it. 289 * For SB700 and later, it is unused and hardcoded to zero. 290 */ 291 { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 }, 292 293 /* 294 * Atheros AR8161/AR8162/E2200/E2400/E2500 Ethernet controllers have 295 * a bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit 296 * of the command register is set. 297 */ 298 { 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 299 { 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 300 { 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 301 { 0xE0B11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 302 { 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 303 304 /* 305 * Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't 306 * issue MSI interrupts with PCIM_CMD_INTxDIS set either. 307 */ 308 { 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714 */ 309 { 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714S */ 310 { 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780 */ 311 { 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780S */ 312 { 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715 */ 313 { 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715S */ 314 315 /* 316 * HPE Gen 10 VGA has a memory range that can't be allocated in the 317 * expected place. 318 */ 319 { 0x98741002, PCI_QUIRK_REALLOC_BAR, 0, 0 }, 320 321 { 0 } 322 }; 323 324 /* map register information */ 325 #define PCI_MAPMEM 0x01 /* memory map */ 326 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 327 #define PCI_MAPPORT 0x04 /* port map */ 328 329 struct devlist pci_devq; 330 uint32_t pci_generation; 331 uint32_t pci_numdevs = 0; 332 static int pcie_chipset, pcix_chipset; 333 334 /* sysctl vars */ 335 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 336 337 static int pci_enable_io_modes = 1; 338 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RWTUN, 339 &pci_enable_io_modes, 1, 340 "Enable I/O and memory bits in the config register. Some BIOSes do not" 341 " enable these bits correctly. We'd like to do this all the time, but" 342 " there are some peripherals that this causes problems with."); 343 344 static int pci_do_realloc_bars = 1; 345 SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RWTUN, 346 &pci_do_realloc_bars, 0, 347 "Attempt to allocate a new range for any BARs whose original " 348 "firmware-assigned ranges fail to allocate during the initial device scan."); 349 350 static int pci_do_power_nodriver = 0; 351 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RWTUN, 352 &pci_do_power_nodriver, 0, 353 "Place a function into D3 state when no driver attaches to it. 0 means" 354 " disable. 1 means conservatively place devices into D3 state. 2 means" 355 " aggressively place devices into D3 state. 3 means put absolutely" 356 " everything in D3 state."); 357 358 int pci_do_power_resume = 1; 359 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RWTUN, 360 &pci_do_power_resume, 1, 361 "Transition from D3 -> D0 on resume."); 362 363 int pci_do_power_suspend = 1; 364 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RWTUN, 365 &pci_do_power_suspend, 1, 366 "Transition from D0 -> D3 on suspend."); 367 368 static int pci_do_msi = 1; 369 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RWTUN, &pci_do_msi, 1, 370 "Enable support for MSI interrupts"); 371 372 static int pci_do_msix = 1; 373 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RWTUN, &pci_do_msix, 1, 374 "Enable support for MSI-X interrupts"); 375 376 static int pci_msix_rewrite_table = 0; 377 SYSCTL_INT(_hw_pci, OID_AUTO, msix_rewrite_table, CTLFLAG_RWTUN, 378 &pci_msix_rewrite_table, 0, 379 "Rewrite entire MSI-X table when updating MSI-X entries"); 380 381 static int pci_honor_msi_blacklist = 1; 382 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RDTUN, 383 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X"); 384 385 #if defined(__i386__) || defined(__amd64__) 386 static int pci_usb_takeover = 1; 387 #else 388 static int pci_usb_takeover = 0; 389 #endif 390 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN, 391 &pci_usb_takeover, 1, 392 "Enable early takeover of USB controllers. Disable this if you depend on" 393 " BIOS emulation of USB devices, that is you use USB devices (like" 394 " keyboard or mouse) but do not load USB drivers"); 395 396 static int pci_clear_bars; 397 SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0, 398 "Ignore firmware-assigned resources for BARs."); 399 400 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 401 static int pci_clear_buses; 402 SYSCTL_INT(_hw_pci, OID_AUTO, clear_buses, CTLFLAG_RDTUN, &pci_clear_buses, 0, 403 "Ignore firmware-assigned bus numbers."); 404 #endif 405 406 static int pci_enable_ari = 1; 407 SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari, 408 0, "Enable support for PCIe Alternative RID Interpretation"); 409 410 static int pci_clear_aer_on_attach = 0; 411 SYSCTL_INT(_hw_pci, OID_AUTO, clear_aer_on_attach, CTLFLAG_RWTUN, 412 &pci_clear_aer_on_attach, 0, 413 "Clear port and device AER state on driver attach"); 414 415 static int 416 pci_has_quirk(uint32_t devid, int quirk) 417 { 418 const struct pci_quirk *q; 419 420 for (q = &pci_quirks[0]; q->devid; q++) { 421 if (q->devid == devid && q->type == quirk) 422 return (1); 423 } 424 return (0); 425 } 426 427 /* Find a device_t by bus/slot/function in domain 0 */ 428 429 device_t 430 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 431 { 432 433 return (pci_find_dbsf(0, bus, slot, func)); 434 } 435 436 /* Find a device_t by domain/bus/slot/function */ 437 438 device_t 439 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func) 440 { 441 struct pci_devinfo *dinfo = NULL; 442 443 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 444 if ((dinfo->cfg.domain == domain) && 445 (dinfo->cfg.bus == bus) && 446 (dinfo->cfg.slot == slot) && 447 (dinfo->cfg.func == func)) { 448 break; 449 } 450 } 451 452 return (dinfo != NULL ? dinfo->cfg.dev : NULL); 453 } 454 455 /* Find a device_t by vendor/device ID */ 456 457 device_t 458 pci_find_device(uint16_t vendor, uint16_t device) 459 { 460 struct pci_devinfo *dinfo; 461 462 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 463 if ((dinfo->cfg.vendor == vendor) && 464 (dinfo->cfg.device == device)) { 465 return (dinfo->cfg.dev); 466 } 467 } 468 469 return (NULL); 470 } 471 472 device_t 473 pci_find_class(uint8_t class, uint8_t subclass) 474 { 475 struct pci_devinfo *dinfo; 476 477 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 478 if (dinfo->cfg.baseclass == class && 479 dinfo->cfg.subclass == subclass) { 480 return (dinfo->cfg.dev); 481 } 482 } 483 484 return (NULL); 485 } 486 487 static int 488 pci_printf(pcicfgregs *cfg, const char *fmt, ...) 489 { 490 va_list ap; 491 int retval; 492 493 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot, 494 cfg->func); 495 va_start(ap, fmt); 496 retval += vprintf(fmt, ap); 497 va_end(ap); 498 return (retval); 499 } 500 501 /* return base address of memory or port map */ 502 503 static pci_addr_t 504 pci_mapbase(uint64_t mapreg) 505 { 506 507 if (PCI_BAR_MEM(mapreg)) 508 return (mapreg & PCIM_BAR_MEM_BASE); 509 else 510 return (mapreg & PCIM_BAR_IO_BASE); 511 } 512 513 /* return map type of memory or port map */ 514 515 static const char * 516 pci_maptype(uint64_t mapreg) 517 { 518 519 if (PCI_BAR_IO(mapreg)) 520 return ("I/O Port"); 521 if (mapreg & PCIM_BAR_MEM_PREFETCH) 522 return ("Prefetchable Memory"); 523 return ("Memory"); 524 } 525 526 /* return log2 of map size decoded for memory or port map */ 527 528 int 529 pci_mapsize(uint64_t testval) 530 { 531 int ln2size; 532 533 testval = pci_mapbase(testval); 534 ln2size = 0; 535 if (testval != 0) { 536 while ((testval & 1) == 0) 537 { 538 ln2size++; 539 testval >>= 1; 540 } 541 } 542 return (ln2size); 543 } 544 545 /* return base address of device ROM */ 546 547 static pci_addr_t 548 pci_rombase(uint64_t mapreg) 549 { 550 551 return (mapreg & PCIM_BIOS_ADDR_MASK); 552 } 553 554 /* return log2 of map size decided for device ROM */ 555 556 static int 557 pci_romsize(uint64_t testval) 558 { 559 int ln2size; 560 561 testval = pci_rombase(testval); 562 ln2size = 0; 563 if (testval != 0) { 564 while ((testval & 1) == 0) 565 { 566 ln2size++; 567 testval >>= 1; 568 } 569 } 570 return (ln2size); 571 } 572 573 /* return log2 of address range supported by map register */ 574 575 static int 576 pci_maprange(uint64_t mapreg) 577 { 578 int ln2range = 0; 579 580 if (PCI_BAR_IO(mapreg)) 581 ln2range = 32; 582 else 583 switch (mapreg & PCIM_BAR_MEM_TYPE) { 584 case PCIM_BAR_MEM_32: 585 ln2range = 32; 586 break; 587 case PCIM_BAR_MEM_1MB: 588 ln2range = 20; 589 break; 590 case PCIM_BAR_MEM_64: 591 ln2range = 64; 592 break; 593 } 594 return (ln2range); 595 } 596 597 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 598 599 static void 600 pci_fixancient(pcicfgregs *cfg) 601 { 602 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) 603 return; 604 605 /* PCI to PCI bridges use header type 1 */ 606 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 607 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE; 608 } 609 610 /* extract header type specific config data */ 611 612 static void 613 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 614 { 615 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 616 switch (cfg->hdrtype & PCIM_HDRTYPE) { 617 case PCIM_HDRTYPE_NORMAL: 618 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 619 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 620 cfg->mingnt = REG(PCIR_MINGNT, 1); 621 cfg->maxlat = REG(PCIR_MAXLAT, 1); 622 cfg->nummaps = PCI_MAXMAPS_0; 623 break; 624 case PCIM_HDRTYPE_BRIDGE: 625 cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1); 626 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1); 627 cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1); 628 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1); 629 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2); 630 cfg->nummaps = PCI_MAXMAPS_1; 631 break; 632 case PCIM_HDRTYPE_CARDBUS: 633 cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1); 634 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1); 635 cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1); 636 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1); 637 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2); 638 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 639 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 640 cfg->nummaps = PCI_MAXMAPS_2; 641 break; 642 } 643 #undef REG 644 } 645 646 /* read configuration header into pcicfgregs structure */ 647 struct pci_devinfo * 648 pci_read_device(device_t pcib, device_t bus, int d, int b, int s, int f) 649 { 650 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 651 uint16_t vid, did; 652 653 vid = REG(PCIR_VENDOR, 2); 654 did = REG(PCIR_DEVICE, 2); 655 if (vid != 0xffff) 656 return (pci_fill_devinfo(pcib, bus, d, b, s, f, vid, did)); 657 658 return (NULL); 659 } 660 661 struct pci_devinfo * 662 pci_alloc_devinfo_method(device_t dev) 663 { 664 665 return (malloc(sizeof(struct pci_devinfo), M_DEVBUF, 666 M_WAITOK | M_ZERO)); 667 } 668 669 static struct pci_devinfo * 670 pci_fill_devinfo(device_t pcib, device_t bus, int d, int b, int s, int f, 671 uint16_t vid, uint16_t did) 672 { 673 struct pci_devinfo *devlist_entry; 674 pcicfgregs *cfg; 675 676 devlist_entry = PCI_ALLOC_DEVINFO(bus); 677 678 cfg = &devlist_entry->cfg; 679 680 cfg->domain = d; 681 cfg->bus = b; 682 cfg->slot = s; 683 cfg->func = f; 684 cfg->vendor = vid; 685 cfg->device = did; 686 cfg->cmdreg = REG(PCIR_COMMAND, 2); 687 cfg->statreg = REG(PCIR_STATUS, 2); 688 cfg->baseclass = REG(PCIR_CLASS, 1); 689 cfg->subclass = REG(PCIR_SUBCLASS, 1); 690 cfg->progif = REG(PCIR_PROGIF, 1); 691 cfg->revid = REG(PCIR_REVID, 1); 692 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 693 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 694 cfg->lattimer = REG(PCIR_LATTIMER, 1); 695 cfg->intpin = REG(PCIR_INTPIN, 1); 696 cfg->intline = REG(PCIR_INTLINE, 1); 697 698 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 699 cfg->hdrtype &= ~PCIM_MFDEV; 700 STAILQ_INIT(&cfg->maps); 701 702 cfg->iov = NULL; 703 704 pci_fixancient(cfg); 705 pci_hdrtypedata(pcib, b, s, f, cfg); 706 707 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 708 pci_read_cap(pcib, cfg); 709 710 STAILQ_INSERT_TAIL(&pci_devq, devlist_entry, pci_links); 711 712 devlist_entry->conf.pc_sel.pc_domain = cfg->domain; 713 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 714 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 715 devlist_entry->conf.pc_sel.pc_func = cfg->func; 716 devlist_entry->conf.pc_hdr = cfg->hdrtype; 717 718 devlist_entry->conf.pc_subvendor = cfg->subvendor; 719 devlist_entry->conf.pc_subdevice = cfg->subdevice; 720 devlist_entry->conf.pc_vendor = cfg->vendor; 721 devlist_entry->conf.pc_device = cfg->device; 722 723 devlist_entry->conf.pc_class = cfg->baseclass; 724 devlist_entry->conf.pc_subclass = cfg->subclass; 725 devlist_entry->conf.pc_progif = cfg->progif; 726 devlist_entry->conf.pc_revid = cfg->revid; 727 728 pci_numdevs++; 729 pci_generation++; 730 731 return (devlist_entry); 732 } 733 #undef REG 734 735 static void 736 pci_ea_fill_info(device_t pcib, pcicfgregs *cfg) 737 { 738 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \ 739 cfg->ea.ea_location + (n), w) 740 int num_ent; 741 int ptr; 742 int a, b; 743 uint32_t val; 744 int ent_size; 745 uint32_t dw[4]; 746 uint64_t base, max_offset; 747 struct pci_ea_entry *eae; 748 749 if (cfg->ea.ea_location == 0) 750 return; 751 752 STAILQ_INIT(&cfg->ea.ea_entries); 753 754 /* Determine the number of entries */ 755 num_ent = REG(PCIR_EA_NUM_ENT, 2); 756 num_ent &= PCIM_EA_NUM_ENT_MASK; 757 758 /* Find the first entry to care of */ 759 ptr = PCIR_EA_FIRST_ENT; 760 761 /* Skip DWORD 2 for type 1 functions */ 762 if ((cfg->hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) 763 ptr += 4; 764 765 for (a = 0; a < num_ent; a++) { 766 767 eae = malloc(sizeof(*eae), M_DEVBUF, M_WAITOK | M_ZERO); 768 eae->eae_cfg_offset = cfg->ea.ea_location + ptr; 769 770 /* Read a number of dwords in the entry */ 771 val = REG(ptr, 4); 772 ptr += 4; 773 ent_size = (val & PCIM_EA_ES); 774 775 for (b = 0; b < ent_size; b++) { 776 dw[b] = REG(ptr, 4); 777 ptr += 4; 778 } 779 780 eae->eae_flags = val; 781 eae->eae_bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; 782 783 base = dw[0] & PCIM_EA_FIELD_MASK; 784 max_offset = dw[1] | ~PCIM_EA_FIELD_MASK; 785 b = 2; 786 if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) { 787 base |= (uint64_t)dw[b] << 32UL; 788 b++; 789 } 790 if (((dw[1] & PCIM_EA_IS_64) != 0) 791 && (b < ent_size)) { 792 max_offset |= (uint64_t)dw[b] << 32UL; 793 b++; 794 } 795 796 eae->eae_base = base; 797 eae->eae_max_offset = max_offset; 798 799 STAILQ_INSERT_TAIL(&cfg->ea.ea_entries, eae, eae_link); 800 801 if (bootverbose) { 802 printf("PCI(EA) dev %04x:%04x, bei %d, flags #%x, base #%jx, max_offset #%jx\n", 803 cfg->vendor, cfg->device, eae->eae_bei, eae->eae_flags, 804 (uintmax_t)eae->eae_base, (uintmax_t)eae->eae_max_offset); 805 } 806 } 807 } 808 #undef REG 809 810 static void 811 pci_read_cap(device_t pcib, pcicfgregs *cfg) 812 { 813 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 814 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 815 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 816 uint64_t addr; 817 #endif 818 uint32_t val; 819 int ptr, nextptr, ptrptr; 820 821 switch (cfg->hdrtype & PCIM_HDRTYPE) { 822 case PCIM_HDRTYPE_NORMAL: 823 case PCIM_HDRTYPE_BRIDGE: 824 ptrptr = PCIR_CAP_PTR; 825 break; 826 case PCIM_HDRTYPE_CARDBUS: 827 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 828 break; 829 default: 830 return; /* no extended capabilities support */ 831 } 832 nextptr = REG(ptrptr, 1); /* sanity check? */ 833 834 /* 835 * Read capability entries. 836 */ 837 while (nextptr != 0) { 838 /* Sanity check */ 839 if (nextptr > 255) { 840 printf("illegal PCI extended capability offset %d\n", 841 nextptr); 842 return; 843 } 844 /* Find the next entry */ 845 ptr = nextptr; 846 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 847 848 /* Process this entry */ 849 switch (REG(ptr + PCICAP_ID, 1)) { 850 case PCIY_PMG: /* PCI power management */ 851 if (cfg->pp.pp_cap == 0) { 852 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 853 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 854 cfg->pp.pp_bse = ptr + PCIR_POWER_BSE; 855 if ((nextptr - ptr) > PCIR_POWER_DATA) 856 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 857 } 858 break; 859 case PCIY_HT: /* HyperTransport */ 860 /* Determine HT-specific capability type. */ 861 val = REG(ptr + PCIR_HT_COMMAND, 2); 862 863 if ((val & 0xe000) == PCIM_HTCAP_SLAVE) 864 cfg->ht.ht_slave = ptr; 865 866 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 867 switch (val & PCIM_HTCMD_CAP_MASK) { 868 case PCIM_HTCAP_MSI_MAPPING: 869 if (!(val & PCIM_HTCMD_MSI_FIXED)) { 870 /* Sanity check the mapping window. */ 871 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 872 4); 873 addr <<= 32; 874 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 875 4); 876 if (addr != MSI_INTEL_ADDR_BASE) 877 device_printf(pcib, 878 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n", 879 cfg->domain, cfg->bus, 880 cfg->slot, cfg->func, 881 (long long)addr); 882 } else 883 addr = MSI_INTEL_ADDR_BASE; 884 885 cfg->ht.ht_msimap = ptr; 886 cfg->ht.ht_msictrl = val; 887 cfg->ht.ht_msiaddr = addr; 888 break; 889 } 890 #endif 891 break; 892 case PCIY_MSI: /* PCI MSI */ 893 cfg->msi.msi_location = ptr; 894 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 895 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 896 PCIM_MSICTRL_MMC_MASK)>>1); 897 break; 898 case PCIY_MSIX: /* PCI MSI-X */ 899 cfg->msix.msix_location = ptr; 900 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); 901 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl & 902 PCIM_MSIXCTRL_TABLE_SIZE) + 1; 903 val = REG(ptr + PCIR_MSIX_TABLE, 4); 904 cfg->msix.msix_table_bar = PCIR_BAR(val & 905 PCIM_MSIX_BIR_MASK); 906 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; 907 val = REG(ptr + PCIR_MSIX_PBA, 4); 908 cfg->msix.msix_pba_bar = PCIR_BAR(val & 909 PCIM_MSIX_BIR_MASK); 910 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; 911 break; 912 case PCIY_VPD: /* PCI Vital Product Data */ 913 cfg->vpd.vpd_reg = ptr; 914 break; 915 case PCIY_SUBVENDOR: 916 /* Should always be true. */ 917 if ((cfg->hdrtype & PCIM_HDRTYPE) == 918 PCIM_HDRTYPE_BRIDGE) { 919 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4); 920 cfg->subvendor = val & 0xffff; 921 cfg->subdevice = val >> 16; 922 } 923 break; 924 case PCIY_PCIX: /* PCI-X */ 925 /* 926 * Assume we have a PCI-X chipset if we have 927 * at least one PCI-PCI bridge with a PCI-X 928 * capability. Note that some systems with 929 * PCI-express or HT chipsets might match on 930 * this check as well. 931 */ 932 if ((cfg->hdrtype & PCIM_HDRTYPE) == 933 PCIM_HDRTYPE_BRIDGE) 934 pcix_chipset = 1; 935 cfg->pcix.pcix_location = ptr; 936 break; 937 case PCIY_EXPRESS: /* PCI-express */ 938 /* 939 * Assume we have a PCI-express chipset if we have 940 * at least one PCI-express device. 941 */ 942 pcie_chipset = 1; 943 cfg->pcie.pcie_location = ptr; 944 val = REG(ptr + PCIER_FLAGS, 2); 945 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE; 946 break; 947 case PCIY_EA: /* Enhanced Allocation */ 948 cfg->ea.ea_location = ptr; 949 pci_ea_fill_info(pcib, cfg); 950 break; 951 default: 952 break; 953 } 954 } 955 956 #if defined(__powerpc__) 957 /* 958 * Enable the MSI mapping window for all HyperTransport 959 * slaves. PCI-PCI bridges have their windows enabled via 960 * PCIB_MAP_MSI(). 961 */ 962 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 && 963 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) { 964 device_printf(pcib, 965 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n", 966 cfg->domain, cfg->bus, cfg->slot, cfg->func); 967 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 968 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl, 969 2); 970 } 971 #endif 972 /* REG and WREG use carry through to next functions */ 973 } 974 975 /* 976 * PCI Vital Product Data 977 */ 978 979 #define PCI_VPD_TIMEOUT 1000000 980 981 static int 982 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data) 983 { 984 int count = PCI_VPD_TIMEOUT; 985 986 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 987 988 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2); 989 990 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) { 991 if (--count < 0) 992 return (ENXIO); 993 DELAY(1); /* limit looping */ 994 } 995 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4)); 996 997 return (0); 998 } 999 1000 #if 0 1001 static int 1002 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 1003 { 1004 int count = PCI_VPD_TIMEOUT; 1005 1006 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 1007 1008 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4); 1009 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2); 1010 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) { 1011 if (--count < 0) 1012 return (ENXIO); 1013 DELAY(1); /* limit looping */ 1014 } 1015 1016 return (0); 1017 } 1018 #endif 1019 1020 #undef PCI_VPD_TIMEOUT 1021 1022 struct vpd_readstate { 1023 device_t pcib; 1024 pcicfgregs *cfg; 1025 uint32_t val; 1026 int bytesinval; 1027 int off; 1028 uint8_t cksum; 1029 }; 1030 1031 static int 1032 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data) 1033 { 1034 uint32_t reg; 1035 uint8_t byte; 1036 1037 if (vrs->bytesinval == 0) { 1038 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®)) 1039 return (ENXIO); 1040 vrs->val = le32toh(reg); 1041 vrs->off += 4; 1042 byte = vrs->val & 0xff; 1043 vrs->bytesinval = 3; 1044 } else { 1045 vrs->val = vrs->val >> 8; 1046 byte = vrs->val & 0xff; 1047 vrs->bytesinval--; 1048 } 1049 1050 vrs->cksum += byte; 1051 *data = byte; 1052 return (0); 1053 } 1054 1055 static void 1056 pci_read_vpd(device_t pcib, pcicfgregs *cfg) 1057 { 1058 struct vpd_readstate vrs; 1059 int state; 1060 int name; 1061 int remain; 1062 int i; 1063 int alloc, off; /* alloc/off for RO/W arrays */ 1064 int cksumvalid; 1065 int dflen; 1066 uint8_t byte; 1067 uint8_t byte2; 1068 1069 /* init vpd reader */ 1070 vrs.bytesinval = 0; 1071 vrs.off = 0; 1072 vrs.pcib = pcib; 1073 vrs.cfg = cfg; 1074 vrs.cksum = 0; 1075 1076 state = 0; 1077 name = remain = i = 0; /* shut up stupid gcc */ 1078 alloc = off = 0; /* shut up stupid gcc */ 1079 dflen = 0; /* shut up stupid gcc */ 1080 cksumvalid = -1; 1081 while (state >= 0) { 1082 if (vpd_nextbyte(&vrs, &byte)) { 1083 state = -2; 1084 break; 1085 } 1086 #if 0 1087 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \ 1088 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val, 1089 vrs.off, vrs.bytesinval, byte, state, remain, name, i); 1090 #endif 1091 switch (state) { 1092 case 0: /* item name */ 1093 if (byte & 0x80) { 1094 if (vpd_nextbyte(&vrs, &byte2)) { 1095 state = -2; 1096 break; 1097 } 1098 remain = byte2; 1099 if (vpd_nextbyte(&vrs, &byte2)) { 1100 state = -2; 1101 break; 1102 } 1103 remain |= byte2 << 8; 1104 if (remain > (0x7f*4 - vrs.off)) { 1105 state = -1; 1106 pci_printf(cfg, 1107 "invalid VPD data, remain %#x\n", 1108 remain); 1109 } 1110 name = byte & 0x7f; 1111 } else { 1112 remain = byte & 0x7; 1113 name = (byte >> 3) & 0xf; 1114 } 1115 switch (name) { 1116 case 0x2: /* String */ 1117 cfg->vpd.vpd_ident = malloc(remain + 1, 1118 M_DEVBUF, M_WAITOK); 1119 i = 0; 1120 state = 1; 1121 break; 1122 case 0xf: /* End */ 1123 state = -1; 1124 break; 1125 case 0x10: /* VPD-R */ 1126 alloc = 8; 1127 off = 0; 1128 cfg->vpd.vpd_ros = malloc(alloc * 1129 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF, 1130 M_WAITOK | M_ZERO); 1131 state = 2; 1132 break; 1133 case 0x11: /* VPD-W */ 1134 alloc = 8; 1135 off = 0; 1136 cfg->vpd.vpd_w = malloc(alloc * 1137 sizeof(*cfg->vpd.vpd_w), M_DEVBUF, 1138 M_WAITOK | M_ZERO); 1139 state = 5; 1140 break; 1141 default: /* Invalid data, abort */ 1142 state = -1; 1143 break; 1144 } 1145 break; 1146 1147 case 1: /* Identifier String */ 1148 cfg->vpd.vpd_ident[i++] = byte; 1149 remain--; 1150 if (remain == 0) { 1151 cfg->vpd.vpd_ident[i] = '\0'; 1152 state = 0; 1153 } 1154 break; 1155 1156 case 2: /* VPD-R Keyword Header */ 1157 if (off == alloc) { 1158 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 1159 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros), 1160 M_DEVBUF, M_WAITOK | M_ZERO); 1161 } 1162 cfg->vpd.vpd_ros[off].keyword[0] = byte; 1163 if (vpd_nextbyte(&vrs, &byte2)) { 1164 state = -2; 1165 break; 1166 } 1167 cfg->vpd.vpd_ros[off].keyword[1] = byte2; 1168 if (vpd_nextbyte(&vrs, &byte2)) { 1169 state = -2; 1170 break; 1171 } 1172 cfg->vpd.vpd_ros[off].len = dflen = byte2; 1173 if (dflen == 0 && 1174 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV", 1175 2) == 0) { 1176 /* 1177 * if this happens, we can't trust the rest 1178 * of the VPD. 1179 */ 1180 pci_printf(cfg, "bad keyword length: %d\n", 1181 dflen); 1182 cksumvalid = 0; 1183 state = -1; 1184 break; 1185 } else if (dflen == 0) { 1186 cfg->vpd.vpd_ros[off].value = malloc(1 * 1187 sizeof(*cfg->vpd.vpd_ros[off].value), 1188 M_DEVBUF, M_WAITOK); 1189 cfg->vpd.vpd_ros[off].value[0] = '\x00'; 1190 } else 1191 cfg->vpd.vpd_ros[off].value = malloc( 1192 (dflen + 1) * 1193 sizeof(*cfg->vpd.vpd_ros[off].value), 1194 M_DEVBUF, M_WAITOK); 1195 remain -= 3; 1196 i = 0; 1197 /* keep in sync w/ state 3's transistions */ 1198 if (dflen == 0 && remain == 0) 1199 state = 0; 1200 else if (dflen == 0) 1201 state = 2; 1202 else 1203 state = 3; 1204 break; 1205 1206 case 3: /* VPD-R Keyword Value */ 1207 cfg->vpd.vpd_ros[off].value[i++] = byte; 1208 if (strncmp(cfg->vpd.vpd_ros[off].keyword, 1209 "RV", 2) == 0 && cksumvalid == -1) { 1210 if (vrs.cksum == 0) 1211 cksumvalid = 1; 1212 else { 1213 if (bootverbose) 1214 pci_printf(cfg, 1215 "bad VPD cksum, remain %hhu\n", 1216 vrs.cksum); 1217 cksumvalid = 0; 1218 state = -1; 1219 break; 1220 } 1221 } 1222 dflen--; 1223 remain--; 1224 /* keep in sync w/ state 2's transistions */ 1225 if (dflen == 0) 1226 cfg->vpd.vpd_ros[off++].value[i++] = '\0'; 1227 if (dflen == 0 && remain == 0) { 1228 cfg->vpd.vpd_rocnt = off; 1229 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 1230 off * sizeof(*cfg->vpd.vpd_ros), 1231 M_DEVBUF, M_WAITOK | M_ZERO); 1232 state = 0; 1233 } else if (dflen == 0) 1234 state = 2; 1235 break; 1236 1237 case 4: 1238 remain--; 1239 if (remain == 0) 1240 state = 0; 1241 break; 1242 1243 case 5: /* VPD-W Keyword Header */ 1244 if (off == alloc) { 1245 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 1246 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w), 1247 M_DEVBUF, M_WAITOK | M_ZERO); 1248 } 1249 cfg->vpd.vpd_w[off].keyword[0] = byte; 1250 if (vpd_nextbyte(&vrs, &byte2)) { 1251 state = -2; 1252 break; 1253 } 1254 cfg->vpd.vpd_w[off].keyword[1] = byte2; 1255 if (vpd_nextbyte(&vrs, &byte2)) { 1256 state = -2; 1257 break; 1258 } 1259 cfg->vpd.vpd_w[off].len = dflen = byte2; 1260 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval; 1261 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) * 1262 sizeof(*cfg->vpd.vpd_w[off].value), 1263 M_DEVBUF, M_WAITOK); 1264 remain -= 3; 1265 i = 0; 1266 /* keep in sync w/ state 6's transistions */ 1267 if (dflen == 0 && remain == 0) 1268 state = 0; 1269 else if (dflen == 0) 1270 state = 5; 1271 else 1272 state = 6; 1273 break; 1274 1275 case 6: /* VPD-W Keyword Value */ 1276 cfg->vpd.vpd_w[off].value[i++] = byte; 1277 dflen--; 1278 remain--; 1279 /* keep in sync w/ state 5's transistions */ 1280 if (dflen == 0) 1281 cfg->vpd.vpd_w[off++].value[i++] = '\0'; 1282 if (dflen == 0 && remain == 0) { 1283 cfg->vpd.vpd_wcnt = off; 1284 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 1285 off * sizeof(*cfg->vpd.vpd_w), 1286 M_DEVBUF, M_WAITOK | M_ZERO); 1287 state = 0; 1288 } else if (dflen == 0) 1289 state = 5; 1290 break; 1291 1292 default: 1293 pci_printf(cfg, "invalid state: %d\n", state); 1294 state = -1; 1295 break; 1296 } 1297 } 1298 1299 if (cksumvalid == 0 || state < -1) { 1300 /* read-only data bad, clean up */ 1301 if (cfg->vpd.vpd_ros != NULL) { 1302 for (off = 0; cfg->vpd.vpd_ros[off].value; off++) 1303 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF); 1304 free(cfg->vpd.vpd_ros, M_DEVBUF); 1305 cfg->vpd.vpd_ros = NULL; 1306 } 1307 } 1308 if (state < -1) { 1309 /* I/O error, clean up */ 1310 pci_printf(cfg, "failed to read VPD data.\n"); 1311 if (cfg->vpd.vpd_ident != NULL) { 1312 free(cfg->vpd.vpd_ident, M_DEVBUF); 1313 cfg->vpd.vpd_ident = NULL; 1314 } 1315 if (cfg->vpd.vpd_w != NULL) { 1316 for (off = 0; cfg->vpd.vpd_w[off].value; off++) 1317 free(cfg->vpd.vpd_w[off].value, M_DEVBUF); 1318 free(cfg->vpd.vpd_w, M_DEVBUF); 1319 cfg->vpd.vpd_w = NULL; 1320 } 1321 } 1322 cfg->vpd.vpd_cached = 1; 1323 #undef REG 1324 #undef WREG 1325 } 1326 1327 int 1328 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 1329 { 1330 struct pci_devinfo *dinfo = device_get_ivars(child); 1331 pcicfgregs *cfg = &dinfo->cfg; 1332 1333 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1334 pci_read_vpd(device_get_parent(dev), cfg); 1335 1336 *identptr = cfg->vpd.vpd_ident; 1337 1338 if (*identptr == NULL) 1339 return (ENXIO); 1340 1341 return (0); 1342 } 1343 1344 int 1345 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 1346 const char **vptr) 1347 { 1348 struct pci_devinfo *dinfo = device_get_ivars(child); 1349 pcicfgregs *cfg = &dinfo->cfg; 1350 int i; 1351 1352 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1353 pci_read_vpd(device_get_parent(dev), cfg); 1354 1355 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 1356 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 1357 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) { 1358 *vptr = cfg->vpd.vpd_ros[i].value; 1359 return (0); 1360 } 1361 1362 *vptr = NULL; 1363 return (ENXIO); 1364 } 1365 1366 struct pcicfg_vpd * 1367 pci_fetch_vpd_list(device_t dev) 1368 { 1369 struct pci_devinfo *dinfo = device_get_ivars(dev); 1370 pcicfgregs *cfg = &dinfo->cfg; 1371 1372 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1373 pci_read_vpd(device_get_parent(device_get_parent(dev)), cfg); 1374 return (&cfg->vpd); 1375 } 1376 1377 /* 1378 * Find the requested HyperTransport capability and return the offset 1379 * in configuration space via the pointer provided. The function 1380 * returns 0 on success and an error code otherwise. 1381 */ 1382 int 1383 pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg) 1384 { 1385 int ptr, error; 1386 uint16_t val; 1387 1388 error = pci_find_cap(child, PCIY_HT, &ptr); 1389 if (error) 1390 return (error); 1391 1392 /* 1393 * Traverse the capabilities list checking each HT capability 1394 * to see if it matches the requested HT capability. 1395 */ 1396 for (;;) { 1397 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1398 if (capability == PCIM_HTCAP_SLAVE || 1399 capability == PCIM_HTCAP_HOST) 1400 val &= 0xe000; 1401 else 1402 val &= PCIM_HTCMD_CAP_MASK; 1403 if (val == capability) { 1404 if (capreg != NULL) 1405 *capreg = ptr; 1406 return (0); 1407 } 1408 1409 /* Skip to the next HT capability. */ 1410 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1411 break; 1412 } 1413 1414 return (ENOENT); 1415 } 1416 1417 /* 1418 * Find the next requested HyperTransport capability after start and return 1419 * the offset in configuration space via the pointer provided. The function 1420 * returns 0 on success and an error code otherwise. 1421 */ 1422 int 1423 pci_find_next_htcap_method(device_t dev, device_t child, int capability, 1424 int start, int *capreg) 1425 { 1426 int ptr; 1427 uint16_t val; 1428 1429 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == PCIY_HT, 1430 ("start capability is not HyperTransport capability")); 1431 ptr = start; 1432 1433 /* 1434 * Traverse the capabilities list checking each HT capability 1435 * to see if it matches the requested HT capability. 1436 */ 1437 for (;;) { 1438 /* Skip to the next HT capability. */ 1439 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1440 break; 1441 1442 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1443 if (capability == PCIM_HTCAP_SLAVE || 1444 capability == PCIM_HTCAP_HOST) 1445 val &= 0xe000; 1446 else 1447 val &= PCIM_HTCMD_CAP_MASK; 1448 if (val == capability) { 1449 if (capreg != NULL) 1450 *capreg = ptr; 1451 return (0); 1452 } 1453 } 1454 1455 return (ENOENT); 1456 } 1457 1458 /* 1459 * Find the requested capability and return the offset in 1460 * configuration space via the pointer provided. The function returns 1461 * 0 on success and an error code otherwise. 1462 */ 1463 int 1464 pci_find_cap_method(device_t dev, device_t child, int capability, 1465 int *capreg) 1466 { 1467 struct pci_devinfo *dinfo = device_get_ivars(child); 1468 pcicfgregs *cfg = &dinfo->cfg; 1469 uint32_t status; 1470 uint8_t ptr; 1471 1472 /* 1473 * Check the CAP_LIST bit of the PCI status register first. 1474 */ 1475 status = pci_read_config(child, PCIR_STATUS, 2); 1476 if (!(status & PCIM_STATUS_CAPPRESENT)) 1477 return (ENXIO); 1478 1479 /* 1480 * Determine the start pointer of the capabilities list. 1481 */ 1482 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1483 case PCIM_HDRTYPE_NORMAL: 1484 case PCIM_HDRTYPE_BRIDGE: 1485 ptr = PCIR_CAP_PTR; 1486 break; 1487 case PCIM_HDRTYPE_CARDBUS: 1488 ptr = PCIR_CAP_PTR_2; 1489 break; 1490 default: 1491 /* XXX: panic? */ 1492 return (ENXIO); /* no extended capabilities support */ 1493 } 1494 ptr = pci_read_config(child, ptr, 1); 1495 1496 /* 1497 * Traverse the capabilities list. 1498 */ 1499 while (ptr != 0) { 1500 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1501 if (capreg != NULL) 1502 *capreg = ptr; 1503 return (0); 1504 } 1505 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1506 } 1507 1508 return (ENOENT); 1509 } 1510 1511 /* 1512 * Find the next requested capability after start and return the offset in 1513 * configuration space via the pointer provided. The function returns 1514 * 0 on success and an error code otherwise. 1515 */ 1516 int 1517 pci_find_next_cap_method(device_t dev, device_t child, int capability, 1518 int start, int *capreg) 1519 { 1520 uint8_t ptr; 1521 1522 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == capability, 1523 ("start capability is not expected capability")); 1524 1525 ptr = pci_read_config(child, start + PCICAP_NEXTPTR, 1); 1526 while (ptr != 0) { 1527 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1528 if (capreg != NULL) 1529 *capreg = ptr; 1530 return (0); 1531 } 1532 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1533 } 1534 1535 return (ENOENT); 1536 } 1537 1538 /* 1539 * Find the requested extended capability and return the offset in 1540 * configuration space via the pointer provided. The function returns 1541 * 0 on success and an error code otherwise. 1542 */ 1543 int 1544 pci_find_extcap_method(device_t dev, device_t child, int capability, 1545 int *capreg) 1546 { 1547 struct pci_devinfo *dinfo = device_get_ivars(child); 1548 pcicfgregs *cfg = &dinfo->cfg; 1549 uint32_t ecap; 1550 uint16_t ptr; 1551 1552 /* Only supported for PCI-express devices. */ 1553 if (cfg->pcie.pcie_location == 0) 1554 return (ENXIO); 1555 1556 ptr = PCIR_EXTCAP; 1557 ecap = pci_read_config(child, ptr, 4); 1558 if (ecap == 0xffffffff || ecap == 0) 1559 return (ENOENT); 1560 for (;;) { 1561 if (PCI_EXTCAP_ID(ecap) == capability) { 1562 if (capreg != NULL) 1563 *capreg = ptr; 1564 return (0); 1565 } 1566 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1567 if (ptr == 0) 1568 break; 1569 ecap = pci_read_config(child, ptr, 4); 1570 } 1571 1572 return (ENOENT); 1573 } 1574 1575 /* 1576 * Find the next requested extended capability after start and return the 1577 * offset in configuration space via the pointer provided. The function 1578 * returns 0 on success and an error code otherwise. 1579 */ 1580 int 1581 pci_find_next_extcap_method(device_t dev, device_t child, int capability, 1582 int start, int *capreg) 1583 { 1584 struct pci_devinfo *dinfo = device_get_ivars(child); 1585 pcicfgregs *cfg = &dinfo->cfg; 1586 uint32_t ecap; 1587 uint16_t ptr; 1588 1589 /* Only supported for PCI-express devices. */ 1590 if (cfg->pcie.pcie_location == 0) 1591 return (ENXIO); 1592 1593 ecap = pci_read_config(child, start, 4); 1594 KASSERT(PCI_EXTCAP_ID(ecap) == capability, 1595 ("start extended capability is not expected capability")); 1596 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1597 while (ptr != 0) { 1598 ecap = pci_read_config(child, ptr, 4); 1599 if (PCI_EXTCAP_ID(ecap) == capability) { 1600 if (capreg != NULL) 1601 *capreg = ptr; 1602 return (0); 1603 } 1604 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1605 } 1606 1607 return (ENOENT); 1608 } 1609 1610 /* 1611 * Support for MSI-X message interrupts. 1612 */ 1613 static void 1614 pci_write_msix_entry(device_t dev, u_int index, uint64_t address, uint32_t data) 1615 { 1616 struct pci_devinfo *dinfo = device_get_ivars(dev); 1617 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1618 uint32_t offset; 1619 1620 KASSERT(msix->msix_table_len > index, ("bogus index")); 1621 offset = msix->msix_table_offset + index * 16; 1622 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff); 1623 bus_write_4(msix->msix_table_res, offset + 4, address >> 32); 1624 bus_write_4(msix->msix_table_res, offset + 8, data); 1625 } 1626 1627 void 1628 pci_enable_msix_method(device_t dev, device_t child, u_int index, 1629 uint64_t address, uint32_t data) 1630 { 1631 1632 if (pci_msix_rewrite_table) { 1633 struct pci_devinfo *dinfo = device_get_ivars(child); 1634 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1635 1636 /* 1637 * Some VM hosts require MSIX to be disabled in the 1638 * control register before updating the MSIX table 1639 * entries are allowed. It is not enough to only 1640 * disable MSIX while updating a single entry. MSIX 1641 * must be disabled while updating all entries in the 1642 * table. 1643 */ 1644 pci_write_config(child, 1645 msix->msix_location + PCIR_MSIX_CTRL, 1646 msix->msix_ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE, 2); 1647 pci_resume_msix(child); 1648 } else 1649 pci_write_msix_entry(child, index, address, data); 1650 1651 /* Enable MSI -> HT mapping. */ 1652 pci_ht_map_msi(child, address); 1653 } 1654 1655 void 1656 pci_mask_msix(device_t dev, u_int index) 1657 { 1658 struct pci_devinfo *dinfo = device_get_ivars(dev); 1659 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1660 uint32_t offset, val; 1661 1662 KASSERT(msix->msix_msgnum > index, ("bogus index")); 1663 offset = msix->msix_table_offset + index * 16 + 12; 1664 val = bus_read_4(msix->msix_table_res, offset); 1665 val |= PCIM_MSIX_VCTRL_MASK; 1666 1667 /* 1668 * Some devices (e.g. Samsung PM961) do not support reads of this 1669 * register, so always write the new value. 1670 */ 1671 bus_write_4(msix->msix_table_res, offset, val); 1672 } 1673 1674 void 1675 pci_unmask_msix(device_t dev, u_int index) 1676 { 1677 struct pci_devinfo *dinfo = device_get_ivars(dev); 1678 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1679 uint32_t offset, val; 1680 1681 KASSERT(msix->msix_table_len > index, ("bogus index")); 1682 offset = msix->msix_table_offset + index * 16 + 12; 1683 val = bus_read_4(msix->msix_table_res, offset); 1684 val &= ~PCIM_MSIX_VCTRL_MASK; 1685 1686 /* 1687 * Some devices (e.g. Samsung PM961) do not support reads of this 1688 * register, so always write the new value. 1689 */ 1690 bus_write_4(msix->msix_table_res, offset, val); 1691 } 1692 1693 int 1694 pci_pending_msix(device_t dev, u_int index) 1695 { 1696 struct pci_devinfo *dinfo = device_get_ivars(dev); 1697 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1698 uint32_t offset, bit; 1699 1700 KASSERT(msix->msix_table_len > index, ("bogus index")); 1701 offset = msix->msix_pba_offset + (index / 32) * 4; 1702 bit = 1 << index % 32; 1703 return (bus_read_4(msix->msix_pba_res, offset) & bit); 1704 } 1705 1706 /* 1707 * Restore MSI-X registers and table during resume. If MSI-X is 1708 * enabled then walk the virtual table to restore the actual MSI-X 1709 * table. 1710 */ 1711 static void 1712 pci_resume_msix(device_t dev) 1713 { 1714 struct pci_devinfo *dinfo = device_get_ivars(dev); 1715 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1716 struct msix_table_entry *mte; 1717 struct msix_vector *mv; 1718 int i; 1719 1720 if (msix->msix_alloc > 0) { 1721 /* First, mask all vectors. */ 1722 for (i = 0; i < msix->msix_msgnum; i++) 1723 pci_mask_msix(dev, i); 1724 1725 /* Second, program any messages with at least one handler. */ 1726 for (i = 0; i < msix->msix_table_len; i++) { 1727 mte = &msix->msix_table[i]; 1728 if (mte->mte_vector == 0 || mte->mte_handlers == 0) 1729 continue; 1730 mv = &msix->msix_vectors[mte->mte_vector - 1]; 1731 pci_write_msix_entry(dev, i, mv->mv_address, 1732 mv->mv_data); 1733 pci_unmask_msix(dev, i); 1734 } 1735 } 1736 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL, 1737 msix->msix_ctrl, 2); 1738 } 1739 1740 /* 1741 * Attempt to allocate *count MSI-X messages. The actual number allocated is 1742 * returned in *count. After this function returns, each message will be 1743 * available to the driver as SYS_RES_IRQ resources starting at rid 1. 1744 */ 1745 int 1746 pci_alloc_msix_method(device_t dev, device_t child, int *count) 1747 { 1748 struct pci_devinfo *dinfo = device_get_ivars(child); 1749 pcicfgregs *cfg = &dinfo->cfg; 1750 struct resource_list_entry *rle; 1751 int actual, error, i, irq, max; 1752 1753 /* Don't let count == 0 get us into trouble. */ 1754 if (*count == 0) 1755 return (EINVAL); 1756 1757 /* If rid 0 is allocated, then fail. */ 1758 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1759 if (rle != NULL && rle->res != NULL) 1760 return (ENXIO); 1761 1762 /* Already have allocated messages? */ 1763 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 1764 return (ENXIO); 1765 1766 /* If MSI-X is blacklisted for this system, fail. */ 1767 if (pci_msix_blacklisted()) 1768 return (ENXIO); 1769 1770 /* MSI-X capability present? */ 1771 if (cfg->msix.msix_location == 0 || !pci_do_msix) 1772 return (ENODEV); 1773 1774 /* Make sure the appropriate BARs are mapped. */ 1775 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1776 cfg->msix.msix_table_bar); 1777 if (rle == NULL || rle->res == NULL || 1778 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1779 return (ENXIO); 1780 cfg->msix.msix_table_res = rle->res; 1781 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { 1782 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1783 cfg->msix.msix_pba_bar); 1784 if (rle == NULL || rle->res == NULL || 1785 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1786 return (ENXIO); 1787 } 1788 cfg->msix.msix_pba_res = rle->res; 1789 1790 if (bootverbose) 1791 device_printf(child, 1792 "attempting to allocate %d MSI-X vectors (%d supported)\n", 1793 *count, cfg->msix.msix_msgnum); 1794 max = min(*count, cfg->msix.msix_msgnum); 1795 for (i = 0; i < max; i++) { 1796 /* Allocate a message. */ 1797 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq); 1798 if (error) { 1799 if (i == 0) 1800 return (error); 1801 break; 1802 } 1803 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1804 irq, 1); 1805 } 1806 actual = i; 1807 1808 if (bootverbose) { 1809 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); 1810 if (actual == 1) 1811 device_printf(child, "using IRQ %ju for MSI-X\n", 1812 rle->start); 1813 else { 1814 int run; 1815 1816 /* 1817 * Be fancy and try to print contiguous runs of 1818 * IRQ values as ranges. 'irq' is the previous IRQ. 1819 * 'run' is true if we are in a range. 1820 */ 1821 device_printf(child, "using IRQs %ju", rle->start); 1822 irq = rle->start; 1823 run = 0; 1824 for (i = 1; i < actual; i++) { 1825 rle = resource_list_find(&dinfo->resources, 1826 SYS_RES_IRQ, i + 1); 1827 1828 /* Still in a run? */ 1829 if (rle->start == irq + 1) { 1830 run = 1; 1831 irq++; 1832 continue; 1833 } 1834 1835 /* Finish previous range. */ 1836 if (run) { 1837 printf("-%d", irq); 1838 run = 0; 1839 } 1840 1841 /* Start new range. */ 1842 printf(",%ju", rle->start); 1843 irq = rle->start; 1844 } 1845 1846 /* Unfinished range? */ 1847 if (run) 1848 printf("-%d", irq); 1849 printf(" for MSI-X\n"); 1850 } 1851 } 1852 1853 /* Mask all vectors. */ 1854 for (i = 0; i < cfg->msix.msix_msgnum; i++) 1855 pci_mask_msix(child, i); 1856 1857 /* Allocate and initialize vector data and virtual table. */ 1858 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual, 1859 M_DEVBUF, M_WAITOK | M_ZERO); 1860 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual, 1861 M_DEVBUF, M_WAITOK | M_ZERO); 1862 for (i = 0; i < actual; i++) { 1863 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1864 cfg->msix.msix_vectors[i].mv_irq = rle->start; 1865 cfg->msix.msix_table[i].mte_vector = i + 1; 1866 } 1867 1868 /* Update control register to enable MSI-X. */ 1869 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 1870 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1871 cfg->msix.msix_ctrl, 2); 1872 1873 /* Update counts of alloc'd messages. */ 1874 cfg->msix.msix_alloc = actual; 1875 cfg->msix.msix_table_len = actual; 1876 *count = actual; 1877 return (0); 1878 } 1879 1880 /* 1881 * By default, pci_alloc_msix() will assign the allocated IRQ 1882 * resources consecutively to the first N messages in the MSI-X table. 1883 * However, device drivers may want to use different layouts if they 1884 * either receive fewer messages than they asked for, or they wish to 1885 * populate the MSI-X table sparsely. This method allows the driver 1886 * to specify what layout it wants. It must be called after a 1887 * successful pci_alloc_msix() but before any of the associated 1888 * SYS_RES_IRQ resources are allocated via bus_alloc_resource(). 1889 * 1890 * The 'vectors' array contains 'count' message vectors. The array 1891 * maps directly to the MSI-X table in that index 0 in the array 1892 * specifies the vector for the first message in the MSI-X table, etc. 1893 * The vector value in each array index can either be 0 to indicate 1894 * that no vector should be assigned to a message slot, or it can be a 1895 * number from 1 to N (where N is the count returned from a 1896 * succcessful call to pci_alloc_msix()) to indicate which message 1897 * vector (IRQ) to be used for the corresponding message. 1898 * 1899 * On successful return, each message with a non-zero vector will have 1900 * an associated SYS_RES_IRQ whose rid is equal to the array index + 1901 * 1. Additionally, if any of the IRQs allocated via the previous 1902 * call to pci_alloc_msix() are not used in the mapping, those IRQs 1903 * will be freed back to the system automatically. 1904 * 1905 * For example, suppose a driver has a MSI-X table with 6 messages and 1906 * asks for 6 messages, but pci_alloc_msix() only returns a count of 1907 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and 1908 * C. After the call to pci_alloc_msix(), the device will be setup to 1909 * have an MSI-X table of ABC--- (where - means no vector assigned). 1910 * If the driver then passes a vector array of { 1, 0, 1, 2, 0, 2 }, 1911 * then the MSI-X table will look like A-AB-B, and the 'C' vector will 1912 * be freed back to the system. This device will also have valid 1913 * SYS_RES_IRQ rids of 1, 3, 4, and 6. 1914 * 1915 * In any case, the SYS_RES_IRQ rid X will always map to the message 1916 * at MSI-X table index X - 1 and will only be valid if a vector is 1917 * assigned to that table entry. 1918 */ 1919 int 1920 pci_remap_msix_method(device_t dev, device_t child, int count, 1921 const u_int *vectors) 1922 { 1923 struct pci_devinfo *dinfo = device_get_ivars(child); 1924 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1925 struct resource_list_entry *rle; 1926 int i, irq, j, *used; 1927 1928 /* 1929 * Have to have at least one message in the table but the 1930 * table can't be bigger than the actual MSI-X table in the 1931 * device. 1932 */ 1933 if (count == 0 || count > msix->msix_msgnum) 1934 return (EINVAL); 1935 1936 /* Sanity check the vectors. */ 1937 for (i = 0; i < count; i++) 1938 if (vectors[i] > msix->msix_alloc) 1939 return (EINVAL); 1940 1941 /* 1942 * Make sure there aren't any holes in the vectors to be used. 1943 * It's a big pain to support it, and it doesn't really make 1944 * sense anyway. Also, at least one vector must be used. 1945 */ 1946 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK | 1947 M_ZERO); 1948 for (i = 0; i < count; i++) 1949 if (vectors[i] != 0) 1950 used[vectors[i] - 1] = 1; 1951 for (i = 0; i < msix->msix_alloc - 1; i++) 1952 if (used[i] == 0 && used[i + 1] == 1) { 1953 free(used, M_DEVBUF); 1954 return (EINVAL); 1955 } 1956 if (used[0] != 1) { 1957 free(used, M_DEVBUF); 1958 return (EINVAL); 1959 } 1960 1961 /* Make sure none of the resources are allocated. */ 1962 for (i = 0; i < msix->msix_table_len; i++) { 1963 if (msix->msix_table[i].mte_vector == 0) 1964 continue; 1965 if (msix->msix_table[i].mte_handlers > 0) { 1966 free(used, M_DEVBUF); 1967 return (EBUSY); 1968 } 1969 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1970 KASSERT(rle != NULL, ("missing resource")); 1971 if (rle->res != NULL) { 1972 free(used, M_DEVBUF); 1973 return (EBUSY); 1974 } 1975 } 1976 1977 /* Free the existing resource list entries. */ 1978 for (i = 0; i < msix->msix_table_len; i++) { 1979 if (msix->msix_table[i].mte_vector == 0) 1980 continue; 1981 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 1982 } 1983 1984 /* 1985 * Build the new virtual table keeping track of which vectors are 1986 * used. 1987 */ 1988 free(msix->msix_table, M_DEVBUF); 1989 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count, 1990 M_DEVBUF, M_WAITOK | M_ZERO); 1991 for (i = 0; i < count; i++) 1992 msix->msix_table[i].mte_vector = vectors[i]; 1993 msix->msix_table_len = count; 1994 1995 /* Free any unused IRQs and resize the vectors array if necessary. */ 1996 j = msix->msix_alloc - 1; 1997 if (used[j] == 0) { 1998 struct msix_vector *vec; 1999 2000 while (used[j] == 0) { 2001 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2002 msix->msix_vectors[j].mv_irq); 2003 j--; 2004 } 2005 vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF, 2006 M_WAITOK); 2007 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) * 2008 (j + 1)); 2009 free(msix->msix_vectors, M_DEVBUF); 2010 msix->msix_vectors = vec; 2011 msix->msix_alloc = j + 1; 2012 } 2013 free(used, M_DEVBUF); 2014 2015 /* Map the IRQs onto the rids. */ 2016 for (i = 0; i < count; i++) { 2017 if (vectors[i] == 0) 2018 continue; 2019 irq = msix->msix_vectors[vectors[i] - 1].mv_irq; 2020 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 2021 irq, 1); 2022 } 2023 2024 if (bootverbose) { 2025 device_printf(child, "Remapped MSI-X IRQs as: "); 2026 for (i = 0; i < count; i++) { 2027 if (i != 0) 2028 printf(", "); 2029 if (vectors[i] == 0) 2030 printf("---"); 2031 else 2032 printf("%d", 2033 msix->msix_vectors[vectors[i] - 1].mv_irq); 2034 } 2035 printf("\n"); 2036 } 2037 2038 return (0); 2039 } 2040 2041 static int 2042 pci_release_msix(device_t dev, device_t child) 2043 { 2044 struct pci_devinfo *dinfo = device_get_ivars(child); 2045 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2046 struct resource_list_entry *rle; 2047 int i; 2048 2049 /* Do we have any messages to release? */ 2050 if (msix->msix_alloc == 0) 2051 return (ENODEV); 2052 2053 /* Make sure none of the resources are allocated. */ 2054 for (i = 0; i < msix->msix_table_len; i++) { 2055 if (msix->msix_table[i].mte_vector == 0) 2056 continue; 2057 if (msix->msix_table[i].mte_handlers > 0) 2058 return (EBUSY); 2059 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2060 KASSERT(rle != NULL, ("missing resource")); 2061 if (rle->res != NULL) 2062 return (EBUSY); 2063 } 2064 2065 /* Update control register to disable MSI-X. */ 2066 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; 2067 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL, 2068 msix->msix_ctrl, 2); 2069 2070 /* Free the resource list entries. */ 2071 for (i = 0; i < msix->msix_table_len; i++) { 2072 if (msix->msix_table[i].mte_vector == 0) 2073 continue; 2074 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2075 } 2076 free(msix->msix_table, M_DEVBUF); 2077 msix->msix_table_len = 0; 2078 2079 /* Release the IRQs. */ 2080 for (i = 0; i < msix->msix_alloc; i++) 2081 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2082 msix->msix_vectors[i].mv_irq); 2083 free(msix->msix_vectors, M_DEVBUF); 2084 msix->msix_alloc = 0; 2085 return (0); 2086 } 2087 2088 /* 2089 * Return the max supported MSI-X messages this device supports. 2090 * Basically, assuming the MD code can alloc messages, this function 2091 * should return the maximum value that pci_alloc_msix() can return. 2092 * Thus, it is subject to the tunables, etc. 2093 */ 2094 int 2095 pci_msix_count_method(device_t dev, device_t child) 2096 { 2097 struct pci_devinfo *dinfo = device_get_ivars(child); 2098 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2099 2100 if (pci_do_msix && msix->msix_location != 0) 2101 return (msix->msix_msgnum); 2102 return (0); 2103 } 2104 2105 int 2106 pci_msix_pba_bar_method(device_t dev, device_t child) 2107 { 2108 struct pci_devinfo *dinfo = device_get_ivars(child); 2109 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2110 2111 if (pci_do_msix && msix->msix_location != 0) 2112 return (msix->msix_pba_bar); 2113 return (-1); 2114 } 2115 2116 int 2117 pci_msix_table_bar_method(device_t dev, device_t child) 2118 { 2119 struct pci_devinfo *dinfo = device_get_ivars(child); 2120 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2121 2122 if (pci_do_msix && msix->msix_location != 0) 2123 return (msix->msix_table_bar); 2124 return (-1); 2125 } 2126 2127 /* 2128 * HyperTransport MSI mapping control 2129 */ 2130 void 2131 pci_ht_map_msi(device_t dev, uint64_t addr) 2132 { 2133 struct pci_devinfo *dinfo = device_get_ivars(dev); 2134 struct pcicfg_ht *ht = &dinfo->cfg.ht; 2135 2136 if (!ht->ht_msimap) 2137 return; 2138 2139 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) && 2140 ht->ht_msiaddr >> 20 == addr >> 20) { 2141 /* Enable MSI -> HT mapping. */ 2142 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 2143 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2144 ht->ht_msictrl, 2); 2145 } 2146 2147 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) { 2148 /* Disable MSI -> HT mapping. */ 2149 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE; 2150 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2151 ht->ht_msictrl, 2); 2152 } 2153 } 2154 2155 int 2156 pci_get_max_payload(device_t dev) 2157 { 2158 struct pci_devinfo *dinfo = device_get_ivars(dev); 2159 int cap; 2160 uint16_t val; 2161 2162 cap = dinfo->cfg.pcie.pcie_location; 2163 if (cap == 0) 2164 return (0); 2165 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2166 val &= PCIEM_CTL_MAX_PAYLOAD; 2167 val >>= 5; 2168 return (1 << (val + 7)); 2169 } 2170 2171 int 2172 pci_get_max_read_req(device_t dev) 2173 { 2174 struct pci_devinfo *dinfo = device_get_ivars(dev); 2175 int cap; 2176 uint16_t val; 2177 2178 cap = dinfo->cfg.pcie.pcie_location; 2179 if (cap == 0) 2180 return (0); 2181 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2182 val &= PCIEM_CTL_MAX_READ_REQUEST; 2183 val >>= 12; 2184 return (1 << (val + 7)); 2185 } 2186 2187 int 2188 pci_set_max_read_req(device_t dev, int size) 2189 { 2190 struct pci_devinfo *dinfo = device_get_ivars(dev); 2191 int cap; 2192 uint16_t val; 2193 2194 cap = dinfo->cfg.pcie.pcie_location; 2195 if (cap == 0) 2196 return (0); 2197 if (size < 128) 2198 size = 128; 2199 if (size > 4096) 2200 size = 4096; 2201 size = (1 << (fls(size) - 1)); 2202 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2203 val &= ~PCIEM_CTL_MAX_READ_REQUEST; 2204 val |= (fls(size) - 8) << 12; 2205 pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2); 2206 return (size); 2207 } 2208 2209 uint32_t 2210 pcie_read_config(device_t dev, int reg, int width) 2211 { 2212 struct pci_devinfo *dinfo = device_get_ivars(dev); 2213 int cap; 2214 2215 cap = dinfo->cfg.pcie.pcie_location; 2216 if (cap == 0) { 2217 if (width == 2) 2218 return (0xffff); 2219 return (0xffffffff); 2220 } 2221 2222 return (pci_read_config(dev, cap + reg, width)); 2223 } 2224 2225 void 2226 pcie_write_config(device_t dev, int reg, uint32_t value, int width) 2227 { 2228 struct pci_devinfo *dinfo = device_get_ivars(dev); 2229 int cap; 2230 2231 cap = dinfo->cfg.pcie.pcie_location; 2232 if (cap == 0) 2233 return; 2234 pci_write_config(dev, cap + reg, value, width); 2235 } 2236 2237 /* 2238 * Adjusts a PCI-e capability register by clearing the bits in mask 2239 * and setting the bits in (value & mask). Bits not set in mask are 2240 * not adjusted. 2241 * 2242 * Returns the old value on success or all ones on failure. 2243 */ 2244 uint32_t 2245 pcie_adjust_config(device_t dev, int reg, uint32_t mask, uint32_t value, 2246 int width) 2247 { 2248 struct pci_devinfo *dinfo = device_get_ivars(dev); 2249 uint32_t old, new; 2250 int cap; 2251 2252 cap = dinfo->cfg.pcie.pcie_location; 2253 if (cap == 0) { 2254 if (width == 2) 2255 return (0xffff); 2256 return (0xffffffff); 2257 } 2258 2259 old = pci_read_config(dev, cap + reg, width); 2260 new = old & ~mask; 2261 new |= (value & mask); 2262 pci_write_config(dev, cap + reg, new, width); 2263 return (old); 2264 } 2265 2266 /* 2267 * Support for MSI message signalled interrupts. 2268 */ 2269 void 2270 pci_enable_msi_method(device_t dev, device_t child, uint64_t address, 2271 uint16_t data) 2272 { 2273 struct pci_devinfo *dinfo = device_get_ivars(child); 2274 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2275 2276 /* Write data and address values. */ 2277 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR, 2278 address & 0xffffffff, 4); 2279 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2280 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR_HIGH, 2281 address >> 32, 4); 2282 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA_64BIT, 2283 data, 2); 2284 } else 2285 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA, data, 2286 2); 2287 2288 /* Enable MSI in the control register. */ 2289 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; 2290 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2291 msi->msi_ctrl, 2); 2292 2293 /* Enable MSI -> HT mapping. */ 2294 pci_ht_map_msi(child, address); 2295 } 2296 2297 void 2298 pci_disable_msi_method(device_t dev, device_t child) 2299 { 2300 struct pci_devinfo *dinfo = device_get_ivars(child); 2301 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2302 2303 /* Disable MSI -> HT mapping. */ 2304 pci_ht_map_msi(child, 0); 2305 2306 /* Disable MSI in the control register. */ 2307 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE; 2308 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2309 msi->msi_ctrl, 2); 2310 } 2311 2312 /* 2313 * Restore MSI registers during resume. If MSI is enabled then 2314 * restore the data and address registers in addition to the control 2315 * register. 2316 */ 2317 static void 2318 pci_resume_msi(device_t dev) 2319 { 2320 struct pci_devinfo *dinfo = device_get_ivars(dev); 2321 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2322 uint64_t address; 2323 uint16_t data; 2324 2325 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { 2326 address = msi->msi_addr; 2327 data = msi->msi_data; 2328 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, 2329 address & 0xffffffff, 4); 2330 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2331 pci_write_config(dev, msi->msi_location + 2332 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 2333 pci_write_config(dev, msi->msi_location + 2334 PCIR_MSI_DATA_64BIT, data, 2); 2335 } else 2336 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, 2337 data, 2); 2338 } 2339 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 2340 2); 2341 } 2342 2343 static int 2344 pci_remap_intr_method(device_t bus, device_t dev, u_int irq) 2345 { 2346 struct pci_devinfo *dinfo = device_get_ivars(dev); 2347 pcicfgregs *cfg = &dinfo->cfg; 2348 struct resource_list_entry *rle; 2349 struct msix_table_entry *mte; 2350 struct msix_vector *mv; 2351 uint64_t addr; 2352 uint32_t data; 2353 int error, i, j; 2354 2355 /* 2356 * Handle MSI first. We try to find this IRQ among our list 2357 * of MSI IRQs. If we find it, we request updated address and 2358 * data registers and apply the results. 2359 */ 2360 if (cfg->msi.msi_alloc > 0) { 2361 2362 /* If we don't have any active handlers, nothing to do. */ 2363 if (cfg->msi.msi_handlers == 0) 2364 return (0); 2365 for (i = 0; i < cfg->msi.msi_alloc; i++) { 2366 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 2367 i + 1); 2368 if (rle->start == irq) { 2369 error = PCIB_MAP_MSI(device_get_parent(bus), 2370 dev, irq, &addr, &data); 2371 if (error) 2372 return (error); 2373 pci_disable_msi(dev); 2374 dinfo->cfg.msi.msi_addr = addr; 2375 dinfo->cfg.msi.msi_data = data; 2376 pci_enable_msi(dev, addr, data); 2377 return (0); 2378 } 2379 } 2380 return (ENOENT); 2381 } 2382 2383 /* 2384 * For MSI-X, we check to see if we have this IRQ. If we do, 2385 * we request the updated mapping info. If that works, we go 2386 * through all the slots that use this IRQ and update them. 2387 */ 2388 if (cfg->msix.msix_alloc > 0) { 2389 for (i = 0; i < cfg->msix.msix_alloc; i++) { 2390 mv = &cfg->msix.msix_vectors[i]; 2391 if (mv->mv_irq == irq) { 2392 error = PCIB_MAP_MSI(device_get_parent(bus), 2393 dev, irq, &addr, &data); 2394 if (error) 2395 return (error); 2396 mv->mv_address = addr; 2397 mv->mv_data = data; 2398 for (j = 0; j < cfg->msix.msix_table_len; j++) { 2399 mte = &cfg->msix.msix_table[j]; 2400 if (mte->mte_vector != i + 1) 2401 continue; 2402 if (mte->mte_handlers == 0) 2403 continue; 2404 pci_mask_msix(dev, j); 2405 pci_enable_msix(dev, j, addr, data); 2406 pci_unmask_msix(dev, j); 2407 } 2408 } 2409 } 2410 return (ENOENT); 2411 } 2412 2413 return (ENOENT); 2414 } 2415 2416 /* 2417 * Returns true if the specified device is blacklisted because MSI 2418 * doesn't work. 2419 */ 2420 int 2421 pci_msi_device_blacklisted(device_t dev) 2422 { 2423 2424 if (!pci_honor_msi_blacklist) 2425 return (0); 2426 2427 return (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSI)); 2428 } 2429 2430 /* 2431 * Determine if MSI is blacklisted globally on this system. Currently, 2432 * we just check for blacklisted chipsets as represented by the 2433 * host-PCI bridge at device 0:0:0. In the future, it may become 2434 * necessary to check other system attributes, such as the kenv values 2435 * that give the motherboard manufacturer and model number. 2436 */ 2437 static int 2438 pci_msi_blacklisted(void) 2439 { 2440 device_t dev; 2441 2442 if (!pci_honor_msi_blacklist) 2443 return (0); 2444 2445 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */ 2446 if (!(pcie_chipset || pcix_chipset)) { 2447 if (vm_guest != VM_GUEST_NO) { 2448 /* 2449 * Whitelist older chipsets in virtual 2450 * machines known to support MSI. 2451 */ 2452 dev = pci_find_bsf(0, 0, 0); 2453 if (dev != NULL) 2454 return (!pci_has_quirk(pci_get_devid(dev), 2455 PCI_QUIRK_ENABLE_MSI_VM)); 2456 } 2457 return (1); 2458 } 2459 2460 dev = pci_find_bsf(0, 0, 0); 2461 if (dev != NULL) 2462 return (pci_msi_device_blacklisted(dev)); 2463 return (0); 2464 } 2465 2466 /* 2467 * Returns true if the specified device is blacklisted because MSI-X 2468 * doesn't work. Note that this assumes that if MSI doesn't work, 2469 * MSI-X doesn't either. 2470 */ 2471 int 2472 pci_msix_device_blacklisted(device_t dev) 2473 { 2474 2475 if (!pci_honor_msi_blacklist) 2476 return (0); 2477 2478 if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSIX)) 2479 return (1); 2480 2481 return (pci_msi_device_blacklisted(dev)); 2482 } 2483 2484 /* 2485 * Determine if MSI-X is blacklisted globally on this system. If MSI 2486 * is blacklisted, assume that MSI-X is as well. Check for additional 2487 * chipsets where MSI works but MSI-X does not. 2488 */ 2489 static int 2490 pci_msix_blacklisted(void) 2491 { 2492 device_t dev; 2493 2494 if (!pci_honor_msi_blacklist) 2495 return (0); 2496 2497 dev = pci_find_bsf(0, 0, 0); 2498 if (dev != NULL && pci_has_quirk(pci_get_devid(dev), 2499 PCI_QUIRK_DISABLE_MSIX)) 2500 return (1); 2501 2502 return (pci_msi_blacklisted()); 2503 } 2504 2505 /* 2506 * Attempt to allocate *count MSI messages. The actual number allocated is 2507 * returned in *count. After this function returns, each message will be 2508 * available to the driver as SYS_RES_IRQ resources starting at a rid 1. 2509 */ 2510 int 2511 pci_alloc_msi_method(device_t dev, device_t child, int *count) 2512 { 2513 struct pci_devinfo *dinfo = device_get_ivars(child); 2514 pcicfgregs *cfg = &dinfo->cfg; 2515 struct resource_list_entry *rle; 2516 int actual, error, i, irqs[32]; 2517 uint16_t ctrl; 2518 2519 /* Don't let count == 0 get us into trouble. */ 2520 if (*count == 0) 2521 return (EINVAL); 2522 2523 /* If rid 0 is allocated, then fail. */ 2524 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 2525 if (rle != NULL && rle->res != NULL) 2526 return (ENXIO); 2527 2528 /* Already have allocated messages? */ 2529 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 2530 return (ENXIO); 2531 2532 /* If MSI is blacklisted for this system, fail. */ 2533 if (pci_msi_blacklisted()) 2534 return (ENXIO); 2535 2536 /* MSI capability present? */ 2537 if (cfg->msi.msi_location == 0 || !pci_do_msi) 2538 return (ENODEV); 2539 2540 if (bootverbose) 2541 device_printf(child, 2542 "attempting to allocate %d MSI vectors (%d supported)\n", 2543 *count, cfg->msi.msi_msgnum); 2544 2545 /* Don't ask for more than the device supports. */ 2546 actual = min(*count, cfg->msi.msi_msgnum); 2547 2548 /* Don't ask for more than 32 messages. */ 2549 actual = min(actual, 32); 2550 2551 /* MSI requires power of 2 number of messages. */ 2552 if (!powerof2(actual)) 2553 return (EINVAL); 2554 2555 for (;;) { 2556 /* Try to allocate N messages. */ 2557 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual, 2558 actual, irqs); 2559 if (error == 0) 2560 break; 2561 if (actual == 1) 2562 return (error); 2563 2564 /* Try N / 2. */ 2565 actual >>= 1; 2566 } 2567 2568 /* 2569 * We now have N actual messages mapped onto SYS_RES_IRQ 2570 * resources in the irqs[] array, so add new resources 2571 * starting at rid 1. 2572 */ 2573 for (i = 0; i < actual; i++) 2574 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, 2575 irqs[i], irqs[i], 1); 2576 2577 if (bootverbose) { 2578 if (actual == 1) 2579 device_printf(child, "using IRQ %d for MSI\n", irqs[0]); 2580 else { 2581 int run; 2582 2583 /* 2584 * Be fancy and try to print contiguous runs 2585 * of IRQ values as ranges. 'run' is true if 2586 * we are in a range. 2587 */ 2588 device_printf(child, "using IRQs %d", irqs[0]); 2589 run = 0; 2590 for (i = 1; i < actual; i++) { 2591 2592 /* Still in a run? */ 2593 if (irqs[i] == irqs[i - 1] + 1) { 2594 run = 1; 2595 continue; 2596 } 2597 2598 /* Finish previous range. */ 2599 if (run) { 2600 printf("-%d", irqs[i - 1]); 2601 run = 0; 2602 } 2603 2604 /* Start new range. */ 2605 printf(",%d", irqs[i]); 2606 } 2607 2608 /* Unfinished range? */ 2609 if (run) 2610 printf("-%d", irqs[actual - 1]); 2611 printf(" for MSI\n"); 2612 } 2613 } 2614 2615 /* Update control register with actual count. */ 2616 ctrl = cfg->msi.msi_ctrl; 2617 ctrl &= ~PCIM_MSICTRL_MME_MASK; 2618 ctrl |= (ffs(actual) - 1) << 4; 2619 cfg->msi.msi_ctrl = ctrl; 2620 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); 2621 2622 /* Update counts of alloc'd messages. */ 2623 cfg->msi.msi_alloc = actual; 2624 cfg->msi.msi_handlers = 0; 2625 *count = actual; 2626 return (0); 2627 } 2628 2629 /* Release the MSI messages associated with this device. */ 2630 int 2631 pci_release_msi_method(device_t dev, device_t child) 2632 { 2633 struct pci_devinfo *dinfo = device_get_ivars(child); 2634 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2635 struct resource_list_entry *rle; 2636 int error, i, irqs[32]; 2637 2638 /* Try MSI-X first. */ 2639 error = pci_release_msix(dev, child); 2640 if (error != ENODEV) 2641 return (error); 2642 2643 /* Do we have any messages to release? */ 2644 if (msi->msi_alloc == 0) 2645 return (ENODEV); 2646 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages")); 2647 2648 /* Make sure none of the resources are allocated. */ 2649 if (msi->msi_handlers > 0) 2650 return (EBUSY); 2651 for (i = 0; i < msi->msi_alloc; i++) { 2652 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2653 KASSERT(rle != NULL, ("missing MSI resource")); 2654 if (rle->res != NULL) 2655 return (EBUSY); 2656 irqs[i] = rle->start; 2657 } 2658 2659 /* Update control register with 0 count. */ 2660 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE), 2661 ("%s: MSI still enabled", __func__)); 2662 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK; 2663 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2664 msi->msi_ctrl, 2); 2665 2666 /* Release the messages. */ 2667 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs); 2668 for (i = 0; i < msi->msi_alloc; i++) 2669 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2670 2671 /* Update alloc count. */ 2672 msi->msi_alloc = 0; 2673 msi->msi_addr = 0; 2674 msi->msi_data = 0; 2675 return (0); 2676 } 2677 2678 /* 2679 * Return the max supported MSI messages this device supports. 2680 * Basically, assuming the MD code can alloc messages, this function 2681 * should return the maximum value that pci_alloc_msi() can return. 2682 * Thus, it is subject to the tunables, etc. 2683 */ 2684 int 2685 pci_msi_count_method(device_t dev, device_t child) 2686 { 2687 struct pci_devinfo *dinfo = device_get_ivars(child); 2688 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2689 2690 if (pci_do_msi && msi->msi_location != 0) 2691 return (msi->msi_msgnum); 2692 return (0); 2693 } 2694 2695 /* free pcicfgregs structure and all depending data structures */ 2696 2697 int 2698 pci_freecfg(struct pci_devinfo *dinfo) 2699 { 2700 struct devlist *devlist_head; 2701 struct pci_map *pm, *next; 2702 int i; 2703 2704 devlist_head = &pci_devq; 2705 2706 if (dinfo->cfg.vpd.vpd_reg) { 2707 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF); 2708 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++) 2709 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF); 2710 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF); 2711 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++) 2712 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF); 2713 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF); 2714 } 2715 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) { 2716 free(pm, M_DEVBUF); 2717 } 2718 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 2719 free(dinfo, M_DEVBUF); 2720 2721 /* increment the generation count */ 2722 pci_generation++; 2723 2724 /* we're losing one device */ 2725 pci_numdevs--; 2726 return (0); 2727 } 2728 2729 /* 2730 * PCI power manangement 2731 */ 2732 int 2733 pci_set_powerstate_method(device_t dev, device_t child, int state) 2734 { 2735 struct pci_devinfo *dinfo = device_get_ivars(child); 2736 pcicfgregs *cfg = &dinfo->cfg; 2737 uint16_t status; 2738 int oldstate, highest, delay; 2739 2740 if (cfg->pp.pp_cap == 0) 2741 return (EOPNOTSUPP); 2742 2743 /* 2744 * Optimize a no state change request away. While it would be OK to 2745 * write to the hardware in theory, some devices have shown odd 2746 * behavior when going from D3 -> D3. 2747 */ 2748 oldstate = pci_get_powerstate(child); 2749 if (oldstate == state) 2750 return (0); 2751 2752 /* 2753 * The PCI power management specification states that after a state 2754 * transition between PCI power states, system software must 2755 * guarantee a minimal delay before the function accesses the device. 2756 * Compute the worst case delay that we need to guarantee before we 2757 * access the device. Many devices will be responsive much more 2758 * quickly than this delay, but there are some that don't respond 2759 * instantly to state changes. Transitions to/from D3 state require 2760 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 2761 * is done below with DELAY rather than a sleeper function because 2762 * this function can be called from contexts where we cannot sleep. 2763 */ 2764 highest = (oldstate > state) ? oldstate : state; 2765 if (highest == PCI_POWERSTATE_D3) 2766 delay = 10000; 2767 else if (highest == PCI_POWERSTATE_D2) 2768 delay = 200; 2769 else 2770 delay = 0; 2771 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 2772 & ~PCIM_PSTAT_DMASK; 2773 switch (state) { 2774 case PCI_POWERSTATE_D0: 2775 status |= PCIM_PSTAT_D0; 2776 break; 2777 case PCI_POWERSTATE_D1: 2778 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 2779 return (EOPNOTSUPP); 2780 status |= PCIM_PSTAT_D1; 2781 break; 2782 case PCI_POWERSTATE_D2: 2783 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 2784 return (EOPNOTSUPP); 2785 status |= PCIM_PSTAT_D2; 2786 break; 2787 case PCI_POWERSTATE_D3: 2788 status |= PCIM_PSTAT_D3; 2789 break; 2790 default: 2791 return (EINVAL); 2792 } 2793 2794 if (bootverbose) 2795 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate, 2796 state); 2797 2798 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 2799 if (delay) 2800 DELAY(delay); 2801 return (0); 2802 } 2803 2804 int 2805 pci_get_powerstate_method(device_t dev, device_t child) 2806 { 2807 struct pci_devinfo *dinfo = device_get_ivars(child); 2808 pcicfgregs *cfg = &dinfo->cfg; 2809 uint16_t status; 2810 int result; 2811 2812 if (cfg->pp.pp_cap != 0) { 2813 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 2814 switch (status & PCIM_PSTAT_DMASK) { 2815 case PCIM_PSTAT_D0: 2816 result = PCI_POWERSTATE_D0; 2817 break; 2818 case PCIM_PSTAT_D1: 2819 result = PCI_POWERSTATE_D1; 2820 break; 2821 case PCIM_PSTAT_D2: 2822 result = PCI_POWERSTATE_D2; 2823 break; 2824 case PCIM_PSTAT_D3: 2825 result = PCI_POWERSTATE_D3; 2826 break; 2827 default: 2828 result = PCI_POWERSTATE_UNKNOWN; 2829 break; 2830 } 2831 } else { 2832 /* No support, device is always at D0 */ 2833 result = PCI_POWERSTATE_D0; 2834 } 2835 return (result); 2836 } 2837 2838 /* 2839 * Some convenience functions for PCI device drivers. 2840 */ 2841 2842 static __inline void 2843 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 2844 { 2845 uint16_t command; 2846 2847 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2848 command |= bit; 2849 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2850 } 2851 2852 static __inline void 2853 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 2854 { 2855 uint16_t command; 2856 2857 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2858 command &= ~bit; 2859 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2860 } 2861 2862 int 2863 pci_enable_busmaster_method(device_t dev, device_t child) 2864 { 2865 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2866 return (0); 2867 } 2868 2869 int 2870 pci_disable_busmaster_method(device_t dev, device_t child) 2871 { 2872 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2873 return (0); 2874 } 2875 2876 int 2877 pci_enable_io_method(device_t dev, device_t child, int space) 2878 { 2879 uint16_t bit; 2880 2881 switch(space) { 2882 case SYS_RES_IOPORT: 2883 bit = PCIM_CMD_PORTEN; 2884 break; 2885 case SYS_RES_MEMORY: 2886 bit = PCIM_CMD_MEMEN; 2887 break; 2888 default: 2889 return (EINVAL); 2890 } 2891 pci_set_command_bit(dev, child, bit); 2892 return (0); 2893 } 2894 2895 int 2896 pci_disable_io_method(device_t dev, device_t child, int space) 2897 { 2898 uint16_t bit; 2899 2900 switch(space) { 2901 case SYS_RES_IOPORT: 2902 bit = PCIM_CMD_PORTEN; 2903 break; 2904 case SYS_RES_MEMORY: 2905 bit = PCIM_CMD_MEMEN; 2906 break; 2907 default: 2908 return (EINVAL); 2909 } 2910 pci_clear_command_bit(dev, child, bit); 2911 return (0); 2912 } 2913 2914 /* 2915 * New style pci driver. Parent device is either a pci-host-bridge or a 2916 * pci-pci-bridge. Both kinds are represented by instances of pcib. 2917 */ 2918 2919 void 2920 pci_print_verbose(struct pci_devinfo *dinfo) 2921 { 2922 2923 if (bootverbose) { 2924 pcicfgregs *cfg = &dinfo->cfg; 2925 2926 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 2927 cfg->vendor, cfg->device, cfg->revid); 2928 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n", 2929 cfg->domain, cfg->bus, cfg->slot, cfg->func); 2930 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 2931 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 2932 cfg->mfdev); 2933 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 2934 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 2935 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 2936 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 2937 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 2938 if (cfg->intpin > 0) 2939 printf("\tintpin=%c, irq=%d\n", 2940 cfg->intpin +'a' -1, cfg->intline); 2941 if (cfg->pp.pp_cap) { 2942 uint16_t status; 2943 2944 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 2945 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 2946 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 2947 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 2948 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 2949 status & PCIM_PSTAT_DMASK); 2950 } 2951 if (cfg->msi.msi_location) { 2952 int ctrl; 2953 2954 ctrl = cfg->msi.msi_ctrl; 2955 printf("\tMSI supports %d message%s%s%s\n", 2956 cfg->msi.msi_msgnum, 2957 (cfg->msi.msi_msgnum == 1) ? "" : "s", 2958 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 2959 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 2960 } 2961 if (cfg->msix.msix_location) { 2962 printf("\tMSI-X supports %d message%s ", 2963 cfg->msix.msix_msgnum, 2964 (cfg->msix.msix_msgnum == 1) ? "" : "s"); 2965 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) 2966 printf("in map 0x%x\n", 2967 cfg->msix.msix_table_bar); 2968 else 2969 printf("in maps 0x%x and 0x%x\n", 2970 cfg->msix.msix_table_bar, 2971 cfg->msix.msix_pba_bar); 2972 } 2973 } 2974 } 2975 2976 static int 2977 pci_porten(device_t dev) 2978 { 2979 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0; 2980 } 2981 2982 static int 2983 pci_memen(device_t dev) 2984 { 2985 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0; 2986 } 2987 2988 void 2989 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp, 2990 int *bar64) 2991 { 2992 struct pci_devinfo *dinfo; 2993 pci_addr_t map, testval; 2994 int ln2range; 2995 uint16_t cmd; 2996 2997 /* 2998 * The device ROM BAR is special. It is always a 32-bit 2999 * memory BAR. Bit 0 is special and should not be set when 3000 * sizing the BAR. 3001 */ 3002 dinfo = device_get_ivars(dev); 3003 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) { 3004 map = pci_read_config(dev, reg, 4); 3005 pci_write_config(dev, reg, 0xfffffffe, 4); 3006 testval = pci_read_config(dev, reg, 4); 3007 pci_write_config(dev, reg, map, 4); 3008 *mapp = map; 3009 *testvalp = testval; 3010 if (bar64 != NULL) 3011 *bar64 = 0; 3012 return; 3013 } 3014 3015 map = pci_read_config(dev, reg, 4); 3016 ln2range = pci_maprange(map); 3017 if (ln2range == 64) 3018 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3019 3020 /* 3021 * Disable decoding via the command register before 3022 * determining the BAR's length since we will be placing it in 3023 * a weird state. 3024 */ 3025 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3026 pci_write_config(dev, PCIR_COMMAND, 3027 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 3028 3029 /* 3030 * Determine the BAR's length by writing all 1's. The bottom 3031 * log_2(size) bits of the BAR will stick as 0 when we read 3032 * the value back. 3033 * 3034 * NB: according to the PCI Local Bus Specification, rev. 3.0: 3035 * "Software writes 0FFFFFFFFh to both registers, reads them back, 3036 * and combines the result into a 64-bit value." (section 6.2.5.1) 3037 * 3038 * Writes to both registers must be performed before attempting to 3039 * read back the size value. 3040 */ 3041 testval = 0; 3042 pci_write_config(dev, reg, 0xffffffff, 4); 3043 if (ln2range == 64) { 3044 pci_write_config(dev, reg + 4, 0xffffffff, 4); 3045 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3046 } 3047 testval |= pci_read_config(dev, reg, 4); 3048 3049 /* 3050 * Restore the original value of the BAR. We may have reprogrammed 3051 * the BAR of the low-level console device and when booting verbose, 3052 * we need the console device addressable. 3053 */ 3054 pci_write_config(dev, reg, map, 4); 3055 if (ln2range == 64) 3056 pci_write_config(dev, reg + 4, map >> 32, 4); 3057 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3058 3059 *mapp = map; 3060 *testvalp = testval; 3061 if (bar64 != NULL) 3062 *bar64 = (ln2range == 64); 3063 } 3064 3065 static void 3066 pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base) 3067 { 3068 struct pci_devinfo *dinfo; 3069 int ln2range; 3070 3071 /* The device ROM BAR is always a 32-bit memory BAR. */ 3072 dinfo = device_get_ivars(dev); 3073 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3074 ln2range = 32; 3075 else 3076 ln2range = pci_maprange(pm->pm_value); 3077 pci_write_config(dev, pm->pm_reg, base, 4); 3078 if (ln2range == 64) 3079 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4); 3080 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4); 3081 if (ln2range == 64) 3082 pm->pm_value |= (pci_addr_t)pci_read_config(dev, 3083 pm->pm_reg + 4, 4) << 32; 3084 } 3085 3086 struct pci_map * 3087 pci_find_bar(device_t dev, int reg) 3088 { 3089 struct pci_devinfo *dinfo; 3090 struct pci_map *pm; 3091 3092 dinfo = device_get_ivars(dev); 3093 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3094 if (pm->pm_reg == reg) 3095 return (pm); 3096 } 3097 return (NULL); 3098 } 3099 3100 int 3101 pci_bar_enabled(device_t dev, struct pci_map *pm) 3102 { 3103 struct pci_devinfo *dinfo; 3104 uint16_t cmd; 3105 3106 dinfo = device_get_ivars(dev); 3107 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) && 3108 !(pm->pm_value & PCIM_BIOS_ENABLE)) 3109 return (0); 3110 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3111 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value)) 3112 return ((cmd & PCIM_CMD_MEMEN) != 0); 3113 else 3114 return ((cmd & PCIM_CMD_PORTEN) != 0); 3115 } 3116 3117 struct pci_map * 3118 pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size) 3119 { 3120 struct pci_devinfo *dinfo; 3121 struct pci_map *pm, *prev; 3122 3123 dinfo = device_get_ivars(dev); 3124 pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO); 3125 pm->pm_reg = reg; 3126 pm->pm_value = value; 3127 pm->pm_size = size; 3128 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) { 3129 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x", 3130 reg)); 3131 if (STAILQ_NEXT(prev, pm_link) == NULL || 3132 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg) 3133 break; 3134 } 3135 if (prev != NULL) 3136 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link); 3137 else 3138 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link); 3139 return (pm); 3140 } 3141 3142 static void 3143 pci_restore_bars(device_t dev) 3144 { 3145 struct pci_devinfo *dinfo; 3146 struct pci_map *pm; 3147 int ln2range; 3148 3149 dinfo = device_get_ivars(dev); 3150 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3151 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3152 ln2range = 32; 3153 else 3154 ln2range = pci_maprange(pm->pm_value); 3155 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4); 3156 if (ln2range == 64) 3157 pci_write_config(dev, pm->pm_reg + 4, 3158 pm->pm_value >> 32, 4); 3159 } 3160 } 3161 3162 /* 3163 * Add a resource based on a pci map register. Return 1 if the map 3164 * register is a 32bit map register or 2 if it is a 64bit register. 3165 */ 3166 static int 3167 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl, 3168 int force, int prefetch) 3169 { 3170 struct pci_map *pm; 3171 pci_addr_t base, map, testval; 3172 pci_addr_t start, end, count; 3173 int barlen, basezero, flags, maprange, mapsize, type; 3174 uint16_t cmd; 3175 struct resource *res; 3176 3177 /* 3178 * The BAR may already exist if the device is a CardBus card 3179 * whose CIS is stored in this BAR. 3180 */ 3181 pm = pci_find_bar(dev, reg); 3182 if (pm != NULL) { 3183 maprange = pci_maprange(pm->pm_value); 3184 barlen = maprange == 64 ? 2 : 1; 3185 return (barlen); 3186 } 3187 3188 pci_read_bar(dev, reg, &map, &testval, NULL); 3189 if (PCI_BAR_MEM(map)) { 3190 type = SYS_RES_MEMORY; 3191 if (map & PCIM_BAR_MEM_PREFETCH) 3192 prefetch = 1; 3193 } else 3194 type = SYS_RES_IOPORT; 3195 mapsize = pci_mapsize(testval); 3196 base = pci_mapbase(map); 3197 #ifdef __PCI_BAR_ZERO_VALID 3198 basezero = 0; 3199 #else 3200 basezero = base == 0; 3201 #endif 3202 maprange = pci_maprange(map); 3203 barlen = maprange == 64 ? 2 : 1; 3204 3205 /* 3206 * For I/O registers, if bottom bit is set, and the next bit up 3207 * isn't clear, we know we have a BAR that doesn't conform to the 3208 * spec, so ignore it. Also, sanity check the size of the data 3209 * areas to the type of memory involved. Memory must be at least 3210 * 16 bytes in size, while I/O ranges must be at least 4. 3211 */ 3212 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0) 3213 return (barlen); 3214 if ((type == SYS_RES_MEMORY && mapsize < 4) || 3215 (type == SYS_RES_IOPORT && mapsize < 2)) 3216 return (barlen); 3217 3218 /* Save a record of this BAR. */ 3219 pm = pci_add_bar(dev, reg, map, mapsize); 3220 if (bootverbose) { 3221 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d", 3222 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize); 3223 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3224 printf(", port disabled\n"); 3225 else if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3226 printf(", memory disabled\n"); 3227 else 3228 printf(", enabled\n"); 3229 } 3230 3231 /* 3232 * If base is 0, then we have problems if this architecture does 3233 * not allow that. It is best to ignore such entries for the 3234 * moment. These will be allocated later if the driver specifically 3235 * requests them. However, some removable buses look better when 3236 * all resources are allocated, so allow '0' to be overriden. 3237 * 3238 * Similarly treat maps whose values is the same as the test value 3239 * read back. These maps have had all f's written to them by the 3240 * BIOS in an attempt to disable the resources. 3241 */ 3242 if (!force && (basezero || map == testval)) 3243 return (barlen); 3244 if ((u_long)base != base) { 3245 device_printf(bus, 3246 "pci%d:%d:%d:%d bar %#x too many address bits", 3247 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev), 3248 pci_get_function(dev), reg); 3249 return (barlen); 3250 } 3251 3252 /* 3253 * This code theoretically does the right thing, but has 3254 * undesirable side effects in some cases where peripherals 3255 * respond oddly to having these bits enabled. Let the user 3256 * be able to turn them off (since pci_enable_io_modes is 1 by 3257 * default). 3258 */ 3259 if (pci_enable_io_modes) { 3260 /* Turn on resources that have been left off by a lazy BIOS */ 3261 if (type == SYS_RES_IOPORT && !pci_porten(dev)) { 3262 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3263 cmd |= PCIM_CMD_PORTEN; 3264 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3265 } 3266 if (type == SYS_RES_MEMORY && !pci_memen(dev)) { 3267 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3268 cmd |= PCIM_CMD_MEMEN; 3269 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3270 } 3271 } else { 3272 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3273 return (barlen); 3274 if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3275 return (barlen); 3276 } 3277 3278 count = (pci_addr_t)1 << mapsize; 3279 flags = RF_ALIGNMENT_LOG2(mapsize); 3280 if (prefetch) 3281 flags |= RF_PREFETCHABLE; 3282 if (basezero || base == pci_mapbase(testval) || pci_clear_bars) { 3283 start = 0; /* Let the parent decide. */ 3284 end = ~0; 3285 } else { 3286 start = base; 3287 end = base + count - 1; 3288 } 3289 resource_list_add(rl, type, reg, start, end, count); 3290 3291 /* 3292 * Try to allocate the resource for this BAR from our parent 3293 * so that this resource range is already reserved. The 3294 * driver for this device will later inherit this resource in 3295 * pci_alloc_resource(). 3296 */ 3297 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count, 3298 flags); 3299 if ((pci_do_realloc_bars 3300 || pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_REALLOC_BAR)) 3301 && res == NULL && (start != 0 || end != ~0)) { 3302 /* 3303 * If the allocation fails, try to allocate a resource for 3304 * this BAR using any available range. The firmware felt 3305 * it was important enough to assign a resource, so don't 3306 * disable decoding if we can help it. 3307 */ 3308 resource_list_delete(rl, type, reg); 3309 resource_list_add(rl, type, reg, 0, ~0, count); 3310 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0, 3311 count, flags); 3312 } 3313 if (res == NULL) { 3314 /* 3315 * If the allocation fails, delete the resource list entry 3316 * and disable decoding for this device. 3317 * 3318 * If the driver requests this resource in the future, 3319 * pci_reserve_map() will try to allocate a fresh 3320 * resource range. 3321 */ 3322 resource_list_delete(rl, type, reg); 3323 pci_disable_io(dev, type); 3324 if (bootverbose) 3325 device_printf(bus, 3326 "pci%d:%d:%d:%d bar %#x failed to allocate\n", 3327 pci_get_domain(dev), pci_get_bus(dev), 3328 pci_get_slot(dev), pci_get_function(dev), reg); 3329 } else { 3330 start = rman_get_start(res); 3331 pci_write_bar(dev, pm, start); 3332 } 3333 return (barlen); 3334 } 3335 3336 /* 3337 * For ATA devices we need to decide early what addressing mode to use. 3338 * Legacy demands that the primary and secondary ATA ports sits on the 3339 * same addresses that old ISA hardware did. This dictates that we use 3340 * those addresses and ignore the BAR's if we cannot set PCI native 3341 * addressing mode. 3342 */ 3343 static void 3344 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force, 3345 uint32_t prefetchmask) 3346 { 3347 int rid, type, progif; 3348 #if 0 3349 /* if this device supports PCI native addressing use it */ 3350 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3351 if ((progif & 0x8a) == 0x8a) { 3352 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 3353 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 3354 printf("Trying ATA native PCI addressing mode\n"); 3355 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 3356 } 3357 } 3358 #endif 3359 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3360 type = SYS_RES_IOPORT; 3361 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 3362 pci_add_map(bus, dev, PCIR_BAR(0), rl, force, 3363 prefetchmask & (1 << 0)); 3364 pci_add_map(bus, dev, PCIR_BAR(1), rl, force, 3365 prefetchmask & (1 << 1)); 3366 } else { 3367 rid = PCIR_BAR(0); 3368 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 3369 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0, 3370 0x1f7, 8, 0); 3371 rid = PCIR_BAR(1); 3372 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 3373 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6, 3374 0x3f6, 1, 0); 3375 } 3376 if (progif & PCIP_STORAGE_IDE_MODESEC) { 3377 pci_add_map(bus, dev, PCIR_BAR(2), rl, force, 3378 prefetchmask & (1 << 2)); 3379 pci_add_map(bus, dev, PCIR_BAR(3), rl, force, 3380 prefetchmask & (1 << 3)); 3381 } else { 3382 rid = PCIR_BAR(2); 3383 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 3384 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x170, 3385 0x177, 8, 0); 3386 rid = PCIR_BAR(3); 3387 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 3388 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x376, 3389 0x376, 1, 0); 3390 } 3391 pci_add_map(bus, dev, PCIR_BAR(4), rl, force, 3392 prefetchmask & (1 << 4)); 3393 pci_add_map(bus, dev, PCIR_BAR(5), rl, force, 3394 prefetchmask & (1 << 5)); 3395 } 3396 3397 static void 3398 pci_assign_interrupt(device_t bus, device_t dev, int force_route) 3399 { 3400 struct pci_devinfo *dinfo = device_get_ivars(dev); 3401 pcicfgregs *cfg = &dinfo->cfg; 3402 char tunable_name[64]; 3403 int irq; 3404 3405 /* Has to have an intpin to have an interrupt. */ 3406 if (cfg->intpin == 0) 3407 return; 3408 3409 /* Let the user override the IRQ with a tunable. */ 3410 irq = PCI_INVALID_IRQ; 3411 snprintf(tunable_name, sizeof(tunable_name), 3412 "hw.pci%d.%d.%d.INT%c.irq", 3413 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 3414 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 3415 irq = PCI_INVALID_IRQ; 3416 3417 /* 3418 * If we didn't get an IRQ via the tunable, then we either use the 3419 * IRQ value in the intline register or we ask the bus to route an 3420 * interrupt for us. If force_route is true, then we only use the 3421 * value in the intline register if the bus was unable to assign an 3422 * IRQ. 3423 */ 3424 if (!PCI_INTERRUPT_VALID(irq)) { 3425 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 3426 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 3427 if (!PCI_INTERRUPT_VALID(irq)) 3428 irq = cfg->intline; 3429 } 3430 3431 /* If after all that we don't have an IRQ, just bail. */ 3432 if (!PCI_INTERRUPT_VALID(irq)) 3433 return; 3434 3435 /* Update the config register if it changed. */ 3436 if (irq != cfg->intline) { 3437 cfg->intline = irq; 3438 pci_write_config(dev, PCIR_INTLINE, irq, 1); 3439 } 3440 3441 /* Add this IRQ as rid 0 interrupt resource. */ 3442 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 3443 } 3444 3445 /* Perform early OHCI takeover from SMM. */ 3446 static void 3447 ohci_early_takeover(device_t self) 3448 { 3449 struct resource *res; 3450 uint32_t ctl; 3451 int rid; 3452 int i; 3453 3454 rid = PCIR_BAR(0); 3455 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3456 if (res == NULL) 3457 return; 3458 3459 ctl = bus_read_4(res, OHCI_CONTROL); 3460 if (ctl & OHCI_IR) { 3461 if (bootverbose) 3462 printf("ohci early: " 3463 "SMM active, request owner change\n"); 3464 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR); 3465 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 3466 DELAY(1000); 3467 ctl = bus_read_4(res, OHCI_CONTROL); 3468 } 3469 if (ctl & OHCI_IR) { 3470 if (bootverbose) 3471 printf("ohci early: " 3472 "SMM does not respond, resetting\n"); 3473 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET); 3474 } 3475 /* Disable interrupts */ 3476 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 3477 } 3478 3479 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3480 } 3481 3482 /* Perform early UHCI takeover from SMM. */ 3483 static void 3484 uhci_early_takeover(device_t self) 3485 { 3486 struct resource *res; 3487 int rid; 3488 3489 /* 3490 * Set the PIRQD enable bit and switch off all the others. We don't 3491 * want legacy support to interfere with us XXX Does this also mean 3492 * that the BIOS won't touch the keyboard anymore if it is connected 3493 * to the ports of the root hub? 3494 */ 3495 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2); 3496 3497 /* Disable interrupts */ 3498 rid = PCI_UHCI_BASE_REG; 3499 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE); 3500 if (res != NULL) { 3501 bus_write_2(res, UHCI_INTR, 0); 3502 bus_release_resource(self, SYS_RES_IOPORT, rid, res); 3503 } 3504 } 3505 3506 /* Perform early EHCI takeover from SMM. */ 3507 static void 3508 ehci_early_takeover(device_t self) 3509 { 3510 struct resource *res; 3511 uint32_t cparams; 3512 uint32_t eec; 3513 uint8_t eecp; 3514 uint8_t bios_sem; 3515 uint8_t offs; 3516 int rid; 3517 int i; 3518 3519 rid = PCIR_BAR(0); 3520 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3521 if (res == NULL) 3522 return; 3523 3524 cparams = bus_read_4(res, EHCI_HCCPARAMS); 3525 3526 /* Synchronise with the BIOS if it owns the controller. */ 3527 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0; 3528 eecp = EHCI_EECP_NEXT(eec)) { 3529 eec = pci_read_config(self, eecp, 4); 3530 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) { 3531 continue; 3532 } 3533 bios_sem = pci_read_config(self, eecp + 3534 EHCI_LEGSUP_BIOS_SEM, 1); 3535 if (bios_sem == 0) { 3536 continue; 3537 } 3538 if (bootverbose) 3539 printf("ehci early: " 3540 "SMM active, request owner change\n"); 3541 3542 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1); 3543 3544 for (i = 0; (i < 100) && (bios_sem != 0); i++) { 3545 DELAY(1000); 3546 bios_sem = pci_read_config(self, eecp + 3547 EHCI_LEGSUP_BIOS_SEM, 1); 3548 } 3549 3550 if (bios_sem != 0) { 3551 if (bootverbose) 3552 printf("ehci early: " 3553 "SMM does not respond\n"); 3554 } 3555 /* Disable interrupts */ 3556 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION)); 3557 bus_write_4(res, offs + EHCI_USBINTR, 0); 3558 } 3559 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3560 } 3561 3562 /* Perform early XHCI takeover from SMM. */ 3563 static void 3564 xhci_early_takeover(device_t self) 3565 { 3566 struct resource *res; 3567 uint32_t cparams; 3568 uint32_t eec; 3569 uint8_t eecp; 3570 uint8_t bios_sem; 3571 uint8_t offs; 3572 int rid; 3573 int i; 3574 3575 rid = PCIR_BAR(0); 3576 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3577 if (res == NULL) 3578 return; 3579 3580 cparams = bus_read_4(res, XHCI_HCSPARAMS0); 3581 3582 eec = -1; 3583 3584 /* Synchronise with the BIOS if it owns the controller. */ 3585 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 3586 eecp += XHCI_XECP_NEXT(eec) << 2) { 3587 eec = bus_read_4(res, eecp); 3588 3589 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 3590 continue; 3591 3592 bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM); 3593 if (bios_sem == 0) 3594 continue; 3595 3596 if (bootverbose) 3597 printf("xhci early: " 3598 "SMM active, request owner change\n"); 3599 3600 bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1); 3601 3602 /* wait a maximum of 5 second */ 3603 3604 for (i = 0; (i < 5000) && (bios_sem != 0); i++) { 3605 DELAY(1000); 3606 bios_sem = bus_read_1(res, eecp + 3607 XHCI_XECP_BIOS_SEM); 3608 } 3609 3610 if (bios_sem != 0) { 3611 if (bootverbose) 3612 printf("xhci early: " 3613 "SMM does not respond\n"); 3614 } 3615 3616 /* Disable interrupts */ 3617 offs = bus_read_1(res, XHCI_CAPLENGTH); 3618 bus_write_4(res, offs + XHCI_USBCMD, 0); 3619 bus_read_4(res, offs + XHCI_USBSTS); 3620 } 3621 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3622 } 3623 3624 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 3625 static void 3626 pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg, 3627 struct resource_list *rl) 3628 { 3629 struct resource *res; 3630 char *cp; 3631 rman_res_t start, end, count; 3632 int rid, sec_bus, sec_reg, sub_bus, sub_reg, sup_bus; 3633 3634 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3635 case PCIM_HDRTYPE_BRIDGE: 3636 sec_reg = PCIR_SECBUS_1; 3637 sub_reg = PCIR_SUBBUS_1; 3638 break; 3639 case PCIM_HDRTYPE_CARDBUS: 3640 sec_reg = PCIR_SECBUS_2; 3641 sub_reg = PCIR_SUBBUS_2; 3642 break; 3643 default: 3644 return; 3645 } 3646 3647 /* 3648 * If the existing bus range is valid, attempt to reserve it 3649 * from our parent. If this fails for any reason, clear the 3650 * secbus and subbus registers. 3651 * 3652 * XXX: Should we reset sub_bus to sec_bus if it is < sec_bus? 3653 * This would at least preserve the existing sec_bus if it is 3654 * valid. 3655 */ 3656 sec_bus = PCI_READ_CONFIG(bus, dev, sec_reg, 1); 3657 sub_bus = PCI_READ_CONFIG(bus, dev, sub_reg, 1); 3658 3659 /* Quirk handling. */ 3660 switch (pci_get_devid(dev)) { 3661 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 3662 sup_bus = pci_read_config(dev, 0x41, 1); 3663 if (sup_bus != 0xff) { 3664 sec_bus = sup_bus + 1; 3665 sub_bus = sup_bus + 1; 3666 PCI_WRITE_CONFIG(bus, dev, sec_reg, sec_bus, 1); 3667 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3668 } 3669 break; 3670 3671 case 0x00dd10de: 3672 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 3673 if ((cp = kern_getenv("smbios.planar.maker")) == NULL) 3674 break; 3675 if (strncmp(cp, "Compal", 6) != 0) { 3676 freeenv(cp); 3677 break; 3678 } 3679 freeenv(cp); 3680 if ((cp = kern_getenv("smbios.planar.product")) == NULL) 3681 break; 3682 if (strncmp(cp, "08A0", 4) != 0) { 3683 freeenv(cp); 3684 break; 3685 } 3686 freeenv(cp); 3687 if (sub_bus < 0xa) { 3688 sub_bus = 0xa; 3689 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3690 } 3691 break; 3692 } 3693 3694 if (bootverbose) 3695 printf("\tsecbus=%d, subbus=%d\n", sec_bus, sub_bus); 3696 if (sec_bus > 0 && sub_bus >= sec_bus) { 3697 start = sec_bus; 3698 end = sub_bus; 3699 count = end - start + 1; 3700 3701 resource_list_add(rl, PCI_RES_BUS, 0, 0, ~0, count); 3702 3703 /* 3704 * If requested, clear secondary bus registers in 3705 * bridge devices to force a complete renumbering 3706 * rather than reserving the existing range. However, 3707 * preserve the existing size. 3708 */ 3709 if (pci_clear_buses) 3710 goto clear; 3711 3712 rid = 0; 3713 res = resource_list_reserve(rl, bus, dev, PCI_RES_BUS, &rid, 3714 start, end, count, 0); 3715 if (res != NULL) 3716 return; 3717 3718 if (bootverbose) 3719 device_printf(bus, 3720 "pci%d:%d:%d:%d secbus failed to allocate\n", 3721 pci_get_domain(dev), pci_get_bus(dev), 3722 pci_get_slot(dev), pci_get_function(dev)); 3723 } 3724 3725 clear: 3726 PCI_WRITE_CONFIG(bus, dev, sec_reg, 0, 1); 3727 PCI_WRITE_CONFIG(bus, dev, sub_reg, 0, 1); 3728 } 3729 3730 static struct resource * 3731 pci_alloc_secbus(device_t dev, device_t child, int *rid, rman_res_t start, 3732 rman_res_t end, rman_res_t count, u_int flags) 3733 { 3734 struct pci_devinfo *dinfo; 3735 pcicfgregs *cfg; 3736 struct resource_list *rl; 3737 struct resource *res; 3738 int sec_reg, sub_reg; 3739 3740 dinfo = device_get_ivars(child); 3741 cfg = &dinfo->cfg; 3742 rl = &dinfo->resources; 3743 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3744 case PCIM_HDRTYPE_BRIDGE: 3745 sec_reg = PCIR_SECBUS_1; 3746 sub_reg = PCIR_SUBBUS_1; 3747 break; 3748 case PCIM_HDRTYPE_CARDBUS: 3749 sec_reg = PCIR_SECBUS_2; 3750 sub_reg = PCIR_SUBBUS_2; 3751 break; 3752 default: 3753 return (NULL); 3754 } 3755 3756 if (*rid != 0) 3757 return (NULL); 3758 3759 if (resource_list_find(rl, PCI_RES_BUS, *rid) == NULL) 3760 resource_list_add(rl, PCI_RES_BUS, *rid, start, end, count); 3761 if (!resource_list_reserved(rl, PCI_RES_BUS, *rid)) { 3762 res = resource_list_reserve(rl, dev, child, PCI_RES_BUS, rid, 3763 start, end, count, flags & ~RF_ACTIVE); 3764 if (res == NULL) { 3765 resource_list_delete(rl, PCI_RES_BUS, *rid); 3766 device_printf(child, "allocating %ju bus%s failed\n", 3767 count, count == 1 ? "" : "es"); 3768 return (NULL); 3769 } 3770 if (bootverbose) 3771 device_printf(child, 3772 "Lazy allocation of %ju bus%s at %ju\n", count, 3773 count == 1 ? "" : "es", rman_get_start(res)); 3774 PCI_WRITE_CONFIG(dev, child, sec_reg, rman_get_start(res), 1); 3775 PCI_WRITE_CONFIG(dev, child, sub_reg, rman_get_end(res), 1); 3776 } 3777 return (resource_list_alloc(rl, dev, child, PCI_RES_BUS, rid, start, 3778 end, count, flags)); 3779 } 3780 #endif 3781 3782 static int 3783 pci_ea_bei_to_rid(device_t dev, int bei) 3784 { 3785 #ifdef PCI_IOV 3786 struct pci_devinfo *dinfo; 3787 int iov_pos; 3788 struct pcicfg_iov *iov; 3789 3790 dinfo = device_get_ivars(dev); 3791 iov = dinfo->cfg.iov; 3792 if (iov != NULL) 3793 iov_pos = iov->iov_pos; 3794 else 3795 iov_pos = 0; 3796 #endif 3797 3798 /* Check if matches BAR */ 3799 if ((bei >= PCIM_EA_BEI_BAR_0) && 3800 (bei <= PCIM_EA_BEI_BAR_5)) 3801 return (PCIR_BAR(bei)); 3802 3803 /* Check ROM */ 3804 if (bei == PCIM_EA_BEI_ROM) 3805 return (PCIR_BIOS); 3806 3807 #ifdef PCI_IOV 3808 /* Check if matches VF_BAR */ 3809 if ((iov != NULL) && (bei >= PCIM_EA_BEI_VF_BAR_0) && 3810 (bei <= PCIM_EA_BEI_VF_BAR_5)) 3811 return (PCIR_SRIOV_BAR(bei - PCIM_EA_BEI_VF_BAR_0) + 3812 iov_pos); 3813 #endif 3814 3815 return (-1); 3816 } 3817 3818 int 3819 pci_ea_is_enabled(device_t dev, int rid) 3820 { 3821 struct pci_ea_entry *ea; 3822 struct pci_devinfo *dinfo; 3823 3824 dinfo = device_get_ivars(dev); 3825 3826 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 3827 if (pci_ea_bei_to_rid(dev, ea->eae_bei) == rid) 3828 return ((ea->eae_flags & PCIM_EA_ENABLE) > 0); 3829 } 3830 3831 return (0); 3832 } 3833 3834 void 3835 pci_add_resources_ea(device_t bus, device_t dev, int alloc_iov) 3836 { 3837 struct pci_ea_entry *ea; 3838 struct pci_devinfo *dinfo; 3839 pci_addr_t start, end, count; 3840 struct resource_list *rl; 3841 int type, flags, rid; 3842 struct resource *res; 3843 uint32_t tmp; 3844 #ifdef PCI_IOV 3845 struct pcicfg_iov *iov; 3846 #endif 3847 3848 dinfo = device_get_ivars(dev); 3849 rl = &dinfo->resources; 3850 flags = 0; 3851 3852 #ifdef PCI_IOV 3853 iov = dinfo->cfg.iov; 3854 #endif 3855 3856 if (dinfo->cfg.ea.ea_location == 0) 3857 return; 3858 3859 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 3860 3861 /* 3862 * TODO: Ignore EA-BAR if is not enabled. 3863 * Currently the EA implementation supports 3864 * only situation, where EA structure contains 3865 * predefined entries. In case they are not enabled 3866 * leave them unallocated and proceed with 3867 * a legacy-BAR mechanism. 3868 */ 3869 if ((ea->eae_flags & PCIM_EA_ENABLE) == 0) 3870 continue; 3871 3872 switch ((ea->eae_flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET) { 3873 case PCIM_EA_P_MEM_PREFETCH: 3874 case PCIM_EA_P_VF_MEM_PREFETCH: 3875 flags = RF_PREFETCHABLE; 3876 /* FALLTHROUGH */ 3877 case PCIM_EA_P_VF_MEM: 3878 case PCIM_EA_P_MEM: 3879 type = SYS_RES_MEMORY; 3880 break; 3881 case PCIM_EA_P_IO: 3882 type = SYS_RES_IOPORT; 3883 break; 3884 default: 3885 continue; 3886 } 3887 3888 if (alloc_iov != 0) { 3889 #ifdef PCI_IOV 3890 /* Allocating IOV, confirm BEI matches */ 3891 if ((ea->eae_bei < PCIM_EA_BEI_VF_BAR_0) || 3892 (ea->eae_bei > PCIM_EA_BEI_VF_BAR_5)) 3893 continue; 3894 #else 3895 continue; 3896 #endif 3897 } else { 3898 /* Allocating BAR, confirm BEI matches */ 3899 if (((ea->eae_bei < PCIM_EA_BEI_BAR_0) || 3900 (ea->eae_bei > PCIM_EA_BEI_BAR_5)) && 3901 (ea->eae_bei != PCIM_EA_BEI_ROM)) 3902 continue; 3903 } 3904 3905 rid = pci_ea_bei_to_rid(dev, ea->eae_bei); 3906 if (rid < 0) 3907 continue; 3908 3909 /* Skip resources already allocated by EA */ 3910 if ((resource_list_find(rl, SYS_RES_MEMORY, rid) != NULL) || 3911 (resource_list_find(rl, SYS_RES_IOPORT, rid) != NULL)) 3912 continue; 3913 3914 start = ea->eae_base; 3915 count = ea->eae_max_offset + 1; 3916 #ifdef PCI_IOV 3917 if (iov != NULL) 3918 count = count * iov->iov_num_vfs; 3919 #endif 3920 end = start + count - 1; 3921 if (count == 0) 3922 continue; 3923 3924 resource_list_add(rl, type, rid, start, end, count); 3925 res = resource_list_reserve(rl, bus, dev, type, &rid, start, end, count, 3926 flags); 3927 if (res == NULL) { 3928 resource_list_delete(rl, type, rid); 3929 3930 /* 3931 * Failed to allocate using EA, disable entry. 3932 * Another attempt to allocation will be performed 3933 * further, but this time using legacy BAR registers 3934 */ 3935 tmp = pci_read_config(dev, ea->eae_cfg_offset, 4); 3936 tmp &= ~PCIM_EA_ENABLE; 3937 pci_write_config(dev, ea->eae_cfg_offset, tmp, 4); 3938 3939 /* 3940 * Disabling entry might fail in case it is hardwired. 3941 * Read flags again to match current status. 3942 */ 3943 ea->eae_flags = pci_read_config(dev, ea->eae_cfg_offset, 4); 3944 3945 continue; 3946 } 3947 3948 /* As per specification, fill BAR with zeros */ 3949 pci_write_config(dev, rid, 0, 4); 3950 } 3951 } 3952 3953 void 3954 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 3955 { 3956 struct pci_devinfo *dinfo; 3957 pcicfgregs *cfg; 3958 struct resource_list *rl; 3959 const struct pci_quirk *q; 3960 uint32_t devid; 3961 int i; 3962 3963 dinfo = device_get_ivars(dev); 3964 cfg = &dinfo->cfg; 3965 rl = &dinfo->resources; 3966 devid = (cfg->device << 16) | cfg->vendor; 3967 3968 /* Allocate resources using Enhanced Allocation */ 3969 pci_add_resources_ea(bus, dev, 0); 3970 3971 /* ATA devices needs special map treatment */ 3972 if ((pci_get_class(dev) == PCIC_STORAGE) && 3973 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 3974 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) || 3975 (!pci_read_config(dev, PCIR_BAR(0), 4) && 3976 !pci_read_config(dev, PCIR_BAR(2), 4))) ) 3977 pci_ata_maps(bus, dev, rl, force, prefetchmask); 3978 else 3979 for (i = 0; i < cfg->nummaps;) { 3980 /* Skip resources already managed by EA */ 3981 if ((resource_list_find(rl, SYS_RES_MEMORY, PCIR_BAR(i)) != NULL) || 3982 (resource_list_find(rl, SYS_RES_IOPORT, PCIR_BAR(i)) != NULL) || 3983 pci_ea_is_enabled(dev, PCIR_BAR(i))) { 3984 i++; 3985 continue; 3986 } 3987 3988 /* 3989 * Skip quirked resources. 3990 */ 3991 for (q = &pci_quirks[0]; q->devid != 0; q++) 3992 if (q->devid == devid && 3993 q->type == PCI_QUIRK_UNMAP_REG && 3994 q->arg1 == PCIR_BAR(i)) 3995 break; 3996 if (q->devid != 0) { 3997 i++; 3998 continue; 3999 } 4000 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force, 4001 prefetchmask & (1 << i)); 4002 } 4003 4004 /* 4005 * Add additional, quirked resources. 4006 */ 4007 for (q = &pci_quirks[0]; q->devid != 0; q++) 4008 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG) 4009 pci_add_map(bus, dev, q->arg1, rl, force, 0); 4010 4011 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 4012 #ifdef __PCI_REROUTE_INTERRUPT 4013 /* 4014 * Try to re-route interrupts. Sometimes the BIOS or 4015 * firmware may leave bogus values in these registers. 4016 * If the re-route fails, then just stick with what we 4017 * have. 4018 */ 4019 pci_assign_interrupt(bus, dev, 1); 4020 #else 4021 pci_assign_interrupt(bus, dev, 0); 4022 #endif 4023 } 4024 4025 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS && 4026 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) { 4027 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI) 4028 xhci_early_takeover(dev); 4029 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI) 4030 ehci_early_takeover(dev); 4031 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI) 4032 ohci_early_takeover(dev); 4033 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI) 4034 uhci_early_takeover(dev); 4035 } 4036 4037 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 4038 /* 4039 * Reserve resources for secondary bus ranges behind bridge 4040 * devices. 4041 */ 4042 pci_reserve_secbus(bus, dev, cfg, rl); 4043 #endif 4044 } 4045 4046 static struct pci_devinfo * 4047 pci_identify_function(device_t pcib, device_t dev, int domain, int busno, 4048 int slot, int func) 4049 { 4050 struct pci_devinfo *dinfo; 4051 4052 dinfo = pci_read_device(pcib, dev, domain, busno, slot, func); 4053 if (dinfo != NULL) 4054 pci_add_child(dev, dinfo); 4055 4056 return (dinfo); 4057 } 4058 4059 void 4060 pci_add_children(device_t dev, int domain, int busno) 4061 { 4062 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4063 device_t pcib = device_get_parent(dev); 4064 struct pci_devinfo *dinfo; 4065 int maxslots; 4066 int s, f, pcifunchigh; 4067 uint8_t hdrtype; 4068 int first_func; 4069 4070 /* 4071 * Try to detect a device at slot 0, function 0. If it exists, try to 4072 * enable ARI. We must enable ARI before detecting the rest of the 4073 * functions on this bus as ARI changes the set of slots and functions 4074 * that are legal on this bus. 4075 */ 4076 dinfo = pci_identify_function(pcib, dev, domain, busno, 0, 0); 4077 if (dinfo != NULL && pci_enable_ari) 4078 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev); 4079 4080 /* 4081 * Start looking for new devices on slot 0 at function 1 because we 4082 * just identified the device at slot 0, function 0. 4083 */ 4084 first_func = 1; 4085 4086 maxslots = PCIB_MAXSLOTS(pcib); 4087 for (s = 0; s <= maxslots; s++, first_func = 0) { 4088 pcifunchigh = 0; 4089 f = 0; 4090 DELAY(1); 4091 hdrtype = REG(PCIR_HDRTYPE, 1); 4092 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4093 continue; 4094 if (hdrtype & PCIM_MFDEV) 4095 pcifunchigh = PCIB_MAXFUNCS(pcib); 4096 for (f = first_func; f <= pcifunchigh; f++) 4097 pci_identify_function(pcib, dev, domain, busno, s, f); 4098 } 4099 #undef REG 4100 } 4101 4102 int 4103 pci_rescan_method(device_t dev) 4104 { 4105 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4106 device_t pcib = device_get_parent(dev); 4107 device_t child, *devlist, *unchanged; 4108 int devcount, error, i, j, maxslots, oldcount; 4109 int busno, domain, s, f, pcifunchigh; 4110 uint8_t hdrtype; 4111 4112 /* No need to check for ARI on a rescan. */ 4113 error = device_get_children(dev, &devlist, &devcount); 4114 if (error) 4115 return (error); 4116 if (devcount != 0) { 4117 unchanged = malloc(devcount * sizeof(device_t), M_TEMP, 4118 M_NOWAIT | M_ZERO); 4119 if (unchanged == NULL) { 4120 free(devlist, M_TEMP); 4121 return (ENOMEM); 4122 } 4123 } else 4124 unchanged = NULL; 4125 4126 domain = pcib_get_domain(dev); 4127 busno = pcib_get_bus(dev); 4128 maxslots = PCIB_MAXSLOTS(pcib); 4129 for (s = 0; s <= maxslots; s++) { 4130 /* If function 0 is not present, skip to the next slot. */ 4131 f = 0; 4132 if (REG(PCIR_VENDOR, 2) == 0xffff) 4133 continue; 4134 pcifunchigh = 0; 4135 hdrtype = REG(PCIR_HDRTYPE, 1); 4136 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4137 continue; 4138 if (hdrtype & PCIM_MFDEV) 4139 pcifunchigh = PCIB_MAXFUNCS(pcib); 4140 for (f = 0; f <= pcifunchigh; f++) { 4141 if (REG(PCIR_VENDOR, 2) == 0xffff) 4142 continue; 4143 4144 /* 4145 * Found a valid function. Check if a 4146 * device_t for this device already exists. 4147 */ 4148 for (i = 0; i < devcount; i++) { 4149 child = devlist[i]; 4150 if (child == NULL) 4151 continue; 4152 if (pci_get_slot(child) == s && 4153 pci_get_function(child) == f) { 4154 unchanged[i] = child; 4155 goto next_func; 4156 } 4157 } 4158 4159 pci_identify_function(pcib, dev, domain, busno, s, f); 4160 next_func:; 4161 } 4162 } 4163 4164 /* Remove devices that are no longer present. */ 4165 for (i = 0; i < devcount; i++) { 4166 if (unchanged[i] != NULL) 4167 continue; 4168 device_delete_child(dev, devlist[i]); 4169 } 4170 4171 free(devlist, M_TEMP); 4172 oldcount = devcount; 4173 4174 /* Try to attach the devices just added. */ 4175 error = device_get_children(dev, &devlist, &devcount); 4176 if (error) { 4177 free(unchanged, M_TEMP); 4178 return (error); 4179 } 4180 4181 for (i = 0; i < devcount; i++) { 4182 for (j = 0; j < oldcount; j++) { 4183 if (devlist[i] == unchanged[j]) 4184 goto next_device; 4185 } 4186 4187 device_probe_and_attach(devlist[i]); 4188 next_device:; 4189 } 4190 4191 free(unchanged, M_TEMP); 4192 free(devlist, M_TEMP); 4193 return (0); 4194 #undef REG 4195 } 4196 4197 #ifdef PCI_IOV 4198 device_t 4199 pci_add_iov_child(device_t bus, device_t pf, uint16_t rid, uint16_t vid, 4200 uint16_t did) 4201 { 4202 struct pci_devinfo *vf_dinfo; 4203 device_t pcib; 4204 int busno, slot, func; 4205 4206 pcib = device_get_parent(bus); 4207 4208 PCIB_DECODE_RID(pcib, rid, &busno, &slot, &func); 4209 4210 vf_dinfo = pci_fill_devinfo(pcib, bus, pci_get_domain(pcib), busno, 4211 slot, func, vid, did); 4212 4213 vf_dinfo->cfg.flags |= PCICFG_VF; 4214 pci_add_child(bus, vf_dinfo); 4215 4216 return (vf_dinfo->cfg.dev); 4217 } 4218 4219 device_t 4220 pci_create_iov_child_method(device_t bus, device_t pf, uint16_t rid, 4221 uint16_t vid, uint16_t did) 4222 { 4223 4224 return (pci_add_iov_child(bus, pf, rid, vid, did)); 4225 } 4226 #endif 4227 4228 static void 4229 pci_add_child_clear_aer(device_t dev, struct pci_devinfo *dinfo) 4230 { 4231 int aer; 4232 uint32_t r; 4233 uint16_t r2; 4234 4235 if (dinfo->cfg.pcie.pcie_location != 0 && 4236 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) { 4237 r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4238 PCIER_ROOT_CTL, 2); 4239 r2 &= ~(PCIEM_ROOT_CTL_SERR_CORR | 4240 PCIEM_ROOT_CTL_SERR_NONFATAL | PCIEM_ROOT_CTL_SERR_FATAL); 4241 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4242 PCIER_ROOT_CTL, r2, 2); 4243 } 4244 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 4245 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 4246 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 4247 if (r != 0 && bootverbose) { 4248 pci_printf(&dinfo->cfg, 4249 "clearing AER UC 0x%08x -> 0x%08x\n", 4250 r, pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4251 4)); 4252 } 4253 4254 r = pci_read_config(dev, aer + PCIR_AER_UC_MASK, 4); 4255 r &= ~(PCIM_AER_UC_TRAINING_ERROR | 4256 PCIM_AER_UC_DL_PROTOCOL_ERROR | 4257 PCIM_AER_UC_SURPRISE_LINK_DOWN | 4258 PCIM_AER_UC_POISONED_TLP | 4259 PCIM_AER_UC_FC_PROTOCOL_ERROR | 4260 PCIM_AER_UC_COMPLETION_TIMEOUT | 4261 PCIM_AER_UC_COMPLETER_ABORT | 4262 PCIM_AER_UC_UNEXPECTED_COMPLETION | 4263 PCIM_AER_UC_RECEIVER_OVERFLOW | 4264 PCIM_AER_UC_MALFORMED_TLP | 4265 PCIM_AER_UC_ECRC_ERROR | 4266 PCIM_AER_UC_UNSUPPORTED_REQUEST | 4267 PCIM_AER_UC_ACS_VIOLATION | 4268 PCIM_AER_UC_INTERNAL_ERROR | 4269 PCIM_AER_UC_MC_BLOCKED_TLP | 4270 PCIM_AER_UC_ATOMIC_EGRESS_BLK | 4271 PCIM_AER_UC_TLP_PREFIX_BLOCKED); 4272 pci_write_config(dev, aer + PCIR_AER_UC_MASK, r, 4); 4273 4274 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 4275 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 4276 if (r != 0 && bootverbose) { 4277 pci_printf(&dinfo->cfg, 4278 "clearing AER COR 0x%08x -> 0x%08x\n", 4279 r, pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4280 4)); 4281 } 4282 4283 r = pci_read_config(dev, aer + PCIR_AER_COR_MASK, 4); 4284 r &= ~(PCIM_AER_COR_RECEIVER_ERROR | 4285 PCIM_AER_COR_BAD_TLP | 4286 PCIM_AER_COR_BAD_DLLP | 4287 PCIM_AER_COR_REPLAY_ROLLOVER | 4288 PCIM_AER_COR_REPLAY_TIMEOUT | 4289 PCIM_AER_COR_ADVISORY_NF_ERROR | 4290 PCIM_AER_COR_INTERNAL_ERROR | 4291 PCIM_AER_COR_HEADER_LOG_OVFLOW); 4292 pci_write_config(dev, aer + PCIR_AER_COR_MASK, r, 4); 4293 4294 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4295 PCIER_DEVICE_CTL, 2); 4296 r |= PCIEM_CTL_COR_ENABLE | PCIEM_CTL_NFER_ENABLE | 4297 PCIEM_CTL_FER_ENABLE | PCIEM_CTL_URR_ENABLE; 4298 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4299 PCIER_DEVICE_CTL, r, 2); 4300 } 4301 } 4302 4303 void 4304 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 4305 { 4306 device_t dev; 4307 4308 dinfo->cfg.dev = dev = device_add_child(bus, NULL, -1); 4309 device_set_ivars(dev, dinfo); 4310 resource_list_init(&dinfo->resources); 4311 pci_cfg_save(dev, dinfo, 0); 4312 pci_cfg_restore(dev, dinfo); 4313 pci_print_verbose(dinfo); 4314 pci_add_resources(bus, dev, 0, 0); 4315 pci_child_added(dinfo->cfg.dev); 4316 4317 if (pci_clear_aer_on_attach) 4318 pci_add_child_clear_aer(dev, dinfo); 4319 4320 EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev); 4321 } 4322 4323 void 4324 pci_child_added_method(device_t dev, device_t child) 4325 { 4326 4327 } 4328 4329 static int 4330 pci_probe(device_t dev) 4331 { 4332 4333 device_set_desc(dev, "PCI bus"); 4334 4335 /* Allow other subclasses to override this driver. */ 4336 return (BUS_PROBE_GENERIC); 4337 } 4338 4339 int 4340 pci_attach_common(device_t dev) 4341 { 4342 struct pci_softc *sc; 4343 int busno, domain; 4344 #ifdef PCI_RES_BUS 4345 int rid; 4346 #endif 4347 4348 sc = device_get_softc(dev); 4349 domain = pcib_get_domain(dev); 4350 busno = pcib_get_bus(dev); 4351 #ifdef PCI_RES_BUS 4352 rid = 0; 4353 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno, 4354 1, 0); 4355 if (sc->sc_bus == NULL) { 4356 device_printf(dev, "failed to allocate bus number\n"); 4357 return (ENXIO); 4358 } 4359 #endif 4360 if (bootverbose) 4361 device_printf(dev, "domain=%d, physical bus=%d\n", 4362 domain, busno); 4363 sc->sc_dma_tag = bus_get_dma_tag(dev); 4364 return (0); 4365 } 4366 4367 int 4368 pci_attach(device_t dev) 4369 { 4370 int busno, domain, error; 4371 4372 error = pci_attach_common(dev); 4373 if (error) 4374 return (error); 4375 4376 /* 4377 * Since there can be multiple independently numbered PCI 4378 * buses on systems with multiple PCI domains, we can't use 4379 * the unit number to decide which bus we are probing. We ask 4380 * the parent pcib what our domain and bus numbers are. 4381 */ 4382 domain = pcib_get_domain(dev); 4383 busno = pcib_get_bus(dev); 4384 pci_add_children(dev, domain, busno); 4385 return (bus_generic_attach(dev)); 4386 } 4387 4388 int 4389 pci_detach(device_t dev) 4390 { 4391 #ifdef PCI_RES_BUS 4392 struct pci_softc *sc; 4393 #endif 4394 int error; 4395 4396 error = bus_generic_detach(dev); 4397 if (error) 4398 return (error); 4399 #ifdef PCI_RES_BUS 4400 sc = device_get_softc(dev); 4401 error = bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus); 4402 if (error) 4403 return (error); 4404 #endif 4405 return (device_delete_children(dev)); 4406 } 4407 4408 static void 4409 pci_hint_device_unit(device_t dev, device_t child, const char *name, int *unitp) 4410 { 4411 int line, unit; 4412 const char *at; 4413 char me1[24], me2[32]; 4414 uint8_t b, s, f; 4415 uint32_t d; 4416 4417 d = pci_get_domain(child); 4418 b = pci_get_bus(child); 4419 s = pci_get_slot(child); 4420 f = pci_get_function(child); 4421 snprintf(me1, sizeof(me1), "pci%u:%u:%u", b, s, f); 4422 snprintf(me2, sizeof(me2), "pci%u:%u:%u:%u", d, b, s, f); 4423 line = 0; 4424 while (resource_find_dev(&line, name, &unit, "at", NULL) == 0) { 4425 resource_string_value(name, unit, "at", &at); 4426 if (strcmp(at, me1) != 0 && strcmp(at, me2) != 0) 4427 continue; /* No match, try next candidate */ 4428 *unitp = unit; 4429 return; 4430 } 4431 } 4432 4433 static void 4434 pci_set_power_child(device_t dev, device_t child, int state) 4435 { 4436 device_t pcib; 4437 int dstate; 4438 4439 /* 4440 * Set the device to the given state. If the firmware suggests 4441 * a different power state, use it instead. If power management 4442 * is not present, the firmware is responsible for managing 4443 * device power. Skip children who aren't attached since they 4444 * are handled separately. 4445 */ 4446 pcib = device_get_parent(dev); 4447 dstate = state; 4448 if (device_is_attached(child) && 4449 PCIB_POWER_FOR_SLEEP(pcib, child, &dstate) == 0) 4450 pci_set_powerstate(child, dstate); 4451 } 4452 4453 int 4454 pci_suspend_child(device_t dev, device_t child) 4455 { 4456 struct pci_devinfo *dinfo; 4457 struct resource_list_entry *rle; 4458 int error; 4459 4460 dinfo = device_get_ivars(child); 4461 4462 /* 4463 * Save the PCI configuration space for the child and set the 4464 * device in the appropriate power state for this sleep state. 4465 */ 4466 pci_cfg_save(child, dinfo, 0); 4467 4468 /* Suspend devices before potentially powering them down. */ 4469 error = bus_generic_suspend_child(dev, child); 4470 4471 if (error) 4472 return (error); 4473 4474 if (pci_do_power_suspend) { 4475 /* 4476 * Make sure this device's interrupt handler is not invoked 4477 * in the case the device uses a shared interrupt that can 4478 * be raised by some other device. 4479 * This is applicable only to regular (legacy) PCI interrupts 4480 * as MSI/MSI-X interrupts are never shared. 4481 */ 4482 rle = resource_list_find(&dinfo->resources, 4483 SYS_RES_IRQ, 0); 4484 if (rle != NULL && rle->res != NULL) 4485 (void)bus_suspend_intr(child, rle->res); 4486 pci_set_power_child(dev, child, PCI_POWERSTATE_D3); 4487 } 4488 4489 return (0); 4490 } 4491 4492 int 4493 pci_resume_child(device_t dev, device_t child) 4494 { 4495 struct pci_devinfo *dinfo; 4496 struct resource_list_entry *rle; 4497 4498 if (pci_do_power_resume) 4499 pci_set_power_child(dev, child, PCI_POWERSTATE_D0); 4500 4501 dinfo = device_get_ivars(child); 4502 pci_cfg_restore(child, dinfo); 4503 if (!device_is_attached(child)) 4504 pci_cfg_save(child, dinfo, 1); 4505 4506 bus_generic_resume_child(dev, child); 4507 4508 /* 4509 * Allow interrupts only after fully resuming the driver and hardware. 4510 */ 4511 if (pci_do_power_suspend) { 4512 /* See pci_suspend_child for details. */ 4513 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 4514 if (rle != NULL && rle->res != NULL) 4515 (void)bus_resume_intr(child, rle->res); 4516 } 4517 4518 return (0); 4519 } 4520 4521 int 4522 pci_resume(device_t dev) 4523 { 4524 device_t child, *devlist; 4525 int error, i, numdevs; 4526 4527 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0) 4528 return (error); 4529 4530 /* 4531 * Resume critical devices first, then everything else later. 4532 */ 4533 for (i = 0; i < numdevs; i++) { 4534 child = devlist[i]; 4535 switch (pci_get_class(child)) { 4536 case PCIC_DISPLAY: 4537 case PCIC_MEMORY: 4538 case PCIC_BRIDGE: 4539 case PCIC_BASEPERIPH: 4540 BUS_RESUME_CHILD(dev, child); 4541 break; 4542 } 4543 } 4544 for (i = 0; i < numdevs; i++) { 4545 child = devlist[i]; 4546 switch (pci_get_class(child)) { 4547 case PCIC_DISPLAY: 4548 case PCIC_MEMORY: 4549 case PCIC_BRIDGE: 4550 case PCIC_BASEPERIPH: 4551 break; 4552 default: 4553 BUS_RESUME_CHILD(dev, child); 4554 } 4555 } 4556 free(devlist, M_TEMP); 4557 return (0); 4558 } 4559 4560 static void 4561 pci_load_vendor_data(void) 4562 { 4563 caddr_t data; 4564 void *ptr; 4565 size_t sz; 4566 4567 data = preload_search_by_type("pci_vendor_data"); 4568 if (data != NULL) { 4569 ptr = preload_fetch_addr(data); 4570 sz = preload_fetch_size(data); 4571 if (ptr != NULL && sz != 0) { 4572 pci_vendordata = ptr; 4573 pci_vendordata_size = sz; 4574 /* terminate the database */ 4575 pci_vendordata[pci_vendordata_size] = '\n'; 4576 } 4577 } 4578 } 4579 4580 void 4581 pci_driver_added(device_t dev, driver_t *driver) 4582 { 4583 int numdevs; 4584 device_t *devlist; 4585 device_t child; 4586 struct pci_devinfo *dinfo; 4587 int i; 4588 4589 if (bootverbose) 4590 device_printf(dev, "driver added\n"); 4591 DEVICE_IDENTIFY(driver, dev); 4592 if (device_get_children(dev, &devlist, &numdevs) != 0) 4593 return; 4594 for (i = 0; i < numdevs; i++) { 4595 child = devlist[i]; 4596 if (device_get_state(child) != DS_NOTPRESENT) 4597 continue; 4598 dinfo = device_get_ivars(child); 4599 pci_print_verbose(dinfo); 4600 if (bootverbose) 4601 pci_printf(&dinfo->cfg, "reprobing on driver added\n"); 4602 pci_cfg_restore(child, dinfo); 4603 if (device_probe_and_attach(child) != 0) 4604 pci_child_detached(dev, child); 4605 } 4606 free(devlist, M_TEMP); 4607 } 4608 4609 int 4610 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags, 4611 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep) 4612 { 4613 struct pci_devinfo *dinfo; 4614 struct msix_table_entry *mte; 4615 struct msix_vector *mv; 4616 uint64_t addr; 4617 uint32_t data; 4618 void *cookie; 4619 int error, rid; 4620 4621 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr, 4622 arg, &cookie); 4623 if (error) 4624 return (error); 4625 4626 /* If this is not a direct child, just bail out. */ 4627 if (device_get_parent(child) != dev) { 4628 *cookiep = cookie; 4629 return(0); 4630 } 4631 4632 rid = rman_get_rid(irq); 4633 if (rid == 0) { 4634 /* Make sure that INTx is enabled */ 4635 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4636 } else { 4637 /* 4638 * Check to see if the interrupt is MSI or MSI-X. 4639 * Ask our parent to map the MSI and give 4640 * us the address and data register values. 4641 * If we fail for some reason, teardown the 4642 * interrupt handler. 4643 */ 4644 dinfo = device_get_ivars(child); 4645 if (dinfo->cfg.msi.msi_alloc > 0) { 4646 if (dinfo->cfg.msi.msi_addr == 0) { 4647 KASSERT(dinfo->cfg.msi.msi_handlers == 0, 4648 ("MSI has handlers, but vectors not mapped")); 4649 error = PCIB_MAP_MSI(device_get_parent(dev), 4650 child, rman_get_start(irq), &addr, &data); 4651 if (error) 4652 goto bad; 4653 dinfo->cfg.msi.msi_addr = addr; 4654 dinfo->cfg.msi.msi_data = data; 4655 } 4656 if (dinfo->cfg.msi.msi_handlers == 0) 4657 pci_enable_msi(child, dinfo->cfg.msi.msi_addr, 4658 dinfo->cfg.msi.msi_data); 4659 dinfo->cfg.msi.msi_handlers++; 4660 } else { 4661 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4662 ("No MSI or MSI-X interrupts allocated")); 4663 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4664 ("MSI-X index too high")); 4665 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4666 KASSERT(mte->mte_vector != 0, ("no message vector")); 4667 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1]; 4668 KASSERT(mv->mv_irq == rman_get_start(irq), 4669 ("IRQ mismatch")); 4670 if (mv->mv_address == 0) { 4671 KASSERT(mte->mte_handlers == 0, 4672 ("MSI-X table entry has handlers, but vector not mapped")); 4673 error = PCIB_MAP_MSI(device_get_parent(dev), 4674 child, rman_get_start(irq), &addr, &data); 4675 if (error) 4676 goto bad; 4677 mv->mv_address = addr; 4678 mv->mv_data = data; 4679 } 4680 4681 /* 4682 * The MSIX table entry must be made valid by 4683 * incrementing the mte_handlers before 4684 * calling pci_enable_msix() and 4685 * pci_resume_msix(). Else the MSIX rewrite 4686 * table quirk will not work as expected. 4687 */ 4688 mte->mte_handlers++; 4689 if (mte->mte_handlers == 1) { 4690 pci_enable_msix(child, rid - 1, mv->mv_address, 4691 mv->mv_data); 4692 pci_unmask_msix(child, rid - 1); 4693 } 4694 } 4695 4696 /* 4697 * Make sure that INTx is disabled if we are using MSI/MSI-X, 4698 * unless the device is affected by PCI_QUIRK_MSI_INTX_BUG, 4699 * in which case we "enable" INTx so MSI/MSI-X actually works. 4700 */ 4701 if (!pci_has_quirk(pci_get_devid(child), 4702 PCI_QUIRK_MSI_INTX_BUG)) 4703 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4704 else 4705 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4706 bad: 4707 if (error) { 4708 (void)bus_generic_teardown_intr(dev, child, irq, 4709 cookie); 4710 return (error); 4711 } 4712 } 4713 *cookiep = cookie; 4714 return (0); 4715 } 4716 4717 int 4718 pci_teardown_intr(device_t dev, device_t child, struct resource *irq, 4719 void *cookie) 4720 { 4721 struct msix_table_entry *mte; 4722 struct resource_list_entry *rle; 4723 struct pci_devinfo *dinfo; 4724 int error, rid; 4725 4726 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE)) 4727 return (EINVAL); 4728 4729 /* If this isn't a direct child, just bail out */ 4730 if (device_get_parent(child) != dev) 4731 return(bus_generic_teardown_intr(dev, child, irq, cookie)); 4732 4733 rid = rman_get_rid(irq); 4734 if (rid == 0) { 4735 /* Mask INTx */ 4736 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4737 } else { 4738 /* 4739 * Check to see if the interrupt is MSI or MSI-X. If so, 4740 * decrement the appropriate handlers count and mask the 4741 * MSI-X message, or disable MSI messages if the count 4742 * drops to 0. 4743 */ 4744 dinfo = device_get_ivars(child); 4745 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid); 4746 if (rle->res != irq) 4747 return (EINVAL); 4748 if (dinfo->cfg.msi.msi_alloc > 0) { 4749 KASSERT(rid <= dinfo->cfg.msi.msi_alloc, 4750 ("MSI-X index too high")); 4751 if (dinfo->cfg.msi.msi_handlers == 0) 4752 return (EINVAL); 4753 dinfo->cfg.msi.msi_handlers--; 4754 if (dinfo->cfg.msi.msi_handlers == 0) 4755 pci_disable_msi(child); 4756 } else { 4757 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4758 ("No MSI or MSI-X interrupts allocated")); 4759 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4760 ("MSI-X index too high")); 4761 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4762 if (mte->mte_handlers == 0) 4763 return (EINVAL); 4764 mte->mte_handlers--; 4765 if (mte->mte_handlers == 0) 4766 pci_mask_msix(child, rid - 1); 4767 } 4768 } 4769 error = bus_generic_teardown_intr(dev, child, irq, cookie); 4770 if (rid > 0) 4771 KASSERT(error == 0, 4772 ("%s: generic teardown failed for MSI/MSI-X", __func__)); 4773 return (error); 4774 } 4775 4776 int 4777 pci_print_child(device_t dev, device_t child) 4778 { 4779 struct pci_devinfo *dinfo; 4780 struct resource_list *rl; 4781 int retval = 0; 4782 4783 dinfo = device_get_ivars(child); 4784 rl = &dinfo->resources; 4785 4786 retval += bus_print_child_header(dev, child); 4787 4788 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#jx"); 4789 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 4790 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 4791 if (device_get_flags(dev)) 4792 retval += printf(" flags %#x", device_get_flags(dev)); 4793 4794 retval += printf(" at device %d.%d", pci_get_slot(child), 4795 pci_get_function(child)); 4796 4797 retval += bus_print_child_domain(dev, child); 4798 retval += bus_print_child_footer(dev, child); 4799 4800 return (retval); 4801 } 4802 4803 static const struct 4804 { 4805 int class; 4806 int subclass; 4807 int report; /* 0 = bootverbose, 1 = always */ 4808 const char *desc; 4809 } pci_nomatch_tab[] = { 4810 {PCIC_OLD, -1, 1, "old"}, 4811 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"}, 4812 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"}, 4813 {PCIC_STORAGE, -1, 1, "mass storage"}, 4814 {PCIC_STORAGE, PCIS_STORAGE_SCSI, 1, "SCSI"}, 4815 {PCIC_STORAGE, PCIS_STORAGE_IDE, 1, "ATA"}, 4816 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, 1, "floppy disk"}, 4817 {PCIC_STORAGE, PCIS_STORAGE_IPI, 1, "IPI"}, 4818 {PCIC_STORAGE, PCIS_STORAGE_RAID, 1, "RAID"}, 4819 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, 1, "ATA (ADMA)"}, 4820 {PCIC_STORAGE, PCIS_STORAGE_SATA, 1, "SATA"}, 4821 {PCIC_STORAGE, PCIS_STORAGE_SAS, 1, "SAS"}, 4822 {PCIC_STORAGE, PCIS_STORAGE_NVM, 1, "NVM"}, 4823 {PCIC_NETWORK, -1, 1, "network"}, 4824 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, 1, "ethernet"}, 4825 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, 1, "token ring"}, 4826 {PCIC_NETWORK, PCIS_NETWORK_FDDI, 1, "fddi"}, 4827 {PCIC_NETWORK, PCIS_NETWORK_ATM, 1, "ATM"}, 4828 {PCIC_NETWORK, PCIS_NETWORK_ISDN, 1, "ISDN"}, 4829 {PCIC_DISPLAY, -1, 1, "display"}, 4830 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, 1, "VGA"}, 4831 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, 1, "XGA"}, 4832 {PCIC_DISPLAY, PCIS_DISPLAY_3D, 1, "3D"}, 4833 {PCIC_MULTIMEDIA, -1, 1, "multimedia"}, 4834 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, 1, "video"}, 4835 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, 1, "audio"}, 4836 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, 1, "telephony"}, 4837 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, 1, "HDA"}, 4838 {PCIC_MEMORY, -1, 1, "memory"}, 4839 {PCIC_MEMORY, PCIS_MEMORY_RAM, 1, "RAM"}, 4840 {PCIC_MEMORY, PCIS_MEMORY_FLASH, 1, "flash"}, 4841 {PCIC_BRIDGE, -1, 1, "bridge"}, 4842 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"}, 4843 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"}, 4844 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"}, 4845 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"}, 4846 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"}, 4847 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"}, 4848 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"}, 4849 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"}, 4850 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"}, 4851 {PCIC_SIMPLECOMM, -1, 1, "simple comms"}, 4852 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, 1, "UART"}, /* could detect 16550 */ 4853 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, 1, "parallel port"}, 4854 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, 1, "multiport serial"}, 4855 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, 1, "generic modem"}, 4856 {PCIC_BASEPERIPH, -1, 0, "base peripheral"}, 4857 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, 1, "interrupt controller"}, 4858 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, 1, "DMA controller"}, 4859 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, 1, "timer"}, 4860 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, 1, "realtime clock"}, 4861 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"}, 4862 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, 1, "SD host controller"}, 4863 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_IOMMU, 1, "IOMMU"}, 4864 {PCIC_INPUTDEV, -1, 1, "input device"}, 4865 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, 1, "keyboard"}, 4866 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,1, "digitizer"}, 4867 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, 1, "mouse"}, 4868 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, 1, "scanner"}, 4869 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, 1, "gameport"}, 4870 {PCIC_DOCKING, -1, 1, "docking station"}, 4871 {PCIC_PROCESSOR, -1, 1, "processor"}, 4872 {PCIC_SERIALBUS, -1, 1, "serial bus"}, 4873 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, 1, "FireWire"}, 4874 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, 1, "AccessBus"}, 4875 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, 1, "SSA"}, 4876 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, 1, "USB"}, 4877 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, 1, "Fibre Channel"}, 4878 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, 0, "SMBus"}, 4879 {PCIC_WIRELESS, -1, 1, "wireless controller"}, 4880 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, 1, "iRDA"}, 4881 {PCIC_WIRELESS, PCIS_WIRELESS_IR, 1, "IR"}, 4882 {PCIC_WIRELESS, PCIS_WIRELESS_RF, 1, "RF"}, 4883 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"}, 4884 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, 1, "I2O"}, 4885 {PCIC_SATCOM, -1, 1, "satellite communication"}, 4886 {PCIC_SATCOM, PCIS_SATCOM_TV, 1, "sat TV"}, 4887 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, 1, "sat audio"}, 4888 {PCIC_SATCOM, PCIS_SATCOM_VOICE, 1, "sat voice"}, 4889 {PCIC_SATCOM, PCIS_SATCOM_DATA, 1, "sat data"}, 4890 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"}, 4891 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, 1, "network/computer crypto"}, 4892 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, 1, "entertainment crypto"}, 4893 {PCIC_DASP, -1, 0, "dasp"}, 4894 {PCIC_DASP, PCIS_DASP_DPIO, 1, "DPIO module"}, 4895 {PCIC_DASP, PCIS_DASP_PERFCNTRS, 1, "performance counters"}, 4896 {PCIC_DASP, PCIS_DASP_COMM_SYNC, 1, "communication synchronizer"}, 4897 {PCIC_DASP, PCIS_DASP_MGMT_CARD, 1, "signal processing management"}, 4898 {0, 0, 0, NULL} 4899 }; 4900 4901 void 4902 pci_probe_nomatch(device_t dev, device_t child) 4903 { 4904 int i, report; 4905 const char *cp, *scp; 4906 char *device; 4907 4908 /* 4909 * Look for a listing for this device in a loaded device database. 4910 */ 4911 report = 1; 4912 if ((device = pci_describe_device(child)) != NULL) { 4913 device_printf(dev, "<%s>", device); 4914 free(device, M_DEVBUF); 4915 } else { 4916 /* 4917 * Scan the class/subclass descriptions for a general 4918 * description. 4919 */ 4920 cp = "unknown"; 4921 scp = NULL; 4922 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 4923 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 4924 if (pci_nomatch_tab[i].subclass == -1) { 4925 cp = pci_nomatch_tab[i].desc; 4926 report = pci_nomatch_tab[i].report; 4927 } else if (pci_nomatch_tab[i].subclass == 4928 pci_get_subclass(child)) { 4929 scp = pci_nomatch_tab[i].desc; 4930 report = pci_nomatch_tab[i].report; 4931 } 4932 } 4933 } 4934 if (report || bootverbose) { 4935 device_printf(dev, "<%s%s%s>", 4936 cp ? cp : "", 4937 ((cp != NULL) && (scp != NULL)) ? ", " : "", 4938 scp ? scp : ""); 4939 } 4940 } 4941 if (report || bootverbose) { 4942 printf(" at device %d.%d (no driver attached)\n", 4943 pci_get_slot(child), pci_get_function(child)); 4944 } 4945 pci_cfg_save(child, device_get_ivars(child), 1); 4946 } 4947 4948 void 4949 pci_child_detached(device_t dev, device_t child) 4950 { 4951 struct pci_devinfo *dinfo; 4952 struct resource_list *rl; 4953 4954 dinfo = device_get_ivars(child); 4955 rl = &dinfo->resources; 4956 4957 /* 4958 * Have to deallocate IRQs before releasing any MSI messages and 4959 * have to release MSI messages before deallocating any memory 4960 * BARs. 4961 */ 4962 if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0) 4963 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n"); 4964 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) { 4965 pci_printf(&dinfo->cfg, "Device leaked MSI vectors\n"); 4966 (void)pci_release_msi(child); 4967 } 4968 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0) 4969 pci_printf(&dinfo->cfg, "Device leaked memory resources\n"); 4970 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0) 4971 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n"); 4972 #ifdef PCI_RES_BUS 4973 if (resource_list_release_active(rl, dev, child, PCI_RES_BUS) != 0) 4974 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n"); 4975 #endif 4976 4977 pci_cfg_save(child, dinfo, 1); 4978 } 4979 4980 /* 4981 * Parse the PCI device database, if loaded, and return a pointer to a 4982 * description of the device. 4983 * 4984 * The database is flat text formatted as follows: 4985 * 4986 * Any line not in a valid format is ignored. 4987 * Lines are terminated with newline '\n' characters. 4988 * 4989 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 4990 * the vendor name. 4991 * 4992 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 4993 * - devices cannot be listed without a corresponding VENDOR line. 4994 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 4995 * another TAB, then the device name. 4996 */ 4997 4998 /* 4999 * Assuming (ptr) points to the beginning of a line in the database, 5000 * return the vendor or device and description of the next entry. 5001 * The value of (vendor) or (device) inappropriate for the entry type 5002 * is set to -1. Returns nonzero at the end of the database. 5003 * 5004 * Note that this is slightly unrobust in the face of corrupt data; 5005 * we attempt to safeguard against this by spamming the end of the 5006 * database with a newline when we initialise. 5007 */ 5008 static int 5009 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 5010 { 5011 char *cp = *ptr; 5012 int left; 5013 5014 *device = -1; 5015 *vendor = -1; 5016 **desc = '\0'; 5017 for (;;) { 5018 left = pci_vendordata_size - (cp - pci_vendordata); 5019 if (left <= 0) { 5020 *ptr = cp; 5021 return(1); 5022 } 5023 5024 /* vendor entry? */ 5025 if (*cp != '\t' && 5026 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 5027 break; 5028 /* device entry? */ 5029 if (*cp == '\t' && 5030 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 5031 break; 5032 5033 /* skip to next line */ 5034 while (*cp != '\n' && left > 0) { 5035 cp++; 5036 left--; 5037 } 5038 if (*cp == '\n') { 5039 cp++; 5040 left--; 5041 } 5042 } 5043 /* skip to next line */ 5044 while (*cp != '\n' && left > 0) { 5045 cp++; 5046 left--; 5047 } 5048 if (*cp == '\n' && left > 0) 5049 cp++; 5050 *ptr = cp; 5051 return(0); 5052 } 5053 5054 static char * 5055 pci_describe_device(device_t dev) 5056 { 5057 int vendor, device; 5058 char *desc, *vp, *dp, *line; 5059 5060 desc = vp = dp = NULL; 5061 5062 /* 5063 * If we have no vendor data, we can't do anything. 5064 */ 5065 if (pci_vendordata == NULL) 5066 goto out; 5067 5068 /* 5069 * Scan the vendor data looking for this device 5070 */ 5071 line = pci_vendordata; 5072 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5073 goto out; 5074 for (;;) { 5075 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 5076 goto out; 5077 if (vendor == pci_get_vendor(dev)) 5078 break; 5079 } 5080 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5081 goto out; 5082 for (;;) { 5083 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 5084 *dp = 0; 5085 break; 5086 } 5087 if (vendor != -1) { 5088 *dp = 0; 5089 break; 5090 } 5091 if (device == pci_get_device(dev)) 5092 break; 5093 } 5094 if (dp[0] == '\0') 5095 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 5096 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 5097 NULL) 5098 sprintf(desc, "%s, %s", vp, dp); 5099 out: 5100 if (vp != NULL) 5101 free(vp, M_DEVBUF); 5102 if (dp != NULL) 5103 free(dp, M_DEVBUF); 5104 return(desc); 5105 } 5106 5107 int 5108 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 5109 { 5110 struct pci_devinfo *dinfo; 5111 pcicfgregs *cfg; 5112 5113 dinfo = device_get_ivars(child); 5114 cfg = &dinfo->cfg; 5115 5116 switch (which) { 5117 case PCI_IVAR_ETHADDR: 5118 /* 5119 * The generic accessor doesn't deal with failure, so 5120 * we set the return value, then return an error. 5121 */ 5122 *((uint8_t **) result) = NULL; 5123 return (EINVAL); 5124 case PCI_IVAR_SUBVENDOR: 5125 *result = cfg->subvendor; 5126 break; 5127 case PCI_IVAR_SUBDEVICE: 5128 *result = cfg->subdevice; 5129 break; 5130 case PCI_IVAR_VENDOR: 5131 *result = cfg->vendor; 5132 break; 5133 case PCI_IVAR_DEVICE: 5134 *result = cfg->device; 5135 break; 5136 case PCI_IVAR_DEVID: 5137 *result = (cfg->device << 16) | cfg->vendor; 5138 break; 5139 case PCI_IVAR_CLASS: 5140 *result = cfg->baseclass; 5141 break; 5142 case PCI_IVAR_SUBCLASS: 5143 *result = cfg->subclass; 5144 break; 5145 case PCI_IVAR_PROGIF: 5146 *result = cfg->progif; 5147 break; 5148 case PCI_IVAR_REVID: 5149 *result = cfg->revid; 5150 break; 5151 case PCI_IVAR_INTPIN: 5152 *result = cfg->intpin; 5153 break; 5154 case PCI_IVAR_IRQ: 5155 *result = cfg->intline; 5156 break; 5157 case PCI_IVAR_DOMAIN: 5158 *result = cfg->domain; 5159 break; 5160 case PCI_IVAR_BUS: 5161 *result = cfg->bus; 5162 break; 5163 case PCI_IVAR_SLOT: 5164 *result = cfg->slot; 5165 break; 5166 case PCI_IVAR_FUNCTION: 5167 *result = cfg->func; 5168 break; 5169 case PCI_IVAR_CMDREG: 5170 *result = cfg->cmdreg; 5171 break; 5172 case PCI_IVAR_CACHELNSZ: 5173 *result = cfg->cachelnsz; 5174 break; 5175 case PCI_IVAR_MINGNT: 5176 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5177 *result = -1; 5178 return (EINVAL); 5179 } 5180 *result = cfg->mingnt; 5181 break; 5182 case PCI_IVAR_MAXLAT: 5183 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5184 *result = -1; 5185 return (EINVAL); 5186 } 5187 *result = cfg->maxlat; 5188 break; 5189 case PCI_IVAR_LATTIMER: 5190 *result = cfg->lattimer; 5191 break; 5192 default: 5193 return (ENOENT); 5194 } 5195 return (0); 5196 } 5197 5198 int 5199 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 5200 { 5201 struct pci_devinfo *dinfo; 5202 5203 dinfo = device_get_ivars(child); 5204 5205 switch (which) { 5206 case PCI_IVAR_INTPIN: 5207 dinfo->cfg.intpin = value; 5208 return (0); 5209 case PCI_IVAR_ETHADDR: 5210 case PCI_IVAR_SUBVENDOR: 5211 case PCI_IVAR_SUBDEVICE: 5212 case PCI_IVAR_VENDOR: 5213 case PCI_IVAR_DEVICE: 5214 case PCI_IVAR_DEVID: 5215 case PCI_IVAR_CLASS: 5216 case PCI_IVAR_SUBCLASS: 5217 case PCI_IVAR_PROGIF: 5218 case PCI_IVAR_REVID: 5219 case PCI_IVAR_IRQ: 5220 case PCI_IVAR_DOMAIN: 5221 case PCI_IVAR_BUS: 5222 case PCI_IVAR_SLOT: 5223 case PCI_IVAR_FUNCTION: 5224 return (EINVAL); /* disallow for now */ 5225 5226 default: 5227 return (ENOENT); 5228 } 5229 } 5230 5231 #include "opt_ddb.h" 5232 #ifdef DDB 5233 #include <ddb/ddb.h> 5234 #include <sys/cons.h> 5235 5236 /* 5237 * List resources based on pci map registers, used for within ddb 5238 */ 5239 5240 DB_SHOW_COMMAND(pciregs, db_pci_dump) 5241 { 5242 struct pci_devinfo *dinfo; 5243 struct devlist *devlist_head; 5244 struct pci_conf *p; 5245 const char *name; 5246 int i, error, none_count; 5247 5248 none_count = 0; 5249 /* get the head of the device queue */ 5250 devlist_head = &pci_devq; 5251 5252 /* 5253 * Go through the list of devices and print out devices 5254 */ 5255 for (error = 0, i = 0, 5256 dinfo = STAILQ_FIRST(devlist_head); 5257 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 5258 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 5259 5260 /* Populate pd_name and pd_unit */ 5261 name = NULL; 5262 if (dinfo->cfg.dev) 5263 name = device_get_name(dinfo->cfg.dev); 5264 5265 p = &dinfo->conf; 5266 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x " 5267 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 5268 (name && *name) ? name : "none", 5269 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 5270 none_count++, 5271 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev, 5272 p->pc_sel.pc_func, (p->pc_class << 16) | 5273 (p->pc_subclass << 8) | p->pc_progif, 5274 (p->pc_subdevice << 16) | p->pc_subvendor, 5275 (p->pc_device << 16) | p->pc_vendor, 5276 p->pc_revid, p->pc_hdr); 5277 } 5278 } 5279 #endif /* DDB */ 5280 5281 static struct resource * 5282 pci_reserve_map(device_t dev, device_t child, int type, int *rid, 5283 rman_res_t start, rman_res_t end, rman_res_t count, u_int num, 5284 u_int flags) 5285 { 5286 struct pci_devinfo *dinfo = device_get_ivars(child); 5287 struct resource_list *rl = &dinfo->resources; 5288 struct resource *res; 5289 struct pci_map *pm; 5290 uint16_t cmd; 5291 pci_addr_t map, testval; 5292 int mapsize; 5293 5294 res = NULL; 5295 5296 /* If rid is managed by EA, ignore it */ 5297 if (pci_ea_is_enabled(child, *rid)) 5298 goto out; 5299 5300 pm = pci_find_bar(child, *rid); 5301 if (pm != NULL) { 5302 /* This is a BAR that we failed to allocate earlier. */ 5303 mapsize = pm->pm_size; 5304 map = pm->pm_value; 5305 } else { 5306 /* 5307 * Weed out the bogons, and figure out how large the 5308 * BAR/map is. BARs that read back 0 here are bogus 5309 * and unimplemented. Note: atapci in legacy mode are 5310 * special and handled elsewhere in the code. If you 5311 * have a atapci device in legacy mode and it fails 5312 * here, that other code is broken. 5313 */ 5314 pci_read_bar(child, *rid, &map, &testval, NULL); 5315 5316 /* 5317 * Determine the size of the BAR and ignore BARs with a size 5318 * of 0. Device ROM BARs use a different mask value. 5319 */ 5320 if (PCIR_IS_BIOS(&dinfo->cfg, *rid)) 5321 mapsize = pci_romsize(testval); 5322 else 5323 mapsize = pci_mapsize(testval); 5324 if (mapsize == 0) 5325 goto out; 5326 pm = pci_add_bar(child, *rid, map, mapsize); 5327 } 5328 5329 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) { 5330 if (type != SYS_RES_MEMORY) { 5331 if (bootverbose) 5332 device_printf(dev, 5333 "child %s requested type %d for rid %#x," 5334 " but the BAR says it is an memio\n", 5335 device_get_nameunit(child), type, *rid); 5336 goto out; 5337 } 5338 } else { 5339 if (type != SYS_RES_IOPORT) { 5340 if (bootverbose) 5341 device_printf(dev, 5342 "child %s requested type %d for rid %#x," 5343 " but the BAR says it is an ioport\n", 5344 device_get_nameunit(child), type, *rid); 5345 goto out; 5346 } 5347 } 5348 5349 /* 5350 * For real BARs, we need to override the size that 5351 * the driver requests, because that's what the BAR 5352 * actually uses and we would otherwise have a 5353 * situation where we might allocate the excess to 5354 * another driver, which won't work. 5355 */ 5356 count = ((pci_addr_t)1 << mapsize) * num; 5357 if (RF_ALIGNMENT(flags) < mapsize) 5358 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 5359 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH)) 5360 flags |= RF_PREFETCHABLE; 5361 5362 /* 5363 * Allocate enough resource, and then write back the 5364 * appropriate BAR for that resource. 5365 */ 5366 resource_list_add(rl, type, *rid, start, end, count); 5367 res = resource_list_reserve(rl, dev, child, type, rid, start, end, 5368 count, flags & ~RF_ACTIVE); 5369 if (res == NULL) { 5370 resource_list_delete(rl, type, *rid); 5371 device_printf(child, 5372 "%#jx bytes of rid %#x res %d failed (%#jx, %#jx).\n", 5373 count, *rid, type, start, end); 5374 goto out; 5375 } 5376 if (bootverbose) 5377 device_printf(child, 5378 "Lazy allocation of %#jx bytes rid %#x type %d at %#jx\n", 5379 count, *rid, type, rman_get_start(res)); 5380 5381 /* Disable decoding via the CMD register before updating the BAR */ 5382 cmd = pci_read_config(child, PCIR_COMMAND, 2); 5383 pci_write_config(child, PCIR_COMMAND, 5384 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 5385 5386 map = rman_get_start(res); 5387 pci_write_bar(child, pm, map); 5388 5389 /* Restore the original value of the CMD register */ 5390 pci_write_config(child, PCIR_COMMAND, cmd, 2); 5391 out: 5392 return (res); 5393 } 5394 5395 struct resource * 5396 pci_alloc_multi_resource(device_t dev, device_t child, int type, int *rid, 5397 rman_res_t start, rman_res_t end, rman_res_t count, u_long num, 5398 u_int flags) 5399 { 5400 struct pci_devinfo *dinfo; 5401 struct resource_list *rl; 5402 struct resource_list_entry *rle; 5403 struct resource *res; 5404 pcicfgregs *cfg; 5405 5406 /* 5407 * Perform lazy resource allocation 5408 */ 5409 dinfo = device_get_ivars(child); 5410 rl = &dinfo->resources; 5411 cfg = &dinfo->cfg; 5412 switch (type) { 5413 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 5414 case PCI_RES_BUS: 5415 return (pci_alloc_secbus(dev, child, rid, start, end, count, 5416 flags)); 5417 #endif 5418 case SYS_RES_IRQ: 5419 /* 5420 * Can't alloc legacy interrupt once MSI messages have 5421 * been allocated. 5422 */ 5423 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || 5424 cfg->msix.msix_alloc > 0)) 5425 return (NULL); 5426 5427 /* 5428 * If the child device doesn't have an interrupt 5429 * routed and is deserving of an interrupt, try to 5430 * assign it one. 5431 */ 5432 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && 5433 (cfg->intpin != 0)) 5434 pci_assign_interrupt(dev, child, 0); 5435 break; 5436 case SYS_RES_IOPORT: 5437 case SYS_RES_MEMORY: 5438 #ifdef NEW_PCIB 5439 /* 5440 * PCI-PCI bridge I/O window resources are not BARs. 5441 * For those allocations just pass the request up the 5442 * tree. 5443 */ 5444 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) { 5445 switch (*rid) { 5446 case PCIR_IOBASEL_1: 5447 case PCIR_MEMBASE_1: 5448 case PCIR_PMBASEL_1: 5449 /* 5450 * XXX: Should we bother creating a resource 5451 * list entry? 5452 */ 5453 return (bus_generic_alloc_resource(dev, child, 5454 type, rid, start, end, count, flags)); 5455 } 5456 } 5457 #endif 5458 /* Reserve resources for this BAR if needed. */ 5459 rle = resource_list_find(rl, type, *rid); 5460 if (rle == NULL) { 5461 res = pci_reserve_map(dev, child, type, rid, start, end, 5462 count, num, flags); 5463 if (res == NULL) 5464 return (NULL); 5465 } 5466 } 5467 return (resource_list_alloc(rl, dev, child, type, rid, 5468 start, end, count, flags)); 5469 } 5470 5471 struct resource * 5472 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 5473 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 5474 { 5475 #ifdef PCI_IOV 5476 struct pci_devinfo *dinfo; 5477 #endif 5478 5479 if (device_get_parent(child) != dev) 5480 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 5481 type, rid, start, end, count, flags)); 5482 5483 #ifdef PCI_IOV 5484 dinfo = device_get_ivars(child); 5485 if (dinfo->cfg.flags & PCICFG_VF) { 5486 switch (type) { 5487 /* VFs can't have I/O BARs. */ 5488 case SYS_RES_IOPORT: 5489 return (NULL); 5490 case SYS_RES_MEMORY: 5491 return (pci_vf_alloc_mem_resource(dev, child, rid, 5492 start, end, count, flags)); 5493 } 5494 5495 /* Fall through for other types of resource allocations. */ 5496 } 5497 #endif 5498 5499 return (pci_alloc_multi_resource(dev, child, type, rid, start, end, 5500 count, 1, flags)); 5501 } 5502 5503 int 5504 pci_release_resource(device_t dev, device_t child, int type, int rid, 5505 struct resource *r) 5506 { 5507 struct pci_devinfo *dinfo; 5508 struct resource_list *rl; 5509 pcicfgregs *cfg; 5510 5511 if (device_get_parent(child) != dev) 5512 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 5513 type, rid, r)); 5514 5515 dinfo = device_get_ivars(child); 5516 cfg = &dinfo->cfg; 5517 5518 #ifdef PCI_IOV 5519 if (dinfo->cfg.flags & PCICFG_VF) { 5520 switch (type) { 5521 /* VFs can't have I/O BARs. */ 5522 case SYS_RES_IOPORT: 5523 return (EDOOFUS); 5524 case SYS_RES_MEMORY: 5525 return (pci_vf_release_mem_resource(dev, child, rid, 5526 r)); 5527 } 5528 5529 /* Fall through for other types of resource allocations. */ 5530 } 5531 #endif 5532 5533 #ifdef NEW_PCIB 5534 /* 5535 * PCI-PCI bridge I/O window resources are not BARs. For 5536 * those allocations just pass the request up the tree. 5537 */ 5538 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE && 5539 (type == SYS_RES_IOPORT || type == SYS_RES_MEMORY)) { 5540 switch (rid) { 5541 case PCIR_IOBASEL_1: 5542 case PCIR_MEMBASE_1: 5543 case PCIR_PMBASEL_1: 5544 return (bus_generic_release_resource(dev, child, type, 5545 rid, r)); 5546 } 5547 } 5548 #endif 5549 5550 rl = &dinfo->resources; 5551 return (resource_list_release(rl, dev, child, type, rid, r)); 5552 } 5553 5554 int 5555 pci_activate_resource(device_t dev, device_t child, int type, int rid, 5556 struct resource *r) 5557 { 5558 struct pci_devinfo *dinfo; 5559 int error; 5560 5561 error = bus_generic_activate_resource(dev, child, type, rid, r); 5562 if (error) 5563 return (error); 5564 5565 /* Enable decoding in the command register when activating BARs. */ 5566 if (device_get_parent(child) == dev) { 5567 /* Device ROMs need their decoding explicitly enabled. */ 5568 dinfo = device_get_ivars(child); 5569 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5570 pci_write_bar(child, pci_find_bar(child, rid), 5571 rman_get_start(r) | PCIM_BIOS_ENABLE); 5572 switch (type) { 5573 case SYS_RES_IOPORT: 5574 case SYS_RES_MEMORY: 5575 error = PCI_ENABLE_IO(dev, child, type); 5576 break; 5577 } 5578 } 5579 return (error); 5580 } 5581 5582 int 5583 pci_deactivate_resource(device_t dev, device_t child, int type, 5584 int rid, struct resource *r) 5585 { 5586 struct pci_devinfo *dinfo; 5587 int error; 5588 5589 error = bus_generic_deactivate_resource(dev, child, type, rid, r); 5590 if (error) 5591 return (error); 5592 5593 /* Disable decoding for device ROMs. */ 5594 if (device_get_parent(child) == dev) { 5595 dinfo = device_get_ivars(child); 5596 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5597 pci_write_bar(child, pci_find_bar(child, rid), 5598 rman_get_start(r)); 5599 } 5600 return (0); 5601 } 5602 5603 void 5604 pci_child_deleted(device_t dev, device_t child) 5605 { 5606 struct resource_list_entry *rle; 5607 struct resource_list *rl; 5608 struct pci_devinfo *dinfo; 5609 5610 dinfo = device_get_ivars(child); 5611 rl = &dinfo->resources; 5612 5613 EVENTHANDLER_INVOKE(pci_delete_device, child); 5614 5615 /* Turn off access to resources we're about to free */ 5616 if (bus_child_present(child) != 0) { 5617 pci_write_config(child, PCIR_COMMAND, pci_read_config(child, 5618 PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2); 5619 5620 pci_disable_busmaster(child); 5621 } 5622 5623 /* Free all allocated resources */ 5624 STAILQ_FOREACH(rle, rl, link) { 5625 if (rle->res) { 5626 if (rman_get_flags(rle->res) & RF_ACTIVE || 5627 resource_list_busy(rl, rle->type, rle->rid)) { 5628 pci_printf(&dinfo->cfg, 5629 "Resource still owned, oops. " 5630 "(type=%d, rid=%d, addr=%lx)\n", 5631 rle->type, rle->rid, 5632 rman_get_start(rle->res)); 5633 bus_release_resource(child, rle->type, rle->rid, 5634 rle->res); 5635 } 5636 resource_list_unreserve(rl, dev, child, rle->type, 5637 rle->rid); 5638 } 5639 } 5640 resource_list_free(rl); 5641 5642 pci_freecfg(dinfo); 5643 } 5644 5645 void 5646 pci_delete_resource(device_t dev, device_t child, int type, int rid) 5647 { 5648 struct pci_devinfo *dinfo; 5649 struct resource_list *rl; 5650 struct resource_list_entry *rle; 5651 5652 if (device_get_parent(child) != dev) 5653 return; 5654 5655 dinfo = device_get_ivars(child); 5656 rl = &dinfo->resources; 5657 rle = resource_list_find(rl, type, rid); 5658 if (rle == NULL) 5659 return; 5660 5661 if (rle->res) { 5662 if (rman_get_flags(rle->res) & RF_ACTIVE || 5663 resource_list_busy(rl, type, rid)) { 5664 device_printf(dev, "delete_resource: " 5665 "Resource still owned by child, oops. " 5666 "(type=%d, rid=%d, addr=%jx)\n", 5667 type, rid, rman_get_start(rle->res)); 5668 return; 5669 } 5670 resource_list_unreserve(rl, dev, child, type, rid); 5671 } 5672 resource_list_delete(rl, type, rid); 5673 } 5674 5675 struct resource_list * 5676 pci_get_resource_list (device_t dev, device_t child) 5677 { 5678 struct pci_devinfo *dinfo = device_get_ivars(child); 5679 5680 return (&dinfo->resources); 5681 } 5682 5683 #ifdef ACPI_DMAR 5684 bus_dma_tag_t dmar_get_dma_tag(device_t dev, device_t child); 5685 bus_dma_tag_t 5686 pci_get_dma_tag(device_t bus, device_t dev) 5687 { 5688 bus_dma_tag_t tag; 5689 struct pci_softc *sc; 5690 5691 if (device_get_parent(dev) == bus) { 5692 /* try dmar and return if it works */ 5693 tag = dmar_get_dma_tag(bus, dev); 5694 } else 5695 tag = NULL; 5696 if (tag == NULL) { 5697 sc = device_get_softc(bus); 5698 tag = sc->sc_dma_tag; 5699 } 5700 return (tag); 5701 } 5702 #else 5703 bus_dma_tag_t 5704 pci_get_dma_tag(device_t bus, device_t dev) 5705 { 5706 struct pci_softc *sc = device_get_softc(bus); 5707 5708 return (sc->sc_dma_tag); 5709 } 5710 #endif 5711 5712 uint32_t 5713 pci_read_config_method(device_t dev, device_t child, int reg, int width) 5714 { 5715 struct pci_devinfo *dinfo = device_get_ivars(child); 5716 pcicfgregs *cfg = &dinfo->cfg; 5717 5718 #ifdef PCI_IOV 5719 /* 5720 * SR-IOV VFs don't implement the VID or DID registers, so we have to 5721 * emulate them here. 5722 */ 5723 if (cfg->flags & PCICFG_VF) { 5724 if (reg == PCIR_VENDOR) { 5725 switch (width) { 5726 case 4: 5727 return (cfg->device << 16 | cfg->vendor); 5728 case 2: 5729 return (cfg->vendor); 5730 case 1: 5731 return (cfg->vendor & 0xff); 5732 default: 5733 return (0xffffffff); 5734 } 5735 } else if (reg == PCIR_DEVICE) { 5736 switch (width) { 5737 /* Note that an unaligned 4-byte read is an error. */ 5738 case 2: 5739 return (cfg->device); 5740 case 1: 5741 return (cfg->device & 0xff); 5742 default: 5743 return (0xffffffff); 5744 } 5745 } 5746 } 5747 #endif 5748 5749 return (PCIB_READ_CONFIG(device_get_parent(dev), 5750 cfg->bus, cfg->slot, cfg->func, reg, width)); 5751 } 5752 5753 void 5754 pci_write_config_method(device_t dev, device_t child, int reg, 5755 uint32_t val, int width) 5756 { 5757 struct pci_devinfo *dinfo = device_get_ivars(child); 5758 pcicfgregs *cfg = &dinfo->cfg; 5759 5760 PCIB_WRITE_CONFIG(device_get_parent(dev), 5761 cfg->bus, cfg->slot, cfg->func, reg, val, width); 5762 } 5763 5764 int 5765 pci_child_location_str_method(device_t dev, device_t child, char *buf, 5766 size_t buflen) 5767 { 5768 5769 snprintf(buf, buflen, "slot=%d function=%d dbsf=pci%d:%d:%d:%d", 5770 pci_get_slot(child), pci_get_function(child), pci_get_domain(child), 5771 pci_get_bus(child), pci_get_slot(child), pci_get_function(child)); 5772 return (0); 5773 } 5774 5775 int 5776 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 5777 size_t buflen) 5778 { 5779 struct pci_devinfo *dinfo; 5780 pcicfgregs *cfg; 5781 5782 dinfo = device_get_ivars(child); 5783 cfg = &dinfo->cfg; 5784 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 5785 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 5786 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 5787 cfg->progif); 5788 return (0); 5789 } 5790 5791 int 5792 pci_assign_interrupt_method(device_t dev, device_t child) 5793 { 5794 struct pci_devinfo *dinfo = device_get_ivars(child); 5795 pcicfgregs *cfg = &dinfo->cfg; 5796 5797 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 5798 cfg->intpin)); 5799 } 5800 5801 static void 5802 pci_lookup(void *arg, const char *name, device_t *dev) 5803 { 5804 long val; 5805 char *end; 5806 int domain, bus, slot, func; 5807 5808 if (*dev != NULL) 5809 return; 5810 5811 /* 5812 * Accept pciconf-style selectors of either pciD:B:S:F or 5813 * pciB:S:F. In the latter case, the domain is assumed to 5814 * be zero. 5815 */ 5816 if (strncmp(name, "pci", 3) != 0) 5817 return; 5818 val = strtol(name + 3, &end, 10); 5819 if (val < 0 || val > INT_MAX || *end != ':') 5820 return; 5821 domain = val; 5822 val = strtol(end + 1, &end, 10); 5823 if (val < 0 || val > INT_MAX || *end != ':') 5824 return; 5825 bus = val; 5826 val = strtol(end + 1, &end, 10); 5827 if (val < 0 || val > INT_MAX) 5828 return; 5829 slot = val; 5830 if (*end == ':') { 5831 val = strtol(end + 1, &end, 10); 5832 if (val < 0 || val > INT_MAX || *end != '\0') 5833 return; 5834 func = val; 5835 } else if (*end == '\0') { 5836 func = slot; 5837 slot = bus; 5838 bus = domain; 5839 domain = 0; 5840 } else 5841 return; 5842 5843 if (domain > PCI_DOMAINMAX || bus > PCI_BUSMAX || slot > PCI_SLOTMAX || 5844 func > PCIE_ARI_FUNCMAX || (slot != 0 && func > PCI_FUNCMAX)) 5845 return; 5846 5847 *dev = pci_find_dbsf(domain, bus, slot, func); 5848 } 5849 5850 static int 5851 pci_modevent(module_t mod, int what, void *arg) 5852 { 5853 static struct cdev *pci_cdev; 5854 static eventhandler_tag tag; 5855 5856 switch (what) { 5857 case MOD_LOAD: 5858 STAILQ_INIT(&pci_devq); 5859 pci_generation = 0; 5860 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 5861 "pci"); 5862 pci_load_vendor_data(); 5863 tag = EVENTHANDLER_REGISTER(dev_lookup, pci_lookup, NULL, 5864 1000); 5865 break; 5866 5867 case MOD_UNLOAD: 5868 if (tag != NULL) 5869 EVENTHANDLER_DEREGISTER(dev_lookup, tag); 5870 destroy_dev(pci_cdev); 5871 break; 5872 } 5873 5874 return (0); 5875 } 5876 5877 static void 5878 pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo) 5879 { 5880 #define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2) 5881 struct pcicfg_pcie *cfg; 5882 int version, pos; 5883 5884 cfg = &dinfo->cfg.pcie; 5885 pos = cfg->pcie_location; 5886 5887 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 5888 5889 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl); 5890 5891 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5892 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 5893 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 5894 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl); 5895 5896 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5897 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 5898 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 5899 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl); 5900 5901 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5902 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 5903 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl); 5904 5905 if (version > 1) { 5906 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2); 5907 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2); 5908 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2); 5909 } 5910 #undef WREG 5911 } 5912 5913 static void 5914 pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo) 5915 { 5916 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 5917 dinfo->cfg.pcix.pcix_command, 2); 5918 } 5919 5920 void 5921 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 5922 { 5923 5924 /* 5925 * Restore the device to full power mode. We must do this 5926 * before we restore the registers because moving from D3 to 5927 * D0 will cause the chip's BARs and some other registers to 5928 * be reset to some unknown power on reset values. Cut down 5929 * the noise on boot by doing nothing if we are already in 5930 * state D0. 5931 */ 5932 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) 5933 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 5934 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 5935 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 5936 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 5937 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 5938 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 5939 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 5940 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 5941 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 5942 case PCIM_HDRTYPE_NORMAL: 5943 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 5944 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 5945 break; 5946 case PCIM_HDRTYPE_BRIDGE: 5947 pci_write_config(dev, PCIR_SECLAT_1, 5948 dinfo->cfg.bridge.br_seclat, 1); 5949 pci_write_config(dev, PCIR_SUBBUS_1, 5950 dinfo->cfg.bridge.br_subbus, 1); 5951 pci_write_config(dev, PCIR_SECBUS_1, 5952 dinfo->cfg.bridge.br_secbus, 1); 5953 pci_write_config(dev, PCIR_PRIBUS_1, 5954 dinfo->cfg.bridge.br_pribus, 1); 5955 pci_write_config(dev, PCIR_BRIDGECTL_1, 5956 dinfo->cfg.bridge.br_control, 2); 5957 break; 5958 case PCIM_HDRTYPE_CARDBUS: 5959 pci_write_config(dev, PCIR_SECLAT_2, 5960 dinfo->cfg.bridge.br_seclat, 1); 5961 pci_write_config(dev, PCIR_SUBBUS_2, 5962 dinfo->cfg.bridge.br_subbus, 1); 5963 pci_write_config(dev, PCIR_SECBUS_2, 5964 dinfo->cfg.bridge.br_secbus, 1); 5965 pci_write_config(dev, PCIR_PRIBUS_2, 5966 dinfo->cfg.bridge.br_pribus, 1); 5967 pci_write_config(dev, PCIR_BRIDGECTL_2, 5968 dinfo->cfg.bridge.br_control, 2); 5969 break; 5970 } 5971 pci_restore_bars(dev); 5972 5973 /* 5974 * Restore extended capabilities for PCI-Express and PCI-X 5975 */ 5976 if (dinfo->cfg.pcie.pcie_location != 0) 5977 pci_cfg_restore_pcie(dev, dinfo); 5978 if (dinfo->cfg.pcix.pcix_location != 0) 5979 pci_cfg_restore_pcix(dev, dinfo); 5980 5981 /* Restore MSI and MSI-X configurations if they are present. */ 5982 if (dinfo->cfg.msi.msi_location != 0) 5983 pci_resume_msi(dev); 5984 if (dinfo->cfg.msix.msix_location != 0) 5985 pci_resume_msix(dev); 5986 5987 #ifdef PCI_IOV 5988 if (dinfo->cfg.iov != NULL) 5989 pci_iov_cfg_restore(dev, dinfo); 5990 #endif 5991 } 5992 5993 static void 5994 pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo) 5995 { 5996 #define RREG(n) pci_read_config(dev, pos + (n), 2) 5997 struct pcicfg_pcie *cfg; 5998 int version, pos; 5999 6000 cfg = &dinfo->cfg.pcie; 6001 pos = cfg->pcie_location; 6002 6003 cfg->pcie_flags = RREG(PCIER_FLAGS); 6004 6005 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 6006 6007 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL); 6008 6009 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6010 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 6011 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 6012 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL); 6013 6014 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6015 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 6016 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 6017 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL); 6018 6019 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6020 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 6021 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL); 6022 6023 if (version > 1) { 6024 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2); 6025 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2); 6026 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2); 6027 } 6028 #undef RREG 6029 } 6030 6031 static void 6032 pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo) 6033 { 6034 dinfo->cfg.pcix.pcix_command = pci_read_config(dev, 6035 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2); 6036 } 6037 6038 void 6039 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 6040 { 6041 uint32_t cls; 6042 int ps; 6043 6044 /* 6045 * Some drivers apparently write to these registers w/o updating our 6046 * cached copy. No harm happens if we update the copy, so do so here 6047 * so we can restore them. The COMMAND register is modified by the 6048 * bus w/o updating the cache. This should represent the normally 6049 * writable portion of the 'defined' part of type 0/1/2 headers. 6050 */ 6051 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 6052 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 6053 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 6054 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 6055 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 6056 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 6057 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 6058 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 6059 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 6060 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 6061 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 6062 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 6063 case PCIM_HDRTYPE_NORMAL: 6064 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 6065 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 6066 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 6067 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 6068 break; 6069 case PCIM_HDRTYPE_BRIDGE: 6070 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6071 PCIR_SECLAT_1, 1); 6072 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6073 PCIR_SUBBUS_1, 1); 6074 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6075 PCIR_SECBUS_1, 1); 6076 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6077 PCIR_PRIBUS_1, 1); 6078 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6079 PCIR_BRIDGECTL_1, 2); 6080 break; 6081 case PCIM_HDRTYPE_CARDBUS: 6082 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6083 PCIR_SECLAT_2, 1); 6084 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6085 PCIR_SUBBUS_2, 1); 6086 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6087 PCIR_SECBUS_2, 1); 6088 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6089 PCIR_PRIBUS_2, 1); 6090 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6091 PCIR_BRIDGECTL_2, 2); 6092 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2); 6093 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2); 6094 break; 6095 } 6096 6097 if (dinfo->cfg.pcie.pcie_location != 0) 6098 pci_cfg_save_pcie(dev, dinfo); 6099 6100 if (dinfo->cfg.pcix.pcix_location != 0) 6101 pci_cfg_save_pcix(dev, dinfo); 6102 6103 #ifdef PCI_IOV 6104 if (dinfo->cfg.iov != NULL) 6105 pci_iov_cfg_save(dev, dinfo); 6106 #endif 6107 6108 /* 6109 * don't set the state for display devices, base peripherals and 6110 * memory devices since bad things happen when they are powered down. 6111 * We should (a) have drivers that can easily detach and (b) use 6112 * generic drivers for these devices so that some device actually 6113 * attaches. We need to make sure that when we implement (a) we don't 6114 * power the device down on a reattach. 6115 */ 6116 cls = pci_get_class(dev); 6117 if (!setstate) 6118 return; 6119 switch (pci_do_power_nodriver) 6120 { 6121 case 0: /* NO powerdown at all */ 6122 return; 6123 case 1: /* Conservative about what to power down */ 6124 if (cls == PCIC_STORAGE) 6125 return; 6126 /*FALLTHROUGH*/ 6127 case 2: /* Aggressive about what to power down */ 6128 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 6129 cls == PCIC_BASEPERIPH) 6130 return; 6131 /*FALLTHROUGH*/ 6132 case 3: /* Power down everything */ 6133 break; 6134 } 6135 /* 6136 * PCI spec says we can only go into D3 state from D0 state. 6137 * Transition from D[12] into D0 before going to D3 state. 6138 */ 6139 ps = pci_get_powerstate(dev); 6140 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6141 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6142 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 6143 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6144 } 6145 6146 /* Wrapper APIs suitable for device driver use. */ 6147 void 6148 pci_save_state(device_t dev) 6149 { 6150 struct pci_devinfo *dinfo; 6151 6152 dinfo = device_get_ivars(dev); 6153 pci_cfg_save(dev, dinfo, 0); 6154 } 6155 6156 void 6157 pci_restore_state(device_t dev) 6158 { 6159 struct pci_devinfo *dinfo; 6160 6161 dinfo = device_get_ivars(dev); 6162 pci_cfg_restore(dev, dinfo); 6163 } 6164 6165 static int 6166 pci_get_id_method(device_t dev, device_t child, enum pci_id_type type, 6167 uintptr_t *id) 6168 { 6169 6170 return (PCIB_GET_ID(device_get_parent(dev), child, type, id)); 6171 } 6172 6173 /* Find the upstream port of a given PCI device in a root complex. */ 6174 device_t 6175 pci_find_pcie_root_port(device_t dev) 6176 { 6177 struct pci_devinfo *dinfo; 6178 devclass_t pci_class; 6179 device_t pcib, bus; 6180 6181 pci_class = devclass_find("pci"); 6182 KASSERT(device_get_devclass(device_get_parent(dev)) == pci_class, 6183 ("%s: non-pci device %s", __func__, device_get_nameunit(dev))); 6184 6185 /* 6186 * Walk the bridge hierarchy until we find a PCI-e root 6187 * port or a non-PCI device. 6188 */ 6189 for (;;) { 6190 bus = device_get_parent(dev); 6191 KASSERT(bus != NULL, ("%s: null parent of %s", __func__, 6192 device_get_nameunit(dev))); 6193 6194 pcib = device_get_parent(bus); 6195 KASSERT(pcib != NULL, ("%s: null bridge of %s", __func__, 6196 device_get_nameunit(bus))); 6197 6198 /* 6199 * pcib's parent must be a PCI bus for this to be a 6200 * PCI-PCI bridge. 6201 */ 6202 if (device_get_devclass(device_get_parent(pcib)) != pci_class) 6203 return (NULL); 6204 6205 dinfo = device_get_ivars(pcib); 6206 if (dinfo->cfg.pcie.pcie_location != 0 && 6207 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) 6208 return (pcib); 6209 6210 dev = pcib; 6211 } 6212 } 6213 6214 /* 6215 * Wait for pending transactions to complete on a PCI-express function. 6216 * 6217 * The maximum delay is specified in milliseconds in max_delay. Note 6218 * that this function may sleep. 6219 * 6220 * Returns true if the function is idle and false if the timeout is 6221 * exceeded. If dev is not a PCI-express function, this returns true. 6222 */ 6223 bool 6224 pcie_wait_for_pending_transactions(device_t dev, u_int max_delay) 6225 { 6226 struct pci_devinfo *dinfo = device_get_ivars(dev); 6227 uint16_t sta; 6228 int cap; 6229 6230 cap = dinfo->cfg.pcie.pcie_location; 6231 if (cap == 0) 6232 return (true); 6233 6234 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6235 while (sta & PCIEM_STA_TRANSACTION_PND) { 6236 if (max_delay == 0) 6237 return (false); 6238 6239 /* Poll once every 100 milliseconds up to the timeout. */ 6240 if (max_delay > 100) { 6241 pause_sbt("pcietp", 100 * SBT_1MS, 0, C_HARDCLOCK); 6242 max_delay -= 100; 6243 } else { 6244 pause_sbt("pcietp", max_delay * SBT_1MS, 0, 6245 C_HARDCLOCK); 6246 max_delay = 0; 6247 } 6248 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6249 } 6250 6251 return (true); 6252 } 6253 6254 /* 6255 * Determine the maximum Completion Timeout in microseconds. 6256 * 6257 * For non-PCI-express functions this returns 0. 6258 */ 6259 int 6260 pcie_get_max_completion_timeout(device_t dev) 6261 { 6262 struct pci_devinfo *dinfo = device_get_ivars(dev); 6263 int cap; 6264 6265 cap = dinfo->cfg.pcie.pcie_location; 6266 if (cap == 0) 6267 return (0); 6268 6269 /* 6270 * Functions using the 1.x spec use the default timeout range of 6271 * 50 microseconds to 50 milliseconds. Functions that do not 6272 * support programmable timeouts also use this range. 6273 */ 6274 if ((dinfo->cfg.pcie.pcie_flags & PCIEM_FLAGS_VERSION) < 2 || 6275 (pci_read_config(dev, cap + PCIER_DEVICE_CAP2, 4) & 6276 PCIEM_CAP2_COMP_TIMO_RANGES) == 0) 6277 return (50 * 1000); 6278 6279 switch (pci_read_config(dev, cap + PCIER_DEVICE_CTL2, 2) & 6280 PCIEM_CTL2_COMP_TIMO_VAL) { 6281 case PCIEM_CTL2_COMP_TIMO_100US: 6282 return (100); 6283 case PCIEM_CTL2_COMP_TIMO_10MS: 6284 return (10 * 1000); 6285 case PCIEM_CTL2_COMP_TIMO_55MS: 6286 return (55 * 1000); 6287 case PCIEM_CTL2_COMP_TIMO_210MS: 6288 return (210 * 1000); 6289 case PCIEM_CTL2_COMP_TIMO_900MS: 6290 return (900 * 1000); 6291 case PCIEM_CTL2_COMP_TIMO_3500MS: 6292 return (3500 * 1000); 6293 case PCIEM_CTL2_COMP_TIMO_13S: 6294 return (13 * 1000 * 1000); 6295 case PCIEM_CTL2_COMP_TIMO_64S: 6296 return (64 * 1000 * 1000); 6297 default: 6298 return (50 * 1000); 6299 } 6300 } 6301 6302 /* 6303 * Perform a Function Level Reset (FLR) on a device. 6304 * 6305 * This function first waits for any pending transactions to complete 6306 * within the timeout specified by max_delay. If transactions are 6307 * still pending, the function will return false without attempting a 6308 * reset. 6309 * 6310 * If dev is not a PCI-express function or does not support FLR, this 6311 * function returns false. 6312 * 6313 * Note that no registers are saved or restored. The caller is 6314 * responsible for saving and restoring any registers including 6315 * PCI-standard registers via pci_save_state() and 6316 * pci_restore_state(). 6317 */ 6318 bool 6319 pcie_flr(device_t dev, u_int max_delay, bool force) 6320 { 6321 struct pci_devinfo *dinfo = device_get_ivars(dev); 6322 uint16_t cmd, ctl; 6323 int compl_delay; 6324 int cap; 6325 6326 cap = dinfo->cfg.pcie.pcie_location; 6327 if (cap == 0) 6328 return (false); 6329 6330 if (!(pci_read_config(dev, cap + PCIER_DEVICE_CAP, 4) & PCIEM_CAP_FLR)) 6331 return (false); 6332 6333 /* 6334 * Disable busmastering to prevent generation of new 6335 * transactions while waiting for the device to go idle. If 6336 * the idle timeout fails, the command register is restored 6337 * which will re-enable busmastering. 6338 */ 6339 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 6340 pci_write_config(dev, PCIR_COMMAND, cmd & ~(PCIM_CMD_BUSMASTEREN), 2); 6341 if (!pcie_wait_for_pending_transactions(dev, max_delay)) { 6342 if (!force) { 6343 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 6344 return (false); 6345 } 6346 pci_printf(&dinfo->cfg, 6347 "Resetting with transactions pending after %d ms\n", 6348 max_delay); 6349 6350 /* 6351 * Extend the post-FLR delay to cover the maximum 6352 * Completion Timeout delay of anything in flight 6353 * during the FLR delay. Enforce a minimum delay of 6354 * at least 10ms. 6355 */ 6356 compl_delay = pcie_get_max_completion_timeout(dev) / 1000; 6357 if (compl_delay < 10) 6358 compl_delay = 10; 6359 } else 6360 compl_delay = 0; 6361 6362 /* Initiate the reset. */ 6363 ctl = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 6364 pci_write_config(dev, cap + PCIER_DEVICE_CTL, ctl | 6365 PCIEM_CTL_INITIATE_FLR, 2); 6366 6367 /* Wait for 100ms. */ 6368 pause_sbt("pcieflr", (100 + compl_delay) * SBT_1MS, 0, C_HARDCLOCK); 6369 6370 if (pci_read_config(dev, cap + PCIER_DEVICE_STA, 2) & 6371 PCIEM_STA_TRANSACTION_PND) 6372 pci_printf(&dinfo->cfg, "Transactions pending after FLR!\n"); 6373 return (true); 6374 } 6375 6376 /* 6377 * Attempt a power-management reset by cycling the device in/out of D3 6378 * state. PCI spec says we can only go into D3 state from D0 state. 6379 * Transition from D[12] into D0 before going to D3 state. 6380 */ 6381 int 6382 pci_power_reset(device_t dev) 6383 { 6384 int ps; 6385 6386 ps = pci_get_powerstate(dev); 6387 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6388 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6389 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6390 pci_set_powerstate(dev, ps); 6391 return (0); 6392 } 6393 6394 /* 6395 * Try link drop and retrain of the downstream port of upstream 6396 * switch, for PCIe. According to the PCIe 3.0 spec 6.6.1, this must 6397 * cause Conventional Hot reset of the device in the slot. 6398 * Alternative, for PCIe, could be the secondary bus reset initiatied 6399 * on the upstream switch PCIR_BRIDGECTL_1, bit 6. 6400 */ 6401 int 6402 pcie_link_reset(device_t port, int pcie_location) 6403 { 6404 uint16_t v; 6405 6406 v = pci_read_config(port, pcie_location + PCIER_LINK_CTL, 2); 6407 v |= PCIEM_LINK_CTL_LINK_DIS; 6408 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6409 pause_sbt("pcier1", mstosbt(20), 0, 0); 6410 v &= ~PCIEM_LINK_CTL_LINK_DIS; 6411 v |= PCIEM_LINK_CTL_RETRAIN_LINK; 6412 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6413 pause_sbt("pcier2", mstosbt(100), 0, 0); /* 100 ms */ 6414 v = pci_read_config(port, pcie_location + PCIER_LINK_STA, 2); 6415 return ((v & PCIEM_LINK_STA_TRAINING) != 0 ? ETIMEDOUT : 0); 6416 } 6417 6418 static int 6419 pci_reset_post(device_t dev, device_t child) 6420 { 6421 6422 if (dev == device_get_parent(child)) 6423 pci_restore_state(child); 6424 return (0); 6425 } 6426 6427 static int 6428 pci_reset_prepare(device_t dev, device_t child) 6429 { 6430 6431 if (dev == device_get_parent(child)) 6432 pci_save_state(child); 6433 return (0); 6434 } 6435 6436 static int 6437 pci_reset_child(device_t dev, device_t child, int flags) 6438 { 6439 int error; 6440 6441 if (dev == NULL || device_get_parent(child) != dev) 6442 return (0); 6443 if ((flags & DEVF_RESET_DETACH) != 0) { 6444 error = device_get_state(child) == DS_ATTACHED ? 6445 device_detach(child) : 0; 6446 } else { 6447 error = BUS_SUSPEND_CHILD(dev, child); 6448 } 6449 if (error == 0) { 6450 if (!pcie_flr(child, 1000, false)) { 6451 error = BUS_RESET_PREPARE(dev, child); 6452 if (error == 0) 6453 pci_power_reset(child); 6454 BUS_RESET_POST(dev, child); 6455 } 6456 if ((flags & DEVF_RESET_DETACH) != 0) 6457 device_probe_and_attach(child); 6458 else 6459 BUS_RESUME_CHILD(dev, child); 6460 } 6461 return (error); 6462 } 6463 6464 const struct pci_device_table * 6465 pci_match_device(device_t child, const struct pci_device_table *id, size_t nelt) 6466 { 6467 bool match; 6468 uint16_t vendor, device, subvendor, subdevice, class, subclass, revid; 6469 6470 vendor = pci_get_vendor(child); 6471 device = pci_get_device(child); 6472 subvendor = pci_get_subvendor(child); 6473 subdevice = pci_get_subdevice(child); 6474 class = pci_get_class(child); 6475 subclass = pci_get_subclass(child); 6476 revid = pci_get_revid(child); 6477 while (nelt-- > 0) { 6478 match = true; 6479 if (id->match_flag_vendor) 6480 match &= vendor == id->vendor; 6481 if (id->match_flag_device) 6482 match &= device == id->device; 6483 if (id->match_flag_subvendor) 6484 match &= subvendor == id->subvendor; 6485 if (id->match_flag_subdevice) 6486 match &= subdevice == id->subdevice; 6487 if (id->match_flag_class) 6488 match &= class == id->class_id; 6489 if (id->match_flag_subclass) 6490 match &= subclass == id->subclass; 6491 if (id->match_flag_revid) 6492 match &= revid == id->revid; 6493 if (match) 6494 return (id); 6495 id++; 6496 } 6497 return (NULL); 6498 } 6499 6500 static void 6501 pci_print_faulted_dev_name(const struct pci_devinfo *dinfo) 6502 { 6503 const char *dev_name; 6504 device_t dev; 6505 6506 dev = dinfo->cfg.dev; 6507 printf("pci%d:%d:%d:%d", dinfo->cfg.domain, dinfo->cfg.bus, 6508 dinfo->cfg.slot, dinfo->cfg.func); 6509 dev_name = device_get_name(dev); 6510 if (dev_name != NULL) 6511 printf(" (%s%d)", dev_name, device_get_unit(dev)); 6512 } 6513 6514 void 6515 pci_print_faulted_dev(void) 6516 { 6517 struct pci_devinfo *dinfo; 6518 device_t dev; 6519 int aer, i; 6520 uint32_t r1, r2; 6521 uint16_t status; 6522 6523 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 6524 dev = dinfo->cfg.dev; 6525 status = pci_read_config(dev, PCIR_STATUS, 2); 6526 status &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 6527 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 6528 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 6529 if (status != 0) { 6530 pci_print_faulted_dev_name(dinfo); 6531 printf(" error 0x%04x\n", status); 6532 } 6533 if (dinfo->cfg.pcie.pcie_location != 0) { 6534 status = pci_read_config(dev, 6535 dinfo->cfg.pcie.pcie_location + 6536 PCIER_DEVICE_STA, 2); 6537 if ((status & (PCIEM_STA_CORRECTABLE_ERROR | 6538 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6539 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6540 pci_print_faulted_dev_name(dinfo); 6541 printf(" PCIe DEVCTL 0x%04x DEVSTA 0x%04x\n", 6542 pci_read_config(dev, 6543 dinfo->cfg.pcie.pcie_location + 6544 PCIER_DEVICE_CTL, 2), 6545 status); 6546 } 6547 } 6548 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6549 r1 = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6550 r2 = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6551 if (r1 != 0 || r2 != 0) { 6552 pci_print_faulted_dev_name(dinfo); 6553 printf(" AER UC 0x%08x Mask 0x%08x Svr 0x%08x\n" 6554 " COR 0x%08x Mask 0x%08x Ctl 0x%08x\n", 6555 r1, pci_read_config(dev, aer + 6556 PCIR_AER_UC_MASK, 4), 6557 pci_read_config(dev, aer + 6558 PCIR_AER_UC_SEVERITY, 4), 6559 r2, pci_read_config(dev, aer + 6560 PCIR_AER_COR_MASK, 4), 6561 pci_read_config(dev, aer + 6562 PCIR_AER_CAP_CONTROL, 4)); 6563 for (i = 0; i < 4; i++) { 6564 r1 = pci_read_config(dev, aer + 6565 PCIR_AER_HEADER_LOG + i * 4, 4); 6566 printf(" HL%d: 0x%08x\n", i, r1); 6567 } 6568 } 6569 } 6570 } 6571 } 6572 6573 #ifdef DDB 6574 DB_SHOW_COMMAND(pcierr, pci_print_faulted_dev_db) 6575 { 6576 6577 pci_print_faulted_dev(); 6578 } 6579 6580 static void 6581 db_clear_pcie_errors(const struct pci_devinfo *dinfo) 6582 { 6583 device_t dev; 6584 int aer; 6585 uint32_t r; 6586 6587 dev = dinfo->cfg.dev; 6588 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 6589 PCIER_DEVICE_STA, 2); 6590 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 6591 PCIER_DEVICE_STA, r, 2); 6592 6593 if (pci_find_extcap(dev, PCIZ_AER, &aer) != 0) 6594 return; 6595 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6596 if (r != 0) 6597 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 6598 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6599 if (r != 0) 6600 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 6601 } 6602 6603 DB_COMMAND(pci_clearerr, db_pci_clearerr) 6604 { 6605 struct pci_devinfo *dinfo; 6606 device_t dev; 6607 uint16_t status, status1; 6608 6609 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 6610 dev = dinfo->cfg.dev; 6611 status1 = status = pci_read_config(dev, PCIR_STATUS, 2); 6612 status1 &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 6613 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 6614 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 6615 if (status1 != 0) { 6616 status &= ~status1; 6617 pci_write_config(dev, PCIR_STATUS, status, 2); 6618 } 6619 if (dinfo->cfg.pcie.pcie_location != 0) 6620 db_clear_pcie_errors(dinfo); 6621 } 6622 } 6623 #endif 6624