xref: /freebsd/sys/dev/pccbb/pccbb_pci.c (revision 9768746ba83efa02837c5b9c66348db6e900208f)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2000-2001 Jonathan Chen All rights reserved.
5  * Copyright (c) 2002-2004 M. Warner Losh <imp@FreeBSD.org>
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  *
28  */
29 
30 /*-
31  * Copyright (c) 1998, 1999 and 2000
32  *      HAYAKAWA Koichi.  All rights reserved.
33  *
34  * Redistribution and use in source and binary forms, with or without
35  * modification, are permitted provided that the following conditions
36  * are met:
37  * 1. Redistributions of source code must retain the above copyright
38  *    notice, this list of conditions and the following disclaimer.
39  * 2. Redistributions in binary form must reproduce the above copyright
40  *    notice, this list of conditions and the following disclaimer in the
41  *    documentation and/or other materials provided with the distribution.
42  * 3. All advertising materials mentioning features or use of this software
43  *    must display the following acknowledgement:
44  *	This product includes software developed by HAYAKAWA Koichi.
45  * 4. The name of the author may not be used to endorse or promote products
46  *    derived from this software without specific prior written permission.
47  *
48  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
49  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
50  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
51  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
52  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
53  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
54  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
55  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
56  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
57  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
58  */
59 
60 /*
61  * Driver for PCI to CardBus Bridge chips
62  *
63  * References:
64  *  TI Datasheets:
65  *   http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS
66  *
67  * Written by Jonathan Chen <jon@freebsd.org>
68  * The author would like to acknowledge:
69  *  * HAYAKAWA Koichi: Author of the NetBSD code for the same thing
70  *  * Warner Losh: Newbus/newcard guru and author of the pccard side of things
71  *  * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver
72  *  * David Cross: Author of the initial ugly hack for a specific cardbus card
73  */
74 
75 #include <sys/cdefs.h>
76 __FBSDID("$FreeBSD$");
77 
78 #include <sys/param.h>
79 #include <sys/systm.h>
80 #include <sys/proc.h>
81 #include <sys/condvar.h>
82 #include <sys/errno.h>
83 #include <sys/kernel.h>
84 #include <sys/lock.h>
85 #include <sys/malloc.h>
86 #include <sys/mutex.h>
87 #include <sys/sysctl.h>
88 #include <sys/kthread.h>
89 #include <sys/bus.h>
90 #include <machine/bus.h>
91 #include <sys/rman.h>
92 #include <machine/resource.h>
93 #include <sys/module.h>
94 
95 #include <dev/pci/pcireg.h>
96 #include <dev/pci/pcivar.h>
97 #include <dev/pci/pcib_private.h>
98 
99 #include <dev/pccard/pccardreg.h>
100 #include <dev/pccard/pccardvar.h>
101 
102 #include <dev/exca/excareg.h>
103 #include <dev/exca/excavar.h>
104 
105 #include <dev/pccbb/pccbbreg.h>
106 #include <dev/pccbb/pccbbvar.h>
107 
108 #include "power_if.h"
109 #include "card_if.h"
110 #include "pcib_if.h"
111 
112 #define	DPRINTF(x) do { if (cbb_debug) printf x; } while (0)
113 #define	DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0)
114 
115 #define	PCI_MASK_CONFIG(DEV,REG,MASK,SIZE)				\
116 	pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE)
117 #define	PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE)			\
118 	pci_write_config(DEV, REG, (					\
119 		pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE)
120 
121 static void cbb_chipinit(struct cbb_softc *sc);
122 static int cbb_pci_filt(void *arg);
123 
124 static struct yenta_chipinfo {
125 	uint32_t yc_id;
126 	const	char *yc_name;
127 	int	yc_chiptype;
128 } yc_chipsets[] = {
129 	/* Texas Instruments chips */
130 	{PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X},
131 	{PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X},
132 	{PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X},
133 
134 	{PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX},
135 	{PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX},
136 	{PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX},
137 	{PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX},
138 	{PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX},
139 	{PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X},
140 	{PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X},
141 	{PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X},
142 	{PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX},
143 	{PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX},
144 	{PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX},
145 	{PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX},
146 	{PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX},
147 	{PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/
148 	{PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX},
149 	{PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX},
150 	{PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX},
151 	{PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX},
152 	{PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX},
153 	{PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX},
154 	{PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX},
155 	{PCIC_ID_TI6411, "TI6411 PCI-CardBus Bridge", CB_TI12XX},
156 	{PCIC_ID_TI6420, "TI6420 PCI-CardBus Bridge", CB_TI12XX},
157 	{PCIC_ID_TI6420SC, "TI6420 PCI-CardBus Bridge", CB_TI12XX},
158 	{PCIC_ID_TI7410, "TI7410 PCI-CardBus Bridge", CB_TI12XX},
159 	{PCIC_ID_TI7510, "TI7510 PCI-CardBus Bridge", CB_TI12XX},
160 	{PCIC_ID_TI7610, "TI7610 PCI-CardBus Bridge", CB_TI12XX},
161 	{PCIC_ID_TI7610M, "TI7610 PCI-CardBus Bridge", CB_TI12XX},
162 	{PCIC_ID_TI7610SD, "TI7610 PCI-CardBus Bridge", CB_TI12XX},
163 	{PCIC_ID_TI7610MS, "TI7610 PCI-CardBus Bridge", CB_TI12XX},
164 
165 	/* ENE */
166 	{PCIC_ID_ENE_CB710, "ENE CB710 PCI-CardBus Bridge", CB_TI12XX},
167 	{PCIC_ID_ENE_CB720, "ENE CB720 PCI-CardBus Bridge", CB_TI12XX},
168 	{PCIC_ID_ENE_CB1211, "ENE CB1211 PCI-CardBus Bridge", CB_TI12XX},
169 	{PCIC_ID_ENE_CB1225, "ENE CB1225 PCI-CardBus Bridge", CB_TI12XX},
170 	{PCIC_ID_ENE_CB1410, "ENE CB1410 PCI-CardBus Bridge", CB_TI12XX},
171 	{PCIC_ID_ENE_CB1420, "ENE CB1420 PCI-CardBus Bridge", CB_TI12XX},
172 
173 	/* Ricoh chips */
174 	{PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X},
175 	{PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X},
176 	{PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X},
177 	{PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X},
178 	{PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X},
179 	{PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X},
180 
181 	/* Toshiba products */
182 	{PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95},
183 	{PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95},
184 	{PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97},
185 	{PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97},
186 
187 	/* Cirrus Logic */
188 	{PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS},
189 	{PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS},
190 	{PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS},
191 
192 	/* 02Micro */
193 	{PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_O2MICRO},
194 	{PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_O2MICRO},
195 	{PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_O2MICRO},
196 	{PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_O2MICRO},
197 	{PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_O2MICRO},
198 	{PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_O2MICRO},
199 	{PCIC_ID_OZ711E1, "O2Micro OZ711E1 PCI-CardBus Bridge", CB_O2MICRO},
200 	{PCIC_ID_OZ711EC1, "O2Micro OZ711EC1/M1 PCI-CardBus Bridge", CB_O2MICRO},
201 	{PCIC_ID_OZ711E2, "O2Micro OZ711E2 PCI-CardBus Bridge", CB_O2MICRO},
202 	{PCIC_ID_OZ711M1, "O2Micro OZ711M1 PCI-CardBus Bridge", CB_O2MICRO},
203 	{PCIC_ID_OZ711M2, "O2Micro OZ711M2 PCI-CardBus Bridge", CB_O2MICRO},
204 	{PCIC_ID_OZ711M3, "O2Micro OZ711M3 PCI-CardBus Bridge", CB_O2MICRO},
205 
206 	/* SMC */
207 	{PCIC_ID_SMC_34C90, "SMC 34C90 PCI-CardBus Bridge", CB_CIRRUS},
208 
209 	/* sentinel */
210 	{0 /* null id */, "unknown", CB_UNKNOWN},
211 };
212 
213 /************************************************************************/
214 /* Probe/Attach								*/
215 /************************************************************************/
216 
217 static int
218 cbb_chipset(uint32_t pci_id, const char **namep)
219 {
220 	struct yenta_chipinfo *ycp;
221 
222 	for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp)
223 		continue;
224 	if (namep != NULL)
225 		*namep = ycp->yc_name;
226 	return (ycp->yc_chiptype);
227 }
228 
229 static int
230 cbb_pci_probe(device_t brdev)
231 {
232 	const char *name;
233 	uint32_t progif;
234 	uint32_t baseclass;
235 	uint32_t subclass;
236 
237 	/*
238 	 * Do we know that we support the chipset?  If so, then we
239 	 * accept the device.
240 	 */
241 	if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) {
242 		device_set_desc(brdev, name);
243 		return (BUS_PROBE_DEFAULT);
244 	}
245 
246 	/*
247 	 * We do support generic CardBus bridges.  All that we've seen
248 	 * to date have progif 0 (the Yenta spec, and successors mandate
249 	 * this).
250 	 */
251 	baseclass = pci_get_class(brdev);
252 	subclass = pci_get_subclass(brdev);
253 	progif = pci_get_progif(brdev);
254 	if (baseclass == PCIC_BRIDGE &&
255 	    subclass == PCIS_BRIDGE_CARDBUS && progif == 0) {
256 		device_set_desc(brdev, "PCI-CardBus Bridge");
257 		return (BUS_PROBE_GENERIC);
258 	}
259 	return (ENXIO);
260 }
261 
262 /*
263  * Print out the config space
264  */
265 static void
266 cbb_print_config(device_t dev)
267 {
268 	int i;
269 
270 	device_printf(dev, "PCI Configuration space:");
271 	for (i = 0; i < 256; i += 4) {
272 		if (i % 16 == 0)
273 			printf("\n  0x%02x: ", i);
274 		printf("0x%08x ", pci_read_config(dev, i, 4));
275 	}
276 	printf("\n");
277 }
278 
279 static int
280 cbb_pci_attach(device_t brdev)
281 {
282 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
283 	static int curr_bus_number = 2; /* XXX EVILE BAD (see below) */
284 	uint32_t pribus;
285 #endif
286 	struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev);
287 	struct sysctl_ctx_list *sctx;
288 	struct sysctl_oid *soid;
289 	int rid;
290 	device_t parent;
291 
292 	parent = device_get_parent(brdev);
293 	mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF);
294 	sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL);
295 	sc->dev = brdev;
296 	sc->cbdev = NULL;
297 	sc->domain = pci_get_domain(brdev);
298 	sc->pribus = pcib_get_bus(parent);
299 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
300 	pci_write_config(brdev, PCIR_PRIBUS_2, sc->pribus, 1);
301 	pcib_setup_secbus(brdev, &sc->bus, 1);
302 #else
303 	sc->bus.sec = pci_read_config(brdev, PCIR_SECBUS_2, 1);
304 	sc->bus.sub = pci_read_config(brdev, PCIR_SUBBUS_2, 1);
305 #endif
306 	SLIST_INIT(&sc->rl);
307 
308 	rid = CBBR_SOCKBASE;
309 	sc->base_res = bus_alloc_resource_any(brdev, SYS_RES_MEMORY, &rid,
310 	    RF_ACTIVE);
311 	if (!sc->base_res) {
312 		device_printf(brdev, "Could not map register memory\n");
313 		mtx_destroy(&sc->mtx);
314 		return (ENOMEM);
315 	} else {
316 		DEVPRINTF((brdev, "Found memory at %jx\n",
317 		    rman_get_start(sc->base_res)));
318 	}
319 
320 	/* attach children */
321 	sc->cbdev = device_add_child(brdev, "cardbus", -1);
322 	if (sc->cbdev == NULL)
323 		DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n"));
324 	else if (device_probe_and_attach(sc->cbdev) != 0)
325 		DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n"));
326 
327 	sc->bst = rman_get_bustag(sc->base_res);
328 	sc->bsh = rman_get_bushandle(sc->base_res);
329 	exca_init(&sc->exca, brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET);
330 	sc->exca.flags |= EXCA_HAS_MEMREG_WIN;
331 	sc->exca.chipset = EXCA_CARDBUS;
332 	sc->chipinit = cbb_chipinit;
333 	sc->chipinit(sc);
334 
335 	/*Sysctls*/
336 	sctx = device_get_sysctl_ctx(brdev);
337 	soid = device_get_sysctl_tree(brdev);
338 	SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain",
339 	    CTLFLAG_RD, &sc->domain, 0, "Domain number");
340 	SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus",
341 	    CTLFLAG_RD, &sc->pribus, 0, "Primary bus number");
342 	SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus",
343 	    CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number");
344 	SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus",
345 	    CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number");
346 #if 0
347 	SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "memory",
348 	    CTLFLAG_RD, &sc->subbus, 0, "Memory window open");
349 	SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "premem",
350 	    CTLFLAG_RD, &sc->subbus, 0, "Prefetch memory window open");
351 	SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io1",
352 	    CTLFLAG_RD, &sc->subbus, 0, "io range 1 open");
353 	SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io2",
354 	    CTLFLAG_RD, &sc->subbus, 0, "io range 2 open");
355 #endif
356 
357 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
358 	/*
359 	 * This is a gross hack.  We should be scanning the entire pci
360 	 * tree, assigning bus numbers in a way such that we (1) can
361 	 * reserve 1 extra bus just in case and (2) all sub buses
362 	 * are in an appropriate range.
363 	 */
364 	DEVPRINTF((brdev, "Secondary bus is %d\n", sc->bus.sec));
365 	pribus = pci_read_config(brdev, PCIR_PRIBUS_2, 1);
366 	if (sc->bus.sec == 0 || sc->pribus != pribus) {
367 		if (curr_bus_number <= sc->pribus)
368 			curr_bus_number = sc->pribus + 1;
369 		if (pribus != sc->pribus) {
370 			DEVPRINTF((brdev, "Setting primary bus to %d\n",
371 			    sc->pribus));
372 			pci_write_config(brdev, PCIR_PRIBUS_2, sc->pribus, 1);
373 		}
374 		sc->bus.sec = curr_bus_number++;
375 		sc->bus.sub = curr_bus_number++;
376 		DEVPRINTF((brdev, "Secondary bus set to %d subbus %d\n",
377 		    sc->bus.sec, sc->bus.sub));
378 		pci_write_config(brdev, PCIR_SECBUS_2, sc->bus.sec, 1);
379 		pci_write_config(brdev, PCIR_SUBBUS_2, sc->bus.sub, 1);
380 	}
381 #endif
382 
383 	/* Map and establish the interrupt. */
384 	rid = 0;
385 	sc->irq_res = bus_alloc_resource_any(brdev, SYS_RES_IRQ, &rid,
386 	    RF_SHAREABLE | RF_ACTIVE);
387 	if (sc->irq_res == NULL) {
388 		device_printf(brdev, "Unable to map IRQ...\n");
389 		goto err;
390 	}
391 
392 	if (bus_setup_intr(brdev, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE,
393 	    cbb_pci_filt, NULL, sc, &sc->intrhand)) {
394 		device_printf(brdev, "couldn't establish interrupt\n");
395 		goto err;
396 	}
397 
398 	/* reset 16-bit pcmcia bus */
399 	exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET);
400 
401 	/* turn off power */
402 	cbb_power(brdev, CARD_OFF);
403 
404 	/* CSC Interrupt: Card detect interrupt on */
405 	cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD);
406 
407 	/* reset interrupt */
408 	cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT));
409 
410 	if (bootverbose)
411 		cbb_print_config(brdev);
412 
413 	/* Start the thread */
414 	if (kproc_create(cbb_event_thread, sc, &sc->event_thread, 0, 0,
415 	    "%s event thread", device_get_nameunit(brdev))) {
416 		device_printf(brdev, "unable to create event thread.\n");
417 		panic("cbb_create_event_thread");
418 	}
419 	sc->sc_root_token = root_mount_hold(device_get_nameunit(sc->dev));
420 	return (0);
421 err:
422 	if (sc->irq_res)
423 		bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res);
424 	if (sc->base_res) {
425 		bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE,
426 		    sc->base_res);
427 	}
428 	mtx_destroy(&sc->mtx);
429 	return (ENOMEM);
430 }
431 
432 static int
433 cbb_pci_detach(device_t brdev)
434 {
435 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
436 	struct cbb_softc *sc = device_get_softc(brdev);
437 #endif
438 	int error;
439 
440 	error = cbb_detach(brdev);
441 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
442 	if (error == 0)
443 		pcib_free_secbus(brdev, &sc->bus);
444 #endif
445 	return (error);
446 }
447 
448 static void
449 cbb_chipinit(struct cbb_softc *sc)
450 {
451 	uint32_t mux, sysctrl, reg;
452 
453 	/* Set CardBus latency timer */
454 	if (pci_read_config(sc->dev, PCIR_SECLAT_2, 1) < 0x20)
455 		pci_write_config(sc->dev, PCIR_SECLAT_2, 0x20, 1);
456 
457 	/* Set PCI latency timer */
458 	if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20)
459 		pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1);
460 
461 	/* Enable DMA, memory access for this card and I/O access for children */
462 	pci_enable_busmaster(sc->dev);
463 	pci_enable_io(sc->dev, SYS_RES_IOPORT);
464 	pci_enable_io(sc->dev, SYS_RES_MEMORY);
465 
466 	/* disable Legacy IO */
467 	switch (sc->chipset) {
468 	case CB_RF5C46X:
469 		PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL,
470 		    & ~(CBBM_BRIDGECTRL_RL_3E0_EN |
471 		    CBBM_BRIDGECTRL_RL_3E2_EN), 2);
472 		break;
473 	default:
474 		pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4);
475 		break;
476 	}
477 
478 	/* Use PCI interrupt for interrupt routing */
479 	PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL,
480 	    & ~(CBBM_BRIDGECTRL_MASTER_ABORT |
481 	    CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN),
482 	    | CBBM_BRIDGECTRL_WRITE_POST_EN,
483 	    2);
484 
485 	/*
486 	 * XXX this should be a function table, ala OLDCARD.  This means
487 	 * that we could more easily support ISA interrupts for pccard
488 	 * cards if we had to.
489 	 */
490 	switch (sc->chipset) {
491 	case CB_TI113X:
492 		/*
493 		 * The TI 1031, TI 1130 and TI 1131 all require another bit
494 		 * be set to enable PCI routing of interrupts, and then
495 		 * a bit for each of the CSC and Function interrupts we
496 		 * want routed.
497 		 */
498 		PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL,
499 		    | CBBM_CBCTRL_113X_PCI_INTR |
500 		    CBBM_CBCTRL_113X_PCI_CSC | CBBM_CBCTRL_113X_PCI_IRQ_EN,
501 		    1);
502 		PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL,
503 		    & ~(CBBM_DEVCTRL_INT_SERIAL |
504 		    CBBM_DEVCTRL_INT_PCI), 1);
505 		break;
506 	case CB_TI12XX:
507 		/*
508 		 * Some TI 12xx (and [14][45]xx) based pci cards
509 		 * sometimes have issues with the MFUNC register not
510 		 * being initialized due to a bad EEPROM on board.
511 		 * Laptops that this matters on have this register
512 		 * properly initialized.
513 		 *
514 		 * The TI125X parts have a different register.
515 		 *
516 		 * Note: Only the lower two nibbles matter. When set
517 		 * to 0, the MFUNC{0,1} pins are GPIO, which isn't
518 		 * going to work out too well because we specifically
519 		 * program these parts to parallel interrupt signalling
520 		 * elsewhere. We preserve the upper bits of this
521 		 * register since changing them have subtle side effects
522 		 * for different variants of the card and are
523 		 * extremely difficult to exaustively test.
524 		 *
525 		 * Also, the TI 1510/1520 changed the default for the MFUNC
526 		 * register from 0x0 to 0x1000 to enable IRQSER by default.
527 		 * We want to be careful to avoid overriding that, and the
528 		 * below test will do that. Should this check prove to be
529 		 * too permissive, we should just check against 0 and 0x1000
530 		 * and not touch it otherwise.
531 		 */
532 		mux = pci_read_config(sc->dev, CBBR_MFUNC, 4);
533 		sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4);
534 		if ((mux & (CBBM_MFUNC_PIN0 | CBBM_MFUNC_PIN1)) == 0) {
535 			mux = (mux & ~CBBM_MFUNC_PIN0) |
536 			    CBBM_MFUNC_PIN0_INTA;
537 			if ((sysctrl & CBBM_SYSCTRL_INTRTIE) == 0)
538 				mux = (mux & ~CBBM_MFUNC_PIN1) |
539 				    CBBM_MFUNC_PIN1_INTB;
540 			pci_write_config(sc->dev, CBBR_MFUNC, mux, 4);
541 		}
542 		/*FALLTHROUGH*/
543 	case CB_TI125X:
544 		/*
545 		 * Disable zoom video.  Some machines initialize this
546 		 * improperly and exerpience has shown that this helps
547 		 * prevent strange behavior. We don't support zoom
548 		 * video anyway, so no harm can come from this.
549 		 */
550 		pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4);
551 		break;
552 	case CB_O2MICRO:
553 		/*
554 		 * Issue #1: INT# generated at the same time as
555 		 * selected ISA IRQ.  When IREQ# or STSCHG# is active,
556 		 * in addition to the ISA IRQ being generated, INT#
557 		 * will also be generated at the same time.
558 		 *
559 		 * Some of the older controllers have an issue in
560 		 * which the slot's PCI INT# will be asserted whenever
561 		 * IREQ# or STSCGH# is asserted even if ExCA registers
562 		 * 03h or 05h have an ISA IRQ selected.
563 		 *
564 		 * The fix for this issue, which will work for any
565 		 * controller (old or new), is to set ExCA registers
566 		 * 3Ah (slot 0) & 7Ah (slot 1) bits 7:4 = 1010b.
567 		 * These bits are undocumented.  By setting this
568 		 * register (of each slot) to '1010xxxxb' a routing of
569 		 * IREQ# to INTC# and STSCHG# to INTC# is selected.
570 		 * Since INTC# isn't connected there will be no
571 		 * unexpected PCI INT when IREQ# or STSCHG# is active.
572 		 * However, INTA# (slot 0) or INTB# (slot 1) will
573 		 * still be correctly generated if NO ISA IRQ is
574 		 * selected (ExCA regs 03h or 05h are cleared).
575 		 */
576 		reg = exca_getb(&sc->exca, EXCA_O2MICRO_CTRL_C);
577 		reg = (reg & 0x0f) |
578 		    EXCA_O2CC_IREQ_INTC | EXCA_O2CC_STSCHG_INTC;
579 		exca_putb(&sc->exca, EXCA_O2MICRO_CTRL_C, reg);
580 		break;
581 	case CB_TOPIC97:
582 		/*
583 		 * Disable Zoom Video, ToPIC 97, 100.
584 		 */
585 		pci_write_config(sc->dev, TOPIC97_ZV_CONTROL, 0, 1);
586 		/*
587 		 * ToPIC 97, 100
588 		 * At offset 0xa1: INTERRUPT CONTROL register
589 		 * 0x1: Turn on INT interrupts.
590 		 */
591 		PCI_MASK_CONFIG(sc->dev, TOPIC_INTCTRL,
592 		    | TOPIC97_INTCTRL_INTIRQSEL, 1);
593 		/*
594 		 * ToPIC97, 100
595 		 * Need to assert support for low voltage cards
596 		 */
597 		exca_setb(&sc->exca, EXCA_TOPIC97_CTRL,
598 		    EXCA_TOPIC97_CTRL_LV_MASK);
599 		goto topic_common;
600 	case CB_TOPIC95:
601 		/*
602 		 * SOCKETCTRL appears to be TOPIC 95/B specific
603 		 */
604 		PCI_MASK_CONFIG(sc->dev, TOPIC95_SOCKETCTRL,
605 		    | TOPIC95_SOCKETCTRL_SCR_IRQSEL, 4);
606 
607 	topic_common:;
608 		/*
609 		 * At offset 0xa0: SLOT CONTROL
610 		 * 0x80 Enable CardBus Functionality
611 		 * 0x40 Enable CardBus and PC Card registers
612 		 * 0x20 Lock ID in exca regs
613 		 * 0x10 Write protect ID in config regs
614 		 * Clear the rest of the bits, which defaults the slot
615 		 * in legacy mode to 0x3e0 and offset 0. (legacy
616 		 * mode is determined elsewhere)
617 		 */
618 		pci_write_config(sc->dev, TOPIC_SLOTCTRL,
619 		    TOPIC_SLOTCTRL_SLOTON |
620 		    TOPIC_SLOTCTRL_SLOTEN |
621 		    TOPIC_SLOTCTRL_ID_LOCK |
622 		    TOPIC_SLOTCTRL_ID_WP, 1);
623 
624 		/*
625 		 * At offset 0xa3 Card Detect Control Register
626 		 * 0x80 CARDBUS enbale
627 		 * 0x01 Cleared for hardware change detect
628 		 */
629 		PCI_MASK2_CONFIG(sc->dev, TOPIC_CDC,
630 		    | TOPIC_CDC_CARDBUS, & ~TOPIC_CDC_SWDETECT, 4);
631 		break;
632 	}
633 
634 	/*
635 	 * Need to tell ExCA registers to CSC interrupts route via PCI
636 	 * interrupts.  There are two ways to do this.  One is to set
637 	 * INTR_ENABLE and the other is to set CSC to 0.  Since both
638 	 * methods are mutually compatible, we do both.
639 	 */
640 	exca_putb(&sc->exca, EXCA_INTR, EXCA_INTR_ENABLE);
641 	exca_putb(&sc->exca, EXCA_CSC_INTR, 0);
642 
643 	cbb_disable_func_intr(sc);
644 
645 	/* close all memory and io windows */
646 	pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4);
647 	pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4);
648 	pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4);
649 	pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4);
650 	pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4);
651 	pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4);
652 	pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4);
653 	pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4);
654 }
655 
656 static int
657 cbb_route_interrupt(device_t pcib, device_t dev, int pin)
658 {
659 	struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(pcib);
660 
661 	return (rman_get_start(sc->irq_res));
662 }
663 
664 static int
665 cbb_pci_shutdown(device_t brdev)
666 {
667 	struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev);
668 
669 	/*
670 	 * We're about to pull the rug out from the card, so mark it as
671 	 * gone to prevent harm.
672          */
673         sc->cardok = 0;
674 
675 	/*
676 	 * Place the cards in reset, turn off the interrupts and power
677 	 * down the socket.
678 	 */
679 	PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2);
680 	exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET);
681 	cbb_set(sc, CBB_SOCKET_MASK, 0);
682 	cbb_set(sc, CBB_SOCKET_EVENT, 0xffffffff);
683 	cbb_power(brdev, CARD_OFF);
684 
685 	/*
686 	 * For paranoia, turn off all address decoding.  Really not needed,
687 	 * it seems, but it can't hurt
688 	 */
689 	exca_putb(&sc->exca, EXCA_ADDRWIN_ENABLE, 0);
690 	pci_write_config(brdev, CBBR_MEMBASE0, 0, 4);
691 	pci_write_config(brdev, CBBR_MEMLIMIT0, 0, 4);
692 	pci_write_config(brdev, CBBR_MEMBASE1, 0, 4);
693 	pci_write_config(brdev, CBBR_MEMLIMIT1, 0, 4);
694 	pci_write_config(brdev, CBBR_IOBASE0, 0, 4);
695 	pci_write_config(brdev, CBBR_IOLIMIT0, 0, 4);
696 	pci_write_config(brdev, CBBR_IOBASE1, 0, 4);
697 	pci_write_config(brdev, CBBR_IOLIMIT1, 0, 4);
698 	return (0);
699 }
700 
701 static int
702 cbb_pci_filt(void *arg)
703 {
704 	struct cbb_softc *sc = arg;
705 	uint32_t sockevent;
706 	uint8_t csc;
707 	int retval = FILTER_STRAY;
708 
709 	/*
710 	 * Some chips also require us to read the old ExCA registe for card
711 	 * status change when we route CSC vis PCI.  This isn't supposed to be
712 	 * required, but it clears the interrupt state on some chipsets.
713 	 * Maybe there's a setting that would obviate its need.  Maybe we
714 	 * should test the status bits and deal with them, but so far we've
715 	 * not found any machines that don't also give us the socket status
716 	 * indication above.
717 	 *
718 	 * This call used to be unconditional.  However, further research
719 	 * suggests that we hit this condition when the card READY interrupt
720 	 * fired.  So now we only read it for 16-bit cards, and we only claim
721 	 * the interrupt if READY is set.  If this still causes problems, then
722 	 * the next step would be to read this if we have a 16-bit card *OR*
723 	 * we have no card.  We treat the READY signal as if it were the power
724 	 * completion signal.  Some bridges may double signal things here, bit
725 	 * signalling twice should be OK since we only sleep on the powerintr
726 	 * in one place and a double wakeup would be benign there.
727 	 */
728 	if (sc->flags & CBB_16BIT_CARD) {
729 		csc = exca_getb(&sc->exca, EXCA_CSC);
730 		if (csc & EXCA_CSC_READY) {
731 			atomic_add_int(&sc->powerintr, 1);
732 			wakeup((void *)&sc->powerintr);
733 			retval = FILTER_HANDLED;
734 		}
735 	}
736 
737 	/*
738 	 * Read the socket event.  Sometimes, the theory goes, the PCI bus is
739 	 * so loaded that it cannot satisfy the read request, so we get
740 	 * garbage back from the following read.  We have to filter out the
741 	 * garbage so that we don't spontaneously reset the card under high
742 	 * load.  PCI isn't supposed to act like this.  No doubt this is a bug
743 	 * in the PCI bridge chipset (or cbb brige) that's being used in
744 	 * certain amd64 laptops today.  Work around the issue by assuming
745 	 * that any bits we don't know about being set means that we got
746 	 * garbage.
747 	 */
748 	sockevent = cbb_get(sc, CBB_SOCKET_EVENT);
749 	if (sockevent != 0 && (sockevent & ~CBB_SOCKET_EVENT_VALID_MASK) == 0) {
750 		/*
751 		 * If anything has happened to the socket, we assume that the
752 		 * card is no longer OK, and we shouldn't call its ISR.  We
753 		 * set cardok as soon as we've attached the card.  This helps
754 		 * in a noisy eject, which happens all too often when users
755 		 * are ejecting their PC Cards.
756 		 *
757 		 * We use this method in preference to checking to see if the
758 		 * card is still there because the check suffers from a race
759 		 * condition in the bouncing case.
760 		 */
761 #define DELTA (CBB_SOCKET_MASK_CD)
762 		if (sockevent & DELTA) {
763 			cbb_clrb(sc, CBB_SOCKET_MASK, DELTA);
764 			cbb_set(sc, CBB_SOCKET_EVENT, DELTA);
765 			sc->cardok = 0;
766 			cbb_disable_func_intr(sc);
767 			wakeup(&sc->intrhand);
768 		}
769 #undef DELTA
770 
771 		/*
772 		 * Wakeup anybody waiting for a power interrupt.  We have to
773 		 * use atomic_add_int for wakups on other cores.
774 		 */
775 		if (sockevent & CBB_SOCKET_EVENT_POWER) {
776 			cbb_clrb(sc, CBB_SOCKET_MASK, CBB_SOCKET_EVENT_POWER);
777 			cbb_set(sc, CBB_SOCKET_EVENT, CBB_SOCKET_EVENT_POWER);
778 			atomic_add_int(&sc->powerintr, 1);
779 			wakeup((void *)&sc->powerintr);
780 		}
781 
782 		/*
783 		 * Status change interrupts aren't presently used in the
784 		 * rest of the driver.  For now, just ACK them.
785 		 */
786 		if (sockevent & CBB_SOCKET_EVENT_CSTS)
787 			cbb_set(sc, CBB_SOCKET_EVENT, CBB_SOCKET_EVENT_CSTS);
788 		retval = FILTER_HANDLED;
789 	}
790 	return retval;
791 }
792 
793 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
794 static struct resource *
795 cbb_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
796     rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
797 {
798 	struct cbb_softc *sc;
799 
800 	sc = device_get_softc(bus);
801 	if (type == PCI_RES_BUS)
802 		return (pcib_alloc_subbus(&sc->bus, child, rid, start, end,
803 		    count, flags));
804 	return (cbb_alloc_resource(bus, child, type, rid, start, end, count,
805 	    flags));
806 }
807 
808 static int
809 cbb_pci_adjust_resource(device_t bus, device_t child, int type,
810     struct resource *r, rman_res_t start, rman_res_t end)
811 {
812 	struct cbb_softc *sc;
813 
814 	sc = device_get_softc(bus);
815 	if (type == PCI_RES_BUS) {
816 		if (!rman_is_region_manager(r, &sc->bus.rman))
817 			return (EINVAL);
818 		return (rman_adjust_resource(r, start, end));
819 	}
820 	return (bus_generic_adjust_resource(bus, child, type, r, start, end));
821 }
822 
823 static int
824 cbb_pci_release_resource(device_t bus, device_t child, int type, int rid,
825     struct resource *r)
826 {
827 	struct cbb_softc *sc;
828 	int error;
829 
830 	sc = device_get_softc(bus);
831 	if (type == PCI_RES_BUS) {
832 		if (!rman_is_region_manager(r, &sc->bus.rman))
833 			return (EINVAL);
834 		if (rman_get_flags(r) & RF_ACTIVE) {
835 			error = bus_deactivate_resource(child, type, rid, r);
836 			if (error)
837 				return (error);
838 		}
839 		return (rman_release_resource(r));
840 	}
841 	return (cbb_release_resource(bus, child, type, rid, r));
842 }
843 #endif
844 
845 /************************************************************************/
846 /* PCI compat methods							*/
847 /************************************************************************/
848 
849 static int
850 cbb_maxslots(device_t brdev)
851 {
852 	return (0);
853 }
854 
855 static uint32_t
856 cbb_read_config(device_t brdev, u_int b, u_int s, u_int f, u_int reg, int width)
857 {
858 	/*
859 	 * Pass through to the next ppb up the chain (i.e. our grandparent).
860 	 */
861 	return (PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)),
862 	    b, s, f, reg, width));
863 }
864 
865 static void
866 cbb_write_config(device_t brdev, u_int b, u_int s, u_int f, u_int reg, uint32_t val,
867     int width)
868 {
869 	/*
870 	 * Pass through to the next ppb up the chain (i.e. our grandparent).
871 	 */
872 	PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)),
873 	    b, s, f, reg, val, width);
874 }
875 
876 static int
877 cbb_pci_suspend(device_t brdev)
878 {
879 	int			error = 0;
880 	struct cbb_softc	*sc = device_get_softc(brdev);
881 
882 	error = bus_generic_suspend(brdev);
883 	if (error != 0)
884 		return (error);
885 	cbb_set(sc, CBB_SOCKET_MASK, 0);	/* Quiet hardware */
886 	sc->cardok = 0;				/* Card is bogus now */
887 	return (0);
888 }
889 
890 static int
891 cbb_pci_resume(device_t brdev)
892 {
893 	int	error = 0;
894 	struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev);
895 	uint32_t tmp;
896 
897 	/*
898 	 * In the APM and early ACPI era, BIOSes saved the PCI config
899 	 * registers. As chips became more complicated, that functionality moved
900 	 * into the ACPI code / tables. We must therefore, restore the settings
901 	 * we made here to make sure the device come back. Transitions to Dx
902 	 * from D0 and back to D0 cause the bridge to lose its config space, so
903 	 * all the bus mappings and such are preserved.
904 	 *
905 	 * The PCI layer handles standard PCI registers like the
906 	 * command register and BARs, but cbb-specific registers are
907 	 * handled here.
908 	 */
909 	sc->chipinit(sc);
910 
911 	/* reset interrupt -- Do we really need to do this? */
912 	tmp = cbb_get(sc, CBB_SOCKET_EVENT);
913 	cbb_set(sc, CBB_SOCKET_EVENT, tmp);
914 
915 	/* CSC Interrupt: Card detect interrupt on */
916 	cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD);
917 
918 	/* Signal the thread to wakeup. */
919 	wakeup(&sc->intrhand);
920 
921 	error = bus_generic_resume(brdev);
922 
923 	return (error);
924 }
925 
926 static device_method_t cbb_methods[] = {
927 	/* Device interface */
928 	DEVMETHOD(device_probe,			cbb_pci_probe),
929 	DEVMETHOD(device_attach,		cbb_pci_attach),
930 	DEVMETHOD(device_detach,		cbb_pci_detach),
931 	DEVMETHOD(device_shutdown,		cbb_pci_shutdown),
932 	DEVMETHOD(device_suspend,		cbb_pci_suspend),
933 	DEVMETHOD(device_resume,		cbb_pci_resume),
934 
935 	/* bus methods */
936 	DEVMETHOD(bus_read_ivar,		cbb_read_ivar),
937 	DEVMETHOD(bus_write_ivar,		cbb_write_ivar),
938 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
939 	DEVMETHOD(bus_alloc_resource,		cbb_pci_alloc_resource),
940 	DEVMETHOD(bus_adjust_resource,		cbb_pci_adjust_resource),
941 	DEVMETHOD(bus_release_resource,		cbb_pci_release_resource),
942 #else
943 	DEVMETHOD(bus_alloc_resource,		cbb_alloc_resource),
944 	DEVMETHOD(bus_release_resource,		cbb_release_resource),
945 #endif
946 	DEVMETHOD(bus_activate_resource,	cbb_activate_resource),
947 	DEVMETHOD(bus_deactivate_resource,	cbb_deactivate_resource),
948 	DEVMETHOD(bus_driver_added,		cbb_driver_added),
949 	DEVMETHOD(bus_child_detached,		cbb_child_detached),
950 	DEVMETHOD(bus_setup_intr,		cbb_setup_intr),
951 	DEVMETHOD(bus_teardown_intr,		cbb_teardown_intr),
952 	DEVMETHOD(bus_child_present,		cbb_child_present),
953 
954 	/* 16-bit card interface */
955 	DEVMETHOD(card_set_res_flags,		cbb_pcic_set_res_flags),
956 	DEVMETHOD(card_set_memory_offset,	cbb_pcic_set_memory_offset),
957 
958 	/* power interface */
959 	DEVMETHOD(power_enable_socket,		cbb_power_enable_socket),
960 	DEVMETHOD(power_disable_socket,		cbb_power_disable_socket),
961 
962 	/* pcib compatibility interface */
963 	DEVMETHOD(pcib_maxslots,		cbb_maxslots),
964 	DEVMETHOD(pcib_read_config,		cbb_read_config),
965 	DEVMETHOD(pcib_write_config,		cbb_write_config),
966 	DEVMETHOD(pcib_route_interrupt,		cbb_route_interrupt),
967 
968 	DEVMETHOD_END
969 };
970 
971 static driver_t cbb_driver = {
972 	"cbb",
973 	cbb_methods,
974 	sizeof(struct cbb_softc)
975 };
976 
977 DRIVER_MODULE(cbb, pci, cbb_driver, 0, 0);
978 MODULE_PNP_INFO("W32:vendor/device;D:#", pci, cbb, yc_chipsets,
979     nitems(yc_chipsets) - 1);
980 MODULE_DEPEND(cbb, exca, 1, 1, 1);
981