1#- 2# Copyright (c) 2015 M. Warner Losh <imp@FreeBSD.org> 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions 6# are met: 7# 1. Redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer. 9# 2. Redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution. 12# 13# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23# SUCH DAMAGE. 24# 25# 26 27#include <sys/bus.h> 28#include <dev/ow/owll.h> 29 30INTERFACE owll; 31 32# 33# Dallas Semiconductor 1-Wire bus Link Layer (owll) 34# 35# See Maxim Application Note AN937: Book of iButton Standards for the 36# 1-Wire protocol specification. 37# http://pdfserv.maximintegrated.com/en/an/AN937.pdf 38# 39# Note: 1-Wire is a registered trademark of Maxim Integrated Products, Inc. 40# 41# This file provides an interface to the logical layer of the protocol. 42# Although the first implementation is done with GPIO bit banging, some 43# SoCs have a 1-Wire controller with more smarts or hardware offload. 44# Maxim datasheets also describe how to use UARTs to generate timing, 45# as well as both usb and i2c 1-Wire controllers. 46# 47# Chapter 4 has all the electrical timing diagrams that make up the link 48# layer of this protocol. 49# 50# Two speed classes are defined: Regular speed and Overdrive speed. 51# It is the responsibility of a device implementing the owll(9) interface 52# to ensure that the timings are met: 53# 54# Regular Overdrive 55# 56# 60us <= tSLOT < 120us 6us <= tSLOT <= 16us 57# 60us <= tLOW0 < tSLOT < 120us 6us <= tLOW0 < tSLOT < 16us 58# 1us <= tLOW1 < 15us 1us <= tLOW < 2us 59# 1us < tLOWR < 15us 1us <= tLOWR < 2us 60# 0 <= tRELEASE < 45us 0 <= tRELEASE < 4us 61# 1us <= tREC < inf 1us <= tREC < inf 62# tRDV = 15us tRDV = 2us 63# 480us <= tRSTL < inf 48us <= tRSTL < 80us 64# 480us <= tRSTH < inf 48us <= tRSTH < inf 65# 15us < tPDH < 60us 2us <= tPDH < 6us 66# 60us < tPDL < 240us 8us <= tPDL < 24us 67# 68# In the diagrams below, R is driven by the resistor pullup, M is driven by 69# the master, and S is driven by the slave / target. 70# 71# All of these methods are expected to be called from the "network"/bus layer 72# for doing its operations. See 1wn_if.m for those. 73# 74# Note: This is the polling / busy-wait interface. An interrupt-based interface 75# may be different. But an interrupt-based, non-blocking interface can be tricky. 76# 77# Only the owbus should talk to this interface. 78# 79 80# WRITE-ONE (see above for timings) From Figure 4-1 AN-937 81# 82# |<---------tSLOT---->|<-tREC->| 83# High RRRRM | RRRRRRRRRRRR|RRRRRRRRM 84# M | R | | | M 85# M| R | | | M 86# Low MMMMMMM | | | MMMMMM... 87# |<-tLOW1->| | | 88# |<------15us--->| | 89# |<--------60us---->| 90# 91# 92METHOD int write_one { 93 device_t lldev; /* Link Level device (eg bridge) */ 94 struct ow_timing *timing; /* timing values */ 95}; 96 97 98# WRITE-ZERO (see above for timings) From Figure 4-2 AN-937 99# 100# |<---------tSLOT------>|<-tREC->| 101# High RRRRM | | |RRRRRRRM 102# M | | R M 103# M| | | |R M 104# Low MMMMMMMMMMMMMMMMMMMMMR MMMMMM... 105# |<--15us->| | | 106# |<------60us--->| | 107# |<-------tLOW0------>| 108# 109# 110METHOD int write_zero { 111 device_t lldev; /* Link Level device (eg bridge) */ 112 struct ow_timing *timing; /* timing values */ 113}; 114 115# READ-DATA (see above for timings) From Figure 4-3 AN-937 116# 117# |<---------tSLOT------>|<-tREC->| 118# High RRRRM | rrrrrrrrrrrrrrrRRRRRRRM 119# M | r | R M 120# M| r | |R M 121# Low MMMMMMMSSSSSSSSSSSSSSR MMMMMM... 122# |<tLOWR>< sample > | 123# |<------tRDV---->| | 124# ->| |<-tRELEASE 125# 126# r -- allowed to pull high via the resistor when slave writes a 1-bit 127# 128METHOD int read_data { 129 device_t lldev; /* Link Level device (eg bridge) */ 130 struct ow_timing *timing; /* timing values */ 131 int *bit; /* Bit we sampled */ 132}; 133 134# RESET AND PRESENCE PULSE (see above for timings) From Figure 4-4 AN-937 135# 136# |<---------tRSTH------------>| 137# High RRRM | | RRRRRRRS | RRRR RRM 138# M | |R| |S | R M 139# M| R | | S |R M 140# Low MMMMMMMM MMMMMM| | | SSSSSSSSSS MMMMMM 141# |<----tRSTL--->| | |<-tPDL---->| 142# | ->| |<-tR | | 143# |<tPDH>| 144# 145# Note: for Regular Speed operations, tRSTL + tR should be less than 960us to 146# avoid interfering with other devives on the bus. 147# 148# Returns errors associating with acquiring the bus, or EIO to indicate 149# that the bus was low during the RRRR time where it should have been 150# pulled high. The present field is always updated, even on error. 151# 152METHOD int reset_and_presence { 153 device_t lldev; /* Link level device (eg bridge) */ 154 struct ow_timing *timing; /* timing values */ 155 int *present; /* 0 = slave 1 = no slave -1 = bus error */ 156}; 157