1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (C) 2013 Emulex 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Emulex Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * Contact Information: 34 * freebsd-drivers@emulex.com 35 * 36 * Emulex 37 * 3333 Susan Street 38 * Costa Mesa, CA 92626 39 */ 40 41 /* $FreeBSD$ */ 42 43 #include "oce_if.h" 44 45 int 46 oce_wait_ready(POCE_SOFTC sc) 47 { 48 #define SLIPORT_READY_TIMEOUT 30000 49 uint32_t sliport_status, i; 50 51 if (!IS_XE201(sc)) 52 return (-1); 53 54 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) { 55 sliport_status = OCE_READ_REG32(sc, db, SLIPORT_STATUS_OFFSET); 56 if (sliport_status & SLIPORT_STATUS_RDY_MASK) 57 return 0; 58 59 if (sliport_status & SLIPORT_STATUS_ERR_MASK && 60 !(sliport_status & SLIPORT_STATUS_RN_MASK)) { 61 device_printf(sc->dev, "Error detected in the card\n"); 62 return EIO; 63 } 64 65 DELAY(1000); 66 } 67 68 device_printf(sc->dev, "Firmware wait timed out\n"); 69 70 return (-1); 71 } 72 73 /** 74 * @brief Reset (firmware) common function 75 * @param sc software handle to the device 76 * @returns 0 on success, ETIMEDOUT on failure 77 */ 78 int 79 oce_reset_fun(POCE_SOFTC sc) 80 { 81 struct oce_mbx *mbx; 82 struct oce_bmbx *mb; 83 struct ioctl_common_function_reset *fwcmd; 84 int rc = 0; 85 86 if (IS_XE201(sc)) { 87 OCE_WRITE_REG32(sc, db, SLIPORT_CONTROL_OFFSET, 88 SLI_PORT_CONTROL_IP_MASK); 89 90 rc = oce_wait_ready(sc); 91 if (rc) { 92 device_printf(sc->dev, "Firmware reset Failed\n"); 93 } 94 95 return rc; 96 } 97 98 mb = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx); 99 mbx = &mb->mbx; 100 bzero(mbx, sizeof(struct oce_mbx)); 101 102 fwcmd = (struct ioctl_common_function_reset *)&mbx->payload; 103 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 104 MBX_SUBSYSTEM_COMMON, 105 OPCODE_COMMON_FUNCTION_RESET, 106 10, /* MBX_TIMEOUT_SEC */ 107 sizeof(struct 108 ioctl_common_function_reset), 109 OCE_MBX_VER_V0); 110 111 mbx->u0.s.embedded = 1; 112 mbx->payload_length = 113 sizeof(struct ioctl_common_function_reset); 114 115 rc = oce_mbox_dispatch(sc, 2); 116 117 return rc; 118 } 119 120 121 /** 122 * @brief This funtions tells firmware we are 123 * done with commands. 124 * @param sc software handle to the device 125 * @returns 0 on success, ETIMEDOUT on failure 126 */ 127 int 128 oce_fw_clean(POCE_SOFTC sc) 129 { 130 struct oce_bmbx *mbx; 131 uint8_t *ptr; 132 int ret = 0; 133 134 mbx = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx); 135 ptr = (uint8_t *) &mbx->mbx; 136 137 /* Endian Signature */ 138 *ptr++ = 0xff; 139 *ptr++ = 0xaa; 140 *ptr++ = 0xbb; 141 *ptr++ = 0xff; 142 *ptr++ = 0xff; 143 *ptr++ = 0xcc; 144 *ptr++ = 0xdd; 145 *ptr = 0xff; 146 147 ret = oce_mbox_dispatch(sc, 2); 148 149 return ret; 150 } 151 152 153 /** 154 * @brief Mailbox wait 155 * @param sc software handle to the device 156 * @param tmo_sec timeout in seconds 157 */ 158 static int 159 oce_mbox_wait(POCE_SOFTC sc, uint32_t tmo_sec) 160 { 161 tmo_sec *= 10000; 162 pd_mpu_mbox_db_t mbox_db; 163 164 for (;;) { 165 if (tmo_sec != 0) { 166 if (--tmo_sec == 0) 167 break; 168 } 169 170 mbox_db.dw0 = OCE_READ_REG32(sc, db, PD_MPU_MBOX_DB); 171 172 if (mbox_db.bits.ready) 173 return 0; 174 175 DELAY(100); 176 } 177 178 device_printf(sc->dev, "Mailbox timed out\n"); 179 180 return ETIMEDOUT; 181 } 182 183 184 /** 185 * @brief Mailbox dispatch 186 * @param sc software handle to the device 187 * @param tmo_sec timeout in seconds 188 */ 189 int 190 oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec) 191 { 192 pd_mpu_mbox_db_t mbox_db; 193 uint32_t pa; 194 int rc; 195 196 oce_dma_sync(&sc->bsmbx, BUS_DMASYNC_PREWRITE); 197 pa = (uint32_t) ((uint64_t) sc->bsmbx.paddr >> 34); 198 bzero(&mbox_db, sizeof(pd_mpu_mbox_db_t)); 199 mbox_db.bits.ready = 0; 200 mbox_db.bits.hi = 1; 201 mbox_db.bits.address = pa; 202 203 rc = oce_mbox_wait(sc, tmo_sec); 204 if (rc == 0) { 205 OCE_WRITE_REG32(sc, db, PD_MPU_MBOX_DB, mbox_db.dw0); 206 207 pa = (uint32_t) ((uint64_t) sc->bsmbx.paddr >> 4) & 0x3fffffff; 208 mbox_db.bits.ready = 0; 209 mbox_db.bits.hi = 0; 210 mbox_db.bits.address = pa; 211 212 rc = oce_mbox_wait(sc, tmo_sec); 213 214 if (rc == 0) { 215 OCE_WRITE_REG32(sc, db, PD_MPU_MBOX_DB, mbox_db.dw0); 216 217 rc = oce_mbox_wait(sc, tmo_sec); 218 219 oce_dma_sync(&sc->bsmbx, BUS_DMASYNC_POSTWRITE); 220 } 221 } 222 223 return rc; 224 } 225 226 227 228 /** 229 * @brief Mailbox common request header initialization 230 * @param hdr mailbox header 231 * @param dom domain 232 * @param port port 233 * @param subsys subsystem 234 * @param opcode opcode 235 * @param timeout timeout 236 * @param pyld_len payload length 237 */ 238 void 239 mbx_common_req_hdr_init(struct mbx_hdr *hdr, 240 uint8_t dom, uint8_t port, 241 uint8_t subsys, uint8_t opcode, 242 uint32_t timeout, uint32_t pyld_len, 243 uint8_t version) 244 { 245 hdr->u0.req.opcode = opcode; 246 hdr->u0.req.subsystem = subsys; 247 hdr->u0.req.port_number = port; 248 hdr->u0.req.domain = dom; 249 250 hdr->u0.req.timeout = timeout; 251 hdr->u0.req.request_length = pyld_len - sizeof(struct mbx_hdr); 252 hdr->u0.req.version = version; 253 } 254 255 256 257 /** 258 * @brief Function to initialize the hw with host endian information 259 * @param sc software handle to the device 260 * @returns 0 on success, ETIMEDOUT on failure 261 */ 262 int 263 oce_mbox_init(POCE_SOFTC sc) 264 { 265 struct oce_bmbx *mbx; 266 uint8_t *ptr; 267 int ret = 0; 268 269 if (sc->flags & OCE_FLAGS_MBOX_ENDIAN_RQD) { 270 mbx = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx); 271 ptr = (uint8_t *) &mbx->mbx; 272 273 /* Endian Signature */ 274 *ptr++ = 0xff; 275 *ptr++ = 0x12; 276 *ptr++ = 0x34; 277 *ptr++ = 0xff; 278 *ptr++ = 0xff; 279 *ptr++ = 0x56; 280 *ptr++ = 0x78; 281 *ptr = 0xff; 282 283 ret = oce_mbox_dispatch(sc, 0); 284 } 285 286 return ret; 287 } 288 289 290 /** 291 * @brief Function to get the firmware version 292 * @param sc software handle to the device 293 * @returns 0 on success, EIO on failure 294 */ 295 int 296 oce_get_fw_version(POCE_SOFTC sc) 297 { 298 struct oce_mbx mbx; 299 struct mbx_get_common_fw_version *fwcmd; 300 int ret = 0; 301 302 bzero(&mbx, sizeof(struct oce_mbx)); 303 304 fwcmd = (struct mbx_get_common_fw_version *)&mbx.payload; 305 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 306 MBX_SUBSYSTEM_COMMON, 307 OPCODE_COMMON_GET_FW_VERSION, 308 MBX_TIMEOUT_SEC, 309 sizeof(struct mbx_get_common_fw_version), 310 OCE_MBX_VER_V0); 311 312 mbx.u0.s.embedded = 1; 313 mbx.payload_length = sizeof(struct mbx_get_common_fw_version); 314 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 315 316 ret = oce_mbox_post(sc, &mbx, NULL); 317 if (!ret) 318 ret = fwcmd->hdr.u0.rsp.status; 319 if (ret) { 320 device_printf(sc->dev, 321 "%s failed - cmd status: %d addi status: %d\n", 322 __FUNCTION__, ret, 323 fwcmd->hdr.u0.rsp.additional_status); 324 goto error; 325 } 326 327 bcopy(fwcmd->params.rsp.fw_ver_str, sc->fw_version, 32); 328 error: 329 return ret; 330 } 331 332 333 /** 334 * @brief Firmware will send gracious notifications during 335 * attach only after sending first mcc commnad. We 336 * use MCC queue only for getting async and mailbox 337 * for sending cmds. So to get gracious notifications 338 * atleast send one dummy command on mcc. 339 */ 340 int 341 oce_first_mcc_cmd(POCE_SOFTC sc) 342 { 343 struct oce_mbx *mbx; 344 struct oce_mq *mq = sc->mq; 345 struct mbx_get_common_fw_version *fwcmd; 346 uint32_t reg_value; 347 348 mbx = RING_GET_PRODUCER_ITEM_VA(mq->ring, struct oce_mbx); 349 bzero(mbx, sizeof(struct oce_mbx)); 350 351 fwcmd = (struct mbx_get_common_fw_version *)&mbx->payload; 352 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 353 MBX_SUBSYSTEM_COMMON, 354 OPCODE_COMMON_GET_FW_VERSION, 355 MBX_TIMEOUT_SEC, 356 sizeof(struct mbx_get_common_fw_version), 357 OCE_MBX_VER_V0); 358 mbx->u0.s.embedded = 1; 359 mbx->payload_length = sizeof(struct mbx_get_common_fw_version); 360 bus_dmamap_sync(mq->ring->dma.tag, mq->ring->dma.map, 361 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 362 RING_PUT(mq->ring, 1); 363 reg_value = (1 << 16) | mq->mq_id; 364 OCE_WRITE_REG32(sc, db, PD_MQ_DB, reg_value); 365 366 return 0; 367 } 368 369 /** 370 * @brief Function to post a MBX to the mbox 371 * @param sc software handle to the device 372 * @param mbx pointer to the MBX to send 373 * @param mbxctx pointer to the mbx context structure 374 * @returns 0 on success, error on failure 375 */ 376 int 377 oce_mbox_post(POCE_SOFTC sc, struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx) 378 { 379 struct oce_mbx *mb_mbx = NULL; 380 struct oce_mq_cqe *mb_cqe = NULL; 381 struct oce_bmbx *mb = NULL; 382 int rc = 0; 383 uint32_t tmo = 0; 384 uint32_t cstatus = 0; 385 uint32_t xstatus = 0; 386 387 LOCK(&sc->bmbx_lock); 388 389 mb = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx); 390 mb_mbx = &mb->mbx; 391 392 /* get the tmo */ 393 tmo = mbx->tag[0]; 394 mbx->tag[0] = 0; 395 396 /* copy mbx into mbox */ 397 bcopy(mbx, mb_mbx, sizeof(struct oce_mbx)); 398 399 /* now dispatch */ 400 rc = oce_mbox_dispatch(sc, tmo); 401 if (rc == 0) { 402 /* 403 * the command completed successfully. Now get the 404 * completion queue entry 405 */ 406 mb_cqe = &mb->cqe; 407 DW_SWAP(u32ptr(&mb_cqe->u0.dw[0]), sizeof(struct oce_mq_cqe)); 408 409 /* copy mbox mbx back */ 410 bcopy(mb_mbx, mbx, sizeof(struct oce_mbx)); 411 412 /* pick up the mailbox status */ 413 cstatus = mb_cqe->u0.s.completion_status; 414 xstatus = mb_cqe->u0.s.extended_status; 415 416 /* 417 * store the mbx context in the cqe tag section so that 418 * the upper layer handling the cqe can associate the mbx 419 * with the response 420 */ 421 if (cstatus == 0 && mbxctx) { 422 /* save context */ 423 mbxctx->mbx = mb_mbx; 424 bcopy(&mbxctx, mb_cqe->u0.s.mq_tag, 425 sizeof(struct oce_mbx_ctx *)); 426 } 427 } 428 429 UNLOCK(&sc->bmbx_lock); 430 431 return rc; 432 } 433 434 /** 435 * @brief Function to read the mac address associated with an interface 436 * @param sc software handle to the device 437 * @param if_id interface id to read the address from 438 * @param perm set to 1 if reading the factory mac address. 439 * In this case if_id is ignored 440 * @param type type of the mac address, whether network or storage 441 * @param[out] mac [OUTPUT] pointer to a buffer containing the 442 * mac address when the command succeeds. 443 * @returns 0 on success, EIO on failure 444 */ 445 int 446 oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id, 447 uint8_t perm, uint8_t type, struct mac_address_format *mac) 448 { 449 struct oce_mbx mbx; 450 struct mbx_query_common_iface_mac *fwcmd; 451 int ret = 0; 452 453 bzero(&mbx, sizeof(struct oce_mbx)); 454 455 fwcmd = (struct mbx_query_common_iface_mac *)&mbx.payload; 456 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 457 MBX_SUBSYSTEM_COMMON, 458 OPCODE_COMMON_QUERY_IFACE_MAC, 459 MBX_TIMEOUT_SEC, 460 sizeof(struct mbx_query_common_iface_mac), 461 OCE_MBX_VER_V0); 462 463 fwcmd->params.req.permanent = perm; 464 if (!perm) 465 fwcmd->params.req.if_id = (uint16_t) if_id; 466 else 467 fwcmd->params.req.if_id = 0; 468 469 fwcmd->params.req.type = type; 470 471 mbx.u0.s.embedded = 1; 472 mbx.payload_length = sizeof(struct mbx_query_common_iface_mac); 473 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 474 475 ret = oce_mbox_post(sc, &mbx, NULL); 476 if (!ret) 477 ret = fwcmd->hdr.u0.rsp.status; 478 if (ret) { 479 device_printf(sc->dev, 480 "%s failed - cmd status: %d addi status: %d\n", 481 __FUNCTION__, ret, 482 fwcmd->hdr.u0.rsp.additional_status); 483 goto error; 484 } 485 486 /* copy the mac addres in the output parameter */ 487 mac->size_of_struct = fwcmd->params.rsp.mac.size_of_struct; 488 bcopy(&fwcmd->params.rsp.mac.mac_addr[0], &mac->mac_addr[0], 489 mac->size_of_struct); 490 error: 491 return ret; 492 } 493 494 /** 495 * @brief Function to query the fw attributes from the hw 496 * @param sc software handle to the device 497 * @returns 0 on success, EIO on failure 498 */ 499 int 500 oce_get_fw_config(POCE_SOFTC sc) 501 { 502 struct oce_mbx mbx; 503 struct mbx_common_query_fw_config *fwcmd; 504 int ret = 0; 505 506 bzero(&mbx, sizeof(struct oce_mbx)); 507 508 fwcmd = (struct mbx_common_query_fw_config *)&mbx.payload; 509 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 510 MBX_SUBSYSTEM_COMMON, 511 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, 512 MBX_TIMEOUT_SEC, 513 sizeof(struct mbx_common_query_fw_config), 514 OCE_MBX_VER_V0); 515 516 mbx.u0.s.embedded = 1; 517 mbx.payload_length = sizeof(struct mbx_common_query_fw_config); 518 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 519 520 ret = oce_mbox_post(sc, &mbx, NULL); 521 if (!ret) 522 ret = fwcmd->hdr.u0.rsp.status; 523 if (ret) { 524 device_printf(sc->dev, 525 "%s failed - cmd status: %d addi status: %d\n", 526 __FUNCTION__, ret, 527 fwcmd->hdr.u0.rsp.additional_status); 528 goto error; 529 } 530 531 DW_SWAP(u32ptr(fwcmd), sizeof(struct mbx_common_query_fw_config)); 532 533 sc->config_number = HOST_32(fwcmd->params.rsp.config_number); 534 sc->asic_revision = HOST_32(fwcmd->params.rsp.asic_revision); 535 sc->port_id = HOST_32(fwcmd->params.rsp.port_id); 536 sc->function_mode = HOST_32(fwcmd->params.rsp.function_mode); 537 if ((sc->function_mode & (ULP_NIC_MODE | ULP_RDMA_MODE)) == 538 (ULP_NIC_MODE | ULP_RDMA_MODE)) { 539 sc->rdma_flags = OCE_RDMA_FLAG_SUPPORTED; 540 } 541 sc->function_caps = HOST_32(fwcmd->params.rsp.function_caps); 542 543 if (fwcmd->params.rsp.ulp[0].ulp_mode & ULP_NIC_MODE) { 544 sc->max_tx_rings = HOST_32(fwcmd->params.rsp.ulp[0].nic_wq_tot); 545 sc->max_rx_rings = HOST_32(fwcmd->params.rsp.ulp[0].lro_rqid_tot); 546 } else { 547 sc->max_tx_rings = HOST_32(fwcmd->params.rsp.ulp[1].nic_wq_tot); 548 sc->max_rx_rings = HOST_32(fwcmd->params.rsp.ulp[1].lro_rqid_tot); 549 } 550 551 error: 552 return ret; 553 554 } 555 556 /** 557 * 558 * @brief function to create a device interface 559 * @param sc software handle to the device 560 * @param cap_flags capability flags 561 * @param en_flags enable capability flags 562 * @param vlan_tag optional vlan tag to associate with the if 563 * @param mac_addr pointer to a buffer containing the mac address 564 * @param[out] if_id [OUTPUT] pointer to an integer to hold the ID of the 565 interface created 566 * @returns 0 on success, EIO on failure 567 */ 568 int 569 oce_if_create(POCE_SOFTC sc, 570 uint32_t cap_flags, 571 uint32_t en_flags, 572 uint16_t vlan_tag, 573 uint8_t *mac_addr, 574 uint32_t *if_id) 575 { 576 struct oce_mbx mbx; 577 struct mbx_create_common_iface *fwcmd; 578 int rc = 0; 579 580 bzero(&mbx, sizeof(struct oce_mbx)); 581 582 fwcmd = (struct mbx_create_common_iface *)&mbx.payload; 583 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 584 MBX_SUBSYSTEM_COMMON, 585 OPCODE_COMMON_CREATE_IFACE, 586 MBX_TIMEOUT_SEC, 587 sizeof(struct mbx_create_common_iface), 588 OCE_MBX_VER_V0); 589 DW_SWAP(u32ptr(&fwcmd->hdr), sizeof(struct mbx_hdr)); 590 591 fwcmd->params.req.version = 0; 592 fwcmd->params.req.cap_flags = LE_32(cap_flags); 593 fwcmd->params.req.enable_flags = LE_32(en_flags); 594 if (mac_addr != NULL) { 595 bcopy(mac_addr, &fwcmd->params.req.mac_addr[0], 6); 596 fwcmd->params.req.vlan_tag.u0.normal.vtag = LE_16(vlan_tag); 597 fwcmd->params.req.mac_invalid = 0; 598 } else { 599 fwcmd->params.req.mac_invalid = 1; 600 } 601 602 mbx.u0.s.embedded = 1; 603 mbx.payload_length = sizeof(struct mbx_create_common_iface); 604 DW_SWAP(u32ptr(&mbx), OCE_BMBX_RHDR_SZ); 605 606 rc = oce_mbox_post(sc, &mbx, NULL); 607 if (!rc) 608 rc = fwcmd->hdr.u0.rsp.status; 609 if (rc) { 610 device_printf(sc->dev, 611 "%s failed - cmd status: %d addi status: %d\n", 612 __FUNCTION__, rc, 613 fwcmd->hdr.u0.rsp.additional_status); 614 goto error; 615 } 616 617 *if_id = HOST_32(fwcmd->params.rsp.if_id); 618 619 if (mac_addr != NULL) 620 sc->pmac_id = HOST_32(fwcmd->params.rsp.pmac_id); 621 error: 622 return rc; 623 } 624 625 /** 626 * @brief Function to delete an interface 627 * @param sc software handle to the device 628 * @param if_id ID of the interface to delete 629 * @returns 0 on success, EIO on failure 630 */ 631 int 632 oce_if_del(POCE_SOFTC sc, uint32_t if_id) 633 { 634 struct oce_mbx mbx; 635 struct mbx_destroy_common_iface *fwcmd; 636 int rc = 0; 637 638 bzero(&mbx, sizeof(struct oce_mbx)); 639 640 fwcmd = (struct mbx_destroy_common_iface *)&mbx.payload; 641 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 642 MBX_SUBSYSTEM_COMMON, 643 OPCODE_COMMON_DESTROY_IFACE, 644 MBX_TIMEOUT_SEC, 645 sizeof(struct mbx_destroy_common_iface), 646 OCE_MBX_VER_V0); 647 648 fwcmd->params.req.if_id = if_id; 649 650 mbx.u0.s.embedded = 1; 651 mbx.payload_length = sizeof(struct mbx_destroy_common_iface); 652 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 653 654 rc = oce_mbox_post(sc, &mbx, NULL); 655 if (!rc) 656 rc = fwcmd->hdr.u0.rsp.status; 657 if (rc) 658 device_printf(sc->dev, 659 "%s failed - cmd status: %d addi status: %d\n", 660 __FUNCTION__, rc, 661 fwcmd->hdr.u0.rsp.additional_status); 662 return rc; 663 } 664 665 /** 666 * @brief Function to send the mbx command to configure vlan 667 * @param sc software handle to the device 668 * @param if_id interface identifier index 669 * @param vtag_arr array of vlan tags 670 * @param vtag_cnt number of elements in array 671 * @param untagged boolean TRUE/FLASE 672 * @param enable_promisc flag to enable/disable VLAN promiscuous mode 673 * @returns 0 on success, EIO on failure 674 */ 675 int 676 oce_config_vlan(POCE_SOFTC sc, 677 uint32_t if_id, 678 struct normal_vlan *vtag_arr, 679 uint8_t vtag_cnt, uint32_t untagged, uint32_t enable_promisc) 680 { 681 struct oce_mbx mbx; 682 struct mbx_common_config_vlan *fwcmd; 683 int rc = 0; 684 685 if (sc->vlans_added > sc->max_vlans) 686 goto vlan_promisc; 687 688 bzero(&mbx, sizeof(struct oce_mbx)); 689 fwcmd = (struct mbx_common_config_vlan *)&mbx.payload; 690 691 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 692 MBX_SUBSYSTEM_COMMON, 693 OPCODE_COMMON_CONFIG_IFACE_VLAN, 694 MBX_TIMEOUT_SEC, 695 sizeof(struct mbx_common_config_vlan), 696 OCE_MBX_VER_V0); 697 698 fwcmd->params.req.if_id = (uint8_t) if_id; 699 fwcmd->params.req.promisc = (uint8_t) enable_promisc; 700 fwcmd->params.req.untagged = (uint8_t) untagged; 701 fwcmd->params.req.num_vlans = vtag_cnt; 702 703 if (!enable_promisc) { 704 bcopy(vtag_arr, fwcmd->params.req.tags.normal_vlans, 705 vtag_cnt * sizeof(struct normal_vlan)); 706 } 707 mbx.u0.s.embedded = 1; 708 mbx.payload_length = sizeof(struct mbx_common_config_vlan); 709 DW_SWAP(u32ptr(&mbx), (OCE_BMBX_RHDR_SZ + mbx.payload_length)); 710 711 rc = oce_mbox_post(sc, &mbx, NULL); 712 if (!rc) 713 rc = fwcmd->hdr.u0.rsp.status; 714 if (rc) 715 device_printf(sc->dev, 716 "%s failed - cmd status: %d addi status: %d\n", 717 __FUNCTION__, rc, 718 fwcmd->hdr.u0.rsp.additional_status); 719 720 goto done; 721 722 vlan_promisc: 723 /* Enable Vlan Promis */ 724 oce_rxf_set_promiscuous(sc, (1 << 1)); 725 device_printf(sc->dev,"Enabling Vlan Promisc Mode\n"); 726 done: 727 return rc; 728 729 } 730 731 /** 732 * @brief Function to set flow control capability in the hardware 733 * @param sc software handle to the device 734 * @param flow_control flow control flags to set 735 * @returns 0 on success, EIO on failure 736 */ 737 int 738 oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control) 739 { 740 struct oce_mbx mbx; 741 struct mbx_common_get_set_flow_control *fwcmd = 742 (struct mbx_common_get_set_flow_control *)&mbx.payload; 743 int rc; 744 745 bzero(&mbx, sizeof(struct oce_mbx)); 746 747 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 748 MBX_SUBSYSTEM_COMMON, 749 OPCODE_COMMON_SET_FLOW_CONTROL, 750 MBX_TIMEOUT_SEC, 751 sizeof(struct mbx_common_get_set_flow_control), 752 OCE_MBX_VER_V0); 753 754 if (flow_control & OCE_FC_TX) 755 fwcmd->tx_flow_control = 1; 756 757 if (flow_control & OCE_FC_RX) 758 fwcmd->rx_flow_control = 1; 759 760 mbx.u0.s.embedded = 1; 761 mbx.payload_length = sizeof(struct mbx_common_get_set_flow_control); 762 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 763 764 rc = oce_mbox_post(sc, &mbx, NULL); 765 if (!rc) 766 rc = fwcmd->hdr.u0.rsp.status; 767 if (rc) 768 device_printf(sc->dev, 769 "%s failed - cmd status: %d addi status: %d\n", 770 __FUNCTION__, rc, 771 fwcmd->hdr.u0.rsp.additional_status); 772 return rc; 773 } 774 775 /** 776 * @brief Initialize the RSS CPU indirection table 777 * 778 * The table is used to choose the queue to place the incomming packets. 779 * Incomming packets are hashed. The lowest bits in the hash result 780 * are used as the index into the CPU indirection table. 781 * Each entry in the table contains the RSS CPU-ID returned by the NIC 782 * create. Based on the CPU ID, the receive completion is routed to 783 * the corresponding RSS CQs. (Non-RSS packets are always completed 784 * on the default (0) CQ). 785 * 786 * @param sc software handle to the device 787 * @param *fwcmd pointer to the rss mbox command 788 * @returns none 789 */ 790 static int 791 oce_rss_itbl_init(POCE_SOFTC sc, struct mbx_config_nic_rss *fwcmd) 792 { 793 int i = 0, j = 0, rc = 0; 794 uint8_t *tbl = fwcmd->params.req.cputable; 795 struct oce_rq *rq = NULL; 796 797 798 for (j = 0; j < INDIRECTION_TABLE_ENTRIES ; j += (sc->nrqs - 1)) { 799 for_all_rss_queues(sc, rq, i) { 800 if ((j + i) >= INDIRECTION_TABLE_ENTRIES) 801 break; 802 tbl[j + i] = rq->rss_cpuid; 803 } 804 } 805 if (i == 0) { 806 device_printf(sc->dev, "error: Invalid number of RSS RQ's\n"); 807 rc = ENXIO; 808 809 } 810 811 /* fill log2 value indicating the size of the CPU table */ 812 if (rc == 0) 813 fwcmd->params.req.cpu_tbl_sz_log2 = LE_16(OCE_LOG2(INDIRECTION_TABLE_ENTRIES)); 814 815 return rc; 816 } 817 818 /** 819 * @brief Function to set flow control capability in the hardware 820 * @param sc software handle to the device 821 * @param if_id interface id to read the address from 822 * @param enable_rss 0=disable, RSS_ENABLE_xxx flags otherwise 823 * @returns 0 on success, EIO on failure 824 */ 825 int 826 oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss) 827 { 828 int rc; 829 struct oce_mbx mbx; 830 struct mbx_config_nic_rss *fwcmd = 831 (struct mbx_config_nic_rss *)&mbx.payload; 832 int version; 833 834 bzero(&mbx, sizeof(struct oce_mbx)); 835 836 if (IS_XE201(sc) || IS_SH(sc)) { 837 version = OCE_MBX_VER_V1; 838 fwcmd->params.req.enable_rss = RSS_ENABLE_UDP_IPV4 | 839 RSS_ENABLE_UDP_IPV6; 840 } else 841 version = OCE_MBX_VER_V0; 842 843 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 844 MBX_SUBSYSTEM_NIC, 845 NIC_CONFIG_RSS, 846 MBX_TIMEOUT_SEC, 847 sizeof(struct mbx_config_nic_rss), 848 version); 849 if (enable_rss) 850 fwcmd->params.req.enable_rss |= (RSS_ENABLE_IPV4 | 851 RSS_ENABLE_TCP_IPV4 | 852 RSS_ENABLE_IPV6 | 853 RSS_ENABLE_TCP_IPV6); 854 855 if(!sc->enable_hwlro) 856 fwcmd->params.req.flush = OCE_FLUSH; 857 else 858 fwcmd->params.req.flush = 0; 859 860 fwcmd->params.req.if_id = LE_32(if_id); 861 862 read_random(fwcmd->params.req.hash, sizeof(fwcmd->params.req.hash)); 863 864 rc = oce_rss_itbl_init(sc, fwcmd); 865 if (rc == 0) { 866 mbx.u0.s.embedded = 1; 867 mbx.payload_length = sizeof(struct mbx_config_nic_rss); 868 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 869 870 rc = oce_mbox_post(sc, &mbx, NULL); 871 if (!rc) 872 rc = fwcmd->hdr.u0.rsp.status; 873 if (rc) 874 device_printf(sc->dev, 875 "%s failed - cmd status: %d addi status: %d\n", 876 __FUNCTION__, rc, 877 fwcmd->hdr.u0.rsp.additional_status); 878 } 879 return rc; 880 } 881 882 /** 883 * @brief RXF function to enable/disable device promiscuous mode 884 * @param sc software handle to the device 885 * @param enable enable/disable flag 886 * @returns 0 on success, EIO on failure 887 * @note 888 * The NIC_CONFIG_PROMISCUOUS command deprecated for Lancer. 889 * This function uses the COMMON_SET_IFACE_RX_FILTER command instead. 890 */ 891 int 892 oce_rxf_set_promiscuous(POCE_SOFTC sc, uint8_t enable) 893 { 894 struct mbx_set_common_iface_rx_filter *fwcmd; 895 int sz = sizeof(struct mbx_set_common_iface_rx_filter); 896 iface_rx_filter_ctx_t *req; 897 OCE_DMA_MEM sgl; 898 int rc; 899 900 /* allocate mbx payload's dma scatter/gather memory */ 901 rc = oce_dma_alloc(sc, sz, &sgl, 0); 902 if (rc) 903 return rc; 904 905 fwcmd = OCE_DMAPTR(&sgl, struct mbx_set_common_iface_rx_filter); 906 907 req = &fwcmd->params.req; 908 req->iface_flags_mask = MBX_RX_IFACE_FLAGS_PROMISCUOUS | 909 MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS; 910 /* Bit 0 Mac promisc, Bit 1 Vlan promisc */ 911 if (enable & 0x01) 912 req->iface_flags = MBX_RX_IFACE_FLAGS_PROMISCUOUS; 913 914 if (enable & 0x02) 915 req->iface_flags |= MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS; 916 917 req->if_id = sc->if_id; 918 919 rc = oce_set_common_iface_rx_filter(sc, &sgl); 920 oce_dma_free(sc, &sgl); 921 922 return rc; 923 } 924 925 926 /** 927 * @brief Function modify and select rx filter options 928 * @param sc software handle to the device 929 * @param sgl scatter/gather request/response 930 * @returns 0 on success, error code on failure 931 */ 932 int 933 oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl) 934 { 935 struct oce_mbx mbx; 936 int mbx_sz = sizeof(struct mbx_set_common_iface_rx_filter); 937 struct mbx_set_common_iface_rx_filter *fwcmd; 938 int rc; 939 940 bzero(&mbx, sizeof(struct oce_mbx)); 941 fwcmd = OCE_DMAPTR(sgl, struct mbx_set_common_iface_rx_filter); 942 943 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 944 MBX_SUBSYSTEM_COMMON, 945 OPCODE_COMMON_SET_IFACE_RX_FILTER, 946 MBX_TIMEOUT_SEC, 947 mbx_sz, 948 OCE_MBX_VER_V0); 949 950 oce_dma_sync(sgl, BUS_DMASYNC_PREWRITE); 951 mbx.u0.s.embedded = 0; 952 mbx.u0.s.sge_count = 1; 953 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(sgl->paddr); 954 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(sgl->paddr); 955 mbx.payload.u0.u1.sgl[0].length = mbx_sz; 956 mbx.payload_length = mbx_sz; 957 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 958 959 rc = oce_mbox_post(sc, &mbx, NULL); 960 if (!rc) 961 rc = fwcmd->hdr.u0.rsp.status; 962 if (rc) 963 device_printf(sc->dev, 964 "%s failed - cmd status: %d addi status: %d\n", 965 __FUNCTION__, rc, 966 fwcmd->hdr.u0.rsp.additional_status); 967 return rc; 968 } 969 970 /** 971 * @brief Function to query the link status from the hardware 972 * @param sc software handle to the device 973 * @param[out] link pointer to the structure returning link attributes 974 * @returns 0 on success, EIO on failure 975 */ 976 int 977 oce_get_link_status(POCE_SOFTC sc, struct link_status *link) 978 { 979 struct oce_mbx mbx; 980 struct mbx_query_common_link_config *fwcmd; 981 int rc = 0, version; 982 983 bzero(&mbx, sizeof(struct oce_mbx)); 984 985 IS_BE2(sc) ? (version = OCE_MBX_VER_V0) : (version = OCE_MBX_VER_V1); 986 987 fwcmd = (struct mbx_query_common_link_config *)&mbx.payload; 988 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 989 MBX_SUBSYSTEM_COMMON, 990 OPCODE_COMMON_QUERY_LINK_CONFIG, 991 MBX_TIMEOUT_SEC, 992 sizeof(struct mbx_query_common_link_config), 993 version); 994 995 mbx.u0.s.embedded = 1; 996 mbx.payload_length = sizeof(struct mbx_query_common_link_config); 997 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 998 999 rc = oce_mbox_post(sc, &mbx, NULL); 1000 1001 if (!rc) 1002 rc = fwcmd->hdr.u0.rsp.status; 1003 if (rc) { 1004 device_printf(sc->dev, 1005 "%s failed - cmd status: %d addi status: %d\n", 1006 __FUNCTION__, rc, 1007 fwcmd->hdr.u0.rsp.additional_status); 1008 goto error; 1009 } 1010 /* interpret response */ 1011 link->qos_link_speed = HOST_16(fwcmd->params.rsp.qos_link_speed); 1012 link->phys_port_speed = fwcmd->params.rsp.physical_port_speed; 1013 link->logical_link_status = fwcmd->params.rsp.logical_link_status; 1014 error: 1015 return rc; 1016 } 1017 1018 1019 /** 1020 * @brief Function to get NIC statistics 1021 * @param sc software handle to the device 1022 * @param *stats pointer to where to store statistics 1023 * @param reset_stats resets statistics of set 1024 * @returns 0 on success, EIO on failure 1025 * @note command depricated in Lancer 1026 */ 1027 #define OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, version) \ 1028 int \ 1029 oce_mbox_get_nic_stats_v##version(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem) \ 1030 { \ 1031 struct oce_mbx mbx; \ 1032 struct mbx_get_nic_stats_v##version *fwcmd; \ 1033 int rc = 0; \ 1034 \ 1035 bzero(&mbx, sizeof(struct oce_mbx)); \ 1036 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_nic_stats_v##version); \ 1037 bzero(fwcmd, sizeof(*fwcmd)); \ 1038 \ 1039 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, \ 1040 MBX_SUBSYSTEM_NIC, \ 1041 NIC_GET_STATS, \ 1042 MBX_TIMEOUT_SEC, \ 1043 sizeof(*fwcmd), \ 1044 OCE_MBX_VER_V##version); \ 1045 \ 1046 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */ \ 1047 mbx.u0.s.sge_count = 1; /* using scatter gather instead */ \ 1048 \ 1049 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE); \ 1050 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr); \ 1051 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr); \ 1052 mbx.payload.u0.u1.sgl[0].length = sizeof(*fwcmd); \ 1053 mbx.payload_length = sizeof(*fwcmd); \ 1054 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); \ 1055 \ 1056 rc = oce_mbox_post(sc, &mbx, NULL); \ 1057 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE); \ 1058 if (!rc) \ 1059 rc = fwcmd->hdr.u0.rsp.status; \ 1060 if (rc) \ 1061 device_printf(sc->dev, \ 1062 "%s failed - cmd status: %d addi status: %d\n", \ 1063 __FUNCTION__, rc, \ 1064 fwcmd->hdr.u0.rsp.additional_status); \ 1065 return rc; \ 1066 } 1067 1068 OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 0); 1069 OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 1); 1070 OCE_MBOX_GET_NIC_STATS(sc, pstats_dma_mem, 2); 1071 1072 1073 /** 1074 * @brief Function to get pport (physical port) statistics 1075 * @param sc software handle to the device 1076 * @param *stats pointer to where to store statistics 1077 * @param reset_stats resets statistics of set 1078 * @returns 0 on success, EIO on failure 1079 */ 1080 int 1081 oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem, 1082 uint32_t reset_stats) 1083 { 1084 struct oce_mbx mbx; 1085 struct mbx_get_pport_stats *fwcmd; 1086 int rc = 0; 1087 1088 bzero(&mbx, sizeof(struct oce_mbx)); 1089 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_pport_stats); 1090 bzero(fwcmd, sizeof(struct mbx_get_pport_stats)); 1091 1092 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1093 MBX_SUBSYSTEM_NIC, 1094 NIC_GET_PPORT_STATS, 1095 MBX_TIMEOUT_SEC, 1096 sizeof(struct mbx_get_pport_stats), 1097 OCE_MBX_VER_V0); 1098 1099 fwcmd->params.req.reset_stats = reset_stats; 1100 fwcmd->params.req.port_number = sc->port_id; 1101 1102 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */ 1103 mbx.u0.s.sge_count = 1; /* using scatter gather instead */ 1104 1105 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE); 1106 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr); 1107 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr); 1108 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_pport_stats); 1109 1110 mbx.payload_length = sizeof(struct mbx_get_pport_stats); 1111 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1112 1113 rc = oce_mbox_post(sc, &mbx, NULL); 1114 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE); 1115 1116 if (!rc) 1117 rc = fwcmd->hdr.u0.rsp.status; 1118 if (rc) 1119 device_printf(sc->dev, 1120 "%s failed - cmd status: %d addi status: %d\n", 1121 __FUNCTION__, rc, 1122 fwcmd->hdr.u0.rsp.additional_status); 1123 return rc; 1124 } 1125 1126 1127 /** 1128 * @brief Function to get vport (virtual port) statistics 1129 * @param sc software handle to the device 1130 * @param *stats pointer to where to store statistics 1131 * @param reset_stats resets statistics of set 1132 * @returns 0 on success, EIO on failure 1133 */ 1134 int 1135 oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem, 1136 uint32_t req_size, uint32_t reset_stats) 1137 { 1138 struct oce_mbx mbx; 1139 struct mbx_get_vport_stats *fwcmd; 1140 int rc = 0; 1141 1142 bzero(&mbx, sizeof(struct oce_mbx)); 1143 1144 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_vport_stats); 1145 bzero(fwcmd, sizeof(struct mbx_get_vport_stats)); 1146 1147 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1148 MBX_SUBSYSTEM_NIC, 1149 NIC_GET_VPORT_STATS, 1150 MBX_TIMEOUT_SEC, 1151 sizeof(struct mbx_get_vport_stats), 1152 OCE_MBX_VER_V0); 1153 1154 fwcmd->params.req.reset_stats = reset_stats; 1155 fwcmd->params.req.vport_number = sc->if_id; 1156 1157 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */ 1158 mbx.u0.s.sge_count = 1; /* using scatter gather instead */ 1159 1160 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE); 1161 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr); 1162 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr); 1163 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_vport_stats); 1164 1165 mbx.payload_length = sizeof(struct mbx_get_vport_stats); 1166 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1167 1168 rc = oce_mbox_post(sc, &mbx, NULL); 1169 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE); 1170 1171 if (!rc) 1172 rc = fwcmd->hdr.u0.rsp.status; 1173 if (rc) 1174 device_printf(sc->dev, 1175 "%s failed - cmd status: %d addi status: %d\n", 1176 __FUNCTION__, rc, 1177 fwcmd->hdr.u0.rsp.additional_status); 1178 return rc; 1179 } 1180 1181 1182 /** 1183 * @brief Function to update the muticast filter with 1184 * values in dma_mem 1185 * @param sc software handle to the device 1186 * @param dma_mem pointer to dma memory region 1187 * @returns 0 on success, EIO on failure 1188 */ 1189 int 1190 oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem) 1191 { 1192 struct oce_mbx mbx; 1193 struct oce_mq_sge *sgl; 1194 struct mbx_set_common_iface_multicast *req = NULL; 1195 int rc = 0; 1196 1197 req = OCE_DMAPTR(pdma_mem, struct mbx_set_common_iface_multicast); 1198 mbx_common_req_hdr_init(&req->hdr, 0, 0, 1199 MBX_SUBSYSTEM_COMMON, 1200 OPCODE_COMMON_SET_IFACE_MULTICAST, 1201 MBX_TIMEOUT_SEC, 1202 sizeof(struct mbx_set_common_iface_multicast), 1203 OCE_MBX_VER_V0); 1204 1205 bzero(&mbx, sizeof(struct oce_mbx)); 1206 1207 mbx.u0.s.embedded = 0; /*Non embeded*/ 1208 mbx.payload_length = sizeof(struct mbx_set_common_iface_multicast); 1209 mbx.u0.s.sge_count = 1; 1210 sgl = &mbx.payload.u0.u1.sgl[0]; 1211 sgl->pa_hi = htole32(upper_32_bits(pdma_mem->paddr)); 1212 sgl->pa_lo = htole32((pdma_mem->paddr) & 0xFFFFFFFF); 1213 sgl->length = htole32(mbx.payload_length); 1214 1215 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1216 1217 rc = oce_mbox_post(sc, &mbx, NULL); 1218 if (!rc) 1219 rc = req->hdr.u0.rsp.status; 1220 if (rc) 1221 device_printf(sc->dev, 1222 "%s failed - cmd status: %d addi status: %d\n", 1223 __FUNCTION__, rc, 1224 req->hdr.u0.rsp.additional_status); 1225 return rc; 1226 } 1227 1228 1229 /** 1230 * @brief Function to send passthrough Ioctls 1231 * @param sc software handle to the device 1232 * @param dma_mem pointer to dma memory region 1233 * @param req_size size of dma_mem 1234 * @returns 0 on success, EIO on failure 1235 */ 1236 int 1237 oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size) 1238 { 1239 struct oce_mbx mbx; 1240 struct oce_mq_sge *sgl; 1241 int rc = 0; 1242 1243 bzero(&mbx, sizeof(struct oce_mbx)); 1244 1245 mbx.u0.s.embedded = 0; /*Non embeded*/ 1246 mbx.payload_length = req_size; 1247 mbx.u0.s.sge_count = 1; 1248 sgl = &mbx.payload.u0.u1.sgl[0]; 1249 sgl->pa_hi = htole32(upper_32_bits(dma_mem->paddr)); 1250 sgl->pa_lo = htole32((dma_mem->paddr) & 0xFFFFFFFF); 1251 sgl->length = htole32(req_size); 1252 1253 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1254 1255 rc = oce_mbox_post(sc, &mbx, NULL); 1256 return rc; 1257 } 1258 1259 1260 int 1261 oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr, 1262 uint32_t if_id, uint32_t *pmac_id) 1263 { 1264 struct oce_mbx mbx; 1265 struct mbx_add_common_iface_mac *fwcmd; 1266 int rc = 0; 1267 1268 bzero(&mbx, sizeof(struct oce_mbx)); 1269 1270 fwcmd = (struct mbx_add_common_iface_mac *)&mbx.payload; 1271 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1272 MBX_SUBSYSTEM_COMMON, 1273 OPCODE_COMMON_ADD_IFACE_MAC, 1274 MBX_TIMEOUT_SEC, 1275 sizeof(struct mbx_add_common_iface_mac), 1276 OCE_MBX_VER_V0); 1277 1278 fwcmd->params.req.if_id = (uint16_t) if_id; 1279 bcopy(mac_addr, fwcmd->params.req.mac_address, 6); 1280 1281 mbx.u0.s.embedded = 1; 1282 mbx.payload_length = sizeof(struct mbx_add_common_iface_mac); 1283 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1284 rc = oce_mbox_post(sc, &mbx, NULL); 1285 if (!rc) 1286 rc = fwcmd->hdr.u0.rsp.status; 1287 if (rc) { 1288 device_printf(sc->dev, 1289 "%s failed - cmd status: %d addi status: %d\n", 1290 __FUNCTION__, rc, 1291 fwcmd->hdr.u0.rsp.additional_status); 1292 goto error; 1293 } 1294 *pmac_id = fwcmd->params.rsp.pmac_id; 1295 error: 1296 return rc; 1297 } 1298 1299 1300 int 1301 oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id) 1302 { 1303 struct oce_mbx mbx; 1304 struct mbx_del_common_iface_mac *fwcmd; 1305 int rc = 0; 1306 1307 bzero(&mbx, sizeof(struct oce_mbx)); 1308 1309 fwcmd = (struct mbx_del_common_iface_mac *)&mbx.payload; 1310 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1311 MBX_SUBSYSTEM_COMMON, 1312 OPCODE_COMMON_DEL_IFACE_MAC, 1313 MBX_TIMEOUT_SEC, 1314 sizeof(struct mbx_del_common_iface_mac), 1315 OCE_MBX_VER_V0); 1316 1317 fwcmd->params.req.if_id = (uint16_t)if_id; 1318 fwcmd->params.req.pmac_id = pmac_id; 1319 1320 mbx.u0.s.embedded = 1; 1321 mbx.payload_length = sizeof(struct mbx_del_common_iface_mac); 1322 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1323 1324 rc = oce_mbox_post(sc, &mbx, NULL); 1325 if (!rc) 1326 rc = fwcmd->hdr.u0.rsp.status; 1327 if (rc) 1328 device_printf(sc->dev, 1329 "%s failed - cmd status: %d addi status: %d\n", 1330 __FUNCTION__, rc, 1331 fwcmd->hdr.u0.rsp.additional_status); 1332 return rc; 1333 } 1334 1335 1336 1337 int 1338 oce_mbox_check_native_mode(POCE_SOFTC sc) 1339 { 1340 struct oce_mbx mbx; 1341 struct mbx_common_set_function_cap *fwcmd; 1342 int rc = 0; 1343 1344 bzero(&mbx, sizeof(struct oce_mbx)); 1345 1346 fwcmd = (struct mbx_common_set_function_cap *)&mbx.payload; 1347 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1348 MBX_SUBSYSTEM_COMMON, 1349 OPCODE_COMMON_SET_FUNCTIONAL_CAPS, 1350 MBX_TIMEOUT_SEC, 1351 sizeof(struct mbx_common_set_function_cap), 1352 OCE_MBX_VER_V0); 1353 1354 fwcmd->params.req.valid_capability_flags = CAP_SW_TIMESTAMPS | 1355 CAP_BE3_NATIVE_ERX_API; 1356 1357 fwcmd->params.req.capability_flags = CAP_BE3_NATIVE_ERX_API; 1358 1359 mbx.u0.s.embedded = 1; 1360 mbx.payload_length = sizeof(struct mbx_common_set_function_cap); 1361 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1362 1363 rc = oce_mbox_post(sc, &mbx, NULL); 1364 if (!rc) 1365 rc = fwcmd->hdr.u0.rsp.status; 1366 if (rc) { 1367 device_printf(sc->dev, 1368 "%s failed - cmd status: %d addi status: %d\n", 1369 __FUNCTION__, rc, 1370 fwcmd->hdr.u0.rsp.additional_status); 1371 goto error; 1372 } 1373 sc->be3_native = HOST_32(fwcmd->params.rsp.capability_flags) 1374 & CAP_BE3_NATIVE_ERX_API; 1375 1376 error: 1377 return 0; 1378 } 1379 1380 1381 1382 int 1383 oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num, 1384 uint8_t loopback_type, uint8_t enable) 1385 { 1386 struct oce_mbx mbx; 1387 struct mbx_lowlevel_set_loopback_mode *fwcmd; 1388 int rc = 0; 1389 1390 1391 bzero(&mbx, sizeof(struct oce_mbx)); 1392 1393 fwcmd = (struct mbx_lowlevel_set_loopback_mode *)&mbx.payload; 1394 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1395 MBX_SUBSYSTEM_LOWLEVEL, 1396 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, 1397 MBX_TIMEOUT_SEC, 1398 sizeof(struct mbx_lowlevel_set_loopback_mode), 1399 OCE_MBX_VER_V0); 1400 1401 fwcmd->params.req.src_port = port_num; 1402 fwcmd->params.req.dest_port = port_num; 1403 fwcmd->params.req.loopback_type = loopback_type; 1404 fwcmd->params.req.loopback_state = enable; 1405 1406 mbx.u0.s.embedded = 1; 1407 mbx.payload_length = sizeof(struct mbx_lowlevel_set_loopback_mode); 1408 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1409 1410 rc = oce_mbox_post(sc, &mbx, NULL); 1411 if (!rc) 1412 rc = fwcmd->hdr.u0.rsp.status; 1413 if (rc) 1414 device_printf(sc->dev, 1415 "%s failed - cmd status: %d addi status: %d\n", 1416 __FUNCTION__, rc, 1417 fwcmd->hdr.u0.rsp.additional_status); 1418 1419 return rc; 1420 1421 } 1422 1423 int 1424 oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num, 1425 uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts, 1426 uint64_t pattern) 1427 { 1428 1429 struct oce_mbx mbx; 1430 struct mbx_lowlevel_test_loopback_mode *fwcmd; 1431 int rc = 0; 1432 1433 1434 bzero(&mbx, sizeof(struct oce_mbx)); 1435 1436 fwcmd = (struct mbx_lowlevel_test_loopback_mode *)&mbx.payload; 1437 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1438 MBX_SUBSYSTEM_LOWLEVEL, 1439 OPCODE_LOWLEVEL_TEST_LOOPBACK, 1440 MBX_TIMEOUT_SEC, 1441 sizeof(struct mbx_lowlevel_test_loopback_mode), 1442 OCE_MBX_VER_V0); 1443 1444 fwcmd->params.req.pattern = pattern; 1445 fwcmd->params.req.src_port = port_num; 1446 fwcmd->params.req.dest_port = port_num; 1447 fwcmd->params.req.pkt_size = pkt_size; 1448 fwcmd->params.req.num_pkts = num_pkts; 1449 fwcmd->params.req.loopback_type = loopback_type; 1450 1451 mbx.u0.s.embedded = 1; 1452 mbx.payload_length = sizeof(struct mbx_lowlevel_test_loopback_mode); 1453 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1454 1455 rc = oce_mbox_post(sc, &mbx, NULL); 1456 if (!rc) 1457 rc = fwcmd->hdr.u0.rsp.status; 1458 if (rc) 1459 device_printf(sc->dev, 1460 "%s failed - cmd status: %d addi status: %d\n", 1461 __FUNCTION__, rc, 1462 fwcmd->hdr.u0.rsp.additional_status); 1463 1464 return rc; 1465 } 1466 1467 int 1468 oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode, 1469 POCE_DMA_MEM pdma_mem, uint32_t num_bytes) 1470 { 1471 1472 struct oce_mbx mbx; 1473 struct oce_mq_sge *sgl = NULL; 1474 struct mbx_common_read_write_flashrom *fwcmd = NULL; 1475 int rc = 0, payload_len = 0; 1476 1477 bzero(&mbx, sizeof(struct oce_mbx)); 1478 fwcmd = OCE_DMAPTR(pdma_mem, struct mbx_common_read_write_flashrom); 1479 payload_len = sizeof(struct mbx_common_read_write_flashrom) + 32*1024; 1480 1481 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1482 MBX_SUBSYSTEM_COMMON, 1483 OPCODE_COMMON_WRITE_FLASHROM, 1484 LONG_TIMEOUT, 1485 payload_len, 1486 OCE_MBX_VER_V0); 1487 1488 fwcmd->flash_op_type = LE_32(optype); 1489 fwcmd->flash_op_code = LE_32(opcode); 1490 fwcmd->data_buffer_size = LE_32(num_bytes); 1491 1492 mbx.u0.s.embedded = 0; /*Non embeded*/ 1493 mbx.payload_length = payload_len; 1494 mbx.u0.s.sge_count = 1; 1495 1496 sgl = &mbx.payload.u0.u1.sgl[0]; 1497 sgl->pa_hi = upper_32_bits(pdma_mem->paddr); 1498 sgl->pa_lo = pdma_mem->paddr & 0xFFFFFFFF; 1499 sgl->length = payload_len; 1500 1501 /* post the command */ 1502 rc = oce_mbox_post(sc, &mbx, NULL); 1503 if (!rc) 1504 rc = fwcmd->hdr.u0.rsp.status; 1505 if (rc) 1506 device_printf(sc->dev, 1507 "%s failed - cmd status: %d addi status: %d\n", 1508 __FUNCTION__, rc, 1509 fwcmd->hdr.u0.rsp.additional_status); 1510 1511 return rc; 1512 1513 } 1514 1515 int 1516 oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc, 1517 uint32_t offset, uint32_t optype) 1518 { 1519 1520 int rc = 0, payload_len = 0; 1521 struct oce_mbx mbx; 1522 struct mbx_common_read_write_flashrom *fwcmd; 1523 1524 bzero(&mbx, sizeof(struct oce_mbx)); 1525 1526 fwcmd = (struct mbx_common_read_write_flashrom *)&mbx.payload; 1527 1528 /* Firmware requires extra 4 bytes with this ioctl. Since there 1529 is enough room in the mbx payload it should be good enough 1530 Reference: Bug 14853 1531 */ 1532 payload_len = sizeof(struct mbx_common_read_write_flashrom) + 4; 1533 1534 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1535 MBX_SUBSYSTEM_COMMON, 1536 OPCODE_COMMON_READ_FLASHROM, 1537 MBX_TIMEOUT_SEC, 1538 payload_len, 1539 OCE_MBX_VER_V0); 1540 1541 fwcmd->flash_op_type = optype; 1542 fwcmd->flash_op_code = FLASHROM_OPER_REPORT; 1543 fwcmd->data_offset = offset; 1544 fwcmd->data_buffer_size = 0x4; 1545 1546 mbx.u0.s.embedded = 1; 1547 mbx.payload_length = payload_len; 1548 1549 /* post the command */ 1550 rc = oce_mbox_post(sc, &mbx, NULL); 1551 if (!rc) 1552 rc = fwcmd->hdr.u0.rsp.status; 1553 if (rc) { 1554 device_printf(sc->dev, 1555 "%s failed - cmd status: %d addi status: %d\n", 1556 __FUNCTION__, rc, 1557 fwcmd->hdr.u0.rsp.additional_status); 1558 goto error; 1559 } 1560 bcopy(fwcmd->data_buffer, flash_crc, 4); 1561 error: 1562 return rc; 1563 } 1564 1565 int 1566 oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info) 1567 { 1568 1569 struct oce_mbx mbx; 1570 struct mbx_common_phy_info *fwcmd; 1571 int rc = 0; 1572 1573 bzero(&mbx, sizeof(struct oce_mbx)); 1574 1575 fwcmd = (struct mbx_common_phy_info *)&mbx.payload; 1576 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1577 MBX_SUBSYSTEM_COMMON, 1578 OPCODE_COMMON_GET_PHY_CONFIG, 1579 MBX_TIMEOUT_SEC, 1580 sizeof(struct mbx_common_phy_info), 1581 OCE_MBX_VER_V0); 1582 1583 mbx.u0.s.embedded = 1; 1584 mbx.payload_length = sizeof(struct mbx_common_phy_info); 1585 1586 /* now post the command */ 1587 rc = oce_mbox_post(sc, &mbx, NULL); 1588 if (!rc) 1589 rc = fwcmd->hdr.u0.rsp.status; 1590 if (rc) { 1591 device_printf(sc->dev, 1592 "%s failed - cmd status: %d addi status: %d\n", 1593 __FUNCTION__, rc, 1594 fwcmd->hdr.u0.rsp.additional_status); 1595 goto error; 1596 } 1597 phy_info->phy_type = HOST_16(fwcmd->params.rsp.phy_info.phy_type); 1598 phy_info->interface_type = 1599 HOST_16(fwcmd->params.rsp.phy_info.interface_type); 1600 phy_info->auto_speeds_supported = 1601 HOST_16(fwcmd->params.rsp.phy_info.auto_speeds_supported); 1602 phy_info->fixed_speeds_supported = 1603 HOST_16(fwcmd->params.rsp.phy_info.fixed_speeds_supported); 1604 phy_info->misc_params = HOST_32(fwcmd->params.rsp.phy_info.misc_params); 1605 error: 1606 return rc; 1607 1608 } 1609 1610 1611 int 1612 oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size, 1613 uint32_t data_offset, POCE_DMA_MEM pdma_mem, 1614 uint32_t *written_data, uint32_t *additional_status) 1615 { 1616 1617 struct oce_mbx mbx; 1618 struct mbx_lancer_common_write_object *fwcmd = NULL; 1619 int rc = 0, payload_len = 0; 1620 1621 bzero(&mbx, sizeof(struct oce_mbx)); 1622 payload_len = sizeof(struct mbx_lancer_common_write_object); 1623 1624 mbx.u0.s.embedded = 1;/* Embedded */ 1625 mbx.payload_length = payload_len; 1626 fwcmd = (struct mbx_lancer_common_write_object *)&mbx.payload; 1627 1628 /* initialize the ioctl header */ 1629 mbx_common_req_hdr_init(&fwcmd->params.req.hdr, 0, 0, 1630 MBX_SUBSYSTEM_COMMON, 1631 OPCODE_COMMON_WRITE_OBJECT, 1632 LONG_TIMEOUT, 1633 payload_len, 1634 OCE_MBX_VER_V0); 1635 1636 fwcmd->params.req.write_length = data_size; 1637 if (data_size == 0) 1638 fwcmd->params.req.eof = 1; 1639 else 1640 fwcmd->params.req.eof = 0; 1641 1642 strcpy(fwcmd->params.req.object_name, "/prg"); 1643 fwcmd->params.req.descriptor_count = 1; 1644 fwcmd->params.req.write_offset = data_offset; 1645 fwcmd->params.req.buffer_length = data_size; 1646 fwcmd->params.req.address_lower = pdma_mem->paddr & 0xFFFFFFFF; 1647 fwcmd->params.req.address_upper = upper_32_bits(pdma_mem->paddr); 1648 1649 /* post the command */ 1650 rc = oce_mbox_post(sc, &mbx, NULL); 1651 if (!rc) 1652 rc = fwcmd->params.rsp.status; 1653 if (rc) { 1654 device_printf(sc->dev, 1655 "%s failed - cmd status: %d addi status: %d\n", 1656 __FUNCTION__, rc, 1657 fwcmd->params.rsp.additional_status); 1658 goto error; 1659 } 1660 *written_data = HOST_32(fwcmd->params.rsp.actual_write_length); 1661 *additional_status = fwcmd->params.rsp.additional_status; 1662 error: 1663 return rc; 1664 1665 } 1666 1667 1668 1669 int 1670 oce_mbox_create_rq(struct oce_rq *rq) 1671 { 1672 1673 struct oce_mbx mbx; 1674 struct mbx_create_nic_rq *fwcmd; 1675 POCE_SOFTC sc = rq->parent; 1676 int rc, num_pages = 0; 1677 1678 if (rq->qstate == QCREATED) 1679 return 0; 1680 1681 bzero(&mbx, sizeof(struct oce_mbx)); 1682 1683 fwcmd = (struct mbx_create_nic_rq *)&mbx.payload; 1684 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1685 MBX_SUBSYSTEM_NIC, 1686 NIC_CREATE_RQ, MBX_TIMEOUT_SEC, 1687 sizeof(struct mbx_create_nic_rq), 1688 OCE_MBX_VER_V0); 1689 1690 /* oce_page_list will also prepare pages */ 1691 num_pages = oce_page_list(rq->ring, &fwcmd->params.req.pages[0]); 1692 1693 if (IS_XE201(sc)) { 1694 fwcmd->params.req.frag_size = rq->cfg.frag_size/2048; 1695 fwcmd->params.req.page_size = 1; 1696 fwcmd->hdr.u0.req.version = OCE_MBX_VER_V1; 1697 } else 1698 fwcmd->params.req.frag_size = OCE_LOG2(rq->cfg.frag_size); 1699 fwcmd->params.req.num_pages = num_pages; 1700 fwcmd->params.req.cq_id = rq->cq->cq_id; 1701 fwcmd->params.req.if_id = sc->if_id; 1702 fwcmd->params.req.max_frame_size = rq->cfg.mtu; 1703 fwcmd->params.req.is_rss_queue = rq->cfg.is_rss_queue; 1704 1705 mbx.u0.s.embedded = 1; 1706 mbx.payload_length = sizeof(struct mbx_create_nic_rq); 1707 1708 rc = oce_mbox_post(sc, &mbx, NULL); 1709 if (!rc) 1710 rc = fwcmd->hdr.u0.rsp.status; 1711 if (rc) { 1712 device_printf(sc->dev, 1713 "%s failed - cmd status: %d addi status: %d\n", 1714 __FUNCTION__, rc, 1715 fwcmd->hdr.u0.rsp.additional_status); 1716 goto error; 1717 } 1718 rq->rq_id = HOST_16(fwcmd->params.rsp.rq_id); 1719 rq->rss_cpuid = fwcmd->params.rsp.rss_cpuid; 1720 error: 1721 return rc; 1722 1723 } 1724 1725 1726 1727 int 1728 oce_mbox_create_wq(struct oce_wq *wq) 1729 { 1730 struct oce_mbx mbx; 1731 struct mbx_create_nic_wq *fwcmd; 1732 POCE_SOFTC sc = wq->parent; 1733 int rc = 0, version, num_pages; 1734 1735 bzero(&mbx, sizeof(struct oce_mbx)); 1736 1737 fwcmd = (struct mbx_create_nic_wq *)&mbx.payload; 1738 if (IS_XE201(sc)) 1739 version = OCE_MBX_VER_V1; 1740 else if(IS_BE(sc)) 1741 IS_PROFILE_SUPER_NIC(sc) ? (version = OCE_MBX_VER_V2) 1742 : (version = OCE_MBX_VER_V0); 1743 else 1744 version = OCE_MBX_VER_V2; 1745 1746 if (version > OCE_MBX_VER_V0) 1747 fwcmd->params.req.if_id = sc->if_id; 1748 1749 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1750 MBX_SUBSYSTEM_NIC, 1751 NIC_CREATE_WQ, MBX_TIMEOUT_SEC, 1752 sizeof(struct mbx_create_nic_wq), 1753 version); 1754 1755 num_pages = oce_page_list(wq->ring, &fwcmd->params.req.pages[0]); 1756 1757 fwcmd->params.req.nic_wq_type = wq->cfg.wq_type; 1758 fwcmd->params.req.num_pages = num_pages; 1759 fwcmd->params.req.wq_size = OCE_LOG2(wq->cfg.q_len) + 1; 1760 fwcmd->params.req.cq_id = wq->cq->cq_id; 1761 fwcmd->params.req.ulp_num = 1; 1762 1763 mbx.u0.s.embedded = 1; 1764 mbx.payload_length = sizeof(struct mbx_create_nic_wq); 1765 1766 rc = oce_mbox_post(sc, &mbx, NULL); 1767 if (!rc) 1768 rc = fwcmd->hdr.u0.rsp.status; 1769 if (rc) { 1770 device_printf(sc->dev, 1771 "%s failed - cmd status: %d addi status: %d\n", 1772 __FUNCTION__, rc, 1773 fwcmd->hdr.u0.rsp.additional_status); 1774 goto error; 1775 } 1776 wq->wq_id = HOST_16(fwcmd->params.rsp.wq_id); 1777 if (version == OCE_MBX_VER_V2) 1778 wq->db_offset = HOST_32(fwcmd->params.rsp.db_offset); 1779 else 1780 wq->db_offset = PD_TXULP_DB; 1781 error: 1782 return rc; 1783 1784 } 1785 1786 1787 1788 int 1789 oce_mbox_create_eq(struct oce_eq *eq) 1790 { 1791 struct oce_mbx mbx; 1792 struct mbx_create_common_eq *fwcmd; 1793 POCE_SOFTC sc = eq->parent; 1794 int rc = 0; 1795 uint32_t num_pages; 1796 1797 bzero(&mbx, sizeof(struct oce_mbx)); 1798 1799 fwcmd = (struct mbx_create_common_eq *)&mbx.payload; 1800 1801 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1802 MBX_SUBSYSTEM_COMMON, 1803 OPCODE_COMMON_CREATE_EQ, MBX_TIMEOUT_SEC, 1804 sizeof(struct mbx_create_common_eq), 1805 OCE_MBX_VER_V0); 1806 1807 num_pages = oce_page_list(eq->ring, &fwcmd->params.req.pages[0]); 1808 fwcmd->params.req.ctx.num_pages = num_pages; 1809 fwcmd->params.req.ctx.valid = 1; 1810 fwcmd->params.req.ctx.size = (eq->eq_cfg.item_size == 4) ? 0 : 1; 1811 fwcmd->params.req.ctx.count = OCE_LOG2(eq->eq_cfg.q_len / 256); 1812 fwcmd->params.req.ctx.armed = 0; 1813 fwcmd->params.req.ctx.delay_mult = eq->eq_cfg.cur_eqd; 1814 1815 1816 mbx.u0.s.embedded = 1; 1817 mbx.payload_length = sizeof(struct mbx_create_common_eq); 1818 1819 rc = oce_mbox_post(sc, &mbx, NULL); 1820 if (!rc) 1821 rc = fwcmd->hdr.u0.rsp.status; 1822 if (rc) { 1823 device_printf(sc->dev, 1824 "%s failed - cmd status: %d addi status: %d\n", 1825 __FUNCTION__, rc, 1826 fwcmd->hdr.u0.rsp.additional_status); 1827 goto error; 1828 } 1829 eq->eq_id = HOST_16(fwcmd->params.rsp.eq_id); 1830 error: 1831 return rc; 1832 } 1833 1834 1835 1836 int 1837 oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce, uint32_t is_eventable) 1838 { 1839 struct oce_mbx mbx; 1840 struct mbx_create_common_cq *fwcmd; 1841 POCE_SOFTC sc = cq->parent; 1842 uint8_t version; 1843 oce_cq_ctx_t *ctx; 1844 uint32_t num_pages, page_size; 1845 int rc = 0; 1846 1847 1848 bzero(&mbx, sizeof(struct oce_mbx)); 1849 1850 fwcmd = (struct mbx_create_common_cq *)&mbx.payload; 1851 1852 if (IS_XE201(sc)) 1853 version = OCE_MBX_VER_V2; 1854 else 1855 version = OCE_MBX_VER_V0; 1856 1857 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1858 MBX_SUBSYSTEM_COMMON, 1859 OPCODE_COMMON_CREATE_CQ, 1860 MBX_TIMEOUT_SEC, 1861 sizeof(struct mbx_create_common_cq), 1862 version); 1863 1864 ctx = &fwcmd->params.req.cq_ctx; 1865 1866 num_pages = oce_page_list(cq->ring, &fwcmd->params.req.pages[0]); 1867 page_size = 1; /* 1 for 4K */ 1868 1869 if (version == OCE_MBX_VER_V2) { 1870 ctx->v2.num_pages = LE_16(num_pages); 1871 ctx->v2.page_size = page_size; 1872 ctx->v2.eventable = is_eventable; 1873 ctx->v2.valid = 1; 1874 ctx->v2.count = OCE_LOG2(cq->cq_cfg.q_len / 256); 1875 ctx->v2.nodelay = cq->cq_cfg.nodelay; 1876 ctx->v2.coalesce_wm = ncoalesce; 1877 ctx->v2.armed = 0; 1878 ctx->v2.eq_id = cq->eq->eq_id; 1879 if (ctx->v2.count == 3) { 1880 if ((u_int)cq->cq_cfg.q_len > (4*1024)-1) 1881 ctx->v2.cqe_count = (4*1024)-1; 1882 else 1883 ctx->v2.cqe_count = cq->cq_cfg.q_len; 1884 } 1885 } else { 1886 ctx->v0.num_pages = LE_16(num_pages); 1887 ctx->v0.eventable = is_eventable; 1888 ctx->v0.valid = 1; 1889 ctx->v0.count = OCE_LOG2(cq->cq_cfg.q_len / 256); 1890 ctx->v0.nodelay = cq->cq_cfg.nodelay; 1891 ctx->v0.coalesce_wm = ncoalesce; 1892 ctx->v0.armed = 0; 1893 ctx->v0.eq_id = cq->eq->eq_id; 1894 } 1895 1896 mbx.u0.s.embedded = 1; 1897 mbx.payload_length = sizeof(struct mbx_create_common_cq); 1898 1899 rc = oce_mbox_post(sc, &mbx, NULL); 1900 if (!rc) 1901 rc = fwcmd->hdr.u0.rsp.status; 1902 if (rc) { 1903 device_printf(sc->dev, 1904 "%s failed - cmd status: %d addi status: %d\n", 1905 __FUNCTION__, rc, 1906 fwcmd->hdr.u0.rsp.additional_status); 1907 goto error; 1908 } 1909 cq->cq_id = HOST_16(fwcmd->params.rsp.cq_id); 1910 error: 1911 return rc; 1912 1913 } 1914 1915 int 1916 oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num) 1917 { 1918 int rc = 0; 1919 struct oce_mbx mbx; 1920 struct mbx_read_common_transrecv_data *fwcmd; 1921 struct oce_mq_sge *sgl; 1922 OCE_DMA_MEM dma; 1923 1924 /* Allocate DMA mem*/ 1925 if (oce_dma_alloc(sc, sizeof(struct mbx_read_common_transrecv_data), 1926 &dma, 0)) 1927 return ENOMEM; 1928 1929 fwcmd = OCE_DMAPTR(&dma, struct mbx_read_common_transrecv_data); 1930 bzero(fwcmd, sizeof(struct mbx_read_common_transrecv_data)); 1931 1932 bzero(&mbx, sizeof(struct oce_mbx)); 1933 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1934 MBX_SUBSYSTEM_COMMON, 1935 OPCODE_COMMON_READ_TRANSRECEIVER_DATA, 1936 MBX_TIMEOUT_SEC, 1937 sizeof(struct mbx_read_common_transrecv_data), 1938 OCE_MBX_VER_V0); 1939 1940 /* fill rest of mbx */ 1941 mbx.u0.s.embedded = 0; 1942 mbx.payload_length = sizeof(struct mbx_read_common_transrecv_data); 1943 mbx.u0.s.sge_count = 1; 1944 sgl = &mbx.payload.u0.u1.sgl[0]; 1945 sgl->pa_hi = htole32(upper_32_bits(dma.paddr)); 1946 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF); 1947 sgl->length = htole32(mbx.payload_length); 1948 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 1949 1950 fwcmd->params.req.port = LE_32(sc->port_id); 1951 fwcmd->params.req.page_num = LE_32(page_num); 1952 1953 /* command post */ 1954 rc = oce_mbox_post(sc, &mbx, NULL); 1955 if (!rc) 1956 rc = fwcmd->hdr.u0.rsp.status; 1957 if (rc) { 1958 device_printf(sc->dev, 1959 "%s failed - cmd status: %d addi status: %d\n", 1960 __FUNCTION__, rc, 1961 fwcmd->hdr.u0.rsp.additional_status); 1962 goto error; 1963 } 1964 if(fwcmd->params.rsp.page_num == PAGE_NUM_A0) 1965 { 1966 bcopy((char *)fwcmd->params.rsp.page_data, 1967 &sfp_vpd_dump_buffer[0], 1968 TRANSCEIVER_A0_SIZE); 1969 } 1970 1971 if(fwcmd->params.rsp.page_num == PAGE_NUM_A2) 1972 { 1973 bcopy((char *)fwcmd->params.rsp.page_data, 1974 &sfp_vpd_dump_buffer[TRANSCEIVER_A0_SIZE], 1975 TRANSCEIVER_A2_SIZE); 1976 } 1977 error: 1978 oce_dma_free(sc, &dma); 1979 return rc; 1980 } 1981 1982 void 1983 oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd, 1984 int num) 1985 { 1986 struct oce_mbx mbx; 1987 struct mbx_modify_common_eq_delay *fwcmd; 1988 int rc = 0; 1989 int i = 0; 1990 1991 bzero(&mbx, sizeof(struct oce_mbx)); 1992 1993 /* Initialize MODIFY_EQ_DELAY ioctl header */ 1994 fwcmd = (struct mbx_modify_common_eq_delay *)&mbx.payload; 1995 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 1996 MBX_SUBSYSTEM_COMMON, 1997 OPCODE_COMMON_MODIFY_EQ_DELAY, 1998 MBX_TIMEOUT_SEC, 1999 sizeof(struct mbx_modify_common_eq_delay), 2000 OCE_MBX_VER_V0); 2001 /* fill rest of mbx */ 2002 mbx.u0.s.embedded = 1; 2003 mbx.payload_length = sizeof(struct mbx_modify_common_eq_delay); 2004 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 2005 2006 fwcmd->params.req.num_eq = num; 2007 for (i = 0; i < num; i++) { 2008 fwcmd->params.req.delay[i].eq_id = 2009 htole32(set_eqd[i].eq_id); 2010 fwcmd->params.req.delay[i].phase = 0; 2011 fwcmd->params.req.delay[i].dm = 2012 htole32(set_eqd[i].delay_multiplier); 2013 } 2014 2015 2016 /* command post */ 2017 rc = oce_mbox_post(sc, &mbx, NULL); 2018 2019 if (!rc) 2020 rc = fwcmd->hdr.u0.rsp.status; 2021 if (rc) 2022 device_printf(sc->dev, 2023 "%s failed - cmd status: %d addi status: %d\n", 2024 __FUNCTION__, rc, 2025 fwcmd->hdr.u0.rsp.additional_status); 2026 } 2027 2028 int 2029 oce_get_profile_config(POCE_SOFTC sc, uint32_t max_rss) 2030 { 2031 struct oce_mbx mbx; 2032 struct mbx_common_get_profile_config *fwcmd; 2033 int rc = 0; 2034 int version = 0; 2035 struct oce_mq_sge *sgl; 2036 OCE_DMA_MEM dma; 2037 uint32_t desc_count = 0; 2038 struct oce_nic_resc_desc *nic_desc = NULL; 2039 int i; 2040 boolean_t nic_desc_valid = FALSE; 2041 2042 if (IS_BE2(sc)) 2043 return -1; 2044 2045 /* Allocate DMA mem*/ 2046 if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_profile_config), 2047 &dma, 0)) 2048 return ENOMEM; 2049 2050 /* Initialize MODIFY_EQ_DELAY ioctl header */ 2051 fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_profile_config); 2052 bzero(fwcmd, sizeof(struct mbx_common_get_profile_config)); 2053 2054 if (!IS_XE201(sc)) 2055 version = OCE_MBX_VER_V1; 2056 else 2057 version = OCE_MBX_VER_V0; 2058 2059 bzero(&mbx, sizeof(struct oce_mbx)); 2060 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 2061 MBX_SUBSYSTEM_COMMON, 2062 OPCODE_COMMON_GET_PROFILE_CONFIG, 2063 MBX_TIMEOUT_SEC, 2064 sizeof(struct mbx_common_get_profile_config), 2065 version); 2066 /* fill rest of mbx */ 2067 mbx.u0.s.embedded = 0; 2068 mbx.payload_length = sizeof(struct mbx_common_get_profile_config); 2069 mbx.u0.s.sge_count = 1; 2070 sgl = &mbx.payload.u0.u1.sgl[0]; 2071 sgl->pa_hi = htole32(upper_32_bits(dma.paddr)); 2072 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF); 2073 sgl->length = htole32(mbx.payload_length); 2074 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 2075 2076 fwcmd->params.req.type = ACTIVE_PROFILE; 2077 2078 /* command post */ 2079 rc = oce_mbox_post(sc, &mbx, NULL); 2080 if (!rc) 2081 rc = fwcmd->hdr.u0.rsp.status; 2082 if (rc) { 2083 device_printf(sc->dev, 2084 "%s failed - cmd status: %d addi status: %d\n", 2085 __FUNCTION__, rc, 2086 fwcmd->hdr.u0.rsp.additional_status); 2087 goto error; 2088 } 2089 2090 nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources; 2091 desc_count = HOST_32(fwcmd->params.rsp.desc_count); 2092 for (i = 0; i < desc_count; i++) { 2093 if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) || 2094 (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) { 2095 nic_desc_valid = TRUE; 2096 break; 2097 } 2098 nic_desc = (struct oce_nic_resc_desc *) \ 2099 ((char *)nic_desc + nic_desc->desc_len); 2100 } 2101 if (!nic_desc_valid) { 2102 rc = -1; 2103 goto error; 2104 } 2105 else { 2106 sc->max_vlans = HOST_16(nic_desc->vlan_count); 2107 sc->nwqs = HOST_16(nic_desc->txq_count); 2108 if (sc->nwqs) 2109 sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ); 2110 else 2111 sc->nwqs = OCE_MAX_WQ; 2112 2113 sc->nrssqs = HOST_16(nic_desc->rssq_count); 2114 if (sc->nrssqs) 2115 sc->nrssqs = MIN(sc->nrssqs, max_rss); 2116 else 2117 sc->nrssqs = max_rss; 2118 sc->nrqs = sc->nrssqs + 1; /* 1 for def RX */ 2119 2120 } 2121 error: 2122 oce_dma_free(sc, &dma); 2123 return rc; 2124 2125 } 2126 2127 int 2128 oce_get_func_config(POCE_SOFTC sc) 2129 { 2130 struct oce_mbx mbx; 2131 struct mbx_common_get_func_config *fwcmd; 2132 int rc = 0; 2133 int version = 0; 2134 struct oce_mq_sge *sgl; 2135 OCE_DMA_MEM dma; 2136 uint32_t desc_count = 0; 2137 struct oce_nic_resc_desc *nic_desc = NULL; 2138 int i; 2139 boolean_t nic_desc_valid = FALSE; 2140 uint32_t max_rss = 0; 2141 2142 if ((IS_BE(sc) || IS_SH(sc)) && (!sc->be3_native)) 2143 max_rss = OCE_LEGACY_MODE_RSS; 2144 else 2145 max_rss = OCE_MAX_RSS; 2146 2147 /* Allocate DMA mem*/ 2148 if (oce_dma_alloc(sc, sizeof(struct mbx_common_get_func_config), 2149 &dma, 0)) 2150 return ENOMEM; 2151 2152 /* Initialize MODIFY_EQ_DELAY ioctl header */ 2153 fwcmd = OCE_DMAPTR(&dma, struct mbx_common_get_func_config); 2154 bzero(fwcmd, sizeof(struct mbx_common_get_func_config)); 2155 2156 if (IS_SH(sc)) 2157 version = OCE_MBX_VER_V1; 2158 else 2159 version = OCE_MBX_VER_V0; 2160 2161 bzero(&mbx, sizeof(struct oce_mbx)); 2162 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 2163 MBX_SUBSYSTEM_COMMON, 2164 OPCODE_COMMON_GET_FUNCTION_CONFIG, 2165 MBX_TIMEOUT_SEC, 2166 sizeof(struct mbx_common_get_func_config), 2167 version); 2168 /* fill rest of mbx */ 2169 mbx.u0.s.embedded = 0; 2170 mbx.payload_length = sizeof(struct mbx_common_get_func_config); 2171 mbx.u0.s.sge_count = 1; 2172 sgl = &mbx.payload.u0.u1.sgl[0]; 2173 sgl->pa_hi = htole32(upper_32_bits(dma.paddr)); 2174 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF); 2175 sgl->length = htole32(mbx.payload_length); 2176 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ); 2177 2178 /* command post */ 2179 rc = oce_mbox_post(sc, &mbx, NULL); 2180 if (!rc) 2181 rc = fwcmd->hdr.u0.rsp.status; 2182 if (rc) { 2183 device_printf(sc->dev, 2184 "%s failed - cmd status: %d addi status: %d\n", 2185 __FUNCTION__, rc, 2186 fwcmd->hdr.u0.rsp.additional_status); 2187 goto error; 2188 } 2189 2190 nic_desc = (struct oce_nic_resc_desc *) fwcmd->params.rsp.resources; 2191 desc_count = HOST_32(fwcmd->params.rsp.desc_count); 2192 for (i = 0; i < desc_count; i++) { 2193 if ((nic_desc->desc_type == NIC_RESC_DESC_TYPE_V0) || 2194 (nic_desc->desc_type == NIC_RESC_DESC_TYPE_V1)) { 2195 nic_desc_valid = TRUE; 2196 break; 2197 } 2198 nic_desc = (struct oce_nic_resc_desc *) \ 2199 ((char *)nic_desc + nic_desc->desc_len); 2200 } 2201 if (!nic_desc_valid) { 2202 rc = -1; 2203 goto error; 2204 } 2205 else { 2206 sc->max_vlans = nic_desc->vlan_count; 2207 sc->nwqs = HOST_32(nic_desc->txq_count); 2208 if (sc->nwqs) 2209 sc->nwqs = MIN(sc->nwqs, OCE_MAX_WQ); 2210 else 2211 sc->nwqs = OCE_MAX_WQ; 2212 2213 sc->nrssqs = HOST_32(nic_desc->rssq_count); 2214 if (sc->nrssqs) 2215 sc->nrssqs = MIN(sc->nrssqs, max_rss); 2216 else 2217 sc->nrssqs = max_rss; 2218 sc->nrqs = sc->nrssqs + 1; /* 1 for def RX */ 2219 } 2220 error: 2221 oce_dma_free(sc, &dma); 2222 return rc; 2223 2224 } 2225 2226 /* hw lro functions */ 2227 2228 int 2229 oce_mbox_nic_query_lro_capabilities(POCE_SOFTC sc, uint32_t *lro_rq_cnt, uint32_t *lro_flags) 2230 { 2231 struct oce_mbx mbx; 2232 struct mbx_nic_query_lro_capabilities *fwcmd; 2233 int rc = 0; 2234 2235 bzero(&mbx, sizeof(struct oce_mbx)); 2236 2237 fwcmd = (struct mbx_nic_query_lro_capabilities *)&mbx.payload; 2238 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 2239 MBX_SUBSYSTEM_NIC, 2240 0x20,MBX_TIMEOUT_SEC, 2241 sizeof(struct mbx_nic_query_lro_capabilities), 2242 OCE_MBX_VER_V0); 2243 2244 mbx.u0.s.embedded = 1; 2245 mbx.payload_length = sizeof(struct mbx_nic_query_lro_capabilities); 2246 2247 rc = oce_mbox_post(sc, &mbx, NULL); 2248 if (!rc) 2249 rc = fwcmd->hdr.u0.rsp.status; 2250 if (rc) { 2251 device_printf(sc->dev, 2252 "%s failed - cmd status: %d addi status: %d\n", 2253 __FUNCTION__, rc, 2254 fwcmd->hdr.u0.rsp.additional_status); 2255 2256 return rc; 2257 } 2258 if(lro_flags) 2259 *lro_flags = HOST_32(fwcmd->params.rsp.lro_flags); 2260 2261 if(lro_rq_cnt) 2262 *lro_rq_cnt = HOST_16(fwcmd->params.rsp.lro_rq_cnt); 2263 2264 return rc; 2265 } 2266 2267 int 2268 oce_mbox_nic_set_iface_lro_config(POCE_SOFTC sc, int enable) 2269 { 2270 struct oce_mbx mbx; 2271 struct mbx_nic_set_iface_lro_config *fwcmd; 2272 int rc = 0; 2273 2274 bzero(&mbx, sizeof(struct oce_mbx)); 2275 2276 fwcmd = (struct mbx_nic_set_iface_lro_config *)&mbx.payload; 2277 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 2278 MBX_SUBSYSTEM_NIC, 2279 0x26,MBX_TIMEOUT_SEC, 2280 sizeof(struct mbx_nic_set_iface_lro_config), 2281 OCE_MBX_VER_V0); 2282 2283 mbx.u0.s.embedded = 1; 2284 mbx.payload_length = sizeof(struct mbx_nic_set_iface_lro_config); 2285 2286 fwcmd->params.req.iface_id = sc->if_id; 2287 fwcmd->params.req.lro_flags = 0; 2288 2289 if(enable) { 2290 fwcmd->params.req.lro_flags = LRO_FLAGS_HASH_MODE | LRO_FLAGS_RSS_MODE; 2291 fwcmd->params.req.lro_flags |= LRO_FLAGS_CLSC_IPV4 | LRO_FLAGS_CLSC_IPV6; 2292 2293 fwcmd->params.req.max_clsc_byte_cnt = 64*1024; /* min = 2974, max = 0xfa59 */ 2294 fwcmd->params.req.max_clsc_seg_cnt = 43; /* min = 2, max = 64 */ 2295 fwcmd->params.req.max_clsc_usec_delay = 18; /* min = 1, max = 256 */ 2296 fwcmd->params.req.min_clsc_frame_byte_cnt = 0; /* min = 1, max = 9014 */ 2297 } 2298 2299 rc = oce_mbox_post(sc, &mbx, NULL); 2300 if (!rc) 2301 rc = fwcmd->hdr.u0.rsp.status; 2302 if (rc) { 2303 device_printf(sc->dev, 2304 "%s failed - cmd status: %d addi status: %d\n", 2305 __FUNCTION__, rc, 2306 fwcmd->hdr.u0.rsp.additional_status); 2307 2308 return rc; 2309 } 2310 return rc; 2311 } 2312 2313 int 2314 oce_mbox_create_rq_v2(struct oce_rq *rq) 2315 { 2316 struct oce_mbx mbx; 2317 struct mbx_create_nic_rq_v2 *fwcmd; 2318 POCE_SOFTC sc = rq->parent; 2319 int rc = 0, num_pages = 0; 2320 2321 if (rq->qstate == QCREATED) 2322 return 0; 2323 2324 bzero(&mbx, sizeof(struct oce_mbx)); 2325 2326 fwcmd = (struct mbx_create_nic_rq_v2 *)&mbx.payload; 2327 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0, 2328 MBX_SUBSYSTEM_NIC, 2329 0x08, MBX_TIMEOUT_SEC, 2330 sizeof(struct mbx_create_nic_rq_v2), 2331 OCE_MBX_VER_V2); 2332 2333 /* oce_page_list will also prepare pages */ 2334 num_pages = oce_page_list(rq->ring, &fwcmd->params.req.pages[0]); 2335 2336 fwcmd->params.req.cq_id = rq->cq->cq_id; 2337 fwcmd->params.req.frag_size = rq->cfg.frag_size/2048; 2338 fwcmd->params.req.num_pages = num_pages; 2339 2340 fwcmd->params.req.if_id = sc->if_id; 2341 2342 fwcmd->params.req.max_frame_size = rq->cfg.mtu; 2343 fwcmd->params.req.page_size = 1; 2344 if(rq->cfg.is_rss_queue) { 2345 fwcmd->params.req.rq_flags = (NIC_RQ_FLAGS_RSS | NIC_RQ_FLAGS_LRO); 2346 }else { 2347 device_printf(sc->dev, 2348 "non rss lro queue should not be created \n"); 2349 goto error; 2350 } 2351 mbx.u0.s.embedded = 1; 2352 mbx.payload_length = sizeof(struct mbx_create_nic_rq_v2); 2353 2354 rc = oce_mbox_post(sc, &mbx, NULL); 2355 if (!rc) 2356 rc = fwcmd->hdr.u0.rsp.status; 2357 if (rc) { 2358 device_printf(sc->dev, 2359 "%s failed - cmd status: %d addi status: %d\n", 2360 __FUNCTION__, rc, 2361 fwcmd->hdr.u0.rsp.additional_status); 2362 goto error; 2363 } 2364 rq->rq_id = HOST_16(fwcmd->params.rsp.rq_id); 2365 rq->rss_cpuid = fwcmd->params.rsp.rss_cpuid; 2366 2367 error: 2368 return rc; 2369 } 2370 2371