1 /*- 2 * Copyright (C) 2012 Emulex 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Emulex Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * Contact Information: 32 * freebsd-drivers@emulex.com 33 * 34 * Emulex 35 * 3333 Susan Street 36 * Costa Mesa, CA 92626 37 */ 38 39 /* $FreeBSD$ */ 40 41 #include <sys/types.h> 42 43 #undef _BIG_ENDIAN /* TODO */ 44 #pragma pack(1) 45 46 #define OC_CNA_GEN2 0x2 47 #define OC_CNA_GEN3 0x3 48 #define DEVID_TIGERSHARK 0x700 49 #define DEVID_TOMCAT 0x710 50 51 /* PCI CSR offsets */ 52 #define PCICFG_F1_CSR 0x0 /* F1 for NIC */ 53 #define PCICFG_SEMAPHORE 0xbc 54 #define PCICFG_SOFT_RESET 0x5c 55 #define PCICFG_UE_STATUS_HI_MASK 0xac 56 #define PCICFG_UE_STATUS_LO_MASK 0xa8 57 #define PCICFG_ONLINE0 0xb0 58 #define PCICFG_ONLINE1 0xb4 59 #define INTR_EN 0x20000000 60 #define IMAGE_TRANSFER_SIZE (32 * 1024) /* 32K at a time */ 61 62 /* CSR register offsets */ 63 #define MPU_EP_CONTROL 0 64 #define MPU_EP_SEMAPHORE_BE3 0xac 65 #define MPU_EP_SEMAPHORE_XE201 0x400 66 #define MPU_EP_SEMAPHORE(sc) \ 67 ((IS_BE(sc)) ? MPU_EP_SEMAPHORE_BE3 : MPU_EP_SEMAPHORE_XE201) 68 #define PCICFG_INTR_CTRL 0xfc 69 #define HOSTINTR_MASK (1 << 29) 70 #define HOSTINTR_PFUNC_SHIFT 26 71 #define HOSTINTR_PFUNC_MASK 7 72 73 /* POST status reg struct */ 74 #define POST_STAGE_POWER_ON_RESET 0x00 75 #define POST_STAGE_AWAITING_HOST_RDY 0x01 76 #define POST_STAGE_HOST_RDY 0x02 77 #define POST_STAGE_CHIP_RESET 0x03 78 #define POST_STAGE_ARMFW_READY 0xc000 79 #define POST_STAGE_ARMFW_UE 0xf000 80 81 /* DOORBELL registers */ 82 #define PD_RXULP_DB 0x0100 83 #define PD_TXULP_DB 0x0060 84 #define DB_RQ_ID_MASK 0x3FF 85 86 #define PD_CQ_DB 0x0120 87 #define PD_EQ_DB PD_CQ_DB 88 #define PD_MPU_MBOX_DB 0x0160 89 #define PD_MQ_DB 0x0140 90 91 /* EQE completion types */ 92 #define EQ_MINOR_CODE_COMPLETION 0x00 93 #define EQ_MINOR_CODE_OTHER 0x01 94 #define EQ_MAJOR_CODE_COMPLETION 0x00 95 96 /* Link Status field values */ 97 #define PHY_LINK_FAULT_NONE 0x0 98 #define PHY_LINK_FAULT_LOCAL 0x01 99 #define PHY_LINK_FAULT_REMOTE 0x02 100 101 #define PHY_LINK_SPEED_ZERO 0x0 /* No link */ 102 #define PHY_LINK_SPEED_10MBPS 0x1 /* (10 Mbps) */ 103 #define PHY_LINK_SPEED_100MBPS 0x2 /* (100 Mbps) */ 104 #define PHY_LINK_SPEED_1GBPS 0x3 /* (1 Gbps) */ 105 #define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */ 106 107 #define PHY_LINK_DUPLEX_NONE 0x0 108 #define PHY_LINK_DUPLEX_HALF 0x1 109 #define PHY_LINK_DUPLEX_FULL 0x2 110 111 #define NTWK_PORT_A 0x0 /* (Port A) */ 112 #define NTWK_PORT_B 0x1 /* (Port B) */ 113 114 #define PHY_LINK_SPEED_ZERO 0x0 /* (No link.) */ 115 #define PHY_LINK_SPEED_10MBPS 0x1 /* (10 Mbps) */ 116 #define PHY_LINK_SPEED_100MBPS 0x2 /* (100 Mbps) */ 117 #define PHY_LINK_SPEED_1GBPS 0x3 /* (1 Gbps) */ 118 #define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */ 119 120 /* Hardware Address types */ 121 #define MAC_ADDRESS_TYPE_STORAGE 0x0 /* (Storage MAC Address) */ 122 #define MAC_ADDRESS_TYPE_NETWORK 0x1 /* (Network MAC Address) */ 123 #define MAC_ADDRESS_TYPE_PD 0x2 /* (Protection Domain MAC Addr) */ 124 #define MAC_ADDRESS_TYPE_MANAGEMENT 0x3 /* (Management MAC Address) */ 125 #define MAC_ADDRESS_TYPE_FCOE 0x4 /* (FCoE MAC Address) */ 126 127 /* CREATE_IFACE capability and cap_en flags */ 128 #define MBX_RX_IFACE_FLAGS_RSS 0x4 129 #define MBX_RX_IFACE_FLAGS_PROMISCUOUS 0x8 130 #define MBX_RX_IFACE_FLAGS_BROADCAST 0x10 131 #define MBX_RX_IFACE_FLAGS_UNTAGGED 0x20 132 #define MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS 0x80 133 #define MBX_RX_IFACE_FLAGS_VLAN 0x100 134 #define MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS 0x200 135 #define MBX_RX_IFACE_FLAGS_PASS_L2_ERR 0x400 136 #define MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR 0x800 137 #define MBX_RX_IFACE_FLAGS_MULTICAST 0x1000 138 #define MBX_RX_IFACE_RX_FILTER_IF_MULTICAST_HASH 0x2000 139 #define MBX_RX_IFACE_FLAGS_HDS 0x4000 140 #define MBX_RX_IFACE_FLAGS_DIRECTED 0x8000 141 #define MBX_RX_IFACE_FLAGS_VMQ 0x10000 142 #define MBX_RX_IFACE_FLAGS_NETQ 0x20000 143 #define MBX_RX_IFACE_FLAGS_QGROUPS 0x40000 144 #define MBX_RX_IFACE_FLAGS_LSO 0x80000 145 #define MBX_RX_IFACE_FLAGS_LRO 0x100000 146 147 #define MQ_RING_CONTEXT_SIZE_16 0x5 /* (16 entries) */ 148 #define MQ_RING_CONTEXT_SIZE_32 0x6 /* (32 entries) */ 149 #define MQ_RING_CONTEXT_SIZE_64 0x7 /* (64 entries) */ 150 #define MQ_RING_CONTEXT_SIZE_128 0x8 /* (128 entries) */ 151 152 #define MBX_DB_READY_BIT 0x1 153 #define MBX_DB_HI_BIT 0x2 154 #define ASYNC_EVENT_CODE_LINK_STATE 0x1 155 #define ASYNC_EVENT_LINK_UP 0x1 156 #define ASYNC_EVENT_LINK_DOWN 0x0 157 #define ASYNC_EVENT_GRP5 0x5 158 #define ASYNC_EVENT_CODE_DEBUG 0x6 159 #define ASYNC_EVENT_PVID_STATE 0x3 160 #define ASYNC_EVENT_DEBUG_QNQ 0x1 161 #define ASYNC_EVENT_CODE_SLIPORT 0x11 162 #define VLAN_VID_MASK 0x0FFF 163 164 /* port link_status */ 165 #define ASYNC_EVENT_LOGICAL 0x02 166 167 /* Logical Link Status */ 168 #define NTWK_LOGICAL_LINK_DOWN 0 169 #define NTWK_LOGICAL_LINK_UP 1 170 171 /* Rx filter bits */ 172 #define NTWK_RX_FILTER_IP_CKSUM 0x1 173 #define NTWK_RX_FILTER_TCP_CKSUM 0x2 174 #define NTWK_RX_FILTER_UDP_CKSUM 0x4 175 #define NTWK_RX_FILTER_STRIP_CRC 0x8 176 177 /* max SGE per mbx */ 178 #define MAX_MBX_SGE 19 179 180 /* Max multicast filter size*/ 181 #define OCE_MAX_MC_FILTER_SIZE 64 182 183 /* PCI SLI (Service Level Interface) capabilities register */ 184 #define OCE_INTF_REG_OFFSET 0x58 185 #define OCE_INTF_VALID_SIG 6 /* register's signature */ 186 #define OCE_INTF_FUNC_RESET_REQD 1 187 #define OCE_INTF_HINT1_NOHINT 0 188 #define OCE_INTF_HINT1_SEMAINIT 1 189 #define OCE_INTF_HINT1_STATCTRL 2 190 #define OCE_INTF_IF_TYPE_0 0 191 #define OCE_INTF_IF_TYPE_1 1 192 #define OCE_INTF_IF_TYPE_2 2 193 #define OCE_INTF_IF_TYPE_3 3 194 #define OCE_INTF_SLI_REV3 3 /* not supported by driver */ 195 #define OCE_INTF_SLI_REV4 4 /* driver supports SLI-4 */ 196 #define OCE_INTF_PHYS_FUNC 0 197 #define OCE_INTF_VIRT_FUNC 1 198 #define OCE_INTF_FAMILY_BE2 0 /* not supported by driver */ 199 #define OCE_INTF_FAMILY_BE3 1 /* driver supports BE3 */ 200 #define OCE_INTF_FAMILY_A0_CHIP 0xA /* Lancer A0 chip (supported) */ 201 #define OCE_INTF_FAMILY_B0_CHIP 0xB /* Lancer B0 chip (future) */ 202 203 #define NIC_WQE_SIZE 16 204 #define NIC_UNICAST 0x00 205 #define NIC_MULTICAST 0x01 206 #define NIC_BROADCAST 0x02 207 208 #define NIC_HDS_NO_SPLIT 0x00 209 #define NIC_HDS_SPLIT_L3PL 0x01 210 #define NIC_HDS_SPLIT_L4PL 0x02 211 212 #define NIC_WQ_TYPE_FORWARDING 0x01 213 #define NIC_WQ_TYPE_STANDARD 0x02 214 #define NIC_WQ_TYPE_LOW_LATENCY 0x04 215 216 #define OCE_RESET_STATS 1 217 #define OCE_RETAIN_STATS 0 218 #define OCE_TXP_SW_SZ 48 219 220 typedef union pci_sli_intf_u { 221 uint32_t dw0; 222 struct { 223 #ifdef _BIG_ENDIAN 224 uint32_t sli_valid:3; 225 uint32_t sli_hint2:5; 226 uint32_t sli_hint1:8; 227 uint32_t sli_if_type:4; 228 uint32_t sli_family:4; 229 uint32_t sli_rev:4; 230 uint32_t rsv0:3; 231 uint32_t sli_func_type:1; 232 #else 233 uint32_t sli_func_type:1; 234 uint32_t rsv0:3; 235 uint32_t sli_rev:4; 236 uint32_t sli_family:4; 237 uint32_t sli_if_type:4; 238 uint32_t sli_hint1:8; 239 uint32_t sli_hint2:5; 240 uint32_t sli_valid:3; 241 #endif 242 } bits; 243 } pci_sli_intf_t; 244 245 246 247 /* physical address structure to be used in MBX */ 248 struct phys_addr { 249 /* dw0 */ 250 uint32_t lo; 251 /* dw1 */ 252 uint32_t hi; 253 }; 254 255 256 257 typedef union pcicfg_intr_ctl_u { 258 uint32_t dw0; 259 struct { 260 #ifdef _BIG_ENDIAN 261 uint32_t winselect:2; 262 uint32_t hostintr:1; 263 uint32_t pfnum:3; 264 uint32_t vf_cev_int_line_en:1; 265 uint32_t winaddr:23; 266 uint32_t membarwinen:1; 267 #else 268 uint32_t membarwinen:1; 269 uint32_t winaddr:23; 270 uint32_t vf_cev_int_line_en:1; 271 uint32_t pfnum:3; 272 uint32_t hostintr:1; 273 uint32_t winselect:2; 274 #endif 275 } bits; 276 } pcicfg_intr_ctl_t; 277 278 279 280 281 typedef union pcicfg_semaphore_u { 282 uint32_t dw0; 283 struct { 284 #ifdef _BIG_ENDIAN 285 uint32_t rsvd:31; 286 uint32_t lock:1; 287 #else 288 uint32_t lock:1; 289 uint32_t rsvd:31; 290 #endif 291 } bits; 292 } pcicfg_semaphore_t; 293 294 295 296 297 typedef union pcicfg_soft_reset_u { 298 uint32_t dw0; 299 struct { 300 #ifdef _BIG_ENDIAN 301 uint32_t nec_ll_rcvdetect:8; 302 uint32_t dbg_all_reqs_62_49:14; 303 uint32_t scratchpad0:1; 304 uint32_t exception_oe:1; 305 uint32_t soft_reset:1; 306 uint32_t rsvd0:7; 307 #else 308 uint32_t rsvd0:7; 309 uint32_t soft_reset:1; 310 uint32_t exception_oe:1; 311 uint32_t scratchpad0:1; 312 uint32_t dbg_all_reqs_62_49:14; 313 uint32_t nec_ll_rcvdetect:8; 314 #endif 315 } bits; 316 } pcicfg_soft_reset_t; 317 318 319 320 321 typedef union pcicfg_online1_u { 322 uint32_t dw0; 323 struct { 324 #ifdef _BIG_ENDIAN 325 uint32_t host8_online:1; 326 uint32_t host7_online:1; 327 uint32_t host6_online:1; 328 uint32_t host5_online:1; 329 uint32_t host4_online:1; 330 uint32_t host3_online:1; 331 uint32_t host2_online:1; 332 uint32_t ipc_online:1; 333 uint32_t arm_online:1; 334 uint32_t txp_online:1; 335 uint32_t xaui_online:1; 336 uint32_t rxpp_online:1; 337 uint32_t txpb_online:1; 338 uint32_t rr_online:1; 339 uint32_t pmem_online:1; 340 uint32_t pctl1_online:1; 341 uint32_t pctl0_online:1; 342 uint32_t pcs1online_online:1; 343 uint32_t mpu_iram_online:1; 344 uint32_t pcs0online_online:1; 345 uint32_t mgmt_mac_online:1; 346 uint32_t lpcmemhost_online:1; 347 #else 348 uint32_t lpcmemhost_online:1; 349 uint32_t mgmt_mac_online:1; 350 uint32_t pcs0online_online:1; 351 uint32_t mpu_iram_online:1; 352 uint32_t pcs1online_online:1; 353 uint32_t pctl0_online:1; 354 uint32_t pctl1_online:1; 355 uint32_t pmem_online:1; 356 uint32_t rr_online:1; 357 uint32_t txpb_online:1; 358 uint32_t rxpp_online:1; 359 uint32_t xaui_online:1; 360 uint32_t txp_online:1; 361 uint32_t arm_online:1; 362 uint32_t ipc_online:1; 363 uint32_t host2_online:1; 364 uint32_t host3_online:1; 365 uint32_t host4_online:1; 366 uint32_t host5_online:1; 367 uint32_t host6_online:1; 368 uint32_t host7_online:1; 369 uint32_t host8_online:1; 370 #endif 371 } bits; 372 } pcicfg_online1_t; 373 374 375 376 typedef union mpu_ep_semaphore_u { 377 uint32_t dw0; 378 struct { 379 #ifdef _BIG_ENDIAN 380 uint32_t error:1; 381 uint32_t backup_fw:1; 382 uint32_t iscsi_no_ip:1; 383 uint32_t iscsi_ip_conflict:1; 384 uint32_t option_rom_installed:1; 385 uint32_t iscsi_drv_loaded:1; 386 uint32_t rsvd0:10; 387 uint32_t stage:16; 388 #else 389 uint32_t stage:16; 390 uint32_t rsvd0:10; 391 uint32_t iscsi_drv_loaded:1; 392 uint32_t option_rom_installed:1; 393 uint32_t iscsi_ip_conflict:1; 394 uint32_t iscsi_no_ip:1; 395 uint32_t backup_fw:1; 396 uint32_t error:1; 397 #endif 398 } bits; 399 } mpu_ep_semaphore_t; 400 401 402 403 404 typedef union mpu_ep_control_u { 405 uint32_t dw0; 406 struct { 407 #ifdef _BIG_ENDIAN 408 uint32_t cpu_reset:1; 409 uint32_t rsvd1:15; 410 uint32_t ep_ram_init_status:1; 411 uint32_t rsvd0:12; 412 uint32_t m2_rxpbuf:1; 413 uint32_t m1_rxpbuf:1; 414 uint32_t m0_rxpbuf:1; 415 #else 416 uint32_t m0_rxpbuf:1; 417 uint32_t m1_rxpbuf:1; 418 uint32_t m2_rxpbuf:1; 419 uint32_t rsvd0:12; 420 uint32_t ep_ram_init_status:1; 421 uint32_t rsvd1:15; 422 uint32_t cpu_reset:1; 423 #endif 424 } bits; 425 } mpu_ep_control_t; 426 427 428 429 430 /* RX doorbell */ 431 typedef union pd_rxulp_db_u { 432 uint32_t dw0; 433 struct { 434 #ifdef _BIG_ENDIAN 435 uint32_t num_posted:8; 436 uint32_t invalidate:1; 437 uint32_t rsvd1:13; 438 uint32_t qid:10; 439 #else 440 uint32_t qid:10; 441 uint32_t rsvd1:13; 442 uint32_t invalidate:1; 443 uint32_t num_posted:8; 444 #endif 445 } bits; 446 } pd_rxulp_db_t; 447 448 449 /* TX doorbell */ 450 typedef union pd_txulp_db_u { 451 uint32_t dw0; 452 struct { 453 #ifdef _BIG_ENDIAN 454 uint32_t rsvd1:2; 455 uint32_t num_posted:14; 456 uint32_t rsvd0:6; 457 uint32_t qid:10; 458 #else 459 uint32_t qid:10; 460 uint32_t rsvd0:6; 461 uint32_t num_posted:14; 462 uint32_t rsvd1:2; 463 #endif 464 } bits; 465 } pd_txulp_db_t; 466 467 /* CQ doorbell */ 468 typedef union cq_db_u { 469 uint32_t dw0; 470 struct { 471 #ifdef _BIG_ENDIAN 472 uint32_t rsvd1:2; 473 uint32_t rearm:1; 474 uint32_t num_popped:13; 475 uint32_t rsvd0:5; 476 uint32_t event:1; 477 uint32_t qid:10; 478 #else 479 uint32_t qid:10; 480 uint32_t event:1; 481 uint32_t rsvd0:5; 482 uint32_t num_popped:13; 483 uint32_t rearm:1; 484 uint32_t rsvd1:2; 485 #endif 486 } bits; 487 } cq_db_t; 488 489 /* EQ doorbell */ 490 typedef union eq_db_u { 491 uint32_t dw0; 492 struct { 493 #ifdef _BIG_ENDIAN 494 uint32_t rsvd1:2; 495 uint32_t rearm:1; 496 uint32_t num_popped:13; 497 uint32_t rsvd0:5; 498 uint32_t event:1; 499 uint32_t clrint:1; 500 uint32_t qid:9; 501 #else 502 uint32_t qid:9; 503 uint32_t clrint:1; 504 uint32_t event:1; 505 uint32_t rsvd0:5; 506 uint32_t num_popped:13; 507 uint32_t rearm:1; 508 uint32_t rsvd1:2; 509 #endif 510 } bits; 511 } eq_db_t; 512 513 /* bootstrap mbox doorbell */ 514 typedef union pd_mpu_mbox_db_u { 515 uint32_t dw0; 516 struct { 517 #ifdef _BIG_ENDIAN 518 uint32_t address:30; 519 uint32_t hi:1; 520 uint32_t ready:1; 521 #else 522 uint32_t ready:1; 523 uint32_t hi:1; 524 uint32_t address:30; 525 #endif 526 } bits; 527 } pd_mpu_mbox_db_t; 528 529 /* MQ ring doorbell */ 530 typedef union pd_mq_db_u { 531 uint32_t dw0; 532 struct { 533 #ifdef _BIG_ENDIAN 534 uint32_t rsvd1:2; 535 uint32_t num_posted:14; 536 uint32_t rsvd0:5; 537 uint32_t mq_id:11; 538 #else 539 uint32_t mq_id:11; 540 uint32_t rsvd0:5; 541 uint32_t num_posted:14; 542 uint32_t rsvd1:2; 543 #endif 544 } bits; 545 } pd_mq_db_t; 546 547 /* 548 * Event Queue Entry 549 */ 550 struct oce_eqe { 551 uint32_t evnt; 552 }; 553 554 /* MQ scatter gather entry. Array of these make an SGL */ 555 struct oce_mq_sge { 556 uint32_t pa_lo; 557 uint32_t pa_hi; 558 uint32_t length; 559 }; 560 561 /* 562 * payload can contain an SGL or an embedded array of upto 59 dwords 563 */ 564 struct oce_mbx_payload { 565 union { 566 union { 567 struct oce_mq_sge sgl[MAX_MBX_SGE]; 568 uint32_t embedded[59]; 569 } u1; 570 uint32_t dw[59]; 571 } u0; 572 }; 573 574 /* 575 * MQ MBX structure 576 */ 577 struct oce_mbx { 578 union { 579 struct { 580 #ifdef _BIG_ENDIAN 581 uint32_t special:8; 582 uint32_t rsvd1:16; 583 uint32_t sge_count:5; 584 uint32_t rsvd0:2; 585 uint32_t embedded:1; 586 #else 587 uint32_t embedded:1; 588 uint32_t rsvd0:2; 589 uint32_t sge_count:5; 590 uint32_t rsvd1:16; 591 uint32_t special:8; 592 #endif 593 } s; 594 uint32_t dw0; 595 } u0; 596 597 uint32_t payload_length; 598 uint32_t tag[2]; 599 uint32_t rsvd2[1]; 600 struct oce_mbx_payload payload; 601 }; 602 603 /* completion queue entry for MQ */ 604 struct oce_mq_cqe { 605 union { 606 struct { 607 #ifdef _BIG_ENDIAN 608 /* dw0 */ 609 uint32_t extended_status:16; 610 uint32_t completion_status:16; 611 /* dw1 dw2 */ 612 uint32_t mq_tag[2]; 613 /* dw3 */ 614 uint32_t valid:1; 615 uint32_t async_event:1; 616 uint32_t hpi_buffer_cmpl:1; 617 uint32_t completed:1; 618 uint32_t consumed:1; 619 uint32_t rsvd0:3; 620 uint32_t async_type:8; 621 uint32_t event_type:8; 622 uint32_t rsvd1:8; 623 #else 624 /* dw0 */ 625 uint32_t completion_status:16; 626 uint32_t extended_status:16; 627 /* dw1 dw2 */ 628 uint32_t mq_tag[2]; 629 /* dw3 */ 630 uint32_t rsvd1:8; 631 uint32_t event_type:8; 632 uint32_t async_type:8; 633 uint32_t rsvd0:3; 634 uint32_t consumed:1; 635 uint32_t completed:1; 636 uint32_t hpi_buffer_cmpl:1; 637 uint32_t async_event:1; 638 uint32_t valid:1; 639 #endif 640 } s; 641 uint32_t dw[4]; 642 } u0; 643 }; 644 645 /* Mailbox Completion Status Codes */ 646 enum MBX_COMPLETION_STATUS { 647 MBX_CQE_STATUS_SUCCESS = 0x00, 648 MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 0x01, 649 MBX_CQE_STATUS_INVALID_PARAMETER = 0x02, 650 MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 0x03, 651 MBX_CQE_STATUS_QUEUE_FLUSHING = 0x04, 652 MBX_CQE_STATUS_DMA_FAILED = 0x05 653 }; 654 655 struct oce_async_cqe_link_state { 656 union { 657 struct { 658 #ifdef _BIG_ENDIAN 659 /* dw0 */ 660 uint8_t speed; 661 uint8_t duplex; 662 uint8_t link_status; 663 uint8_t phy_port; 664 /* dw1 */ 665 uint16_t qos_link_speed; 666 uint8_t rsvd0; 667 uint8_t fault; 668 /* dw2 */ 669 uint32_t event_tag; 670 /* dw3 */ 671 uint32_t valid:1; 672 uint32_t async_event:1; 673 uint32_t rsvd2:6; 674 uint32_t event_type:8; 675 uint32_t event_code:8; 676 uint32_t rsvd1:8; 677 #else 678 /* dw0 */ 679 uint8_t phy_port; 680 uint8_t link_status; 681 uint8_t duplex; 682 uint8_t speed; 683 /* dw1 */ 684 uint8_t fault; 685 uint8_t rsvd0; 686 uint16_t qos_link_speed; 687 /* dw2 */ 688 uint32_t event_tag; 689 /* dw3 */ 690 uint32_t rsvd1:8; 691 uint32_t event_code:8; 692 uint32_t event_type:8; 693 uint32_t rsvd2:6; 694 uint32_t async_event:1; 695 uint32_t valid:1; 696 #endif 697 } s; 698 uint32_t dw[4]; 699 } u0; 700 }; 701 702 703 /* PVID aync event */ 704 struct oce_async_event_grp5_pvid_state { 705 uint8_t enabled; 706 uint8_t rsvd0; 707 uint16_t tag; 708 uint32_t event_tag; 709 uint32_t rsvd1; 710 uint32_t code; 711 }; 712 713 /* async event indicating outer VLAN tag in QnQ */ 714 struct oce_async_event_qnq { 715 uint8_t valid; /* Indicates if outer VLAN is valid */ 716 uint8_t rsvd0; 717 uint16_t vlan_tag; 718 uint32_t event_tag; 719 uint8_t rsvd1[4]; 720 uint32_t code; 721 } ; 722 723 724 typedef union oce_mq_ext_ctx_u { 725 uint32_t dw[6]; 726 struct { 727 #ifdef _BIG_ENDIAN 728 /* dw0 */ 729 uint32_t dw4rsvd1:16; 730 uint32_t num_pages:16; 731 /* dw1 */ 732 uint32_t async_evt_bitmap; 733 /* dw2 */ 734 uint32_t cq_id:10; 735 uint32_t dw5rsvd2:2; 736 uint32_t ring_size:4; 737 uint32_t dw5rsvd1:16; 738 /* dw3 */ 739 uint32_t valid:1; 740 uint32_t dw6rsvd1:31; 741 /* dw4 */ 742 uint32_t dw7rsvd1:21; 743 uint32_t async_cq_id:10; 744 uint32_t async_cq_valid:1; 745 #else 746 /* dw0 */ 747 uint32_t num_pages:16; 748 uint32_t dw4rsvd1:16; 749 /* dw1 */ 750 uint32_t async_evt_bitmap; 751 /* dw2 */ 752 uint32_t dw5rsvd1:16; 753 uint32_t ring_size:4; 754 uint32_t dw5rsvd2:2; 755 uint32_t cq_id:10; 756 /* dw3 */ 757 uint32_t dw6rsvd1:31; 758 uint32_t valid:1; 759 /* dw4 */ 760 uint32_t async_cq_valid:1; 761 uint32_t async_cq_id:10; 762 uint32_t dw7rsvd1:21; 763 #endif 764 /* dw5 */ 765 uint32_t dw8rsvd1; 766 } v0; 767 struct { 768 #ifdef _BIG_ENDIAN 769 /* dw0 */ 770 uint32_t cq_id:16; 771 uint32_t num_pages:16; 772 /* dw1 */ 773 uint32_t async_evt_bitmap; 774 /* dw2 */ 775 uint32_t dw5rsvd2:12; 776 uint32_t ring_size:4; 777 uint32_t async_cq_id:16; 778 /* dw3 */ 779 uint32_t valid:1; 780 uint32_t dw6rsvd1:31; 781 /* dw4 */ 782 uint32_t dw7rsvd1:31; 783 uint32_t async_cq_valid:1; 784 #else 785 /* dw0 */ 786 uint32_t num_pages:16; 787 uint32_t cq_id:16; 788 /* dw1 */ 789 uint32_t async_evt_bitmap; 790 /* dw2 */ 791 uint32_t async_cq_id:16; 792 uint32_t ring_size:4; 793 uint32_t dw5rsvd2:12; 794 /* dw3 */ 795 uint32_t dw6rsvd1:31; 796 uint32_t valid:1; 797 /* dw4 */ 798 uint32_t async_cq_valid:1; 799 uint32_t dw7rsvd1:31; 800 #endif 801 /* dw5 */ 802 uint32_t dw8rsvd1; 803 } v1; 804 805 } oce_mq_ext_ctx_t; 806 807 808 /* MQ mailbox structure */ 809 struct oce_bmbx { 810 struct oce_mbx mbx; 811 struct oce_mq_cqe cqe; 812 }; 813 814 /* ---[ MBXs start here ]---------------------------------------------- */ 815 /* MBXs sub system codes */ 816 enum MBX_SUBSYSTEM_CODES { 817 MBX_SUBSYSTEM_RSVD = 0, 818 MBX_SUBSYSTEM_COMMON = 1, 819 MBX_SUBSYSTEM_COMMON_ISCSI = 2, 820 MBX_SUBSYSTEM_NIC = 3, 821 MBX_SUBSYSTEM_TOE = 4, 822 MBX_SUBSYSTEM_PXE_UNDI = 5, 823 MBX_SUBSYSTEM_ISCSI_INI = 6, 824 MBX_SUBSYSTEM_ISCSI_TGT = 7, 825 MBX_SUBSYSTEM_MILI_PTL = 8, 826 MBX_SUBSYSTEM_MILI_TMD = 9, 827 MBX_SUBSYSTEM_RDMA = 10, 828 MBX_SUBSYSTEM_LOWLEVEL = 11, 829 MBX_SUBSYSTEM_LRO = 13, 830 IOCBMBX_SUBSYSTEM_DCBX = 15, 831 IOCBMBX_SUBSYSTEM_DIAG = 16, 832 IOCBMBX_SUBSYSTEM_VENDOR = 17 833 }; 834 835 /* common ioctl opcodes */ 836 enum COMMON_SUBSYSTEM_OPCODES { 837 /* These opcodes are common to both networking and storage PCI functions 838 * They are used to reserve resources and configure CNA. These opcodes 839 * all use the MBX_SUBSYSTEM_COMMON subsystem code. 840 */ 841 OPCODE_COMMON_QUERY_IFACE_MAC = 1, 842 OPCODE_COMMON_SET_IFACE_MAC = 2, 843 OPCODE_COMMON_SET_IFACE_MULTICAST = 3, 844 OPCODE_COMMON_CONFIG_IFACE_VLAN = 4, 845 OPCODE_COMMON_QUERY_LINK_CONFIG = 5, 846 OPCODE_COMMON_READ_FLASHROM = 6, 847 OPCODE_COMMON_WRITE_FLASHROM = 7, 848 OPCODE_COMMON_QUERY_MAX_MBX_BUFFER_SIZE = 8, 849 OPCODE_COMMON_CREATE_CQ = 12, 850 OPCODE_COMMON_CREATE_EQ = 13, 851 OPCODE_COMMON_CREATE_MQ = 21, 852 OPCODE_COMMON_GET_QOS = 27, 853 OPCODE_COMMON_SET_QOS = 28, 854 OPCODE_COMMON_READ_EPROM = 30, 855 OPCODE_COMMON_GET_CNTL_ATTRIBUTES = 32, 856 OPCODE_COMMON_NOP = 33, 857 OPCODE_COMMON_SET_IFACE_RX_FILTER = 34, 858 OPCODE_COMMON_GET_FW_VERSION = 35, 859 OPCODE_COMMON_SET_FLOW_CONTROL = 36, 860 OPCODE_COMMON_GET_FLOW_CONTROL = 37, 861 OPCODE_COMMON_SET_FRAME_SIZE = 39, 862 OPCODE_COMMON_MODIFY_EQ_DELAY = 41, 863 OPCODE_COMMON_CREATE_IFACE = 50, 864 OPCODE_COMMON_DESTROY_IFACE = 51, 865 OPCODE_COMMON_MODIFY_MSI_MESSAGES = 52, 866 OPCODE_COMMON_DESTROY_MQ = 53, 867 OPCODE_COMMON_DESTROY_CQ = 54, 868 OPCODE_COMMON_DESTROY_EQ = 55, 869 OPCODE_COMMON_UPLOAD_TCP = 56, 870 OPCODE_COMMON_SET_NTWK_LINK_SPEED = 57, 871 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG = 58, 872 OPCODE_COMMON_ADD_IFACE_MAC = 59, 873 OPCODE_COMMON_DEL_IFACE_MAC = 60, 874 OPCODE_COMMON_FUNCTION_RESET = 61, 875 OPCODE_COMMON_SET_PHYSICAL_LINK_CONFIG = 62, 876 OPCODE_COMMON_GET_BOOT_CONFIG = 66, 877 OPCPDE_COMMON_SET_BOOT_CONFIG = 67, 878 OPCODE_COMMON_SET_BEACON_CONFIG = 69, 879 OPCODE_COMMON_GET_BEACON_CONFIG = 70, 880 OPCODE_COMMON_GET_PHYSICAL_LINK_CONFIG = 71, 881 OPCODE_COMMON_READ_TRANSRECEIVER_DATA = 73, 882 OPCODE_COMMON_GET_OEM_ATTRIBUTES = 76, 883 OPCODE_COMMON_GET_PORT_NAME = 77, 884 OPCODE_COMMON_GET_CONFIG_SIGNATURE = 78, 885 OPCODE_COMMON_SET_CONFIG_SIGNATURE = 79, 886 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG = 80, 887 OPCODE_COMMON_GET_BE_CONFIGURATION_RESOURCES = 81, 888 OPCODE_COMMON_SET_BE_CONFIGURATION_RESOURCES = 82, 889 OPCODE_COMMON_GET_RESET_NEEDED = 84, 890 OPCODE_COMMON_GET_SERIAL_NUMBER = 85, 891 OPCODE_COMMON_GET_NCSI_CONFIG = 86, 892 OPCODE_COMMON_SET_NCSI_CONFIG = 87, 893 OPCODE_COMMON_CREATE_MQ_EXT = 90, 894 OPCODE_COMMON_SET_FUNCTION_PRIVILEGES = 100, 895 OPCODE_COMMON_SET_VF_PORT_TYPE = 101, 896 OPCODE_COMMON_GET_PHY_CONFIG = 102, 897 OPCODE_COMMON_SET_FUNCTIONAL_CAPS = 103, 898 OPCODE_COMMON_GET_ADAPTER_ID = 110, 899 OPCODE_COMMON_GET_UPGRADE_FEATURES = 111, 900 OPCODE_COMMON_GET_INSTALLED_FEATURES = 112, 901 OPCODE_COMMON_GET_AVAIL_PERSONALITIES = 113, 902 OPCODE_COMMON_GET_CONFIG_PERSONALITIES = 114, 903 OPCODE_COMMON_SEND_ACTIVATION = 115, 904 OPCODE_COMMON_RESET_LICENSES = 116, 905 OPCODE_COMMON_GET_CNTL_ADDL_ATTRIBUTES = 121, 906 OPCODE_COMMON_QUERY_TCB = 144, 907 OPCODE_COMMON_ADD_IFACE_QUEUE_FILTER = 145, 908 OPCODE_COMMON_DEL_IFACE_QUEUE_FILTER = 146, 909 OPCODE_COMMON_GET_IFACE_MAC_LIST = 147, 910 OPCODE_COMMON_SET_IFACE_MAC_LIST = 148, 911 OPCODE_COMMON_MODIFY_CQ = 149, 912 OPCODE_COMMON_GET_IFACE_VLAN_LIST = 150, 913 OPCODE_COMMON_SET_IFACE_VLAN_LIST = 151, 914 OPCODE_COMMON_GET_HSW_CONFIG = 152, 915 OPCODE_COMMON_SET_HSW_CONFIG = 153, 916 OPCODE_COMMON_GET_RESOURCE_EXTENT_INFO = 154, 917 OPCODE_COMMON_GET_ALLOCATED_RESOURCE_EXTENTS = 155, 918 OPCODE_COMMON_ALLOC_RESOURCE_EXTENTS = 156, 919 OPCODE_COMMON_DEALLOC_RESOURCE_EXTENTS = 157, 920 OPCODE_COMMON_SET_DIAG_REGISTERS = 158, 921 OPCODE_COMMON_GET_FUNCTION_CONFIG = 160, 922 OPCODE_COMMON_GET_PROFILE_CAPACITIES = 161, 923 OPCODE_COMMON_GET_MR_PROFILE_CAPACITIES = 162, 924 OPCODE_COMMON_SET_MR_PROFILE_CAPACITIES = 163, 925 OPCODE_COMMON_GET_PROFILE_CONFIG = 164, 926 OPCODE_COMMON_SET_PROFILE_CONFIG = 165, 927 OPCODE_COMMON_GET_PROFILE_LIST = 166, 928 OPCODE_COMMON_GET_ACTIVE_PROFILE = 167, 929 OPCODE_COMMON_SET_ACTIVE_PROFILE = 168, 930 OPCODE_COMMON_GET_FUNCTION_PRIVILEGES = 170, 931 OPCODE_COMMON_READ_OBJECT = 171, 932 OPCODE_COMMON_WRITE_OBJECT = 172 933 }; 934 935 /* common ioctl header */ 936 #define OCE_MBX_VER_V2 0x0002 /* Version V2 mailbox command */ 937 #define OCE_MBX_VER_V1 0x0001 /* Version V1 mailbox command */ 938 #define OCE_MBX_VER_V0 0x0000 /* Version V0 mailbox command */ 939 struct mbx_hdr { 940 union { 941 uint32_t dw[4]; 942 struct { 943 #ifdef _BIG_ENDIAN 944 /* dw 0 */ 945 uint32_t domain:8; 946 uint32_t port_number:8; 947 uint32_t subsystem:8; 948 uint32_t opcode:8; 949 /* dw 1 */ 950 uint32_t timeout; 951 /* dw 2 */ 952 uint32_t request_length; 953 /* dw 3 */ 954 uint32_t rsvd0:24; 955 uint32_t version:8; 956 #else 957 /* dw 0 */ 958 uint32_t opcode:8; 959 uint32_t subsystem:8; 960 uint32_t port_number:8; 961 uint32_t domain:8; 962 /* dw 1 */ 963 uint32_t timeout; 964 /* dw 2 */ 965 uint32_t request_length; 966 /* dw 3 */ 967 uint32_t version:8; 968 uint32_t rsvd0:24; 969 #endif 970 } req; 971 struct { 972 #ifdef _BIG_ENDIAN 973 /* dw 0 */ 974 uint32_t domain:8; 975 uint32_t rsvd0:8; 976 uint32_t subsystem:8; 977 uint32_t opcode:8; 978 /* dw 1 */ 979 uint32_t rsvd1:16; 980 uint32_t additional_status:8; 981 uint32_t status:8; 982 #else 983 /* dw 0 */ 984 uint32_t opcode:8; 985 uint32_t subsystem:8; 986 uint32_t rsvd0:8; 987 uint32_t domain:8; 988 /* dw 1 */ 989 uint32_t status:8; 990 uint32_t additional_status:8; 991 uint32_t rsvd1:16; 992 #endif 993 uint32_t rsp_length; 994 uint32_t actual_rsp_length; 995 } rsp; 996 } u0; 997 }; 998 #define OCE_BMBX_RHDR_SZ 20 999 #define OCE_MBX_RRHDR_SZ sizeof (struct mbx_hdr) 1000 #define OCE_MBX_ADDL_STATUS(_MHDR) ((_MHDR)->u0.rsp.additional_status) 1001 #define OCE_MBX_STATUS(_MHDR) ((_MHDR)->u0.rsp.status) 1002 1003 /* [05] OPCODE_COMMON_QUERY_LINK_CONFIG */ 1004 struct mbx_query_common_link_config { 1005 struct mbx_hdr hdr; 1006 union { 1007 struct { 1008 uint32_t rsvd0; 1009 } req; 1010 1011 struct { 1012 /* dw 0 */ 1013 uint8_t physical_port; 1014 uint8_t mac_duplex; 1015 uint8_t mac_speed; 1016 uint8_t mac_fault; 1017 /* dw 1 */ 1018 uint8_t mgmt_mac_duplex; 1019 uint8_t mgmt_mac_speed; 1020 uint16_t qos_link_speed; 1021 uint32_t logical_link_status; 1022 } rsp; 1023 } params; 1024 }; 1025 1026 /* [57] OPCODE_COMMON_SET_LINK_SPEED */ 1027 struct mbx_set_common_link_speed { 1028 struct mbx_hdr hdr; 1029 union { 1030 struct { 1031 #ifdef _BIG_ENDIAN 1032 uint8_t rsvd0; 1033 uint8_t mac_speed; 1034 uint8_t virtual_port; 1035 uint8_t physical_port; 1036 #else 1037 uint8_t physical_port; 1038 uint8_t virtual_port; 1039 uint8_t mac_speed; 1040 uint8_t rsvd0; 1041 #endif 1042 } req; 1043 1044 struct { 1045 uint32_t rsvd0; 1046 } rsp; 1047 1048 uint32_t dw; 1049 } params; 1050 }; 1051 1052 struct mac_address_format { 1053 uint16_t size_of_struct; 1054 uint8_t mac_addr[6]; 1055 }; 1056 1057 /* [01] OPCODE_COMMON_QUERY_IFACE_MAC */ 1058 struct mbx_query_common_iface_mac { 1059 struct mbx_hdr hdr; 1060 union { 1061 struct { 1062 #ifdef _BIG_ENDIAN 1063 uint16_t if_id; 1064 uint8_t permanent; 1065 uint8_t type; 1066 #else 1067 uint8_t type; 1068 uint8_t permanent; 1069 uint16_t if_id; 1070 #endif 1071 1072 } req; 1073 1074 struct { 1075 struct mac_address_format mac; 1076 } rsp; 1077 } params; 1078 }; 1079 1080 /* [02] OPCODE_COMMON_SET_IFACE_MAC */ 1081 struct mbx_set_common_iface_mac { 1082 struct mbx_hdr hdr; 1083 union { 1084 struct { 1085 #ifdef _BIG_ENDIAN 1086 /* dw 0 */ 1087 uint16_t if_id; 1088 uint8_t invalidate; 1089 uint8_t type; 1090 #else 1091 /* dw 0 */ 1092 uint8_t type; 1093 uint8_t invalidate; 1094 uint16_t if_id; 1095 #endif 1096 /* dw 1 */ 1097 struct mac_address_format mac; 1098 } req; 1099 1100 struct { 1101 uint32_t rsvd0; 1102 } rsp; 1103 1104 uint32_t dw[2]; 1105 } params; 1106 }; 1107 1108 /* [03] OPCODE_COMMON_SET_IFACE_MULTICAST */ 1109 struct mbx_set_common_iface_multicast { 1110 struct mbx_hdr hdr; 1111 union { 1112 struct { 1113 /* dw 0 */ 1114 uint16_t num_mac; 1115 uint8_t promiscuous; 1116 uint8_t if_id; 1117 /* dw 1-48 */ 1118 struct { 1119 uint8_t byte[6]; 1120 } mac[32]; 1121 1122 } req; 1123 1124 struct { 1125 uint32_t rsvd0; 1126 } rsp; 1127 1128 uint32_t dw[49]; 1129 } params; 1130 }; 1131 1132 struct qinq_vlan { 1133 #ifdef _BIG_ENDIAN 1134 uint16_t inner; 1135 uint16_t outer; 1136 #else 1137 uint16_t outer; 1138 uint16_t inner; 1139 #endif 1140 }; 1141 1142 struct normal_vlan { 1143 uint16_t vtag; 1144 }; 1145 1146 struct ntwk_if_vlan_tag { 1147 union { 1148 struct normal_vlan normal; 1149 struct qinq_vlan qinq; 1150 } u0; 1151 }; 1152 1153 /* [50] OPCODE_COMMON_CREATE_IFACE */ 1154 struct mbx_create_common_iface { 1155 struct mbx_hdr hdr; 1156 union { 1157 struct { 1158 uint32_t version; 1159 uint32_t cap_flags; 1160 uint32_t enable_flags; 1161 uint8_t mac_addr[6]; 1162 uint8_t rsvd0; 1163 uint8_t mac_invalid; 1164 struct ntwk_if_vlan_tag vlan_tag; 1165 } req; 1166 1167 struct { 1168 uint32_t if_id; 1169 uint32_t pmac_id; 1170 } rsp; 1171 uint32_t dw[4]; 1172 } params; 1173 }; 1174 1175 /* [51] OPCODE_COMMON_DESTROY_IFACE */ 1176 struct mbx_destroy_common_iface { 1177 struct mbx_hdr hdr; 1178 union { 1179 struct { 1180 uint32_t if_id; 1181 } req; 1182 1183 struct { 1184 uint32_t rsvd0; 1185 } rsp; 1186 1187 uint32_t dw; 1188 } params; 1189 }; 1190 1191 /* event queue context structure */ 1192 struct oce_eq_ctx { 1193 #ifdef _BIG_ENDIAN 1194 uint32_t dw4rsvd1:16; 1195 uint32_t num_pages:16; 1196 1197 uint32_t size:1; 1198 uint32_t dw5rsvd2:1; 1199 uint32_t valid:1; 1200 uint32_t dw5rsvd1:29; 1201 1202 uint32_t armed:1; 1203 uint32_t dw6rsvd2:2; 1204 uint32_t count:3; 1205 uint32_t dw6rsvd1:26; 1206 1207 uint32_t dw7rsvd2:9; 1208 uint32_t delay_mult:10; 1209 uint32_t dw7rsvd1:13; 1210 1211 uint32_t dw8rsvd1; 1212 #else 1213 uint32_t num_pages:16; 1214 uint32_t dw4rsvd1:16; 1215 1216 uint32_t dw5rsvd1:29; 1217 uint32_t valid:1; 1218 uint32_t dw5rsvd2:1; 1219 uint32_t size:1; 1220 1221 uint32_t dw6rsvd1:26; 1222 uint32_t count:3; 1223 uint32_t dw6rsvd2:2; 1224 uint32_t armed:1; 1225 1226 uint32_t dw7rsvd1:13; 1227 uint32_t delay_mult:10; 1228 uint32_t dw7rsvd2:9; 1229 1230 uint32_t dw8rsvd1; 1231 #endif 1232 }; 1233 1234 /* [13] OPCODE_COMMON_CREATE_EQ */ 1235 struct mbx_create_common_eq { 1236 struct mbx_hdr hdr; 1237 union { 1238 struct { 1239 struct oce_eq_ctx ctx; 1240 struct phys_addr pages[8]; 1241 } req; 1242 1243 struct { 1244 uint16_t eq_id; 1245 uint16_t rsvd0; 1246 } rsp; 1247 } params; 1248 }; 1249 1250 /* [55] OPCODE_COMMON_DESTROY_EQ */ 1251 struct mbx_destroy_common_eq { 1252 struct mbx_hdr hdr; 1253 union { 1254 struct { 1255 #ifdef _BIG_ENDIAN 1256 uint16_t rsvd0; 1257 uint16_t id; 1258 #else 1259 uint16_t id; 1260 uint16_t rsvd0; 1261 #endif 1262 } req; 1263 1264 struct { 1265 uint32_t rsvd0; 1266 } rsp; 1267 } params; 1268 }; 1269 1270 /* SLI-4 CQ context - use version V0 for B3, version V2 for Lancer */ 1271 typedef union oce_cq_ctx_u { 1272 uint32_t dw[5]; 1273 struct { 1274 #ifdef _BIG_ENDIAN 1275 /* dw4 */ 1276 uint32_t dw4rsvd1:16; 1277 uint32_t num_pages:16; 1278 /* dw5 */ 1279 uint32_t eventable:1; 1280 uint32_t dw5rsvd3:1; 1281 uint32_t valid:1; 1282 uint32_t count:2; 1283 uint32_t dw5rsvd2:12; 1284 uint32_t nodelay:1; 1285 uint32_t coalesce_wm:2; 1286 uint32_t dw5rsvd1:12; 1287 /* dw6 */ 1288 uint32_t armed:1; 1289 uint32_t dw6rsvd2:1; 1290 uint32_t eq_id:8; 1291 uint32_t dw6rsvd1:22; 1292 #else 1293 /* dw4 */ 1294 uint32_t num_pages:16; 1295 uint32_t dw4rsvd1:16; 1296 /* dw5 */ 1297 uint32_t dw5rsvd1:12; 1298 uint32_t coalesce_wm:2; 1299 uint32_t nodelay:1; 1300 uint32_t dw5rsvd2:12; 1301 uint32_t count:2; 1302 uint32_t valid:1; 1303 uint32_t dw5rsvd3:1; 1304 uint32_t eventable:1; 1305 /* dw6 */ 1306 uint32_t dw6rsvd1:22; 1307 uint32_t eq_id:8; 1308 uint32_t dw6rsvd2:1; 1309 uint32_t armed:1; 1310 #endif 1311 /* dw7 */ 1312 uint32_t dw7rsvd1; 1313 /* dw8 */ 1314 uint32_t dw8rsvd1; 1315 } v0; 1316 struct { 1317 #ifdef _BIG_ENDIAN 1318 /* dw4 */ 1319 uint32_t dw4rsvd1:8; 1320 uint32_t page_size:8; 1321 uint32_t num_pages:16; 1322 /* dw5 */ 1323 uint32_t eventable:1; 1324 uint32_t dw5rsvd3:1; 1325 uint32_t valid:1; 1326 uint32_t count:2; 1327 uint32_t dw5rsvd2:11; 1328 uint32_t autovalid:1; 1329 uint32_t nodelay:1; 1330 uint32_t coalesce_wm:2; 1331 uint32_t dw5rsvd1:12; 1332 /* dw6 */ 1333 uint32_t armed:1; 1334 uint32_t dw6rsvd1:15; 1335 uint32_t eq_id:16; 1336 /* dw7 */ 1337 uint32_t dw7rsvd1:16; 1338 uint32_t cqe_count:16; 1339 #else 1340 /* dw4 */ 1341 uint32_t num_pages:16; 1342 uint32_t page_size:8; 1343 uint32_t dw4rsvd1:8; 1344 /* dw5 */ 1345 uint32_t dw5rsvd1:12; 1346 uint32_t coalesce_wm:2; 1347 uint32_t nodelay:1; 1348 uint32_t autovalid:1; 1349 uint32_t dw5rsvd2:11; 1350 uint32_t count:2; 1351 uint32_t valid:1; 1352 uint32_t dw5rsvd3:1; 1353 uint32_t eventable:1; 1354 /* dw6 */ 1355 uint32_t eq_id:8; 1356 uint32_t dw6rsvd1:15; 1357 uint32_t armed:1; 1358 /* dw7 */ 1359 uint32_t cqe_count:16; 1360 uint32_t dw7rsvd1:16; 1361 #endif 1362 /* dw8 */ 1363 uint32_t dw8rsvd1; 1364 } v2; 1365 } oce_cq_ctx_t; 1366 1367 /* [12] OPCODE_COMMON_CREATE_CQ */ 1368 struct mbx_create_common_cq { 1369 struct mbx_hdr hdr; 1370 union { 1371 struct { 1372 oce_cq_ctx_t cq_ctx; 1373 struct phys_addr pages[4]; 1374 } req; 1375 1376 struct { 1377 uint16_t cq_id; 1378 uint16_t rsvd0; 1379 } rsp; 1380 } params; 1381 }; 1382 1383 /* [54] OPCODE_COMMON_DESTROY_CQ */ 1384 struct mbx_destroy_common_cq { 1385 struct mbx_hdr hdr; 1386 union { 1387 struct { 1388 #ifdef _BIG_ENDIAN 1389 uint16_t rsvd0; 1390 uint16_t id; 1391 #else 1392 uint16_t id; 1393 uint16_t rsvd0; 1394 #endif 1395 } req; 1396 1397 struct { 1398 uint32_t rsvd0; 1399 } rsp; 1400 } params; 1401 }; 1402 1403 typedef union oce_mq_ctx_u { 1404 uint32_t dw[5]; 1405 struct { 1406 #ifdef _BIG_ENDIAN 1407 /* dw4 */ 1408 uint32_t dw4rsvd1:16; 1409 uint32_t num_pages:16; 1410 /* dw5 */ 1411 uint32_t cq_id:10; 1412 uint32_t dw5rsvd2:2; 1413 uint32_t ring_size:4; 1414 uint32_t dw5rsvd1:16; 1415 /* dw6 */ 1416 uint32_t valid:1; 1417 uint32_t dw6rsvd1:31; 1418 /* dw7 */ 1419 uint32_t dw7rsvd1:21; 1420 uint32_t async_cq_id:10; 1421 uint32_t async_cq_valid:1; 1422 #else 1423 /* dw4 */ 1424 uint32_t num_pages:16; 1425 uint32_t dw4rsvd1:16; 1426 /* dw5 */ 1427 uint32_t dw5rsvd1:16; 1428 uint32_t ring_size:4; 1429 uint32_t dw5rsvd2:2; 1430 uint32_t cq_id:10; 1431 /* dw6 */ 1432 uint32_t dw6rsvd1:31; 1433 uint32_t valid:1; 1434 /* dw7 */ 1435 uint32_t async_cq_valid:1; 1436 uint32_t async_cq_id:10; 1437 uint32_t dw7rsvd1:21; 1438 #endif 1439 /* dw8 */ 1440 uint32_t dw8rsvd1; 1441 } v0; 1442 } oce_mq_ctx_t; 1443 1444 /** 1445 * @brief [21] OPCODE_COMMON_CREATE_MQ 1446 * A MQ must be at least 16 entries deep (corresponding to 1 page) and 1447 * at most 128 entries deep (corresponding to 8 pages). 1448 */ 1449 struct mbx_create_common_mq { 1450 struct mbx_hdr hdr; 1451 union { 1452 struct { 1453 oce_mq_ctx_t context; 1454 struct phys_addr pages[8]; 1455 } req; 1456 1457 struct { 1458 uint32_t mq_id:16; 1459 uint32_t rsvd0:16; 1460 } rsp; 1461 } params; 1462 }; 1463 1464 struct mbx_create_common_mq_ex { 1465 struct mbx_hdr hdr; 1466 union { 1467 struct { 1468 oce_mq_ext_ctx_t context; 1469 struct phys_addr pages[8]; 1470 } req; 1471 1472 struct { 1473 uint32_t mq_id:16; 1474 uint32_t rsvd0:16; 1475 } rsp; 1476 } params; 1477 }; 1478 1479 1480 1481 /* [53] OPCODE_COMMON_DESTROY_MQ */ 1482 struct mbx_destroy_common_mq { 1483 struct mbx_hdr hdr; 1484 union { 1485 struct { 1486 #ifdef _BIG_ENDIAN 1487 uint16_t rsvd0; 1488 uint16_t id; 1489 #else 1490 uint16_t id; 1491 uint16_t rsvd0; 1492 #endif 1493 } req; 1494 1495 struct { 1496 uint32_t rsvd0; 1497 } rsp; 1498 } params; 1499 }; 1500 1501 /* [35] OPCODE_COMMON_GET_ FW_VERSION */ 1502 struct mbx_get_common_fw_version { 1503 struct mbx_hdr hdr; 1504 union { 1505 struct { 1506 uint32_t rsvd0; 1507 } req; 1508 1509 struct { 1510 uint8_t fw_ver_str[32]; 1511 uint8_t fw_on_flash_ver_str[32]; 1512 } rsp; 1513 } params; 1514 }; 1515 1516 /* [52] OPCODE_COMMON_CEV_MODIFY_MSI_MESSAGES */ 1517 struct mbx_common_cev_modify_msi_messages { 1518 struct mbx_hdr hdr; 1519 union { 1520 struct { 1521 uint32_t num_msi_msgs; 1522 } req; 1523 1524 struct { 1525 uint32_t rsvd0; 1526 } rsp; 1527 } params; 1528 }; 1529 1530 /* [36] OPCODE_COMMON_SET_FLOW_CONTROL */ 1531 /* [37] OPCODE_COMMON_GET_FLOW_CONTROL */ 1532 struct mbx_common_get_set_flow_control { 1533 struct mbx_hdr hdr; 1534 #ifdef _BIG_ENDIAN 1535 uint16_t tx_flow_control; 1536 uint16_t rx_flow_control; 1537 #else 1538 uint16_t rx_flow_control; 1539 uint16_t tx_flow_control; 1540 #endif 1541 }; 1542 1543 enum e_flash_opcode { 1544 MGMT_FLASHROM_OPCODE_FLASH = 1, 1545 MGMT_FLASHROM_OPCODE_SAVE = 2 1546 }; 1547 1548 /* [06] OPCODE_READ_COMMON_FLASHROM */ 1549 /* [07] OPCODE_WRITE_COMMON_FLASHROM */ 1550 1551 struct mbx_common_read_write_flashrom { 1552 struct mbx_hdr hdr; 1553 uint32_t flash_op_code; 1554 uint32_t flash_op_type; 1555 uint32_t data_buffer_size; 1556 uint32_t data_offset; 1557 uint8_t data_buffer[4]; /* + IMAGE_TRANSFER_SIZE */ 1558 }; 1559 1560 struct oce_phy_info { 1561 uint16_t phy_type; 1562 uint16_t interface_type; 1563 uint32_t misc_params; 1564 uint16_t ext_phy_details; 1565 uint16_t rsvd; 1566 uint16_t auto_speeds_supported; 1567 uint16_t fixed_speeds_supported; 1568 uint32_t future_use[2]; 1569 }; 1570 1571 struct mbx_common_phy_info { 1572 struct mbx_hdr hdr; 1573 union { 1574 struct { 1575 uint32_t rsvd0[4]; 1576 } req; 1577 struct { 1578 struct oce_phy_info phy_info; 1579 } rsp; 1580 } params; 1581 }; 1582 1583 /*Lancer firmware*/ 1584 1585 struct mbx_lancer_common_write_object { 1586 union { 1587 struct { 1588 struct mbx_hdr hdr; 1589 uint32_t write_length: 24; 1590 uint32_t rsvd: 7; 1591 uint32_t eof: 1; 1592 uint32_t write_offset; 1593 uint8_t object_name[104]; 1594 uint32_t descriptor_count; 1595 uint32_t buffer_length; 1596 uint32_t address_lower; 1597 uint32_t address_upper; 1598 } req; 1599 struct { 1600 uint8_t opcode; 1601 uint8_t subsystem; 1602 uint8_t rsvd1[2]; 1603 uint8_t status; 1604 uint8_t additional_status; 1605 uint8_t rsvd2[2]; 1606 uint32_t response_length; 1607 uint32_t actual_response_length; 1608 uint32_t actual_write_length; 1609 } rsp; 1610 } params; 1611 }; 1612 1613 /** 1614 * @brief MBX Common Quiery Firmaware Config 1615 * This command retrieves firmware configuration parameters and adapter 1616 * resources available to the driver originating the request. The firmware 1617 * configuration defines supported protocols by the installed adapter firmware. 1618 * This includes which ULP processors support the specified protocols and 1619 * the number of TCP connections allowed for that protocol. 1620 */ 1621 struct mbx_common_query_fw_config { 1622 struct mbx_hdr hdr; 1623 union { 1624 struct { 1625 uint32_t rsvd0[30]; 1626 } req; 1627 1628 struct { 1629 uint32_t config_number; 1630 uint32_t asic_revision; 1631 uint32_t port_id; /* used for stats retrieval */ 1632 uint32_t function_mode; 1633 struct { 1634 1635 uint32_t ulp_mode; 1636 uint32_t nic_wqid_base; 1637 uint32_t nic_wq_tot; 1638 uint32_t toe_wqid_base; 1639 uint32_t toe_wq_tot; 1640 uint32_t toe_rqid_base; 1641 uint32_t toe_rqid_tot; 1642 uint32_t toe_defrqid_base; 1643 uint32_t toe_defrqid_count; 1644 uint32_t lro_rqid_base; 1645 uint32_t lro_rqid_tot; 1646 uint32_t iscsi_icd_base; 1647 uint32_t iscsi_icd_count; 1648 } ulp[2]; 1649 uint32_t function_caps; 1650 uint32_t cqid_base; 1651 uint32_t cqid_tot; 1652 uint32_t eqid_base; 1653 uint32_t eqid_tot; 1654 } rsp; 1655 } params; 1656 }; 1657 1658 enum CQFW_CONFIG_NUMBER { 1659 FCN_NIC_ISCSI_Initiator = 0x0, 1660 FCN_ISCSI_Target = 0x3, 1661 FCN_FCoE = 0x7, 1662 FCN_ISCSI_Initiator_Target = 0x9, 1663 FCN_NIC_RDMA_TOE = 0xA, 1664 FCN_NIC_RDMA_FCoE = 0xB, 1665 FCN_NIC_RDMA_iSCSI = 0xC, 1666 FCN_NIC_iSCSI_FCoE = 0xD 1667 }; 1668 1669 /** 1670 * @brief Function Capabilites 1671 * This field contains the flags indicating the capabilities of 1672 * the SLI Host’s PCI function. 1673 */ 1674 enum CQFW_FUNCTION_CAPABILITIES { 1675 FNC_UNCLASSIFIED_STATS = 0x1, 1676 FNC_RSS = 0x2, 1677 FNC_PROMISCUOUS = 0x4, 1678 FNC_LEGACY_MODE = 0x8, 1679 FNC_HDS = 0x4000, 1680 FNC_VMQ = 0x10000, 1681 FNC_NETQ = 0x20000, 1682 FNC_QGROUPS = 0x40000, 1683 FNC_LRO = 0x100000, 1684 FNC_VLAN_OFFLOAD = 0x800000 1685 }; 1686 1687 enum CQFW_ULP_MODES_SUPPORTED { 1688 ULP_TOE_MODE = 0x1, 1689 ULP_NIC_MODE = 0x2, 1690 ULP_RDMA_MODE = 0x4, 1691 ULP_ISCSI_INI_MODE = 0x10, 1692 ULP_ISCSI_TGT_MODE = 0x20, 1693 ULP_FCOE_INI_MODE = 0x40, 1694 ULP_FCOE_TGT_MODE = 0x80, 1695 ULP_DAL_MODE = 0x100, 1696 ULP_LRO_MODE = 0x200 1697 }; 1698 1699 /** 1700 * @brief Function Modes Supported 1701 * Valid function modes (or protocol-types) supported on the SLI-Host’s 1702 * PCIe function. This field is a logical OR of the following values: 1703 */ 1704 enum CQFW_FUNCTION_MODES_SUPPORTED { 1705 FNM_TOE_MODE = 0x1, /* TCP offload supported */ 1706 FNM_NIC_MODE = 0x2, /* Raw Ethernet supported */ 1707 FNM_RDMA_MODE = 0x4, /* RDMA protocol supported */ 1708 FNM_VM_MODE = 0x8, /* Virtual Machines supported */ 1709 FNM_ISCSI_INI_MODE = 0x10, /* iSCSI initiator supported */ 1710 FNM_ISCSI_TGT_MODE = 0x20, /* iSCSI target plus initiator */ 1711 FNM_FCOE_INI_MODE = 0x40, /* FCoE Initiator supported */ 1712 FNM_FCOE_TGT_MODE = 0x80, /* FCoE target supported */ 1713 FNM_DAL_MODE = 0x100, /* DAL supported */ 1714 FNM_LRO_MODE = 0x200, /* LRO supported */ 1715 FNM_FLEX10_MODE = 0x400, /* QinQ, FLEX-10 or VNIC */ 1716 FNM_NCSI_MODE = 0x800, /* NCSI supported */ 1717 FNM_IPV6_MODE = 0x1000, /* IPV6 stack enabled */ 1718 FNM_BE2_COMPAT_MODE = 0x2000, /* BE2 compatibility (BE3 disable)*/ 1719 FNM_INVALID_MODE = 0x8000, /* Invalid */ 1720 FNM_BE3_COMPAT_MODE = 0x10000, /* BE3 features */ 1721 FNM_VNIC_MODE = 0x20000, /* Set when IBM vNIC mode is set */ 1722 FNM_VNTAG_MODE = 0x40000, /* Set when VNTAG mode is set */ 1723 FNM_UMC_MODE = 0x1000000, /* Set when UMC mode is set */ 1724 FNM_UMC_DEF_EN = 0x100000, /* Set when UMC Default is set */ 1725 FNM_ONE_GB_EN = 0x200000, /* Set when 1GB Default is set */ 1726 FNM_VNIC_DEF_VALID = 0x400000, /* Set when VNIC_DEF_EN is valid */ 1727 FNM_VNIC_DEF_EN = 0x800000 /* Set when VNIC Default enabled */ 1728 }; 1729 1730 1731 struct mbx_common_config_vlan { 1732 struct mbx_hdr hdr; 1733 union { 1734 struct { 1735 #ifdef _BIG_ENDIAN 1736 uint8_t num_vlans; 1737 uint8_t untagged; 1738 uint8_t promisc; 1739 uint8_t if_id; 1740 #else 1741 uint8_t if_id; 1742 uint8_t promisc; 1743 uint8_t untagged; 1744 uint8_t num_vlans; 1745 #endif 1746 union { 1747 struct normal_vlan normal_vlans[64]; 1748 struct qinq_vlan qinq_vlans[32]; 1749 } tags; 1750 } req; 1751 1752 struct { 1753 uint32_t rsvd; 1754 } rsp; 1755 } params; 1756 }; 1757 1758 typedef struct iface_rx_filter_ctx { 1759 uint32_t global_flags_mask; 1760 uint32_t global_flags; 1761 uint32_t iface_flags_mask; 1762 uint32_t iface_flags; 1763 uint32_t if_id; 1764 #define IFACE_RX_NUM_MCAST_MAX 64 1765 uint32_t num_mcast; 1766 struct mbx_mcast_addr { 1767 uint8_t byte[6]; 1768 } mac[IFACE_RX_NUM_MCAST_MAX]; 1769 } iface_rx_filter_ctx_t; 1770 1771 /* [34] OPCODE_COMMON_SET_IFACE_RX_FILTER */ 1772 struct mbx_set_common_iface_rx_filter { 1773 struct mbx_hdr hdr; 1774 union { 1775 iface_rx_filter_ctx_t req; 1776 iface_rx_filter_ctx_t rsp; 1777 } params; 1778 }; 1779 1780 struct be_set_eqd { 1781 uint32_t eq_id; 1782 uint32_t phase; 1783 uint32_t dm; 1784 }; 1785 1786 /* [41] OPCODE_COMMON_MODIFY_EQ_DELAY */ 1787 struct mbx_modify_common_eq_delay { 1788 struct mbx_hdr hdr; 1789 union { 1790 struct { 1791 uint32_t num_eq; 1792 struct { 1793 uint32_t eq_id; 1794 uint32_t phase; 1795 uint32_t dm; 1796 } delay[8]; 1797 } req; 1798 1799 struct { 1800 uint32_t rsvd0; 1801 } rsp; 1802 } params; 1803 }; 1804 1805 /* [32] OPCODE_COMMON_GET_CNTL_ATTRIBUTES */ 1806 1807 struct mgmt_hba_attr { 1808 int8_t flashrom_ver_str[32]; 1809 int8_t manufac_name[32]; 1810 uint32_t supp_modes; 1811 int8_t seeprom_ver_lo; 1812 int8_t seeprom_ver_hi; 1813 int8_t rsvd0[2]; 1814 uint32_t ioctl_data_struct_ver; 1815 uint32_t ep_fw_data_struct_ver; 1816 uint8_t ncsi_ver_str[12]; 1817 uint32_t def_ext_to; 1818 int8_t cntl_mod_num[32]; 1819 int8_t cntl_desc[64]; 1820 int8_t cntl_ser_num[32]; 1821 int8_t ip_ver_str[32]; 1822 int8_t fw_ver_str[32]; 1823 int8_t bios_ver_str[32]; 1824 int8_t redboot_ver_str[32]; 1825 int8_t drv_ver_str[32]; 1826 int8_t fw_on_flash_ver_str[32]; 1827 uint32_t funcs_supp; 1828 uint16_t max_cdblen; 1829 uint8_t asic_rev; 1830 uint8_t gen_guid[16]; 1831 uint8_t hba_port_count; 1832 uint16_t default_link_down_timeout; 1833 uint8_t iscsi_ver_min_max; 1834 uint8_t multifunc_dev; 1835 uint8_t cache_valid; 1836 uint8_t hba_status; 1837 uint8_t max_domains_supp; 1838 uint8_t phy_port; 1839 uint32_t fw_post_status; 1840 uint32_t hba_mtu[8]; 1841 uint8_t iSCSI_feat; 1842 uint8_t asic_gen; 1843 uint8_t future_u8[2]; 1844 uint32_t future_u32[3]; 1845 }; 1846 1847 struct mgmt_cntl_attr { 1848 struct mgmt_hba_attr hba_attr; 1849 uint16_t pci_vendor_id; 1850 uint16_t pci_device_id; 1851 uint16_t pci_sub_vendor_id; 1852 uint16_t pci_sub_system_id; 1853 uint8_t pci_bus_num; 1854 uint8_t pci_dev_num; 1855 uint8_t pci_func_num; 1856 uint8_t interface_type; 1857 uint64_t unique_id; 1858 uint8_t netfilters; 1859 uint8_t rsvd0[3]; 1860 uint32_t future_u32[4]; 1861 }; 1862 1863 struct mbx_common_get_cntl_attr { 1864 struct mbx_hdr hdr; 1865 union { 1866 struct { 1867 uint32_t rsvd0; 1868 } req; 1869 struct { 1870 struct mgmt_cntl_attr cntl_attr_info; 1871 } rsp; 1872 } params; 1873 }; 1874 1875 /* [59] OPCODE_ADD_COMMON_IFACE_MAC */ 1876 struct mbx_add_common_iface_mac { 1877 struct mbx_hdr hdr; 1878 union { 1879 struct { 1880 uint32_t if_id; 1881 uint8_t mac_address[6]; 1882 uint8_t rsvd0[2]; 1883 } req; 1884 struct { 1885 uint32_t pmac_id; 1886 } rsp; 1887 } params; 1888 }; 1889 1890 /* [60] OPCODE_DEL_COMMON_IFACE_MAC */ 1891 struct mbx_del_common_iface_mac { 1892 struct mbx_hdr hdr; 1893 union { 1894 struct { 1895 uint32_t if_id; 1896 uint32_t pmac_id; 1897 } req; 1898 struct { 1899 uint32_t rsvd0; 1900 } rsp; 1901 } params; 1902 }; 1903 1904 /* [8] OPCODE_QUERY_COMMON_MAX_MBX_BUFFER_SIZE */ 1905 struct mbx_query_common_max_mbx_buffer_size { 1906 struct mbx_hdr hdr; 1907 struct { 1908 uint32_t max_ioctl_bufsz; 1909 } rsp; 1910 }; 1911 1912 /* [61] OPCODE_COMMON_FUNCTION_RESET */ 1913 struct ioctl_common_function_reset { 1914 struct mbx_hdr hdr; 1915 }; 1916 1917 /* [73] OPCODE_COMMON_READ_TRANSRECEIVER_DATA */ 1918 struct mbx_read_common_transrecv_data { 1919 struct mbx_hdr hdr; 1920 union { 1921 struct { 1922 uint32_t page_num; 1923 uint32_t port; 1924 } req; 1925 struct { 1926 uint32_t page_num; 1927 uint32_t port; 1928 uint32_t page_data[32]; 1929 } rsp; 1930 } params; 1931 1932 }; 1933 1934 /* [80] OPCODE_COMMON_FUNCTION_LINK_CONFIG */ 1935 struct mbx_common_func_link_cfg { 1936 struct mbx_hdr hdr; 1937 union { 1938 struct { 1939 uint32_t enable; 1940 } req; 1941 struct { 1942 uint32_t rsvd0; 1943 } rsp; 1944 } params; 1945 }; 1946 1947 /* [103] OPCODE_COMMON_SET_FUNCTIONAL_CAPS */ 1948 #define CAP_SW_TIMESTAMPS 2 1949 #define CAP_BE3_NATIVE_ERX_API 4 1950 1951 struct mbx_common_set_function_cap { 1952 struct mbx_hdr hdr; 1953 union { 1954 struct { 1955 uint32_t valid_capability_flags; 1956 uint32_t capability_flags; 1957 uint8_t sbz[212]; 1958 } req; 1959 struct { 1960 uint32_t valid_capability_flags; 1961 uint32_t capability_flags; 1962 uint8_t sbz[212]; 1963 } rsp; 1964 } params; 1965 }; 1966 struct mbx_lowlevel_test_loopback_mode { 1967 struct mbx_hdr hdr; 1968 union { 1969 struct { 1970 uint32_t loopback_type; 1971 uint32_t num_pkts; 1972 uint64_t pattern; 1973 uint32_t src_port; 1974 uint32_t dest_port; 1975 uint32_t pkt_size; 1976 }req; 1977 struct { 1978 uint32_t status; 1979 uint32_t num_txfer; 1980 uint32_t num_rx; 1981 uint32_t miscomp_off; 1982 uint32_t ticks_compl; 1983 }rsp; 1984 } params; 1985 }; 1986 1987 struct mbx_lowlevel_set_loopback_mode { 1988 struct mbx_hdr hdr; 1989 union { 1990 struct { 1991 uint8_t src_port; 1992 uint8_t dest_port; 1993 uint8_t loopback_type; 1994 uint8_t loopback_state; 1995 } req; 1996 struct { 1997 uint8_t rsvd0[4]; 1998 } rsp; 1999 } params; 2000 }; 2001 2002 struct flash_file_hdr { 2003 uint8_t sign[52]; 2004 uint8_t ufi_version[4]; 2005 uint32_t file_len; 2006 uint32_t cksum; 2007 uint32_t antidote; 2008 uint32_t num_imgs; 2009 uint8_t build[24]; 2010 uint8_t rsvd[32]; 2011 }; 2012 2013 struct image_hdr { 2014 uint32_t imageid; 2015 uint32_t imageoffset; 2016 uint32_t imagelength; 2017 uint32_t image_checksum; 2018 uint8_t image_version[32]; 2019 }; 2020 2021 struct flash_section_hdr { 2022 uint32_t format_rev; 2023 uint32_t cksum; 2024 uint32_t antidote; 2025 uint32_t num_images; 2026 uint8_t id_string[128]; 2027 uint32_t rsvd[4]; 2028 }; 2029 2030 struct flash_section_entry { 2031 uint32_t type; 2032 uint32_t offset; 2033 uint32_t pad_size; 2034 uint32_t image_size; 2035 uint32_t cksum; 2036 uint32_t entry_point; 2037 uint32_t rsvd0; 2038 uint32_t rsvd1; 2039 uint8_t ver_data[32]; 2040 }; 2041 2042 struct flash_sec_info { 2043 uint8_t cookie[32]; 2044 struct flash_section_hdr fsec_hdr; 2045 struct flash_section_entry fsec_entry[32]; 2046 }; 2047 2048 2049 enum LOWLEVEL_SUBSYSTEM_OPCODES { 2050 /* Opcodes used for lowlevel functions common to many subystems. 2051 * Some of these opcodes are used for diagnostic functions only. 2052 * These opcodes use the MBX_SUBSYSTEM_LOWLEVEL subsystem code. 2053 */ 2054 OPCODE_LOWLEVEL_TEST_LOOPBACK = 18, 2055 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE = 19, 2056 OPCODE_LOWLEVEL_GET_LOOPBACK_MODE = 20 2057 }; 2058 2059 enum LLDP_SUBSYSTEM_OPCODES { 2060 /* Opcodes used for LLDP susbsytem for configuring the LLDP state machines. */ 2061 OPCODE_LLDP_GET_CFG = 1, 2062 OPCODE_LLDP_SET_CFG = 2, 2063 OPCODE_LLDP_GET_STATS = 3 2064 }; 2065 2066 enum DCBX_SUBSYSTEM_OPCODES { 2067 /* Opcodes used for DCBX. */ 2068 OPCODE_DCBX_GET_CFG = 1, 2069 OPCODE_DCBX_SET_CFG = 2, 2070 OPCODE_DCBX_GET_MIB_INFO = 3, 2071 OPCODE_DCBX_GET_DCBX_MODE = 4, 2072 OPCODE_DCBX_SET_MODE = 5 2073 }; 2074 2075 enum DMTF_SUBSYSTEM_OPCODES { 2076 /* Opcodes used for DCBX subsystem. */ 2077 OPCODE_DMTF_EXEC_CLP_CMD = 1 2078 }; 2079 2080 enum DIAG_SUBSYSTEM_OPCODES { 2081 /* Opcodes used for diag functions common to many subsystems. */ 2082 OPCODE_DIAG_RUN_DMA_TEST = 1, 2083 OPCODE_DIAG_RUN_MDIO_TEST = 2, 2084 OPCODE_DIAG_RUN_NLB_TEST = 3, 2085 OPCODE_DIAG_RUN_ARM_TIMER_TEST = 4, 2086 OPCODE_DIAG_GET_MAC = 5 2087 }; 2088 2089 enum VENDOR_SUBSYSTEM_OPCODES { 2090 /* Opcodes used for Vendor subsystem. */ 2091 OPCODE_VENDOR_SLI = 1 2092 }; 2093 2094 /* Management Status Codes */ 2095 enum MGMT_STATUS_SUCCESS { 2096 MGMT_SUCCESS = 0, 2097 MGMT_FAILED = 1, 2098 MGMT_ILLEGAL_REQUEST = 2, 2099 MGMT_ILLEGAL_FIELD = 3, 2100 MGMT_INSUFFICIENT_BUFFER = 4, 2101 MGMT_UNAUTHORIZED_REQUEST = 5, 2102 MGMT_INVALID_ISNS_ADDRESS = 10, 2103 MGMT_INVALID_IPADDR = 11, 2104 MGMT_INVALID_GATEWAY = 12, 2105 MGMT_INVALID_SUBNETMASK = 13, 2106 MGMT_INVALID_TARGET_IPADDR = 16, 2107 MGMT_TGTTBL_FULL = 20, 2108 MGMT_FLASHROM_SAVE_FAILED = 23, 2109 MGMT_IOCTLHANDLE_ALLOC_FAILED = 27, 2110 MGMT_INVALID_SESSION = 31, 2111 MGMT_INVALID_CONNECTION = 32, 2112 MGMT_BTL_PATH_EXCEEDS_OSM_LIMIT = 33, 2113 MGMT_BTL_TGTID_EXCEEDS_OSM_LIMIT = 34, 2114 MGMT_BTL_PATH_TGTID_OCCUPIED = 35, 2115 MGMT_BTL_NO_FREE_SLOT_PATH = 36, 2116 MGMT_BTL_NO_FREE_SLOT_TGTID = 37, 2117 MGMT_POLL_IOCTL_TIMEOUT = 40, 2118 MGMT_ERROR_ACITISCSI = 41, 2119 MGMT_BUFFER_SIZE_EXCEED_OSM_OR_OS_LIMIT = 43, 2120 MGMT_REBOOT_REQUIRED = 44, 2121 MGMT_INSUFFICIENT_TIMEOUT = 45, 2122 MGMT_IPADDR_NOT_SET = 46, 2123 MGMT_IPADDR_DUP_DETECTED = 47, 2124 MGMT_CANT_REMOVE_LAST_CONNECTION = 48, 2125 MGMT_TARGET_BUSY = 49, 2126 MGMT_TGT_ERR_LISTEN_SOCKET = 50, 2127 MGMT_TGT_ERR_BIND_SOCKET = 51, 2128 MGMT_TGT_ERR_NO_SOCKET = 52, 2129 MGMT_TGT_ERR_ISNS_COMM_FAILED = 55, 2130 MGMT_CANNOT_DELETE_BOOT_TARGET = 56, 2131 MGMT_TGT_PORTAL_MODE_IN_LISTEN = 57, 2132 MGMT_FCF_IN_USE = 58 , 2133 MGMT_NO_CQE = 59, 2134 MGMT_TARGET_NOT_FOUND = 65, 2135 MGMT_NOT_SUPPORTED = 66, 2136 MGMT_NO_FCF_RECORDS = 67, 2137 MGMT_FEATURE_NOT_SUPPORTED = 68, 2138 MGMT_VPD_FUNCTION_OUT_OF_RANGE = 69, 2139 MGMT_VPD_FUNCTION_TYPE_INCORRECT = 70, 2140 MGMT_INVALID_NON_EMBEDDED_WRB = 71, 2141 MGMT_OOR = 100, 2142 MGMT_INVALID_PD = 101, 2143 MGMT_STATUS_PD_INUSE = 102, 2144 MGMT_INVALID_CQ = 103, 2145 MGMT_INVALID_QP = 104, 2146 MGMT_INVALID_STAG = 105, 2147 MGMT_ORD_EXCEEDS = 106, 2148 MGMT_IRD_EXCEEDS = 107, 2149 MGMT_SENDQ_WQE_EXCEEDS = 108, 2150 MGMT_RECVQ_RQE_EXCEEDS = 109, 2151 MGMT_SGE_SEND_EXCEEDS = 110, 2152 MGMT_SGE_WRITE_EXCEEDS = 111, 2153 MGMT_SGE_RECV_EXCEEDS = 112, 2154 MGMT_INVALID_STATE_CHANGE = 113, 2155 MGMT_MW_BOUND = 114, 2156 MGMT_INVALID_VA = 115, 2157 MGMT_INVALID_LENGTH = 116, 2158 MGMT_INVALID_FBO = 117, 2159 MGMT_INVALID_ACC_RIGHTS = 118, 2160 MGMT_INVALID_PBE_SIZE = 119, 2161 MGMT_INVALID_PBL_ENTRY = 120, 2162 MGMT_INVALID_PBL_OFFSET = 121, 2163 MGMT_ADDR_NON_EXIST = 122, 2164 MGMT_INVALID_VLANID = 123, 2165 MGMT_INVALID_MTU = 124, 2166 MGMT_INVALID_BACKLOG = 125, 2167 MGMT_CONNECTION_INPROGRESS = 126, 2168 MGMT_INVALID_RQE_SIZE = 127, 2169 MGMT_INVALID_RQE_ENTRY = 128 2170 }; 2171 2172 /* Additional Management Status Codes */ 2173 enum MGMT_ADDI_STATUS { 2174 MGMT_ADDI_NO_STATUS = 0, 2175 MGMT_ADDI_INVALID_IPTYPE = 1, 2176 MGMT_ADDI_TARGET_HANDLE_NOT_FOUND = 9, 2177 MGMT_ADDI_SESSION_HANDLE_NOT_FOUND = 10, 2178 MGMT_ADDI_CONNECTION_HANDLE_NOT_FOUND = 11, 2179 MGMT_ADDI_ACTIVE_SESSIONS_PRESENT = 16, 2180 MGMT_ADDI_SESSION_ALREADY_OPENED = 17, 2181 MGMT_ADDI_SESSION_ALREADY_CLOSED = 18, 2182 MGMT_ADDI_DEST_HOST_UNREACHABLE = 19, 2183 MGMT_ADDI_LOGIN_IN_PROGRESS = 20, 2184 MGMT_ADDI_TCP_CONNECT_FAILED = 21, 2185 MGMT_ADDI_INSUFFICIENT_RESOURCES = 22, 2186 MGMT_ADDI_LINK_DOWN = 23, 2187 MGMT_ADDI_DHCP_ERROR = 24, 2188 MGMT_ADDI_CONNECTION_OFFLOADED = 25, 2189 MGMT_ADDI_CONNECTION_NOT_OFFLOADED = 26, 2190 MGMT_ADDI_CONNECTION_UPLOAD_IN_PROGRESS = 27, 2191 MGMT_ADDI_REQUEST_REJECTED = 28, 2192 MGMT_ADDI_INVALID_SUBSYSTEM = 29, 2193 MGMT_ADDI_INVALID_OPCODE = 30, 2194 MGMT_ADDI_INVALID_MAXCONNECTION_PARAM = 31, 2195 MGMT_ADDI_INVALID_KEY = 32, 2196 MGMT_ADDI_INVALID_DOMAIN = 35, 2197 MGMT_ADDI_LOGIN_INITIATOR_ERROR = 43, 2198 MGMT_ADDI_LOGIN_AUTHENTICATION_ERROR = 44, 2199 MGMT_ADDI_LOGIN_AUTHORIZATION_ERROR = 45, 2200 MGMT_ADDI_LOGIN_NOT_FOUND = 46, 2201 MGMT_ADDI_LOGIN_TARGET_REMOVED = 47, 2202 MGMT_ADDI_LOGIN_UNSUPPORTED_VERSION = 48, 2203 MGMT_ADDI_LOGIN_TOO_MANY_CONNECTIONS = 49, 2204 MGMT_ADDI_LOGIN_MISSING_PARAMETER = 50, 2205 MGMT_ADDI_LOGIN_NO_SESSION_SPANNING = 51, 2206 MGMT_ADDI_LOGIN_SESSION_TYPE_NOT_SUPPORTED = 52, 2207 MGMT_ADDI_LOGIN_SESSION_DOES_NOT_EXIST = 53, 2208 MGMT_ADDI_LOGIN_INVALID_DURING_LOGIN = 54, 2209 MGMT_ADDI_LOGIN_TARGET_ERROR = 55, 2210 MGMT_ADDI_LOGIN_SERVICE_UNAVAILABLE = 56, 2211 MGMT_ADDI_LOGIN_OUT_OF_RESOURCES = 57, 2212 MGMT_ADDI_SAME_CHAP_SECRET = 58, 2213 MGMT_ADDI_INVALID_SECRET_LENGTH = 59, 2214 MGMT_ADDI_DUPLICATE_ENTRY = 60, 2215 MGMT_ADDI_SETTINGS_MODIFIED_REBOOT_REQD = 63, 2216 MGMT_ADDI_INVALID_EXTENDED_TIMEOUT = 64, 2217 MGMT_ADDI_INVALID_INTERFACE_HANDLE = 65, 2218 MGMT_ADDI_ERR_VLAN_ON_DEF_INTERFACE = 66, 2219 MGMT_ADDI_INTERFACE_DOES_NOT_EXIST = 67, 2220 MGMT_ADDI_INTERFACE_ALREADY_EXISTS = 68, 2221 MGMT_ADDI_INVALID_VLAN_RANGE = 69, 2222 MGMT_ADDI_ERR_SET_VLAN = 70, 2223 MGMT_ADDI_ERR_DEL_VLAN = 71, 2224 MGMT_ADDI_CANNOT_DEL_DEF_INTERFACE = 72, 2225 MGMT_ADDI_DHCP_REQ_ALREADY_PENDING = 73, 2226 MGMT_ADDI_TOO_MANY_INTERFACES = 74, 2227 MGMT_ADDI_INVALID_REQUEST = 75 2228 }; 2229 2230 enum NIC_SUBSYSTEM_OPCODES { 2231 /** 2232 * @brief NIC Subsystem Opcodes (see Network SLI-4 manual >= Rev4, v21-2) 2233 * These opcodes are used for configuring the Ethernet interfaces. 2234 * These opcodes all use the MBX_SUBSYSTEM_NIC subsystem code. 2235 */ 2236 NIC_CONFIG_RSS = 1, 2237 NIC_CONFIG_ACPI = 2, 2238 NIC_CONFIG_PROMISCUOUS = 3, 2239 NIC_GET_STATS = 4, 2240 NIC_CREATE_WQ = 7, 2241 NIC_CREATE_RQ = 8, 2242 NIC_DELETE_WQ = 9, 2243 NIC_DELETE_RQ = 10, 2244 NIC_CONFIG_ACPI_WOL_MAGIC = 12, 2245 NIC_GET_NETWORK_STATS = 13, 2246 NIC_CREATE_HDS_RQ = 16, 2247 NIC_DELETE_HDS_RQ = 17, 2248 NIC_GET_PPORT_STATS = 18, 2249 NIC_GET_VPORT_STATS = 19, 2250 NIC_GET_QUEUE_STATS = 20 2251 }; 2252 2253 /* Hash option flags for RSS enable */ 2254 enum RSS_ENABLE_FLAGS { 2255 RSS_ENABLE_NONE = 0x0, /* (No RSS) */ 2256 RSS_ENABLE_IPV4 = 0x1, /* (IPV4 HASH enabled ) */ 2257 RSS_ENABLE_TCP_IPV4 = 0x2, /* (TCP IPV4 Hash enabled) */ 2258 RSS_ENABLE_IPV6 = 0x4, /* (IPV6 HASH enabled) */ 2259 RSS_ENABLE_TCP_IPV6 = 0x8, /* (TCP IPV6 HASH */ 2260 RSS_ENABLE_UDP_IPV4 = 0x10, /* UDP IPV4 HASH */ 2261 RSS_ENABLE_UDP_IPV6 = 0x20 /* UDP IPV6 HASH */ 2262 }; 2263 #define RSS_ENABLE (RSS_ENABLE_IPV4 | RSS_ENABLE_TCP_IPV4) 2264 #define RSS_DISABLE RSS_ENABLE_NONE 2265 2266 /* NIC header WQE */ 2267 struct oce_nic_hdr_wqe { 2268 union { 2269 struct { 2270 #ifdef _BIG_ENDIAN 2271 /* dw0 */ 2272 uint32_t rsvd0; 2273 2274 /* dw1 */ 2275 uint32_t last_seg_udp_len:14; 2276 uint32_t rsvd1:18; 2277 2278 /* dw2 */ 2279 uint32_t lso_mss:14; 2280 uint32_t num_wqe:5; 2281 uint32_t rsvd4:2; 2282 uint32_t vlan:1; 2283 uint32_t lso:1; 2284 uint32_t tcpcs:1; 2285 uint32_t udpcs:1; 2286 uint32_t ipcs:1; 2287 uint32_t rsvd3:1; 2288 uint32_t rsvd2:1; 2289 uint32_t forward:1; 2290 uint32_t crc:1; 2291 uint32_t event:1; 2292 uint32_t complete:1; 2293 2294 /* dw3 */ 2295 uint32_t vlan_tag:16; 2296 uint32_t total_length:16; 2297 #else 2298 /* dw0 */ 2299 uint32_t rsvd0; 2300 2301 /* dw1 */ 2302 uint32_t rsvd1:18; 2303 uint32_t last_seg_udp_len:14; 2304 2305 /* dw2 */ 2306 uint32_t complete:1; 2307 uint32_t event:1; 2308 uint32_t crc:1; 2309 uint32_t forward:1; 2310 uint32_t rsvd2:1; 2311 uint32_t rsvd3:1; 2312 uint32_t ipcs:1; 2313 uint32_t udpcs:1; 2314 uint32_t tcpcs:1; 2315 uint32_t lso:1; 2316 uint32_t vlan:1; 2317 uint32_t rsvd4:2; 2318 uint32_t num_wqe:5; 2319 uint32_t lso_mss:14; 2320 2321 /* dw3 */ 2322 uint32_t total_length:16; 2323 uint32_t vlan_tag:16; 2324 #endif 2325 } s; 2326 uint32_t dw[4]; 2327 } u0; 2328 }; 2329 2330 /* NIC fragment WQE */ 2331 struct oce_nic_frag_wqe { 2332 union { 2333 struct { 2334 /* dw0 */ 2335 uint32_t frag_pa_hi; 2336 /* dw1 */ 2337 uint32_t frag_pa_lo; 2338 /* dw2 */ 2339 uint32_t rsvd0; 2340 uint32_t frag_len; 2341 } s; 2342 uint32_t dw[4]; 2343 } u0; 2344 }; 2345 2346 /* Ethernet Tx Completion Descriptor */ 2347 struct oce_nic_tx_cqe { 2348 union { 2349 struct { 2350 #ifdef _BIG_ENDIAN 2351 /* dw 0 */ 2352 uint32_t status:4; 2353 uint32_t rsvd0:8; 2354 uint32_t port:2; 2355 uint32_t ct:2; 2356 uint32_t wqe_index:16; 2357 2358 /* dw 1 */ 2359 uint32_t rsvd1:5; 2360 uint32_t cast_enc:2; 2361 uint32_t lso:1; 2362 uint32_t nwh_bytes:8; 2363 uint32_t user_bytes:16; 2364 2365 /* dw 2 */ 2366 uint32_t rsvd2; 2367 2368 /* dw 3 */ 2369 uint32_t valid:1; 2370 uint32_t rsvd3:4; 2371 uint32_t wq_id:11; 2372 uint32_t num_pkts:16; 2373 #else 2374 /* dw 0 */ 2375 uint32_t wqe_index:16; 2376 uint32_t ct:2; 2377 uint32_t port:2; 2378 uint32_t rsvd0:8; 2379 uint32_t status:4; 2380 2381 /* dw 1 */ 2382 uint32_t user_bytes:16; 2383 uint32_t nwh_bytes:8; 2384 uint32_t lso:1; 2385 uint32_t cast_enc:2; 2386 uint32_t rsvd1:5; 2387 /* dw 2 */ 2388 uint32_t rsvd2; 2389 2390 /* dw 3 */ 2391 uint32_t num_pkts:16; 2392 uint32_t wq_id:11; 2393 uint32_t rsvd3:4; 2394 uint32_t valid:1; 2395 #endif 2396 } s; 2397 uint32_t dw[4]; 2398 } u0; 2399 }; 2400 #define WQ_CQE_VALID(_cqe) (_cqe->u0.dw[3]) 2401 #define WQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[3] = 0) 2402 2403 /* Receive Queue Entry (RQE) */ 2404 struct oce_nic_rqe { 2405 union { 2406 struct { 2407 uint32_t frag_pa_hi; 2408 uint32_t frag_pa_lo; 2409 } s; 2410 uint32_t dw[2]; 2411 } u0; 2412 }; 2413 2414 /* NIC Receive CQE */ 2415 struct oce_nic_rx_cqe { 2416 union { 2417 struct { 2418 #ifdef _BIG_ENDIAN 2419 /* dw 0 */ 2420 uint32_t ip_options:1; 2421 uint32_t port:1; 2422 uint32_t pkt_size:14; 2423 uint32_t vlan_tag:16; 2424 2425 /* dw 1 */ 2426 uint32_t num_fragments:3; 2427 uint32_t switched:1; 2428 uint32_t ct:2; 2429 uint32_t frag_index:10; 2430 uint32_t rsvd0:1; 2431 uint32_t vlan_tag_present:1; 2432 uint32_t mac_dst:6; 2433 uint32_t ip_ver:1; 2434 uint32_t l4_cksum_pass:1; 2435 uint32_t ip_cksum_pass:1; 2436 uint32_t udpframe:1; 2437 uint32_t tcpframe:1; 2438 uint32_t ipframe:1; 2439 uint32_t rss_hp:1; 2440 uint32_t error:1; 2441 2442 /* dw 2 */ 2443 uint32_t valid:1; 2444 uint32_t hds_type:2; 2445 uint32_t lro_pkt:1; 2446 uint32_t rsvd4:1; 2447 uint32_t hds_hdr_size:12; 2448 uint32_t hds_hdr_frag_index:10; 2449 uint32_t rss_bank:1; 2450 uint32_t qnq:1; 2451 uint32_t pkt_type:2; 2452 uint32_t rss_flush:1; 2453 2454 /* dw 3 */ 2455 uint32_t rss_hash_value; 2456 #else 2457 /* dw 0 */ 2458 uint32_t vlan_tag:16; 2459 uint32_t pkt_size:14; 2460 uint32_t port:1; 2461 uint32_t ip_options:1; 2462 /* dw 1 */ 2463 uint32_t error:1; 2464 uint32_t rss_hp:1; 2465 uint32_t ipframe:1; 2466 uint32_t tcpframe:1; 2467 uint32_t udpframe:1; 2468 uint32_t ip_cksum_pass:1; 2469 uint32_t l4_cksum_pass:1; 2470 uint32_t ip_ver:1; 2471 uint32_t mac_dst:6; 2472 uint32_t vlan_tag_present:1; 2473 uint32_t rsvd0:1; 2474 uint32_t frag_index:10; 2475 uint32_t ct:2; 2476 uint32_t switched:1; 2477 uint32_t num_fragments:3; 2478 2479 /* dw 2 */ 2480 uint32_t rss_flush:1; 2481 uint32_t pkt_type:2; 2482 uint32_t qnq:1; 2483 uint32_t rss_bank:1; 2484 uint32_t hds_hdr_frag_index:10; 2485 uint32_t hds_hdr_size:12; 2486 uint32_t rsvd4:1; 2487 uint32_t lro_pkt:1; 2488 uint32_t hds_type:2; 2489 uint32_t valid:1; 2490 /* dw 3 */ 2491 uint32_t rss_hash_value; 2492 #endif 2493 } s; 2494 uint32_t dw[4]; 2495 } u0; 2496 }; 2497 /* NIC Receive CQE_v1 */ 2498 struct oce_nic_rx_cqe_v1 { 2499 union { 2500 struct { 2501 #ifdef _BIG_ENDIAN 2502 /* dw 0 */ 2503 uint32_t ip_options:1; 2504 uint32_t vlan_tag_present:1; 2505 uint32_t pkt_size:14; 2506 uint32_t vlan_tag:16; 2507 2508 /* dw 1 */ 2509 uint32_t num_fragments:3; 2510 uint32_t switched:1; 2511 uint32_t ct:2; 2512 uint32_t frag_index:10; 2513 uint32_t rsvd0:1; 2514 uint32_t mac_dst:7; 2515 uint32_t ip_ver:1; 2516 uint32_t l4_cksum_pass:1; 2517 uint32_t ip_cksum_pass:1; 2518 uint32_t udpframe:1; 2519 uint32_t tcpframe:1; 2520 uint32_t ipframe:1; 2521 uint32_t rss_hp:1; 2522 uint32_t error:1; 2523 2524 /* dw 2 */ 2525 uint32_t valid:1; 2526 uint32_t rsvd4:13; 2527 uint32_t hds_hdr_size: 2528 uint32_t hds_hdr_frag_index:8; 2529 uint32_t vlantag:1; 2530 uint32_t port:2; 2531 uint32_t rss_bank:1; 2532 uint32_t qnq:1; 2533 uint32_t pkt_type:2; 2534 uint32_t rss_flush:1; 2535 2536 /* dw 3 */ 2537 uint32_t rss_hash_value; 2538 #else 2539 /* dw 0 */ 2540 uint32_t vlan_tag:16; 2541 uint32_t pkt_size:14; 2542 uint32_t vlan_tag_present:1; 2543 uint32_t ip_options:1; 2544 /* dw 1 */ 2545 uint32_t error:1; 2546 uint32_t rss_hp:1; 2547 uint32_t ipframe:1; 2548 uint32_t tcpframe:1; 2549 uint32_t udpframe:1; 2550 uint32_t ip_cksum_pass:1; 2551 uint32_t l4_cksum_pass:1; 2552 uint32_t ip_ver:1; 2553 uint32_t mac_dst:7; 2554 uint32_t rsvd0:1; 2555 uint32_t frag_index:10; 2556 uint32_t ct:2; 2557 uint32_t switched:1; 2558 uint32_t num_fragments:3; 2559 2560 /* dw 2 */ 2561 uint32_t rss_flush:1; 2562 uint32_t pkt_type:2; 2563 uint32_t qnq:1; 2564 uint32_t rss_bank:1; 2565 uint32_t port:2; 2566 uint32_t vlantag:1; 2567 uint32_t hds_hdr_frag_index:8; 2568 uint32_t hds_hdr_size:2; 2569 uint32_t rsvd4:13; 2570 uint32_t valid:1; 2571 /* dw 3 */ 2572 uint32_t rss_hash_value; 2573 #endif 2574 } s; 2575 uint32_t dw[4]; 2576 } u0; 2577 }; 2578 2579 #define RQ_CQE_VALID_MASK 0x80 2580 #define RQ_CQE_VALID(_cqe) (_cqe->u0.dw[2]) 2581 #define RQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[2] = 0) 2582 2583 struct mbx_config_nic_promiscuous { 2584 struct mbx_hdr hdr; 2585 union { 2586 struct { 2587 #ifdef _BIG_ENDIAN 2588 uint16_t rsvd0; 2589 uint8_t port1_promisc; 2590 uint8_t port0_promisc; 2591 #else 2592 uint8_t port0_promisc; 2593 uint8_t port1_promisc; 2594 uint16_t rsvd0; 2595 #endif 2596 } req; 2597 2598 struct { 2599 uint32_t rsvd0; 2600 } rsp; 2601 } params; 2602 }; 2603 2604 typedef union oce_wq_ctx_u { 2605 uint32_t dw[17]; 2606 struct { 2607 #ifdef _BIG_ENDIAN 2608 /* dw4 */ 2609 uint32_t dw4rsvd2:8; 2610 uint32_t nic_wq_type:8; 2611 uint32_t dw4rsvd1:8; 2612 uint32_t num_pages:8; 2613 /* dw5 */ 2614 uint32_t dw5rsvd2:12; 2615 uint32_t wq_size:4; 2616 uint32_t dw5rsvd1:16; 2617 /* dw6 */ 2618 uint32_t valid:1; 2619 uint32_t dw6rsvd1:31; 2620 /* dw7 */ 2621 uint32_t dw7rsvd1:16; 2622 uint32_t cq_id:16; 2623 #else 2624 /* dw4 */ 2625 uint32_t num_pages:8; 2626 #if 0 2627 uint32_t dw4rsvd1:8; 2628 #else 2629 /* PSP: this workaround is not documented: fill 0x01 for ulp_mask */ 2630 uint32_t ulp_mask:8; 2631 #endif 2632 uint32_t nic_wq_type:8; 2633 uint32_t dw4rsvd2:8; 2634 /* dw5 */ 2635 uint32_t dw5rsvd1:16; 2636 uint32_t wq_size:4; 2637 uint32_t dw5rsvd2:12; 2638 /* dw6 */ 2639 uint32_t dw6rsvd1:31; 2640 uint32_t valid:1; 2641 /* dw7 */ 2642 uint32_t cq_id:16; 2643 uint32_t dw7rsvd1:16; 2644 #endif 2645 /* dw8 - dw20 */ 2646 uint32_t dw8_20rsvd1[13]; 2647 } v0; 2648 struct { 2649 #ifdef _BIG_ENDIAN 2650 /* dw4 */ 2651 uint32_t dw4rsvd2:8; 2652 uint32_t nic_wq_type:8; 2653 uint32_t dw4rsvd1:8; 2654 uint32_t num_pages:8; 2655 /* dw5 */ 2656 uint32_t dw5rsvd2:12; 2657 uint32_t wq_size:4; 2658 uint32_t iface_id:16; 2659 /* dw6 */ 2660 uint32_t valid:1; 2661 uint32_t dw6rsvd1:31; 2662 /* dw7 */ 2663 uint32_t dw7rsvd1:16; 2664 uint32_t cq_id:16; 2665 #else 2666 /* dw4 */ 2667 uint32_t num_pages:8; 2668 uint32_t dw4rsvd1:8; 2669 uint32_t nic_wq_type:8; 2670 uint32_t dw4rsvd2:8; 2671 /* dw5 */ 2672 uint32_t iface_id:16; 2673 uint32_t wq_size:4; 2674 uint32_t dw5rsvd2:12; 2675 /* dw6 */ 2676 uint32_t dw6rsvd1:31; 2677 uint32_t valid:1; 2678 /* dw7 */ 2679 uint32_t cq_id:16; 2680 uint32_t dw7rsvd1:16; 2681 #endif 2682 /* dw8 - dw20 */ 2683 uint32_t dw8_20rsvd1[13]; 2684 } v1; 2685 } oce_wq_ctx_t; 2686 2687 /** 2688 * @brief [07] NIC_CREATE_WQ 2689 * @note 2690 * Lancer requires an InterfaceID to be specified with every WQ. This 2691 * is the basis for NIC IOV where the Interface maps to a vPort and maps 2692 * to both Tx and Rx sides. 2693 */ 2694 #define OCE_WQ_TYPE_FORWARDING 0x1 /* wq forwards pkts to TOE */ 2695 #define OCE_WQ_TYPE_STANDARD 0x2 /* wq sends network pkts */ 2696 struct mbx_create_nic_wq { 2697 struct mbx_hdr hdr; 2698 union { 2699 struct { 2700 uint8_t num_pages; 2701 uint8_t ulp_num; 2702 uint16_t nic_wq_type; 2703 uint16_t if_id; 2704 uint8_t wq_size; 2705 uint8_t rsvd1; 2706 uint32_t rsvd2; 2707 uint16_t cq_id; 2708 uint16_t rsvd3; 2709 uint32_t rsvd4[13]; 2710 struct phys_addr pages[8]; 2711 2712 } req; 2713 2714 struct { 2715 uint16_t wq_id; 2716 uint16_t rid; 2717 uint32_t db_offset; 2718 uint8_t tc_id; 2719 uint8_t rsvd0[3]; 2720 } rsp; 2721 } params; 2722 }; 2723 2724 /* [09] NIC_DELETE_WQ */ 2725 struct mbx_delete_nic_wq { 2726 /* dw0 - dw3 */ 2727 struct mbx_hdr hdr; 2728 union { 2729 struct { 2730 #ifdef _BIG_ENDIAN 2731 /* dw4 */ 2732 uint16_t rsvd0; 2733 uint16_t wq_id; 2734 #else 2735 /* dw4 */ 2736 uint16_t wq_id; 2737 uint16_t rsvd0; 2738 #endif 2739 } req; 2740 struct { 2741 uint32_t rsvd0; 2742 } rsp; 2743 } params; 2744 }; 2745 2746 2747 2748 struct mbx_create_nic_rq { 2749 struct mbx_hdr hdr; 2750 union { 2751 struct { 2752 uint16_t cq_id; 2753 uint8_t frag_size; 2754 uint8_t num_pages; 2755 struct phys_addr pages[2]; 2756 uint32_t if_id; 2757 uint16_t max_frame_size; 2758 uint16_t page_size; 2759 uint32_t is_rss_queue; 2760 } req; 2761 2762 struct { 2763 uint16_t rq_id; 2764 uint8_t rss_cpuid; 2765 uint8_t rsvd0; 2766 } rsp; 2767 2768 } params; 2769 }; 2770 2771 2772 2773 /* [10] NIC_DELETE_RQ */ 2774 struct mbx_delete_nic_rq { 2775 /* dw0 - dw3 */ 2776 struct mbx_hdr hdr; 2777 union { 2778 struct { 2779 #ifdef _BIG_ENDIAN 2780 /* dw4 */ 2781 uint16_t bypass_flush; 2782 uint16_t rq_id; 2783 #else 2784 /* dw4 */ 2785 uint16_t rq_id; 2786 uint16_t bypass_flush; 2787 #endif 2788 } req; 2789 2790 struct { 2791 /* dw4 */ 2792 uint32_t rsvd0; 2793 } rsp; 2794 } params; 2795 }; 2796 2797 2798 2799 2800 struct oce_port_rxf_stats_v0 { 2801 uint32_t rx_bytes_lsd; /* dword 0*/ 2802 uint32_t rx_bytes_msd; /* dword 1*/ 2803 uint32_t rx_total_frames; /* dword 2*/ 2804 uint32_t rx_unicast_frames; /* dword 3*/ 2805 uint32_t rx_multicast_frames; /* dword 4*/ 2806 uint32_t rx_broadcast_frames; /* dword 5*/ 2807 uint32_t rx_crc_errors; /* dword 6*/ 2808 uint32_t rx_alignment_symbol_errors; /* dword 7*/ 2809 uint32_t rx_pause_frames; /* dword 8*/ 2810 uint32_t rx_control_frames; /* dword 9*/ 2811 uint32_t rx_in_range_errors; /* dword 10*/ 2812 uint32_t rx_out_range_errors; /* dword 11*/ 2813 uint32_t rx_frame_too_long; /* dword 12*/ 2814 uint32_t rx_address_match_errors; /* dword 13*/ 2815 uint32_t rx_vlan_mismatch; /* dword 14*/ 2816 uint32_t rx_dropped_too_small; /* dword 15*/ 2817 uint32_t rx_dropped_too_short; /* dword 16*/ 2818 uint32_t rx_dropped_header_too_small; /* dword 17*/ 2819 uint32_t rx_dropped_tcp_length; /* dword 18*/ 2820 uint32_t rx_dropped_runt; /* dword 19*/ 2821 uint32_t rx_64_byte_packets; /* dword 20*/ 2822 uint32_t rx_65_127_byte_packets; /* dword 21*/ 2823 uint32_t rx_128_256_byte_packets; /* dword 22*/ 2824 uint32_t rx_256_511_byte_packets; /* dword 23*/ 2825 uint32_t rx_512_1023_byte_packets; /* dword 24*/ 2826 uint32_t rx_1024_1518_byte_packets; /* dword 25*/ 2827 uint32_t rx_1519_2047_byte_packets; /* dword 26*/ 2828 uint32_t rx_2048_4095_byte_packets; /* dword 27*/ 2829 uint32_t rx_4096_8191_byte_packets; /* dword 28*/ 2830 uint32_t rx_8192_9216_byte_packets; /* dword 29*/ 2831 uint32_t rx_ip_checksum_errs; /* dword 30*/ 2832 uint32_t rx_tcp_checksum_errs; /* dword 31*/ 2833 uint32_t rx_udp_checksum_errs; /* dword 32*/ 2834 uint32_t rx_non_rss_packets; /* dword 33*/ 2835 uint32_t rx_ipv4_packets; /* dword 34*/ 2836 uint32_t rx_ipv6_packets; /* dword 35*/ 2837 uint32_t rx_ipv4_bytes_lsd; /* dword 36*/ 2838 uint32_t rx_ipv4_bytes_msd; /* dword 37*/ 2839 uint32_t rx_ipv6_bytes_lsd; /* dword 38*/ 2840 uint32_t rx_ipv6_bytes_msd; /* dword 39*/ 2841 uint32_t rx_chute1_packets; /* dword 40*/ 2842 uint32_t rx_chute2_packets; /* dword 41*/ 2843 uint32_t rx_chute3_packets; /* dword 42*/ 2844 uint32_t rx_management_packets; /* dword 43*/ 2845 uint32_t rx_switched_unicast_packets; /* dword 44*/ 2846 uint32_t rx_switched_multicast_packets; /* dword 45*/ 2847 uint32_t rx_switched_broadcast_packets; /* dword 46*/ 2848 uint32_t tx_bytes_lsd; /* dword 47*/ 2849 uint32_t tx_bytes_msd; /* dword 48*/ 2850 uint32_t tx_unicastframes; /* dword 49*/ 2851 uint32_t tx_multicastframes; /* dword 50*/ 2852 uint32_t tx_broadcastframes; /* dword 51*/ 2853 uint32_t tx_pauseframes; /* dword 52*/ 2854 uint32_t tx_controlframes; /* dword 53*/ 2855 uint32_t tx_64_byte_packets; /* dword 54*/ 2856 uint32_t tx_65_127_byte_packets; /* dword 55*/ 2857 uint32_t tx_128_256_byte_packets; /* dword 56*/ 2858 uint32_t tx_256_511_byte_packets; /* dword 57*/ 2859 uint32_t tx_512_1023_byte_packets; /* dword 58*/ 2860 uint32_t tx_1024_1518_byte_packets; /* dword 59*/ 2861 uint32_t tx_1519_2047_byte_packets; /* dword 60*/ 2862 uint32_t tx_2048_4095_byte_packets; /* dword 61*/ 2863 uint32_t tx_4096_8191_byte_packets; /* dword 62*/ 2864 uint32_t tx_8192_9216_byte_packets; /* dword 63*/ 2865 uint32_t rxpp_fifo_overflow_drop; /* dword 64*/ 2866 uint32_t rx_input_fifo_overflow_drop; /* dword 65*/ 2867 }; 2868 2869 2870 struct oce_rxf_stats_v0 { 2871 struct oce_port_rxf_stats_v0 port[2]; 2872 uint32_t rx_drops_no_pbuf; /* dword 132*/ 2873 uint32_t rx_drops_no_txpb; /* dword 133*/ 2874 uint32_t rx_drops_no_erx_descr; /* dword 134*/ 2875 uint32_t rx_drops_no_tpre_descr; /* dword 135*/ 2876 uint32_t management_rx_port_packets; /* dword 136*/ 2877 uint32_t management_rx_port_bytes; /* dword 137*/ 2878 uint32_t management_rx_port_pause_frames;/* dword 138*/ 2879 uint32_t management_rx_port_errors; /* dword 139*/ 2880 uint32_t management_tx_port_packets; /* dword 140*/ 2881 uint32_t management_tx_port_bytes; /* dword 141*/ 2882 uint32_t management_tx_port_pause; /* dword 142*/ 2883 uint32_t management_rx_port_rxfifo_overflow; /* dword 143*/ 2884 uint32_t rx_drops_too_many_frags; /* dword 144*/ 2885 uint32_t rx_drops_invalid_ring; /* dword 145*/ 2886 uint32_t forwarded_packets; /* dword 146*/ 2887 uint32_t rx_drops_mtu; /* dword 147*/ 2888 uint32_t rsvd0[7]; 2889 uint32_t port0_jabber_events; 2890 uint32_t port1_jabber_events; 2891 uint32_t rsvd1[6]; 2892 }; 2893 2894 struct oce_port_rxf_stats_v1 { 2895 uint32_t rsvd0[12]; 2896 uint32_t rx_crc_errors; 2897 uint32_t rx_alignment_symbol_errors; 2898 uint32_t rx_pause_frames; 2899 uint32_t rx_priority_pause_frames; 2900 uint32_t rx_control_frames; 2901 uint32_t rx_in_range_errors; 2902 uint32_t rx_out_range_errors; 2903 uint32_t rx_frame_too_long; 2904 uint32_t rx_address_match_errors; 2905 uint32_t rx_dropped_too_small; 2906 uint32_t rx_dropped_too_short; 2907 uint32_t rx_dropped_header_too_small; 2908 uint32_t rx_dropped_tcp_length; 2909 uint32_t rx_dropped_runt; 2910 uint32_t rsvd1[10]; 2911 uint32_t rx_ip_checksum_errs; 2912 uint32_t rx_tcp_checksum_errs; 2913 uint32_t rx_udp_checksum_errs; 2914 uint32_t rsvd2[7]; 2915 uint32_t rx_switched_unicast_packets; 2916 uint32_t rx_switched_multicast_packets; 2917 uint32_t rx_switched_broadcast_packets; 2918 uint32_t rsvd3[3]; 2919 uint32_t tx_pauseframes; 2920 uint32_t tx_priority_pauseframes; 2921 uint32_t tx_controlframes; 2922 uint32_t rsvd4[10]; 2923 uint32_t rxpp_fifo_overflow_drop; 2924 uint32_t rx_input_fifo_overflow_drop; 2925 uint32_t pmem_fifo_overflow_drop; 2926 uint32_t jabber_events; 2927 uint32_t rsvd5[3]; 2928 }; 2929 2930 2931 struct oce_rxf_stats_v1 { 2932 struct oce_port_rxf_stats_v1 port[4]; 2933 uint32_t rsvd0[2]; 2934 uint32_t rx_drops_no_pbuf; 2935 uint32_t rx_drops_no_txpb; 2936 uint32_t rx_drops_no_erx_descr; 2937 uint32_t rx_drops_no_tpre_descr; 2938 uint32_t rsvd1[6]; 2939 uint32_t rx_drops_too_many_frags; 2940 uint32_t rx_drops_invalid_ring; 2941 uint32_t forwarded_packets; 2942 uint32_t rx_drops_mtu; 2943 uint32_t rsvd2[14]; 2944 }; 2945 2946 struct oce_erx_stats_v1 { 2947 uint32_t rx_drops_no_fragments[68]; 2948 uint32_t rsvd[4]; 2949 }; 2950 2951 2952 struct oce_erx_stats_v0 { 2953 uint32_t rx_drops_no_fragments[44]; 2954 uint32_t rsvd[4]; 2955 }; 2956 2957 struct oce_pmem_stats { 2958 uint32_t eth_red_drops; 2959 uint32_t rsvd[5]; 2960 }; 2961 2962 struct oce_hw_stats_v1 { 2963 struct oce_rxf_stats_v1 rxf; 2964 uint32_t rsvd0[OCE_TXP_SW_SZ]; 2965 struct oce_erx_stats_v1 erx; 2966 struct oce_pmem_stats pmem; 2967 uint32_t rsvd1[18]; 2968 }; 2969 2970 struct oce_hw_stats_v0 { 2971 struct oce_rxf_stats_v0 rxf; 2972 uint32_t rsvd[48]; 2973 struct oce_erx_stats_v0 erx; 2974 struct oce_pmem_stats pmem; 2975 }; 2976 2977 struct mbx_get_nic_stats_v0 { 2978 struct mbx_hdr hdr; 2979 union { 2980 struct { 2981 uint32_t rsvd0; 2982 } req; 2983 2984 union { 2985 struct oce_hw_stats_v0 stats; 2986 } rsp; 2987 } params; 2988 }; 2989 2990 struct mbx_get_nic_stats { 2991 struct mbx_hdr hdr; 2992 union { 2993 struct { 2994 uint32_t rsvd0; 2995 } req; 2996 2997 struct { 2998 struct oce_hw_stats_v1 stats; 2999 } rsp; 3000 } params; 3001 }; 3002 3003 3004 /* [18(0x12)] NIC_GET_PPORT_STATS */ 3005 struct pport_stats { 3006 uint64_t tx_pkts; 3007 uint64_t tx_unicast_pkts; 3008 uint64_t tx_multicast_pkts; 3009 uint64_t tx_broadcast_pkts; 3010 uint64_t tx_bytes; 3011 uint64_t tx_unicast_bytes; 3012 uint64_t tx_multicast_bytes; 3013 uint64_t tx_broadcast_bytes; 3014 uint64_t tx_discards; 3015 uint64_t tx_errors; 3016 uint64_t tx_pause_frames; 3017 uint64_t tx_pause_on_frames; 3018 uint64_t tx_pause_off_frames; 3019 uint64_t tx_internal_mac_errors; 3020 uint64_t tx_control_frames; 3021 uint64_t tx_pkts_64_bytes; 3022 uint64_t tx_pkts_65_to_127_bytes; 3023 uint64_t tx_pkts_128_to_255_bytes; 3024 uint64_t tx_pkts_256_to_511_bytes; 3025 uint64_t tx_pkts_512_to_1023_bytes; 3026 uint64_t tx_pkts_1024_to_1518_bytes; 3027 uint64_t tx_pkts_1519_to_2047_bytes; 3028 uint64_t tx_pkts_2048_to_4095_bytes; 3029 uint64_t tx_pkts_4096_to_8191_bytes; 3030 uint64_t tx_pkts_8192_to_9216_bytes; 3031 uint64_t tx_lso_pkts; 3032 uint64_t rx_pkts; 3033 uint64_t rx_unicast_pkts; 3034 uint64_t rx_multicast_pkts; 3035 uint64_t rx_broadcast_pkts; 3036 uint64_t rx_bytes; 3037 uint64_t rx_unicast_bytes; 3038 uint64_t rx_multicast_bytes; 3039 uint64_t rx_broadcast_bytes; 3040 uint32_t rx_unknown_protos; 3041 uint32_t reserved_word69; 3042 uint64_t rx_discards; 3043 uint64_t rx_errors; 3044 uint64_t rx_crc_errors; 3045 uint64_t rx_alignment_errors; 3046 uint64_t rx_symbol_errors; 3047 uint64_t rx_pause_frames; 3048 uint64_t rx_pause_on_frames; 3049 uint64_t rx_pause_off_frames; 3050 uint64_t rx_frames_too_long; 3051 uint64_t rx_internal_mac_errors; 3052 uint32_t rx_undersize_pkts; 3053 uint32_t rx_oversize_pkts; 3054 uint32_t rx_fragment_pkts; 3055 uint32_t rx_jabbers; 3056 uint64_t rx_control_frames; 3057 uint64_t rx_control_frames_unknown_opcode; 3058 uint32_t rx_in_range_errors; 3059 uint32_t rx_out_of_range_errors; 3060 uint32_t rx_address_match_errors; 3061 uint32_t rx_vlan_mismatch_errors; 3062 uint32_t rx_dropped_too_small; 3063 uint32_t rx_dropped_too_short; 3064 uint32_t rx_dropped_header_too_small; 3065 uint32_t rx_dropped_invalid_tcp_length; 3066 uint32_t rx_dropped_runt; 3067 uint32_t rx_ip_checksum_errors; 3068 uint32_t rx_tcp_checksum_errors; 3069 uint32_t rx_udp_checksum_errors; 3070 uint32_t rx_non_rss_pkts; 3071 uint64_t reserved_word111; 3072 uint64_t rx_ipv4_pkts; 3073 uint64_t rx_ipv6_pkts; 3074 uint64_t rx_ipv4_bytes; 3075 uint64_t rx_ipv6_bytes; 3076 uint64_t rx_nic_pkts; 3077 uint64_t rx_tcp_pkts; 3078 uint64_t rx_iscsi_pkts; 3079 uint64_t rx_management_pkts; 3080 uint64_t rx_switched_unicast_pkts; 3081 uint64_t rx_switched_multicast_pkts; 3082 uint64_t rx_switched_broadcast_pkts; 3083 uint64_t num_forwards; 3084 uint32_t rx_fifo_overflow; 3085 uint32_t rx_input_fifo_overflow; 3086 uint64_t rx_drops_too_many_frags; 3087 uint32_t rx_drops_invalid_queue; 3088 uint32_t reserved_word141; 3089 uint64_t rx_drops_mtu; 3090 uint64_t rx_pkts_64_bytes; 3091 uint64_t rx_pkts_65_to_127_bytes; 3092 uint64_t rx_pkts_128_to_255_bytes; 3093 uint64_t rx_pkts_256_to_511_bytes; 3094 uint64_t rx_pkts_512_to_1023_bytes; 3095 uint64_t rx_pkts_1024_to_1518_bytes; 3096 uint64_t rx_pkts_1519_to_2047_bytes; 3097 uint64_t rx_pkts_2048_to_4095_bytes; 3098 uint64_t rx_pkts_4096_to_8191_bytes; 3099 uint64_t rx_pkts_8192_to_9216_bytes; 3100 }; 3101 3102 struct mbx_get_pport_stats { 3103 /* dw0 - dw3 */ 3104 struct mbx_hdr hdr; 3105 union { 3106 struct { 3107 /* dw4 */ 3108 #ifdef _BIG_ENDIAN 3109 uint32_t reset_stats:8; 3110 uint32_t rsvd0:8; 3111 uint32_t port_number:16; 3112 #else 3113 uint32_t port_number:16; 3114 uint32_t rsvd0:8; 3115 uint32_t reset_stats:8; 3116 #endif 3117 } req; 3118 3119 union { 3120 struct pport_stats pps; 3121 uint32_t pport_stats[164 - 4 + 1]; 3122 } rsp; 3123 } params; 3124 }; 3125 3126 /* [19(0x13)] NIC_GET_VPORT_STATS */ 3127 struct vport_stats { 3128 uint64_t tx_pkts; 3129 uint64_t tx_unicast_pkts; 3130 uint64_t tx_multicast_pkts; 3131 uint64_t tx_broadcast_pkts; 3132 uint64_t tx_bytes; 3133 uint64_t tx_unicast_bytes; 3134 uint64_t tx_multicast_bytes; 3135 uint64_t tx_broadcast_bytes; 3136 uint64_t tx_discards; 3137 uint64_t tx_errors; 3138 uint64_t tx_pkts_64_bytes; 3139 uint64_t tx_pkts_65_to_127_bytes; 3140 uint64_t tx_pkts_128_to_255_bytes; 3141 uint64_t tx_pkts_256_to_511_bytes; 3142 uint64_t tx_pkts_512_to_1023_bytes; 3143 uint64_t tx_pkts_1024_to_1518_bytes; 3144 uint64_t tx_pkts_1519_to_9699_bytes; 3145 uint64_t tx_pkts_over_9699_bytes; 3146 uint64_t rx_pkts; 3147 uint64_t rx_unicast_pkts; 3148 uint64_t rx_multicast_pkts; 3149 uint64_t rx_broadcast_pkts; 3150 uint64_t rx_bytes; 3151 uint64_t rx_unicast_bytes; 3152 uint64_t rx_multicast_bytes; 3153 uint64_t rx_broadcast_bytes; 3154 uint64_t rx_discards; 3155 uint64_t rx_errors; 3156 uint64_t rx_pkts_64_bytes; 3157 uint64_t rx_pkts_65_to_127_bytes; 3158 uint64_t rx_pkts_128_to_255_bytes; 3159 uint64_t rx_pkts_256_to_511_bytes; 3160 uint64_t rx_pkts_512_to_1023_bytes; 3161 uint64_t rx_pkts_1024_to_1518_bytes; 3162 uint64_t rx_pkts_1519_to_9699_bytes; 3163 uint64_t rx_pkts_gt_9699_bytes; 3164 }; 3165 struct mbx_get_vport_stats { 3166 /* dw0 - dw3 */ 3167 struct mbx_hdr hdr; 3168 union { 3169 struct { 3170 /* dw4 */ 3171 #ifdef _BIG_ENDIAN 3172 uint32_t reset_stats:8; 3173 uint32_t rsvd0:8; 3174 uint32_t vport_number:16; 3175 #else 3176 uint32_t vport_number:16; 3177 uint32_t rsvd0:8; 3178 uint32_t reset_stats:8; 3179 #endif 3180 } req; 3181 3182 union { 3183 struct vport_stats vps; 3184 uint32_t vport_stats[75 - 4 + 1]; 3185 } rsp; 3186 } params; 3187 }; 3188 3189 /** 3190 * @brief [20(0x14)] NIC_GET_QUEUE_STATS 3191 * The significant difference between vPort and Queue statistics is 3192 * the packet byte counters. 3193 */ 3194 struct queue_stats { 3195 uint64_t packets; 3196 uint64_t bytes; 3197 uint64_t errors; 3198 uint64_t drops; 3199 uint64_t buffer_errors; /* rsvd when tx */ 3200 }; 3201 3202 #define QUEUE_TYPE_WQ 0 3203 #define QUEUE_TYPE_RQ 1 3204 #define QUEUE_TYPE_HDS_RQ 1 /* same as RQ */ 3205 3206 struct mbx_get_queue_stats { 3207 /* dw0 - dw3 */ 3208 struct mbx_hdr hdr; 3209 union { 3210 struct { 3211 /* dw4 */ 3212 #ifdef _BIG_ENDIAN 3213 uint32_t reset_stats:8; 3214 uint32_t queue_type:8; 3215 uint32_t queue_id:16; 3216 #else 3217 uint32_t queue_id:16; 3218 uint32_t queue_type:8; 3219 uint32_t reset_stats:8; 3220 #endif 3221 } req; 3222 3223 union { 3224 struct queue_stats qs; 3225 uint32_t queue_stats[13 - 4 + 1]; 3226 } rsp; 3227 } params; 3228 }; 3229 3230 3231 /* [01] NIC_CONFIG_RSS */ 3232 #define OCE_HASH_TBL_SZ 10 3233 #define OCE_CPU_TBL_SZ 128 3234 #define OCE_FLUSH 1 /* RSS flush completion per CQ port */ 3235 struct mbx_config_nic_rss { 3236 struct mbx_hdr hdr; 3237 union { 3238 struct { 3239 #ifdef _BIG_ENDIAN 3240 uint32_t if_id; 3241 uint16_t cpu_tbl_sz_log2; 3242 uint16_t enable_rss; 3243 uint32_t hash[OCE_HASH_TBL_SZ]; 3244 uint8_t cputable[OCE_CPU_TBL_SZ]; 3245 uint8_t rsvd[3]; 3246 uint8_t flush; 3247 #else 3248 uint32_t if_id; 3249 uint16_t enable_rss; 3250 uint16_t cpu_tbl_sz_log2; 3251 uint32_t hash[OCE_HASH_TBL_SZ]; 3252 uint8_t cputable[OCE_CPU_TBL_SZ]; 3253 uint8_t flush; 3254 uint8_t rsvd[3]; 3255 #endif 3256 } req; 3257 struct { 3258 uint8_t rsvd[3]; 3259 uint8_t rss_bank; 3260 } rsp; 3261 } params; 3262 }; 3263 3264 3265 #pragma pack() 3266 3267 3268 typedef uint32_t oce_stat_t; /* statistic counter */ 3269 3270 enum OCE_RXF_PORT_STATS { 3271 RXF_RX_BYTES_LSD, 3272 RXF_RX_BYTES_MSD, 3273 RXF_RX_TOTAL_FRAMES, 3274 RXF_RX_UNICAST_FRAMES, 3275 RXF_RX_MULTICAST_FRAMES, 3276 RXF_RX_BROADCAST_FRAMES, 3277 RXF_RX_CRC_ERRORS, 3278 RXF_RX_ALIGNMENT_SYMBOL_ERRORS, 3279 RXF_RX_PAUSE_FRAMES, 3280 RXF_RX_CONTROL_FRAMES, 3281 RXF_RX_IN_RANGE_ERRORS, 3282 RXF_RX_OUT_RANGE_ERRORS, 3283 RXF_RX_FRAME_TOO_LONG, 3284 RXF_RX_ADDRESS_MATCH_ERRORS, 3285 RXF_RX_VLAN_MISMATCH, 3286 RXF_RX_DROPPED_TOO_SMALL, 3287 RXF_RX_DROPPED_TOO_SHORT, 3288 RXF_RX_DROPPED_HEADER_TOO_SMALL, 3289 RXF_RX_DROPPED_TCP_LENGTH, 3290 RXF_RX_DROPPED_RUNT, 3291 RXF_RX_64_BYTE_PACKETS, 3292 RXF_RX_65_127_BYTE_PACKETS, 3293 RXF_RX_128_256_BYTE_PACKETS, 3294 RXF_RX_256_511_BYTE_PACKETS, 3295 RXF_RX_512_1023_BYTE_PACKETS, 3296 RXF_RX_1024_1518_BYTE_PACKETS, 3297 RXF_RX_1519_2047_BYTE_PACKETS, 3298 RXF_RX_2048_4095_BYTE_PACKETS, 3299 RXF_RX_4096_8191_BYTE_PACKETS, 3300 RXF_RX_8192_9216_BYTE_PACKETS, 3301 RXF_RX_IP_CHECKSUM_ERRS, 3302 RXF_RX_TCP_CHECKSUM_ERRS, 3303 RXF_RX_UDP_CHECKSUM_ERRS, 3304 RXF_RX_NON_RSS_PACKETS, 3305 RXF_RX_IPV4_PACKETS, 3306 RXF_RX_IPV6_PACKETS, 3307 RXF_RX_IPV4_BYTES_LSD, 3308 RXF_RX_IPV4_BYTES_MSD, 3309 RXF_RX_IPV6_BYTES_LSD, 3310 RXF_RX_IPV6_BYTES_MSD, 3311 RXF_RX_CHUTE1_PACKETS, 3312 RXF_RX_CHUTE2_PACKETS, 3313 RXF_RX_CHUTE3_PACKETS, 3314 RXF_RX_MANAGEMENT_PACKETS, 3315 RXF_RX_SWITCHED_UNICAST_PACKETS, 3316 RXF_RX_SWITCHED_MULTICAST_PACKETS, 3317 RXF_RX_SWITCHED_BROADCAST_PACKETS, 3318 RXF_TX_BYTES_LSD, 3319 RXF_TX_BYTES_MSD, 3320 RXF_TX_UNICAST_FRAMES, 3321 RXF_TX_MULTICAST_FRAMES, 3322 RXF_TX_BROADCAST_FRAMES, 3323 RXF_TX_PAUSE_FRAMES, 3324 RXF_TX_CONTROL_FRAMES, 3325 RXF_TX_64_BYTE_PACKETS, 3326 RXF_TX_65_127_BYTE_PACKETS, 3327 RXF_TX_128_256_BYTE_PACKETS, 3328 RXF_TX_256_511_BYTE_PACKETS, 3329 RXF_TX_512_1023_BYTE_PACKETS, 3330 RXF_TX_1024_1518_BYTE_PACKETS, 3331 RXF_TX_1519_2047_BYTE_PACKETS, 3332 RXF_TX_2048_4095_BYTE_PACKETS, 3333 RXF_TX_4096_8191_BYTE_PACKETS, 3334 RXF_TX_8192_9216_BYTE_PACKETS, 3335 RXF_RX_FIFO_OVERFLOW, 3336 RXF_RX_INPUT_FIFO_OVERFLOW, 3337 RXF_PORT_STATS_N_WORDS 3338 }; 3339 3340 enum OCE_RXF_ADDL_STATS { 3341 RXF_RX_DROPS_NO_PBUF, 3342 RXF_RX_DROPS_NO_TXPB, 3343 RXF_RX_DROPS_NO_ERX_DESCR, 3344 RXF_RX_DROPS_NO_TPRE_DESCR, 3345 RXF_MANAGEMENT_RX_PORT_PACKETS, 3346 RXF_MANAGEMENT_RX_PORT_BYTES, 3347 RXF_MANAGEMENT_RX_PORT_PAUSE_FRAMES, 3348 RXF_MANAGEMENT_RX_PORT_ERRORS, 3349 RXF_MANAGEMENT_TX_PORT_PACKETS, 3350 RXF_MANAGEMENT_TX_PORT_BYTES, 3351 RXF_MANAGEMENT_TX_PORT_PAUSE, 3352 RXF_MANAGEMENT_RX_PORT_RXFIFO_OVERFLOW, 3353 RXF_RX_DROPS_TOO_MANY_FRAGS, 3354 RXF_RX_DROPS_INVALID_RING, 3355 RXF_FORWARDED_PACKETS, 3356 RXF_RX_DROPS_MTU, 3357 RXF_ADDL_STATS_N_WORDS 3358 }; 3359 3360 enum OCE_TX_CHUTE_PORT_STATS { 3361 CTPT_XMT_IPV4_PKTS, 3362 CTPT_XMT_IPV4_LSD, 3363 CTPT_XMT_IPV4_MSD, 3364 CTPT_XMT_IPV6_PKTS, 3365 CTPT_XMT_IPV6_LSD, 3366 CTPT_XMT_IPV6_MSD, 3367 CTPT_REXMT_IPV4_PKTs, 3368 CTPT_REXMT_IPV4_LSD, 3369 CTPT_REXMT_IPV4_MSD, 3370 CTPT_REXMT_IPV6_PKTs, 3371 CTPT_REXMT_IPV6_LSD, 3372 CTPT_REXMT_IPV6_MSD, 3373 CTPT_N_WORDS, 3374 }; 3375 3376 enum OCE_RX_ERR_STATS { 3377 RX_DROPS_NO_FRAGMENTS_0, 3378 RX_DROPS_NO_FRAGMENTS_1, 3379 RX_DROPS_NO_FRAGMENTS_2, 3380 RX_DROPS_NO_FRAGMENTS_3, 3381 RX_DROPS_NO_FRAGMENTS_4, 3382 RX_DROPS_NO_FRAGMENTS_5, 3383 RX_DROPS_NO_FRAGMENTS_6, 3384 RX_DROPS_NO_FRAGMENTS_7, 3385 RX_DROPS_NO_FRAGMENTS_8, 3386 RX_DROPS_NO_FRAGMENTS_9, 3387 RX_DROPS_NO_FRAGMENTS_10, 3388 RX_DROPS_NO_FRAGMENTS_11, 3389 RX_DROPS_NO_FRAGMENTS_12, 3390 RX_DROPS_NO_FRAGMENTS_13, 3391 RX_DROPS_NO_FRAGMENTS_14, 3392 RX_DROPS_NO_FRAGMENTS_15, 3393 RX_DROPS_NO_FRAGMENTS_16, 3394 RX_DROPS_NO_FRAGMENTS_17, 3395 RX_DROPS_NO_FRAGMENTS_18, 3396 RX_DROPS_NO_FRAGMENTS_19, 3397 RX_DROPS_NO_FRAGMENTS_20, 3398 RX_DROPS_NO_FRAGMENTS_21, 3399 RX_DROPS_NO_FRAGMENTS_22, 3400 RX_DROPS_NO_FRAGMENTS_23, 3401 RX_DROPS_NO_FRAGMENTS_24, 3402 RX_DROPS_NO_FRAGMENTS_25, 3403 RX_DROPS_NO_FRAGMENTS_26, 3404 RX_DROPS_NO_FRAGMENTS_27, 3405 RX_DROPS_NO_FRAGMENTS_28, 3406 RX_DROPS_NO_FRAGMENTS_29, 3407 RX_DROPS_NO_FRAGMENTS_30, 3408 RX_DROPS_NO_FRAGMENTS_31, 3409 RX_DROPS_NO_FRAGMENTS_32, 3410 RX_DROPS_NO_FRAGMENTS_33, 3411 RX_DROPS_NO_FRAGMENTS_34, 3412 RX_DROPS_NO_FRAGMENTS_35, 3413 RX_DROPS_NO_FRAGMENTS_36, 3414 RX_DROPS_NO_FRAGMENTS_37, 3415 RX_DROPS_NO_FRAGMENTS_38, 3416 RX_DROPS_NO_FRAGMENTS_39, 3417 RX_DROPS_NO_FRAGMENTS_40, 3418 RX_DROPS_NO_FRAGMENTS_41, 3419 RX_DROPS_NO_FRAGMENTS_42, 3420 RX_DROPS_NO_FRAGMENTS_43, 3421 RX_DEBUG_WDMA_SENT_HOLD, 3422 RX_DEBUG_WDMA_PBFREE_SENT_HOLD, 3423 RX_DEBUG_WDMA_0B_PBFREE_SENT_HOLD, 3424 RX_DEBUG_PMEM_PBUF_DEALLOC, 3425 RX_ERRORS_N_WORDS 3426 }; 3427 3428 enum OCE_PMEM_ERR_STATS { 3429 PMEM_ETH_RED_DROPS, 3430 PMEM_LRO_RED_DROPS, 3431 PMEM_ULP0_RED_DROPS, 3432 PMEM_ULP1_RED_DROPS, 3433 PMEM_GLOBAL_RED_DROPS, 3434 PMEM_ERRORS_N_WORDS 3435 }; 3436 3437 /** 3438 * @brief Statistics for a given Physical Port 3439 * These satisfy all the required BE2 statistics and also the 3440 * following MIB objects: 3441 * 3442 * RFC 2863 - The Interfaces Group MIB 3443 * RFC 2819 - Remote Network Monitoring Management Information Base (RMON) 3444 * RFC 3635 - Managed Objects for the Ethernet-like Interface Types 3445 * RFC 4502 - Remote Network Monitoring Mgmt Information Base Ver-2 (RMON2) 3446 * 3447 */ 3448 enum OCE_PPORT_STATS { 3449 PPORT_TX_PKTS = 0, 3450 PPORT_TX_UNICAST_PKTS = 2, 3451 PPORT_TX_MULTICAST_PKTS = 4, 3452 PPORT_TX_BROADCAST_PKTS = 6, 3453 PPORT_TX_BYTES = 8, 3454 PPORT_TX_UNICAST_BYTES = 10, 3455 PPORT_TX_MULTICAST_BYTES = 12, 3456 PPORT_TX_BROADCAST_BYTES = 14, 3457 PPORT_TX_DISCARDS = 16, 3458 PPORT_TX_ERRORS = 18, 3459 PPORT_TX_PAUSE_FRAMES = 20, 3460 PPORT_TX_PAUSE_ON_FRAMES = 22, 3461 PPORT_TX_PAUSE_OFF_FRAMES = 24, 3462 PPORT_TX_INTERNAL_MAC_ERRORS = 26, 3463 PPORT_TX_CONTROL_FRAMES = 28, 3464 PPORT_TX_PKTS_64_BYTES = 30, 3465 PPORT_TX_PKTS_65_TO_127_BYTES = 32, 3466 PPORT_TX_PKTS_128_TO_255_BYTES = 34, 3467 PPORT_TX_PKTS_256_TO_511_BYTES = 36, 3468 PPORT_TX_PKTS_512_TO_1023_BYTES = 38, 3469 PPORT_TX_PKTS_1024_TO_1518_BYTES = 40, 3470 PPORT_TX_PKTS_1519_TO_2047_BYTES = 42, 3471 PPORT_TX_PKTS_2048_TO_4095_BYTES = 44, 3472 PPORT_TX_PKTS_4096_TO_8191_BYTES = 46, 3473 PPORT_TX_PKTS_8192_TO_9216_BYTES = 48, 3474 PPORT_TX_LSO_PKTS = 50, 3475 PPORT_RX_PKTS = 52, 3476 PPORT_RX_UNICAST_PKTS = 54, 3477 PPORT_RX_MULTICAST_PKTS = 56, 3478 PPORT_RX_BROADCAST_PKTS = 58, 3479 PPORT_RX_BYTES = 60, 3480 PPORT_RX_UNICAST_BYTES = 62, 3481 PPORT_RX_MULTICAST_BYTES = 64, 3482 PPORT_RX_BROADCAST_BYTES = 66, 3483 PPORT_RX_UNKNOWN_PROTOS = 68, 3484 PPORT_RESERVED_WORD69 = 69, 3485 PPORT_RX_DISCARDS = 70, 3486 PPORT_RX_ERRORS = 72, 3487 PPORT_RX_CRC_ERRORS = 74, 3488 PPORT_RX_ALIGNMENT_ERRORS = 76, 3489 PPORT_RX_SYMBOL_ERRORS = 78, 3490 PPORT_RX_PAUSE_FRAMES = 80, 3491 PPORT_RX_PAUSE_ON_FRAMES = 82, 3492 PPORT_RX_PAUSE_OFF_FRAMES = 84, 3493 PPORT_RX_FRAMES_TOO_LONG = 86, 3494 PPORT_RX_INTERNAL_MAC_ERRORS = 88, 3495 PPORT_RX_UNDERSIZE_PKTS = 90, 3496 PPORT_RX_OVERSIZE_PKTS = 91, 3497 PPORT_RX_FRAGMENT_PKTS = 92, 3498 PPORT_RX_JABBERS = 93, 3499 PPORT_RX_CONTROL_FRAMES = 94, 3500 PPORT_RX_CONTROL_FRAMES_UNK_OPCODE = 96, 3501 PPORT_RX_IN_RANGE_ERRORS = 98, 3502 PPORT_RX_OUT_OF_RANGE_ERRORS = 99, 3503 PPORT_RX_ADDRESS_MATCH_ERRORS = 100, 3504 PPORT_RX_VLAN_MISMATCH_ERRORS = 101, 3505 PPORT_RX_DROPPED_TOO_SMALL = 102, 3506 PPORT_RX_DROPPED_TOO_SHORT = 103, 3507 PPORT_RX_DROPPED_HEADER_TOO_SMALL = 104, 3508 PPORT_RX_DROPPED_INVALID_TCP_LENGTH = 105, 3509 PPORT_RX_DROPPED_RUNT = 106, 3510 PPORT_RX_IP_CHECKSUM_ERRORS = 107, 3511 PPORT_RX_TCP_CHECKSUM_ERRORS = 108, 3512 PPORT_RX_UDP_CHECKSUM_ERRORS = 109, 3513 PPORT_RX_NON_RSS_PKTS = 110, 3514 PPORT_RESERVED_WORD111 = 111, 3515 PPORT_RX_IPV4_PKTS = 112, 3516 PPORT_RX_IPV6_PKTS = 114, 3517 PPORT_RX_IPV4_BYTES = 116, 3518 PPORT_RX_IPV6_BYTES = 118, 3519 PPORT_RX_NIC_PKTS = 120, 3520 PPORT_RX_TCP_PKTS = 122, 3521 PPORT_RX_ISCSI_PKTS = 124, 3522 PPORT_RX_MANAGEMENT_PKTS = 126, 3523 PPORT_RX_SWITCHED_UNICAST_PKTS = 128, 3524 PPORT_RX_SWITCHED_MULTICAST_PKTS = 130, 3525 PPORT_RX_SWITCHED_BROADCAST_PKTS = 132, 3526 PPORT_NUM_FORWARDS = 134, 3527 PPORT_RX_FIFO_OVERFLOW = 136, 3528 PPORT_RX_INPUT_FIFO_OVERFLOW = 137, 3529 PPORT_RX_DROPS_TOO_MANY_FRAGS = 138, 3530 PPORT_RX_DROPS_INVALID_QUEUE = 140, 3531 PPORT_RESERVED_WORD141 = 141, 3532 PPORT_RX_DROPS_MTU = 142, 3533 PPORT_RX_PKTS_64_BYTES = 144, 3534 PPORT_RX_PKTS_65_TO_127_BYTES = 146, 3535 PPORT_RX_PKTS_128_TO_255_BYTES = 148, 3536 PPORT_RX_PKTS_256_TO_511_BYTES = 150, 3537 PPORT_RX_PKTS_512_TO_1023_BYTES = 152, 3538 PPORT_RX_PKTS_1024_TO_1518_BYTES = 154, 3539 PPORT_RX_PKTS_1519_TO_2047_BYTES = 156, 3540 PPORT_RX_PKTS_2048_TO_4095_BYTES = 158, 3541 PPORT_RX_PKTS_4096_TO_8191_BYTES = 160, 3542 PPORT_RX_PKTS_8192_TO_9216_BYTES = 162, 3543 PPORT_N_WORDS = 164 3544 }; 3545 3546 /** 3547 * @brief Statistics for a given Virtual Port (vPort) 3548 * The following describes the vPort statistics satisfying 3549 * requirements of Linux/VMWare netdev statistics and 3550 * Microsoft Windows Statistics along with other Operating Systems. 3551 */ 3552 enum OCE_VPORT_STATS { 3553 VPORT_TX_PKTS = 0, 3554 VPORT_TX_UNICAST_PKTS = 2, 3555 VPORT_TX_MULTICAST_PKTS = 4, 3556 VPORT_TX_BROADCAST_PKTS = 6, 3557 VPORT_TX_BYTES = 8, 3558 VPORT_TX_UNICAST_BYTES = 10, 3559 VPORT_TX_MULTICAST_BYTES = 12, 3560 VPORT_TX_BROADCAST_BYTES = 14, 3561 VPORT_TX_DISCARDS = 16, 3562 VPORT_TX_ERRORS = 18, 3563 VPORT_TX_PKTS_64_BYTES = 20, 3564 VPORT_TX_PKTS_65_TO_127_BYTES = 22, 3565 VPORT_TX_PKTS_128_TO_255_BYTES = 24, 3566 VPORT_TX_PKTS_256_TO_511_BYTES = 26, 3567 VPORT_TX_PKTS_512_TO_1023_BYTEs = 28, 3568 VPORT_TX_PKTS_1024_TO_1518_BYTEs = 30, 3569 VPORT_TX_PKTS_1519_TO_9699_BYTEs = 32, 3570 VPORT_TX_PKTS_OVER_9699_BYTES = 34, 3571 VPORT_RX_PKTS = 36, 3572 VPORT_RX_UNICAST_PKTS = 38, 3573 VPORT_RX_MULTICAST_PKTS = 40, 3574 VPORT_RX_BROADCAST_PKTS = 42, 3575 VPORT_RX_BYTES = 44, 3576 VPORT_RX_UNICAST_BYTES = 46, 3577 VPORT_RX_MULTICAST_BYTES = 48, 3578 VPORT_RX_BROADCAST_BYTES = 50, 3579 VPORT_RX_DISCARDS = 52, 3580 VPORT_RX_ERRORS = 54, 3581 VPORT_RX_PKTS_64_BYTES = 56, 3582 VPORT_RX_PKTS_65_TO_127_BYTES = 58, 3583 VPORT_RX_PKTS_128_TO_255_BYTES = 60, 3584 VPORT_RX_PKTS_256_TO_511_BYTES = 62, 3585 VPORT_RX_PKTS_512_TO_1023_BYTEs = 64, 3586 VPORT_RX_PKTS_1024_TO_1518_BYTEs = 66, 3587 VPORT_RX_PKTS_1519_TO_9699_BYTEs = 68, 3588 VPORT_RX_PKTS_OVER_9699_BYTES = 70, 3589 VPORT_N_WORDS = 72 3590 }; 3591 3592 /** 3593 * @brief Statistics for a given queue (NIC WQ, RQ, or HDS RQ) 3594 * This set satisfies requirements of VMQare NetQueue and Microsoft VMQ 3595 */ 3596 enum OCE_QUEUE_TX_STATS { 3597 QUEUE_TX_PKTS = 0, 3598 QUEUE_TX_BYTES = 2, 3599 QUEUE_TX_ERRORS = 4, 3600 QUEUE_TX_DROPS = 6, 3601 QUEUE_TX_N_WORDS = 8 3602 }; 3603 3604 enum OCE_QUEUE_RX_STATS { 3605 QUEUE_RX_PKTS = 0, 3606 QUEUE_RX_BYTES = 2, 3607 QUEUE_RX_ERRORS = 4, 3608 QUEUE_RX_DROPS = 6, 3609 QUEUE_RX_BUFFER_ERRORS = 8, 3610 QUEUE_RX_N_WORDS = 10 3611 }; 3612 3613