1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (C) 2013 Emulex 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Emulex Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * Contact Information: 34 * freebsd-drivers@emulex.com 35 * 36 * Emulex 37 * 3333 Susan Street 38 * Costa Mesa, CA 92626 39 */ 40 41 /* $FreeBSD$ */ 42 43 #include <sys/types.h> 44 45 #undef _BIG_ENDIAN /* TODO */ 46 #pragma pack(1) 47 48 #define OC_CNA_GEN2 0x2 49 #define OC_CNA_GEN3 0x3 50 #define DEVID_TIGERSHARK 0x700 51 #define DEVID_TOMCAT 0x710 52 53 /* PCI CSR offsets */ 54 #define PCICFG_F1_CSR 0x0 /* F1 for NIC */ 55 #define PCICFG_SEMAPHORE 0xbc 56 #define PCICFG_SOFT_RESET 0x5c 57 #define PCICFG_UE_STATUS_HI_MASK 0xac 58 #define PCICFG_UE_STATUS_LO_MASK 0xa8 59 #define PCICFG_ONLINE0 0xb0 60 #define PCICFG_ONLINE1 0xb4 61 #define INTR_EN 0x20000000 62 #define IMAGE_TRANSFER_SIZE (32 * 1024) /* 32K at a time */ 63 64 65 /********* UE Status and Mask Registers ***/ 66 #define PCICFG_UE_STATUS_LOW 0xA0 67 #define PCICFG_UE_STATUS_HIGH 0xA4 68 #define PCICFG_UE_STATUS_LOW_MASK 0xA8 69 70 /* Lancer SLIPORT registers */ 71 #define SLIPORT_STATUS_OFFSET 0x404 72 #define SLIPORT_CONTROL_OFFSET 0x408 73 #define SLIPORT_ERROR1_OFFSET 0x40C 74 #define SLIPORT_ERROR2_OFFSET 0x410 75 #define PHYSDEV_CONTROL_OFFSET 0x414 76 77 #define SLIPORT_STATUS_ERR_MASK 0x80000000 78 #define SLIPORT_STATUS_DIP_MASK 0x02000000 79 #define SLIPORT_STATUS_RN_MASK 0x01000000 80 #define SLIPORT_STATUS_RDY_MASK 0x00800000 81 #define SLI_PORT_CONTROL_IP_MASK 0x08000000 82 #define PHYSDEV_CONTROL_FW_RESET_MASK 0x00000002 83 #define PHYSDEV_CONTROL_DD_MASK 0x00000004 84 #define PHYSDEV_CONTROL_INP_MASK 0x40000000 85 86 #define SLIPORT_ERROR_NO_RESOURCE1 0x2 87 #define SLIPORT_ERROR_NO_RESOURCE2 0x9 88 /* CSR register offsets */ 89 #define MPU_EP_CONTROL 0 90 #define MPU_EP_SEMAPHORE_BE3 0xac 91 #define MPU_EP_SEMAPHORE_XE201 0x400 92 #define MPU_EP_SEMAPHORE_SH 0x94 93 #define PCICFG_INTR_CTRL 0xfc 94 #define HOSTINTR_MASK (1 << 29) 95 #define HOSTINTR_PFUNC_SHIFT 26 96 #define HOSTINTR_PFUNC_MASK 7 97 98 /* POST status reg struct */ 99 #define POST_STAGE_POWER_ON_RESET 0x00 100 #define POST_STAGE_AWAITING_HOST_RDY 0x01 101 #define POST_STAGE_HOST_RDY 0x02 102 #define POST_STAGE_CHIP_RESET 0x03 103 #define POST_STAGE_ARMFW_READY 0xc000 104 #define POST_STAGE_ARMFW_UE 0xf000 105 106 /* DOORBELL registers */ 107 #define PD_RXULP_DB 0x0100 108 #define PD_TXULP_DB 0x0060 109 #define DB_RQ_ID_MASK 0x3FF 110 111 #define PD_CQ_DB 0x0120 112 #define PD_EQ_DB PD_CQ_DB 113 #define PD_MPU_MBOX_DB 0x0160 114 #define PD_MQ_DB 0x0140 115 116 #define DB_OFFSET 0xc0 117 #define DB_LRO_RQ_ID_MASK 0x7FF 118 119 /* EQE completion types */ 120 #define EQ_MINOR_CODE_COMPLETION 0x00 121 #define EQ_MINOR_CODE_OTHER 0x01 122 #define EQ_MAJOR_CODE_COMPLETION 0x00 123 124 /* Link Status field values */ 125 #define PHY_LINK_FAULT_NONE 0x0 126 #define PHY_LINK_FAULT_LOCAL 0x01 127 #define PHY_LINK_FAULT_REMOTE 0x02 128 129 #define PHY_LINK_SPEED_ZERO 0x0 /* No link */ 130 #define PHY_LINK_SPEED_10MBPS 0x1 /* (10 Mbps) */ 131 #define PHY_LINK_SPEED_100MBPS 0x2 /* (100 Mbps) */ 132 #define PHY_LINK_SPEED_1GBPS 0x3 /* (1 Gbps) */ 133 #define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */ 134 135 #define PHY_LINK_DUPLEX_NONE 0x0 136 #define PHY_LINK_DUPLEX_HALF 0x1 137 #define PHY_LINK_DUPLEX_FULL 0x2 138 139 #define NTWK_PORT_A 0x0 /* (Port A) */ 140 #define NTWK_PORT_B 0x1 /* (Port B) */ 141 142 #define PHY_LINK_SPEED_ZERO 0x0 /* (No link.) */ 143 #define PHY_LINK_SPEED_10MBPS 0x1 /* (10 Mbps) */ 144 #define PHY_LINK_SPEED_100MBPS 0x2 /* (100 Mbps) */ 145 #define PHY_LINK_SPEED_1GBPS 0x3 /* (1 Gbps) */ 146 #define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */ 147 148 /* Hardware Address types */ 149 #define MAC_ADDRESS_TYPE_STORAGE 0x0 /* (Storage MAC Address) */ 150 #define MAC_ADDRESS_TYPE_NETWORK 0x1 /* (Network MAC Address) */ 151 #define MAC_ADDRESS_TYPE_PD 0x2 /* (Protection Domain MAC Addr) */ 152 #define MAC_ADDRESS_TYPE_MANAGEMENT 0x3 /* (Management MAC Address) */ 153 #define MAC_ADDRESS_TYPE_FCOE 0x4 /* (FCoE MAC Address) */ 154 155 /* CREATE_IFACE capability and cap_en flags */ 156 #define MBX_RX_IFACE_FLAGS_RSS 0x4 157 #define MBX_RX_IFACE_FLAGS_PROMISCUOUS 0x8 158 #define MBX_RX_IFACE_FLAGS_BROADCAST 0x10 159 #define MBX_RX_IFACE_FLAGS_UNTAGGED 0x20 160 #define MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS 0x80 161 #define MBX_RX_IFACE_FLAGS_VLAN 0x100 162 #define MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS 0x200 163 #define MBX_RX_IFACE_FLAGS_PASS_L2_ERR 0x400 164 #define MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR 0x800 165 #define MBX_RX_IFACE_FLAGS_MULTICAST 0x1000 166 #define MBX_RX_IFACE_RX_FILTER_IF_MULTICAST_HASH 0x2000 167 #define MBX_RX_IFACE_FLAGS_HDS 0x4000 168 #define MBX_RX_IFACE_FLAGS_DIRECTED 0x8000 169 #define MBX_RX_IFACE_FLAGS_VMQ 0x10000 170 #define MBX_RX_IFACE_FLAGS_NETQ 0x20000 171 #define MBX_RX_IFACE_FLAGS_QGROUPS 0x40000 172 #define MBX_RX_IFACE_FLAGS_LSO 0x80000 173 #define MBX_RX_IFACE_FLAGS_LRO 0x100000 174 175 #define MQ_RING_CONTEXT_SIZE_16 0x5 /* (16 entries) */ 176 #define MQ_RING_CONTEXT_SIZE_32 0x6 /* (32 entries) */ 177 #define MQ_RING_CONTEXT_SIZE_64 0x7 /* (64 entries) */ 178 #define MQ_RING_CONTEXT_SIZE_128 0x8 /* (128 entries) */ 179 180 #define MBX_DB_READY_BIT 0x1 181 #define MBX_DB_HI_BIT 0x2 182 #define ASYNC_EVENT_CODE_LINK_STATE 0x1 183 #define ASYNC_EVENT_LINK_UP 0x1 184 #define ASYNC_EVENT_LINK_DOWN 0x0 185 #define ASYNC_EVENT_GRP5 0x5 186 #define ASYNC_EVENT_CODE_DEBUG 0x6 187 #define ASYNC_EVENT_PVID_STATE 0x3 188 #define ASYNC_EVENT_OS2BMC 0x5 189 #define ASYNC_EVENT_DEBUG_QNQ 0x1 190 #define ASYNC_EVENT_CODE_SLIPORT 0x11 191 #define VLAN_VID_MASK 0x0FFF 192 193 /* port link_status */ 194 #define ASYNC_EVENT_LOGICAL 0x02 195 196 /* Logical Link Status */ 197 #define NTWK_LOGICAL_LINK_DOWN 0 198 #define NTWK_LOGICAL_LINK_UP 1 199 200 /* Rx filter bits */ 201 #define NTWK_RX_FILTER_IP_CKSUM 0x1 202 #define NTWK_RX_FILTER_TCP_CKSUM 0x2 203 #define NTWK_RX_FILTER_UDP_CKSUM 0x4 204 #define NTWK_RX_FILTER_STRIP_CRC 0x8 205 206 /* max SGE per mbx */ 207 #define MAX_MBX_SGE 19 208 209 /* Max multicast filter size*/ 210 #define OCE_MAX_MC_FILTER_SIZE 64 211 212 /* PCI SLI (Service Level Interface) capabilities register */ 213 #define OCE_INTF_REG_OFFSET 0x58 214 #define OCE_INTF_VALID_SIG 6 /* register's signature */ 215 #define OCE_INTF_FUNC_RESET_REQD 1 216 #define OCE_INTF_HINT1_NOHINT 0 217 #define OCE_INTF_HINT1_SEMAINIT 1 218 #define OCE_INTF_HINT1_STATCTRL 2 219 #define OCE_INTF_IF_TYPE_0 0 220 #define OCE_INTF_IF_TYPE_1 1 221 #define OCE_INTF_IF_TYPE_2 2 222 #define OCE_INTF_IF_TYPE_3 3 223 #define OCE_INTF_SLI_REV3 3 /* not supported by driver */ 224 #define OCE_INTF_SLI_REV4 4 /* driver supports SLI-4 */ 225 #define OCE_INTF_PHYS_FUNC 0 226 #define OCE_INTF_VIRT_FUNC 1 227 #define OCE_INTF_FAMILY_BE2 0 /* not supported by driver */ 228 #define OCE_INTF_FAMILY_BE3 1 /* driver supports BE3 */ 229 #define OCE_INTF_FAMILY_A0_CHIP 0xA /* Lancer A0 chip (supported) */ 230 #define OCE_INTF_FAMILY_B0_CHIP 0xB /* Lancer B0 chip (future) */ 231 232 #define NIC_WQE_SIZE 16 233 #define NIC_UNICAST 0x00 234 #define NIC_MULTICAST 0x01 235 #define NIC_BROADCAST 0x02 236 237 #define NIC_HDS_NO_SPLIT 0x00 238 #define NIC_HDS_SPLIT_L3PL 0x01 239 #define NIC_HDS_SPLIT_L4PL 0x02 240 241 #define NIC_WQ_TYPE_FORWARDING 0x01 242 #define NIC_WQ_TYPE_STANDARD 0x02 243 #define NIC_WQ_TYPE_LOW_LATENCY 0x04 244 245 #define OCE_RESET_STATS 1 246 #define OCE_RETAIN_STATS 0 247 #define OCE_TXP_SW_SZ 48 248 249 typedef union pci_sli_intf_u { 250 uint32_t dw0; 251 struct { 252 #ifdef _BIG_ENDIAN 253 uint32_t sli_valid:3; 254 uint32_t sli_hint2:5; 255 uint32_t sli_hint1:8; 256 uint32_t sli_if_type:4; 257 uint32_t sli_family:4; 258 uint32_t sli_rev:4; 259 uint32_t rsv0:3; 260 uint32_t sli_func_type:1; 261 #else 262 uint32_t sli_func_type:1; 263 uint32_t rsv0:3; 264 uint32_t sli_rev:4; 265 uint32_t sli_family:4; 266 uint32_t sli_if_type:4; 267 uint32_t sli_hint1:8; 268 uint32_t sli_hint2:5; 269 uint32_t sli_valid:3; 270 #endif 271 } bits; 272 } pci_sli_intf_t; 273 274 275 276 /* physical address structure to be used in MBX */ 277 struct phys_addr { 278 /* dw0 */ 279 uint32_t lo; 280 /* dw1 */ 281 uint32_t hi; 282 }; 283 284 285 286 typedef union pcicfg_intr_ctl_u { 287 uint32_t dw0; 288 struct { 289 #ifdef _BIG_ENDIAN 290 uint32_t winselect:2; 291 uint32_t hostintr:1; 292 uint32_t pfnum:3; 293 uint32_t vf_cev_int_line_en:1; 294 uint32_t winaddr:23; 295 uint32_t membarwinen:1; 296 #else 297 uint32_t membarwinen:1; 298 uint32_t winaddr:23; 299 uint32_t vf_cev_int_line_en:1; 300 uint32_t pfnum:3; 301 uint32_t hostintr:1; 302 uint32_t winselect:2; 303 #endif 304 } bits; 305 } pcicfg_intr_ctl_t; 306 307 308 309 310 typedef union pcicfg_semaphore_u { 311 uint32_t dw0; 312 struct { 313 #ifdef _BIG_ENDIAN 314 uint32_t rsvd:31; 315 uint32_t lock:1; 316 #else 317 uint32_t lock:1; 318 uint32_t rsvd:31; 319 #endif 320 } bits; 321 } pcicfg_semaphore_t; 322 323 324 325 326 typedef union pcicfg_soft_reset_u { 327 uint32_t dw0; 328 struct { 329 #ifdef _BIG_ENDIAN 330 uint32_t nec_ll_rcvdetect:8; 331 uint32_t dbg_all_reqs_62_49:14; 332 uint32_t scratchpad0:1; 333 uint32_t exception_oe:1; 334 uint32_t soft_reset:1; 335 uint32_t rsvd0:7; 336 #else 337 uint32_t rsvd0:7; 338 uint32_t soft_reset:1; 339 uint32_t exception_oe:1; 340 uint32_t scratchpad0:1; 341 uint32_t dbg_all_reqs_62_49:14; 342 uint32_t nec_ll_rcvdetect:8; 343 #endif 344 } bits; 345 } pcicfg_soft_reset_t; 346 347 348 349 350 typedef union pcicfg_online1_u { 351 uint32_t dw0; 352 struct { 353 #ifdef _BIG_ENDIAN 354 uint32_t host8_online:1; 355 uint32_t host7_online:1; 356 uint32_t host6_online:1; 357 uint32_t host5_online:1; 358 uint32_t host4_online:1; 359 uint32_t host3_online:1; 360 uint32_t host2_online:1; 361 uint32_t ipc_online:1; 362 uint32_t arm_online:1; 363 uint32_t txp_online:1; 364 uint32_t xaui_online:1; 365 uint32_t rxpp_online:1; 366 uint32_t txpb_online:1; 367 uint32_t rr_online:1; 368 uint32_t pmem_online:1; 369 uint32_t pctl1_online:1; 370 uint32_t pctl0_online:1; 371 uint32_t pcs1online_online:1; 372 uint32_t mpu_iram_online:1; 373 uint32_t pcs0online_online:1; 374 uint32_t mgmt_mac_online:1; 375 uint32_t lpcmemhost_online:1; 376 #else 377 uint32_t lpcmemhost_online:1; 378 uint32_t mgmt_mac_online:1; 379 uint32_t pcs0online_online:1; 380 uint32_t mpu_iram_online:1; 381 uint32_t pcs1online_online:1; 382 uint32_t pctl0_online:1; 383 uint32_t pctl1_online:1; 384 uint32_t pmem_online:1; 385 uint32_t rr_online:1; 386 uint32_t txpb_online:1; 387 uint32_t rxpp_online:1; 388 uint32_t xaui_online:1; 389 uint32_t txp_online:1; 390 uint32_t arm_online:1; 391 uint32_t ipc_online:1; 392 uint32_t host2_online:1; 393 uint32_t host3_online:1; 394 uint32_t host4_online:1; 395 uint32_t host5_online:1; 396 uint32_t host6_online:1; 397 uint32_t host7_online:1; 398 uint32_t host8_online:1; 399 #endif 400 } bits; 401 } pcicfg_online1_t; 402 403 404 405 typedef union mpu_ep_semaphore_u { 406 uint32_t dw0; 407 struct { 408 #ifdef _BIG_ENDIAN 409 uint32_t error:1; 410 uint32_t backup_fw:1; 411 uint32_t iscsi_no_ip:1; 412 uint32_t iscsi_ip_conflict:1; 413 uint32_t option_rom_installed:1; 414 uint32_t iscsi_drv_loaded:1; 415 uint32_t rsvd0:10; 416 uint32_t stage:16; 417 #else 418 uint32_t stage:16; 419 uint32_t rsvd0:10; 420 uint32_t iscsi_drv_loaded:1; 421 uint32_t option_rom_installed:1; 422 uint32_t iscsi_ip_conflict:1; 423 uint32_t iscsi_no_ip:1; 424 uint32_t backup_fw:1; 425 uint32_t error:1; 426 #endif 427 } bits; 428 } mpu_ep_semaphore_t; 429 430 431 432 433 typedef union mpu_ep_control_u { 434 uint32_t dw0; 435 struct { 436 #ifdef _BIG_ENDIAN 437 uint32_t cpu_reset:1; 438 uint32_t rsvd1:15; 439 uint32_t ep_ram_init_status:1; 440 uint32_t rsvd0:12; 441 uint32_t m2_rxpbuf:1; 442 uint32_t m1_rxpbuf:1; 443 uint32_t m0_rxpbuf:1; 444 #else 445 uint32_t m0_rxpbuf:1; 446 uint32_t m1_rxpbuf:1; 447 uint32_t m2_rxpbuf:1; 448 uint32_t rsvd0:12; 449 uint32_t ep_ram_init_status:1; 450 uint32_t rsvd1:15; 451 uint32_t cpu_reset:1; 452 #endif 453 } bits; 454 } mpu_ep_control_t; 455 456 457 458 459 /* RX doorbell */ 460 typedef union pd_rxulp_db_u { 461 uint32_t dw0; 462 struct { 463 #ifdef _BIG_ENDIAN 464 uint32_t num_posted:8; 465 uint32_t invalidate:1; 466 uint32_t rsvd1:13; 467 uint32_t qid:10; 468 #else 469 uint32_t qid:10; 470 uint32_t rsvd1:13; 471 uint32_t invalidate:1; 472 uint32_t num_posted:8; 473 #endif 474 } bits; 475 } pd_rxulp_db_t; 476 477 478 /* TX doorbell */ 479 typedef union pd_txulp_db_u { 480 uint32_t dw0; 481 struct { 482 #ifdef _BIG_ENDIAN 483 uint32_t rsvd1:2; 484 uint32_t num_posted:14; 485 uint32_t rsvd0:6; 486 uint32_t qid:10; 487 #else 488 uint32_t qid:10; 489 uint32_t rsvd0:6; 490 uint32_t num_posted:14; 491 uint32_t rsvd1:2; 492 #endif 493 } bits; 494 } pd_txulp_db_t; 495 496 /* CQ doorbell */ 497 typedef union cq_db_u { 498 uint32_t dw0; 499 struct { 500 #ifdef _BIG_ENDIAN 501 uint32_t rsvd1:2; 502 uint32_t rearm:1; 503 uint32_t num_popped:13; 504 uint32_t rsvd0:5; 505 uint32_t event:1; 506 uint32_t qid:10; 507 #else 508 uint32_t qid:10; 509 uint32_t event:1; 510 uint32_t rsvd0:5; 511 uint32_t num_popped:13; 512 uint32_t rearm:1; 513 uint32_t rsvd1:2; 514 #endif 515 } bits; 516 } cq_db_t; 517 518 /* EQ doorbell */ 519 typedef union eq_db_u { 520 uint32_t dw0; 521 struct { 522 #ifdef _BIG_ENDIAN 523 uint32_t rsvd1:2; 524 uint32_t rearm:1; 525 uint32_t num_popped:13; 526 uint32_t rsvd0:5; 527 uint32_t event:1; 528 uint32_t clrint:1; 529 uint32_t qid:9; 530 #else 531 uint32_t qid:9; 532 uint32_t clrint:1; 533 uint32_t event:1; 534 uint32_t rsvd0:5; 535 uint32_t num_popped:13; 536 uint32_t rearm:1; 537 uint32_t rsvd1:2; 538 #endif 539 } bits; 540 } eq_db_t; 541 542 /* bootstrap mbox doorbell */ 543 typedef union pd_mpu_mbox_db_u { 544 uint32_t dw0; 545 struct { 546 #ifdef _BIG_ENDIAN 547 uint32_t address:30; 548 uint32_t hi:1; 549 uint32_t ready:1; 550 #else 551 uint32_t ready:1; 552 uint32_t hi:1; 553 uint32_t address:30; 554 #endif 555 } bits; 556 } pd_mpu_mbox_db_t; 557 558 /* MQ ring doorbell */ 559 typedef union pd_mq_db_u { 560 uint32_t dw0; 561 struct { 562 #ifdef _BIG_ENDIAN 563 uint32_t rsvd1:2; 564 uint32_t num_posted:14; 565 uint32_t rsvd0:5; 566 uint32_t mq_id:11; 567 #else 568 uint32_t mq_id:11; 569 uint32_t rsvd0:5; 570 uint32_t num_posted:14; 571 uint32_t rsvd1:2; 572 #endif 573 } bits; 574 } pd_mq_db_t; 575 576 /* 577 * Event Queue Entry 578 */ 579 struct oce_eqe { 580 uint32_t evnt; 581 }; 582 583 /* MQ scatter gather entry. Array of these make an SGL */ 584 struct oce_mq_sge { 585 uint32_t pa_lo; 586 uint32_t pa_hi; 587 uint32_t length; 588 }; 589 590 /* 591 * payload can contain an SGL or an embedded array of upto 59 dwords 592 */ 593 struct oce_mbx_payload { 594 union { 595 union { 596 struct oce_mq_sge sgl[MAX_MBX_SGE]; 597 uint32_t embedded[59]; 598 } u1; 599 uint32_t dw[59]; 600 } u0; 601 }; 602 603 /* 604 * MQ MBX structure 605 */ 606 struct oce_mbx { 607 union { 608 struct { 609 #ifdef _BIG_ENDIAN 610 uint32_t special:8; 611 uint32_t rsvd1:16; 612 uint32_t sge_count:5; 613 uint32_t rsvd0:2; 614 uint32_t embedded:1; 615 #else 616 uint32_t embedded:1; 617 uint32_t rsvd0:2; 618 uint32_t sge_count:5; 619 uint32_t rsvd1:16; 620 uint32_t special:8; 621 #endif 622 } s; 623 uint32_t dw0; 624 } u0; 625 626 uint32_t payload_length; 627 uint32_t tag[2]; 628 uint32_t rsvd2[1]; 629 struct oce_mbx_payload payload; 630 }; 631 632 /* completion queue entry for MQ */ 633 struct oce_mq_cqe { 634 union { 635 struct { 636 #ifdef _BIG_ENDIAN 637 /* dw0 */ 638 uint32_t extended_status:16; 639 uint32_t completion_status:16; 640 /* dw1 dw2 */ 641 uint32_t mq_tag[2]; 642 /* dw3 */ 643 uint32_t valid:1; 644 uint32_t async_event:1; 645 uint32_t hpi_buffer_cmpl:1; 646 uint32_t completed:1; 647 uint32_t consumed:1; 648 uint32_t rsvd0:3; 649 uint32_t async_type:8; 650 uint32_t event_type:8; 651 uint32_t rsvd1:8; 652 #else 653 /* dw0 */ 654 uint32_t completion_status:16; 655 uint32_t extended_status:16; 656 /* dw1 dw2 */ 657 uint32_t mq_tag[2]; 658 /* dw3 */ 659 uint32_t rsvd1:8; 660 uint32_t event_type:8; 661 uint32_t async_type:8; 662 uint32_t rsvd0:3; 663 uint32_t consumed:1; 664 uint32_t completed:1; 665 uint32_t hpi_buffer_cmpl:1; 666 uint32_t async_event:1; 667 uint32_t valid:1; 668 #endif 669 } s; 670 uint32_t dw[4]; 671 } u0; 672 }; 673 674 /* Mailbox Completion Status Codes */ 675 enum MBX_COMPLETION_STATUS { 676 MBX_CQE_STATUS_SUCCESS = 0x00, 677 MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 0x01, 678 MBX_CQE_STATUS_INVALID_PARAMETER = 0x02, 679 MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 0x03, 680 MBX_CQE_STATUS_QUEUE_FLUSHING = 0x04, 681 MBX_CQE_STATUS_DMA_FAILED = 0x05 682 }; 683 684 struct oce_async_cqe_link_state { 685 union { 686 struct { 687 #ifdef _BIG_ENDIAN 688 /* dw0 */ 689 uint8_t speed; 690 uint8_t duplex; 691 uint8_t link_status; 692 uint8_t phy_port; 693 /* dw1 */ 694 uint16_t qos_link_speed; 695 uint8_t rsvd0; 696 uint8_t fault; 697 /* dw2 */ 698 uint32_t event_tag; 699 /* dw3 */ 700 uint32_t valid:1; 701 uint32_t async_event:1; 702 uint32_t rsvd2:6; 703 uint32_t event_type:8; 704 uint32_t event_code:8; 705 uint32_t rsvd1:8; 706 #else 707 /* dw0 */ 708 uint8_t phy_port; 709 uint8_t link_status; 710 uint8_t duplex; 711 uint8_t speed; 712 /* dw1 */ 713 uint8_t fault; 714 uint8_t rsvd0; 715 uint16_t qos_link_speed; 716 /* dw2 */ 717 uint32_t event_tag; 718 /* dw3 */ 719 uint32_t rsvd1:8; 720 uint32_t event_code:8; 721 uint32_t event_type:8; 722 uint32_t rsvd2:6; 723 uint32_t async_event:1; 724 uint32_t valid:1; 725 #endif 726 } s; 727 uint32_t dw[4]; 728 } u0; 729 }; 730 731 /* OS2BMC async event */ 732 struct oce_async_evt_grp5_os2bmc { 733 union { 734 struct { 735 uint32_t lrn_enable:1; 736 uint32_t lrn_disable:1; 737 uint32_t mgmt_enable:1; 738 uint32_t mgmt_disable:1; 739 uint32_t rsvd0:12; 740 uint32_t vlan_tag:16; 741 uint32_t arp_filter:1; 742 uint32_t dhcp_client_filt:1; 743 uint32_t dhcp_server_filt:1; 744 uint32_t net_bios_filt:1; 745 uint32_t rsvd1:3; 746 uint32_t bcast_filt:1; 747 uint32_t ipv6_nbr_filt:1; 748 uint32_t ipv6_ra_filt:1; 749 uint32_t ipv6_ras_filt:1; 750 uint32_t rsvd2[4]; 751 uint32_t mcast_filt:1; 752 uint32_t rsvd3:16; 753 uint32_t evt_tag; 754 uint32_t dword3; 755 } s; 756 uint32_t dword[4]; 757 } u; 758 }; 759 760 /* PVID aync event */ 761 struct oce_async_event_grp5_pvid_state { 762 uint8_t enabled; 763 uint8_t rsvd0; 764 uint16_t tag; 765 uint32_t event_tag; 766 uint32_t rsvd1; 767 uint32_t code; 768 }; 769 770 /* async event indicating outer VLAN tag in QnQ */ 771 struct oce_async_event_qnq { 772 uint8_t valid; /* Indicates if outer VLAN is valid */ 773 uint8_t rsvd0; 774 uint16_t vlan_tag; 775 uint32_t event_tag; 776 uint8_t rsvd1[4]; 777 uint32_t code; 778 } ; 779 780 781 typedef union oce_mq_ext_ctx_u { 782 uint32_t dw[6]; 783 struct { 784 #ifdef _BIG_ENDIAN 785 /* dw0 */ 786 uint32_t dw4rsvd1:16; 787 uint32_t num_pages:16; 788 /* dw1 */ 789 uint32_t async_evt_bitmap; 790 /* dw2 */ 791 uint32_t cq_id:10; 792 uint32_t dw5rsvd2:2; 793 uint32_t ring_size:4; 794 uint32_t dw5rsvd1:16; 795 /* dw3 */ 796 uint32_t valid:1; 797 uint32_t dw6rsvd1:31; 798 /* dw4 */ 799 uint32_t dw7rsvd1:21; 800 uint32_t async_cq_id:10; 801 uint32_t async_cq_valid:1; 802 #else 803 /* dw0 */ 804 uint32_t num_pages:16; 805 uint32_t dw4rsvd1:16; 806 /* dw1 */ 807 uint32_t async_evt_bitmap; 808 /* dw2 */ 809 uint32_t dw5rsvd1:16; 810 uint32_t ring_size:4; 811 uint32_t dw5rsvd2:2; 812 uint32_t cq_id:10; 813 /* dw3 */ 814 uint32_t dw6rsvd1:31; 815 uint32_t valid:1; 816 /* dw4 */ 817 uint32_t async_cq_valid:1; 818 uint32_t async_cq_id:10; 819 uint32_t dw7rsvd1:21; 820 #endif 821 /* dw5 */ 822 uint32_t dw8rsvd1; 823 } v0; 824 struct { 825 #ifdef _BIG_ENDIAN 826 /* dw0 */ 827 uint32_t cq_id:16; 828 uint32_t num_pages:16; 829 /* dw1 */ 830 uint32_t async_evt_bitmap; 831 /* dw2 */ 832 uint32_t dw5rsvd2:12; 833 uint32_t ring_size:4; 834 uint32_t async_cq_id:16; 835 /* dw3 */ 836 uint32_t valid:1; 837 uint32_t dw6rsvd1:31; 838 /* dw4 */ 839 uint32_t dw7rsvd1:31; 840 uint32_t async_cq_valid:1; 841 #else 842 /* dw0 */ 843 uint32_t num_pages:16; 844 uint32_t cq_id:16; 845 /* dw1 */ 846 uint32_t async_evt_bitmap; 847 /* dw2 */ 848 uint32_t async_cq_id:16; 849 uint32_t ring_size:4; 850 uint32_t dw5rsvd2:12; 851 /* dw3 */ 852 uint32_t dw6rsvd1:31; 853 uint32_t valid:1; 854 /* dw4 */ 855 uint32_t async_cq_valid:1; 856 uint32_t dw7rsvd1:31; 857 #endif 858 /* dw5 */ 859 uint32_t dw8rsvd1; 860 } v1; 861 862 } oce_mq_ext_ctx_t; 863 864 865 /* MQ mailbox structure */ 866 struct oce_bmbx { 867 struct oce_mbx mbx; 868 struct oce_mq_cqe cqe; 869 }; 870 871 /* ---[ MBXs start here ]---------------------------------------------- */ 872 /* MBXs sub system codes */ 873 enum MBX_SUBSYSTEM_CODES { 874 MBX_SUBSYSTEM_RSVD = 0, 875 MBX_SUBSYSTEM_COMMON = 1, 876 MBX_SUBSYSTEM_COMMON_ISCSI = 2, 877 MBX_SUBSYSTEM_NIC = 3, 878 MBX_SUBSYSTEM_TOE = 4, 879 MBX_SUBSYSTEM_PXE_UNDI = 5, 880 MBX_SUBSYSTEM_ISCSI_INI = 6, 881 MBX_SUBSYSTEM_ISCSI_TGT = 7, 882 MBX_SUBSYSTEM_MILI_PTL = 8, 883 MBX_SUBSYSTEM_MILI_TMD = 9, 884 MBX_SUBSYSTEM_RDMA = 10, 885 MBX_SUBSYSTEM_LOWLEVEL = 11, 886 MBX_SUBSYSTEM_LRO = 13, 887 IOCBMBX_SUBSYSTEM_DCBX = 15, 888 IOCBMBX_SUBSYSTEM_DIAG = 16, 889 IOCBMBX_SUBSYSTEM_VENDOR = 17 890 }; 891 892 /* common ioctl opcodes */ 893 enum COMMON_SUBSYSTEM_OPCODES { 894 /* These opcodes are common to both networking and storage PCI functions 895 * They are used to reserve resources and configure CNA. These opcodes 896 * all use the MBX_SUBSYSTEM_COMMON subsystem code. 897 */ 898 OPCODE_COMMON_QUERY_IFACE_MAC = 1, 899 OPCODE_COMMON_SET_IFACE_MAC = 2, 900 OPCODE_COMMON_SET_IFACE_MULTICAST = 3, 901 OPCODE_COMMON_CONFIG_IFACE_VLAN = 4, 902 OPCODE_COMMON_QUERY_LINK_CONFIG = 5, 903 OPCODE_COMMON_READ_FLASHROM = 6, 904 OPCODE_COMMON_WRITE_FLASHROM = 7, 905 OPCODE_COMMON_QUERY_MAX_MBX_BUFFER_SIZE = 8, 906 OPCODE_COMMON_CREATE_CQ = 12, 907 OPCODE_COMMON_CREATE_EQ = 13, 908 OPCODE_COMMON_CREATE_MQ = 21, 909 OPCODE_COMMON_GET_QOS = 27, 910 OPCODE_COMMON_SET_QOS = 28, 911 OPCODE_COMMON_READ_EPROM = 30, 912 OPCODE_COMMON_GET_CNTL_ATTRIBUTES = 32, 913 OPCODE_COMMON_NOP = 33, 914 OPCODE_COMMON_SET_IFACE_RX_FILTER = 34, 915 OPCODE_COMMON_GET_FW_VERSION = 35, 916 OPCODE_COMMON_SET_FLOW_CONTROL = 36, 917 OPCODE_COMMON_GET_FLOW_CONTROL = 37, 918 OPCODE_COMMON_SET_FRAME_SIZE = 39, 919 OPCODE_COMMON_MODIFY_EQ_DELAY = 41, 920 OPCODE_COMMON_CREATE_IFACE = 50, 921 OPCODE_COMMON_DESTROY_IFACE = 51, 922 OPCODE_COMMON_MODIFY_MSI_MESSAGES = 52, 923 OPCODE_COMMON_DESTROY_MQ = 53, 924 OPCODE_COMMON_DESTROY_CQ = 54, 925 OPCODE_COMMON_DESTROY_EQ = 55, 926 OPCODE_COMMON_UPLOAD_TCP = 56, 927 OPCODE_COMMON_SET_NTWK_LINK_SPEED = 57, 928 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG = 58, 929 OPCODE_COMMON_ADD_IFACE_MAC = 59, 930 OPCODE_COMMON_DEL_IFACE_MAC = 60, 931 OPCODE_COMMON_FUNCTION_RESET = 61, 932 OPCODE_COMMON_SET_PHYSICAL_LINK_CONFIG = 62, 933 OPCODE_COMMON_GET_BOOT_CONFIG = 66, 934 OPCPDE_COMMON_SET_BOOT_CONFIG = 67, 935 OPCODE_COMMON_SET_BEACON_CONFIG = 69, 936 OPCODE_COMMON_GET_BEACON_CONFIG = 70, 937 OPCODE_COMMON_GET_PHYSICAL_LINK_CONFIG = 71, 938 OPCODE_COMMON_READ_TRANSRECEIVER_DATA = 73, 939 OPCODE_COMMON_GET_OEM_ATTRIBUTES = 76, 940 OPCODE_COMMON_GET_PORT_NAME = 77, 941 OPCODE_COMMON_GET_CONFIG_SIGNATURE = 78, 942 OPCODE_COMMON_SET_CONFIG_SIGNATURE = 79, 943 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG = 80, 944 OPCODE_COMMON_GET_BE_CONFIGURATION_RESOURCES = 81, 945 OPCODE_COMMON_SET_BE_CONFIGURATION_RESOURCES = 82, 946 OPCODE_COMMON_GET_RESET_NEEDED = 84, 947 OPCODE_COMMON_GET_SERIAL_NUMBER = 85, 948 OPCODE_COMMON_GET_NCSI_CONFIG = 86, 949 OPCODE_COMMON_SET_NCSI_CONFIG = 87, 950 OPCODE_COMMON_CREATE_MQ_EXT = 90, 951 OPCODE_COMMON_SET_FUNCTION_PRIVILEGES = 100, 952 OPCODE_COMMON_SET_VF_PORT_TYPE = 101, 953 OPCODE_COMMON_GET_PHY_CONFIG = 102, 954 OPCODE_COMMON_SET_FUNCTIONAL_CAPS = 103, 955 OPCODE_COMMON_GET_ADAPTER_ID = 110, 956 OPCODE_COMMON_GET_UPGRADE_FEATURES = 111, 957 OPCODE_COMMON_GET_INSTALLED_FEATURES = 112, 958 OPCODE_COMMON_GET_AVAIL_PERSONALITIES = 113, 959 OPCODE_COMMON_GET_CONFIG_PERSONALITIES = 114, 960 OPCODE_COMMON_SEND_ACTIVATION = 115, 961 OPCODE_COMMON_RESET_LICENSES = 116, 962 OPCODE_COMMON_GET_CNTL_ADDL_ATTRIBUTES = 121, 963 OPCODE_COMMON_QUERY_TCB = 144, 964 OPCODE_COMMON_ADD_IFACE_QUEUE_FILTER = 145, 965 OPCODE_COMMON_DEL_IFACE_QUEUE_FILTER = 146, 966 OPCODE_COMMON_GET_IFACE_MAC_LIST = 147, 967 OPCODE_COMMON_SET_IFACE_MAC_LIST = 148, 968 OPCODE_COMMON_MODIFY_CQ = 149, 969 OPCODE_COMMON_GET_IFACE_VLAN_LIST = 150, 970 OPCODE_COMMON_SET_IFACE_VLAN_LIST = 151, 971 OPCODE_COMMON_GET_HSW_CONFIG = 152, 972 OPCODE_COMMON_SET_HSW_CONFIG = 153, 973 OPCODE_COMMON_GET_RESOURCE_EXTENT_INFO = 154, 974 OPCODE_COMMON_GET_ALLOCATED_RESOURCE_EXTENTS = 155, 975 OPCODE_COMMON_ALLOC_RESOURCE_EXTENTS = 156, 976 OPCODE_COMMON_DEALLOC_RESOURCE_EXTENTS = 157, 977 OPCODE_COMMON_SET_DIAG_REGISTERS = 158, 978 OPCODE_COMMON_GET_FUNCTION_CONFIG = 160, 979 OPCODE_COMMON_GET_PROFILE_CAPACITIES = 161, 980 OPCODE_COMMON_GET_MR_PROFILE_CAPACITIES = 162, 981 OPCODE_COMMON_SET_MR_PROFILE_CAPACITIES = 163, 982 OPCODE_COMMON_GET_PROFILE_CONFIG = 164, 983 OPCODE_COMMON_SET_PROFILE_CONFIG = 165, 984 OPCODE_COMMON_GET_PROFILE_LIST = 166, 985 OPCODE_COMMON_GET_ACTIVE_PROFILE = 167, 986 OPCODE_COMMON_SET_ACTIVE_PROFILE = 168, 987 OPCODE_COMMON_GET_FUNCTION_PRIVILEGES = 170, 988 OPCODE_COMMON_READ_OBJECT = 171, 989 OPCODE_COMMON_WRITE_OBJECT = 172 990 }; 991 992 /* common ioctl header */ 993 #define OCE_MBX_VER_V2 0x0002 /* Version V2 mailbox command */ 994 #define OCE_MBX_VER_V1 0x0001 /* Version V1 mailbox command */ 995 #define OCE_MBX_VER_V0 0x0000 /* Version V0 mailbox command */ 996 struct mbx_hdr { 997 union { 998 uint32_t dw[4]; 999 struct { 1000 #ifdef _BIG_ENDIAN 1001 /* dw 0 */ 1002 uint32_t domain:8; 1003 uint32_t port_number:8; 1004 uint32_t subsystem:8; 1005 uint32_t opcode:8; 1006 /* dw 1 */ 1007 uint32_t timeout; 1008 /* dw 2 */ 1009 uint32_t request_length; 1010 /* dw 3 */ 1011 uint32_t rsvd0:24; 1012 uint32_t version:8; 1013 #else 1014 /* dw 0 */ 1015 uint32_t opcode:8; 1016 uint32_t subsystem:8; 1017 uint32_t port_number:8; 1018 uint32_t domain:8; 1019 /* dw 1 */ 1020 uint32_t timeout; 1021 /* dw 2 */ 1022 uint32_t request_length; 1023 /* dw 3 */ 1024 uint32_t version:8; 1025 uint32_t rsvd0:24; 1026 #endif 1027 } req; 1028 struct { 1029 #ifdef _BIG_ENDIAN 1030 /* dw 0 */ 1031 uint32_t domain:8; 1032 uint32_t rsvd0:8; 1033 uint32_t subsystem:8; 1034 uint32_t opcode:8; 1035 /* dw 1 */ 1036 uint32_t rsvd1:16; 1037 uint32_t additional_status:8; 1038 uint32_t status:8; 1039 #else 1040 /* dw 0 */ 1041 uint32_t opcode:8; 1042 uint32_t subsystem:8; 1043 uint32_t rsvd0:8; 1044 uint32_t domain:8; 1045 /* dw 1 */ 1046 uint32_t status:8; 1047 uint32_t additional_status:8; 1048 uint32_t rsvd1:16; 1049 #endif 1050 uint32_t rsp_length; 1051 uint32_t actual_rsp_length; 1052 } rsp; 1053 } u0; 1054 }; 1055 #define OCE_BMBX_RHDR_SZ 20 1056 #define OCE_MBX_RRHDR_SZ sizeof (struct mbx_hdr) 1057 #define OCE_MBX_ADDL_STATUS(_MHDR) ((_MHDR)->u0.rsp.additional_status) 1058 #define OCE_MBX_STATUS(_MHDR) ((_MHDR)->u0.rsp.status) 1059 1060 /* [05] OPCODE_COMMON_QUERY_LINK_CONFIG_V1 */ 1061 struct mbx_query_common_link_config { 1062 struct mbx_hdr hdr; 1063 union { 1064 struct { 1065 uint32_t rsvd0; 1066 } req; 1067 1068 struct { 1069 #ifdef _BIG_ENDIAN 1070 uint32_t physical_port_fault:8; 1071 uint32_t physical_port_speed:8; 1072 uint32_t link_duplex:8; 1073 uint32_t pt:2; 1074 uint32_t port_number:6; 1075 1076 uint16_t qos_link_speed; 1077 uint16_t rsvd0; 1078 1079 uint32_t rsvd1:21; 1080 uint32_t phys_fcv:1; 1081 uint32_t phys_rxf:1; 1082 uint32_t phys_txf:1; 1083 uint32_t logical_link_status:8; 1084 #else 1085 uint32_t port_number:6; 1086 uint32_t pt:2; 1087 uint32_t link_duplex:8; 1088 uint32_t physical_port_speed:8; 1089 uint32_t physical_port_fault:8; 1090 1091 uint16_t rsvd0; 1092 uint16_t qos_link_speed; 1093 1094 uint32_t logical_link_status:8; 1095 uint32_t phys_txf:1; 1096 uint32_t phys_rxf:1; 1097 uint32_t phys_fcv:1; 1098 uint32_t rsvd1:21; 1099 #endif 1100 } rsp; 1101 } params; 1102 }; 1103 1104 /* [57] OPCODE_COMMON_SET_LINK_SPEED */ 1105 struct mbx_set_common_link_speed { 1106 struct mbx_hdr hdr; 1107 union { 1108 struct { 1109 #ifdef _BIG_ENDIAN 1110 uint8_t rsvd0; 1111 uint8_t mac_speed; 1112 uint8_t virtual_port; 1113 uint8_t physical_port; 1114 #else 1115 uint8_t physical_port; 1116 uint8_t virtual_port; 1117 uint8_t mac_speed; 1118 uint8_t rsvd0; 1119 #endif 1120 } req; 1121 1122 struct { 1123 uint32_t rsvd0; 1124 } rsp; 1125 1126 uint32_t dw; 1127 } params; 1128 }; 1129 1130 struct mac_address_format { 1131 uint16_t size_of_struct; 1132 uint8_t mac_addr[6]; 1133 }; 1134 1135 /* [01] OPCODE_COMMON_QUERY_IFACE_MAC */ 1136 struct mbx_query_common_iface_mac { 1137 struct mbx_hdr hdr; 1138 union { 1139 struct { 1140 #ifdef _BIG_ENDIAN 1141 uint16_t if_id; 1142 uint8_t permanent; 1143 uint8_t type; 1144 #else 1145 uint8_t type; 1146 uint8_t permanent; 1147 uint16_t if_id; 1148 #endif 1149 1150 } req; 1151 1152 struct { 1153 struct mac_address_format mac; 1154 } rsp; 1155 } params; 1156 }; 1157 1158 /* [02] OPCODE_COMMON_SET_IFACE_MAC */ 1159 struct mbx_set_common_iface_mac { 1160 struct mbx_hdr hdr; 1161 union { 1162 struct { 1163 #ifdef _BIG_ENDIAN 1164 /* dw 0 */ 1165 uint16_t if_id; 1166 uint8_t invalidate; 1167 uint8_t type; 1168 #else 1169 /* dw 0 */ 1170 uint8_t type; 1171 uint8_t invalidate; 1172 uint16_t if_id; 1173 #endif 1174 /* dw 1 */ 1175 struct mac_address_format mac; 1176 } req; 1177 1178 struct { 1179 uint32_t rsvd0; 1180 } rsp; 1181 1182 uint32_t dw[2]; 1183 } params; 1184 }; 1185 1186 /* [03] OPCODE_COMMON_SET_IFACE_MULTICAST */ 1187 struct mbx_set_common_iface_multicast { 1188 struct mbx_hdr hdr; 1189 union { 1190 struct { 1191 /* dw 0 */ 1192 uint16_t num_mac; 1193 uint8_t promiscuous; 1194 uint8_t if_id; 1195 /* dw 1-48 */ 1196 struct { 1197 uint8_t byte[6]; 1198 } mac[32]; 1199 1200 } req; 1201 1202 struct { 1203 uint32_t rsvd0; 1204 } rsp; 1205 1206 uint32_t dw[49]; 1207 } params; 1208 }; 1209 1210 struct qinq_vlan { 1211 #ifdef _BIG_ENDIAN 1212 uint16_t inner; 1213 uint16_t outer; 1214 #else 1215 uint16_t outer; 1216 uint16_t inner; 1217 #endif 1218 }; 1219 1220 struct normal_vlan { 1221 uint16_t vtag; 1222 }; 1223 1224 struct ntwk_if_vlan_tag { 1225 union { 1226 struct normal_vlan normal; 1227 struct qinq_vlan qinq; 1228 } u0; 1229 }; 1230 1231 /* [50] OPCODE_COMMON_CREATE_IFACE */ 1232 struct mbx_create_common_iface { 1233 struct mbx_hdr hdr; 1234 union { 1235 struct { 1236 uint32_t version; 1237 uint32_t cap_flags; 1238 uint32_t enable_flags; 1239 uint8_t mac_addr[6]; 1240 uint8_t rsvd0; 1241 uint8_t mac_invalid; 1242 struct ntwk_if_vlan_tag vlan_tag; 1243 } req; 1244 1245 struct { 1246 uint32_t if_id; 1247 uint32_t pmac_id; 1248 } rsp; 1249 uint32_t dw[4]; 1250 } params; 1251 }; 1252 1253 /* [51] OPCODE_COMMON_DESTROY_IFACE */ 1254 struct mbx_destroy_common_iface { 1255 struct mbx_hdr hdr; 1256 union { 1257 struct { 1258 uint32_t if_id; 1259 } req; 1260 1261 struct { 1262 uint32_t rsvd0; 1263 } rsp; 1264 1265 uint32_t dw; 1266 } params; 1267 }; 1268 1269 /* event queue context structure */ 1270 struct oce_eq_ctx { 1271 #ifdef _BIG_ENDIAN 1272 uint32_t dw4rsvd1:16; 1273 uint32_t num_pages:16; 1274 1275 uint32_t size:1; 1276 uint32_t dw5rsvd2:1; 1277 uint32_t valid:1; 1278 uint32_t dw5rsvd1:29; 1279 1280 uint32_t armed:1; 1281 uint32_t dw6rsvd2:2; 1282 uint32_t count:3; 1283 uint32_t dw6rsvd1:26; 1284 1285 uint32_t dw7rsvd2:9; 1286 uint32_t delay_mult:10; 1287 uint32_t dw7rsvd1:13; 1288 1289 uint32_t dw8rsvd1; 1290 #else 1291 uint32_t num_pages:16; 1292 uint32_t dw4rsvd1:16; 1293 1294 uint32_t dw5rsvd1:29; 1295 uint32_t valid:1; 1296 uint32_t dw5rsvd2:1; 1297 uint32_t size:1; 1298 1299 uint32_t dw6rsvd1:26; 1300 uint32_t count:3; 1301 uint32_t dw6rsvd2:2; 1302 uint32_t armed:1; 1303 1304 uint32_t dw7rsvd1:13; 1305 uint32_t delay_mult:10; 1306 uint32_t dw7rsvd2:9; 1307 1308 uint32_t dw8rsvd1; 1309 #endif 1310 }; 1311 1312 /* [13] OPCODE_COMMON_CREATE_EQ */ 1313 struct mbx_create_common_eq { 1314 struct mbx_hdr hdr; 1315 union { 1316 struct { 1317 struct oce_eq_ctx ctx; 1318 struct phys_addr pages[8]; 1319 } req; 1320 1321 struct { 1322 uint16_t eq_id; 1323 uint16_t rsvd0; 1324 } rsp; 1325 } params; 1326 }; 1327 1328 /* [55] OPCODE_COMMON_DESTROY_EQ */ 1329 struct mbx_destroy_common_eq { 1330 struct mbx_hdr hdr; 1331 union { 1332 struct { 1333 #ifdef _BIG_ENDIAN 1334 uint16_t rsvd0; 1335 uint16_t id; 1336 #else 1337 uint16_t id; 1338 uint16_t rsvd0; 1339 #endif 1340 } req; 1341 1342 struct { 1343 uint32_t rsvd0; 1344 } rsp; 1345 } params; 1346 }; 1347 1348 /* SLI-4 CQ context - use version V0 for B3, version V2 for Lancer */ 1349 typedef union oce_cq_ctx_u { 1350 uint32_t dw[5]; 1351 struct { 1352 #ifdef _BIG_ENDIAN 1353 /* dw4 */ 1354 uint32_t dw4rsvd1:16; 1355 uint32_t num_pages:16; 1356 /* dw5 */ 1357 uint32_t eventable:1; 1358 uint32_t dw5rsvd3:1; 1359 uint32_t valid:1; 1360 uint32_t count:2; 1361 uint32_t dw5rsvd2:12; 1362 uint32_t nodelay:1; 1363 uint32_t coalesce_wm:2; 1364 uint32_t dw5rsvd1:12; 1365 /* dw6 */ 1366 uint32_t armed:1; 1367 uint32_t dw6rsvd2:1; 1368 uint32_t eq_id:8; 1369 uint32_t dw6rsvd1:22; 1370 #else 1371 /* dw4 */ 1372 uint32_t num_pages:16; 1373 uint32_t dw4rsvd1:16; 1374 /* dw5 */ 1375 uint32_t dw5rsvd1:12; 1376 uint32_t coalesce_wm:2; 1377 uint32_t nodelay:1; 1378 uint32_t dw5rsvd2:12; 1379 uint32_t count:2; 1380 uint32_t valid:1; 1381 uint32_t dw5rsvd3:1; 1382 uint32_t eventable:1; 1383 /* dw6 */ 1384 uint32_t dw6rsvd1:22; 1385 uint32_t eq_id:8; 1386 uint32_t dw6rsvd2:1; 1387 uint32_t armed:1; 1388 #endif 1389 /* dw7 */ 1390 uint32_t dw7rsvd1; 1391 /* dw8 */ 1392 uint32_t dw8rsvd1; 1393 } v0; 1394 struct { 1395 #ifdef _BIG_ENDIAN 1396 /* dw4 */ 1397 uint32_t dw4rsvd1:8; 1398 uint32_t page_size:8; 1399 uint32_t num_pages:16; 1400 /* dw5 */ 1401 uint32_t eventable:1; 1402 uint32_t dw5rsvd3:1; 1403 uint32_t valid:1; 1404 uint32_t count:2; 1405 uint32_t dw5rsvd2:11; 1406 uint32_t autovalid:1; 1407 uint32_t nodelay:1; 1408 uint32_t coalesce_wm:2; 1409 uint32_t dw5rsvd1:12; 1410 /* dw6 */ 1411 uint32_t armed:1; 1412 uint32_t dw6rsvd1:15; 1413 uint32_t eq_id:16; 1414 /* dw7 */ 1415 uint32_t dw7rsvd1:16; 1416 uint32_t cqe_count:16; 1417 #else 1418 /* dw4 */ 1419 uint32_t num_pages:16; 1420 uint32_t page_size:8; 1421 uint32_t dw4rsvd1:8; 1422 /* dw5 */ 1423 uint32_t dw5rsvd1:12; 1424 uint32_t coalesce_wm:2; 1425 uint32_t nodelay:1; 1426 uint32_t autovalid:1; 1427 uint32_t dw5rsvd2:11; 1428 uint32_t count:2; 1429 uint32_t valid:1; 1430 uint32_t dw5rsvd3:1; 1431 uint32_t eventable:1; 1432 /* dw6 */ 1433 uint32_t eq_id:16; 1434 uint32_t dw6rsvd1:15; 1435 uint32_t armed:1; 1436 /* dw7 */ 1437 uint32_t cqe_count:16; 1438 uint32_t dw7rsvd1:16; 1439 #endif 1440 /* dw8 */ 1441 uint32_t dw8rsvd1; 1442 } v2; 1443 } oce_cq_ctx_t; 1444 1445 /* [12] OPCODE_COMMON_CREATE_CQ */ 1446 struct mbx_create_common_cq { 1447 struct mbx_hdr hdr; 1448 union { 1449 struct { 1450 oce_cq_ctx_t cq_ctx; 1451 struct phys_addr pages[4]; 1452 } req; 1453 1454 struct { 1455 uint16_t cq_id; 1456 uint16_t rsvd0; 1457 } rsp; 1458 } params; 1459 }; 1460 1461 /* [54] OPCODE_COMMON_DESTROY_CQ */ 1462 struct mbx_destroy_common_cq { 1463 struct mbx_hdr hdr; 1464 union { 1465 struct { 1466 #ifdef _BIG_ENDIAN 1467 uint16_t rsvd0; 1468 uint16_t id; 1469 #else 1470 uint16_t id; 1471 uint16_t rsvd0; 1472 #endif 1473 } req; 1474 1475 struct { 1476 uint32_t rsvd0; 1477 } rsp; 1478 } params; 1479 }; 1480 1481 typedef union oce_mq_ctx_u { 1482 uint32_t dw[5]; 1483 struct { 1484 #ifdef _BIG_ENDIAN 1485 /* dw4 */ 1486 uint32_t dw4rsvd1:16; 1487 uint32_t num_pages:16; 1488 /* dw5 */ 1489 uint32_t cq_id:10; 1490 uint32_t dw5rsvd2:2; 1491 uint32_t ring_size:4; 1492 uint32_t dw5rsvd1:16; 1493 /* dw6 */ 1494 uint32_t valid:1; 1495 uint32_t dw6rsvd1:31; 1496 /* dw7 */ 1497 uint32_t dw7rsvd1:21; 1498 uint32_t async_cq_id:10; 1499 uint32_t async_cq_valid:1; 1500 #else 1501 /* dw4 */ 1502 uint32_t num_pages:16; 1503 uint32_t dw4rsvd1:16; 1504 /* dw5 */ 1505 uint32_t dw5rsvd1:16; 1506 uint32_t ring_size:4; 1507 uint32_t dw5rsvd2:2; 1508 uint32_t cq_id:10; 1509 /* dw6 */ 1510 uint32_t dw6rsvd1:31; 1511 uint32_t valid:1; 1512 /* dw7 */ 1513 uint32_t async_cq_valid:1; 1514 uint32_t async_cq_id:10; 1515 uint32_t dw7rsvd1:21; 1516 #endif 1517 /* dw8 */ 1518 uint32_t dw8rsvd1; 1519 } v0; 1520 } oce_mq_ctx_t; 1521 1522 /** 1523 * @brief [21] OPCODE_COMMON_CREATE_MQ 1524 * A MQ must be at least 16 entries deep (corresponding to 1 page) and 1525 * at most 128 entries deep (corresponding to 8 pages). 1526 */ 1527 struct mbx_create_common_mq { 1528 struct mbx_hdr hdr; 1529 union { 1530 struct { 1531 oce_mq_ctx_t context; 1532 struct phys_addr pages[8]; 1533 } req; 1534 1535 struct { 1536 uint32_t mq_id:16; 1537 uint32_t rsvd0:16; 1538 } rsp; 1539 } params; 1540 }; 1541 1542 struct mbx_create_common_mq_ex { 1543 struct mbx_hdr hdr; 1544 union { 1545 struct { 1546 oce_mq_ext_ctx_t context; 1547 struct phys_addr pages[8]; 1548 } req; 1549 1550 struct { 1551 uint32_t mq_id:16; 1552 uint32_t rsvd0:16; 1553 } rsp; 1554 } params; 1555 }; 1556 1557 1558 1559 /* [53] OPCODE_COMMON_DESTROY_MQ */ 1560 struct mbx_destroy_common_mq { 1561 struct mbx_hdr hdr; 1562 union { 1563 struct { 1564 #ifdef _BIG_ENDIAN 1565 uint16_t rsvd0; 1566 uint16_t id; 1567 #else 1568 uint16_t id; 1569 uint16_t rsvd0; 1570 #endif 1571 } req; 1572 1573 struct { 1574 uint32_t rsvd0; 1575 } rsp; 1576 } params; 1577 }; 1578 1579 /* [35] OPCODE_COMMON_GET_ FW_VERSION */ 1580 struct mbx_get_common_fw_version { 1581 struct mbx_hdr hdr; 1582 union { 1583 struct { 1584 uint32_t rsvd0; 1585 } req; 1586 1587 struct { 1588 uint8_t fw_ver_str[32]; 1589 uint8_t fw_on_flash_ver_str[32]; 1590 } rsp; 1591 } params; 1592 }; 1593 1594 /* [52] OPCODE_COMMON_CEV_MODIFY_MSI_MESSAGES */ 1595 struct mbx_common_cev_modify_msi_messages { 1596 struct mbx_hdr hdr; 1597 union { 1598 struct { 1599 uint32_t num_msi_msgs; 1600 } req; 1601 1602 struct { 1603 uint32_t rsvd0; 1604 } rsp; 1605 } params; 1606 }; 1607 1608 /* [36] OPCODE_COMMON_SET_FLOW_CONTROL */ 1609 /* [37] OPCODE_COMMON_GET_FLOW_CONTROL */ 1610 struct mbx_common_get_set_flow_control { 1611 struct mbx_hdr hdr; 1612 #ifdef _BIG_ENDIAN 1613 uint16_t tx_flow_control; 1614 uint16_t rx_flow_control; 1615 #else 1616 uint16_t rx_flow_control; 1617 uint16_t tx_flow_control; 1618 #endif 1619 }; 1620 1621 enum e_flash_opcode { 1622 MGMT_FLASHROM_OPCODE_FLASH = 1, 1623 MGMT_FLASHROM_OPCODE_SAVE = 2 1624 }; 1625 1626 /* [06] OPCODE_READ_COMMON_FLASHROM */ 1627 /* [07] OPCODE_WRITE_COMMON_FLASHROM */ 1628 1629 struct mbx_common_read_write_flashrom { 1630 struct mbx_hdr hdr; 1631 uint32_t flash_op_code; 1632 uint32_t flash_op_type; 1633 uint32_t data_buffer_size; 1634 uint32_t data_offset; 1635 uint8_t data_buffer[32768]; /* + IMAGE_TRANSFER_SIZE */ 1636 uint8_t rsvd[4]; 1637 }; 1638 1639 struct oce_phy_info { 1640 uint16_t phy_type; 1641 uint16_t interface_type; 1642 uint32_t misc_params; 1643 uint16_t ext_phy_details; 1644 uint16_t rsvd; 1645 uint16_t auto_speeds_supported; 1646 uint16_t fixed_speeds_supported; 1647 uint32_t future_use[2]; 1648 }; 1649 1650 struct mbx_common_phy_info { 1651 struct mbx_hdr hdr; 1652 union { 1653 struct { 1654 uint32_t rsvd0[4]; 1655 } req; 1656 struct { 1657 struct oce_phy_info phy_info; 1658 } rsp; 1659 } params; 1660 }; 1661 1662 /*Lancer firmware*/ 1663 1664 struct mbx_lancer_common_write_object { 1665 union { 1666 struct { 1667 struct mbx_hdr hdr; 1668 uint32_t write_length: 24; 1669 uint32_t rsvd: 7; 1670 uint32_t eof: 1; 1671 uint32_t write_offset; 1672 uint8_t object_name[104]; 1673 uint32_t descriptor_count; 1674 uint32_t buffer_length; 1675 uint32_t address_lower; 1676 uint32_t address_upper; 1677 } req; 1678 struct { 1679 uint8_t opcode; 1680 uint8_t subsystem; 1681 uint8_t rsvd1[2]; 1682 uint8_t status; 1683 uint8_t additional_status; 1684 uint8_t rsvd2[2]; 1685 uint32_t response_length; 1686 uint32_t actual_response_length; 1687 uint32_t actual_write_length; 1688 } rsp; 1689 } params; 1690 }; 1691 1692 /** 1693 * @brief MBX Common Quiery Firmaware Config 1694 * This command retrieves firmware configuration parameters and adapter 1695 * resources available to the driver originating the request. The firmware 1696 * configuration defines supported protocols by the installed adapter firmware. 1697 * This includes which ULP processors support the specified protocols and 1698 * the number of TCP connections allowed for that protocol. 1699 */ 1700 struct mbx_common_query_fw_config { 1701 struct mbx_hdr hdr; 1702 union { 1703 struct { 1704 uint32_t rsvd0[30]; 1705 } req; 1706 1707 struct { 1708 uint32_t config_number; 1709 uint32_t asic_revision; 1710 uint32_t port_id; /* used for stats retrieval */ 1711 uint32_t function_mode; 1712 struct { 1713 1714 uint32_t ulp_mode; 1715 uint32_t nic_wqid_base; 1716 uint32_t nic_wq_tot; 1717 uint32_t toe_wqid_base; 1718 uint32_t toe_wq_tot; 1719 uint32_t toe_rqid_base; 1720 uint32_t toe_rqid_tot; 1721 uint32_t toe_defrqid_base; 1722 uint32_t toe_defrqid_count; 1723 uint32_t lro_rqid_base; 1724 uint32_t lro_rqid_tot; 1725 uint32_t iscsi_icd_base; 1726 uint32_t iscsi_icd_count; 1727 } ulp[2]; 1728 uint32_t function_caps; 1729 uint32_t cqid_base; 1730 uint32_t cqid_tot; 1731 uint32_t eqid_base; 1732 uint32_t eqid_tot; 1733 } rsp; 1734 } params; 1735 }; 1736 1737 enum CQFW_CONFIG_NUMBER { 1738 FCN_NIC_ISCSI_Initiator = 0x0, 1739 FCN_ISCSI_Target = 0x3, 1740 FCN_FCoE = 0x7, 1741 FCN_ISCSI_Initiator_Target = 0x9, 1742 FCN_NIC_RDMA_TOE = 0xA, 1743 FCN_NIC_RDMA_FCoE = 0xB, 1744 FCN_NIC_RDMA_iSCSI = 0xC, 1745 FCN_NIC_iSCSI_FCoE = 0xD 1746 }; 1747 1748 /** 1749 * @brief Function Capabilites 1750 * This field contains the flags indicating the capabilities of 1751 * the SLI Host’s PCI function. 1752 */ 1753 enum CQFW_FUNCTION_CAPABILITIES { 1754 FNC_UNCLASSIFIED_STATS = 0x1, 1755 FNC_RSS = 0x2, 1756 FNC_PROMISCUOUS = 0x4, 1757 FNC_LEGACY_MODE = 0x8, 1758 FNC_HDS = 0x4000, 1759 FNC_VMQ = 0x10000, 1760 FNC_NETQ = 0x20000, 1761 FNC_QGROUPS = 0x40000, 1762 FNC_LRO = 0x100000, 1763 FNC_VLAN_OFFLOAD = 0x800000 1764 }; 1765 1766 enum CQFW_ULP_MODES_SUPPORTED { 1767 ULP_TOE_MODE = 0x1, 1768 ULP_NIC_MODE = 0x2, 1769 ULP_RDMA_MODE = 0x4, 1770 ULP_ISCSI_INI_MODE = 0x10, 1771 ULP_ISCSI_TGT_MODE = 0x20, 1772 ULP_FCOE_INI_MODE = 0x40, 1773 ULP_FCOE_TGT_MODE = 0x80, 1774 ULP_DAL_MODE = 0x100, 1775 ULP_LRO_MODE = 0x200 1776 }; 1777 1778 /** 1779 * @brief Function Modes Supported 1780 * Valid function modes (or protocol-types) supported on the SLI-Host’s 1781 * PCIe function. This field is a logical OR of the following values: 1782 */ 1783 enum CQFW_FUNCTION_MODES_SUPPORTED { 1784 FNM_TOE_MODE = 0x1, /* TCP offload supported */ 1785 FNM_NIC_MODE = 0x2, /* Raw Ethernet supported */ 1786 FNM_RDMA_MODE = 0x4, /* RDMA protocol supported */ 1787 FNM_VM_MODE = 0x8, /* Virtual Machines supported */ 1788 FNM_ISCSI_INI_MODE = 0x10, /* iSCSI initiator supported */ 1789 FNM_ISCSI_TGT_MODE = 0x20, /* iSCSI target plus initiator */ 1790 FNM_FCOE_INI_MODE = 0x40, /* FCoE Initiator supported */ 1791 FNM_FCOE_TGT_MODE = 0x80, /* FCoE target supported */ 1792 FNM_DAL_MODE = 0x100, /* DAL supported */ 1793 FNM_LRO_MODE = 0x200, /* LRO supported */ 1794 FNM_FLEX10_MODE = 0x400, /* QinQ, FLEX-10 or VNIC */ 1795 FNM_NCSI_MODE = 0x800, /* NCSI supported */ 1796 FNM_IPV6_MODE = 0x1000, /* IPV6 stack enabled */ 1797 FNM_BE2_COMPAT_MODE = 0x2000, /* BE2 compatibility (BE3 disable)*/ 1798 FNM_INVALID_MODE = 0x8000, /* Invalid */ 1799 FNM_BE3_COMPAT_MODE = 0x10000, /* BE3 features */ 1800 FNM_VNIC_MODE = 0x20000, /* Set when IBM vNIC mode is set */ 1801 FNM_VNTAG_MODE = 0x40000, /* Set when VNTAG mode is set */ 1802 FNM_UMC_MODE = 0x1000000, /* Set when UMC mode is set */ 1803 FNM_UMC_DEF_EN = 0x100000, /* Set when UMC Default is set */ 1804 FNM_ONE_GB_EN = 0x200000, /* Set when 1GB Default is set */ 1805 FNM_VNIC_DEF_VALID = 0x400000, /* Set when VNIC_DEF_EN is valid */ 1806 FNM_VNIC_DEF_EN = 0x800000 /* Set when VNIC Default enabled */ 1807 }; 1808 1809 1810 struct mbx_common_config_vlan { 1811 struct mbx_hdr hdr; 1812 union { 1813 struct { 1814 #ifdef _BIG_ENDIAN 1815 uint8_t num_vlans; 1816 uint8_t untagged; 1817 uint8_t promisc; 1818 uint8_t if_id; 1819 #else 1820 uint8_t if_id; 1821 uint8_t promisc; 1822 uint8_t untagged; 1823 uint8_t num_vlans; 1824 #endif 1825 union { 1826 struct normal_vlan normal_vlans[64]; 1827 struct qinq_vlan qinq_vlans[32]; 1828 } tags; 1829 } req; 1830 1831 struct { 1832 uint32_t rsvd; 1833 } rsp; 1834 } params; 1835 }; 1836 1837 typedef struct iface_rx_filter_ctx { 1838 uint32_t global_flags_mask; 1839 uint32_t global_flags; 1840 uint32_t iface_flags_mask; 1841 uint32_t iface_flags; 1842 uint32_t if_id; 1843 #define IFACE_RX_NUM_MCAST_MAX 64 1844 uint32_t num_mcast; 1845 struct mbx_mcast_addr { 1846 uint8_t byte[6]; 1847 } mac[IFACE_RX_NUM_MCAST_MAX]; 1848 } iface_rx_filter_ctx_t; 1849 1850 /* [34] OPCODE_COMMON_SET_IFACE_RX_FILTER */ 1851 struct mbx_set_common_iface_rx_filter { 1852 struct mbx_hdr hdr; 1853 union { 1854 iface_rx_filter_ctx_t req; 1855 iface_rx_filter_ctx_t rsp; 1856 } params; 1857 }; 1858 1859 struct be_set_eqd { 1860 uint32_t eq_id; 1861 uint32_t phase; 1862 uint32_t dm; 1863 }; 1864 1865 /* [41] OPCODE_COMMON_MODIFY_EQ_DELAY */ 1866 struct mbx_modify_common_eq_delay { 1867 struct mbx_hdr hdr; 1868 union { 1869 struct { 1870 uint32_t num_eq; 1871 struct { 1872 uint32_t eq_id; 1873 uint32_t phase; 1874 uint32_t dm; 1875 } delay[8]; 1876 } req; 1877 1878 struct { 1879 uint32_t rsvd0; 1880 } rsp; 1881 } params; 1882 }; 1883 1884 /* [32] OPCODE_COMMON_GET_CNTL_ATTRIBUTES */ 1885 1886 struct mgmt_hba_attr { 1887 int8_t flashrom_ver_str[32]; 1888 int8_t manufac_name[32]; 1889 uint32_t supp_modes; 1890 int8_t seeprom_ver_lo; 1891 int8_t seeprom_ver_hi; 1892 int8_t rsvd0[2]; 1893 uint32_t ioctl_data_struct_ver; 1894 uint32_t ep_fw_data_struct_ver; 1895 uint8_t ncsi_ver_str[12]; 1896 uint32_t def_ext_to; 1897 int8_t cntl_mod_num[32]; 1898 int8_t cntl_desc[64]; 1899 int8_t cntl_ser_num[32]; 1900 int8_t ip_ver_str[32]; 1901 int8_t fw_ver_str[32]; 1902 int8_t bios_ver_str[32]; 1903 int8_t redboot_ver_str[32]; 1904 int8_t drv_ver_str[32]; 1905 int8_t fw_on_flash_ver_str[32]; 1906 uint32_t funcs_supp; 1907 uint16_t max_cdblen; 1908 uint8_t asic_rev; 1909 uint8_t gen_guid[16]; 1910 uint8_t hba_port_count; 1911 uint16_t default_link_down_timeout; 1912 uint8_t iscsi_ver_min_max; 1913 uint8_t multifunc_dev; 1914 uint8_t cache_valid; 1915 uint8_t hba_status; 1916 uint8_t max_domains_supp; 1917 uint8_t phy_port; 1918 uint32_t fw_post_status; 1919 uint32_t hba_mtu[8]; 1920 uint8_t iSCSI_feat; 1921 uint8_t asic_gen; 1922 uint8_t future_u8[2]; 1923 uint32_t future_u32[3]; 1924 }; 1925 1926 struct mgmt_cntl_attr { 1927 struct mgmt_hba_attr hba_attr; 1928 uint16_t pci_vendor_id; 1929 uint16_t pci_device_id; 1930 uint16_t pci_sub_vendor_id; 1931 uint16_t pci_sub_system_id; 1932 uint8_t pci_bus_num; 1933 uint8_t pci_dev_num; 1934 uint8_t pci_func_num; 1935 uint8_t interface_type; 1936 uint64_t unique_id; 1937 uint8_t netfilters; 1938 uint8_t rsvd0[3]; 1939 uint32_t future_u32[4]; 1940 }; 1941 1942 struct mbx_common_get_cntl_attr { 1943 struct mbx_hdr hdr; 1944 union { 1945 struct { 1946 uint32_t rsvd0; 1947 } req; 1948 struct { 1949 struct mgmt_cntl_attr cntl_attr_info; 1950 } rsp; 1951 } params; 1952 }; 1953 1954 /* [59] OPCODE_ADD_COMMON_IFACE_MAC */ 1955 struct mbx_add_common_iface_mac { 1956 struct mbx_hdr hdr; 1957 union { 1958 struct { 1959 uint32_t if_id; 1960 uint8_t mac_address[6]; 1961 uint8_t rsvd0[2]; 1962 } req; 1963 struct { 1964 uint32_t pmac_id; 1965 } rsp; 1966 } params; 1967 }; 1968 1969 /* [60] OPCODE_DEL_COMMON_IFACE_MAC */ 1970 struct mbx_del_common_iface_mac { 1971 struct mbx_hdr hdr; 1972 union { 1973 struct { 1974 uint32_t if_id; 1975 uint32_t pmac_id; 1976 } req; 1977 struct { 1978 uint32_t rsvd0; 1979 } rsp; 1980 } params; 1981 }; 1982 1983 /* [8] OPCODE_QUERY_COMMON_MAX_MBX_BUFFER_SIZE */ 1984 struct mbx_query_common_max_mbx_buffer_size { 1985 struct mbx_hdr hdr; 1986 struct { 1987 uint32_t max_ioctl_bufsz; 1988 } rsp; 1989 }; 1990 1991 /* [61] OPCODE_COMMON_FUNCTION_RESET */ 1992 struct ioctl_common_function_reset { 1993 struct mbx_hdr hdr; 1994 }; 1995 1996 /* [73] OPCODE_COMMON_READ_TRANSRECEIVER_DATA */ 1997 struct mbx_read_common_transrecv_data { 1998 struct mbx_hdr hdr; 1999 union { 2000 struct { 2001 uint32_t page_num; 2002 uint32_t port; 2003 } req; 2004 struct { 2005 uint32_t page_num; 2006 uint32_t port; 2007 uint32_t page_data[32]; 2008 } rsp; 2009 } params; 2010 2011 }; 2012 2013 /* [80] OPCODE_COMMON_FUNCTION_LINK_CONFIG */ 2014 struct mbx_common_func_link_cfg { 2015 struct mbx_hdr hdr; 2016 union { 2017 struct { 2018 uint32_t enable; 2019 } req; 2020 struct { 2021 uint32_t rsvd0; 2022 } rsp; 2023 } params; 2024 }; 2025 2026 /* [103] OPCODE_COMMON_SET_FUNCTIONAL_CAPS */ 2027 #define CAP_SW_TIMESTAMPS 2 2028 #define CAP_BE3_NATIVE_ERX_API 4 2029 2030 struct mbx_common_set_function_cap { 2031 struct mbx_hdr hdr; 2032 union { 2033 struct { 2034 uint32_t valid_capability_flags; 2035 uint32_t capability_flags; 2036 uint8_t sbz[212]; 2037 } req; 2038 struct { 2039 uint32_t valid_capability_flags; 2040 uint32_t capability_flags; 2041 uint8_t sbz[212]; 2042 } rsp; 2043 } params; 2044 }; 2045 struct mbx_lowlevel_test_loopback_mode { 2046 struct mbx_hdr hdr; 2047 union { 2048 struct { 2049 uint32_t loopback_type; 2050 uint32_t num_pkts; 2051 uint64_t pattern; 2052 uint32_t src_port; 2053 uint32_t dest_port; 2054 uint32_t pkt_size; 2055 }req; 2056 struct { 2057 uint32_t status; 2058 uint32_t num_txfer; 2059 uint32_t num_rx; 2060 uint32_t miscomp_off; 2061 uint32_t ticks_compl; 2062 }rsp; 2063 } params; 2064 }; 2065 2066 struct mbx_lowlevel_set_loopback_mode { 2067 struct mbx_hdr hdr; 2068 union { 2069 struct { 2070 uint8_t src_port; 2071 uint8_t dest_port; 2072 uint8_t loopback_type; 2073 uint8_t loopback_state; 2074 } req; 2075 struct { 2076 uint8_t rsvd0[4]; 2077 } rsp; 2078 } params; 2079 }; 2080 #define MAX_RESC_DESC 256 2081 #define RESC_DESC_SIZE 88 2082 #define ACTIVE_PROFILE 2 2083 #define NIC_RESC_DESC_TYPE_V0 0x41 2084 #define NIC_RESC_DESC_TYPE_V1 0x51 2085 /* OPCODE_COMMON_GET_FUNCTION_CONFIG */ 2086 struct mbx_common_get_func_config { 2087 struct mbx_hdr hdr; 2088 union { 2089 struct { 2090 uint8_t rsvd; 2091 uint8_t type; 2092 uint16_t rsvd1; 2093 } req; 2094 struct { 2095 uint32_t desc_count; 2096 uint8_t resources[MAX_RESC_DESC * RESC_DESC_SIZE]; 2097 } rsp; 2098 } params; 2099 }; 2100 2101 2102 /* OPCODE_COMMON_GET_PROFILE_CONFIG */ 2103 2104 struct mbx_common_get_profile_config { 2105 struct mbx_hdr hdr; 2106 union { 2107 struct { 2108 uint8_t rsvd; 2109 uint8_t type; 2110 uint16_t rsvd1; 2111 } req; 2112 struct { 2113 uint32_t desc_count; 2114 uint8_t resources[MAX_RESC_DESC * RESC_DESC_SIZE]; 2115 } rsp; 2116 } params; 2117 }; 2118 2119 struct oce_nic_resc_desc { 2120 uint8_t desc_type; 2121 uint8_t desc_len; 2122 uint8_t rsvd1; 2123 uint8_t flags; 2124 uint8_t vf_num; 2125 uint8_t rsvd2; 2126 uint8_t pf_num; 2127 uint8_t rsvd3; 2128 uint16_t unicast_mac_count; 2129 uint8_t rsvd4[6]; 2130 uint16_t mcc_count; 2131 uint16_t vlan_count; 2132 uint16_t mcast_mac_count; 2133 uint16_t txq_count; 2134 uint16_t rq_count; 2135 uint16_t rssq_count; 2136 uint16_t lro_count; 2137 uint16_t cq_count; 2138 uint16_t toe_conn_count; 2139 uint16_t eq_count; 2140 uint32_t rsvd5; 2141 uint32_t cap_flags; 2142 uint8_t link_param; 2143 uint8_t rsvd6[3]; 2144 uint32_t bw_min; 2145 uint32_t bw_max; 2146 uint8_t acpi_params; 2147 uint8_t wol_param; 2148 uint16_t rsvd7; 2149 uint32_t rsvd8[7]; 2150 2151 }; 2152 2153 2154 struct flash_file_hdr { 2155 uint8_t sign[52]; 2156 uint8_t ufi_version[4]; 2157 uint32_t file_len; 2158 uint32_t cksum; 2159 uint32_t antidote; 2160 uint32_t num_imgs; 2161 uint8_t build[24]; 2162 uint8_t asic_type_rev; 2163 uint8_t rsvd[31]; 2164 }; 2165 2166 struct image_hdr { 2167 uint32_t imageid; 2168 uint32_t imageoffset; 2169 uint32_t imagelength; 2170 uint32_t image_checksum; 2171 uint8_t image_version[32]; 2172 }; 2173 2174 struct flash_section_hdr { 2175 uint32_t format_rev; 2176 uint32_t cksum; 2177 uint32_t antidote; 2178 uint32_t num_images; 2179 uint8_t id_string[128]; 2180 uint32_t rsvd[4]; 2181 }; 2182 2183 struct flash_section_entry { 2184 uint32_t type; 2185 uint32_t offset; 2186 uint32_t pad_size; 2187 uint32_t image_size; 2188 uint32_t cksum; 2189 uint32_t entry_point; 2190 uint32_t rsvd0; 2191 uint32_t rsvd1; 2192 uint8_t ver_data[32]; 2193 }; 2194 2195 struct flash_sec_info { 2196 uint8_t cookie[32]; 2197 struct flash_section_hdr fsec_hdr; 2198 struct flash_section_entry fsec_entry[32]; 2199 }; 2200 2201 2202 enum LOWLEVEL_SUBSYSTEM_OPCODES { 2203 /* Opcodes used for lowlevel functions common to many subystems. 2204 * Some of these opcodes are used for diagnostic functions only. 2205 * These opcodes use the MBX_SUBSYSTEM_LOWLEVEL subsystem code. 2206 */ 2207 OPCODE_LOWLEVEL_TEST_LOOPBACK = 18, 2208 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE = 19, 2209 OPCODE_LOWLEVEL_GET_LOOPBACK_MODE = 20 2210 }; 2211 2212 enum LLDP_SUBSYSTEM_OPCODES { 2213 /* Opcodes used for LLDP susbsytem for configuring the LLDP state machines. */ 2214 OPCODE_LLDP_GET_CFG = 1, 2215 OPCODE_LLDP_SET_CFG = 2, 2216 OPCODE_LLDP_GET_STATS = 3 2217 }; 2218 2219 enum DCBX_SUBSYSTEM_OPCODES { 2220 /* Opcodes used for DCBX. */ 2221 OPCODE_DCBX_GET_CFG = 1, 2222 OPCODE_DCBX_SET_CFG = 2, 2223 OPCODE_DCBX_GET_MIB_INFO = 3, 2224 OPCODE_DCBX_GET_DCBX_MODE = 4, 2225 OPCODE_DCBX_SET_MODE = 5 2226 }; 2227 2228 enum DMTF_SUBSYSTEM_OPCODES { 2229 /* Opcodes used for DCBX subsystem. */ 2230 OPCODE_DMTF_EXEC_CLP_CMD = 1 2231 }; 2232 2233 enum DIAG_SUBSYSTEM_OPCODES { 2234 /* Opcodes used for diag functions common to many subsystems. */ 2235 OPCODE_DIAG_RUN_DMA_TEST = 1, 2236 OPCODE_DIAG_RUN_MDIO_TEST = 2, 2237 OPCODE_DIAG_RUN_NLB_TEST = 3, 2238 OPCODE_DIAG_RUN_ARM_TIMER_TEST = 4, 2239 OPCODE_DIAG_GET_MAC = 5 2240 }; 2241 2242 enum VENDOR_SUBSYSTEM_OPCODES { 2243 /* Opcodes used for Vendor subsystem. */ 2244 OPCODE_VENDOR_SLI = 1 2245 }; 2246 2247 /* Management Status Codes */ 2248 enum MGMT_STATUS_SUCCESS { 2249 MGMT_SUCCESS = 0, 2250 MGMT_FAILED = 1, 2251 MGMT_ILLEGAL_REQUEST = 2, 2252 MGMT_ILLEGAL_FIELD = 3, 2253 MGMT_INSUFFICIENT_BUFFER = 4, 2254 MGMT_UNAUTHORIZED_REQUEST = 5, 2255 MGMT_INVALID_ISNS_ADDRESS = 10, 2256 MGMT_INVALID_IPADDR = 11, 2257 MGMT_INVALID_GATEWAY = 12, 2258 MGMT_INVALID_SUBNETMASK = 13, 2259 MGMT_INVALID_TARGET_IPADDR = 16, 2260 MGMT_TGTTBL_FULL = 20, 2261 MGMT_FLASHROM_SAVE_FAILED = 23, 2262 MGMT_IOCTLHANDLE_ALLOC_FAILED = 27, 2263 MGMT_INVALID_SESSION = 31, 2264 MGMT_INVALID_CONNECTION = 32, 2265 MGMT_BTL_PATH_EXCEEDS_OSM_LIMIT = 33, 2266 MGMT_BTL_TGTID_EXCEEDS_OSM_LIMIT = 34, 2267 MGMT_BTL_PATH_TGTID_OCCUPIED = 35, 2268 MGMT_BTL_NO_FREE_SLOT_PATH = 36, 2269 MGMT_BTL_NO_FREE_SLOT_TGTID = 37, 2270 MGMT_POLL_IOCTL_TIMEOUT = 40, 2271 MGMT_ERROR_ACITISCSI = 41, 2272 MGMT_BUFFER_SIZE_EXCEED_OSM_OR_OS_LIMIT = 43, 2273 MGMT_REBOOT_REQUIRED = 44, 2274 MGMT_INSUFFICIENT_TIMEOUT = 45, 2275 MGMT_IPADDR_NOT_SET = 46, 2276 MGMT_IPADDR_DUP_DETECTED = 47, 2277 MGMT_CANT_REMOVE_LAST_CONNECTION = 48, 2278 MGMT_TARGET_BUSY = 49, 2279 MGMT_TGT_ERR_LISTEN_SOCKET = 50, 2280 MGMT_TGT_ERR_BIND_SOCKET = 51, 2281 MGMT_TGT_ERR_NO_SOCKET = 52, 2282 MGMT_TGT_ERR_ISNS_COMM_FAILED = 55, 2283 MGMT_CANNOT_DELETE_BOOT_TARGET = 56, 2284 MGMT_TGT_PORTAL_MODE_IN_LISTEN = 57, 2285 MGMT_FCF_IN_USE = 58 , 2286 MGMT_NO_CQE = 59, 2287 MGMT_TARGET_NOT_FOUND = 65, 2288 MGMT_NOT_SUPPORTED = 66, 2289 MGMT_NO_FCF_RECORDS = 67, 2290 MGMT_FEATURE_NOT_SUPPORTED = 68, 2291 MGMT_VPD_FUNCTION_OUT_OF_RANGE = 69, 2292 MGMT_VPD_FUNCTION_TYPE_INCORRECT = 70, 2293 MGMT_INVALID_NON_EMBEDDED_WRB = 71, 2294 MGMT_OOR = 100, 2295 MGMT_INVALID_PD = 101, 2296 MGMT_STATUS_PD_INUSE = 102, 2297 MGMT_INVALID_CQ = 103, 2298 MGMT_INVALID_QP = 104, 2299 MGMT_INVALID_STAG = 105, 2300 MGMT_ORD_EXCEEDS = 106, 2301 MGMT_IRD_EXCEEDS = 107, 2302 MGMT_SENDQ_WQE_EXCEEDS = 108, 2303 MGMT_RECVQ_RQE_EXCEEDS = 109, 2304 MGMT_SGE_SEND_EXCEEDS = 110, 2305 MGMT_SGE_WRITE_EXCEEDS = 111, 2306 MGMT_SGE_RECV_EXCEEDS = 112, 2307 MGMT_INVALID_STATE_CHANGE = 113, 2308 MGMT_MW_BOUND = 114, 2309 MGMT_INVALID_VA = 115, 2310 MGMT_INVALID_LENGTH = 116, 2311 MGMT_INVALID_FBO = 117, 2312 MGMT_INVALID_ACC_RIGHTS = 118, 2313 MGMT_INVALID_PBE_SIZE = 119, 2314 MGMT_INVALID_PBL_ENTRY = 120, 2315 MGMT_INVALID_PBL_OFFSET = 121, 2316 MGMT_ADDR_NON_EXIST = 122, 2317 MGMT_INVALID_VLANID = 123, 2318 MGMT_INVALID_MTU = 124, 2319 MGMT_INVALID_BACKLOG = 125, 2320 MGMT_CONNECTION_INPROGRESS = 126, 2321 MGMT_INVALID_RQE_SIZE = 127, 2322 MGMT_INVALID_RQE_ENTRY = 128 2323 }; 2324 2325 /* Additional Management Status Codes */ 2326 enum MGMT_ADDI_STATUS { 2327 MGMT_ADDI_NO_STATUS = 0, 2328 MGMT_ADDI_INVALID_IPTYPE = 1, 2329 MGMT_ADDI_TARGET_HANDLE_NOT_FOUND = 9, 2330 MGMT_ADDI_SESSION_HANDLE_NOT_FOUND = 10, 2331 MGMT_ADDI_CONNECTION_HANDLE_NOT_FOUND = 11, 2332 MGMT_ADDI_ACTIVE_SESSIONS_PRESENT = 16, 2333 MGMT_ADDI_SESSION_ALREADY_OPENED = 17, 2334 MGMT_ADDI_SESSION_ALREADY_CLOSED = 18, 2335 MGMT_ADDI_DEST_HOST_UNREACHABLE = 19, 2336 MGMT_ADDI_LOGIN_IN_PROGRESS = 20, 2337 MGMT_ADDI_TCP_CONNECT_FAILED = 21, 2338 MGMT_ADDI_INSUFFICIENT_RESOURCES = 22, 2339 MGMT_ADDI_LINK_DOWN = 23, 2340 MGMT_ADDI_DHCP_ERROR = 24, 2341 MGMT_ADDI_CONNECTION_OFFLOADED = 25, 2342 MGMT_ADDI_CONNECTION_NOT_OFFLOADED = 26, 2343 MGMT_ADDI_CONNECTION_UPLOAD_IN_PROGRESS = 27, 2344 MGMT_ADDI_REQUEST_REJECTED = 28, 2345 MGMT_ADDI_INVALID_SUBSYSTEM = 29, 2346 MGMT_ADDI_INVALID_OPCODE = 30, 2347 MGMT_ADDI_INVALID_MAXCONNECTION_PARAM = 31, 2348 MGMT_ADDI_INVALID_KEY = 32, 2349 MGMT_ADDI_INVALID_DOMAIN = 35, 2350 MGMT_ADDI_LOGIN_INITIATOR_ERROR = 43, 2351 MGMT_ADDI_LOGIN_AUTHENTICATION_ERROR = 44, 2352 MGMT_ADDI_LOGIN_AUTHORIZATION_ERROR = 45, 2353 MGMT_ADDI_LOGIN_NOT_FOUND = 46, 2354 MGMT_ADDI_LOGIN_TARGET_REMOVED = 47, 2355 MGMT_ADDI_LOGIN_UNSUPPORTED_VERSION = 48, 2356 MGMT_ADDI_LOGIN_TOO_MANY_CONNECTIONS = 49, 2357 MGMT_ADDI_LOGIN_MISSING_PARAMETER = 50, 2358 MGMT_ADDI_LOGIN_NO_SESSION_SPANNING = 51, 2359 MGMT_ADDI_LOGIN_SESSION_TYPE_NOT_SUPPORTED = 52, 2360 MGMT_ADDI_LOGIN_SESSION_DOES_NOT_EXIST = 53, 2361 MGMT_ADDI_LOGIN_INVALID_DURING_LOGIN = 54, 2362 MGMT_ADDI_LOGIN_TARGET_ERROR = 55, 2363 MGMT_ADDI_LOGIN_SERVICE_UNAVAILABLE = 56, 2364 MGMT_ADDI_LOGIN_OUT_OF_RESOURCES = 57, 2365 MGMT_ADDI_SAME_CHAP_SECRET = 58, 2366 MGMT_ADDI_INVALID_SECRET_LENGTH = 59, 2367 MGMT_ADDI_DUPLICATE_ENTRY = 60, 2368 MGMT_ADDI_SETTINGS_MODIFIED_REBOOT_REQD = 63, 2369 MGMT_ADDI_INVALID_EXTENDED_TIMEOUT = 64, 2370 MGMT_ADDI_INVALID_INTERFACE_HANDLE = 65, 2371 MGMT_ADDI_ERR_VLAN_ON_DEF_INTERFACE = 66, 2372 MGMT_ADDI_INTERFACE_DOES_NOT_EXIST = 67, 2373 MGMT_ADDI_INTERFACE_ALREADY_EXISTS = 68, 2374 MGMT_ADDI_INVALID_VLAN_RANGE = 69, 2375 MGMT_ADDI_ERR_SET_VLAN = 70, 2376 MGMT_ADDI_ERR_DEL_VLAN = 71, 2377 MGMT_ADDI_CANNOT_DEL_DEF_INTERFACE = 72, 2378 MGMT_ADDI_DHCP_REQ_ALREADY_PENDING = 73, 2379 MGMT_ADDI_TOO_MANY_INTERFACES = 74, 2380 MGMT_ADDI_INVALID_REQUEST = 75 2381 }; 2382 2383 enum NIC_SUBSYSTEM_OPCODES { 2384 /** 2385 * @brief NIC Subsystem Opcodes (see Network SLI-4 manual >= Rev4, v21-2) 2386 * These opcodes are used for configuring the Ethernet interfaces. 2387 * These opcodes all use the MBX_SUBSYSTEM_NIC subsystem code. 2388 */ 2389 NIC_CONFIG_RSS = 1, 2390 NIC_CONFIG_ACPI = 2, 2391 NIC_CONFIG_PROMISCUOUS = 3, 2392 NIC_GET_STATS = 4, 2393 NIC_CREATE_WQ = 7, 2394 NIC_CREATE_RQ = 8, 2395 NIC_DELETE_WQ = 9, 2396 NIC_DELETE_RQ = 10, 2397 NIC_CONFIG_ACPI_WOL_MAGIC = 12, 2398 NIC_GET_NETWORK_STATS = 13, 2399 NIC_CREATE_HDS_RQ = 16, 2400 NIC_DELETE_HDS_RQ = 17, 2401 NIC_GET_PPORT_STATS = 18, 2402 NIC_GET_VPORT_STATS = 19, 2403 NIC_GET_QUEUE_STATS = 20 2404 }; 2405 2406 /* Hash option flags for RSS enable */ 2407 enum RSS_ENABLE_FLAGS { 2408 RSS_ENABLE_NONE = 0x0, /* (No RSS) */ 2409 RSS_ENABLE_IPV4 = 0x1, /* (IPV4 HASH enabled ) */ 2410 RSS_ENABLE_TCP_IPV4 = 0x2, /* (TCP IPV4 Hash enabled) */ 2411 RSS_ENABLE_IPV6 = 0x4, /* (IPV6 HASH enabled) */ 2412 RSS_ENABLE_TCP_IPV6 = 0x8, /* (TCP IPV6 HASH */ 2413 RSS_ENABLE_UDP_IPV4 = 0x10, /* UDP IPV4 HASH */ 2414 RSS_ENABLE_UDP_IPV6 = 0x20 /* UDP IPV6 HASH */ 2415 }; 2416 #define RSS_ENABLE (RSS_ENABLE_IPV4 | RSS_ENABLE_TCP_IPV4) 2417 #define RSS_DISABLE RSS_ENABLE_NONE 2418 2419 /* NIC header WQE */ 2420 struct oce_nic_hdr_wqe { 2421 union { 2422 struct { 2423 #ifdef _BIG_ENDIAN 2424 /* dw0 */ 2425 uint32_t rsvd0; 2426 2427 /* dw1 */ 2428 uint32_t last_seg_udp_len:14; 2429 uint32_t rsvd1:18; 2430 2431 /* dw2 */ 2432 uint32_t lso_mss:14; 2433 uint32_t num_wqe:5; 2434 uint32_t rsvd4:2; 2435 uint32_t vlan:1; 2436 uint32_t lso:1; 2437 uint32_t tcpcs:1; 2438 uint32_t udpcs:1; 2439 uint32_t ipcs:1; 2440 uint32_t mgmt:1; 2441 uint32_t lso6:1; 2442 uint32_t forward:1; 2443 uint32_t crc:1; 2444 uint32_t event:1; 2445 uint32_t complete:1; 2446 2447 /* dw3 */ 2448 uint32_t vlan_tag:16; 2449 uint32_t total_length:16; 2450 #else 2451 /* dw0 */ 2452 uint32_t rsvd0; 2453 2454 /* dw1 */ 2455 uint32_t rsvd1:18; 2456 uint32_t last_seg_udp_len:14; 2457 2458 /* dw2 */ 2459 uint32_t complete:1; 2460 uint32_t event:1; 2461 uint32_t crc:1; 2462 uint32_t forward:1; 2463 uint32_t lso6:1; 2464 uint32_t mgmt:1; 2465 uint32_t ipcs:1; 2466 uint32_t udpcs:1; 2467 uint32_t tcpcs:1; 2468 uint32_t lso:1; 2469 uint32_t vlan:1; 2470 uint32_t rsvd4:2; 2471 uint32_t num_wqe:5; 2472 uint32_t lso_mss:14; 2473 2474 /* dw3 */ 2475 uint32_t total_length:16; 2476 uint32_t vlan_tag:16; 2477 #endif 2478 } s; 2479 uint32_t dw[4]; 2480 } u0; 2481 }; 2482 2483 /* NIC fragment WQE */ 2484 struct oce_nic_frag_wqe { 2485 union { 2486 struct { 2487 /* dw0 */ 2488 uint32_t frag_pa_hi; 2489 /* dw1 */ 2490 uint32_t frag_pa_lo; 2491 /* dw2 */ 2492 uint32_t rsvd0; 2493 uint32_t frag_len; 2494 } s; 2495 uint32_t dw[4]; 2496 } u0; 2497 }; 2498 2499 /* Ethernet Tx Completion Descriptor */ 2500 struct oce_nic_tx_cqe { 2501 union { 2502 struct { 2503 #ifdef _BIG_ENDIAN 2504 /* dw 0 */ 2505 uint32_t status:4; 2506 uint32_t rsvd0:8; 2507 uint32_t port:2; 2508 uint32_t ct:2; 2509 uint32_t wqe_index:16; 2510 2511 /* dw 1 */ 2512 uint32_t rsvd1:5; 2513 uint32_t cast_enc:2; 2514 uint32_t lso:1; 2515 uint32_t nwh_bytes:8; 2516 uint32_t user_bytes:16; 2517 2518 /* dw 2 */ 2519 uint32_t rsvd2; 2520 2521 /* dw 3 */ 2522 uint32_t valid:1; 2523 uint32_t rsvd3:4; 2524 uint32_t wq_id:11; 2525 uint32_t num_pkts:16; 2526 #else 2527 /* dw 0 */ 2528 uint32_t wqe_index:16; 2529 uint32_t ct:2; 2530 uint32_t port:2; 2531 uint32_t rsvd0:8; 2532 uint32_t status:4; 2533 2534 /* dw 1 */ 2535 uint32_t user_bytes:16; 2536 uint32_t nwh_bytes:8; 2537 uint32_t lso:1; 2538 uint32_t cast_enc:2; 2539 uint32_t rsvd1:5; 2540 /* dw 2 */ 2541 uint32_t rsvd2; 2542 2543 /* dw 3 */ 2544 uint32_t num_pkts:16; 2545 uint32_t wq_id:11; 2546 uint32_t rsvd3:4; 2547 uint32_t valid:1; 2548 #endif 2549 } s; 2550 uint32_t dw[4]; 2551 } u0; 2552 }; 2553 #define WQ_CQE_VALID(_cqe) (_cqe->u0.dw[3]) 2554 #define WQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[3] = 0) 2555 2556 /* Receive Queue Entry (RQE) */ 2557 struct oce_nic_rqe { 2558 union { 2559 struct { 2560 uint32_t frag_pa_hi; 2561 uint32_t frag_pa_lo; 2562 } s; 2563 uint32_t dw[2]; 2564 } u0; 2565 }; 2566 2567 /* NIC Receive CQE */ 2568 struct oce_nic_rx_cqe { 2569 union { 2570 struct { 2571 #ifdef _BIG_ENDIAN 2572 /* dw 0 */ 2573 uint32_t ip_options:1; 2574 uint32_t port:1; 2575 uint32_t pkt_size:14; 2576 uint32_t vlan_tag:16; 2577 2578 /* dw 1 */ 2579 uint32_t num_fragments:3; 2580 uint32_t switched:1; 2581 uint32_t ct:2; 2582 uint32_t frag_index:10; 2583 uint32_t rsvd0:1; 2584 uint32_t vlan_tag_present:1; 2585 uint32_t mac_dst:6; 2586 uint32_t ip_ver:1; 2587 uint32_t l4_cksum_pass:1; 2588 uint32_t ip_cksum_pass:1; 2589 uint32_t udpframe:1; 2590 uint32_t tcpframe:1; 2591 uint32_t ipframe:1; 2592 uint32_t rss_hp:1; 2593 uint32_t error:1; 2594 2595 /* dw 2 */ 2596 uint32_t valid:1; 2597 uint32_t hds_type:2; 2598 uint32_t lro_pkt:1; 2599 uint32_t rsvd4:1; 2600 uint32_t hds_hdr_size:12; 2601 uint32_t hds_hdr_frag_index:10; 2602 uint32_t rss_bank:1; 2603 uint32_t qnq:1; 2604 uint32_t pkt_type:2; 2605 uint32_t rss_flush:1; 2606 2607 /* dw 3 */ 2608 uint32_t rss_hash_value; 2609 #else 2610 /* dw 0 */ 2611 uint32_t vlan_tag:16; 2612 uint32_t pkt_size:14; 2613 uint32_t port:1; 2614 uint32_t ip_options:1; 2615 /* dw 1 */ 2616 uint32_t error:1; 2617 uint32_t rss_hp:1; 2618 uint32_t ipframe:1; 2619 uint32_t tcpframe:1; 2620 uint32_t udpframe:1; 2621 uint32_t ip_cksum_pass:1; 2622 uint32_t l4_cksum_pass:1; 2623 uint32_t ip_ver:1; 2624 uint32_t mac_dst:6; 2625 uint32_t vlan_tag_present:1; 2626 uint32_t rsvd0:1; 2627 uint32_t frag_index:10; 2628 uint32_t ct:2; 2629 uint32_t switched:1; 2630 uint32_t num_fragments:3; 2631 2632 /* dw 2 */ 2633 uint32_t rss_flush:1; 2634 uint32_t pkt_type:2; 2635 uint32_t qnq:1; 2636 uint32_t rss_bank:1; 2637 uint32_t hds_hdr_frag_index:10; 2638 uint32_t hds_hdr_size:12; 2639 uint32_t rsvd4:1; 2640 uint32_t lro_pkt:1; 2641 uint32_t hds_type:2; 2642 uint32_t valid:1; 2643 /* dw 3 */ 2644 uint32_t rss_hash_value; 2645 #endif 2646 } s; 2647 uint32_t dw[4]; 2648 } u0; 2649 }; 2650 /* NIC Receive CQE_v1 */ 2651 struct oce_nic_rx_cqe_v1 { 2652 union { 2653 struct { 2654 #ifdef _BIG_ENDIAN 2655 /* dw 0 */ 2656 uint32_t ip_options:1; 2657 uint32_t vlan_tag_present:1; 2658 uint32_t pkt_size:14; 2659 uint32_t vlan_tag:16; 2660 2661 /* dw 1 */ 2662 uint32_t num_fragments:3; 2663 uint32_t switched:1; 2664 uint32_t ct:2; 2665 uint32_t frag_index:10; 2666 uint32_t rsvd0:1; 2667 uint32_t mac_dst:7; 2668 uint32_t ip_ver:1; 2669 uint32_t l4_cksum_pass:1; 2670 uint32_t ip_cksum_pass:1; 2671 uint32_t udpframe:1; 2672 uint32_t tcpframe:1; 2673 uint32_t ipframe:1; 2674 uint32_t rss_hp:1; 2675 uint32_t error:1; 2676 2677 /* dw 2 */ 2678 uint32_t valid:1; 2679 uint32_t rsvd4:13; 2680 uint32_t hds_hdr_size: 2681 uint32_t hds_hdr_frag_index:8; 2682 uint32_t vlantag:1; 2683 uint32_t port:2; 2684 uint32_t rss_bank:1; 2685 uint32_t qnq:1; 2686 uint32_t pkt_type:2; 2687 uint32_t rss_flush:1; 2688 2689 /* dw 3 */ 2690 uint32_t rss_hash_value; 2691 #else 2692 /* dw 0 */ 2693 uint32_t vlan_tag:16; 2694 uint32_t pkt_size:14; 2695 uint32_t vlan_tag_present:1; 2696 uint32_t ip_options:1; 2697 /* dw 1 */ 2698 uint32_t error:1; 2699 uint32_t rss_hp:1; 2700 uint32_t ipframe:1; 2701 uint32_t tcpframe:1; 2702 uint32_t udpframe:1; 2703 uint32_t ip_cksum_pass:1; 2704 uint32_t l4_cksum_pass:1; 2705 uint32_t ip_ver:1; 2706 uint32_t mac_dst:7; 2707 uint32_t rsvd0:1; 2708 uint32_t frag_index:10; 2709 uint32_t ct:2; 2710 uint32_t switched:1; 2711 uint32_t num_fragments:3; 2712 2713 /* dw 2 */ 2714 uint32_t rss_flush:1; 2715 uint32_t pkt_type:2; 2716 uint32_t qnq:1; 2717 uint32_t rss_bank:1; 2718 uint32_t port:2; 2719 uint32_t vlantag:1; 2720 uint32_t hds_hdr_frag_index:8; 2721 uint32_t hds_hdr_size:2; 2722 uint32_t rsvd4:13; 2723 uint32_t valid:1; 2724 /* dw 3 */ 2725 uint32_t rss_hash_value; 2726 #endif 2727 } s; 2728 uint32_t dw[4]; 2729 } u0; 2730 }; 2731 2732 #define RQ_CQE_VALID_MASK 0x80 2733 #define RQ_CQE_VALID(_cqe) (_cqe->u0.dw[2]) 2734 #define RQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[2] = 0) 2735 2736 struct mbx_config_nic_promiscuous { 2737 struct mbx_hdr hdr; 2738 union { 2739 struct { 2740 #ifdef _BIG_ENDIAN 2741 uint16_t rsvd0; 2742 uint8_t port1_promisc; 2743 uint8_t port0_promisc; 2744 #else 2745 uint8_t port0_promisc; 2746 uint8_t port1_promisc; 2747 uint16_t rsvd0; 2748 #endif 2749 } req; 2750 2751 struct { 2752 uint32_t rsvd0; 2753 } rsp; 2754 } params; 2755 }; 2756 2757 typedef union oce_wq_ctx_u { 2758 uint32_t dw[17]; 2759 struct { 2760 #ifdef _BIG_ENDIAN 2761 /* dw4 */ 2762 uint32_t dw4rsvd2:8; 2763 uint32_t nic_wq_type:8; 2764 uint32_t dw4rsvd1:8; 2765 uint32_t num_pages:8; 2766 /* dw5 */ 2767 uint32_t dw5rsvd2:12; 2768 uint32_t wq_size:4; 2769 uint32_t dw5rsvd1:16; 2770 /* dw6 */ 2771 uint32_t valid:1; 2772 uint32_t dw6rsvd1:31; 2773 /* dw7 */ 2774 uint32_t dw7rsvd1:16; 2775 uint32_t cq_id:16; 2776 #else 2777 /* dw4 */ 2778 uint32_t num_pages:8; 2779 #if 0 2780 uint32_t dw4rsvd1:8; 2781 #else 2782 /* PSP: this workaround is not documented: fill 0x01 for ulp_mask */ 2783 uint32_t ulp_mask:8; 2784 #endif 2785 uint32_t nic_wq_type:8; 2786 uint32_t dw4rsvd2:8; 2787 /* dw5 */ 2788 uint32_t dw5rsvd1:16; 2789 uint32_t wq_size:4; 2790 uint32_t dw5rsvd2:12; 2791 /* dw6 */ 2792 uint32_t dw6rsvd1:31; 2793 uint32_t valid:1; 2794 /* dw7 */ 2795 uint32_t cq_id:16; 2796 uint32_t dw7rsvd1:16; 2797 #endif 2798 /* dw8 - dw20 */ 2799 uint32_t dw8_20rsvd1[13]; 2800 } v0; 2801 struct { 2802 #ifdef _BIG_ENDIAN 2803 /* dw4 */ 2804 uint32_t dw4rsvd2:8; 2805 uint32_t nic_wq_type:8; 2806 uint32_t dw4rsvd1:8; 2807 uint32_t num_pages:8; 2808 /* dw5 */ 2809 uint32_t dw5rsvd2:12; 2810 uint32_t wq_size:4; 2811 uint32_t iface_id:16; 2812 /* dw6 */ 2813 uint32_t valid:1; 2814 uint32_t dw6rsvd1:31; 2815 /* dw7 */ 2816 uint32_t dw7rsvd1:16; 2817 uint32_t cq_id:16; 2818 #else 2819 /* dw4 */ 2820 uint32_t num_pages:8; 2821 uint32_t dw4rsvd1:8; 2822 uint32_t nic_wq_type:8; 2823 uint32_t dw4rsvd2:8; 2824 /* dw5 */ 2825 uint32_t iface_id:16; 2826 uint32_t wq_size:4; 2827 uint32_t dw5rsvd2:12; 2828 /* dw6 */ 2829 uint32_t dw6rsvd1:31; 2830 uint32_t valid:1; 2831 /* dw7 */ 2832 uint32_t cq_id:16; 2833 uint32_t dw7rsvd1:16; 2834 #endif 2835 /* dw8 - dw20 */ 2836 uint32_t dw8_20rsvd1[13]; 2837 } v1; 2838 } oce_wq_ctx_t; 2839 2840 /** 2841 * @brief [07] NIC_CREATE_WQ 2842 * @note 2843 * Lancer requires an InterfaceID to be specified with every WQ. This 2844 * is the basis for NIC IOV where the Interface maps to a vPort and maps 2845 * to both Tx and Rx sides. 2846 */ 2847 #define OCE_WQ_TYPE_FORWARDING 0x1 /* wq forwards pkts to TOE */ 2848 #define OCE_WQ_TYPE_STANDARD 0x2 /* wq sends network pkts */ 2849 struct mbx_create_nic_wq { 2850 struct mbx_hdr hdr; 2851 union { 2852 struct { 2853 uint8_t num_pages; 2854 uint8_t ulp_num; 2855 uint16_t nic_wq_type; 2856 uint16_t if_id; 2857 uint8_t wq_size; 2858 uint8_t rsvd1; 2859 uint32_t rsvd2; 2860 uint16_t cq_id; 2861 uint16_t rsvd3; 2862 uint32_t rsvd4[13]; 2863 struct phys_addr pages[8]; 2864 2865 } req; 2866 2867 struct { 2868 uint16_t wq_id; 2869 uint16_t rid; 2870 uint32_t db_offset; 2871 uint8_t tc_id; 2872 uint8_t rsvd0[3]; 2873 } rsp; 2874 } params; 2875 }; 2876 2877 /* [09] NIC_DELETE_WQ */ 2878 struct mbx_delete_nic_wq { 2879 /* dw0 - dw3 */ 2880 struct mbx_hdr hdr; 2881 union { 2882 struct { 2883 #ifdef _BIG_ENDIAN 2884 /* dw4 */ 2885 uint16_t rsvd0; 2886 uint16_t wq_id; 2887 #else 2888 /* dw4 */ 2889 uint16_t wq_id; 2890 uint16_t rsvd0; 2891 #endif 2892 } req; 2893 struct { 2894 uint32_t rsvd0; 2895 } rsp; 2896 } params; 2897 }; 2898 2899 2900 2901 struct mbx_create_nic_rq { 2902 struct mbx_hdr hdr; 2903 union { 2904 struct { 2905 uint16_t cq_id; 2906 uint8_t frag_size; 2907 uint8_t num_pages; 2908 struct phys_addr pages[2]; 2909 uint32_t if_id; 2910 uint16_t max_frame_size; 2911 uint16_t page_size; 2912 uint32_t is_rss_queue; 2913 } req; 2914 2915 struct { 2916 uint16_t rq_id; 2917 uint8_t rss_cpuid; 2918 uint8_t rsvd0; 2919 } rsp; 2920 2921 } params; 2922 }; 2923 2924 2925 2926 /* [10] NIC_DELETE_RQ */ 2927 struct mbx_delete_nic_rq { 2928 /* dw0 - dw3 */ 2929 struct mbx_hdr hdr; 2930 union { 2931 struct { 2932 #ifdef _BIG_ENDIAN 2933 /* dw4 */ 2934 uint16_t bypass_flush; 2935 uint16_t rq_id; 2936 #else 2937 /* dw4 */ 2938 uint16_t rq_id; 2939 uint16_t bypass_flush; 2940 #endif 2941 } req; 2942 2943 struct { 2944 /* dw4 */ 2945 uint32_t rsvd0; 2946 } rsp; 2947 } params; 2948 }; 2949 2950 2951 2952 2953 struct oce_port_rxf_stats_v0 { 2954 uint32_t rx_bytes_lsd; /* dword 0*/ 2955 uint32_t rx_bytes_msd; /* dword 1*/ 2956 uint32_t rx_total_frames; /* dword 2*/ 2957 uint32_t rx_unicast_frames; /* dword 3*/ 2958 uint32_t rx_multicast_frames; /* dword 4*/ 2959 uint32_t rx_broadcast_frames; /* dword 5*/ 2960 uint32_t rx_crc_errors; /* dword 6*/ 2961 uint32_t rx_alignment_symbol_errors; /* dword 7*/ 2962 uint32_t rx_pause_frames; /* dword 8*/ 2963 uint32_t rx_control_frames; /* dword 9*/ 2964 uint32_t rx_in_range_errors; /* dword 10*/ 2965 uint32_t rx_out_range_errors; /* dword 11*/ 2966 uint32_t rx_frame_too_long; /* dword 12*/ 2967 uint32_t rx_address_match_errors; /* dword 13*/ 2968 uint32_t rx_vlan_mismatch; /* dword 14*/ 2969 uint32_t rx_dropped_too_small; /* dword 15*/ 2970 uint32_t rx_dropped_too_short; /* dword 16*/ 2971 uint32_t rx_dropped_header_too_small; /* dword 17*/ 2972 uint32_t rx_dropped_tcp_length; /* dword 18*/ 2973 uint32_t rx_dropped_runt; /* dword 19*/ 2974 uint32_t rx_64_byte_packets; /* dword 20*/ 2975 uint32_t rx_65_127_byte_packets; /* dword 21*/ 2976 uint32_t rx_128_256_byte_packets; /* dword 22*/ 2977 uint32_t rx_256_511_byte_packets; /* dword 23*/ 2978 uint32_t rx_512_1023_byte_packets; /* dword 24*/ 2979 uint32_t rx_1024_1518_byte_packets; /* dword 25*/ 2980 uint32_t rx_1519_2047_byte_packets; /* dword 26*/ 2981 uint32_t rx_2048_4095_byte_packets; /* dword 27*/ 2982 uint32_t rx_4096_8191_byte_packets; /* dword 28*/ 2983 uint32_t rx_8192_9216_byte_packets; /* dword 29*/ 2984 uint32_t rx_ip_checksum_errs; /* dword 30*/ 2985 uint32_t rx_tcp_checksum_errs; /* dword 31*/ 2986 uint32_t rx_udp_checksum_errs; /* dword 32*/ 2987 uint32_t rx_non_rss_packets; /* dword 33*/ 2988 uint32_t rx_ipv4_packets; /* dword 34*/ 2989 uint32_t rx_ipv6_packets; /* dword 35*/ 2990 uint32_t rx_ipv4_bytes_lsd; /* dword 36*/ 2991 uint32_t rx_ipv4_bytes_msd; /* dword 37*/ 2992 uint32_t rx_ipv6_bytes_lsd; /* dword 38*/ 2993 uint32_t rx_ipv6_bytes_msd; /* dword 39*/ 2994 uint32_t rx_chute1_packets; /* dword 40*/ 2995 uint32_t rx_chute2_packets; /* dword 41*/ 2996 uint32_t rx_chute3_packets; /* dword 42*/ 2997 uint32_t rx_management_packets; /* dword 43*/ 2998 uint32_t rx_switched_unicast_packets; /* dword 44*/ 2999 uint32_t rx_switched_multicast_packets; /* dword 45*/ 3000 uint32_t rx_switched_broadcast_packets; /* dword 46*/ 3001 uint32_t tx_bytes_lsd; /* dword 47*/ 3002 uint32_t tx_bytes_msd; /* dword 48*/ 3003 uint32_t tx_unicastframes; /* dword 49*/ 3004 uint32_t tx_multicastframes; /* dword 50*/ 3005 uint32_t tx_broadcastframes; /* dword 51*/ 3006 uint32_t tx_pauseframes; /* dword 52*/ 3007 uint32_t tx_controlframes; /* dword 53*/ 3008 uint32_t tx_64_byte_packets; /* dword 54*/ 3009 uint32_t tx_65_127_byte_packets; /* dword 55*/ 3010 uint32_t tx_128_256_byte_packets; /* dword 56*/ 3011 uint32_t tx_256_511_byte_packets; /* dword 57*/ 3012 uint32_t tx_512_1023_byte_packets; /* dword 58*/ 3013 uint32_t tx_1024_1518_byte_packets; /* dword 59*/ 3014 uint32_t tx_1519_2047_byte_packets; /* dword 60*/ 3015 uint32_t tx_2048_4095_byte_packets; /* dword 61*/ 3016 uint32_t tx_4096_8191_byte_packets; /* dword 62*/ 3017 uint32_t tx_8192_9216_byte_packets; /* dword 63*/ 3018 uint32_t rxpp_fifo_overflow_drop; /* dword 64*/ 3019 uint32_t rx_input_fifo_overflow_drop; /* dword 65*/ 3020 }; 3021 3022 3023 struct oce_rxf_stats_v0 { 3024 struct oce_port_rxf_stats_v0 port[2]; 3025 uint32_t rx_drops_no_pbuf; /* dword 132*/ 3026 uint32_t rx_drops_no_txpb; /* dword 133*/ 3027 uint32_t rx_drops_no_erx_descr; /* dword 134*/ 3028 uint32_t rx_drops_no_tpre_descr; /* dword 135*/ 3029 uint32_t management_rx_port_packets; /* dword 136*/ 3030 uint32_t management_rx_port_bytes; /* dword 137*/ 3031 uint32_t management_rx_port_pause_frames;/* dword 138*/ 3032 uint32_t management_rx_port_errors; /* dword 139*/ 3033 uint32_t management_tx_port_packets; /* dword 140*/ 3034 uint32_t management_tx_port_bytes; /* dword 141*/ 3035 uint32_t management_tx_port_pause; /* dword 142*/ 3036 uint32_t management_rx_port_rxfifo_overflow; /* dword 143*/ 3037 uint32_t rx_drops_too_many_frags; /* dword 144*/ 3038 uint32_t rx_drops_invalid_ring; /* dword 145*/ 3039 uint32_t forwarded_packets; /* dword 146*/ 3040 uint32_t rx_drops_mtu; /* dword 147*/ 3041 uint32_t rsvd0[7]; 3042 uint32_t port0_jabber_events; 3043 uint32_t port1_jabber_events; 3044 uint32_t rsvd1[6]; 3045 }; 3046 3047 struct oce_port_rxf_stats_v2 { 3048 uint32_t rsvd0[10]; 3049 uint32_t roce_bytes_received_lsd; 3050 uint32_t roce_bytes_received_msd; 3051 uint32_t rsvd1[5]; 3052 uint32_t roce_frames_received; 3053 uint32_t rx_crc_errors; 3054 uint32_t rx_alignment_symbol_errors; 3055 uint32_t rx_pause_frames; 3056 uint32_t rx_priority_pause_frames; 3057 uint32_t rx_control_frames; 3058 uint32_t rx_in_range_errors; 3059 uint32_t rx_out_range_errors; 3060 uint32_t rx_frame_too_long; 3061 uint32_t rx_address_match_errors; 3062 uint32_t rx_dropped_too_small; 3063 uint32_t rx_dropped_too_short; 3064 uint32_t rx_dropped_header_too_small; 3065 uint32_t rx_dropped_tcp_length; 3066 uint32_t rx_dropped_runt; 3067 uint32_t rsvd2[10]; 3068 uint32_t rx_ip_checksum_errs; 3069 uint32_t rx_tcp_checksum_errs; 3070 uint32_t rx_udp_checksum_errs; 3071 uint32_t rsvd3[7]; 3072 uint32_t rx_switched_unicast_packets; 3073 uint32_t rx_switched_multicast_packets; 3074 uint32_t rx_switched_broadcast_packets; 3075 uint32_t rsvd4[3]; 3076 uint32_t tx_pauseframes; 3077 uint32_t tx_priority_pauseframes; 3078 uint32_t tx_controlframes; 3079 uint32_t rsvd5[10]; 3080 uint32_t rxpp_fifo_overflow_drop; 3081 uint32_t rx_input_fifo_overflow_drop; 3082 uint32_t pmem_fifo_overflow_drop; 3083 uint32_t jabber_events; 3084 uint32_t rsvd6[3]; 3085 uint32_t rx_drops_payload_size; 3086 uint32_t rx_drops_clipped_header; 3087 uint32_t rx_drops_crc; 3088 uint32_t roce_drops_payload_len; 3089 uint32_t roce_drops_crc; 3090 uint32_t rsvd7[19]; 3091 }; 3092 3093 3094 struct oce_port_rxf_stats_v1 { 3095 uint32_t rsvd0[12]; 3096 uint32_t rx_crc_errors; 3097 uint32_t rx_alignment_symbol_errors; 3098 uint32_t rx_pause_frames; 3099 uint32_t rx_priority_pause_frames; 3100 uint32_t rx_control_frames; 3101 uint32_t rx_in_range_errors; 3102 uint32_t rx_out_range_errors; 3103 uint32_t rx_frame_too_long; 3104 uint32_t rx_address_match_errors; 3105 uint32_t rx_dropped_too_small; 3106 uint32_t rx_dropped_too_short; 3107 uint32_t rx_dropped_header_too_small; 3108 uint32_t rx_dropped_tcp_length; 3109 uint32_t rx_dropped_runt; 3110 uint32_t rsvd1[10]; 3111 uint32_t rx_ip_checksum_errs; 3112 uint32_t rx_tcp_checksum_errs; 3113 uint32_t rx_udp_checksum_errs; 3114 uint32_t rsvd2[7]; 3115 uint32_t rx_switched_unicast_packets; 3116 uint32_t rx_switched_multicast_packets; 3117 uint32_t rx_switched_broadcast_packets; 3118 uint32_t rsvd3[3]; 3119 uint32_t tx_pauseframes; 3120 uint32_t tx_priority_pauseframes; 3121 uint32_t tx_controlframes; 3122 uint32_t rsvd4[10]; 3123 uint32_t rxpp_fifo_overflow_drop; 3124 uint32_t rx_input_fifo_overflow_drop; 3125 uint32_t pmem_fifo_overflow_drop; 3126 uint32_t jabber_events; 3127 uint32_t rsvd5[3]; 3128 }; 3129 3130 struct oce_rxf_stats_v2 { 3131 struct oce_port_rxf_stats_v2 port[4]; 3132 uint32_t rsvd0[2]; 3133 uint32_t rx_drops_no_pbuf; 3134 uint32_t rx_drops_no_txpb; 3135 uint32_t rx_drops_no_erx_descr; 3136 uint32_t rx_drops_no_tpre_descr; 3137 uint32_t rsvd1[6]; 3138 uint32_t rx_drops_too_many_frags; 3139 uint32_t rx_drops_invalid_ring; 3140 uint32_t forwarded_packets; 3141 uint32_t rx_drops_mtu; 3142 uint32_t rsvd2[35]; 3143 }; 3144 3145 struct oce_rxf_stats_v1 { 3146 struct oce_port_rxf_stats_v1 port[4]; 3147 uint32_t rsvd0[2]; 3148 uint32_t rx_drops_no_pbuf; 3149 uint32_t rx_drops_no_txpb; 3150 uint32_t rx_drops_no_erx_descr; 3151 uint32_t rx_drops_no_tpre_descr; 3152 uint32_t rsvd1[6]; 3153 uint32_t rx_drops_too_many_frags; 3154 uint32_t rx_drops_invalid_ring; 3155 uint32_t forwarded_packets; 3156 uint32_t rx_drops_mtu; 3157 uint32_t rsvd2[14]; 3158 }; 3159 3160 struct oce_erx_stats_v2 { 3161 uint32_t rx_drops_no_fragments[136]; 3162 uint32_t rsvd[3]; 3163 }; 3164 3165 struct oce_erx_stats_v1 { 3166 uint32_t rx_drops_no_fragments[68]; 3167 uint32_t rsvd[4]; 3168 }; 3169 3170 3171 struct oce_erx_stats_v0 { 3172 uint32_t rx_drops_no_fragments[44]; 3173 uint32_t rsvd[4]; 3174 }; 3175 3176 struct oce_pmem_stats { 3177 uint32_t eth_red_drops; 3178 uint32_t rsvd[5]; 3179 }; 3180 3181 struct oce_hw_stats_v2 { 3182 struct oce_rxf_stats_v2 rxf; 3183 uint32_t rsvd0[OCE_TXP_SW_SZ]; 3184 struct oce_erx_stats_v2 erx; 3185 struct oce_pmem_stats pmem; 3186 uint32_t rsvd1[18]; 3187 }; 3188 3189 3190 struct oce_hw_stats_v1 { 3191 struct oce_rxf_stats_v1 rxf; 3192 uint32_t rsvd0[OCE_TXP_SW_SZ]; 3193 struct oce_erx_stats_v1 erx; 3194 struct oce_pmem_stats pmem; 3195 uint32_t rsvd1[18]; 3196 }; 3197 3198 struct oce_hw_stats_v0 { 3199 struct oce_rxf_stats_v0 rxf; 3200 uint32_t rsvd[48]; 3201 struct oce_erx_stats_v0 erx; 3202 struct oce_pmem_stats pmem; 3203 }; 3204 3205 #define MBX_GET_NIC_STATS(version) \ 3206 struct mbx_get_nic_stats_v##version { \ 3207 struct mbx_hdr hdr; \ 3208 union { \ 3209 struct { \ 3210 uint32_t rsvd0; \ 3211 } req; \ 3212 union { \ 3213 struct oce_hw_stats_v##version stats; \ 3214 } rsp; \ 3215 } params; \ 3216 } 3217 3218 MBX_GET_NIC_STATS(0); 3219 MBX_GET_NIC_STATS(1); 3220 MBX_GET_NIC_STATS(2); 3221 3222 /* [18(0x12)] NIC_GET_PPORT_STATS */ 3223 struct pport_stats { 3224 uint64_t tx_pkts; 3225 uint64_t tx_unicast_pkts; 3226 uint64_t tx_multicast_pkts; 3227 uint64_t tx_broadcast_pkts; 3228 uint64_t tx_bytes; 3229 uint64_t tx_unicast_bytes; 3230 uint64_t tx_multicast_bytes; 3231 uint64_t tx_broadcast_bytes; 3232 uint64_t tx_discards; 3233 uint64_t tx_errors; 3234 uint64_t tx_pause_frames; 3235 uint64_t tx_pause_on_frames; 3236 uint64_t tx_pause_off_frames; 3237 uint64_t tx_internal_mac_errors; 3238 uint64_t tx_control_frames; 3239 uint64_t tx_pkts_64_bytes; 3240 uint64_t tx_pkts_65_to_127_bytes; 3241 uint64_t tx_pkts_128_to_255_bytes; 3242 uint64_t tx_pkts_256_to_511_bytes; 3243 uint64_t tx_pkts_512_to_1023_bytes; 3244 uint64_t tx_pkts_1024_to_1518_bytes; 3245 uint64_t tx_pkts_1519_to_2047_bytes; 3246 uint64_t tx_pkts_2048_to_4095_bytes; 3247 uint64_t tx_pkts_4096_to_8191_bytes; 3248 uint64_t tx_pkts_8192_to_9216_bytes; 3249 uint64_t tx_lso_pkts; 3250 uint64_t rx_pkts; 3251 uint64_t rx_unicast_pkts; 3252 uint64_t rx_multicast_pkts; 3253 uint64_t rx_broadcast_pkts; 3254 uint64_t rx_bytes; 3255 uint64_t rx_unicast_bytes; 3256 uint64_t rx_multicast_bytes; 3257 uint64_t rx_broadcast_bytes; 3258 uint32_t rx_unknown_protos; 3259 uint32_t reserved_word69; 3260 uint64_t rx_discards; 3261 uint64_t rx_errors; 3262 uint64_t rx_crc_errors; 3263 uint64_t rx_alignment_errors; 3264 uint64_t rx_symbol_errors; 3265 uint64_t rx_pause_frames; 3266 uint64_t rx_pause_on_frames; 3267 uint64_t rx_pause_off_frames; 3268 uint64_t rx_frames_too_long; 3269 uint64_t rx_internal_mac_errors; 3270 uint32_t rx_undersize_pkts; 3271 uint32_t rx_oversize_pkts; 3272 uint32_t rx_fragment_pkts; 3273 uint32_t rx_jabbers; 3274 uint64_t rx_control_frames; 3275 uint64_t rx_control_frames_unknown_opcode; 3276 uint32_t rx_in_range_errors; 3277 uint32_t rx_out_of_range_errors; 3278 uint32_t rx_address_match_errors; 3279 uint32_t rx_vlan_mismatch_errors; 3280 uint32_t rx_dropped_too_small; 3281 uint32_t rx_dropped_too_short; 3282 uint32_t rx_dropped_header_too_small; 3283 uint32_t rx_dropped_invalid_tcp_length; 3284 uint32_t rx_dropped_runt; 3285 uint32_t rx_ip_checksum_errors; 3286 uint32_t rx_tcp_checksum_errors; 3287 uint32_t rx_udp_checksum_errors; 3288 uint32_t rx_non_rss_pkts; 3289 uint64_t reserved_word111; 3290 uint64_t rx_ipv4_pkts; 3291 uint64_t rx_ipv6_pkts; 3292 uint64_t rx_ipv4_bytes; 3293 uint64_t rx_ipv6_bytes; 3294 uint64_t rx_nic_pkts; 3295 uint64_t rx_tcp_pkts; 3296 uint64_t rx_iscsi_pkts; 3297 uint64_t rx_management_pkts; 3298 uint64_t rx_switched_unicast_pkts; 3299 uint64_t rx_switched_multicast_pkts; 3300 uint64_t rx_switched_broadcast_pkts; 3301 uint64_t num_forwards; 3302 uint32_t rx_fifo_overflow; 3303 uint32_t rx_input_fifo_overflow; 3304 uint64_t rx_drops_too_many_frags; 3305 uint32_t rx_drops_invalid_queue; 3306 uint32_t reserved_word141; 3307 uint64_t rx_drops_mtu; 3308 uint64_t rx_pkts_64_bytes; 3309 uint64_t rx_pkts_65_to_127_bytes; 3310 uint64_t rx_pkts_128_to_255_bytes; 3311 uint64_t rx_pkts_256_to_511_bytes; 3312 uint64_t rx_pkts_512_to_1023_bytes; 3313 uint64_t rx_pkts_1024_to_1518_bytes; 3314 uint64_t rx_pkts_1519_to_2047_bytes; 3315 uint64_t rx_pkts_2048_to_4095_bytes; 3316 uint64_t rx_pkts_4096_to_8191_bytes; 3317 uint64_t rx_pkts_8192_to_9216_bytes; 3318 }; 3319 3320 struct mbx_get_pport_stats { 3321 /* dw0 - dw3 */ 3322 struct mbx_hdr hdr; 3323 union { 3324 struct { 3325 /* dw4 */ 3326 #ifdef _BIG_ENDIAN 3327 uint32_t reset_stats:8; 3328 uint32_t rsvd0:8; 3329 uint32_t port_number:16; 3330 #else 3331 uint32_t port_number:16; 3332 uint32_t rsvd0:8; 3333 uint32_t reset_stats:8; 3334 #endif 3335 } req; 3336 3337 union { 3338 struct pport_stats pps; 3339 uint32_t pport_stats[164 - 4 + 1]; 3340 } rsp; 3341 } params; 3342 }; 3343 3344 /* [19(0x13)] NIC_GET_VPORT_STATS */ 3345 struct vport_stats { 3346 uint64_t tx_pkts; 3347 uint64_t tx_unicast_pkts; 3348 uint64_t tx_multicast_pkts; 3349 uint64_t tx_broadcast_pkts; 3350 uint64_t tx_bytes; 3351 uint64_t tx_unicast_bytes; 3352 uint64_t tx_multicast_bytes; 3353 uint64_t tx_broadcast_bytes; 3354 uint64_t tx_discards; 3355 uint64_t tx_errors; 3356 uint64_t tx_pkts_64_bytes; 3357 uint64_t tx_pkts_65_to_127_bytes; 3358 uint64_t tx_pkts_128_to_255_bytes; 3359 uint64_t tx_pkts_256_to_511_bytes; 3360 uint64_t tx_pkts_512_to_1023_bytes; 3361 uint64_t tx_pkts_1024_to_1518_bytes; 3362 uint64_t tx_pkts_1519_to_9699_bytes; 3363 uint64_t tx_pkts_over_9699_bytes; 3364 uint64_t rx_pkts; 3365 uint64_t rx_unicast_pkts; 3366 uint64_t rx_multicast_pkts; 3367 uint64_t rx_broadcast_pkts; 3368 uint64_t rx_bytes; 3369 uint64_t rx_unicast_bytes; 3370 uint64_t rx_multicast_bytes; 3371 uint64_t rx_broadcast_bytes; 3372 uint64_t rx_discards; 3373 uint64_t rx_errors; 3374 uint64_t rx_pkts_64_bytes; 3375 uint64_t rx_pkts_65_to_127_bytes; 3376 uint64_t rx_pkts_128_to_255_bytes; 3377 uint64_t rx_pkts_256_to_511_bytes; 3378 uint64_t rx_pkts_512_to_1023_bytes; 3379 uint64_t rx_pkts_1024_to_1518_bytes; 3380 uint64_t rx_pkts_1519_to_9699_bytes; 3381 uint64_t rx_pkts_gt_9699_bytes; 3382 }; 3383 struct mbx_get_vport_stats { 3384 /* dw0 - dw3 */ 3385 struct mbx_hdr hdr; 3386 union { 3387 struct { 3388 /* dw4 */ 3389 #ifdef _BIG_ENDIAN 3390 uint32_t reset_stats:8; 3391 uint32_t rsvd0:8; 3392 uint32_t vport_number:16; 3393 #else 3394 uint32_t vport_number:16; 3395 uint32_t rsvd0:8; 3396 uint32_t reset_stats:8; 3397 #endif 3398 } req; 3399 3400 union { 3401 struct vport_stats vps; 3402 uint32_t vport_stats[75 - 4 + 1]; 3403 } rsp; 3404 } params; 3405 }; 3406 3407 /** 3408 * @brief [20(0x14)] NIC_GET_QUEUE_STATS 3409 * The significant difference between vPort and Queue statistics is 3410 * the packet byte counters. 3411 */ 3412 struct queue_stats { 3413 uint64_t packets; 3414 uint64_t bytes; 3415 uint64_t errors; 3416 uint64_t drops; 3417 uint64_t buffer_errors; /* rsvd when tx */ 3418 }; 3419 3420 #define QUEUE_TYPE_WQ 0 3421 #define QUEUE_TYPE_RQ 1 3422 #define QUEUE_TYPE_HDS_RQ 1 /* same as RQ */ 3423 3424 struct mbx_get_queue_stats { 3425 /* dw0 - dw3 */ 3426 struct mbx_hdr hdr; 3427 union { 3428 struct { 3429 /* dw4 */ 3430 #ifdef _BIG_ENDIAN 3431 uint32_t reset_stats:8; 3432 uint32_t queue_type:8; 3433 uint32_t queue_id:16; 3434 #else 3435 uint32_t queue_id:16; 3436 uint32_t queue_type:8; 3437 uint32_t reset_stats:8; 3438 #endif 3439 } req; 3440 3441 union { 3442 struct queue_stats qs; 3443 uint32_t queue_stats[13 - 4 + 1]; 3444 } rsp; 3445 } params; 3446 }; 3447 3448 3449 /* [01] NIC_CONFIG_RSS */ 3450 #define OCE_HASH_TBL_SZ 10 3451 #define OCE_CPU_TBL_SZ 128 3452 #define OCE_FLUSH 1 /* RSS flush completion per CQ port */ 3453 struct mbx_config_nic_rss { 3454 struct mbx_hdr hdr; 3455 union { 3456 struct { 3457 #ifdef _BIG_ENDIAN 3458 uint32_t if_id; 3459 uint16_t cpu_tbl_sz_log2; 3460 uint16_t enable_rss; 3461 uint32_t hash[OCE_HASH_TBL_SZ]; 3462 uint8_t cputable[OCE_CPU_TBL_SZ]; 3463 uint8_t rsvd[3]; 3464 uint8_t flush; 3465 #else 3466 uint32_t if_id; 3467 uint16_t enable_rss; 3468 uint16_t cpu_tbl_sz_log2; 3469 uint32_t hash[OCE_HASH_TBL_SZ]; 3470 uint8_t cputable[OCE_CPU_TBL_SZ]; 3471 uint8_t flush; 3472 uint8_t rsvd[3]; 3473 #endif 3474 } req; 3475 struct { 3476 uint8_t rsvd[3]; 3477 uint8_t rss_bank; 3478 } rsp; 3479 } params; 3480 }; 3481 3482 3483 #pragma pack() 3484 3485 3486 typedef uint32_t oce_stat_t; /* statistic counter */ 3487 3488 enum OCE_RXF_PORT_STATS { 3489 RXF_RX_BYTES_LSD, 3490 RXF_RX_BYTES_MSD, 3491 RXF_RX_TOTAL_FRAMES, 3492 RXF_RX_UNICAST_FRAMES, 3493 RXF_RX_MULTICAST_FRAMES, 3494 RXF_RX_BROADCAST_FRAMES, 3495 RXF_RX_CRC_ERRORS, 3496 RXF_RX_ALIGNMENT_SYMBOL_ERRORS, 3497 RXF_RX_PAUSE_FRAMES, 3498 RXF_RX_CONTROL_FRAMES, 3499 RXF_RX_IN_RANGE_ERRORS, 3500 RXF_RX_OUT_RANGE_ERRORS, 3501 RXF_RX_FRAME_TOO_LONG, 3502 RXF_RX_ADDRESS_MATCH_ERRORS, 3503 RXF_RX_VLAN_MISMATCH, 3504 RXF_RX_DROPPED_TOO_SMALL, 3505 RXF_RX_DROPPED_TOO_SHORT, 3506 RXF_RX_DROPPED_HEADER_TOO_SMALL, 3507 RXF_RX_DROPPED_TCP_LENGTH, 3508 RXF_RX_DROPPED_RUNT, 3509 RXF_RX_64_BYTE_PACKETS, 3510 RXF_RX_65_127_BYTE_PACKETS, 3511 RXF_RX_128_256_BYTE_PACKETS, 3512 RXF_RX_256_511_BYTE_PACKETS, 3513 RXF_RX_512_1023_BYTE_PACKETS, 3514 RXF_RX_1024_1518_BYTE_PACKETS, 3515 RXF_RX_1519_2047_BYTE_PACKETS, 3516 RXF_RX_2048_4095_BYTE_PACKETS, 3517 RXF_RX_4096_8191_BYTE_PACKETS, 3518 RXF_RX_8192_9216_BYTE_PACKETS, 3519 RXF_RX_IP_CHECKSUM_ERRS, 3520 RXF_RX_TCP_CHECKSUM_ERRS, 3521 RXF_RX_UDP_CHECKSUM_ERRS, 3522 RXF_RX_NON_RSS_PACKETS, 3523 RXF_RX_IPV4_PACKETS, 3524 RXF_RX_IPV6_PACKETS, 3525 RXF_RX_IPV4_BYTES_LSD, 3526 RXF_RX_IPV4_BYTES_MSD, 3527 RXF_RX_IPV6_BYTES_LSD, 3528 RXF_RX_IPV6_BYTES_MSD, 3529 RXF_RX_CHUTE1_PACKETS, 3530 RXF_RX_CHUTE2_PACKETS, 3531 RXF_RX_CHUTE3_PACKETS, 3532 RXF_RX_MANAGEMENT_PACKETS, 3533 RXF_RX_SWITCHED_UNICAST_PACKETS, 3534 RXF_RX_SWITCHED_MULTICAST_PACKETS, 3535 RXF_RX_SWITCHED_BROADCAST_PACKETS, 3536 RXF_TX_BYTES_LSD, 3537 RXF_TX_BYTES_MSD, 3538 RXF_TX_UNICAST_FRAMES, 3539 RXF_TX_MULTICAST_FRAMES, 3540 RXF_TX_BROADCAST_FRAMES, 3541 RXF_TX_PAUSE_FRAMES, 3542 RXF_TX_CONTROL_FRAMES, 3543 RXF_TX_64_BYTE_PACKETS, 3544 RXF_TX_65_127_BYTE_PACKETS, 3545 RXF_TX_128_256_BYTE_PACKETS, 3546 RXF_TX_256_511_BYTE_PACKETS, 3547 RXF_TX_512_1023_BYTE_PACKETS, 3548 RXF_TX_1024_1518_BYTE_PACKETS, 3549 RXF_TX_1519_2047_BYTE_PACKETS, 3550 RXF_TX_2048_4095_BYTE_PACKETS, 3551 RXF_TX_4096_8191_BYTE_PACKETS, 3552 RXF_TX_8192_9216_BYTE_PACKETS, 3553 RXF_RX_FIFO_OVERFLOW, 3554 RXF_RX_INPUT_FIFO_OVERFLOW, 3555 RXF_PORT_STATS_N_WORDS 3556 }; 3557 3558 enum OCE_RXF_ADDL_STATS { 3559 RXF_RX_DROPS_NO_PBUF, 3560 RXF_RX_DROPS_NO_TXPB, 3561 RXF_RX_DROPS_NO_ERX_DESCR, 3562 RXF_RX_DROPS_NO_TPRE_DESCR, 3563 RXF_MANAGEMENT_RX_PORT_PACKETS, 3564 RXF_MANAGEMENT_RX_PORT_BYTES, 3565 RXF_MANAGEMENT_RX_PORT_PAUSE_FRAMES, 3566 RXF_MANAGEMENT_RX_PORT_ERRORS, 3567 RXF_MANAGEMENT_TX_PORT_PACKETS, 3568 RXF_MANAGEMENT_TX_PORT_BYTES, 3569 RXF_MANAGEMENT_TX_PORT_PAUSE, 3570 RXF_MANAGEMENT_RX_PORT_RXFIFO_OVERFLOW, 3571 RXF_RX_DROPS_TOO_MANY_FRAGS, 3572 RXF_RX_DROPS_INVALID_RING, 3573 RXF_FORWARDED_PACKETS, 3574 RXF_RX_DROPS_MTU, 3575 RXF_ADDL_STATS_N_WORDS 3576 }; 3577 3578 enum OCE_TX_CHUTE_PORT_STATS { 3579 CTPT_XMT_IPV4_PKTS, 3580 CTPT_XMT_IPV4_LSD, 3581 CTPT_XMT_IPV4_MSD, 3582 CTPT_XMT_IPV6_PKTS, 3583 CTPT_XMT_IPV6_LSD, 3584 CTPT_XMT_IPV6_MSD, 3585 CTPT_REXMT_IPV4_PKTs, 3586 CTPT_REXMT_IPV4_LSD, 3587 CTPT_REXMT_IPV4_MSD, 3588 CTPT_REXMT_IPV6_PKTs, 3589 CTPT_REXMT_IPV6_LSD, 3590 CTPT_REXMT_IPV6_MSD, 3591 CTPT_N_WORDS, 3592 }; 3593 3594 enum OCE_RX_ERR_STATS { 3595 RX_DROPS_NO_FRAGMENTS_0, 3596 RX_DROPS_NO_FRAGMENTS_1, 3597 RX_DROPS_NO_FRAGMENTS_2, 3598 RX_DROPS_NO_FRAGMENTS_3, 3599 RX_DROPS_NO_FRAGMENTS_4, 3600 RX_DROPS_NO_FRAGMENTS_5, 3601 RX_DROPS_NO_FRAGMENTS_6, 3602 RX_DROPS_NO_FRAGMENTS_7, 3603 RX_DROPS_NO_FRAGMENTS_8, 3604 RX_DROPS_NO_FRAGMENTS_9, 3605 RX_DROPS_NO_FRAGMENTS_10, 3606 RX_DROPS_NO_FRAGMENTS_11, 3607 RX_DROPS_NO_FRAGMENTS_12, 3608 RX_DROPS_NO_FRAGMENTS_13, 3609 RX_DROPS_NO_FRAGMENTS_14, 3610 RX_DROPS_NO_FRAGMENTS_15, 3611 RX_DROPS_NO_FRAGMENTS_16, 3612 RX_DROPS_NO_FRAGMENTS_17, 3613 RX_DROPS_NO_FRAGMENTS_18, 3614 RX_DROPS_NO_FRAGMENTS_19, 3615 RX_DROPS_NO_FRAGMENTS_20, 3616 RX_DROPS_NO_FRAGMENTS_21, 3617 RX_DROPS_NO_FRAGMENTS_22, 3618 RX_DROPS_NO_FRAGMENTS_23, 3619 RX_DROPS_NO_FRAGMENTS_24, 3620 RX_DROPS_NO_FRAGMENTS_25, 3621 RX_DROPS_NO_FRAGMENTS_26, 3622 RX_DROPS_NO_FRAGMENTS_27, 3623 RX_DROPS_NO_FRAGMENTS_28, 3624 RX_DROPS_NO_FRAGMENTS_29, 3625 RX_DROPS_NO_FRAGMENTS_30, 3626 RX_DROPS_NO_FRAGMENTS_31, 3627 RX_DROPS_NO_FRAGMENTS_32, 3628 RX_DROPS_NO_FRAGMENTS_33, 3629 RX_DROPS_NO_FRAGMENTS_34, 3630 RX_DROPS_NO_FRAGMENTS_35, 3631 RX_DROPS_NO_FRAGMENTS_36, 3632 RX_DROPS_NO_FRAGMENTS_37, 3633 RX_DROPS_NO_FRAGMENTS_38, 3634 RX_DROPS_NO_FRAGMENTS_39, 3635 RX_DROPS_NO_FRAGMENTS_40, 3636 RX_DROPS_NO_FRAGMENTS_41, 3637 RX_DROPS_NO_FRAGMENTS_42, 3638 RX_DROPS_NO_FRAGMENTS_43, 3639 RX_DEBUG_WDMA_SENT_HOLD, 3640 RX_DEBUG_WDMA_PBFREE_SENT_HOLD, 3641 RX_DEBUG_WDMA_0B_PBFREE_SENT_HOLD, 3642 RX_DEBUG_PMEM_PBUF_DEALLOC, 3643 RX_ERRORS_N_WORDS 3644 }; 3645 3646 enum OCE_PMEM_ERR_STATS { 3647 PMEM_ETH_RED_DROPS, 3648 PMEM_LRO_RED_DROPS, 3649 PMEM_ULP0_RED_DROPS, 3650 PMEM_ULP1_RED_DROPS, 3651 PMEM_GLOBAL_RED_DROPS, 3652 PMEM_ERRORS_N_WORDS 3653 }; 3654 3655 /** 3656 * @brief Statistics for a given Physical Port 3657 * These satisfy all the required BE2 statistics and also the 3658 * following MIB objects: 3659 * 3660 * RFC 2863 - The Interfaces Group MIB 3661 * RFC 2819 - Remote Network Monitoring Management Information Base (RMON) 3662 * RFC 3635 - Managed Objects for the Ethernet-like Interface Types 3663 * RFC 4502 - Remote Network Monitoring Mgmt Information Base Ver-2 (RMON2) 3664 * 3665 */ 3666 enum OCE_PPORT_STATS { 3667 PPORT_TX_PKTS = 0, 3668 PPORT_TX_UNICAST_PKTS = 2, 3669 PPORT_TX_MULTICAST_PKTS = 4, 3670 PPORT_TX_BROADCAST_PKTS = 6, 3671 PPORT_TX_BYTES = 8, 3672 PPORT_TX_UNICAST_BYTES = 10, 3673 PPORT_TX_MULTICAST_BYTES = 12, 3674 PPORT_TX_BROADCAST_BYTES = 14, 3675 PPORT_TX_DISCARDS = 16, 3676 PPORT_TX_ERRORS = 18, 3677 PPORT_TX_PAUSE_FRAMES = 20, 3678 PPORT_TX_PAUSE_ON_FRAMES = 22, 3679 PPORT_TX_PAUSE_OFF_FRAMES = 24, 3680 PPORT_TX_INTERNAL_MAC_ERRORS = 26, 3681 PPORT_TX_CONTROL_FRAMES = 28, 3682 PPORT_TX_PKTS_64_BYTES = 30, 3683 PPORT_TX_PKTS_65_TO_127_BYTES = 32, 3684 PPORT_TX_PKTS_128_TO_255_BYTES = 34, 3685 PPORT_TX_PKTS_256_TO_511_BYTES = 36, 3686 PPORT_TX_PKTS_512_TO_1023_BYTES = 38, 3687 PPORT_TX_PKTS_1024_TO_1518_BYTES = 40, 3688 PPORT_TX_PKTS_1519_TO_2047_BYTES = 42, 3689 PPORT_TX_PKTS_2048_TO_4095_BYTES = 44, 3690 PPORT_TX_PKTS_4096_TO_8191_BYTES = 46, 3691 PPORT_TX_PKTS_8192_TO_9216_BYTES = 48, 3692 PPORT_TX_LSO_PKTS = 50, 3693 PPORT_RX_PKTS = 52, 3694 PPORT_RX_UNICAST_PKTS = 54, 3695 PPORT_RX_MULTICAST_PKTS = 56, 3696 PPORT_RX_BROADCAST_PKTS = 58, 3697 PPORT_RX_BYTES = 60, 3698 PPORT_RX_UNICAST_BYTES = 62, 3699 PPORT_RX_MULTICAST_BYTES = 64, 3700 PPORT_RX_BROADCAST_BYTES = 66, 3701 PPORT_RX_UNKNOWN_PROTOS = 68, 3702 PPORT_RESERVED_WORD69 = 69, 3703 PPORT_RX_DISCARDS = 70, 3704 PPORT_RX_ERRORS = 72, 3705 PPORT_RX_CRC_ERRORS = 74, 3706 PPORT_RX_ALIGNMENT_ERRORS = 76, 3707 PPORT_RX_SYMBOL_ERRORS = 78, 3708 PPORT_RX_PAUSE_FRAMES = 80, 3709 PPORT_RX_PAUSE_ON_FRAMES = 82, 3710 PPORT_RX_PAUSE_OFF_FRAMES = 84, 3711 PPORT_RX_FRAMES_TOO_LONG = 86, 3712 PPORT_RX_INTERNAL_MAC_ERRORS = 88, 3713 PPORT_RX_UNDERSIZE_PKTS = 90, 3714 PPORT_RX_OVERSIZE_PKTS = 91, 3715 PPORT_RX_FRAGMENT_PKTS = 92, 3716 PPORT_RX_JABBERS = 93, 3717 PPORT_RX_CONTROL_FRAMES = 94, 3718 PPORT_RX_CONTROL_FRAMES_UNK_OPCODE = 96, 3719 PPORT_RX_IN_RANGE_ERRORS = 98, 3720 PPORT_RX_OUT_OF_RANGE_ERRORS = 99, 3721 PPORT_RX_ADDRESS_MATCH_ERRORS = 100, 3722 PPORT_RX_VLAN_MISMATCH_ERRORS = 101, 3723 PPORT_RX_DROPPED_TOO_SMALL = 102, 3724 PPORT_RX_DROPPED_TOO_SHORT = 103, 3725 PPORT_RX_DROPPED_HEADER_TOO_SMALL = 104, 3726 PPORT_RX_DROPPED_INVALID_TCP_LENGTH = 105, 3727 PPORT_RX_DROPPED_RUNT = 106, 3728 PPORT_RX_IP_CHECKSUM_ERRORS = 107, 3729 PPORT_RX_TCP_CHECKSUM_ERRORS = 108, 3730 PPORT_RX_UDP_CHECKSUM_ERRORS = 109, 3731 PPORT_RX_NON_RSS_PKTS = 110, 3732 PPORT_RESERVED_WORD111 = 111, 3733 PPORT_RX_IPV4_PKTS = 112, 3734 PPORT_RX_IPV6_PKTS = 114, 3735 PPORT_RX_IPV4_BYTES = 116, 3736 PPORT_RX_IPV6_BYTES = 118, 3737 PPORT_RX_NIC_PKTS = 120, 3738 PPORT_RX_TCP_PKTS = 122, 3739 PPORT_RX_ISCSI_PKTS = 124, 3740 PPORT_RX_MANAGEMENT_PKTS = 126, 3741 PPORT_RX_SWITCHED_UNICAST_PKTS = 128, 3742 PPORT_RX_SWITCHED_MULTICAST_PKTS = 130, 3743 PPORT_RX_SWITCHED_BROADCAST_PKTS = 132, 3744 PPORT_NUM_FORWARDS = 134, 3745 PPORT_RX_FIFO_OVERFLOW = 136, 3746 PPORT_RX_INPUT_FIFO_OVERFLOW = 137, 3747 PPORT_RX_DROPS_TOO_MANY_FRAGS = 138, 3748 PPORT_RX_DROPS_INVALID_QUEUE = 140, 3749 PPORT_RESERVED_WORD141 = 141, 3750 PPORT_RX_DROPS_MTU = 142, 3751 PPORT_RX_PKTS_64_BYTES = 144, 3752 PPORT_RX_PKTS_65_TO_127_BYTES = 146, 3753 PPORT_RX_PKTS_128_TO_255_BYTES = 148, 3754 PPORT_RX_PKTS_256_TO_511_BYTES = 150, 3755 PPORT_RX_PKTS_512_TO_1023_BYTES = 152, 3756 PPORT_RX_PKTS_1024_TO_1518_BYTES = 154, 3757 PPORT_RX_PKTS_1519_TO_2047_BYTES = 156, 3758 PPORT_RX_PKTS_2048_TO_4095_BYTES = 158, 3759 PPORT_RX_PKTS_4096_TO_8191_BYTES = 160, 3760 PPORT_RX_PKTS_8192_TO_9216_BYTES = 162, 3761 PPORT_N_WORDS = 164 3762 }; 3763 3764 /** 3765 * @brief Statistics for a given Virtual Port (vPort) 3766 * The following describes the vPort statistics satisfying 3767 * requirements of Linux/VMWare netdev statistics and 3768 * Microsoft Windows Statistics along with other Operating Systems. 3769 */ 3770 enum OCE_VPORT_STATS { 3771 VPORT_TX_PKTS = 0, 3772 VPORT_TX_UNICAST_PKTS = 2, 3773 VPORT_TX_MULTICAST_PKTS = 4, 3774 VPORT_TX_BROADCAST_PKTS = 6, 3775 VPORT_TX_BYTES = 8, 3776 VPORT_TX_UNICAST_BYTES = 10, 3777 VPORT_TX_MULTICAST_BYTES = 12, 3778 VPORT_TX_BROADCAST_BYTES = 14, 3779 VPORT_TX_DISCARDS = 16, 3780 VPORT_TX_ERRORS = 18, 3781 VPORT_TX_PKTS_64_BYTES = 20, 3782 VPORT_TX_PKTS_65_TO_127_BYTES = 22, 3783 VPORT_TX_PKTS_128_TO_255_BYTES = 24, 3784 VPORT_TX_PKTS_256_TO_511_BYTES = 26, 3785 VPORT_TX_PKTS_512_TO_1023_BYTEs = 28, 3786 VPORT_TX_PKTS_1024_TO_1518_BYTEs = 30, 3787 VPORT_TX_PKTS_1519_TO_9699_BYTEs = 32, 3788 VPORT_TX_PKTS_OVER_9699_BYTES = 34, 3789 VPORT_RX_PKTS = 36, 3790 VPORT_RX_UNICAST_PKTS = 38, 3791 VPORT_RX_MULTICAST_PKTS = 40, 3792 VPORT_RX_BROADCAST_PKTS = 42, 3793 VPORT_RX_BYTES = 44, 3794 VPORT_RX_UNICAST_BYTES = 46, 3795 VPORT_RX_MULTICAST_BYTES = 48, 3796 VPORT_RX_BROADCAST_BYTES = 50, 3797 VPORT_RX_DISCARDS = 52, 3798 VPORT_RX_ERRORS = 54, 3799 VPORT_RX_PKTS_64_BYTES = 56, 3800 VPORT_RX_PKTS_65_TO_127_BYTES = 58, 3801 VPORT_RX_PKTS_128_TO_255_BYTES = 60, 3802 VPORT_RX_PKTS_256_TO_511_BYTES = 62, 3803 VPORT_RX_PKTS_512_TO_1023_BYTEs = 64, 3804 VPORT_RX_PKTS_1024_TO_1518_BYTEs = 66, 3805 VPORT_RX_PKTS_1519_TO_9699_BYTEs = 68, 3806 VPORT_RX_PKTS_OVER_9699_BYTES = 70, 3807 VPORT_N_WORDS = 72 3808 }; 3809 3810 /** 3811 * @brief Statistics for a given queue (NIC WQ, RQ, or HDS RQ) 3812 * This set satisfies requirements of VMQare NetQueue and Microsoft VMQ 3813 */ 3814 enum OCE_QUEUE_TX_STATS { 3815 QUEUE_TX_PKTS = 0, 3816 QUEUE_TX_BYTES = 2, 3817 QUEUE_TX_ERRORS = 4, 3818 QUEUE_TX_DROPS = 6, 3819 QUEUE_TX_N_WORDS = 8 3820 }; 3821 3822 enum OCE_QUEUE_RX_STATS { 3823 QUEUE_RX_PKTS = 0, 3824 QUEUE_RX_BYTES = 2, 3825 QUEUE_RX_ERRORS = 4, 3826 QUEUE_RX_DROPS = 6, 3827 QUEUE_RX_BUFFER_ERRORS = 8, 3828 QUEUE_RX_N_WORDS = 10 3829 }; 3830 3831 /* HW LRO structures */ 3832 struct mbx_nic_query_lro_capabilities { 3833 struct mbx_hdr hdr; 3834 union { 3835 struct { 3836 uint32_t rsvd[6]; 3837 } req; 3838 struct { 3839 #ifdef _BIG_ENDIAN 3840 uint32_t lro_flags; 3841 uint16_t lro_rq_cnt; 3842 uint16_t plro_max_offload; 3843 uint32_t rsvd[4]; 3844 #else 3845 uint32_t lro_flags; 3846 uint16_t plro_max_offload; 3847 uint16_t lro_rq_cnt; 3848 uint32_t rsvd[4]; 3849 #endif 3850 } rsp; 3851 } params; 3852 }; 3853 3854 struct mbx_nic_set_iface_lro_config { 3855 struct mbx_hdr hdr; 3856 union { 3857 struct { 3858 #ifdef _BIG_ENDIAN 3859 uint32_t lro_flags; 3860 uint32_t iface_id; 3861 uint32_t max_clsc_byte_cnt; 3862 uint32_t max_clsc_seg_cnt; 3863 uint32_t max_clsc_usec_delay; 3864 uint32_t min_clsc_frame_byte_cnt; 3865 uint32_t rsvd[2]; 3866 #else 3867 uint32_t lro_flags; 3868 uint32_t iface_id; 3869 uint32_t max_clsc_byte_cnt; 3870 uint32_t max_clsc_seg_cnt; 3871 uint32_t max_clsc_usec_delay; 3872 uint32_t min_clsc_frame_byte_cnt; 3873 uint32_t rsvd[2]; 3874 #endif 3875 } req; 3876 struct { 3877 #ifdef _BIG_ENDIAN 3878 uint32_t lro_flags; 3879 uint32_t rsvd[7]; 3880 #else 3881 uint32_t lro_flags; 3882 uint32_t rsvd[7]; 3883 #endif 3884 } rsp; 3885 } params; 3886 }; 3887 3888 3889 struct mbx_create_nic_rq_v2 { 3890 struct mbx_hdr hdr; 3891 union { 3892 struct { 3893 #ifdef _BIG_ENDIAN 3894 uint8_t num_pages; 3895 uint8_t frag_size; 3896 uint16_t cq_id; 3897 3898 uint32_t if_id; 3899 3900 uint16_t page_size; 3901 uint16_t max_frame_size; 3902 3903 uint16_t rsvd; 3904 uint16_t pd_id; 3905 3906 uint16_t rsvd1; 3907 uint16_t rq_flags; 3908 3909 uint16_t hds_fixed_offset; 3910 uint8_t hds_start; 3911 uint8_t hds_frag; 3912 3913 uint16_t hds_backfill_size; 3914 uint16_t hds_frag_size; 3915 3916 uint32_t rbq_id; 3917 3918 uint32_t rsvd2[8]; 3919 3920 struct phys_addr pages[2]; 3921 #else 3922 uint16_t cq_id; 3923 uint8_t frag_size; 3924 uint8_t num_pages; 3925 3926 uint32_t if_id; 3927 3928 uint16_t max_frame_size; 3929 uint16_t page_size; 3930 3931 uint16_t pd_id; 3932 uint16_t rsvd; 3933 3934 uint16_t rq_flags; 3935 uint16_t rsvd1; 3936 3937 uint8_t hds_frag; 3938 uint8_t hds_start; 3939 uint16_t hds_fixed_offset; 3940 3941 uint16_t hds_frag_size; 3942 uint16_t hds_backfill_size; 3943 3944 uint32_t rbq_id; 3945 3946 uint32_t rsvd2[8]; 3947 3948 struct phys_addr pages[2]; 3949 #endif 3950 } req; 3951 struct { 3952 #ifdef _BIG_ENDIAN 3953 uint8_t rsvd0; 3954 uint8_t rss_cpuid; 3955 uint16_t rq_id; 3956 3957 uint8_t db_format; 3958 uint8_t db_reg_set; 3959 uint16_t rsvd1; 3960 3961 uint32_t db_offset; 3962 3963 uint32_t rsvd2; 3964 3965 uint16_t rsvd3; 3966 uint16_t rq_flags; 3967 3968 #else 3969 uint16_t rq_id; 3970 uint8_t rss_cpuid; 3971 uint8_t rsvd0; 3972 3973 uint16_t rsvd1; 3974 uint8_t db_reg_set; 3975 uint8_t db_format; 3976 3977 uint32_t db_offset; 3978 3979 uint32_t rsvd2; 3980 3981 uint16_t rq_flags; 3982 uint16_t rsvd3; 3983 #endif 3984 } rsp; 3985 3986 } params; 3987 }; 3988 3989 struct mbx_delete_nic_rq_v1 { 3990 struct mbx_hdr hdr; 3991 union { 3992 struct { 3993 #ifdef _BIG_ENDIAN 3994 uint16_t bypass_flush; 3995 uint16_t rq_id; 3996 uint16_t rsvd; 3997 uint16_t rq_flags; 3998 #else 3999 uint16_t rq_id; 4000 uint16_t bypass_flush; 4001 uint16_t rq_flags; 4002 uint16_t rsvd; 4003 #endif 4004 } req; 4005 struct { 4006 uint32_t rsvd[2]; 4007 } rsp; 4008 } params; 4009 }; 4010 4011 struct nic_hwlro_singleton_cqe { 4012 #ifdef _BIG_ENDIAN 4013 /* dw 0 */ 4014 uint32_t ip_opt:1; 4015 uint32_t vtp:1; 4016 uint32_t pkt_size:14; 4017 uint32_t vlan_tag:16; 4018 4019 /* dw 1 */ 4020 uint32_t num_frags:3; 4021 uint32_t rsvd1:3; 4022 uint32_t frag_index:10; 4023 uint32_t rsvd:8; 4024 uint32_t ipv6_frame:1; 4025 uint32_t l4_cksum_pass:1; 4026 uint32_t ip_cksum_pass:1; 4027 uint32_t udpframe:1; 4028 uint32_t tcpframe:1; 4029 uint32_t ipframe:1; 4030 uint32_t rss_hp:1; 4031 uint32_t error:1; 4032 4033 /* dw 2 */ 4034 uint32_t valid:1; 4035 uint32_t cqe_type:2; 4036 uint32_t debug:7; 4037 uint32_t rsvd4:6; 4038 uint32_t data_offset:8; 4039 uint32_t rsvd3:3; 4040 uint32_t rss_bank:1; 4041 uint32_t qnq:1; 4042 uint32_t rsvd2:3; 4043 4044 /* dw 3 */ 4045 uint32_t rss_hash_value; 4046 #else 4047 /* dw 0 */ 4048 uint32_t vlan_tag:16; 4049 uint32_t pkt_size:14; 4050 uint32_t vtp:1; 4051 uint32_t ip_opt:1; 4052 4053 /* dw 1 */ 4054 uint32_t error:1; 4055 uint32_t rss_hp:1; 4056 uint32_t ipframe:1; 4057 uint32_t tcpframe:1; 4058 uint32_t udpframe:1; 4059 uint32_t ip_cksum_pass:1; 4060 uint32_t l4_cksum_pass:1; 4061 uint32_t ipv6_frame:1; 4062 uint32_t rsvd:8; 4063 uint32_t frag_index:10; 4064 uint32_t rsvd1:3; 4065 uint32_t num_frags:3; 4066 4067 /* dw 2 */ 4068 uint32_t rsvd2:3; 4069 uint32_t qnq:1; 4070 uint32_t rss_bank:1; 4071 uint32_t rsvd3:3; 4072 uint32_t data_offset:8; 4073 uint32_t rsvd4:6; 4074 uint32_t debug:7; 4075 uint32_t cqe_type:2; 4076 uint32_t valid:1; 4077 4078 /* dw 3 */ 4079 uint32_t rss_hash_value; 4080 #endif 4081 }; 4082 4083 struct nic_hwlro_cqe_part1 { 4084 #ifdef _BIG_ENDIAN 4085 /* dw 0 */ 4086 uint32_t tcp_timestamp_val; 4087 4088 /* dw 1 */ 4089 uint32_t tcp_timestamp_ecr; 4090 4091 /* dw 2 */ 4092 uint32_t valid:1; 4093 uint32_t cqe_type:2; 4094 uint32_t rsvd3:7; 4095 uint32_t rss_policy:4; 4096 uint32_t rsvd2:2; 4097 uint32_t data_offset:8; 4098 uint32_t rsvd1:1; 4099 uint32_t lro_desc:1; 4100 uint32_t lro_timer_pop:1; 4101 uint32_t rss_bank:1; 4102 uint32_t qnq:1; 4103 uint32_t rsvd:2; 4104 uint32_t rss_flush:1; 4105 4106 /* dw 3 */ 4107 uint32_t rss_hash_value; 4108 #else 4109 /* dw 0 */ 4110 uint32_t tcp_timestamp_val; 4111 4112 /* dw 1 */ 4113 uint32_t tcp_timestamp_ecr; 4114 4115 /* dw 2 */ 4116 uint32_t rss_flush:1; 4117 uint32_t rsvd:2; 4118 uint32_t qnq:1; 4119 uint32_t rss_bank:1; 4120 uint32_t lro_timer_pop:1; 4121 uint32_t lro_desc:1; 4122 uint32_t rsvd1:1; 4123 uint32_t data_offset:8; 4124 uint32_t rsvd2:2; 4125 uint32_t rss_policy:4; 4126 uint32_t rsvd3:7; 4127 uint32_t cqe_type:2; 4128 uint32_t valid:1; 4129 4130 /* dw 3 */ 4131 uint32_t rss_hash_value; 4132 #endif 4133 }; 4134 4135 struct nic_hwlro_cqe_part2 { 4136 #ifdef _BIG_ENDIAN 4137 /* dw 0 */ 4138 uint32_t ip_opt:1; 4139 uint32_t vtp:1; 4140 uint32_t pkt_size:14; 4141 uint32_t vlan_tag:16; 4142 4143 /* dw 1 */ 4144 uint32_t tcp_window:16; 4145 uint32_t coalesced_size:16; 4146 4147 /* dw 2 */ 4148 uint32_t valid:1; 4149 uint32_t cqe_type:2; 4150 uint32_t rsvd:2; 4151 uint32_t push:1; 4152 uint32_t ts_opt:1; 4153 uint32_t threshold:1; 4154 uint32_t seg_cnt:8; 4155 uint32_t frame_lifespan:8; 4156 uint32_t ipv6_frame:1; 4157 uint32_t l4_cksum_pass:1; 4158 uint32_t ip_cksum_pass:1; 4159 uint32_t udpframe:1; 4160 uint32_t tcpframe:1; 4161 uint32_t ipframe:1; 4162 uint32_t rss_hp:1; 4163 uint32_t error:1; 4164 4165 /* dw 3 */ 4166 uint32_t tcp_ack_num; 4167 #else 4168 /* dw 0 */ 4169 uint32_t vlan_tag:16; 4170 uint32_t pkt_size:14; 4171 uint32_t vtp:1; 4172 uint32_t ip_opt:1; 4173 4174 /* dw 1 */ 4175 uint32_t coalesced_size:16; 4176 uint32_t tcp_window:16; 4177 4178 /* dw 2 */ 4179 uint32_t error:1; 4180 uint32_t rss_hp:1; 4181 uint32_t ipframe:1; 4182 uint32_t tcpframe:1; 4183 uint32_t udpframe:1; 4184 uint32_t ip_cksum_pass:1; 4185 uint32_t l4_cksum_pass:1; 4186 uint32_t ipv6_frame:1; 4187 uint32_t frame_lifespan:8; 4188 uint32_t seg_cnt:8; 4189 uint32_t threshold:1; 4190 uint32_t ts_opt:1; 4191 uint32_t push:1; 4192 uint32_t rsvd:2; 4193 uint32_t cqe_type:2; 4194 uint32_t valid:1; 4195 4196 /* dw 3 */ 4197 uint32_t tcp_ack_num; 4198 #endif 4199 }; 4200