1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2012-2013 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef __NVME_H__ 32 #define __NVME_H__ 33 34 #ifdef _KERNEL 35 #include <sys/types.h> 36 #endif 37 38 #include <sys/param.h> 39 #include <sys/endian.h> 40 41 #define NVME_PASSTHROUGH_CMD _IOWR('n', 0, struct nvme_pt_command) 42 #define NVME_RESET_CONTROLLER _IO('n', 1) 43 #define NVME_GET_NSID _IOR('n', 2, struct nvme_get_nsid) 44 #define NVME_GET_MAX_XFER_SIZE _IOR('n', 3, uint64_t) 45 46 #define NVME_IO_TEST _IOWR('n', 100, struct nvme_io_test) 47 #define NVME_BIO_TEST _IOWR('n', 101, struct nvme_io_test) 48 49 /* 50 * Macros to deal with NVME revisions, as defined VS register 51 */ 52 #define NVME_REV(x, y) (((x) << 16) | ((y) << 8)) 53 #define NVME_MAJOR(r) (((r) >> 16) & 0xffff) 54 #define NVME_MINOR(r) (((r) >> 8) & 0xff) 55 56 /* 57 * Use to mark a command to apply to all namespaces, or to retrieve global 58 * log pages. 59 */ 60 #define NVME_GLOBAL_NAMESPACE_TAG ((uint32_t)0xFFFFFFFF) 61 62 /* Cap transfers by the maximum addressable by page-sized PRP (4KB -> 2MB). */ 63 #define NVME_MAX_XFER_SIZE MIN(maxphys, (PAGE_SIZE/8*PAGE_SIZE)) 64 65 /* Register field definitions */ 66 #define NVME_CAP_LO_REG_MQES_SHIFT (0) 67 #define NVME_CAP_LO_REG_MQES_MASK (0xFFFF) 68 #define NVME_CAP_LO_REG_CQR_SHIFT (16) 69 #define NVME_CAP_LO_REG_CQR_MASK (0x1) 70 #define NVME_CAP_LO_REG_AMS_SHIFT (17) 71 #define NVME_CAP_LO_REG_AMS_MASK (0x3) 72 #define NVME_CAP_LO_REG_TO_SHIFT (24) 73 #define NVME_CAP_LO_REG_TO_MASK (0xFF) 74 #define NVME_CAP_LO_MQES(x) \ 75 (((x) >> NVME_CAP_LO_REG_MQES_SHIFT) & NVME_CAP_LO_REG_MQES_MASK) 76 #define NVME_CAP_LO_CQR(x) \ 77 (((x) >> NVME_CAP_LO_REG_CQR_SHIFT) & NVME_CAP_LO_REG_CQR_MASK) 78 #define NVME_CAP_LO_AMS(x) \ 79 (((x) >> NVME_CAP_LO_REG_AMS_SHIFT) & NVME_CAP_LO_REG_AMS_MASK) 80 #define NVME_CAP_LO_TO(x) \ 81 (((x) >> NVME_CAP_LO_REG_TO_SHIFT) & NVME_CAP_LO_REG_TO_MASK) 82 83 #define NVME_CAP_HI_REG_DSTRD_SHIFT (0) 84 #define NVME_CAP_HI_REG_DSTRD_MASK (0xF) 85 #define NVME_CAP_HI_REG_NSSRS_SHIFT (4) 86 #define NVME_CAP_HI_REG_NSSRS_MASK (0x1) 87 #define NVME_CAP_HI_REG_CSS_SHIFT (5) 88 #define NVME_CAP_HI_REG_CSS_MASK (0xff) 89 #define NVME_CAP_HI_REG_CSS_NVM_SHIFT (5) 90 #define NVME_CAP_HI_REG_CSS_NVM_MASK (0x1) 91 #define NVME_CAP_HI_REG_BPS_SHIFT (13) 92 #define NVME_CAP_HI_REG_BPS_MASK (0x1) 93 #define NVME_CAP_HI_REG_MPSMIN_SHIFT (16) 94 #define NVME_CAP_HI_REG_MPSMIN_MASK (0xF) 95 #define NVME_CAP_HI_REG_MPSMAX_SHIFT (20) 96 #define NVME_CAP_HI_REG_MPSMAX_MASK (0xF) 97 #define NVME_CAP_HI_REG_PMRS_SHIFT (24) 98 #define NVME_CAP_HI_REG_PMRS_MASK (0x1) 99 #define NVME_CAP_HI_REG_CMBS_SHIFT (25) 100 #define NVME_CAP_HI_REG_CMBS_MASK (0x1) 101 #define NVME_CAP_HI_DSTRD(x) \ 102 (((x) >> NVME_CAP_HI_REG_DSTRD_SHIFT) & NVME_CAP_HI_REG_DSTRD_MASK) 103 #define NVME_CAP_HI_NSSRS(x) \ 104 (((x) >> NVME_CAP_HI_REG_NSSRS_SHIFT) & NVME_CAP_HI_REG_NSSRS_MASK) 105 #define NVME_CAP_HI_CSS(x) \ 106 (((x) >> NVME_CAP_HI_REG_CSS_SHIFT) & NVME_CAP_HI_REG_CSS_MASK) 107 #define NVME_CAP_HI_CSS_NVM(x) \ 108 (((x) >> NVME_CAP_HI_REG_CSS_NVM_SHIFT) & NVME_CAP_HI_REG_CSS_NVM_MASK) 109 #define NVME_CAP_HI_BPS(x) \ 110 (((x) >> NVME_CAP_HI_REG_BPS_SHIFT) & NVME_CAP_HI_REG_BPS_MASK) 111 #define NVME_CAP_HI_MPSMIN(x) \ 112 (((x) >> NVME_CAP_HI_REG_MPSMIN_SHIFT) & NVME_CAP_HI_REG_MPSMIN_MASK) 113 #define NVME_CAP_HI_MPSMAX(x) \ 114 (((x) >> NVME_CAP_HI_REG_MPSMAX_SHIFT) & NVME_CAP_HI_REG_MPSMAX_MASK) 115 #define NVME_CAP_HI_PMRS(x) \ 116 (((x) >> NVME_CAP_HI_REG_PMRS_SHIFT) & NVME_CAP_HI_REG_PMRS_MASK) 117 #define NVME_CAP_HI_CMBS(x) \ 118 (((x) >> NVME_CAP_HI_REG_CMBS_SHIFT) & NVME_CAP_HI_REG_CMBS_MASK) 119 120 #define NVME_CC_REG_EN_SHIFT (0) 121 #define NVME_CC_REG_EN_MASK (0x1) 122 #define NVME_CC_REG_CSS_SHIFT (4) 123 #define NVME_CC_REG_CSS_MASK (0x7) 124 #define NVME_CC_REG_MPS_SHIFT (7) 125 #define NVME_CC_REG_MPS_MASK (0xF) 126 #define NVME_CC_REG_AMS_SHIFT (11) 127 #define NVME_CC_REG_AMS_MASK (0x7) 128 #define NVME_CC_REG_SHN_SHIFT (14) 129 #define NVME_CC_REG_SHN_MASK (0x3) 130 #define NVME_CC_REG_IOSQES_SHIFT (16) 131 #define NVME_CC_REG_IOSQES_MASK (0xF) 132 #define NVME_CC_REG_IOCQES_SHIFT (20) 133 #define NVME_CC_REG_IOCQES_MASK (0xF) 134 135 #define NVME_CSTS_REG_RDY_SHIFT (0) 136 #define NVME_CSTS_REG_RDY_MASK (0x1) 137 #define NVME_CSTS_REG_CFS_SHIFT (1) 138 #define NVME_CSTS_REG_CFS_MASK (0x1) 139 #define NVME_CSTS_REG_SHST_SHIFT (2) 140 #define NVME_CSTS_REG_SHST_MASK (0x3) 141 #define NVME_CSTS_REG_NVSRO_SHIFT (4) 142 #define NVME_CSTS_REG_NVSRO_MASK (0x1) 143 #define NVME_CSTS_REG_PP_SHIFT (5) 144 #define NVME_CSTS_REG_PP_MASK (0x1) 145 146 #define NVME_CSTS_GET_SHST(csts) (((csts) >> NVME_CSTS_REG_SHST_SHIFT) & NVME_CSTS_REG_SHST_MASK) 147 148 #define NVME_AQA_REG_ASQS_SHIFT (0) 149 #define NVME_AQA_REG_ASQS_MASK (0xFFF) 150 #define NVME_AQA_REG_ACQS_SHIFT (16) 151 #define NVME_AQA_REG_ACQS_MASK (0xFFF) 152 153 #define NVME_PMRCAP_REG_RDS_SHIFT (3) 154 #define NVME_PMRCAP_REG_RDS_MASK (0x1) 155 #define NVME_PMRCAP_REG_WDS_SHIFT (4) 156 #define NVME_PMRCAP_REG_WDS_MASK (0x1) 157 #define NVME_PMRCAP_REG_BIR_SHIFT (5) 158 #define NVME_PMRCAP_REG_BIR_MASK (0x7) 159 #define NVME_PMRCAP_REG_PMRTU_SHIFT (8) 160 #define NVME_PMRCAP_REG_PMRTU_MASK (0x3) 161 #define NVME_PMRCAP_REG_PMRWBM_SHIFT (10) 162 #define NVME_PMRCAP_REG_PMRWBM_MASK (0xf) 163 #define NVME_PMRCAP_REG_PMRTO_SHIFT (16) 164 #define NVME_PMRCAP_REG_PMRTO_MASK (0xff) 165 #define NVME_PMRCAP_REG_CMSS_SHIFT (24) 166 #define NVME_PMRCAP_REG_CMSS_MASK (0x1) 167 168 #define NVME_PMRCAP_RDS(x) \ 169 (((x) >> NVME_PMRCAP_REG_RDS_SHIFT) & NVME_PMRCAP_REG_RDS_MASK) 170 #define NVME_PMRCAP_WDS(x) \ 171 (((x) >> NVME_PMRCAP_REG_WDS_SHIFT) & NVME_PMRCAP_REG_WDS_MASK) 172 #define NVME_PMRCAP_BIR(x) \ 173 (((x) >> NVME_PMRCAP_REG_BIR_SHIFT) & NVME_PMRCAP_REG_BIR_MASK) 174 #define NVME_PMRCAP_PMRTU(x) \ 175 (((x) >> NVME_PMRCAP_REG_PMRTU_SHIFT) & NVME_PMRCAP_REG_PMRTU_MASK) 176 #define NVME_PMRCAP_PMRWBM(x) \ 177 (((x) >> NVME_PMRCAP_REG_PMRWBM_SHIFT) & NVME_PMRCAP_REG_PMRWBM_MASK) 178 #define NVME_PMRCAP_PMRTO(x) \ 179 (((x) >> NVME_PMRCAP_REG_PMRTO_SHIFT) & NVME_PMRCAP_REG_PMRTO_MASK) 180 #define NVME_PMRCAP_CMSS(x) \ 181 (((x) >> NVME_PMRCAP_REG_CMSS_SHIFT) & NVME_PMRCAP_REG_CMSS_MASK) 182 183 /* Command field definitions */ 184 185 #define NVME_CMD_FUSE_SHIFT (8) 186 #define NVME_CMD_FUSE_MASK (0x3) 187 188 #define NVME_STATUS_P_SHIFT (0) 189 #define NVME_STATUS_P_MASK (0x1) 190 #define NVME_STATUS_SC_SHIFT (1) 191 #define NVME_STATUS_SC_MASK (0xFF) 192 #define NVME_STATUS_SCT_SHIFT (9) 193 #define NVME_STATUS_SCT_MASK (0x7) 194 #define NVME_STATUS_CRD_SHIFT (12) 195 #define NVME_STATUS_CRD_MASK (0x3) 196 #define NVME_STATUS_M_SHIFT (14) 197 #define NVME_STATUS_M_MASK (0x1) 198 #define NVME_STATUS_DNR_SHIFT (15) 199 #define NVME_STATUS_DNR_MASK (0x1) 200 201 #define NVME_STATUS_GET_P(st) (((st) >> NVME_STATUS_P_SHIFT) & NVME_STATUS_P_MASK) 202 #define NVME_STATUS_GET_SC(st) (((st) >> NVME_STATUS_SC_SHIFT) & NVME_STATUS_SC_MASK) 203 #define NVME_STATUS_GET_SCT(st) (((st) >> NVME_STATUS_SCT_SHIFT) & NVME_STATUS_SCT_MASK) 204 #define NVME_STATUS_GET_M(st) (((st) >> NVME_STATUS_M_SHIFT) & NVME_STATUS_M_MASK) 205 #define NVME_STATUS_GET_DNR(st) (((st) >> NVME_STATUS_DNR_SHIFT) & NVME_STATUS_DNR_MASK) 206 207 #define NVME_PWR_ST_MPS_SHIFT (0) 208 #define NVME_PWR_ST_MPS_MASK (0x1) 209 #define NVME_PWR_ST_NOPS_SHIFT (1) 210 #define NVME_PWR_ST_NOPS_MASK (0x1) 211 #define NVME_PWR_ST_RRT_SHIFT (0) 212 #define NVME_PWR_ST_RRT_MASK (0x1F) 213 #define NVME_PWR_ST_RRL_SHIFT (0) 214 #define NVME_PWR_ST_RRL_MASK (0x1F) 215 #define NVME_PWR_ST_RWT_SHIFT (0) 216 #define NVME_PWR_ST_RWT_MASK (0x1F) 217 #define NVME_PWR_ST_RWL_SHIFT (0) 218 #define NVME_PWR_ST_RWL_MASK (0x1F) 219 #define NVME_PWR_ST_IPS_SHIFT (6) 220 #define NVME_PWR_ST_IPS_MASK (0x3) 221 #define NVME_PWR_ST_APW_SHIFT (0) 222 #define NVME_PWR_ST_APW_MASK (0x7) 223 #define NVME_PWR_ST_APS_SHIFT (6) 224 #define NVME_PWR_ST_APS_MASK (0x3) 225 226 /** Controller Multi-path I/O and Namespace Sharing Capabilities */ 227 /* More then one port */ 228 #define NVME_CTRLR_DATA_MIC_MPORTS_SHIFT (0) 229 #define NVME_CTRLR_DATA_MIC_MPORTS_MASK (0x1) 230 /* More then one controller */ 231 #define NVME_CTRLR_DATA_MIC_MCTRLRS_SHIFT (1) 232 #define NVME_CTRLR_DATA_MIC_MCTRLRS_MASK (0x1) 233 /* SR-IOV Virtual Function */ 234 #define NVME_CTRLR_DATA_MIC_SRIOVVF_SHIFT (2) 235 #define NVME_CTRLR_DATA_MIC_SRIOVVF_MASK (0x1) 236 /* Asymmetric Namespace Access Reporting */ 237 #define NVME_CTRLR_DATA_MIC_ANAR_SHIFT (3) 238 #define NVME_CTRLR_DATA_MIC_ANAR_MASK (0x1) 239 240 /** OAES - Optional Asynchronous Events Supported */ 241 /* supports Namespace Attribute Notices event */ 242 #define NVME_CTRLR_DATA_OAES_NS_ATTR_SHIFT (8) 243 #define NVME_CTRLR_DATA_OAES_NS_ATTR_MASK (0x1) 244 /* supports Firmware Activation Notices event */ 245 #define NVME_CTRLR_DATA_OAES_FW_ACTIVATE_SHIFT (9) 246 #define NVME_CTRLR_DATA_OAES_FW_ACTIVATE_MASK (0x1) 247 /* supports Asymmetric Namespace Access Change Notices event */ 248 #define NVME_CTRLR_DATA_OAES_ASYM_NS_CHANGE_SHIFT (11) 249 #define NVME_CTRLR_DATA_OAES_ASYM_NS_CHANGE_MASK (0x1) 250 /* supports Predictable Latency Event Aggregate Log Change Notices event */ 251 #define NVME_CTRLR_DATA_OAES_PREDICT_LATENCY_SHIFT (12) 252 #define NVME_CTRLR_DATA_OAES_PREDICT_LATENCY_MASK (0x1) 253 /* supports LBA Status Information Notices event */ 254 #define NVME_CTRLR_DATA_OAES_LBA_STATUS_SHIFT (13) 255 #define NVME_CTRLR_DATA_OAES_LBA_STATUS_MASK (0x1) 256 /* supports Endurance Group Event Aggregate Log Page Changes Notices event */ 257 #define NVME_CTRLR_DATA_OAES_ENDURANCE_GROUP_SHIFT (14) 258 #define NVME_CTRLR_DATA_OAES_ENDURANCE_GROUP_MASK (0x1) 259 /* supports Normal NVM Subsystem Shutdown event */ 260 #define NVME_CTRLR_DATA_OAES_NORMAL_SHUTDOWN_SHIFT (15) 261 #define NVME_CTRLR_DATA_OAES_NORMAL_SHUTDOWN_MASK (0x1) 262 /* supports Zone Descriptor Changed Notices event */ 263 #define NVME_CTRLR_DATA_OAES_ZONE_DESC_CHANGE_SHIFT (27) 264 #define NVME_CTRLR_DATA_OAES_ZONE_DESC_CHANGE_MASK (0x1) 265 /* supports Discovery Log Page Change Notification event */ 266 #define NVME_CTRLR_DATA_OAES_LOG_PAGE_CHANGE_SHIFT (31) 267 #define NVME_CTRLR_DATA_OAES_LOG_PAGE_CHANGE_MASK (0x1) 268 269 /** OACS - optional admin command support */ 270 /* supports security send/receive commands */ 271 #define NVME_CTRLR_DATA_OACS_SECURITY_SHIFT (0) 272 #define NVME_CTRLR_DATA_OACS_SECURITY_MASK (0x1) 273 /* supports format nvm command */ 274 #define NVME_CTRLR_DATA_OACS_FORMAT_SHIFT (1) 275 #define NVME_CTRLR_DATA_OACS_FORMAT_MASK (0x1) 276 /* supports firmware activate/download commands */ 277 #define NVME_CTRLR_DATA_OACS_FIRMWARE_SHIFT (2) 278 #define NVME_CTRLR_DATA_OACS_FIRMWARE_MASK (0x1) 279 /* supports namespace management commands */ 280 #define NVME_CTRLR_DATA_OACS_NSMGMT_SHIFT (3) 281 #define NVME_CTRLR_DATA_OACS_NSMGMT_MASK (0x1) 282 /* supports Device Self-test command */ 283 #define NVME_CTRLR_DATA_OACS_SELFTEST_SHIFT (4) 284 #define NVME_CTRLR_DATA_OACS_SELFTEST_MASK (0x1) 285 /* supports Directives */ 286 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_SHIFT (5) 287 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_MASK (0x1) 288 /* supports NVMe-MI Send/Receive */ 289 #define NVME_CTRLR_DATA_OACS_NVMEMI_SHIFT (6) 290 #define NVME_CTRLR_DATA_OACS_NVMEMI_MASK (0x1) 291 /* supports Virtualization Management */ 292 #define NVME_CTRLR_DATA_OACS_VM_SHIFT (7) 293 #define NVME_CTRLR_DATA_OACS_VM_MASK (0x1) 294 /* supports Doorbell Buffer Config */ 295 #define NVME_CTRLR_DATA_OACS_DBBUFFER_SHIFT (8) 296 #define NVME_CTRLR_DATA_OACS_DBBUFFER_MASK (0x1) 297 /* supports Get LBA Status */ 298 #define NVME_CTRLR_DATA_OACS_GETLBA_SHIFT (9) 299 #define NVME_CTRLR_DATA_OACS_GETLBA_MASK (0x1) 300 301 /** firmware updates */ 302 /* first slot is read-only */ 303 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_SHIFT (0) 304 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_MASK (0x1) 305 /* number of firmware slots */ 306 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_SHIFT (1) 307 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_MASK (0x7) 308 /* firmware activation without reset */ 309 #define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_SHIFT (4) 310 #define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_MASK (0x1) 311 312 /** log page attributes */ 313 /* per namespace smart/health log page */ 314 #define NVME_CTRLR_DATA_LPA_NS_SMART_SHIFT (0) 315 #define NVME_CTRLR_DATA_LPA_NS_SMART_MASK (0x1) 316 317 /** AVSCC - admin vendor specific command configuration */ 318 /* admin vendor specific commands use spec format */ 319 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_SHIFT (0) 320 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_MASK (0x1) 321 322 /** Autonomous Power State Transition Attributes */ 323 /* Autonomous Power State Transitions supported */ 324 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_SHIFT (0) 325 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_MASK (0x1) 326 327 /** Sanitize Capabilities */ 328 /* Crypto Erase Support */ 329 #define NVME_CTRLR_DATA_SANICAP_CES_SHIFT (0) 330 #define NVME_CTRLR_DATA_SANICAP_CES_MASK (0x1) 331 /* Block Erase Support */ 332 #define NVME_CTRLR_DATA_SANICAP_BES_SHIFT (1) 333 #define NVME_CTRLR_DATA_SANICAP_BES_MASK (0x1) 334 /* Overwrite Support */ 335 #define NVME_CTRLR_DATA_SANICAP_OWS_SHIFT (2) 336 #define NVME_CTRLR_DATA_SANICAP_OWS_MASK (0x1) 337 /* No-Deallocate Inhibited */ 338 #define NVME_CTRLR_DATA_SANICAP_NDI_SHIFT (29) 339 #define NVME_CTRLR_DATA_SANICAP_NDI_MASK (0x1) 340 /* No-Deallocate Modifies Media After Sanitize */ 341 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_SHIFT (30) 342 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_MASK (0x3) 343 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_UNDEF (0) 344 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_NO (1) 345 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_YES (2) 346 347 /** submission queue entry size */ 348 #define NVME_CTRLR_DATA_SQES_MIN_SHIFT (0) 349 #define NVME_CTRLR_DATA_SQES_MIN_MASK (0xF) 350 #define NVME_CTRLR_DATA_SQES_MAX_SHIFT (4) 351 #define NVME_CTRLR_DATA_SQES_MAX_MASK (0xF) 352 353 /** completion queue entry size */ 354 #define NVME_CTRLR_DATA_CQES_MIN_SHIFT (0) 355 #define NVME_CTRLR_DATA_CQES_MIN_MASK (0xF) 356 #define NVME_CTRLR_DATA_CQES_MAX_SHIFT (4) 357 #define NVME_CTRLR_DATA_CQES_MAX_MASK (0xF) 358 359 /** optional nvm command support */ 360 #define NVME_CTRLR_DATA_ONCS_COMPARE_SHIFT (0) 361 #define NVME_CTRLR_DATA_ONCS_COMPARE_MASK (0x1) 362 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_SHIFT (1) 363 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_MASK (0x1) 364 #define NVME_CTRLR_DATA_ONCS_DSM_SHIFT (2) 365 #define NVME_CTRLR_DATA_ONCS_DSM_MASK (0x1) 366 #define NVME_CTRLR_DATA_ONCS_WRZERO_SHIFT (3) 367 #define NVME_CTRLR_DATA_ONCS_WRZERO_MASK (0x1) 368 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_SHIFT (4) 369 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_MASK (0x1) 370 #define NVME_CTRLR_DATA_ONCS_RESERV_SHIFT (5) 371 #define NVME_CTRLR_DATA_ONCS_RESERV_MASK (0x1) 372 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_SHIFT (6) 373 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_MASK (0x1) 374 #define NVME_CTRLR_DATA_ONCS_VERIFY_SHIFT (7) 375 #define NVME_CTRLR_DATA_ONCS_VERIFY_MASK (0x1) 376 377 /** Fused Operation Support */ 378 #define NVME_CTRLR_DATA_FUSES_CNW_SHIFT (0) 379 #define NVME_CTRLR_DATA_FUSES_CNW_MASK (0x1) 380 381 /** Format NVM Attributes */ 382 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_SHIFT (0) 383 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_MASK (0x1) 384 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_SHIFT (1) 385 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_MASK (0x1) 386 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_SHIFT (2) 387 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_MASK (0x1) 388 389 /** volatile write cache */ 390 /* volatile write cache present */ 391 #define NVME_CTRLR_DATA_VWC_PRESENT_SHIFT (0) 392 #define NVME_CTRLR_DATA_VWC_PRESENT_MASK (0x1) 393 /* flush all namespaces supported */ 394 #define NVME_CTRLR_DATA_VWC_ALL_SHIFT (1) 395 #define NVME_CTRLR_DATA_VWC_ALL_MASK (0x3) 396 #define NVME_CTRLR_DATA_VWC_ALL_UNKNOWN (0) 397 #define NVME_CTRLR_DATA_VWC_ALL_NO (2) 398 #define NVME_CTRLR_DATA_VWC_ALL_YES (3) 399 400 /** namespace features */ 401 /* thin provisioning */ 402 #define NVME_NS_DATA_NSFEAT_THIN_PROV_SHIFT (0) 403 #define NVME_NS_DATA_NSFEAT_THIN_PROV_MASK (0x1) 404 /* NAWUN, NAWUPF, and NACWU fields are valid */ 405 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_SHIFT (1) 406 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_MASK (0x1) 407 /* Deallocated or Unwritten Logical Block errors supported */ 408 #define NVME_NS_DATA_NSFEAT_DEALLOC_SHIFT (2) 409 #define NVME_NS_DATA_NSFEAT_DEALLOC_MASK (0x1) 410 /* NGUID and EUI64 fields are not reusable */ 411 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_SHIFT (3) 412 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_MASK (0x1) 413 /* NPWG, NPWA, NPDG, NPDA, and NOWS are valid */ 414 #define NVME_NS_DATA_NSFEAT_NPVALID_SHIFT (4) 415 #define NVME_NS_DATA_NSFEAT_NPVALID_MASK (0x1) 416 417 /** formatted lba size */ 418 #define NVME_NS_DATA_FLBAS_FORMAT_SHIFT (0) 419 #define NVME_NS_DATA_FLBAS_FORMAT_MASK (0xF) 420 #define NVME_NS_DATA_FLBAS_EXTENDED_SHIFT (4) 421 #define NVME_NS_DATA_FLBAS_EXTENDED_MASK (0x1) 422 423 /** metadata capabilities */ 424 /* metadata can be transferred as part of data prp list */ 425 #define NVME_NS_DATA_MC_EXTENDED_SHIFT (0) 426 #define NVME_NS_DATA_MC_EXTENDED_MASK (0x1) 427 /* metadata can be transferred with separate metadata pointer */ 428 #define NVME_NS_DATA_MC_POINTER_SHIFT (1) 429 #define NVME_NS_DATA_MC_POINTER_MASK (0x1) 430 431 /** end-to-end data protection capabilities */ 432 /* protection information type 1 */ 433 #define NVME_NS_DATA_DPC_PIT1_SHIFT (0) 434 #define NVME_NS_DATA_DPC_PIT1_MASK (0x1) 435 /* protection information type 2 */ 436 #define NVME_NS_DATA_DPC_PIT2_SHIFT (1) 437 #define NVME_NS_DATA_DPC_PIT2_MASK (0x1) 438 /* protection information type 3 */ 439 #define NVME_NS_DATA_DPC_PIT3_SHIFT (2) 440 #define NVME_NS_DATA_DPC_PIT3_MASK (0x1) 441 /* first eight bytes of metadata */ 442 #define NVME_NS_DATA_DPC_MD_START_SHIFT (3) 443 #define NVME_NS_DATA_DPC_MD_START_MASK (0x1) 444 /* last eight bytes of metadata */ 445 #define NVME_NS_DATA_DPC_MD_END_SHIFT (4) 446 #define NVME_NS_DATA_DPC_MD_END_MASK (0x1) 447 448 /** end-to-end data protection type settings */ 449 /* protection information type */ 450 #define NVME_NS_DATA_DPS_PIT_SHIFT (0) 451 #define NVME_NS_DATA_DPS_PIT_MASK (0x7) 452 /* 1 == protection info transferred at start of metadata */ 453 /* 0 == protection info transferred at end of metadata */ 454 #define NVME_NS_DATA_DPS_MD_START_SHIFT (3) 455 #define NVME_NS_DATA_DPS_MD_START_MASK (0x1) 456 457 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */ 458 /* the namespace may be attached to two or more controllers */ 459 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_SHIFT (0) 460 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_MASK (0x1) 461 462 /** Reservation Capabilities */ 463 /* Persist Through Power Loss */ 464 #define NVME_NS_DATA_RESCAP_PTPL_SHIFT (0) 465 #define NVME_NS_DATA_RESCAP_PTPL_MASK (0x1) 466 /* supports the Write Exclusive */ 467 #define NVME_NS_DATA_RESCAP_WR_EX_SHIFT (1) 468 #define NVME_NS_DATA_RESCAP_WR_EX_MASK (0x1) 469 /* supports the Exclusive Access */ 470 #define NVME_NS_DATA_RESCAP_EX_AC_SHIFT (2) 471 #define NVME_NS_DATA_RESCAP_EX_AC_MASK (0x1) 472 /* supports the Write Exclusive – Registrants Only */ 473 #define NVME_NS_DATA_RESCAP_WR_EX_RO_SHIFT (3) 474 #define NVME_NS_DATA_RESCAP_WR_EX_RO_MASK (0x1) 475 /* supports the Exclusive Access - Registrants Only */ 476 #define NVME_NS_DATA_RESCAP_EX_AC_RO_SHIFT (4) 477 #define NVME_NS_DATA_RESCAP_EX_AC_RO_MASK (0x1) 478 /* supports the Write Exclusive – All Registrants */ 479 #define NVME_NS_DATA_RESCAP_WR_EX_AR_SHIFT (5) 480 #define NVME_NS_DATA_RESCAP_WR_EX_AR_MASK (0x1) 481 /* supports the Exclusive Access - All Registrants */ 482 #define NVME_NS_DATA_RESCAP_EX_AC_AR_SHIFT (6) 483 #define NVME_NS_DATA_RESCAP_EX_AC_AR_MASK (0x1) 484 /* Ignore Existing Key is used as defined in revision 1.3 or later */ 485 #define NVME_NS_DATA_RESCAP_IEKEY13_SHIFT (7) 486 #define NVME_NS_DATA_RESCAP_IEKEY13_MASK (0x1) 487 488 /** Format Progress Indicator */ 489 /* percentage of the Format NVM command that remains to be completed */ 490 #define NVME_NS_DATA_FPI_PERC_SHIFT (0) 491 #define NVME_NS_DATA_FPI_PERC_MASK (0x7f) 492 /* namespace supports the Format Progress Indicator */ 493 #define NVME_NS_DATA_FPI_SUPP_SHIFT (7) 494 #define NVME_NS_DATA_FPI_SUPP_MASK (0x1) 495 496 /** Deallocate Logical Block Features */ 497 /* deallocated logical block read behavior */ 498 #define NVME_NS_DATA_DLFEAT_READ_SHIFT (0) 499 #define NVME_NS_DATA_DLFEAT_READ_MASK (0x07) 500 #define NVME_NS_DATA_DLFEAT_READ_NR (0x00) 501 #define NVME_NS_DATA_DLFEAT_READ_00 (0x01) 502 #define NVME_NS_DATA_DLFEAT_READ_FF (0x02) 503 /* supports the Deallocate bit in the Write Zeroes */ 504 #define NVME_NS_DATA_DLFEAT_DWZ_SHIFT (3) 505 #define NVME_NS_DATA_DLFEAT_DWZ_MASK (0x01) 506 /* Guard field for deallocated logical blocks is set to the CRC */ 507 #define NVME_NS_DATA_DLFEAT_GCRC_SHIFT (4) 508 #define NVME_NS_DATA_DLFEAT_GCRC_MASK (0x01) 509 510 /** lba format support */ 511 /* metadata size */ 512 #define NVME_NS_DATA_LBAF_MS_SHIFT (0) 513 #define NVME_NS_DATA_LBAF_MS_MASK (0xFFFF) 514 /* lba data size */ 515 #define NVME_NS_DATA_LBAF_LBADS_SHIFT (16) 516 #define NVME_NS_DATA_LBAF_LBADS_MASK (0xFF) 517 /* relative performance */ 518 #define NVME_NS_DATA_LBAF_RP_SHIFT (24) 519 #define NVME_NS_DATA_LBAF_RP_MASK (0x3) 520 521 enum nvme_critical_warning_state { 522 NVME_CRIT_WARN_ST_AVAILABLE_SPARE = 0x1, 523 NVME_CRIT_WARN_ST_TEMPERATURE = 0x2, 524 NVME_CRIT_WARN_ST_DEVICE_RELIABILITY = 0x4, 525 NVME_CRIT_WARN_ST_READ_ONLY = 0x8, 526 NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP = 0x10, 527 }; 528 #define NVME_CRIT_WARN_ST_RESERVED_MASK (0xE0) 529 #define NVME_ASYNC_EVENT_NS_ATTRIBUTE (0x100) 530 #define NVME_ASYNC_EVENT_FW_ACTIVATE (0x200) 531 532 /* slot for current FW */ 533 #define NVME_FIRMWARE_PAGE_AFI_SLOT_SHIFT (0) 534 #define NVME_FIRMWARE_PAGE_AFI_SLOT_MASK (0x7) 535 536 /* Commands Supported and Effects */ 537 #define NVME_CE_PAGE_CSUP_SHIFT (0) 538 #define NVME_CE_PAGE_CSUP_MASK (0x1) 539 #define NVME_CE_PAGE_LBCC_SHIFT (1) 540 #define NVME_CE_PAGE_LBCC_MASK (0x1) 541 #define NVME_CE_PAGE_NCC_SHIFT (2) 542 #define NVME_CE_PAGE_NCC_MASK (0x1) 543 #define NVME_CE_PAGE_NIC_SHIFT (3) 544 #define NVME_CE_PAGE_NIC_MASK (0x1) 545 #define NVME_CE_PAGE_CCC_SHIFT (4) 546 #define NVME_CE_PAGE_CCC_MASK (0x1) 547 #define NVME_CE_PAGE_CSE_SHIFT (16) 548 #define NVME_CE_PAGE_CSE_MASK (0x7) 549 #define NVME_CE_PAGE_UUID_SHIFT (19) 550 #define NVME_CE_PAGE_UUID_MASK (0x1) 551 552 /* Sanitize Status */ 553 #define NVME_SS_PAGE_SSTAT_STATUS_SHIFT (0) 554 #define NVME_SS_PAGE_SSTAT_STATUS_MASK (0x7) 555 #define NVME_SS_PAGE_SSTAT_STATUS_NEVER (0) 556 #define NVME_SS_PAGE_SSTAT_STATUS_COMPLETED (1) 557 #define NVME_SS_PAGE_SSTAT_STATUS_INPROG (2) 558 #define NVME_SS_PAGE_SSTAT_STATUS_FAILED (3) 559 #define NVME_SS_PAGE_SSTAT_STATUS_COMPLETEDWD (4) 560 #define NVME_SS_PAGE_SSTAT_PASSES_SHIFT (3) 561 #define NVME_SS_PAGE_SSTAT_PASSES_MASK (0x1f) 562 #define NVME_SS_PAGE_SSTAT_GDE_SHIFT (8) 563 #define NVME_SS_PAGE_SSTAT_GDE_MASK (0x1) 564 565 /* Helper macro to combine *_MASK and *_SHIFT defines */ 566 #define NVMEB(name) (name##_MASK << name##_SHIFT) 567 568 /* CC register SHN field values */ 569 enum shn_value { 570 NVME_SHN_NORMAL = 0x1, 571 NVME_SHN_ABRUPT = 0x2, 572 }; 573 574 /* CSTS register SHST field values */ 575 enum shst_value { 576 NVME_SHST_NORMAL = 0x0, 577 NVME_SHST_OCCURRING = 0x1, 578 NVME_SHST_COMPLETE = 0x2, 579 }; 580 581 struct nvme_registers { 582 uint32_t cap_lo; /* controller capabilities */ 583 uint32_t cap_hi; 584 uint32_t vs; /* version */ 585 uint32_t intms; /* interrupt mask set */ 586 uint32_t intmc; /* interrupt mask clear */ 587 uint32_t cc; /* controller configuration */ 588 uint32_t reserved1; 589 uint32_t csts; /* controller status */ 590 uint32_t nssr; /* NVM Subsystem Reset */ 591 uint32_t aqa; /* admin queue attributes */ 592 uint64_t asq; /* admin submission queue base addr */ 593 uint64_t acq; /* admin completion queue base addr */ 594 uint32_t cmbloc; /* Controller Memory Buffer Location */ 595 uint32_t cmbsz; /* Controller Memory Buffer Size */ 596 uint32_t bpinfo; /* Boot Partition Information */ 597 uint32_t bprsel; /* Boot Partition Read Select */ 598 uint64_t bpmbl; /* Boot Partition Memory Buffer Location */ 599 uint64_t cmbmsc; /* Controller Memory Buffer Memory Space Control */ 600 uint32_t cmbsts; /* Controller Memory Buffer Status */ 601 uint8_t reserved3[3492]; /* 5Ch - DFFh */ 602 uint32_t pmrcap; /* Persistent Memory Capabilities */ 603 uint32_t pmrctl; /* Persistent Memory Region Control */ 604 uint32_t pmrsts; /* Persistent Memory Region Status */ 605 uint32_t pmrebs; /* Persistent Memory Region Elasticity Buffer Size */ 606 uint32_t pmrswtp; /* Persistent Memory Region Sustained Write Throughput */ 607 uint32_t pmrmsc_lo; /* Persistent Memory Region Controller Memory Space Control */ 608 uint32_t pmrmsc_hi; 609 uint8_t reserved4[484]; /* E1Ch - FFFh */ 610 struct { 611 uint32_t sq_tdbl; /* submission queue tail doorbell */ 612 uint32_t cq_hdbl; /* completion queue head doorbell */ 613 } doorbell[1]; 614 }; 615 616 _Static_assert(sizeof(struct nvme_registers) == 0x1008, "bad size for nvme_registers"); 617 618 struct nvme_command { 619 /* dword 0 */ 620 uint8_t opc; /* opcode */ 621 uint8_t fuse; /* fused operation */ 622 uint16_t cid; /* command identifier */ 623 624 /* dword 1 */ 625 uint32_t nsid; /* namespace identifier */ 626 627 /* dword 2-3 */ 628 uint32_t rsvd2; 629 uint32_t rsvd3; 630 631 /* dword 4-5 */ 632 uint64_t mptr; /* metadata pointer */ 633 634 /* dword 6-7 */ 635 uint64_t prp1; /* prp entry 1 */ 636 637 /* dword 8-9 */ 638 uint64_t prp2; /* prp entry 2 */ 639 640 /* dword 10-15 */ 641 uint32_t cdw10; /* command-specific */ 642 uint32_t cdw11; /* command-specific */ 643 uint32_t cdw12; /* command-specific */ 644 uint32_t cdw13; /* command-specific */ 645 uint32_t cdw14; /* command-specific */ 646 uint32_t cdw15; /* command-specific */ 647 }; 648 649 _Static_assert(sizeof(struct nvme_command) == 16 * 4, "bad size for nvme_command"); 650 651 struct nvme_completion { 652 /* dword 0 */ 653 uint32_t cdw0; /* command-specific */ 654 655 /* dword 1 */ 656 uint32_t rsvd1; 657 658 /* dword 2 */ 659 uint16_t sqhd; /* submission queue head pointer */ 660 uint16_t sqid; /* submission queue identifier */ 661 662 /* dword 3 */ 663 uint16_t cid; /* command identifier */ 664 uint16_t status; 665 } __aligned(8); /* riscv: nvme_qpair_process_completions has better code gen */ 666 667 _Static_assert(sizeof(struct nvme_completion) == 4 * 4, "bad size for nvme_completion"); 668 669 struct nvme_dsm_range { 670 uint32_t attributes; 671 uint32_t length; 672 uint64_t starting_lba; 673 }; 674 675 /* Largest DSM Trim that can be done */ 676 #define NVME_MAX_DSM_TRIM 4096 677 678 _Static_assert(sizeof(struct nvme_dsm_range) == 16, "bad size for nvme_dsm_ranage"); 679 680 /* status code types */ 681 enum nvme_status_code_type { 682 NVME_SCT_GENERIC = 0x0, 683 NVME_SCT_COMMAND_SPECIFIC = 0x1, 684 NVME_SCT_MEDIA_ERROR = 0x2, 685 NVME_SCT_PATH_RELATED = 0x3, 686 /* 0x3-0x6 - reserved */ 687 NVME_SCT_VENDOR_SPECIFIC = 0x7, 688 }; 689 690 /* generic command status codes */ 691 enum nvme_generic_command_status_code { 692 NVME_SC_SUCCESS = 0x00, 693 NVME_SC_INVALID_OPCODE = 0x01, 694 NVME_SC_INVALID_FIELD = 0x02, 695 NVME_SC_COMMAND_ID_CONFLICT = 0x03, 696 NVME_SC_DATA_TRANSFER_ERROR = 0x04, 697 NVME_SC_ABORTED_POWER_LOSS = 0x05, 698 NVME_SC_INTERNAL_DEVICE_ERROR = 0x06, 699 NVME_SC_ABORTED_BY_REQUEST = 0x07, 700 NVME_SC_ABORTED_SQ_DELETION = 0x08, 701 NVME_SC_ABORTED_FAILED_FUSED = 0x09, 702 NVME_SC_ABORTED_MISSING_FUSED = 0x0a, 703 NVME_SC_INVALID_NAMESPACE_OR_FORMAT = 0x0b, 704 NVME_SC_COMMAND_SEQUENCE_ERROR = 0x0c, 705 NVME_SC_INVALID_SGL_SEGMENT_DESCR = 0x0d, 706 NVME_SC_INVALID_NUMBER_OF_SGL_DESCR = 0x0e, 707 NVME_SC_DATA_SGL_LENGTH_INVALID = 0x0f, 708 NVME_SC_METADATA_SGL_LENGTH_INVALID = 0x10, 709 NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID = 0x11, 710 NVME_SC_INVALID_USE_OF_CMB = 0x12, 711 NVME_SC_PRP_OFFET_INVALID = 0x13, 712 NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED = 0x14, 713 NVME_SC_OPERATION_DENIED = 0x15, 714 NVME_SC_SGL_OFFSET_INVALID = 0x16, 715 /* 0x17 - reserved */ 716 NVME_SC_HOST_ID_INCONSISTENT_FORMAT = 0x18, 717 NVME_SC_KEEP_ALIVE_TIMEOUT_EXPIRED = 0x19, 718 NVME_SC_KEEP_ALIVE_TIMEOUT_INVALID = 0x1a, 719 NVME_SC_ABORTED_DUE_TO_PREEMPT = 0x1b, 720 NVME_SC_SANITIZE_FAILED = 0x1c, 721 NVME_SC_SANITIZE_IN_PROGRESS = 0x1d, 722 NVME_SC_SGL_DATA_BLOCK_GRAN_INVALID = 0x1e, 723 NVME_SC_NOT_SUPPORTED_IN_CMB = 0x1f, 724 NVME_SC_NAMESPACE_IS_WRITE_PROTECTED = 0x20, 725 NVME_SC_COMMAND_INTERRUPTED = 0x21, 726 NVME_SC_TRANSIENT_TRANSPORT_ERROR = 0x22, 727 728 NVME_SC_LBA_OUT_OF_RANGE = 0x80, 729 NVME_SC_CAPACITY_EXCEEDED = 0x81, 730 NVME_SC_NAMESPACE_NOT_READY = 0x82, 731 NVME_SC_RESERVATION_CONFLICT = 0x83, 732 NVME_SC_FORMAT_IN_PROGRESS = 0x84, 733 }; 734 735 /* command specific status codes */ 736 enum nvme_command_specific_status_code { 737 NVME_SC_COMPLETION_QUEUE_INVALID = 0x00, 738 NVME_SC_INVALID_QUEUE_IDENTIFIER = 0x01, 739 NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED = 0x02, 740 NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED = 0x03, 741 /* 0x04 - reserved */ 742 NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05, 743 NVME_SC_INVALID_FIRMWARE_SLOT = 0x06, 744 NVME_SC_INVALID_FIRMWARE_IMAGE = 0x07, 745 NVME_SC_INVALID_INTERRUPT_VECTOR = 0x08, 746 NVME_SC_INVALID_LOG_PAGE = 0x09, 747 NVME_SC_INVALID_FORMAT = 0x0a, 748 NVME_SC_FIRMWARE_REQUIRES_RESET = 0x0b, 749 NVME_SC_INVALID_QUEUE_DELETION = 0x0c, 750 NVME_SC_FEATURE_NOT_SAVEABLE = 0x0d, 751 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x0e, 752 NVME_SC_FEATURE_NOT_NS_SPECIFIC = 0x0f, 753 NVME_SC_FW_ACT_REQUIRES_NVMS_RESET = 0x10, 754 NVME_SC_FW_ACT_REQUIRES_RESET = 0x11, 755 NVME_SC_FW_ACT_REQUIRES_TIME = 0x12, 756 NVME_SC_FW_ACT_PROHIBITED = 0x13, 757 NVME_SC_OVERLAPPING_RANGE = 0x14, 758 NVME_SC_NS_INSUFFICIENT_CAPACITY = 0x15, 759 NVME_SC_NS_ID_UNAVAILABLE = 0x16, 760 /* 0x17 - reserved */ 761 NVME_SC_NS_ALREADY_ATTACHED = 0x18, 762 NVME_SC_NS_IS_PRIVATE = 0x19, 763 NVME_SC_NS_NOT_ATTACHED = 0x1a, 764 NVME_SC_THIN_PROV_NOT_SUPPORTED = 0x1b, 765 NVME_SC_CTRLR_LIST_INVALID = 0x1c, 766 NVME_SC_SELF_TEST_IN_PROGRESS = 0x1d, 767 NVME_SC_BOOT_PART_WRITE_PROHIB = 0x1e, 768 NVME_SC_INVALID_CTRLR_ID = 0x1f, 769 NVME_SC_INVALID_SEC_CTRLR_STATE = 0x20, 770 NVME_SC_INVALID_NUM_OF_CTRLR_RESRC = 0x21, 771 NVME_SC_INVALID_RESOURCE_ID = 0x22, 772 NVME_SC_SANITIZE_PROHIBITED_WPMRE = 0x23, 773 NVME_SC_ANA_GROUP_ID_INVALID = 0x24, 774 NVME_SC_ANA_ATTACH_FAILED = 0x25, 775 776 NVME_SC_CONFLICTING_ATTRIBUTES = 0x80, 777 NVME_SC_INVALID_PROTECTION_INFO = 0x81, 778 NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE = 0x82, 779 }; 780 781 /* media error status codes */ 782 enum nvme_media_error_status_code { 783 NVME_SC_WRITE_FAULTS = 0x80, 784 NVME_SC_UNRECOVERED_READ_ERROR = 0x81, 785 NVME_SC_GUARD_CHECK_ERROR = 0x82, 786 NVME_SC_APPLICATION_TAG_CHECK_ERROR = 0x83, 787 NVME_SC_REFERENCE_TAG_CHECK_ERROR = 0x84, 788 NVME_SC_COMPARE_FAILURE = 0x85, 789 NVME_SC_ACCESS_DENIED = 0x86, 790 NVME_SC_DEALLOCATED_OR_UNWRITTEN = 0x87, 791 }; 792 793 /* path related status codes */ 794 enum nvme_path_related_status_code { 795 NVME_SC_INTERNAL_PATH_ERROR = 0x00, 796 NVME_SC_ASYMMETRIC_ACCESS_PERSISTENT_LOSS = 0x01, 797 NVME_SC_ASYMMETRIC_ACCESS_INACCESSIBLE = 0x02, 798 NVME_SC_ASYMMETRIC_ACCESS_TRANSITION = 0x03, 799 NVME_SC_CONTROLLER_PATHING_ERROR = 0x60, 800 NVME_SC_HOST_PATHING_ERROR = 0x70, 801 NVME_SC_COMMAND_ABOTHED_BY_HOST = 0x71, 802 }; 803 804 /* admin opcodes */ 805 enum nvme_admin_opcode { 806 NVME_OPC_DELETE_IO_SQ = 0x00, 807 NVME_OPC_CREATE_IO_SQ = 0x01, 808 NVME_OPC_GET_LOG_PAGE = 0x02, 809 /* 0x03 - reserved */ 810 NVME_OPC_DELETE_IO_CQ = 0x04, 811 NVME_OPC_CREATE_IO_CQ = 0x05, 812 NVME_OPC_IDENTIFY = 0x06, 813 /* 0x07 - reserved */ 814 NVME_OPC_ABORT = 0x08, 815 NVME_OPC_SET_FEATURES = 0x09, 816 NVME_OPC_GET_FEATURES = 0x0a, 817 /* 0x0b - reserved */ 818 NVME_OPC_ASYNC_EVENT_REQUEST = 0x0c, 819 NVME_OPC_NAMESPACE_MANAGEMENT = 0x0d, 820 /* 0x0e-0x0f - reserved */ 821 NVME_OPC_FIRMWARE_ACTIVATE = 0x10, 822 NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD = 0x11, 823 /* 0x12-0x13 - reserved */ 824 NVME_OPC_DEVICE_SELF_TEST = 0x14, 825 NVME_OPC_NAMESPACE_ATTACHMENT = 0x15, 826 /* 0x16-0x17 - reserved */ 827 NVME_OPC_KEEP_ALIVE = 0x18, 828 NVME_OPC_DIRECTIVE_SEND = 0x19, 829 NVME_OPC_DIRECTIVE_RECEIVE = 0x1a, 830 /* 0x1b - reserved */ 831 NVME_OPC_VIRTUALIZATION_MANAGEMENT = 0x1c, 832 NVME_OPC_NVME_MI_SEND = 0x1d, 833 NVME_OPC_NVME_MI_RECEIVE = 0x1e, 834 /* 0x1f-0x7b - reserved */ 835 NVME_OPC_DOORBELL_BUFFER_CONFIG = 0x7c, 836 837 NVME_OPC_FORMAT_NVM = 0x80, 838 NVME_OPC_SECURITY_SEND = 0x81, 839 NVME_OPC_SECURITY_RECEIVE = 0x82, 840 /* 0x83 - reserved */ 841 NVME_OPC_SANITIZE = 0x84, 842 /* 0x85 - reserved */ 843 NVME_OPC_GET_LBA_STATUS = 0x86, 844 }; 845 846 /* nvme nvm opcodes */ 847 enum nvme_nvm_opcode { 848 NVME_OPC_FLUSH = 0x00, 849 NVME_OPC_WRITE = 0x01, 850 NVME_OPC_READ = 0x02, 851 /* 0x03 - reserved */ 852 NVME_OPC_WRITE_UNCORRECTABLE = 0x04, 853 NVME_OPC_COMPARE = 0x05, 854 /* 0x06-0x07 - reserved */ 855 NVME_OPC_WRITE_ZEROES = 0x08, 856 NVME_OPC_DATASET_MANAGEMENT = 0x09, 857 /* 0x0a-0x0b - reserved */ 858 NVME_OPC_VERIFY = 0x0c, 859 NVME_OPC_RESERVATION_REGISTER = 0x0d, 860 NVME_OPC_RESERVATION_REPORT = 0x0e, 861 /* 0x0f-0x10 - reserved */ 862 NVME_OPC_RESERVATION_ACQUIRE = 0x11, 863 /* 0x12-0x14 - reserved */ 864 NVME_OPC_RESERVATION_RELEASE = 0x15, 865 }; 866 867 enum nvme_feature { 868 /* 0x00 - reserved */ 869 NVME_FEAT_ARBITRATION = 0x01, 870 NVME_FEAT_POWER_MANAGEMENT = 0x02, 871 NVME_FEAT_LBA_RANGE_TYPE = 0x03, 872 NVME_FEAT_TEMPERATURE_THRESHOLD = 0x04, 873 NVME_FEAT_ERROR_RECOVERY = 0x05, 874 NVME_FEAT_VOLATILE_WRITE_CACHE = 0x06, 875 NVME_FEAT_NUMBER_OF_QUEUES = 0x07, 876 NVME_FEAT_INTERRUPT_COALESCING = 0x08, 877 NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09, 878 NVME_FEAT_WRITE_ATOMICITY = 0x0A, 879 NVME_FEAT_ASYNC_EVENT_CONFIGURATION = 0x0B, 880 NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION = 0x0C, 881 NVME_FEAT_HOST_MEMORY_BUFFER = 0x0D, 882 NVME_FEAT_TIMESTAMP = 0x0E, 883 NVME_FEAT_KEEP_ALIVE_TIMER = 0x0F, 884 NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT = 0x10, 885 NVME_FEAT_NON_OP_POWER_STATE_CONFIG = 0x11, 886 NVME_FEAT_READ_RECOVERY_LEVEL_CONFIG = 0x12, 887 NVME_FEAT_PREDICTABLE_LATENCY_MODE_CONFIG = 0x13, 888 NVME_FEAT_PREDICTABLE_LATENCY_MODE_WINDOW = 0x14, 889 NVME_FEAT_LBA_STATUS_INFORMATION_ATTRIBUTES = 0x15, 890 NVME_FEAT_HOST_BEHAVIOR_SUPPORT = 0x16, 891 NVME_FEAT_SANITIZE_CONFIG = 0x17, 892 NVME_FEAT_ENDURANCE_GROUP_EVENT_CONFIGURATION = 0x18, 893 /* 0x19-0x77 - reserved */ 894 /* 0x78-0x7f - NVMe Management Interface */ 895 NVME_FEAT_SOFTWARE_PROGRESS_MARKER = 0x80, 896 NVME_FEAT_HOST_IDENTIFIER = 0x81, 897 NVME_FEAT_RESERVATION_NOTIFICATION_MASK = 0x82, 898 NVME_FEAT_RESERVATION_PERSISTENCE = 0x83, 899 NVME_FEAT_NAMESPACE_WRITE_PROTECTION_CONFIG = 0x84, 900 /* 0x85-0xBF - command set specific (reserved) */ 901 /* 0xC0-0xFF - vendor specific */ 902 }; 903 904 enum nvme_dsm_attribute { 905 NVME_DSM_ATTR_INTEGRAL_READ = 0x1, 906 NVME_DSM_ATTR_INTEGRAL_WRITE = 0x2, 907 NVME_DSM_ATTR_DEALLOCATE = 0x4, 908 }; 909 910 enum nvme_activate_action { 911 NVME_AA_REPLACE_NO_ACTIVATE = 0x0, 912 NVME_AA_REPLACE_ACTIVATE = 0x1, 913 NVME_AA_ACTIVATE = 0x2, 914 }; 915 916 struct nvme_power_state { 917 /** Maximum Power */ 918 uint16_t mp; /* Maximum Power */ 919 uint8_t ps_rsvd1; 920 uint8_t mps_nops; /* Max Power Scale, Non-Operational State */ 921 922 uint32_t enlat; /* Entry Latency */ 923 uint32_t exlat; /* Exit Latency */ 924 925 uint8_t rrt; /* Relative Read Throughput */ 926 uint8_t rrl; /* Relative Read Latency */ 927 uint8_t rwt; /* Relative Write Throughput */ 928 uint8_t rwl; /* Relative Write Latency */ 929 930 uint16_t idlp; /* Idle Power */ 931 uint8_t ips; /* Idle Power Scale */ 932 uint8_t ps_rsvd8; 933 934 uint16_t actp; /* Active Power */ 935 uint8_t apw_aps; /* Active Power Workload, Active Power Scale */ 936 uint8_t ps_rsvd10[9]; 937 } __packed; 938 939 _Static_assert(sizeof(struct nvme_power_state) == 32, "bad size for nvme_power_state"); 940 941 #define NVME_SERIAL_NUMBER_LENGTH 20 942 #define NVME_MODEL_NUMBER_LENGTH 40 943 #define NVME_FIRMWARE_REVISION_LENGTH 8 944 945 struct nvme_controller_data { 946 /* bytes 0-255: controller capabilities and features */ 947 948 /** pci vendor id */ 949 uint16_t vid; 950 951 /** pci subsystem vendor id */ 952 uint16_t ssvid; 953 954 /** serial number */ 955 uint8_t sn[NVME_SERIAL_NUMBER_LENGTH]; 956 957 /** model number */ 958 uint8_t mn[NVME_MODEL_NUMBER_LENGTH]; 959 960 /** firmware revision */ 961 uint8_t fr[NVME_FIRMWARE_REVISION_LENGTH]; 962 963 /** recommended arbitration burst */ 964 uint8_t rab; 965 966 /** ieee oui identifier */ 967 uint8_t ieee[3]; 968 969 /** multi-interface capabilities */ 970 uint8_t mic; 971 972 /** maximum data transfer size */ 973 uint8_t mdts; 974 975 /** Controller ID */ 976 uint16_t ctrlr_id; 977 978 /** Version */ 979 uint32_t ver; 980 981 /** RTD3 Resume Latency */ 982 uint32_t rtd3r; 983 984 /** RTD3 Enter Latency */ 985 uint32_t rtd3e; 986 987 /** Optional Asynchronous Events Supported */ 988 uint32_t oaes; /* bitfield really */ 989 990 /** Controller Attributes */ 991 uint32_t ctratt; /* bitfield really */ 992 993 /** Read Recovery Levels Supported */ 994 uint16_t rrls; 995 996 uint8_t reserved1[9]; 997 998 /** Controller Type */ 999 uint8_t cntrltype; 1000 1001 /** FRU Globally Unique Identifier */ 1002 uint8_t fguid[16]; 1003 1004 /** Command Retry Delay Time 1 */ 1005 uint16_t crdt1; 1006 1007 /** Command Retry Delay Time 2 */ 1008 uint16_t crdt2; 1009 1010 /** Command Retry Delay Time 3 */ 1011 uint16_t crdt3; 1012 1013 uint8_t reserved2[122]; 1014 1015 /* bytes 256-511: admin command set attributes */ 1016 1017 /** optional admin command support */ 1018 uint16_t oacs; 1019 1020 /** abort command limit */ 1021 uint8_t acl; 1022 1023 /** asynchronous event request limit */ 1024 uint8_t aerl; 1025 1026 /** firmware updates */ 1027 uint8_t frmw; 1028 1029 /** log page attributes */ 1030 uint8_t lpa; 1031 1032 /** error log page entries */ 1033 uint8_t elpe; 1034 1035 /** number of power states supported */ 1036 uint8_t npss; 1037 1038 /** admin vendor specific command configuration */ 1039 uint8_t avscc; 1040 1041 /** Autonomous Power State Transition Attributes */ 1042 uint8_t apsta; 1043 1044 /** Warning Composite Temperature Threshold */ 1045 uint16_t wctemp; 1046 1047 /** Critical Composite Temperature Threshold */ 1048 uint16_t cctemp; 1049 1050 /** Maximum Time for Firmware Activation */ 1051 uint16_t mtfa; 1052 1053 /** Host Memory Buffer Preferred Size */ 1054 uint32_t hmpre; 1055 1056 /** Host Memory Buffer Minimum Size */ 1057 uint32_t hmmin; 1058 1059 /** Name space capabilities */ 1060 struct { 1061 /* if nsmgmt, report tnvmcap and unvmcap */ 1062 uint8_t tnvmcap[16]; 1063 uint8_t unvmcap[16]; 1064 } __packed untncap; 1065 1066 /** Replay Protected Memory Block Support */ 1067 uint32_t rpmbs; /* Really a bitfield */ 1068 1069 /** Extended Device Self-test Time */ 1070 uint16_t edstt; 1071 1072 /** Device Self-test Options */ 1073 uint8_t dsto; /* Really a bitfield */ 1074 1075 /** Firmware Update Granularity */ 1076 uint8_t fwug; 1077 1078 /** Keep Alive Support */ 1079 uint16_t kas; 1080 1081 /** Host Controlled Thermal Management Attributes */ 1082 uint16_t hctma; /* Really a bitfield */ 1083 1084 /** Minimum Thermal Management Temperature */ 1085 uint16_t mntmt; 1086 1087 /** Maximum Thermal Management Temperature */ 1088 uint16_t mxtmt; 1089 1090 /** Sanitize Capabilities */ 1091 uint32_t sanicap; /* Really a bitfield */ 1092 1093 /** Host Memory Buffer Minimum Descriptor Entry Size */ 1094 uint32_t hmminds; 1095 1096 /** Host Memory Maximum Descriptors Entries */ 1097 uint16_t hmmaxd; 1098 1099 /** NVM Set Identifier Maximum */ 1100 uint16_t nsetidmax; 1101 1102 /** Endurance Group Identifier Maximum */ 1103 uint16_t endgidmax; 1104 1105 /** ANA Transition Time */ 1106 uint8_t anatt; 1107 1108 /** Asymmetric Namespace Access Capabilities */ 1109 uint8_t anacap; 1110 1111 /** ANA Group Identifier Maximum */ 1112 uint32_t anagrpmax; 1113 1114 /** Number of ANA Group Identifiers */ 1115 uint32_t nanagrpid; 1116 1117 /** Persistent Event Log Size */ 1118 uint32_t pels; 1119 1120 uint8_t reserved3[156]; 1121 /* bytes 512-703: nvm command set attributes */ 1122 1123 /** submission queue entry size */ 1124 uint8_t sqes; 1125 1126 /** completion queue entry size */ 1127 uint8_t cqes; 1128 1129 /** Maximum Outstanding Commands */ 1130 uint16_t maxcmd; 1131 1132 /** number of namespaces */ 1133 uint32_t nn; 1134 1135 /** optional nvm command support */ 1136 uint16_t oncs; 1137 1138 /** fused operation support */ 1139 uint16_t fuses; 1140 1141 /** format nvm attributes */ 1142 uint8_t fna; 1143 1144 /** volatile write cache */ 1145 uint8_t vwc; 1146 1147 /** Atomic Write Unit Normal */ 1148 uint16_t awun; 1149 1150 /** Atomic Write Unit Power Fail */ 1151 uint16_t awupf; 1152 1153 /** NVM Vendor Specific Command Configuration */ 1154 uint8_t nvscc; 1155 1156 /** Namespace Write Protection Capabilities */ 1157 uint8_t nwpc; 1158 1159 /** Atomic Compare & Write Unit */ 1160 uint16_t acwu; 1161 uint16_t reserved6; 1162 1163 /** SGL Support */ 1164 uint32_t sgls; 1165 1166 /** Maximum Number of Allowed Namespaces */ 1167 uint32_t mnan; 1168 1169 /* bytes 540-767: Reserved */ 1170 uint8_t reserved7[224]; 1171 1172 /** NVM Subsystem NVMe Qualified Name */ 1173 uint8_t subnqn[256]; 1174 1175 /* bytes 1024-1791: Reserved */ 1176 uint8_t reserved8[768]; 1177 1178 /* bytes 1792-2047: NVMe over Fabrics specification */ 1179 uint8_t reserved9[256]; 1180 1181 /* bytes 2048-3071: power state descriptors */ 1182 struct nvme_power_state power_state[32]; 1183 1184 /* bytes 3072-4095: vendor specific */ 1185 uint8_t vs[1024]; 1186 } __packed __aligned(4); 1187 1188 _Static_assert(sizeof(struct nvme_controller_data) == 4096, "bad size for nvme_controller_data"); 1189 1190 struct nvme_namespace_data { 1191 /** namespace size */ 1192 uint64_t nsze; 1193 1194 /** namespace capacity */ 1195 uint64_t ncap; 1196 1197 /** namespace utilization */ 1198 uint64_t nuse; 1199 1200 /** namespace features */ 1201 uint8_t nsfeat; 1202 1203 /** number of lba formats */ 1204 uint8_t nlbaf; 1205 1206 /** formatted lba size */ 1207 uint8_t flbas; 1208 1209 /** metadata capabilities */ 1210 uint8_t mc; 1211 1212 /** end-to-end data protection capabilities */ 1213 uint8_t dpc; 1214 1215 /** end-to-end data protection type settings */ 1216 uint8_t dps; 1217 1218 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */ 1219 uint8_t nmic; 1220 1221 /** Reservation Capabilities */ 1222 uint8_t rescap; 1223 1224 /** Format Progress Indicator */ 1225 uint8_t fpi; 1226 1227 /** Deallocate Logical Block Features */ 1228 uint8_t dlfeat; 1229 1230 /** Namespace Atomic Write Unit Normal */ 1231 uint16_t nawun; 1232 1233 /** Namespace Atomic Write Unit Power Fail */ 1234 uint16_t nawupf; 1235 1236 /** Namespace Atomic Compare & Write Unit */ 1237 uint16_t nacwu; 1238 1239 /** Namespace Atomic Boundary Size Normal */ 1240 uint16_t nabsn; 1241 1242 /** Namespace Atomic Boundary Offset */ 1243 uint16_t nabo; 1244 1245 /** Namespace Atomic Boundary Size Power Fail */ 1246 uint16_t nabspf; 1247 1248 /** Namespace Optimal IO Boundary */ 1249 uint16_t noiob; 1250 1251 /** NVM Capacity */ 1252 uint8_t nvmcap[16]; 1253 1254 /** Namespace Preferred Write Granularity */ 1255 uint16_t npwg; 1256 1257 /** Namespace Preferred Write Alignment */ 1258 uint16_t npwa; 1259 1260 /** Namespace Preferred Deallocate Granularity */ 1261 uint16_t npdg; 1262 1263 /** Namespace Preferred Deallocate Alignment */ 1264 uint16_t npda; 1265 1266 /** Namespace Optimal Write Size */ 1267 uint16_t nows; 1268 1269 /* bytes 74-91: Reserved */ 1270 uint8_t reserved5[18]; 1271 1272 /** ANA Group Identifier */ 1273 uint32_t anagrpid; 1274 1275 /* bytes 96-98: Reserved */ 1276 uint8_t reserved6[3]; 1277 1278 /** Namespace Attributes */ 1279 uint8_t nsattr; 1280 1281 /** NVM Set Identifier */ 1282 uint16_t nvmsetid; 1283 1284 /** Endurance Group Identifier */ 1285 uint16_t endgid; 1286 1287 /** Namespace Globally Unique Identifier */ 1288 uint8_t nguid[16]; 1289 1290 /** IEEE Extended Unique Identifier */ 1291 uint8_t eui64[8]; 1292 1293 /** lba format support */ 1294 uint32_t lbaf[16]; 1295 1296 uint8_t reserved7[192]; 1297 1298 uint8_t vendor_specific[3712]; 1299 } __packed __aligned(4); 1300 1301 _Static_assert(sizeof(struct nvme_namespace_data) == 4096, "bad size for nvme_namepsace_data"); 1302 1303 enum nvme_log_page { 1304 /* 0x00 - reserved */ 1305 NVME_LOG_ERROR = 0x01, 1306 NVME_LOG_HEALTH_INFORMATION = 0x02, 1307 NVME_LOG_FIRMWARE_SLOT = 0x03, 1308 NVME_LOG_CHANGED_NAMESPACE = 0x04, 1309 NVME_LOG_COMMAND_EFFECT = 0x05, 1310 NVME_LOG_DEVICE_SELF_TEST = 0x06, 1311 NVME_LOG_TELEMETRY_HOST_INITIATED = 0x07, 1312 NVME_LOG_TELEMETRY_CONTROLLER_INITIATED = 0x08, 1313 NVME_LOG_ENDURANCE_GROUP_INFORMATION = 0x09, 1314 NVME_LOG_PREDICTABLE_LATENCY_PER_NVM_SET = 0x0a, 1315 NVME_LOG_PREDICTABLE_LATENCY_EVENT_AGGREGATE = 0x0b, 1316 NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS = 0x0c, 1317 NVME_LOG_PERSISTENT_EVENT_LOG = 0x0d, 1318 NVME_LOG_LBA_STATUS_INFORMATION = 0x0e, 1319 NVME_LOG_ENDURANCE_GROUP_EVENT_AGGREGATE = 0x0f, 1320 /* 0x06-0x7F - reserved */ 1321 /* 0x80-0xBF - I/O command set specific */ 1322 NVME_LOG_RES_NOTIFICATION = 0x80, 1323 NVME_LOG_SANITIZE_STATUS = 0x81, 1324 /* 0x82-0xBF - reserved */ 1325 /* 0xC0-0xFF - vendor specific */ 1326 1327 /* 1328 * The following are Intel Specific log pages, but they seem 1329 * to be widely implemented. 1330 */ 1331 INTEL_LOG_READ_LAT_LOG = 0xc1, 1332 INTEL_LOG_WRITE_LAT_LOG = 0xc2, 1333 INTEL_LOG_TEMP_STATS = 0xc5, 1334 INTEL_LOG_ADD_SMART = 0xca, 1335 INTEL_LOG_DRIVE_MKT_NAME = 0xdd, 1336 1337 /* 1338 * HGST log page, with lots ofs sub pages. 1339 */ 1340 HGST_INFO_LOG = 0xc1, 1341 }; 1342 1343 struct nvme_error_information_entry { 1344 uint64_t error_count; 1345 uint16_t sqid; 1346 uint16_t cid; 1347 uint16_t status; 1348 uint16_t error_location; 1349 uint64_t lba; 1350 uint32_t nsid; 1351 uint8_t vendor_specific; 1352 uint8_t trtype; 1353 uint16_t reserved30; 1354 uint64_t csi; 1355 uint16_t ttsi; 1356 uint8_t reserved[22]; 1357 } __packed __aligned(4); 1358 1359 _Static_assert(sizeof(struct nvme_error_information_entry) == 64, "bad size for nvme_error_information_entry"); 1360 1361 struct nvme_health_information_page { 1362 uint8_t critical_warning; 1363 uint16_t temperature; 1364 uint8_t available_spare; 1365 uint8_t available_spare_threshold; 1366 uint8_t percentage_used; 1367 1368 uint8_t reserved[26]; 1369 1370 /* 1371 * Note that the following are 128-bit values, but are 1372 * defined as an array of 2 64-bit values. 1373 */ 1374 /* Data Units Read is always in 512-byte units. */ 1375 uint64_t data_units_read[2]; 1376 /* Data Units Written is always in 512-byte units. */ 1377 uint64_t data_units_written[2]; 1378 /* For NVM command set, this includes Compare commands. */ 1379 uint64_t host_read_commands[2]; 1380 uint64_t host_write_commands[2]; 1381 /* Controller Busy Time is reported in minutes. */ 1382 uint64_t controller_busy_time[2]; 1383 uint64_t power_cycles[2]; 1384 uint64_t power_on_hours[2]; 1385 uint64_t unsafe_shutdowns[2]; 1386 uint64_t media_errors[2]; 1387 uint64_t num_error_info_log_entries[2]; 1388 uint32_t warning_temp_time; 1389 uint32_t error_temp_time; 1390 uint16_t temp_sensor[8]; 1391 /* Thermal Management Temperature 1 Transition Count */ 1392 uint32_t tmt1tc; 1393 /* Thermal Management Temperature 2 Transition Count */ 1394 uint32_t tmt2tc; 1395 /* Total Time For Thermal Management Temperature 1 */ 1396 uint32_t ttftmt1; 1397 /* Total Time For Thermal Management Temperature 2 */ 1398 uint32_t ttftmt2; 1399 1400 uint8_t reserved2[280]; 1401 } __packed __aligned(4); 1402 1403 _Static_assert(sizeof(struct nvme_health_information_page) == 512, "bad size for nvme_health_information_page"); 1404 1405 struct nvme_firmware_page { 1406 uint8_t afi; 1407 uint8_t reserved[7]; 1408 uint64_t revision[7]; /* revisions for 7 slots */ 1409 uint8_t reserved2[448]; 1410 } __packed __aligned(4); 1411 1412 _Static_assert(sizeof(struct nvme_firmware_page) == 512, "bad size for nvme_firmware_page"); 1413 1414 struct nvme_ns_list { 1415 uint32_t ns[1024]; 1416 } __packed __aligned(4); 1417 1418 _Static_assert(sizeof(struct nvme_ns_list) == 4096, "bad size for nvme_ns_list"); 1419 1420 struct nvme_command_effects_page { 1421 uint32_t acs[256]; 1422 uint32_t iocs[256]; 1423 uint8_t reserved[2048]; 1424 } __packed __aligned(4); 1425 1426 _Static_assert(sizeof(struct nvme_command_effects_page) == 4096, 1427 "bad size for nvme_command_effects_page"); 1428 1429 struct nvme_device_self_test_page { 1430 uint8_t curr_operation; 1431 uint8_t curr_compl; 1432 uint8_t rsvd2[2]; 1433 struct { 1434 uint8_t status; 1435 uint8_t segment_num; 1436 uint8_t valid_diag_info; 1437 uint8_t rsvd3; 1438 uint64_t poh; 1439 uint32_t nsid; 1440 /* Define as an array to simplify alignment issues */ 1441 uint8_t failing_lba[8]; 1442 uint8_t status_code_type; 1443 uint8_t status_code; 1444 uint8_t vendor_specific[2]; 1445 } __packed result[20]; 1446 } __packed __aligned(4); 1447 1448 _Static_assert(sizeof(struct nvme_device_self_test_page) == 564, 1449 "bad size for nvme_device_self_test_page"); 1450 1451 struct nvme_res_notification_page { 1452 uint64_t log_page_count; 1453 uint8_t log_page_type; 1454 uint8_t available_log_pages; 1455 uint8_t reserved2; 1456 uint32_t nsid; 1457 uint8_t reserved[48]; 1458 } __packed __aligned(4); 1459 1460 _Static_assert(sizeof(struct nvme_res_notification_page) == 64, 1461 "bad size for nvme_res_notification_page"); 1462 1463 struct nvme_sanitize_status_page { 1464 uint16_t sprog; 1465 uint16_t sstat; 1466 uint32_t scdw10; 1467 uint32_t etfo; 1468 uint32_t etfbe; 1469 uint32_t etfce; 1470 uint32_t etfownd; 1471 uint32_t etfbewnd; 1472 uint32_t etfcewnd; 1473 uint8_t reserved[480]; 1474 } __packed __aligned(4); 1475 1476 _Static_assert(sizeof(struct nvme_sanitize_status_page) == 512, 1477 "bad size for nvme_sanitize_status_page"); 1478 1479 struct intel_log_temp_stats { 1480 uint64_t current; 1481 uint64_t overtemp_flag_last; 1482 uint64_t overtemp_flag_life; 1483 uint64_t max_temp; 1484 uint64_t min_temp; 1485 uint64_t _rsvd[5]; 1486 uint64_t max_oper_temp; 1487 uint64_t min_oper_temp; 1488 uint64_t est_offset; 1489 } __packed __aligned(4); 1490 1491 _Static_assert(sizeof(struct intel_log_temp_stats) == 13 * 8, "bad size for intel_log_temp_stats"); 1492 1493 struct nvme_resv_reg_ctrlr { 1494 uint16_t ctrlr_id; /* Controller ID */ 1495 uint8_t rcsts; /* Reservation Status */ 1496 uint8_t reserved3[5]; 1497 uint64_t hostid; /* Host Identifier */ 1498 uint64_t rkey; /* Reservation Key */ 1499 } __packed __aligned(4); 1500 1501 _Static_assert(sizeof(struct nvme_resv_reg_ctrlr) == 24, "bad size for nvme_resv_reg_ctrlr"); 1502 1503 struct nvme_resv_reg_ctrlr_ext { 1504 uint16_t ctrlr_id; /* Controller ID */ 1505 uint8_t rcsts; /* Reservation Status */ 1506 uint8_t reserved3[5]; 1507 uint64_t rkey; /* Reservation Key */ 1508 uint64_t hostid[2]; /* Host Identifier */ 1509 uint8_t reserved32[32]; 1510 } __packed __aligned(4); 1511 1512 _Static_assert(sizeof(struct nvme_resv_reg_ctrlr_ext) == 64, "bad size for nvme_resv_reg_ctrlr_ext"); 1513 1514 struct nvme_resv_status { 1515 uint32_t gen; /* Generation */ 1516 uint8_t rtype; /* Reservation Type */ 1517 uint8_t regctl[2]; /* Number of Registered Controllers */ 1518 uint8_t reserved7[2]; 1519 uint8_t ptpls; /* Persist Through Power Loss State */ 1520 uint8_t reserved10[14]; 1521 struct nvme_resv_reg_ctrlr ctrlr[0]; 1522 } __packed __aligned(4); 1523 1524 _Static_assert(sizeof(struct nvme_resv_status) == 24, "bad size for nvme_resv_status"); 1525 1526 struct nvme_resv_status_ext { 1527 uint32_t gen; /* Generation */ 1528 uint8_t rtype; /* Reservation Type */ 1529 uint8_t regctl[2]; /* Number of Registered Controllers */ 1530 uint8_t reserved7[2]; 1531 uint8_t ptpls; /* Persist Through Power Loss State */ 1532 uint8_t reserved10[14]; 1533 uint8_t reserved24[40]; 1534 struct nvme_resv_reg_ctrlr_ext ctrlr[0]; 1535 } __packed __aligned(4); 1536 1537 _Static_assert(sizeof(struct nvme_resv_status_ext) == 64, "bad size for nvme_resv_status_ext"); 1538 1539 #define NVME_TEST_MAX_THREADS 128 1540 1541 struct nvme_io_test { 1542 enum nvme_nvm_opcode opc; 1543 uint32_t size; 1544 uint32_t time; /* in seconds */ 1545 uint32_t num_threads; 1546 uint32_t flags; 1547 uint64_t io_completed[NVME_TEST_MAX_THREADS]; 1548 }; 1549 1550 enum nvme_io_test_flags { 1551 /* 1552 * Specifies whether dev_refthread/dev_relthread should be 1553 * called during NVME_BIO_TEST. Ignored for other test 1554 * types. 1555 */ 1556 NVME_TEST_FLAG_REFTHREAD = 0x1, 1557 }; 1558 1559 struct nvme_pt_command { 1560 /* 1561 * cmd is used to specify a passthrough command to a controller or 1562 * namespace. 1563 * 1564 * The following fields from cmd may be specified by the caller: 1565 * * opc (opcode) 1566 * * nsid (namespace id) - for admin commands only 1567 * * cdw10-cdw15 1568 * 1569 * Remaining fields must be set to 0 by the caller. 1570 */ 1571 struct nvme_command cmd; 1572 1573 /* 1574 * cpl returns completion status for the passthrough command 1575 * specified by cmd. 1576 * 1577 * The following fields will be filled out by the driver, for 1578 * consumption by the caller: 1579 * * cdw0 1580 * * status (except for phase) 1581 * 1582 * Remaining fields will be set to 0 by the driver. 1583 */ 1584 struct nvme_completion cpl; 1585 1586 /* buf is the data buffer associated with this passthrough command. */ 1587 void * buf; 1588 1589 /* 1590 * len is the length of the data buffer associated with this 1591 * passthrough command. 1592 */ 1593 uint32_t len; 1594 1595 /* 1596 * is_read = 1 if the passthrough command will read data into the 1597 * supplied buffer from the controller. 1598 * 1599 * is_read = 0 if the passthrough command will write data from the 1600 * supplied buffer to the controller. 1601 */ 1602 uint32_t is_read; 1603 1604 /* 1605 * driver_lock is used by the driver only. It must be set to 0 1606 * by the caller. 1607 */ 1608 struct mtx * driver_lock; 1609 }; 1610 1611 struct nvme_get_nsid { 1612 char cdev[SPECNAMELEN + 1]; 1613 uint32_t nsid; 1614 }; 1615 1616 struct nvme_hmb_desc { 1617 uint64_t addr; 1618 uint32_t size; 1619 uint32_t reserved; 1620 }; 1621 1622 #define nvme_completion_is_error(cpl) \ 1623 (NVME_STATUS_GET_SC((cpl)->status) != 0 || NVME_STATUS_GET_SCT((cpl)->status) != 0) 1624 1625 void nvme_strvis(uint8_t *dst, const uint8_t *src, int dstlen, int srclen); 1626 1627 #ifdef _KERNEL 1628 1629 struct bio; 1630 struct thread; 1631 1632 struct nvme_namespace; 1633 struct nvme_controller; 1634 struct nvme_consumer; 1635 1636 typedef void (*nvme_cb_fn_t)(void *, const struct nvme_completion *); 1637 1638 typedef void *(*nvme_cons_ns_fn_t)(struct nvme_namespace *, void *); 1639 typedef void *(*nvme_cons_ctrlr_fn_t)(struct nvme_controller *); 1640 typedef void (*nvme_cons_async_fn_t)(void *, const struct nvme_completion *, 1641 uint32_t, void *, uint32_t); 1642 typedef void (*nvme_cons_fail_fn_t)(void *); 1643 1644 enum nvme_namespace_flags { 1645 NVME_NS_DEALLOCATE_SUPPORTED = 0x1, 1646 NVME_NS_FLUSH_SUPPORTED = 0x2, 1647 }; 1648 1649 int nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr, 1650 struct nvme_pt_command *pt, 1651 uint32_t nsid, int is_user_buffer, 1652 int is_admin_cmd); 1653 1654 /* Admin functions */ 1655 void nvme_ctrlr_cmd_set_feature(struct nvme_controller *ctrlr, 1656 uint8_t feature, uint32_t cdw11, 1657 uint32_t cdw12, uint32_t cdw13, 1658 uint32_t cdw14, uint32_t cdw15, 1659 void *payload, uint32_t payload_size, 1660 nvme_cb_fn_t cb_fn, void *cb_arg); 1661 void nvme_ctrlr_cmd_get_feature(struct nvme_controller *ctrlr, 1662 uint8_t feature, uint32_t cdw11, 1663 void *payload, uint32_t payload_size, 1664 nvme_cb_fn_t cb_fn, void *cb_arg); 1665 void nvme_ctrlr_cmd_get_log_page(struct nvme_controller *ctrlr, 1666 uint8_t log_page, uint32_t nsid, 1667 void *payload, uint32_t payload_size, 1668 nvme_cb_fn_t cb_fn, void *cb_arg); 1669 1670 /* NVM I/O functions */ 1671 int nvme_ns_cmd_write(struct nvme_namespace *ns, void *payload, 1672 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn, 1673 void *cb_arg); 1674 int nvme_ns_cmd_write_bio(struct nvme_namespace *ns, struct bio *bp, 1675 nvme_cb_fn_t cb_fn, void *cb_arg); 1676 int nvme_ns_cmd_read(struct nvme_namespace *ns, void *payload, 1677 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn, 1678 void *cb_arg); 1679 int nvme_ns_cmd_read_bio(struct nvme_namespace *ns, struct bio *bp, 1680 nvme_cb_fn_t cb_fn, void *cb_arg); 1681 int nvme_ns_cmd_deallocate(struct nvme_namespace *ns, void *payload, 1682 uint8_t num_ranges, nvme_cb_fn_t cb_fn, 1683 void *cb_arg); 1684 int nvme_ns_cmd_flush(struct nvme_namespace *ns, nvme_cb_fn_t cb_fn, 1685 void *cb_arg); 1686 int nvme_ns_dump(struct nvme_namespace *ns, void *virt, off_t offset, 1687 size_t len); 1688 1689 /* Registration functions */ 1690 struct nvme_consumer * nvme_register_consumer(nvme_cons_ns_fn_t ns_fn, 1691 nvme_cons_ctrlr_fn_t ctrlr_fn, 1692 nvme_cons_async_fn_t async_fn, 1693 nvme_cons_fail_fn_t fail_fn); 1694 void nvme_unregister_consumer(struct nvme_consumer *consumer); 1695 1696 /* Controller helper functions */ 1697 device_t nvme_ctrlr_get_device(struct nvme_controller *ctrlr); 1698 const struct nvme_controller_data * 1699 nvme_ctrlr_get_data(struct nvme_controller *ctrlr); 1700 static inline bool 1701 nvme_ctrlr_has_dataset_mgmt(const struct nvme_controller_data *cd) 1702 { 1703 /* Assumes cd was byte swapped by nvme_controller_data_swapbytes() */ 1704 return ((cd->oncs >> NVME_CTRLR_DATA_ONCS_DSM_SHIFT) & 1705 NVME_CTRLR_DATA_ONCS_DSM_MASK); 1706 } 1707 1708 /* Namespace helper functions */ 1709 uint32_t nvme_ns_get_max_io_xfer_size(struct nvme_namespace *ns); 1710 uint32_t nvme_ns_get_sector_size(struct nvme_namespace *ns); 1711 uint64_t nvme_ns_get_num_sectors(struct nvme_namespace *ns); 1712 uint64_t nvme_ns_get_size(struct nvme_namespace *ns); 1713 uint32_t nvme_ns_get_flags(struct nvme_namespace *ns); 1714 const char * nvme_ns_get_serial_number(struct nvme_namespace *ns); 1715 const char * nvme_ns_get_model_number(struct nvme_namespace *ns); 1716 const struct nvme_namespace_data * 1717 nvme_ns_get_data(struct nvme_namespace *ns); 1718 uint32_t nvme_ns_get_stripesize(struct nvme_namespace *ns); 1719 1720 int nvme_ns_bio_process(struct nvme_namespace *ns, struct bio *bp, 1721 nvme_cb_fn_t cb_fn); 1722 int nvme_ns_ioctl_process(struct nvme_namespace *ns, u_long cmd, 1723 caddr_t arg, int flag, struct thread *td); 1724 1725 /* 1726 * Command building helper functions -- shared with CAM 1727 * These functions assume allocator zeros out cmd structure 1728 * CAM's xpt_get_ccb and the request allocator for nvme both 1729 * do zero'd allocations. 1730 */ 1731 static inline 1732 void nvme_ns_flush_cmd(struct nvme_command *cmd, uint32_t nsid) 1733 { 1734 1735 cmd->opc = NVME_OPC_FLUSH; 1736 cmd->nsid = htole32(nsid); 1737 } 1738 1739 static inline 1740 void nvme_ns_rw_cmd(struct nvme_command *cmd, uint32_t rwcmd, uint32_t nsid, 1741 uint64_t lba, uint32_t count) 1742 { 1743 cmd->opc = rwcmd; 1744 cmd->nsid = htole32(nsid); 1745 cmd->cdw10 = htole32(lba & 0xffffffffu); 1746 cmd->cdw11 = htole32(lba >> 32); 1747 cmd->cdw12 = htole32(count-1); 1748 } 1749 1750 static inline 1751 void nvme_ns_write_cmd(struct nvme_command *cmd, uint32_t nsid, 1752 uint64_t lba, uint32_t count) 1753 { 1754 nvme_ns_rw_cmd(cmd, NVME_OPC_WRITE, nsid, lba, count); 1755 } 1756 1757 static inline 1758 void nvme_ns_read_cmd(struct nvme_command *cmd, uint32_t nsid, 1759 uint64_t lba, uint32_t count) 1760 { 1761 nvme_ns_rw_cmd(cmd, NVME_OPC_READ, nsid, lba, count); 1762 } 1763 1764 static inline 1765 void nvme_ns_trim_cmd(struct nvme_command *cmd, uint32_t nsid, 1766 uint32_t num_ranges) 1767 { 1768 cmd->opc = NVME_OPC_DATASET_MANAGEMENT; 1769 cmd->nsid = htole32(nsid); 1770 cmd->cdw10 = htole32(num_ranges - 1); 1771 cmd->cdw11 = htole32(NVME_DSM_ATTR_DEALLOCATE); 1772 } 1773 1774 extern int nvme_use_nvd; 1775 1776 #endif /* _KERNEL */ 1777 1778 /* Endianess conversion functions for NVMe structs */ 1779 static inline 1780 void nvme_completion_swapbytes(struct nvme_completion *s __unused) 1781 { 1782 #if _BYTE_ORDER != _LITTLE_ENDIAN 1783 1784 s->cdw0 = le32toh(s->cdw0); 1785 /* omit rsvd1 */ 1786 s->sqhd = le16toh(s->sqhd); 1787 s->sqid = le16toh(s->sqid); 1788 /* omit cid */ 1789 s->status = le16toh(s->status); 1790 #endif 1791 } 1792 1793 static inline 1794 void nvme_power_state_swapbytes(struct nvme_power_state *s __unused) 1795 { 1796 #if _BYTE_ORDER != _LITTLE_ENDIAN 1797 1798 s->mp = le16toh(s->mp); 1799 s->enlat = le32toh(s->enlat); 1800 s->exlat = le32toh(s->exlat); 1801 s->idlp = le16toh(s->idlp); 1802 s->actp = le16toh(s->actp); 1803 #endif 1804 } 1805 1806 static inline 1807 void nvme_controller_data_swapbytes(struct nvme_controller_data *s __unused) 1808 { 1809 #if _BYTE_ORDER != _LITTLE_ENDIAN 1810 int i; 1811 1812 s->vid = le16toh(s->vid); 1813 s->ssvid = le16toh(s->ssvid); 1814 s->ctrlr_id = le16toh(s->ctrlr_id); 1815 s->ver = le32toh(s->ver); 1816 s->rtd3r = le32toh(s->rtd3r); 1817 s->rtd3e = le32toh(s->rtd3e); 1818 s->oaes = le32toh(s->oaes); 1819 s->ctratt = le32toh(s->ctratt); 1820 s->rrls = le16toh(s->rrls); 1821 s->crdt1 = le16toh(s->crdt1); 1822 s->crdt2 = le16toh(s->crdt2); 1823 s->crdt3 = le16toh(s->crdt3); 1824 s->oacs = le16toh(s->oacs); 1825 s->wctemp = le16toh(s->wctemp); 1826 s->cctemp = le16toh(s->cctemp); 1827 s->mtfa = le16toh(s->mtfa); 1828 s->hmpre = le32toh(s->hmpre); 1829 s->hmmin = le32toh(s->hmmin); 1830 s->rpmbs = le32toh(s->rpmbs); 1831 s->edstt = le16toh(s->edstt); 1832 s->kas = le16toh(s->kas); 1833 s->hctma = le16toh(s->hctma); 1834 s->mntmt = le16toh(s->mntmt); 1835 s->mxtmt = le16toh(s->mxtmt); 1836 s->sanicap = le32toh(s->sanicap); 1837 s->hmminds = le32toh(s->hmminds); 1838 s->hmmaxd = le16toh(s->hmmaxd); 1839 s->nsetidmax = le16toh(s->nsetidmax); 1840 s->endgidmax = le16toh(s->endgidmax); 1841 s->anagrpmax = le32toh(s->anagrpmax); 1842 s->nanagrpid = le32toh(s->nanagrpid); 1843 s->pels = le32toh(s->pels); 1844 s->maxcmd = le16toh(s->maxcmd); 1845 s->nn = le32toh(s->nn); 1846 s->oncs = le16toh(s->oncs); 1847 s->fuses = le16toh(s->fuses); 1848 s->awun = le16toh(s->awun); 1849 s->awupf = le16toh(s->awupf); 1850 s->acwu = le16toh(s->acwu); 1851 s->sgls = le32toh(s->sgls); 1852 s->mnan = le32toh(s->mnan); 1853 for (i = 0; i < 32; i++) 1854 nvme_power_state_swapbytes(&s->power_state[i]); 1855 #endif 1856 } 1857 1858 static inline 1859 void nvme_namespace_data_swapbytes(struct nvme_namespace_data *s __unused) 1860 { 1861 #if _BYTE_ORDER != _LITTLE_ENDIAN 1862 int i; 1863 1864 s->nsze = le64toh(s->nsze); 1865 s->ncap = le64toh(s->ncap); 1866 s->nuse = le64toh(s->nuse); 1867 s->nawun = le16toh(s->nawun); 1868 s->nawupf = le16toh(s->nawupf); 1869 s->nacwu = le16toh(s->nacwu); 1870 s->nabsn = le16toh(s->nabsn); 1871 s->nabo = le16toh(s->nabo); 1872 s->nabspf = le16toh(s->nabspf); 1873 s->noiob = le16toh(s->noiob); 1874 s->npwg = le16toh(s->npwg); 1875 s->npwa = le16toh(s->npwa); 1876 s->npdg = le16toh(s->npdg); 1877 s->npda = le16toh(s->npda); 1878 s->nows = le16toh(s->nows); 1879 s->anagrpid = le32toh(s->anagrpid); 1880 s->nvmsetid = le16toh(s->nvmsetid); 1881 s->endgid = le16toh(s->endgid); 1882 for (i = 0; i < 16; i++) 1883 s->lbaf[i] = le32toh(s->lbaf[i]); 1884 #endif 1885 } 1886 1887 static inline 1888 void nvme_error_information_entry_swapbytes( 1889 struct nvme_error_information_entry *s __unused) 1890 { 1891 #if _BYTE_ORDER != _LITTLE_ENDIAN 1892 1893 s->error_count = le64toh(s->error_count); 1894 s->sqid = le16toh(s->sqid); 1895 s->cid = le16toh(s->cid); 1896 s->status = le16toh(s->status); 1897 s->error_location = le16toh(s->error_location); 1898 s->lba = le64toh(s->lba); 1899 s->nsid = le32toh(s->nsid); 1900 s->csi = le64toh(s->csi); 1901 s->ttsi = le16toh(s->ttsi); 1902 #endif 1903 } 1904 1905 static inline 1906 void nvme_le128toh(void *p __unused) 1907 { 1908 #if _BYTE_ORDER != _LITTLE_ENDIAN 1909 /* Swap 16 bytes in place */ 1910 char *tmp = (char*)p; 1911 char b; 1912 int i; 1913 for (i = 0; i < 8; i++) { 1914 b = tmp[i]; 1915 tmp[i] = tmp[15-i]; 1916 tmp[15-i] = b; 1917 } 1918 #endif 1919 } 1920 1921 static inline 1922 void nvme_health_information_page_swapbytes( 1923 struct nvme_health_information_page *s __unused) 1924 { 1925 #if _BYTE_ORDER != _LITTLE_ENDIAN 1926 int i; 1927 1928 s->temperature = le16toh(s->temperature); 1929 nvme_le128toh((void *)s->data_units_read); 1930 nvme_le128toh((void *)s->data_units_written); 1931 nvme_le128toh((void *)s->host_read_commands); 1932 nvme_le128toh((void *)s->host_write_commands); 1933 nvme_le128toh((void *)s->controller_busy_time); 1934 nvme_le128toh((void *)s->power_cycles); 1935 nvme_le128toh((void *)s->power_on_hours); 1936 nvme_le128toh((void *)s->unsafe_shutdowns); 1937 nvme_le128toh((void *)s->media_errors); 1938 nvme_le128toh((void *)s->num_error_info_log_entries); 1939 s->warning_temp_time = le32toh(s->warning_temp_time); 1940 s->error_temp_time = le32toh(s->error_temp_time); 1941 for (i = 0; i < 8; i++) 1942 s->temp_sensor[i] = le16toh(s->temp_sensor[i]); 1943 s->tmt1tc = le32toh(s->tmt1tc); 1944 s->tmt2tc = le32toh(s->tmt2tc); 1945 s->ttftmt1 = le32toh(s->ttftmt1); 1946 s->ttftmt2 = le32toh(s->ttftmt2); 1947 #endif 1948 } 1949 1950 static inline 1951 void nvme_firmware_page_swapbytes(struct nvme_firmware_page *s __unused) 1952 { 1953 #if _BYTE_ORDER != _LITTLE_ENDIAN 1954 int i; 1955 1956 for (i = 0; i < 7; i++) 1957 s->revision[i] = le64toh(s->revision[i]); 1958 #endif 1959 } 1960 1961 static inline 1962 void nvme_ns_list_swapbytes(struct nvme_ns_list *s __unused) 1963 { 1964 #if _BYTE_ORDER != _LITTLE_ENDIAN 1965 int i; 1966 1967 for (i = 0; i < 1024; i++) 1968 s->ns[i] = le32toh(s->ns[i]); 1969 #endif 1970 } 1971 1972 static inline 1973 void nvme_command_effects_page_swapbytes( 1974 struct nvme_command_effects_page *s __unused) 1975 { 1976 #if _BYTE_ORDER != _LITTLE_ENDIAN 1977 int i; 1978 1979 for (i = 0; i < 256; i++) 1980 s->acs[i] = le32toh(s->acs[i]); 1981 for (i = 0; i < 256; i++) 1982 s->iocs[i] = le32toh(s->iocs[i]); 1983 #endif 1984 } 1985 1986 static inline 1987 void nvme_res_notification_page_swapbytes( 1988 struct nvme_res_notification_page *s __unused) 1989 { 1990 #if _BYTE_ORDER != _LITTLE_ENDIAN 1991 s->log_page_count = le64toh(s->log_page_count); 1992 s->nsid = le32toh(s->nsid); 1993 #endif 1994 } 1995 1996 static inline 1997 void nvme_sanitize_status_page_swapbytes( 1998 struct nvme_sanitize_status_page *s __unused) 1999 { 2000 #if _BYTE_ORDER != _LITTLE_ENDIAN 2001 s->sprog = le16toh(s->sprog); 2002 s->sstat = le16toh(s->sstat); 2003 s->scdw10 = le32toh(s->scdw10); 2004 s->etfo = le32toh(s->etfo); 2005 s->etfbe = le32toh(s->etfbe); 2006 s->etfce = le32toh(s->etfce); 2007 s->etfownd = le32toh(s->etfownd); 2008 s->etfbewnd = le32toh(s->etfbewnd); 2009 s->etfcewnd = le32toh(s->etfcewnd); 2010 #endif 2011 } 2012 2013 static inline 2014 void intel_log_temp_stats_swapbytes(struct intel_log_temp_stats *s __unused) 2015 { 2016 #if _BYTE_ORDER != _LITTLE_ENDIAN 2017 2018 s->current = le64toh(s->current); 2019 s->overtemp_flag_last = le64toh(s->overtemp_flag_last); 2020 s->overtemp_flag_life = le64toh(s->overtemp_flag_life); 2021 s->max_temp = le64toh(s->max_temp); 2022 s->min_temp = le64toh(s->min_temp); 2023 /* omit _rsvd[] */ 2024 s->max_oper_temp = le64toh(s->max_oper_temp); 2025 s->min_oper_temp = le64toh(s->min_oper_temp); 2026 s->est_offset = le64toh(s->est_offset); 2027 #endif 2028 } 2029 2030 static inline 2031 void nvme_resv_status_swapbytes(struct nvme_resv_status *s __unused, 2032 size_t size __unused) 2033 { 2034 #if _BYTE_ORDER != _LITTLE_ENDIAN 2035 u_int i, n; 2036 2037 s->gen = le32toh(s->gen); 2038 n = (s->regctl[1] << 8) | s->regctl[0]; 2039 n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0])); 2040 for (i = 0; i < n; i++) { 2041 s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id); 2042 s->ctrlr[i].hostid = le64toh(s->ctrlr[i].hostid); 2043 s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey); 2044 } 2045 #endif 2046 } 2047 2048 static inline 2049 void nvme_resv_status_ext_swapbytes(struct nvme_resv_status_ext *s __unused, 2050 size_t size __unused) 2051 { 2052 #if _BYTE_ORDER != _LITTLE_ENDIAN 2053 u_int i, n; 2054 2055 s->gen = le32toh(s->gen); 2056 n = (s->regctl[1] << 8) | s->regctl[0]; 2057 n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0])); 2058 for (i = 0; i < n; i++) { 2059 s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id); 2060 s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey); 2061 nvme_le128toh((void *)s->ctrlr[i].hostid); 2062 } 2063 #endif 2064 } 2065 2066 static inline void 2067 nvme_device_self_test_swapbytes(struct nvme_device_self_test_page *s __unused) 2068 { 2069 #if _BYTE_ORDER != _LITTLE_ENDIAN 2070 uint8_t *tmp; 2071 uint32_t r, i; 2072 uint8_t b; 2073 2074 for (r = 0; r < 20; r++) { 2075 s->result[r].poh = le64toh(s->result[r].poh); 2076 s->result[r].nsid = le32toh(s->result[r].nsid); 2077 /* Unaligned 64-bit loads fail on some architectures */ 2078 tmp = s->result[r].failing_lba; 2079 for (i = 0; i < 4; i++) { 2080 b = tmp[i]; 2081 tmp[i] = tmp[7-i]; 2082 tmp[7-i] = b; 2083 } 2084 } 2085 #endif 2086 } 2087 #endif /* __NVME_H__ */ 2088