1 /* $OpenBSD: if_nfe.c,v 1.54 2006/04/07 12:38:12 jsg Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Shigeaki Tagashira <shigeaki@se.hiroshima-u.ac.jp> 5 * Copyright (c) 2006 Damien Bergamini <damien.bergamini@free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg@openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __FBSDID("$FreeBSD$"); 25 26 #ifdef HAVE_KERNEL_OPTION_HEADERS 27 #include "opt_device_polling.h" 28 #endif 29 30 #include <sys/param.h> 31 #include <sys/endian.h> 32 #include <sys/systm.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/malloc.h> 36 #include <sys/module.h> 37 #include <sys/kernel.h> 38 #include <sys/queue.h> 39 #include <sys/socket.h> 40 #include <sys/sysctl.h> 41 #include <sys/taskqueue.h> 42 43 #include <net/if.h> 44 #include <net/if_var.h> 45 #include <net/if_arp.h> 46 #include <net/ethernet.h> 47 #include <net/if_dl.h> 48 #include <net/if_media.h> 49 #include <net/if_types.h> 50 #include <net/if_vlan_var.h> 51 52 #include <net/bpf.h> 53 54 #include <machine/bus.h> 55 #include <machine/resource.h> 56 #include <sys/bus.h> 57 #include <sys/rman.h> 58 59 #include <dev/mii/mii.h> 60 #include <dev/mii/miivar.h> 61 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcivar.h> 64 65 #include <dev/nfe/if_nfereg.h> 66 #include <dev/nfe/if_nfevar.h> 67 68 MODULE_DEPEND(nfe, pci, 1, 1, 1); 69 MODULE_DEPEND(nfe, ether, 1, 1, 1); 70 MODULE_DEPEND(nfe, miibus, 1, 1, 1); 71 72 /* "device miibus" required. See GENERIC if you get errors here. */ 73 #include "miibus_if.h" 74 75 static int nfe_probe(device_t); 76 static int nfe_attach(device_t); 77 static int nfe_detach(device_t); 78 static int nfe_suspend(device_t); 79 static int nfe_resume(device_t); 80 static int nfe_shutdown(device_t); 81 static int nfe_can_use_msix(struct nfe_softc *); 82 static int nfe_detect_msik9(struct nfe_softc *); 83 static void nfe_power(struct nfe_softc *); 84 static int nfe_miibus_readreg(device_t, int, int); 85 static int nfe_miibus_writereg(device_t, int, int, int); 86 static void nfe_miibus_statchg(device_t); 87 static void nfe_mac_config(struct nfe_softc *, struct mii_data *); 88 static void nfe_set_intr(struct nfe_softc *); 89 static __inline void nfe_enable_intr(struct nfe_softc *); 90 static __inline void nfe_disable_intr(struct nfe_softc *); 91 static int nfe_ioctl(if_t, u_long, caddr_t); 92 static void nfe_alloc_msix(struct nfe_softc *, int); 93 static int nfe_intr(void *); 94 static void nfe_int_task(void *, int); 95 static __inline void nfe_discard_rxbuf(struct nfe_softc *, int); 96 static __inline void nfe_discard_jrxbuf(struct nfe_softc *, int); 97 static int nfe_newbuf(struct nfe_softc *, int); 98 static int nfe_jnewbuf(struct nfe_softc *, int); 99 static int nfe_rxeof(struct nfe_softc *, int, int *); 100 static int nfe_jrxeof(struct nfe_softc *, int, int *); 101 static void nfe_txeof(struct nfe_softc *); 102 static int nfe_encap(struct nfe_softc *, struct mbuf **); 103 static void nfe_setmulti(struct nfe_softc *); 104 static void nfe_start(if_t); 105 static void nfe_start_locked(if_t); 106 static void nfe_watchdog(if_t); 107 static void nfe_init(void *); 108 static void nfe_init_locked(void *); 109 static void nfe_stop(if_t); 110 static int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 111 static void nfe_alloc_jrx_ring(struct nfe_softc *, struct nfe_jrx_ring *); 112 static int nfe_init_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 113 static int nfe_init_jrx_ring(struct nfe_softc *, struct nfe_jrx_ring *); 114 static void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 115 static void nfe_free_jrx_ring(struct nfe_softc *, struct nfe_jrx_ring *); 116 static int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 117 static void nfe_init_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 118 static void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 119 static int nfe_ifmedia_upd(if_t); 120 static void nfe_ifmedia_sts(if_t, struct ifmediareq *); 121 static void nfe_tick(void *); 122 static void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 123 static void nfe_set_macaddr(struct nfe_softc *, uint8_t *); 124 static void nfe_dma_map_segs(void *, bus_dma_segment_t *, int, int); 125 126 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 127 static int sysctl_hw_nfe_proc_limit(SYSCTL_HANDLER_ARGS); 128 static void nfe_sysctl_node(struct nfe_softc *); 129 static void nfe_stats_clear(struct nfe_softc *); 130 static void nfe_stats_update(struct nfe_softc *); 131 static void nfe_set_linkspeed(struct nfe_softc *); 132 static void nfe_set_wol(struct nfe_softc *); 133 134 #ifdef NFE_DEBUG 135 static int nfedebug = 0; 136 #define DPRINTF(sc, ...) do { \ 137 if (nfedebug) \ 138 device_printf((sc)->nfe_dev, __VA_ARGS__); \ 139 } while (0) 140 #define DPRINTFN(sc, n, ...) do { \ 141 if (nfedebug >= (n)) \ 142 device_printf((sc)->nfe_dev, __VA_ARGS__); \ 143 } while (0) 144 #else 145 #define DPRINTF(sc, ...) 146 #define DPRINTFN(sc, n, ...) 147 #endif 148 149 #define NFE_LOCK(_sc) mtx_lock(&(_sc)->nfe_mtx) 150 #define NFE_UNLOCK(_sc) mtx_unlock(&(_sc)->nfe_mtx) 151 #define NFE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->nfe_mtx, MA_OWNED) 152 153 /* Tunables. */ 154 static int msi_disable = 0; 155 static int msix_disable = 0; 156 static int jumbo_disable = 0; 157 TUNABLE_INT("hw.nfe.msi_disable", &msi_disable); 158 TUNABLE_INT("hw.nfe.msix_disable", &msix_disable); 159 TUNABLE_INT("hw.nfe.jumbo_disable", &jumbo_disable); 160 161 static device_method_t nfe_methods[] = { 162 /* Device interface */ 163 DEVMETHOD(device_probe, nfe_probe), 164 DEVMETHOD(device_attach, nfe_attach), 165 DEVMETHOD(device_detach, nfe_detach), 166 DEVMETHOD(device_suspend, nfe_suspend), 167 DEVMETHOD(device_resume, nfe_resume), 168 DEVMETHOD(device_shutdown, nfe_shutdown), 169 170 /* MII interface */ 171 DEVMETHOD(miibus_readreg, nfe_miibus_readreg), 172 DEVMETHOD(miibus_writereg, nfe_miibus_writereg), 173 DEVMETHOD(miibus_statchg, nfe_miibus_statchg), 174 175 DEVMETHOD_END 176 }; 177 178 static driver_t nfe_driver = { 179 "nfe", 180 nfe_methods, 181 sizeof(struct nfe_softc) 182 }; 183 184 static devclass_t nfe_devclass; 185 186 DRIVER_MODULE(nfe, pci, nfe_driver, nfe_devclass, 0, 0); 187 DRIVER_MODULE(miibus, nfe, miibus_driver, miibus_devclass, 0, 0); 188 189 static struct nfe_type nfe_devs[] = { 190 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN, 191 "NVIDIA nForce MCP Networking Adapter"}, 192 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN, 193 "NVIDIA nForce2 MCP2 Networking Adapter"}, 194 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1, 195 "NVIDIA nForce2 400 MCP4 Networking Adapter"}, 196 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2, 197 "NVIDIA nForce2 400 MCP5 Networking Adapter"}, 198 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1, 199 "NVIDIA nForce3 MCP3 Networking Adapter"}, 200 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN, 201 "NVIDIA nForce3 250 MCP6 Networking Adapter"}, 202 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4, 203 "NVIDIA nForce3 MCP7 Networking Adapter"}, 204 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE4_LAN1, 205 "NVIDIA nForce4 CK804 MCP8 Networking Adapter"}, 206 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE4_LAN2, 207 "NVIDIA nForce4 CK804 MCP9 Networking Adapter"}, 208 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1, 209 "NVIDIA nForce MCP04 Networking Adapter"}, /* MCP10 */ 210 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2, 211 "NVIDIA nForce MCP04 Networking Adapter"}, /* MCP11 */ 212 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE430_LAN1, 213 "NVIDIA nForce 430 MCP12 Networking Adapter"}, 214 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE430_LAN2, 215 "NVIDIA nForce 430 MCP13 Networking Adapter"}, 216 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1, 217 "NVIDIA nForce MCP55 Networking Adapter"}, 218 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2, 219 "NVIDIA nForce MCP55 Networking Adapter"}, 220 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1, 221 "NVIDIA nForce MCP61 Networking Adapter"}, 222 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2, 223 "NVIDIA nForce MCP61 Networking Adapter"}, 224 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3, 225 "NVIDIA nForce MCP61 Networking Adapter"}, 226 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4, 227 "NVIDIA nForce MCP61 Networking Adapter"}, 228 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1, 229 "NVIDIA nForce MCP65 Networking Adapter"}, 230 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2, 231 "NVIDIA nForce MCP65 Networking Adapter"}, 232 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3, 233 "NVIDIA nForce MCP65 Networking Adapter"}, 234 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4, 235 "NVIDIA nForce MCP65 Networking Adapter"}, 236 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1, 237 "NVIDIA nForce MCP67 Networking Adapter"}, 238 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2, 239 "NVIDIA nForce MCP67 Networking Adapter"}, 240 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3, 241 "NVIDIA nForce MCP67 Networking Adapter"}, 242 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4, 243 "NVIDIA nForce MCP67 Networking Adapter"}, 244 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1, 245 "NVIDIA nForce MCP73 Networking Adapter"}, 246 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2, 247 "NVIDIA nForce MCP73 Networking Adapter"}, 248 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3, 249 "NVIDIA nForce MCP73 Networking Adapter"}, 250 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4, 251 "NVIDIA nForce MCP73 Networking Adapter"}, 252 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1, 253 "NVIDIA nForce MCP77 Networking Adapter"}, 254 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2, 255 "NVIDIA nForce MCP77 Networking Adapter"}, 256 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3, 257 "NVIDIA nForce MCP77 Networking Adapter"}, 258 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4, 259 "NVIDIA nForce MCP77 Networking Adapter"}, 260 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1, 261 "NVIDIA nForce MCP79 Networking Adapter"}, 262 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2, 263 "NVIDIA nForce MCP79 Networking Adapter"}, 264 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3, 265 "NVIDIA nForce MCP79 Networking Adapter"}, 266 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4, 267 "NVIDIA nForce MCP79 Networking Adapter"}, 268 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP89_LAN, 269 "NVIDIA nForce MCP89 Networking Adapter"}, 270 {0, 0, NULL} 271 }; 272 273 /* Probe for supported hardware ID's */ 274 static int 275 nfe_probe(device_t dev) 276 { 277 struct nfe_type *t; 278 279 t = nfe_devs; 280 /* Check for matching PCI DEVICE ID's */ 281 while (t->name != NULL) { 282 if ((pci_get_vendor(dev) == t->vid_id) && 283 (pci_get_device(dev) == t->dev_id)) { 284 device_set_desc(dev, t->name); 285 return (BUS_PROBE_DEFAULT); 286 } 287 t++; 288 } 289 290 return (ENXIO); 291 } 292 293 static void 294 nfe_alloc_msix(struct nfe_softc *sc, int count) 295 { 296 int rid; 297 298 rid = PCIR_BAR(2); 299 sc->nfe_msix_res = bus_alloc_resource_any(sc->nfe_dev, SYS_RES_MEMORY, 300 &rid, RF_ACTIVE); 301 if (sc->nfe_msix_res == NULL) { 302 device_printf(sc->nfe_dev, 303 "couldn't allocate MSIX table resource\n"); 304 return; 305 } 306 rid = PCIR_BAR(3); 307 sc->nfe_msix_pba_res = bus_alloc_resource_any(sc->nfe_dev, 308 SYS_RES_MEMORY, &rid, RF_ACTIVE); 309 if (sc->nfe_msix_pba_res == NULL) { 310 device_printf(sc->nfe_dev, 311 "couldn't allocate MSIX PBA resource\n"); 312 bus_release_resource(sc->nfe_dev, SYS_RES_MEMORY, PCIR_BAR(2), 313 sc->nfe_msix_res); 314 sc->nfe_msix_res = NULL; 315 return; 316 } 317 318 if (pci_alloc_msix(sc->nfe_dev, &count) == 0) { 319 if (count == NFE_MSI_MESSAGES) { 320 if (bootverbose) 321 device_printf(sc->nfe_dev, 322 "Using %d MSIX messages\n", count); 323 sc->nfe_msix = 1; 324 } else { 325 if (bootverbose) 326 device_printf(sc->nfe_dev, 327 "couldn't allocate MSIX\n"); 328 pci_release_msi(sc->nfe_dev); 329 bus_release_resource(sc->nfe_dev, SYS_RES_MEMORY, 330 PCIR_BAR(3), sc->nfe_msix_pba_res); 331 bus_release_resource(sc->nfe_dev, SYS_RES_MEMORY, 332 PCIR_BAR(2), sc->nfe_msix_res); 333 sc->nfe_msix_pba_res = NULL; 334 sc->nfe_msix_res = NULL; 335 } 336 } 337 } 338 339 static int 340 nfe_detect_msik9(struct nfe_softc *sc) 341 { 342 static const char *maker = "MSI"; 343 static const char *product = "K9N6PGM2-V2 (MS-7309)"; 344 char *m, *p; 345 int found; 346 347 found = 0; 348 m = kern_getenv("smbios.planar.maker"); 349 p = kern_getenv("smbios.planar.product"); 350 if (m != NULL && p != NULL) { 351 if (strcmp(m, maker) == 0 && strcmp(p, product) == 0) 352 found = 1; 353 } 354 if (m != NULL) 355 freeenv(m); 356 if (p != NULL) 357 freeenv(p); 358 359 return (found); 360 } 361 362 static int 363 nfe_attach(device_t dev) 364 { 365 struct nfe_softc *sc; 366 if_t ifp; 367 bus_addr_t dma_addr_max; 368 int error = 0, i, msic, phyloc, reg, rid; 369 370 sc = device_get_softc(dev); 371 sc->nfe_dev = dev; 372 373 mtx_init(&sc->nfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 374 MTX_DEF); 375 callout_init_mtx(&sc->nfe_stat_ch, &sc->nfe_mtx, 0); 376 377 pci_enable_busmaster(dev); 378 379 rid = PCIR_BAR(0); 380 sc->nfe_res[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 381 RF_ACTIVE); 382 if (sc->nfe_res[0] == NULL) { 383 device_printf(dev, "couldn't map memory resources\n"); 384 mtx_destroy(&sc->nfe_mtx); 385 return (ENXIO); 386 } 387 388 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 389 uint16_t v, width; 390 391 v = pci_read_config(dev, reg + 0x08, 2); 392 /* Change max. read request size to 4096. */ 393 v &= ~(7 << 12); 394 v |= (5 << 12); 395 pci_write_config(dev, reg + 0x08, v, 2); 396 397 v = pci_read_config(dev, reg + 0x0c, 2); 398 /* link capability */ 399 v = (v >> 4) & 0x0f; 400 width = pci_read_config(dev, reg + 0x12, 2); 401 /* negotiated link width */ 402 width = (width >> 4) & 0x3f; 403 if (v != width) 404 device_printf(sc->nfe_dev, 405 "warning, negotiated width of link(x%d) != " 406 "max. width of link(x%d)\n", width, v); 407 } 408 409 if (nfe_can_use_msix(sc) == 0) { 410 device_printf(sc->nfe_dev, 411 "MSI/MSI-X capability black-listed, will use INTx\n"); 412 msix_disable = 1; 413 msi_disable = 1; 414 } 415 416 /* Allocate interrupt */ 417 if (msix_disable == 0 || msi_disable == 0) { 418 if (msix_disable == 0 && 419 (msic = pci_msix_count(dev)) == NFE_MSI_MESSAGES) 420 nfe_alloc_msix(sc, msic); 421 if (msi_disable == 0 && sc->nfe_msix == 0 && 422 (msic = pci_msi_count(dev)) == NFE_MSI_MESSAGES && 423 pci_alloc_msi(dev, &msic) == 0) { 424 if (msic == NFE_MSI_MESSAGES) { 425 if (bootverbose) 426 device_printf(dev, 427 "Using %d MSI messages\n", msic); 428 sc->nfe_msi = 1; 429 } else 430 pci_release_msi(dev); 431 } 432 } 433 434 if (sc->nfe_msix == 0 && sc->nfe_msi == 0) { 435 rid = 0; 436 sc->nfe_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 437 RF_SHAREABLE | RF_ACTIVE); 438 if (sc->nfe_irq[0] == NULL) { 439 device_printf(dev, "couldn't allocate IRQ resources\n"); 440 error = ENXIO; 441 goto fail; 442 } 443 } else { 444 for (i = 0, rid = 1; i < NFE_MSI_MESSAGES; i++, rid++) { 445 sc->nfe_irq[i] = bus_alloc_resource_any(dev, 446 SYS_RES_IRQ, &rid, RF_ACTIVE); 447 if (sc->nfe_irq[i] == NULL) { 448 device_printf(dev, 449 "couldn't allocate IRQ resources for " 450 "message %d\n", rid); 451 error = ENXIO; 452 goto fail; 453 } 454 } 455 /* Map interrupts to vector 0. */ 456 if (sc->nfe_msix != 0) { 457 NFE_WRITE(sc, NFE_MSIX_MAP0, 0); 458 NFE_WRITE(sc, NFE_MSIX_MAP1, 0); 459 } else if (sc->nfe_msi != 0) { 460 NFE_WRITE(sc, NFE_MSI_MAP0, 0); 461 NFE_WRITE(sc, NFE_MSI_MAP1, 0); 462 } 463 } 464 465 /* Set IRQ status/mask register. */ 466 sc->nfe_irq_status = NFE_IRQ_STATUS; 467 sc->nfe_irq_mask = NFE_IRQ_MASK; 468 sc->nfe_intrs = NFE_IRQ_WANTED; 469 sc->nfe_nointrs = 0; 470 if (sc->nfe_msix != 0) { 471 sc->nfe_irq_status = NFE_MSIX_IRQ_STATUS; 472 sc->nfe_nointrs = NFE_IRQ_WANTED; 473 } else if (sc->nfe_msi != 0) { 474 sc->nfe_irq_mask = NFE_MSI_IRQ_MASK; 475 sc->nfe_intrs = NFE_MSI_VECTOR_0_ENABLED; 476 } 477 478 sc->nfe_devid = pci_get_device(dev); 479 sc->nfe_revid = pci_get_revid(dev); 480 sc->nfe_flags = 0; 481 482 switch (sc->nfe_devid) { 483 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 484 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 485 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 486 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 487 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 488 break; 489 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 490 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 491 sc->nfe_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT | NFE_MIB_V1; 492 break; 493 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 494 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 495 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 496 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 497 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 498 NFE_MIB_V1; 499 break; 500 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 501 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 502 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 503 NFE_HW_VLAN | NFE_PWR_MGMT | NFE_TX_FLOW_CTRL | NFE_MIB_V2; 504 break; 505 506 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 507 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 508 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 509 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 510 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 511 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 512 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 513 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 514 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 515 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 516 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 517 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 518 sc->nfe_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT | 519 NFE_CORRECT_MACADDR | NFE_TX_FLOW_CTRL | NFE_MIB_V2; 520 break; 521 case PCI_PRODUCT_NVIDIA_MCP77_LAN1: 522 case PCI_PRODUCT_NVIDIA_MCP77_LAN2: 523 case PCI_PRODUCT_NVIDIA_MCP77_LAN3: 524 case PCI_PRODUCT_NVIDIA_MCP77_LAN4: 525 /* XXX flow control */ 526 sc->nfe_flags |= NFE_40BIT_ADDR | NFE_HW_CSUM | NFE_PWR_MGMT | 527 NFE_CORRECT_MACADDR | NFE_MIB_V3; 528 break; 529 case PCI_PRODUCT_NVIDIA_MCP79_LAN1: 530 case PCI_PRODUCT_NVIDIA_MCP79_LAN2: 531 case PCI_PRODUCT_NVIDIA_MCP79_LAN3: 532 case PCI_PRODUCT_NVIDIA_MCP79_LAN4: 533 case PCI_PRODUCT_NVIDIA_MCP89_LAN: 534 /* XXX flow control */ 535 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 536 NFE_PWR_MGMT | NFE_CORRECT_MACADDR | NFE_MIB_V3; 537 break; 538 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 539 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 540 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 541 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 542 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | 543 NFE_PWR_MGMT | NFE_CORRECT_MACADDR | NFE_TX_FLOW_CTRL | 544 NFE_MIB_V2; 545 break; 546 } 547 548 nfe_power(sc); 549 /* Check for reversed ethernet address */ 550 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) 551 sc->nfe_flags |= NFE_CORRECT_MACADDR; 552 nfe_get_macaddr(sc, sc->eaddr); 553 /* 554 * Allocate the parent bus DMA tag appropriate for PCI. 555 */ 556 dma_addr_max = BUS_SPACE_MAXADDR_32BIT; 557 if ((sc->nfe_flags & NFE_40BIT_ADDR) != 0) 558 dma_addr_max = NFE_DMA_MAXADDR; 559 error = bus_dma_tag_create( 560 bus_get_dma_tag(sc->nfe_dev), /* parent */ 561 1, 0, /* alignment, boundary */ 562 dma_addr_max, /* lowaddr */ 563 BUS_SPACE_MAXADDR, /* highaddr */ 564 NULL, NULL, /* filter, filterarg */ 565 BUS_SPACE_MAXSIZE_32BIT, 0, /* maxsize, nsegments */ 566 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 567 0, /* flags */ 568 NULL, NULL, /* lockfunc, lockarg */ 569 &sc->nfe_parent_tag); 570 if (error) 571 goto fail; 572 573 ifp = sc->nfe_ifp = if_gethandle(IFT_ETHER); 574 if (ifp == NULL) { 575 device_printf(dev, "can not if_gethandle()\n"); 576 error = ENOSPC; 577 goto fail; 578 } 579 580 /* 581 * Allocate Tx and Rx rings. 582 */ 583 if ((error = nfe_alloc_tx_ring(sc, &sc->txq)) != 0) 584 goto fail; 585 586 if ((error = nfe_alloc_rx_ring(sc, &sc->rxq)) != 0) 587 goto fail; 588 589 nfe_alloc_jrx_ring(sc, &sc->jrxq); 590 /* Create sysctl node. */ 591 nfe_sysctl_node(sc); 592 593 if_setsoftc(ifp, sc); 594 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 595 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 596 if_setioctlfn(ifp, nfe_ioctl); 597 if_setstartfn(ifp, nfe_start); 598 if_sethwassist(ifp, 0); 599 if_setcapabilities(ifp, 0); 600 if_setinitfn(ifp, nfe_init); 601 if_setsendqlen(ifp, NFE_TX_RING_COUNT - 1); 602 if_setsendqready(ifp); 603 604 if (sc->nfe_flags & NFE_HW_CSUM) { 605 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_TSO4, 0); 606 if_sethwassistbits(ifp, NFE_CSUM_FEATURES | CSUM_TSO, 0); 607 } 608 if_setcapenable(ifp, if_getcapabilities(ifp)); 609 610 sc->nfe_framesize = if_getmtu(ifp) + NFE_RX_HEADERS; 611 /* VLAN capability setup. */ 612 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 613 if ((sc->nfe_flags & NFE_HW_VLAN) != 0) { 614 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING, 0); 615 if ((if_getcapabilities(ifp) & IFCAP_HWCSUM) != 0) 616 if_setcapabilitiesbit(ifp, 617 (IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO), 0); 618 } 619 620 if (pci_find_cap(dev, PCIY_PMG, ®) == 0) 621 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0); 622 if_setcapenable(ifp, if_getcapabilities(ifp)); 623 624 /* 625 * Tell the upper layer(s) we support long frames. 626 * Must appear after the call to ether_ifattach() because 627 * ether_ifattach() sets ifi_hdrlen to the default value. 628 */ 629 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 630 631 #ifdef DEVICE_POLLING 632 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 633 #endif 634 635 /* Do MII setup */ 636 phyloc = MII_PHY_ANY; 637 if (sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN1 || 638 sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN2 || 639 sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN3 || 640 sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN4) { 641 if (nfe_detect_msik9(sc) != 0) 642 phyloc = 0; 643 } 644 error = mii_attach(dev, &sc->nfe_miibus, ifp, 645 (ifm_change_cb_t)nfe_ifmedia_upd, (ifm_stat_cb_t)nfe_ifmedia_sts, 646 BMSR_DEFCAPMASK, phyloc, MII_OFFSET_ANY, MIIF_DOPAUSE); 647 if (error != 0) { 648 device_printf(dev, "attaching PHYs failed\n"); 649 goto fail; 650 } 651 ether_ifattach(ifp, sc->eaddr); 652 653 NET_TASK_INIT(&sc->nfe_int_task, 0, nfe_int_task, sc); 654 sc->nfe_tq = taskqueue_create_fast("nfe_taskq", M_WAITOK, 655 taskqueue_thread_enqueue, &sc->nfe_tq); 656 taskqueue_start_threads(&sc->nfe_tq, 1, PI_NET, "%s taskq", 657 device_get_nameunit(sc->nfe_dev)); 658 error = 0; 659 if (sc->nfe_msi == 0 && sc->nfe_msix == 0) { 660 error = bus_setup_intr(dev, sc->nfe_irq[0], 661 INTR_TYPE_NET | INTR_MPSAFE, nfe_intr, NULL, sc, 662 &sc->nfe_intrhand[0]); 663 } else { 664 for (i = 0; i < NFE_MSI_MESSAGES; i++) { 665 error = bus_setup_intr(dev, sc->nfe_irq[i], 666 INTR_TYPE_NET | INTR_MPSAFE, nfe_intr, NULL, sc, 667 &sc->nfe_intrhand[i]); 668 if (error != 0) 669 break; 670 } 671 } 672 if (error) { 673 device_printf(dev, "couldn't set up irq\n"); 674 taskqueue_free(sc->nfe_tq); 675 sc->nfe_tq = NULL; 676 ether_ifdetach(ifp); 677 goto fail; 678 } 679 680 fail: 681 if (error) 682 nfe_detach(dev); 683 684 return (error); 685 } 686 687 static int 688 nfe_detach(device_t dev) 689 { 690 struct nfe_softc *sc; 691 if_t ifp; 692 uint8_t eaddr[ETHER_ADDR_LEN]; 693 int i, rid; 694 695 sc = device_get_softc(dev); 696 KASSERT(mtx_initialized(&sc->nfe_mtx), ("nfe mutex not initialized")); 697 ifp = sc->nfe_ifp; 698 699 #ifdef DEVICE_POLLING 700 if (ifp != NULL && if_getcapenable(ifp) & IFCAP_POLLING) 701 ether_poll_deregister(ifp); 702 #endif 703 if (device_is_attached(dev)) { 704 NFE_LOCK(sc); 705 nfe_stop(ifp); 706 if_setflagbits(ifp, 0, IFF_UP); 707 NFE_UNLOCK(sc); 708 callout_drain(&sc->nfe_stat_ch); 709 ether_ifdetach(ifp); 710 } 711 712 if (ifp) { 713 /* restore ethernet address */ 714 if ((sc->nfe_flags & NFE_CORRECT_MACADDR) == 0) { 715 for (i = 0; i < ETHER_ADDR_LEN; i++) { 716 eaddr[i] = sc->eaddr[5 - i]; 717 } 718 } else 719 bcopy(sc->eaddr, eaddr, ETHER_ADDR_LEN); 720 nfe_set_macaddr(sc, eaddr); 721 if_free(ifp); 722 } 723 if (sc->nfe_miibus) 724 device_delete_child(dev, sc->nfe_miibus); 725 bus_generic_detach(dev); 726 if (sc->nfe_tq != NULL) { 727 taskqueue_drain(sc->nfe_tq, &sc->nfe_int_task); 728 taskqueue_free(sc->nfe_tq); 729 sc->nfe_tq = NULL; 730 } 731 732 for (i = 0; i < NFE_MSI_MESSAGES; i++) { 733 if (sc->nfe_intrhand[i] != NULL) { 734 bus_teardown_intr(dev, sc->nfe_irq[i], 735 sc->nfe_intrhand[i]); 736 sc->nfe_intrhand[i] = NULL; 737 } 738 } 739 740 if (sc->nfe_msi == 0 && sc->nfe_msix == 0) { 741 if (sc->nfe_irq[0] != NULL) 742 bus_release_resource(dev, SYS_RES_IRQ, 0, 743 sc->nfe_irq[0]); 744 } else { 745 for (i = 0, rid = 1; i < NFE_MSI_MESSAGES; i++, rid++) { 746 if (sc->nfe_irq[i] != NULL) { 747 bus_release_resource(dev, SYS_RES_IRQ, rid, 748 sc->nfe_irq[i]); 749 sc->nfe_irq[i] = NULL; 750 } 751 } 752 pci_release_msi(dev); 753 } 754 if (sc->nfe_msix_pba_res != NULL) { 755 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(3), 756 sc->nfe_msix_pba_res); 757 sc->nfe_msix_pba_res = NULL; 758 } 759 if (sc->nfe_msix_res != NULL) { 760 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(2), 761 sc->nfe_msix_res); 762 sc->nfe_msix_res = NULL; 763 } 764 if (sc->nfe_res[0] != NULL) { 765 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 766 sc->nfe_res[0]); 767 sc->nfe_res[0] = NULL; 768 } 769 770 nfe_free_tx_ring(sc, &sc->txq); 771 nfe_free_rx_ring(sc, &sc->rxq); 772 nfe_free_jrx_ring(sc, &sc->jrxq); 773 774 if (sc->nfe_parent_tag) { 775 bus_dma_tag_destroy(sc->nfe_parent_tag); 776 sc->nfe_parent_tag = NULL; 777 } 778 779 mtx_destroy(&sc->nfe_mtx); 780 781 return (0); 782 } 783 784 static int 785 nfe_suspend(device_t dev) 786 { 787 struct nfe_softc *sc; 788 789 sc = device_get_softc(dev); 790 791 NFE_LOCK(sc); 792 nfe_stop(sc->nfe_ifp); 793 nfe_set_wol(sc); 794 sc->nfe_suspended = 1; 795 NFE_UNLOCK(sc); 796 797 return (0); 798 } 799 800 static int 801 nfe_resume(device_t dev) 802 { 803 struct nfe_softc *sc; 804 if_t ifp; 805 806 sc = device_get_softc(dev); 807 808 NFE_LOCK(sc); 809 nfe_power(sc); 810 ifp = sc->nfe_ifp; 811 if (if_getflags(ifp) & IFF_UP) 812 nfe_init_locked(sc); 813 sc->nfe_suspended = 0; 814 NFE_UNLOCK(sc); 815 816 return (0); 817 } 818 819 static int 820 nfe_can_use_msix(struct nfe_softc *sc) 821 { 822 static struct msix_blacklist { 823 char *maker; 824 char *product; 825 } msix_blacklists[] = { 826 { "ASUSTeK Computer INC.", "P5N32-SLI PREMIUM" } 827 }; 828 829 struct msix_blacklist *mblp; 830 char *maker, *product; 831 int count, n, use_msix; 832 833 /* 834 * Search base board manufacturer and product name table 835 * to see this system has a known MSI/MSI-X issue. 836 */ 837 maker = kern_getenv("smbios.planar.maker"); 838 product = kern_getenv("smbios.planar.product"); 839 use_msix = 1; 840 if (maker != NULL && product != NULL) { 841 count = nitems(msix_blacklists); 842 mblp = msix_blacklists; 843 for (n = 0; n < count; n++) { 844 if (strcmp(maker, mblp->maker) == 0 && 845 strcmp(product, mblp->product) == 0) { 846 use_msix = 0; 847 break; 848 } 849 mblp++; 850 } 851 } 852 if (maker != NULL) 853 freeenv(maker); 854 if (product != NULL) 855 freeenv(product); 856 857 return (use_msix); 858 } 859 860 /* Take PHY/NIC out of powerdown, from Linux */ 861 static void 862 nfe_power(struct nfe_softc *sc) 863 { 864 uint32_t pwr; 865 866 if ((sc->nfe_flags & NFE_PWR_MGMT) == 0) 867 return; 868 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2); 869 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC); 870 DELAY(100); 871 NFE_WRITE(sc, NFE_MAC_RESET, 0); 872 DELAY(100); 873 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2); 874 pwr = NFE_READ(sc, NFE_PWR2_CTL); 875 pwr &= ~NFE_PWR2_WAKEUP_MASK; 876 if (sc->nfe_revid >= 0xa3 && 877 (sc->nfe_devid == PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 || 878 sc->nfe_devid == PCI_PRODUCT_NVIDIA_NFORCE430_LAN2)) 879 pwr |= NFE_PWR2_REVA3; 880 NFE_WRITE(sc, NFE_PWR2_CTL, pwr); 881 } 882 883 static void 884 nfe_miibus_statchg(device_t dev) 885 { 886 struct nfe_softc *sc; 887 struct mii_data *mii; 888 if_t ifp; 889 uint32_t rxctl, txctl; 890 891 sc = device_get_softc(dev); 892 893 mii = device_get_softc(sc->nfe_miibus); 894 ifp = sc->nfe_ifp; 895 896 sc->nfe_link = 0; 897 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 898 (IFM_ACTIVE | IFM_AVALID)) { 899 switch (IFM_SUBTYPE(mii->mii_media_active)) { 900 case IFM_10_T: 901 case IFM_100_TX: 902 case IFM_1000_T: 903 sc->nfe_link = 1; 904 break; 905 default: 906 break; 907 } 908 } 909 910 nfe_mac_config(sc, mii); 911 txctl = NFE_READ(sc, NFE_TX_CTL); 912 rxctl = NFE_READ(sc, NFE_RX_CTL); 913 if (sc->nfe_link != 0 && (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 914 txctl |= NFE_TX_START; 915 rxctl |= NFE_RX_START; 916 } else { 917 txctl &= ~NFE_TX_START; 918 rxctl &= ~NFE_RX_START; 919 } 920 NFE_WRITE(sc, NFE_TX_CTL, txctl); 921 NFE_WRITE(sc, NFE_RX_CTL, rxctl); 922 } 923 924 static void 925 nfe_mac_config(struct nfe_softc *sc, struct mii_data *mii) 926 { 927 uint32_t link, misc, phy, seed; 928 uint32_t val; 929 930 NFE_LOCK_ASSERT(sc); 931 932 phy = NFE_READ(sc, NFE_PHY_IFACE); 933 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 934 935 seed = NFE_READ(sc, NFE_RNDSEED); 936 seed &= ~NFE_SEED_MASK; 937 938 misc = NFE_MISC1_MAGIC; 939 link = NFE_MEDIA_SET; 940 941 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) { 942 phy |= NFE_PHY_HDX; /* half-duplex */ 943 misc |= NFE_MISC1_HDX; 944 } 945 946 switch (IFM_SUBTYPE(mii->mii_media_active)) { 947 case IFM_1000_T: /* full-duplex only */ 948 link |= NFE_MEDIA_1000T; 949 seed |= NFE_SEED_1000T; 950 phy |= NFE_PHY_1000T; 951 break; 952 case IFM_100_TX: 953 link |= NFE_MEDIA_100TX; 954 seed |= NFE_SEED_100TX; 955 phy |= NFE_PHY_100TX; 956 break; 957 case IFM_10_T: 958 link |= NFE_MEDIA_10T; 959 seed |= NFE_SEED_10T; 960 break; 961 } 962 963 if ((phy & 0x10000000) != 0) { 964 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 965 val = NFE_R1_MAGIC_1000; 966 else 967 val = NFE_R1_MAGIC_10_100; 968 } else 969 val = NFE_R1_MAGIC_DEFAULT; 970 NFE_WRITE(sc, NFE_SETUP_R1, val); 971 972 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 973 974 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 975 NFE_WRITE(sc, NFE_MISC1, misc); 976 NFE_WRITE(sc, NFE_LINKSPEED, link); 977 978 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 979 /* It seems all hardwares supports Rx pause frames. */ 980 val = NFE_READ(sc, NFE_RXFILTER); 981 if ((IFM_OPTIONS(mii->mii_media_active) & 982 IFM_ETH_RXPAUSE) != 0) 983 val |= NFE_PFF_RX_PAUSE; 984 else 985 val &= ~NFE_PFF_RX_PAUSE; 986 NFE_WRITE(sc, NFE_RXFILTER, val); 987 if ((sc->nfe_flags & NFE_TX_FLOW_CTRL) != 0) { 988 val = NFE_READ(sc, NFE_MISC1); 989 if ((IFM_OPTIONS(mii->mii_media_active) & 990 IFM_ETH_TXPAUSE) != 0) { 991 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, 992 NFE_TX_PAUSE_FRAME_ENABLE); 993 val |= NFE_MISC1_TX_PAUSE; 994 } else { 995 val &= ~NFE_MISC1_TX_PAUSE; 996 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, 997 NFE_TX_PAUSE_FRAME_DISABLE); 998 } 999 NFE_WRITE(sc, NFE_MISC1, val); 1000 } 1001 } else { 1002 /* disable rx/tx pause frames */ 1003 val = NFE_READ(sc, NFE_RXFILTER); 1004 val &= ~NFE_PFF_RX_PAUSE; 1005 NFE_WRITE(sc, NFE_RXFILTER, val); 1006 if ((sc->nfe_flags & NFE_TX_FLOW_CTRL) != 0) { 1007 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, 1008 NFE_TX_PAUSE_FRAME_DISABLE); 1009 val = NFE_READ(sc, NFE_MISC1); 1010 val &= ~NFE_MISC1_TX_PAUSE; 1011 NFE_WRITE(sc, NFE_MISC1, val); 1012 } 1013 } 1014 } 1015 1016 static int 1017 nfe_miibus_readreg(device_t dev, int phy, int reg) 1018 { 1019 struct nfe_softc *sc = device_get_softc(dev); 1020 uint32_t val; 1021 int ntries; 1022 1023 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1024 1025 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 1026 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 1027 DELAY(100); 1028 } 1029 1030 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 1031 1032 for (ntries = 0; ntries < NFE_TIMEOUT; ntries++) { 1033 DELAY(100); 1034 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 1035 break; 1036 } 1037 if (ntries == NFE_TIMEOUT) { 1038 DPRINTFN(sc, 2, "timeout waiting for PHY\n"); 1039 return 0; 1040 } 1041 1042 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 1043 DPRINTFN(sc, 2, "could not read PHY\n"); 1044 return 0; 1045 } 1046 1047 val = NFE_READ(sc, NFE_PHY_DATA); 1048 if (val != 0xffffffff && val != 0) 1049 sc->mii_phyaddr = phy; 1050 1051 DPRINTFN(sc, 2, "mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val); 1052 1053 return (val); 1054 } 1055 1056 static int 1057 nfe_miibus_writereg(device_t dev, int phy, int reg, int val) 1058 { 1059 struct nfe_softc *sc = device_get_softc(dev); 1060 uint32_t ctl; 1061 int ntries; 1062 1063 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1064 1065 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 1066 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 1067 DELAY(100); 1068 } 1069 1070 NFE_WRITE(sc, NFE_PHY_DATA, val); 1071 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 1072 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 1073 1074 for (ntries = 0; ntries < NFE_TIMEOUT; ntries++) { 1075 DELAY(100); 1076 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 1077 break; 1078 } 1079 #ifdef NFE_DEBUG 1080 if (nfedebug >= 2 && ntries == NFE_TIMEOUT) 1081 device_printf(sc->nfe_dev, "could not write to PHY\n"); 1082 #endif 1083 return (0); 1084 } 1085 1086 struct nfe_dmamap_arg { 1087 bus_addr_t nfe_busaddr; 1088 }; 1089 1090 static int 1091 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1092 { 1093 struct nfe_dmamap_arg ctx; 1094 struct nfe_rx_data *data; 1095 void *desc; 1096 int i, error, descsize; 1097 1098 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1099 desc = ring->desc64; 1100 descsize = sizeof (struct nfe_desc64); 1101 } else { 1102 desc = ring->desc32; 1103 descsize = sizeof (struct nfe_desc32); 1104 } 1105 1106 ring->cur = ring->next = 0; 1107 1108 error = bus_dma_tag_create(sc->nfe_parent_tag, 1109 NFE_RING_ALIGN, 0, /* alignment, boundary */ 1110 BUS_SPACE_MAXADDR, /* lowaddr */ 1111 BUS_SPACE_MAXADDR, /* highaddr */ 1112 NULL, NULL, /* filter, filterarg */ 1113 NFE_RX_RING_COUNT * descsize, 1, /* maxsize, nsegments */ 1114 NFE_RX_RING_COUNT * descsize, /* maxsegsize */ 1115 0, /* flags */ 1116 NULL, NULL, /* lockfunc, lockarg */ 1117 &ring->rx_desc_tag); 1118 if (error != 0) { 1119 device_printf(sc->nfe_dev, "could not create desc DMA tag\n"); 1120 goto fail; 1121 } 1122 1123 /* allocate memory to desc */ 1124 error = bus_dmamem_alloc(ring->rx_desc_tag, &desc, BUS_DMA_WAITOK | 1125 BUS_DMA_COHERENT | BUS_DMA_ZERO, &ring->rx_desc_map); 1126 if (error != 0) { 1127 device_printf(sc->nfe_dev, "could not create desc DMA map\n"); 1128 goto fail; 1129 } 1130 if (sc->nfe_flags & NFE_40BIT_ADDR) 1131 ring->desc64 = desc; 1132 else 1133 ring->desc32 = desc; 1134 1135 /* map desc to device visible address space */ 1136 ctx.nfe_busaddr = 0; 1137 error = bus_dmamap_load(ring->rx_desc_tag, ring->rx_desc_map, desc, 1138 NFE_RX_RING_COUNT * descsize, nfe_dma_map_segs, &ctx, 0); 1139 if (error != 0) { 1140 device_printf(sc->nfe_dev, "could not load desc DMA map\n"); 1141 goto fail; 1142 } 1143 ring->physaddr = ctx.nfe_busaddr; 1144 1145 error = bus_dma_tag_create(sc->nfe_parent_tag, 1146 1, 0, /* alignment, boundary */ 1147 BUS_SPACE_MAXADDR, /* lowaddr */ 1148 BUS_SPACE_MAXADDR, /* highaddr */ 1149 NULL, NULL, /* filter, filterarg */ 1150 MCLBYTES, 1, /* maxsize, nsegments */ 1151 MCLBYTES, /* maxsegsize */ 1152 0, /* flags */ 1153 NULL, NULL, /* lockfunc, lockarg */ 1154 &ring->rx_data_tag); 1155 if (error != 0) { 1156 device_printf(sc->nfe_dev, "could not create Rx DMA tag\n"); 1157 goto fail; 1158 } 1159 1160 error = bus_dmamap_create(ring->rx_data_tag, 0, &ring->rx_spare_map); 1161 if (error != 0) { 1162 device_printf(sc->nfe_dev, 1163 "could not create Rx DMA spare map\n"); 1164 goto fail; 1165 } 1166 1167 /* 1168 * Pre-allocate Rx buffers and populate Rx ring. 1169 */ 1170 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1171 data = &sc->rxq.data[i]; 1172 data->rx_data_map = NULL; 1173 data->m = NULL; 1174 error = bus_dmamap_create(ring->rx_data_tag, 0, 1175 &data->rx_data_map); 1176 if (error != 0) { 1177 device_printf(sc->nfe_dev, 1178 "could not create Rx DMA map\n"); 1179 goto fail; 1180 } 1181 } 1182 1183 fail: 1184 return (error); 1185 } 1186 1187 static void 1188 nfe_alloc_jrx_ring(struct nfe_softc *sc, struct nfe_jrx_ring *ring) 1189 { 1190 struct nfe_dmamap_arg ctx; 1191 struct nfe_rx_data *data; 1192 void *desc; 1193 int i, error, descsize; 1194 1195 if ((sc->nfe_flags & NFE_JUMBO_SUP) == 0) 1196 return; 1197 if (jumbo_disable != 0) { 1198 device_printf(sc->nfe_dev, "disabling jumbo frame support\n"); 1199 sc->nfe_jumbo_disable = 1; 1200 return; 1201 } 1202 1203 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1204 desc = ring->jdesc64; 1205 descsize = sizeof (struct nfe_desc64); 1206 } else { 1207 desc = ring->jdesc32; 1208 descsize = sizeof (struct nfe_desc32); 1209 } 1210 1211 ring->jcur = ring->jnext = 0; 1212 1213 /* Create DMA tag for jumbo Rx ring. */ 1214 error = bus_dma_tag_create(sc->nfe_parent_tag, 1215 NFE_RING_ALIGN, 0, /* alignment, boundary */ 1216 BUS_SPACE_MAXADDR, /* lowaddr */ 1217 BUS_SPACE_MAXADDR, /* highaddr */ 1218 NULL, NULL, /* filter, filterarg */ 1219 NFE_JUMBO_RX_RING_COUNT * descsize, /* maxsize */ 1220 1, /* nsegments */ 1221 NFE_JUMBO_RX_RING_COUNT * descsize, /* maxsegsize */ 1222 0, /* flags */ 1223 NULL, NULL, /* lockfunc, lockarg */ 1224 &ring->jrx_desc_tag); 1225 if (error != 0) { 1226 device_printf(sc->nfe_dev, 1227 "could not create jumbo ring DMA tag\n"); 1228 goto fail; 1229 } 1230 1231 /* Create DMA tag for jumbo Rx buffers. */ 1232 error = bus_dma_tag_create(sc->nfe_parent_tag, 1233 1, 0, /* alignment, boundary */ 1234 BUS_SPACE_MAXADDR, /* lowaddr */ 1235 BUS_SPACE_MAXADDR, /* highaddr */ 1236 NULL, NULL, /* filter, filterarg */ 1237 MJUM9BYTES, /* maxsize */ 1238 1, /* nsegments */ 1239 MJUM9BYTES, /* maxsegsize */ 1240 0, /* flags */ 1241 NULL, NULL, /* lockfunc, lockarg */ 1242 &ring->jrx_data_tag); 1243 if (error != 0) { 1244 device_printf(sc->nfe_dev, 1245 "could not create jumbo Rx buffer DMA tag\n"); 1246 goto fail; 1247 } 1248 1249 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 1250 error = bus_dmamem_alloc(ring->jrx_desc_tag, &desc, BUS_DMA_WAITOK | 1251 BUS_DMA_COHERENT | BUS_DMA_ZERO, &ring->jrx_desc_map); 1252 if (error != 0) { 1253 device_printf(sc->nfe_dev, 1254 "could not allocate DMA'able memory for jumbo Rx ring\n"); 1255 goto fail; 1256 } 1257 if (sc->nfe_flags & NFE_40BIT_ADDR) 1258 ring->jdesc64 = desc; 1259 else 1260 ring->jdesc32 = desc; 1261 1262 ctx.nfe_busaddr = 0; 1263 error = bus_dmamap_load(ring->jrx_desc_tag, ring->jrx_desc_map, desc, 1264 NFE_JUMBO_RX_RING_COUNT * descsize, nfe_dma_map_segs, &ctx, 0); 1265 if (error != 0) { 1266 device_printf(sc->nfe_dev, 1267 "could not load DMA'able memory for jumbo Rx ring\n"); 1268 goto fail; 1269 } 1270 ring->jphysaddr = ctx.nfe_busaddr; 1271 1272 /* Create DMA maps for jumbo Rx buffers. */ 1273 error = bus_dmamap_create(ring->jrx_data_tag, 0, &ring->jrx_spare_map); 1274 if (error != 0) { 1275 device_printf(sc->nfe_dev, 1276 "could not create jumbo Rx DMA spare map\n"); 1277 goto fail; 1278 } 1279 1280 for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) { 1281 data = &sc->jrxq.jdata[i]; 1282 data->rx_data_map = NULL; 1283 data->m = NULL; 1284 error = bus_dmamap_create(ring->jrx_data_tag, 0, 1285 &data->rx_data_map); 1286 if (error != 0) { 1287 device_printf(sc->nfe_dev, 1288 "could not create jumbo Rx DMA map\n"); 1289 goto fail; 1290 } 1291 } 1292 1293 return; 1294 1295 fail: 1296 /* 1297 * Running without jumbo frame support is ok for most cases 1298 * so don't fail on creating dma tag/map for jumbo frame. 1299 */ 1300 nfe_free_jrx_ring(sc, ring); 1301 device_printf(sc->nfe_dev, "disabling jumbo frame support due to " 1302 "resource shortage\n"); 1303 sc->nfe_jumbo_disable = 1; 1304 } 1305 1306 static int 1307 nfe_init_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1308 { 1309 void *desc; 1310 size_t descsize; 1311 int i; 1312 1313 ring->cur = ring->next = 0; 1314 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1315 desc = ring->desc64; 1316 descsize = sizeof (struct nfe_desc64); 1317 } else { 1318 desc = ring->desc32; 1319 descsize = sizeof (struct nfe_desc32); 1320 } 1321 bzero(desc, descsize * NFE_RX_RING_COUNT); 1322 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1323 if (nfe_newbuf(sc, i) != 0) 1324 return (ENOBUFS); 1325 } 1326 1327 bus_dmamap_sync(ring->rx_desc_tag, ring->rx_desc_map, 1328 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1329 1330 return (0); 1331 } 1332 1333 static int 1334 nfe_init_jrx_ring(struct nfe_softc *sc, struct nfe_jrx_ring *ring) 1335 { 1336 void *desc; 1337 size_t descsize; 1338 int i; 1339 1340 ring->jcur = ring->jnext = 0; 1341 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1342 desc = ring->jdesc64; 1343 descsize = sizeof (struct nfe_desc64); 1344 } else { 1345 desc = ring->jdesc32; 1346 descsize = sizeof (struct nfe_desc32); 1347 } 1348 bzero(desc, descsize * NFE_JUMBO_RX_RING_COUNT); 1349 for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) { 1350 if (nfe_jnewbuf(sc, i) != 0) 1351 return (ENOBUFS); 1352 } 1353 1354 bus_dmamap_sync(ring->jrx_desc_tag, ring->jrx_desc_map, 1355 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1356 1357 return (0); 1358 } 1359 1360 static void 1361 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1362 { 1363 struct nfe_rx_data *data; 1364 void *desc; 1365 int i; 1366 1367 if (sc->nfe_flags & NFE_40BIT_ADDR) 1368 desc = ring->desc64; 1369 else 1370 desc = ring->desc32; 1371 1372 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1373 data = &ring->data[i]; 1374 if (data->rx_data_map != NULL) { 1375 bus_dmamap_destroy(ring->rx_data_tag, 1376 data->rx_data_map); 1377 data->rx_data_map = NULL; 1378 } 1379 if (data->m != NULL) { 1380 m_freem(data->m); 1381 data->m = NULL; 1382 } 1383 } 1384 if (ring->rx_data_tag != NULL) { 1385 if (ring->rx_spare_map != NULL) { 1386 bus_dmamap_destroy(ring->rx_data_tag, 1387 ring->rx_spare_map); 1388 ring->rx_spare_map = NULL; 1389 } 1390 bus_dma_tag_destroy(ring->rx_data_tag); 1391 ring->rx_data_tag = NULL; 1392 } 1393 1394 if (desc != NULL) { 1395 bus_dmamap_unload(ring->rx_desc_tag, ring->rx_desc_map); 1396 bus_dmamem_free(ring->rx_desc_tag, desc, ring->rx_desc_map); 1397 ring->desc64 = NULL; 1398 ring->desc32 = NULL; 1399 } 1400 if (ring->rx_desc_tag != NULL) { 1401 bus_dma_tag_destroy(ring->rx_desc_tag); 1402 ring->rx_desc_tag = NULL; 1403 } 1404 } 1405 1406 static void 1407 nfe_free_jrx_ring(struct nfe_softc *sc, struct nfe_jrx_ring *ring) 1408 { 1409 struct nfe_rx_data *data; 1410 void *desc; 1411 int i; 1412 1413 if ((sc->nfe_flags & NFE_JUMBO_SUP) == 0) 1414 return; 1415 1416 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1417 desc = ring->jdesc64; 1418 } else { 1419 desc = ring->jdesc32; 1420 } 1421 1422 for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) { 1423 data = &ring->jdata[i]; 1424 if (data->rx_data_map != NULL) { 1425 bus_dmamap_destroy(ring->jrx_data_tag, 1426 data->rx_data_map); 1427 data->rx_data_map = NULL; 1428 } 1429 if (data->m != NULL) { 1430 m_freem(data->m); 1431 data->m = NULL; 1432 } 1433 } 1434 if (ring->jrx_data_tag != NULL) { 1435 if (ring->jrx_spare_map != NULL) { 1436 bus_dmamap_destroy(ring->jrx_data_tag, 1437 ring->jrx_spare_map); 1438 ring->jrx_spare_map = NULL; 1439 } 1440 bus_dma_tag_destroy(ring->jrx_data_tag); 1441 ring->jrx_data_tag = NULL; 1442 } 1443 1444 if (desc != NULL) { 1445 bus_dmamap_unload(ring->jrx_desc_tag, ring->jrx_desc_map); 1446 bus_dmamem_free(ring->jrx_desc_tag, desc, ring->jrx_desc_map); 1447 ring->jdesc64 = NULL; 1448 ring->jdesc32 = NULL; 1449 } 1450 1451 if (ring->jrx_desc_tag != NULL) { 1452 bus_dma_tag_destroy(ring->jrx_desc_tag); 1453 ring->jrx_desc_tag = NULL; 1454 } 1455 } 1456 1457 static int 1458 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1459 { 1460 struct nfe_dmamap_arg ctx; 1461 int i, error; 1462 void *desc; 1463 int descsize; 1464 1465 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1466 desc = ring->desc64; 1467 descsize = sizeof (struct nfe_desc64); 1468 } else { 1469 desc = ring->desc32; 1470 descsize = sizeof (struct nfe_desc32); 1471 } 1472 1473 ring->queued = 0; 1474 ring->cur = ring->next = 0; 1475 1476 error = bus_dma_tag_create(sc->nfe_parent_tag, 1477 NFE_RING_ALIGN, 0, /* alignment, boundary */ 1478 BUS_SPACE_MAXADDR, /* lowaddr */ 1479 BUS_SPACE_MAXADDR, /* highaddr */ 1480 NULL, NULL, /* filter, filterarg */ 1481 NFE_TX_RING_COUNT * descsize, 1, /* maxsize, nsegments */ 1482 NFE_TX_RING_COUNT * descsize, /* maxsegsize */ 1483 0, /* flags */ 1484 NULL, NULL, /* lockfunc, lockarg */ 1485 &ring->tx_desc_tag); 1486 if (error != 0) { 1487 device_printf(sc->nfe_dev, "could not create desc DMA tag\n"); 1488 goto fail; 1489 } 1490 1491 error = bus_dmamem_alloc(ring->tx_desc_tag, &desc, BUS_DMA_WAITOK | 1492 BUS_DMA_COHERENT | BUS_DMA_ZERO, &ring->tx_desc_map); 1493 if (error != 0) { 1494 device_printf(sc->nfe_dev, "could not create desc DMA map\n"); 1495 goto fail; 1496 } 1497 if (sc->nfe_flags & NFE_40BIT_ADDR) 1498 ring->desc64 = desc; 1499 else 1500 ring->desc32 = desc; 1501 1502 ctx.nfe_busaddr = 0; 1503 error = bus_dmamap_load(ring->tx_desc_tag, ring->tx_desc_map, desc, 1504 NFE_TX_RING_COUNT * descsize, nfe_dma_map_segs, &ctx, 0); 1505 if (error != 0) { 1506 device_printf(sc->nfe_dev, "could not load desc DMA map\n"); 1507 goto fail; 1508 } 1509 ring->physaddr = ctx.nfe_busaddr; 1510 1511 error = bus_dma_tag_create(sc->nfe_parent_tag, 1512 1, 0, 1513 BUS_SPACE_MAXADDR, 1514 BUS_SPACE_MAXADDR, 1515 NULL, NULL, 1516 NFE_TSO_MAXSIZE, 1517 NFE_MAX_SCATTER, 1518 NFE_TSO_MAXSGSIZE, 1519 0, 1520 NULL, NULL, 1521 &ring->tx_data_tag); 1522 if (error != 0) { 1523 device_printf(sc->nfe_dev, "could not create Tx DMA tag\n"); 1524 goto fail; 1525 } 1526 1527 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1528 error = bus_dmamap_create(ring->tx_data_tag, 0, 1529 &ring->data[i].tx_data_map); 1530 if (error != 0) { 1531 device_printf(sc->nfe_dev, 1532 "could not create Tx DMA map\n"); 1533 goto fail; 1534 } 1535 } 1536 1537 fail: 1538 return (error); 1539 } 1540 1541 static void 1542 nfe_init_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1543 { 1544 void *desc; 1545 size_t descsize; 1546 1547 sc->nfe_force_tx = 0; 1548 ring->queued = 0; 1549 ring->cur = ring->next = 0; 1550 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1551 desc = ring->desc64; 1552 descsize = sizeof (struct nfe_desc64); 1553 } else { 1554 desc = ring->desc32; 1555 descsize = sizeof (struct nfe_desc32); 1556 } 1557 bzero(desc, descsize * NFE_TX_RING_COUNT); 1558 1559 bus_dmamap_sync(ring->tx_desc_tag, ring->tx_desc_map, 1560 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1561 } 1562 1563 static void 1564 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1565 { 1566 struct nfe_tx_data *data; 1567 void *desc; 1568 int i; 1569 1570 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1571 desc = ring->desc64; 1572 } else { 1573 desc = ring->desc32; 1574 } 1575 1576 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1577 data = &ring->data[i]; 1578 1579 if (data->m != NULL) { 1580 bus_dmamap_sync(ring->tx_data_tag, data->tx_data_map, 1581 BUS_DMASYNC_POSTWRITE); 1582 bus_dmamap_unload(ring->tx_data_tag, data->tx_data_map); 1583 m_freem(data->m); 1584 data->m = NULL; 1585 } 1586 if (data->tx_data_map != NULL) { 1587 bus_dmamap_destroy(ring->tx_data_tag, 1588 data->tx_data_map); 1589 data->tx_data_map = NULL; 1590 } 1591 } 1592 1593 if (ring->tx_data_tag != NULL) { 1594 bus_dma_tag_destroy(ring->tx_data_tag); 1595 ring->tx_data_tag = NULL; 1596 } 1597 1598 if (desc != NULL) { 1599 bus_dmamap_sync(ring->tx_desc_tag, ring->tx_desc_map, 1600 BUS_DMASYNC_POSTWRITE); 1601 bus_dmamap_unload(ring->tx_desc_tag, ring->tx_desc_map); 1602 bus_dmamem_free(ring->tx_desc_tag, desc, ring->tx_desc_map); 1603 ring->desc64 = NULL; 1604 ring->desc32 = NULL; 1605 bus_dma_tag_destroy(ring->tx_desc_tag); 1606 ring->tx_desc_tag = NULL; 1607 } 1608 } 1609 1610 #ifdef DEVICE_POLLING 1611 static poll_handler_t nfe_poll; 1612 1613 static int 1614 nfe_poll(if_t ifp, enum poll_cmd cmd, int count) 1615 { 1616 struct nfe_softc *sc = if_getsoftc(ifp); 1617 uint32_t r; 1618 int rx_npkts = 0; 1619 1620 NFE_LOCK(sc); 1621 1622 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 1623 NFE_UNLOCK(sc); 1624 return (rx_npkts); 1625 } 1626 1627 if (sc->nfe_framesize > MCLBYTES - ETHER_HDR_LEN) 1628 rx_npkts = nfe_jrxeof(sc, count, &rx_npkts); 1629 else 1630 rx_npkts = nfe_rxeof(sc, count, &rx_npkts); 1631 nfe_txeof(sc); 1632 if (!if_sendq_empty(ifp)) 1633 nfe_start_locked(ifp); 1634 1635 if (cmd == POLL_AND_CHECK_STATUS) { 1636 if ((r = NFE_READ(sc, sc->nfe_irq_status)) == 0) { 1637 NFE_UNLOCK(sc); 1638 return (rx_npkts); 1639 } 1640 NFE_WRITE(sc, sc->nfe_irq_status, r); 1641 1642 if (r & NFE_IRQ_LINK) { 1643 NFE_READ(sc, NFE_PHY_STATUS); 1644 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1645 DPRINTF(sc, "link state changed\n"); 1646 } 1647 } 1648 NFE_UNLOCK(sc); 1649 return (rx_npkts); 1650 } 1651 #endif /* DEVICE_POLLING */ 1652 1653 static void 1654 nfe_set_intr(struct nfe_softc *sc) 1655 { 1656 1657 if (sc->nfe_msi != 0) 1658 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1659 } 1660 1661 /* In MSIX, a write to mask reegisters behaves as XOR. */ 1662 static __inline void 1663 nfe_enable_intr(struct nfe_softc *sc) 1664 { 1665 1666 if (sc->nfe_msix != 0) { 1667 /* XXX Should have a better way to enable interrupts! */ 1668 if (NFE_READ(sc, sc->nfe_irq_mask) == 0) 1669 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_intrs); 1670 } else 1671 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_intrs); 1672 } 1673 1674 static __inline void 1675 nfe_disable_intr(struct nfe_softc *sc) 1676 { 1677 1678 if (sc->nfe_msix != 0) { 1679 /* XXX Should have a better way to disable interrupts! */ 1680 if (NFE_READ(sc, sc->nfe_irq_mask) != 0) 1681 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_nointrs); 1682 } else 1683 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_nointrs); 1684 } 1685 1686 static int 1687 nfe_ioctl(if_t ifp, u_long cmd, caddr_t data) 1688 { 1689 struct nfe_softc *sc; 1690 struct ifreq *ifr; 1691 struct mii_data *mii; 1692 int error, init, mask; 1693 1694 sc = if_getsoftc(ifp); 1695 ifr = (struct ifreq *) data; 1696 error = 0; 1697 init = 0; 1698 switch (cmd) { 1699 case SIOCSIFMTU: 1700 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > NFE_JUMBO_MTU) 1701 error = EINVAL; 1702 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 1703 if ((((sc->nfe_flags & NFE_JUMBO_SUP) == 0) || 1704 (sc->nfe_jumbo_disable != 0)) && 1705 ifr->ifr_mtu > ETHERMTU) 1706 error = EINVAL; 1707 else { 1708 NFE_LOCK(sc); 1709 if_setmtu(ifp, ifr->ifr_mtu); 1710 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1711 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1712 nfe_init_locked(sc); 1713 } 1714 NFE_UNLOCK(sc); 1715 } 1716 } 1717 break; 1718 case SIOCSIFFLAGS: 1719 NFE_LOCK(sc); 1720 if (if_getflags(ifp) & IFF_UP) { 1721 /* 1722 * If only the PROMISC or ALLMULTI flag changes, then 1723 * don't do a full re-init of the chip, just update 1724 * the Rx filter. 1725 */ 1726 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) && 1727 ((if_getflags(ifp) ^ sc->nfe_if_flags) & 1728 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 1729 nfe_setmulti(sc); 1730 else 1731 nfe_init_locked(sc); 1732 } else { 1733 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1734 nfe_stop(ifp); 1735 } 1736 sc->nfe_if_flags = if_getflags(ifp); 1737 NFE_UNLOCK(sc); 1738 error = 0; 1739 break; 1740 case SIOCADDMULTI: 1741 case SIOCDELMULTI: 1742 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1743 NFE_LOCK(sc); 1744 nfe_setmulti(sc); 1745 NFE_UNLOCK(sc); 1746 error = 0; 1747 } 1748 break; 1749 case SIOCSIFMEDIA: 1750 case SIOCGIFMEDIA: 1751 mii = device_get_softc(sc->nfe_miibus); 1752 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1753 break; 1754 case SIOCSIFCAP: 1755 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1756 #ifdef DEVICE_POLLING 1757 if ((mask & IFCAP_POLLING) != 0) { 1758 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) { 1759 error = ether_poll_register(nfe_poll, ifp); 1760 if (error) 1761 break; 1762 NFE_LOCK(sc); 1763 nfe_disable_intr(sc); 1764 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 1765 NFE_UNLOCK(sc); 1766 } else { 1767 error = ether_poll_deregister(ifp); 1768 /* Enable interrupt even in error case */ 1769 NFE_LOCK(sc); 1770 nfe_enable_intr(sc); 1771 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 1772 NFE_UNLOCK(sc); 1773 } 1774 } 1775 #endif /* DEVICE_POLLING */ 1776 if ((mask & IFCAP_WOL_MAGIC) != 0 && 1777 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 1778 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 1779 if ((mask & IFCAP_TXCSUM) != 0 && 1780 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 1781 if_togglecapenable(ifp, IFCAP_TXCSUM); 1782 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 1783 if_sethwassistbits(ifp, NFE_CSUM_FEATURES, 0); 1784 else 1785 if_sethwassistbits(ifp, 0, NFE_CSUM_FEATURES); 1786 } 1787 if ((mask & IFCAP_RXCSUM) != 0 && 1788 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) { 1789 if_togglecapenable(ifp, IFCAP_RXCSUM); 1790 init++; 1791 } 1792 if ((mask & IFCAP_TSO4) != 0 && 1793 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 1794 if_togglecapenable(ifp, IFCAP_TSO4); 1795 if ((IFCAP_TSO4 & if_getcapenable(ifp)) != 0) 1796 if_sethwassistbits(ifp, CSUM_TSO, 0); 1797 else 1798 if_sethwassistbits(ifp, 0, CSUM_TSO); 1799 } 1800 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1801 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 1802 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 1803 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1804 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 1805 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 1806 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 1807 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO); 1808 init++; 1809 } 1810 /* 1811 * XXX 1812 * It seems that VLAN stripping requires Rx checksum offload. 1813 * Unfortunately FreeBSD has no way to disable only Rx side 1814 * VLAN stripping. So when we know Rx checksum offload is 1815 * disabled turn entire hardware VLAN assist off. 1816 */ 1817 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) == 0) { 1818 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 1819 init++; 1820 if_setcapenablebit(ifp, 0, 1821 (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO)); 1822 } 1823 if (init > 0 && (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1824 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1825 nfe_init(sc); 1826 } 1827 if_vlancap(ifp); 1828 break; 1829 default: 1830 error = ether_ioctl(ifp, cmd, data); 1831 break; 1832 } 1833 1834 return (error); 1835 } 1836 1837 static int 1838 nfe_intr(void *arg) 1839 { 1840 struct nfe_softc *sc; 1841 uint32_t status; 1842 1843 sc = (struct nfe_softc *)arg; 1844 1845 status = NFE_READ(sc, sc->nfe_irq_status); 1846 if (status == 0 || status == 0xffffffff) 1847 return (FILTER_STRAY); 1848 nfe_disable_intr(sc); 1849 taskqueue_enqueue(sc->nfe_tq, &sc->nfe_int_task); 1850 1851 return (FILTER_HANDLED); 1852 } 1853 1854 static void 1855 nfe_int_task(void *arg, int pending) 1856 { 1857 struct nfe_softc *sc = arg; 1858 if_t ifp = sc->nfe_ifp; 1859 uint32_t r; 1860 int domore; 1861 1862 NFE_LOCK(sc); 1863 1864 if ((r = NFE_READ(sc, sc->nfe_irq_status)) == 0) { 1865 nfe_enable_intr(sc); 1866 NFE_UNLOCK(sc); 1867 return; /* not for us */ 1868 } 1869 NFE_WRITE(sc, sc->nfe_irq_status, r); 1870 1871 DPRINTFN(sc, 5, "nfe_intr: interrupt register %x\n", r); 1872 1873 #ifdef DEVICE_POLLING 1874 if (if_getcapenable(ifp) & IFCAP_POLLING) { 1875 NFE_UNLOCK(sc); 1876 return; 1877 } 1878 #endif 1879 1880 if (r & NFE_IRQ_LINK) { 1881 NFE_READ(sc, NFE_PHY_STATUS); 1882 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1883 DPRINTF(sc, "link state changed\n"); 1884 } 1885 1886 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 1887 NFE_UNLOCK(sc); 1888 nfe_disable_intr(sc); 1889 return; 1890 } 1891 1892 domore = 0; 1893 /* check Rx ring */ 1894 if (sc->nfe_framesize > MCLBYTES - ETHER_HDR_LEN) 1895 domore = nfe_jrxeof(sc, sc->nfe_process_limit, NULL); 1896 else 1897 domore = nfe_rxeof(sc, sc->nfe_process_limit, NULL); 1898 /* check Tx ring */ 1899 nfe_txeof(sc); 1900 1901 if (!if_sendq_empty(ifp)) 1902 nfe_start_locked(ifp); 1903 1904 NFE_UNLOCK(sc); 1905 1906 if (domore || (NFE_READ(sc, sc->nfe_irq_status) != 0)) { 1907 taskqueue_enqueue(sc->nfe_tq, &sc->nfe_int_task); 1908 return; 1909 } 1910 1911 /* Reenable interrupts. */ 1912 nfe_enable_intr(sc); 1913 } 1914 1915 static __inline void 1916 nfe_discard_rxbuf(struct nfe_softc *sc, int idx) 1917 { 1918 struct nfe_desc32 *desc32; 1919 struct nfe_desc64 *desc64; 1920 struct nfe_rx_data *data; 1921 struct mbuf *m; 1922 1923 data = &sc->rxq.data[idx]; 1924 m = data->m; 1925 1926 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1927 desc64 = &sc->rxq.desc64[idx]; 1928 /* VLAN packet may have overwritten it. */ 1929 desc64->physaddr[0] = htole32(NFE_ADDR_HI(data->paddr)); 1930 desc64->physaddr[1] = htole32(NFE_ADDR_LO(data->paddr)); 1931 desc64->length = htole16(m->m_len); 1932 desc64->flags = htole16(NFE_RX_READY); 1933 } else { 1934 desc32 = &sc->rxq.desc32[idx]; 1935 desc32->length = htole16(m->m_len); 1936 desc32->flags = htole16(NFE_RX_READY); 1937 } 1938 } 1939 1940 static __inline void 1941 nfe_discard_jrxbuf(struct nfe_softc *sc, int idx) 1942 { 1943 struct nfe_desc32 *desc32; 1944 struct nfe_desc64 *desc64; 1945 struct nfe_rx_data *data; 1946 struct mbuf *m; 1947 1948 data = &sc->jrxq.jdata[idx]; 1949 m = data->m; 1950 1951 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1952 desc64 = &sc->jrxq.jdesc64[idx]; 1953 /* VLAN packet may have overwritten it. */ 1954 desc64->physaddr[0] = htole32(NFE_ADDR_HI(data->paddr)); 1955 desc64->physaddr[1] = htole32(NFE_ADDR_LO(data->paddr)); 1956 desc64->length = htole16(m->m_len); 1957 desc64->flags = htole16(NFE_RX_READY); 1958 } else { 1959 desc32 = &sc->jrxq.jdesc32[idx]; 1960 desc32->length = htole16(m->m_len); 1961 desc32->flags = htole16(NFE_RX_READY); 1962 } 1963 } 1964 1965 static int 1966 nfe_newbuf(struct nfe_softc *sc, int idx) 1967 { 1968 struct nfe_rx_data *data; 1969 struct nfe_desc32 *desc32; 1970 struct nfe_desc64 *desc64; 1971 struct mbuf *m; 1972 bus_dma_segment_t segs[1]; 1973 bus_dmamap_t map; 1974 int nsegs; 1975 1976 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1977 if (m == NULL) 1978 return (ENOBUFS); 1979 1980 m->m_len = m->m_pkthdr.len = MCLBYTES; 1981 m_adj(m, ETHER_ALIGN); 1982 1983 if (bus_dmamap_load_mbuf_sg(sc->rxq.rx_data_tag, sc->rxq.rx_spare_map, 1984 m, segs, &nsegs, BUS_DMA_NOWAIT) != 0) { 1985 m_freem(m); 1986 return (ENOBUFS); 1987 } 1988 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1989 1990 data = &sc->rxq.data[idx]; 1991 if (data->m != NULL) { 1992 bus_dmamap_sync(sc->rxq.rx_data_tag, data->rx_data_map, 1993 BUS_DMASYNC_POSTREAD); 1994 bus_dmamap_unload(sc->rxq.rx_data_tag, data->rx_data_map); 1995 } 1996 map = data->rx_data_map; 1997 data->rx_data_map = sc->rxq.rx_spare_map; 1998 sc->rxq.rx_spare_map = map; 1999 bus_dmamap_sync(sc->rxq.rx_data_tag, data->rx_data_map, 2000 BUS_DMASYNC_PREREAD); 2001 data->paddr = segs[0].ds_addr; 2002 data->m = m; 2003 /* update mapping address in h/w descriptor */ 2004 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2005 desc64 = &sc->rxq.desc64[idx]; 2006 desc64->physaddr[0] = htole32(NFE_ADDR_HI(segs[0].ds_addr)); 2007 desc64->physaddr[1] = htole32(NFE_ADDR_LO(segs[0].ds_addr)); 2008 desc64->length = htole16(segs[0].ds_len); 2009 desc64->flags = htole16(NFE_RX_READY); 2010 } else { 2011 desc32 = &sc->rxq.desc32[idx]; 2012 desc32->physaddr = htole32(NFE_ADDR_LO(segs[0].ds_addr)); 2013 desc32->length = htole16(segs[0].ds_len); 2014 desc32->flags = htole16(NFE_RX_READY); 2015 } 2016 2017 return (0); 2018 } 2019 2020 static int 2021 nfe_jnewbuf(struct nfe_softc *sc, int idx) 2022 { 2023 struct nfe_rx_data *data; 2024 struct nfe_desc32 *desc32; 2025 struct nfe_desc64 *desc64; 2026 struct mbuf *m; 2027 bus_dma_segment_t segs[1]; 2028 bus_dmamap_t map; 2029 int nsegs; 2030 2031 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 2032 if (m == NULL) 2033 return (ENOBUFS); 2034 m->m_pkthdr.len = m->m_len = MJUM9BYTES; 2035 m_adj(m, ETHER_ALIGN); 2036 2037 if (bus_dmamap_load_mbuf_sg(sc->jrxq.jrx_data_tag, 2038 sc->jrxq.jrx_spare_map, m, segs, &nsegs, BUS_DMA_NOWAIT) != 0) { 2039 m_freem(m); 2040 return (ENOBUFS); 2041 } 2042 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2043 2044 data = &sc->jrxq.jdata[idx]; 2045 if (data->m != NULL) { 2046 bus_dmamap_sync(sc->jrxq.jrx_data_tag, data->rx_data_map, 2047 BUS_DMASYNC_POSTREAD); 2048 bus_dmamap_unload(sc->jrxq.jrx_data_tag, data->rx_data_map); 2049 } 2050 map = data->rx_data_map; 2051 data->rx_data_map = sc->jrxq.jrx_spare_map; 2052 sc->jrxq.jrx_spare_map = map; 2053 bus_dmamap_sync(sc->jrxq.jrx_data_tag, data->rx_data_map, 2054 BUS_DMASYNC_PREREAD); 2055 data->paddr = segs[0].ds_addr; 2056 data->m = m; 2057 /* update mapping address in h/w descriptor */ 2058 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2059 desc64 = &sc->jrxq.jdesc64[idx]; 2060 desc64->physaddr[0] = htole32(NFE_ADDR_HI(segs[0].ds_addr)); 2061 desc64->physaddr[1] = htole32(NFE_ADDR_LO(segs[0].ds_addr)); 2062 desc64->length = htole16(segs[0].ds_len); 2063 desc64->flags = htole16(NFE_RX_READY); 2064 } else { 2065 desc32 = &sc->jrxq.jdesc32[idx]; 2066 desc32->physaddr = htole32(NFE_ADDR_LO(segs[0].ds_addr)); 2067 desc32->length = htole16(segs[0].ds_len); 2068 desc32->flags = htole16(NFE_RX_READY); 2069 } 2070 2071 return (0); 2072 } 2073 2074 static int 2075 nfe_rxeof(struct nfe_softc *sc, int count, int *rx_npktsp) 2076 { 2077 if_t ifp = sc->nfe_ifp; 2078 struct nfe_desc32 *desc32; 2079 struct nfe_desc64 *desc64; 2080 struct nfe_rx_data *data; 2081 struct mbuf *m; 2082 uint16_t flags; 2083 int len, prog, rx_npkts; 2084 uint32_t vtag = 0; 2085 2086 rx_npkts = 0; 2087 NFE_LOCK_ASSERT(sc); 2088 2089 bus_dmamap_sync(sc->rxq.rx_desc_tag, sc->rxq.rx_desc_map, 2090 BUS_DMASYNC_POSTREAD); 2091 2092 for (prog = 0;;NFE_INC(sc->rxq.cur, NFE_RX_RING_COUNT), vtag = 0) { 2093 if (count <= 0) 2094 break; 2095 count--; 2096 2097 data = &sc->rxq.data[sc->rxq.cur]; 2098 2099 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2100 desc64 = &sc->rxq.desc64[sc->rxq.cur]; 2101 vtag = le32toh(desc64->physaddr[1]); 2102 flags = le16toh(desc64->flags); 2103 len = le16toh(desc64->length) & NFE_RX_LEN_MASK; 2104 } else { 2105 desc32 = &sc->rxq.desc32[sc->rxq.cur]; 2106 flags = le16toh(desc32->flags); 2107 len = le16toh(desc32->length) & NFE_RX_LEN_MASK; 2108 } 2109 2110 if (flags & NFE_RX_READY) 2111 break; 2112 prog++; 2113 if ((sc->nfe_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 2114 if (!(flags & NFE_RX_VALID_V1)) { 2115 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2116 nfe_discard_rxbuf(sc, sc->rxq.cur); 2117 continue; 2118 } 2119 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 2120 flags &= ~NFE_RX_ERROR; 2121 len--; /* fix buffer length */ 2122 } 2123 } else { 2124 if (!(flags & NFE_RX_VALID_V2)) { 2125 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2126 nfe_discard_rxbuf(sc, sc->rxq.cur); 2127 continue; 2128 } 2129 2130 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 2131 flags &= ~NFE_RX_ERROR; 2132 len--; /* fix buffer length */ 2133 } 2134 } 2135 2136 if (flags & NFE_RX_ERROR) { 2137 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2138 nfe_discard_rxbuf(sc, sc->rxq.cur); 2139 continue; 2140 } 2141 2142 m = data->m; 2143 if (nfe_newbuf(sc, sc->rxq.cur) != 0) { 2144 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2145 nfe_discard_rxbuf(sc, sc->rxq.cur); 2146 continue; 2147 } 2148 2149 if ((vtag & NFE_RX_VTAG) != 0 && 2150 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 2151 m->m_pkthdr.ether_vtag = vtag & 0xffff; 2152 m->m_flags |= M_VLANTAG; 2153 } 2154 2155 m->m_pkthdr.len = m->m_len = len; 2156 m->m_pkthdr.rcvif = ifp; 2157 2158 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) { 2159 if ((flags & NFE_RX_IP_CSUMOK) != 0) { 2160 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2161 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2162 if ((flags & NFE_RX_TCP_CSUMOK) != 0 || 2163 (flags & NFE_RX_UDP_CSUMOK) != 0) { 2164 m->m_pkthdr.csum_flags |= 2165 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2166 m->m_pkthdr.csum_data = 0xffff; 2167 } 2168 } 2169 } 2170 2171 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2172 2173 NFE_UNLOCK(sc); 2174 if_input(ifp, m); 2175 NFE_LOCK(sc); 2176 rx_npkts++; 2177 } 2178 2179 if (prog > 0) 2180 bus_dmamap_sync(sc->rxq.rx_desc_tag, sc->rxq.rx_desc_map, 2181 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2182 2183 if (rx_npktsp != NULL) 2184 *rx_npktsp = rx_npkts; 2185 return (count > 0 ? 0 : EAGAIN); 2186 } 2187 2188 static int 2189 nfe_jrxeof(struct nfe_softc *sc, int count, int *rx_npktsp) 2190 { 2191 if_t ifp = sc->nfe_ifp; 2192 struct nfe_desc32 *desc32; 2193 struct nfe_desc64 *desc64; 2194 struct nfe_rx_data *data; 2195 struct mbuf *m; 2196 uint16_t flags; 2197 int len, prog, rx_npkts; 2198 uint32_t vtag = 0; 2199 2200 rx_npkts = 0; 2201 NFE_LOCK_ASSERT(sc); 2202 2203 bus_dmamap_sync(sc->jrxq.jrx_desc_tag, sc->jrxq.jrx_desc_map, 2204 BUS_DMASYNC_POSTREAD); 2205 2206 for (prog = 0;;NFE_INC(sc->jrxq.jcur, NFE_JUMBO_RX_RING_COUNT), 2207 vtag = 0) { 2208 if (count <= 0) 2209 break; 2210 count--; 2211 2212 data = &sc->jrxq.jdata[sc->jrxq.jcur]; 2213 2214 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2215 desc64 = &sc->jrxq.jdesc64[sc->jrxq.jcur]; 2216 vtag = le32toh(desc64->physaddr[1]); 2217 flags = le16toh(desc64->flags); 2218 len = le16toh(desc64->length) & NFE_RX_LEN_MASK; 2219 } else { 2220 desc32 = &sc->jrxq.jdesc32[sc->jrxq.jcur]; 2221 flags = le16toh(desc32->flags); 2222 len = le16toh(desc32->length) & NFE_RX_LEN_MASK; 2223 } 2224 2225 if (flags & NFE_RX_READY) 2226 break; 2227 prog++; 2228 if ((sc->nfe_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 2229 if (!(flags & NFE_RX_VALID_V1)) { 2230 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2231 nfe_discard_jrxbuf(sc, sc->jrxq.jcur); 2232 continue; 2233 } 2234 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 2235 flags &= ~NFE_RX_ERROR; 2236 len--; /* fix buffer length */ 2237 } 2238 } else { 2239 if (!(flags & NFE_RX_VALID_V2)) { 2240 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2241 nfe_discard_jrxbuf(sc, sc->jrxq.jcur); 2242 continue; 2243 } 2244 2245 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 2246 flags &= ~NFE_RX_ERROR; 2247 len--; /* fix buffer length */ 2248 } 2249 } 2250 2251 if (flags & NFE_RX_ERROR) { 2252 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2253 nfe_discard_jrxbuf(sc, sc->jrxq.jcur); 2254 continue; 2255 } 2256 2257 m = data->m; 2258 if (nfe_jnewbuf(sc, sc->jrxq.jcur) != 0) { 2259 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2260 nfe_discard_jrxbuf(sc, sc->jrxq.jcur); 2261 continue; 2262 } 2263 2264 if ((vtag & NFE_RX_VTAG) != 0 && 2265 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 2266 m->m_pkthdr.ether_vtag = vtag & 0xffff; 2267 m->m_flags |= M_VLANTAG; 2268 } 2269 2270 m->m_pkthdr.len = m->m_len = len; 2271 m->m_pkthdr.rcvif = ifp; 2272 2273 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) { 2274 if ((flags & NFE_RX_IP_CSUMOK) != 0) { 2275 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2276 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2277 if ((flags & NFE_RX_TCP_CSUMOK) != 0 || 2278 (flags & NFE_RX_UDP_CSUMOK) != 0) { 2279 m->m_pkthdr.csum_flags |= 2280 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2281 m->m_pkthdr.csum_data = 0xffff; 2282 } 2283 } 2284 } 2285 2286 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2287 2288 NFE_UNLOCK(sc); 2289 if_input(ifp, m); 2290 NFE_LOCK(sc); 2291 rx_npkts++; 2292 } 2293 2294 if (prog > 0) 2295 bus_dmamap_sync(sc->jrxq.jrx_desc_tag, sc->jrxq.jrx_desc_map, 2296 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2297 2298 if (rx_npktsp != NULL) 2299 *rx_npktsp = rx_npkts; 2300 return (count > 0 ? 0 : EAGAIN); 2301 } 2302 2303 static void 2304 nfe_txeof(struct nfe_softc *sc) 2305 { 2306 if_t ifp = sc->nfe_ifp; 2307 struct nfe_desc32 *desc32; 2308 struct nfe_desc64 *desc64; 2309 struct nfe_tx_data *data = NULL; 2310 uint16_t flags; 2311 int cons, prog; 2312 2313 NFE_LOCK_ASSERT(sc); 2314 2315 bus_dmamap_sync(sc->txq.tx_desc_tag, sc->txq.tx_desc_map, 2316 BUS_DMASYNC_POSTREAD); 2317 2318 prog = 0; 2319 for (cons = sc->txq.next; cons != sc->txq.cur; 2320 NFE_INC(cons, NFE_TX_RING_COUNT)) { 2321 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2322 desc64 = &sc->txq.desc64[cons]; 2323 flags = le16toh(desc64->flags); 2324 } else { 2325 desc32 = &sc->txq.desc32[cons]; 2326 flags = le16toh(desc32->flags); 2327 } 2328 2329 if (flags & NFE_TX_VALID) 2330 break; 2331 2332 prog++; 2333 sc->txq.queued--; 2334 data = &sc->txq.data[cons]; 2335 2336 if ((sc->nfe_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 2337 if ((flags & NFE_TX_LASTFRAG_V1) == 0) 2338 continue; 2339 if ((flags & NFE_TX_ERROR_V1) != 0) { 2340 device_printf(sc->nfe_dev, 2341 "tx v1 error 0x%4b\n", flags, NFE_V1_TXERR); 2342 2343 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2344 } else 2345 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2346 } else { 2347 if ((flags & NFE_TX_LASTFRAG_V2) == 0) 2348 continue; 2349 if ((flags & NFE_TX_ERROR_V2) != 0) { 2350 device_printf(sc->nfe_dev, 2351 "tx v2 error 0x%4b\n", flags, NFE_V2_TXERR); 2352 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2353 } else 2354 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2355 } 2356 2357 /* last fragment of the mbuf chain transmitted */ 2358 KASSERT(data->m != NULL, ("%s: freeing NULL mbuf!", __func__)); 2359 bus_dmamap_sync(sc->txq.tx_data_tag, data->tx_data_map, 2360 BUS_DMASYNC_POSTWRITE); 2361 bus_dmamap_unload(sc->txq.tx_data_tag, data->tx_data_map); 2362 m_freem(data->m); 2363 data->m = NULL; 2364 } 2365 2366 if (prog > 0) { 2367 sc->nfe_force_tx = 0; 2368 sc->txq.next = cons; 2369 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2370 if (sc->txq.queued == 0) 2371 sc->nfe_watchdog_timer = 0; 2372 } 2373 } 2374 2375 static int 2376 nfe_encap(struct nfe_softc *sc, struct mbuf **m_head) 2377 { 2378 struct nfe_desc32 *desc32 = NULL; 2379 struct nfe_desc64 *desc64 = NULL; 2380 bus_dmamap_t map; 2381 bus_dma_segment_t segs[NFE_MAX_SCATTER]; 2382 int error, i, nsegs, prod, si; 2383 uint32_t tsosegsz; 2384 uint16_t cflags, flags; 2385 struct mbuf *m; 2386 2387 prod = si = sc->txq.cur; 2388 map = sc->txq.data[prod].tx_data_map; 2389 2390 error = bus_dmamap_load_mbuf_sg(sc->txq.tx_data_tag, map, *m_head, segs, 2391 &nsegs, BUS_DMA_NOWAIT); 2392 if (error == EFBIG) { 2393 m = m_collapse(*m_head, M_NOWAIT, NFE_MAX_SCATTER); 2394 if (m == NULL) { 2395 m_freem(*m_head); 2396 *m_head = NULL; 2397 return (ENOBUFS); 2398 } 2399 *m_head = m; 2400 error = bus_dmamap_load_mbuf_sg(sc->txq.tx_data_tag, map, 2401 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2402 if (error != 0) { 2403 m_freem(*m_head); 2404 *m_head = NULL; 2405 return (ENOBUFS); 2406 } 2407 } else if (error != 0) 2408 return (error); 2409 if (nsegs == 0) { 2410 m_freem(*m_head); 2411 *m_head = NULL; 2412 return (EIO); 2413 } 2414 2415 if (sc->txq.queued + nsegs >= NFE_TX_RING_COUNT - 2) { 2416 bus_dmamap_unload(sc->txq.tx_data_tag, map); 2417 return (ENOBUFS); 2418 } 2419 2420 m = *m_head; 2421 cflags = flags = 0; 2422 tsosegsz = 0; 2423 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2424 tsosegsz = (uint32_t)m->m_pkthdr.tso_segsz << 2425 NFE_TX_TSO_SHIFT; 2426 cflags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_UDP_CSUM); 2427 cflags |= NFE_TX_TSO; 2428 } else if ((m->m_pkthdr.csum_flags & NFE_CSUM_FEATURES) != 0) { 2429 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2430 cflags |= NFE_TX_IP_CSUM; 2431 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2432 cflags |= NFE_TX_TCP_UDP_CSUM; 2433 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2434 cflags |= NFE_TX_TCP_UDP_CSUM; 2435 } 2436 2437 for (i = 0; i < nsegs; i++) { 2438 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2439 desc64 = &sc->txq.desc64[prod]; 2440 desc64->physaddr[0] = 2441 htole32(NFE_ADDR_HI(segs[i].ds_addr)); 2442 desc64->physaddr[1] = 2443 htole32(NFE_ADDR_LO(segs[i].ds_addr)); 2444 desc64->vtag = 0; 2445 desc64->length = htole16(segs[i].ds_len - 1); 2446 desc64->flags = htole16(flags); 2447 } else { 2448 desc32 = &sc->txq.desc32[prod]; 2449 desc32->physaddr = 2450 htole32(NFE_ADDR_LO(segs[i].ds_addr)); 2451 desc32->length = htole16(segs[i].ds_len - 1); 2452 desc32->flags = htole16(flags); 2453 } 2454 2455 /* 2456 * Setting of the valid bit in the first descriptor is 2457 * deferred until the whole chain is fully setup. 2458 */ 2459 flags |= NFE_TX_VALID; 2460 2461 sc->txq.queued++; 2462 NFE_INC(prod, NFE_TX_RING_COUNT); 2463 } 2464 2465 /* 2466 * the whole mbuf chain has been DMA mapped, fix last/first descriptor. 2467 * csum flags, vtag and TSO belong to the first fragment only. 2468 */ 2469 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2470 desc64->flags |= htole16(NFE_TX_LASTFRAG_V2); 2471 desc64 = &sc->txq.desc64[si]; 2472 if ((m->m_flags & M_VLANTAG) != 0) 2473 desc64->vtag = htole32(NFE_TX_VTAG | 2474 m->m_pkthdr.ether_vtag); 2475 if (tsosegsz != 0) { 2476 /* 2477 * XXX 2478 * The following indicates the descriptor element 2479 * is a 32bit quantity. 2480 */ 2481 desc64->length |= htole16((uint16_t)tsosegsz); 2482 desc64->flags |= htole16(tsosegsz >> 16); 2483 } 2484 /* 2485 * finally, set the valid/checksum/TSO bit in the first 2486 * descriptor. 2487 */ 2488 desc64->flags |= htole16(NFE_TX_VALID | cflags); 2489 } else { 2490 if (sc->nfe_flags & NFE_JUMBO_SUP) 2491 desc32->flags |= htole16(NFE_TX_LASTFRAG_V2); 2492 else 2493 desc32->flags |= htole16(NFE_TX_LASTFRAG_V1); 2494 desc32 = &sc->txq.desc32[si]; 2495 if (tsosegsz != 0) { 2496 /* 2497 * XXX 2498 * The following indicates the descriptor element 2499 * is a 32bit quantity. 2500 */ 2501 desc32->length |= htole16((uint16_t)tsosegsz); 2502 desc32->flags |= htole16(tsosegsz >> 16); 2503 } 2504 /* 2505 * finally, set the valid/checksum/TSO bit in the first 2506 * descriptor. 2507 */ 2508 desc32->flags |= htole16(NFE_TX_VALID | cflags); 2509 } 2510 2511 sc->txq.cur = prod; 2512 prod = (prod + NFE_TX_RING_COUNT - 1) % NFE_TX_RING_COUNT; 2513 sc->txq.data[si].tx_data_map = sc->txq.data[prod].tx_data_map; 2514 sc->txq.data[prod].tx_data_map = map; 2515 sc->txq.data[prod].m = m; 2516 2517 bus_dmamap_sync(sc->txq.tx_data_tag, map, BUS_DMASYNC_PREWRITE); 2518 2519 return (0); 2520 } 2521 2522 struct nfe_hash_maddr_ctx { 2523 uint8_t addr[ETHER_ADDR_LEN]; 2524 uint8_t mask[ETHER_ADDR_LEN]; 2525 }; 2526 2527 static u_int 2528 nfe_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 2529 { 2530 struct nfe_hash_maddr_ctx *ctx = arg; 2531 uint8_t *addrp, mcaddr; 2532 int j; 2533 2534 addrp = LLADDR(sdl); 2535 for (j = 0; j < ETHER_ADDR_LEN; j++) { 2536 mcaddr = addrp[j]; 2537 ctx->addr[j] &= mcaddr; 2538 ctx->mask[j] &= ~mcaddr; 2539 } 2540 2541 return (1); 2542 } 2543 2544 static void 2545 nfe_setmulti(struct nfe_softc *sc) 2546 { 2547 if_t ifp = sc->nfe_ifp; 2548 struct nfe_hash_maddr_ctx ctx; 2549 uint32_t filter; 2550 uint8_t etherbroadcastaddr[ETHER_ADDR_LEN] = { 2551 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 2552 }; 2553 int i; 2554 2555 NFE_LOCK_ASSERT(sc); 2556 2557 if ((if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 2558 bzero(ctx.addr, ETHER_ADDR_LEN); 2559 bzero(ctx.mask, ETHER_ADDR_LEN); 2560 goto done; 2561 } 2562 2563 bcopy(etherbroadcastaddr, ctx.addr, ETHER_ADDR_LEN); 2564 bcopy(etherbroadcastaddr, ctx.mask, ETHER_ADDR_LEN); 2565 2566 if_foreach_llmaddr(ifp, nfe_hash_maddr, &ctx); 2567 2568 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2569 ctx.mask[i] |= ctx.addr[i]; 2570 } 2571 2572 done: 2573 ctx.addr[0] |= 0x01; /* make sure multicast bit is set */ 2574 2575 NFE_WRITE(sc, NFE_MULTIADDR_HI, ctx.addr[3] << 24 | ctx.addr[2] << 16 | 2576 ctx.addr[1] << 8 | ctx.addr[0]); 2577 NFE_WRITE(sc, NFE_MULTIADDR_LO, 2578 ctx.addr[5] << 8 | ctx.addr[4]); 2579 NFE_WRITE(sc, NFE_MULTIMASK_HI, ctx.mask[3] << 24 | ctx.mask[2] << 16 | 2580 ctx.mask[1] << 8 | ctx.mask[0]); 2581 NFE_WRITE(sc, NFE_MULTIMASK_LO, 2582 ctx.mask[5] << 8 | ctx.mask[4]); 2583 2584 filter = NFE_READ(sc, NFE_RXFILTER); 2585 filter &= NFE_PFF_RX_PAUSE; 2586 filter |= NFE_RXFILTER_MAGIC; 2587 filter |= (if_getflags(ifp) & IFF_PROMISC) ? NFE_PFF_PROMISC : NFE_PFF_U2M; 2588 NFE_WRITE(sc, NFE_RXFILTER, filter); 2589 } 2590 2591 static void 2592 nfe_start(if_t ifp) 2593 { 2594 struct nfe_softc *sc = if_getsoftc(ifp); 2595 2596 NFE_LOCK(sc); 2597 nfe_start_locked(ifp); 2598 NFE_UNLOCK(sc); 2599 } 2600 2601 static void 2602 nfe_start_locked(if_t ifp) 2603 { 2604 struct nfe_softc *sc = if_getsoftc(ifp); 2605 struct mbuf *m0; 2606 int enq = 0; 2607 2608 NFE_LOCK_ASSERT(sc); 2609 2610 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2611 IFF_DRV_RUNNING || sc->nfe_link == 0) 2612 return; 2613 2614 while (!if_sendq_empty(ifp)) { 2615 m0 = if_dequeue(ifp); 2616 2617 if (m0 == NULL) 2618 break; 2619 2620 if (nfe_encap(sc, &m0) != 0) { 2621 if (m0 == NULL) 2622 break; 2623 if_sendq_prepend(ifp, m0); 2624 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2625 break; 2626 } 2627 enq++; 2628 if_etherbpfmtap(ifp, m0); 2629 } 2630 2631 if (enq > 0) { 2632 bus_dmamap_sync(sc->txq.tx_desc_tag, sc->txq.tx_desc_map, 2633 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2634 2635 /* kick Tx */ 2636 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 2637 2638 /* 2639 * Set a timeout in case the chip goes out to lunch. 2640 */ 2641 sc->nfe_watchdog_timer = 5; 2642 } 2643 } 2644 2645 static void 2646 nfe_watchdog(if_t ifp) 2647 { 2648 struct nfe_softc *sc = if_getsoftc(ifp); 2649 2650 if (sc->nfe_watchdog_timer == 0 || --sc->nfe_watchdog_timer) 2651 return; 2652 2653 /* Check if we've lost Tx completion interrupt. */ 2654 nfe_txeof(sc); 2655 if (sc->txq.queued == 0) { 2656 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 2657 "-- recovering\n"); 2658 if (!if_sendq_empty(ifp)) 2659 nfe_start_locked(ifp); 2660 return; 2661 } 2662 /* Check if we've lost start Tx command. */ 2663 sc->nfe_force_tx++; 2664 if (sc->nfe_force_tx <= 3) { 2665 /* 2666 * If this is the case for watchdog timeout, the following 2667 * code should go to nfe_txeof(). 2668 */ 2669 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 2670 return; 2671 } 2672 sc->nfe_force_tx = 0; 2673 2674 if_printf(ifp, "watchdog timeout\n"); 2675 2676 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2677 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2678 nfe_init_locked(sc); 2679 } 2680 2681 static void 2682 nfe_init(void *xsc) 2683 { 2684 struct nfe_softc *sc = xsc; 2685 2686 NFE_LOCK(sc); 2687 nfe_init_locked(sc); 2688 NFE_UNLOCK(sc); 2689 } 2690 2691 static void 2692 nfe_init_locked(void *xsc) 2693 { 2694 struct nfe_softc *sc = xsc; 2695 if_t ifp = sc->nfe_ifp; 2696 struct mii_data *mii; 2697 uint32_t val; 2698 int error; 2699 2700 NFE_LOCK_ASSERT(sc); 2701 2702 mii = device_get_softc(sc->nfe_miibus); 2703 2704 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2705 return; 2706 2707 nfe_stop(ifp); 2708 2709 sc->nfe_framesize = if_getmtu(ifp) + NFE_RX_HEADERS; 2710 2711 nfe_init_tx_ring(sc, &sc->txq); 2712 if (sc->nfe_framesize > (MCLBYTES - ETHER_HDR_LEN)) 2713 error = nfe_init_jrx_ring(sc, &sc->jrxq); 2714 else 2715 error = nfe_init_rx_ring(sc, &sc->rxq); 2716 if (error != 0) { 2717 device_printf(sc->nfe_dev, 2718 "initialization failed: no memory for rx buffers\n"); 2719 nfe_stop(ifp); 2720 return; 2721 } 2722 2723 val = 0; 2724 if ((sc->nfe_flags & NFE_CORRECT_MACADDR) != 0) 2725 val |= NFE_MAC_ADDR_INORDER; 2726 NFE_WRITE(sc, NFE_TX_UNK, val); 2727 NFE_WRITE(sc, NFE_STATUS, 0); 2728 2729 if ((sc->nfe_flags & NFE_TX_FLOW_CTRL) != 0) 2730 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, NFE_TX_PAUSE_FRAME_DISABLE); 2731 2732 sc->rxtxctl = NFE_RXTX_BIT2; 2733 if (sc->nfe_flags & NFE_40BIT_ADDR) 2734 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 2735 else if (sc->nfe_flags & NFE_JUMBO_SUP) 2736 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 2737 2738 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 2739 sc->rxtxctl |= NFE_RXTX_RXCSUM; 2740 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 2741 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT | NFE_RXTX_VTAG_STRIP; 2742 2743 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 2744 DELAY(10); 2745 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 2746 2747 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 2748 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 2749 else 2750 NFE_WRITE(sc, NFE_VTAG_CTL, 0); 2751 2752 NFE_WRITE(sc, NFE_SETUP_R6, 0); 2753 2754 /* set MAC address */ 2755 nfe_set_macaddr(sc, if_getlladdr(ifp)); 2756 2757 /* tell MAC where rings are in memory */ 2758 if (sc->nfe_framesize > MCLBYTES - ETHER_HDR_LEN) { 2759 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, 2760 NFE_ADDR_HI(sc->jrxq.jphysaddr)); 2761 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, 2762 NFE_ADDR_LO(sc->jrxq.jphysaddr)); 2763 } else { 2764 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, 2765 NFE_ADDR_HI(sc->rxq.physaddr)); 2766 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, 2767 NFE_ADDR_LO(sc->rxq.physaddr)); 2768 } 2769 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, NFE_ADDR_HI(sc->txq.physaddr)); 2770 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, NFE_ADDR_LO(sc->txq.physaddr)); 2771 2772 NFE_WRITE(sc, NFE_RING_SIZE, 2773 (NFE_RX_RING_COUNT - 1) << 16 | 2774 (NFE_TX_RING_COUNT - 1)); 2775 2776 NFE_WRITE(sc, NFE_RXBUFSZ, sc->nfe_framesize); 2777 2778 /* force MAC to wakeup */ 2779 val = NFE_READ(sc, NFE_PWR_STATE); 2780 if ((val & NFE_PWR_WAKEUP) == 0) 2781 NFE_WRITE(sc, NFE_PWR_STATE, val | NFE_PWR_WAKEUP); 2782 DELAY(10); 2783 val = NFE_READ(sc, NFE_PWR_STATE); 2784 NFE_WRITE(sc, NFE_PWR_STATE, val | NFE_PWR_VALID); 2785 2786 #if 1 2787 /* configure interrupts coalescing/mitigation */ 2788 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 2789 #else 2790 /* no interrupt mitigation: one interrupt per packet */ 2791 NFE_WRITE(sc, NFE_IMTIMER, 970); 2792 #endif 2793 2794 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC_10_100); 2795 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 2796 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 2797 2798 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 2799 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 2800 2801 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 2802 /* Disable WOL. */ 2803 NFE_WRITE(sc, NFE_WOL_CTL, 0); 2804 2805 sc->rxtxctl &= ~NFE_RXTX_BIT2; 2806 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 2807 DELAY(10); 2808 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 2809 2810 /* set Rx filter */ 2811 nfe_setmulti(sc); 2812 2813 /* enable Rx */ 2814 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 2815 2816 /* enable Tx */ 2817 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 2818 2819 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 2820 2821 /* Clear hardware stats. */ 2822 nfe_stats_clear(sc); 2823 2824 #ifdef DEVICE_POLLING 2825 if (if_getcapenable(ifp) & IFCAP_POLLING) 2826 nfe_disable_intr(sc); 2827 else 2828 #endif 2829 nfe_set_intr(sc); 2830 nfe_enable_intr(sc); /* enable interrupts */ 2831 2832 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 2833 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2834 2835 sc->nfe_link = 0; 2836 mii_mediachg(mii); 2837 2838 callout_reset(&sc->nfe_stat_ch, hz, nfe_tick, sc); 2839 } 2840 2841 static void 2842 nfe_stop(if_t ifp) 2843 { 2844 struct nfe_softc *sc = if_getsoftc(ifp); 2845 struct nfe_rx_ring *rx_ring; 2846 struct nfe_jrx_ring *jrx_ring; 2847 struct nfe_tx_ring *tx_ring; 2848 struct nfe_rx_data *rdata; 2849 struct nfe_tx_data *tdata; 2850 int i; 2851 2852 NFE_LOCK_ASSERT(sc); 2853 2854 sc->nfe_watchdog_timer = 0; 2855 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2856 2857 callout_stop(&sc->nfe_stat_ch); 2858 2859 /* abort Tx */ 2860 NFE_WRITE(sc, NFE_TX_CTL, 0); 2861 2862 /* disable Rx */ 2863 NFE_WRITE(sc, NFE_RX_CTL, 0); 2864 2865 /* disable interrupts */ 2866 nfe_disable_intr(sc); 2867 2868 sc->nfe_link = 0; 2869 2870 /* free Rx and Tx mbufs still in the queues. */ 2871 rx_ring = &sc->rxq; 2872 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 2873 rdata = &rx_ring->data[i]; 2874 if (rdata->m != NULL) { 2875 bus_dmamap_sync(rx_ring->rx_data_tag, 2876 rdata->rx_data_map, BUS_DMASYNC_POSTREAD); 2877 bus_dmamap_unload(rx_ring->rx_data_tag, 2878 rdata->rx_data_map); 2879 m_freem(rdata->m); 2880 rdata->m = NULL; 2881 } 2882 } 2883 2884 if ((sc->nfe_flags & NFE_JUMBO_SUP) != 0) { 2885 jrx_ring = &sc->jrxq; 2886 for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) { 2887 rdata = &jrx_ring->jdata[i]; 2888 if (rdata->m != NULL) { 2889 bus_dmamap_sync(jrx_ring->jrx_data_tag, 2890 rdata->rx_data_map, BUS_DMASYNC_POSTREAD); 2891 bus_dmamap_unload(jrx_ring->jrx_data_tag, 2892 rdata->rx_data_map); 2893 m_freem(rdata->m); 2894 rdata->m = NULL; 2895 } 2896 } 2897 } 2898 2899 tx_ring = &sc->txq; 2900 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 2901 tdata = &tx_ring->data[i]; 2902 if (tdata->m != NULL) { 2903 bus_dmamap_sync(tx_ring->tx_data_tag, 2904 tdata->tx_data_map, BUS_DMASYNC_POSTWRITE); 2905 bus_dmamap_unload(tx_ring->tx_data_tag, 2906 tdata->tx_data_map); 2907 m_freem(tdata->m); 2908 tdata->m = NULL; 2909 } 2910 } 2911 /* Update hardware stats. */ 2912 nfe_stats_update(sc); 2913 } 2914 2915 static int 2916 nfe_ifmedia_upd(if_t ifp) 2917 { 2918 struct nfe_softc *sc = if_getsoftc(ifp); 2919 struct mii_data *mii; 2920 2921 NFE_LOCK(sc); 2922 mii = device_get_softc(sc->nfe_miibus); 2923 mii_mediachg(mii); 2924 NFE_UNLOCK(sc); 2925 2926 return (0); 2927 } 2928 2929 static void 2930 nfe_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 2931 { 2932 struct nfe_softc *sc; 2933 struct mii_data *mii; 2934 2935 sc = if_getsoftc(ifp); 2936 2937 NFE_LOCK(sc); 2938 mii = device_get_softc(sc->nfe_miibus); 2939 mii_pollstat(mii); 2940 2941 ifmr->ifm_active = mii->mii_media_active; 2942 ifmr->ifm_status = mii->mii_media_status; 2943 NFE_UNLOCK(sc); 2944 } 2945 2946 void 2947 nfe_tick(void *xsc) 2948 { 2949 struct nfe_softc *sc; 2950 struct mii_data *mii; 2951 if_t ifp; 2952 2953 sc = (struct nfe_softc *)xsc; 2954 2955 NFE_LOCK_ASSERT(sc); 2956 2957 ifp = sc->nfe_ifp; 2958 2959 mii = device_get_softc(sc->nfe_miibus); 2960 mii_tick(mii); 2961 nfe_stats_update(sc); 2962 nfe_watchdog(ifp); 2963 callout_reset(&sc->nfe_stat_ch, hz, nfe_tick, sc); 2964 } 2965 2966 static int 2967 nfe_shutdown(device_t dev) 2968 { 2969 2970 return (nfe_suspend(dev)); 2971 } 2972 2973 static void 2974 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 2975 { 2976 uint32_t val; 2977 2978 if ((sc->nfe_flags & NFE_CORRECT_MACADDR) == 0) { 2979 val = NFE_READ(sc, NFE_MACADDR_LO); 2980 addr[0] = (val >> 8) & 0xff; 2981 addr[1] = (val & 0xff); 2982 2983 val = NFE_READ(sc, NFE_MACADDR_HI); 2984 addr[2] = (val >> 24) & 0xff; 2985 addr[3] = (val >> 16) & 0xff; 2986 addr[4] = (val >> 8) & 0xff; 2987 addr[5] = (val & 0xff); 2988 } else { 2989 val = NFE_READ(sc, NFE_MACADDR_LO); 2990 addr[5] = (val >> 8) & 0xff; 2991 addr[4] = (val & 0xff); 2992 2993 val = NFE_READ(sc, NFE_MACADDR_HI); 2994 addr[3] = (val >> 24) & 0xff; 2995 addr[2] = (val >> 16) & 0xff; 2996 addr[1] = (val >> 8) & 0xff; 2997 addr[0] = (val & 0xff); 2998 } 2999 } 3000 3001 static void 3002 nfe_set_macaddr(struct nfe_softc *sc, uint8_t *addr) 3003 { 3004 3005 NFE_WRITE(sc, NFE_MACADDR_LO, addr[5] << 8 | addr[4]); 3006 NFE_WRITE(sc, NFE_MACADDR_HI, addr[3] << 24 | addr[2] << 16 | 3007 addr[1] << 8 | addr[0]); 3008 } 3009 3010 /* 3011 * Map a single buffer address. 3012 */ 3013 3014 static void 3015 nfe_dma_map_segs(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3016 { 3017 struct nfe_dmamap_arg *ctx; 3018 3019 if (error != 0) 3020 return; 3021 3022 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 3023 3024 ctx = (struct nfe_dmamap_arg *)arg; 3025 ctx->nfe_busaddr = segs[0].ds_addr; 3026 } 3027 3028 static int 3029 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3030 { 3031 int error, value; 3032 3033 if (!arg1) 3034 return (EINVAL); 3035 value = *(int *)arg1; 3036 error = sysctl_handle_int(oidp, &value, 0, req); 3037 if (error || !req->newptr) 3038 return (error); 3039 if (value < low || value > high) 3040 return (EINVAL); 3041 *(int *)arg1 = value; 3042 3043 return (0); 3044 } 3045 3046 static int 3047 sysctl_hw_nfe_proc_limit(SYSCTL_HANDLER_ARGS) 3048 { 3049 3050 return (sysctl_int_range(oidp, arg1, arg2, req, NFE_PROC_MIN, 3051 NFE_PROC_MAX)); 3052 } 3053 3054 #define NFE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 3055 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 3056 #define NFE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 3057 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 3058 3059 static void 3060 nfe_sysctl_node(struct nfe_softc *sc) 3061 { 3062 struct sysctl_ctx_list *ctx; 3063 struct sysctl_oid_list *child, *parent; 3064 struct sysctl_oid *tree; 3065 struct nfe_hw_stats *stats; 3066 int error; 3067 3068 stats = &sc->nfe_stats; 3069 ctx = device_get_sysctl_ctx(sc->nfe_dev); 3070 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->nfe_dev)); 3071 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 3072 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 3073 &sc->nfe_process_limit, 0, sysctl_hw_nfe_proc_limit, "I", 3074 "max number of Rx events to process"); 3075 3076 sc->nfe_process_limit = NFE_PROC_DEFAULT; 3077 error = resource_int_value(device_get_name(sc->nfe_dev), 3078 device_get_unit(sc->nfe_dev), "process_limit", 3079 &sc->nfe_process_limit); 3080 if (error == 0) { 3081 if (sc->nfe_process_limit < NFE_PROC_MIN || 3082 sc->nfe_process_limit > NFE_PROC_MAX) { 3083 device_printf(sc->nfe_dev, 3084 "process_limit value out of range; " 3085 "using default: %d\n", NFE_PROC_DEFAULT); 3086 sc->nfe_process_limit = NFE_PROC_DEFAULT; 3087 } 3088 } 3089 3090 if ((sc->nfe_flags & (NFE_MIB_V1 | NFE_MIB_V2 | NFE_MIB_V3)) == 0) 3091 return; 3092 3093 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 3094 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "NFE statistics"); 3095 parent = SYSCTL_CHILDREN(tree); 3096 3097 /* Rx statistics. */ 3098 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 3099 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 3100 child = SYSCTL_CHILDREN(tree); 3101 3102 NFE_SYSCTL_STAT_ADD32(ctx, child, "frame_errors", 3103 &stats->rx_frame_errors, "Framing Errors"); 3104 NFE_SYSCTL_STAT_ADD32(ctx, child, "extra_bytes", 3105 &stats->rx_extra_bytes, "Extra Bytes"); 3106 NFE_SYSCTL_STAT_ADD32(ctx, child, "late_cols", 3107 &stats->rx_late_cols, "Late Collisions"); 3108 NFE_SYSCTL_STAT_ADD32(ctx, child, "runts", 3109 &stats->rx_runts, "Runts"); 3110 NFE_SYSCTL_STAT_ADD32(ctx, child, "jumbos", 3111 &stats->rx_jumbos, "Jumbos"); 3112 NFE_SYSCTL_STAT_ADD32(ctx, child, "fifo_overuns", 3113 &stats->rx_fifo_overuns, "FIFO Overruns"); 3114 NFE_SYSCTL_STAT_ADD32(ctx, child, "crc_errors", 3115 &stats->rx_crc_errors, "CRC Errors"); 3116 NFE_SYSCTL_STAT_ADD32(ctx, child, "fae", 3117 &stats->rx_fae, "Frame Alignment Errors"); 3118 NFE_SYSCTL_STAT_ADD32(ctx, child, "len_errors", 3119 &stats->rx_len_errors, "Length Errors"); 3120 NFE_SYSCTL_STAT_ADD32(ctx, child, "unicast", 3121 &stats->rx_unicast, "Unicast Frames"); 3122 NFE_SYSCTL_STAT_ADD32(ctx, child, "multicast", 3123 &stats->rx_multicast, "Multicast Frames"); 3124 NFE_SYSCTL_STAT_ADD32(ctx, child, "broadcast", 3125 &stats->rx_broadcast, "Broadcast Frames"); 3126 if ((sc->nfe_flags & NFE_MIB_V2) != 0) { 3127 NFE_SYSCTL_STAT_ADD64(ctx, child, "octets", 3128 &stats->rx_octets, "Octets"); 3129 NFE_SYSCTL_STAT_ADD32(ctx, child, "pause", 3130 &stats->rx_pause, "Pause frames"); 3131 NFE_SYSCTL_STAT_ADD32(ctx, child, "drops", 3132 &stats->rx_drops, "Drop frames"); 3133 } 3134 3135 /* Tx statistics. */ 3136 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 3137 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 3138 child = SYSCTL_CHILDREN(tree); 3139 NFE_SYSCTL_STAT_ADD64(ctx, child, "octets", 3140 &stats->tx_octets, "Octets"); 3141 NFE_SYSCTL_STAT_ADD32(ctx, child, "zero_rexmits", 3142 &stats->tx_zero_rexmits, "Zero Retransmits"); 3143 NFE_SYSCTL_STAT_ADD32(ctx, child, "one_rexmits", 3144 &stats->tx_one_rexmits, "One Retransmits"); 3145 NFE_SYSCTL_STAT_ADD32(ctx, child, "multi_rexmits", 3146 &stats->tx_multi_rexmits, "Multiple Retransmits"); 3147 NFE_SYSCTL_STAT_ADD32(ctx, child, "late_cols", 3148 &stats->tx_late_cols, "Late Collisions"); 3149 NFE_SYSCTL_STAT_ADD32(ctx, child, "fifo_underuns", 3150 &stats->tx_fifo_underuns, "FIFO Underruns"); 3151 NFE_SYSCTL_STAT_ADD32(ctx, child, "carrier_losts", 3152 &stats->tx_carrier_losts, "Carrier Losts"); 3153 NFE_SYSCTL_STAT_ADD32(ctx, child, "excess_deferrals", 3154 &stats->tx_excess_deferals, "Excess Deferrals"); 3155 NFE_SYSCTL_STAT_ADD32(ctx, child, "retry_errors", 3156 &stats->tx_retry_errors, "Retry Errors"); 3157 if ((sc->nfe_flags & NFE_MIB_V2) != 0) { 3158 NFE_SYSCTL_STAT_ADD32(ctx, child, "deferrals", 3159 &stats->tx_deferals, "Deferrals"); 3160 NFE_SYSCTL_STAT_ADD32(ctx, child, "frames", 3161 &stats->tx_frames, "Frames"); 3162 NFE_SYSCTL_STAT_ADD32(ctx, child, "pause", 3163 &stats->tx_pause, "Pause Frames"); 3164 } 3165 if ((sc->nfe_flags & NFE_MIB_V3) != 0) { 3166 NFE_SYSCTL_STAT_ADD32(ctx, child, "unicast", 3167 &stats->tx_deferals, "Unicast Frames"); 3168 NFE_SYSCTL_STAT_ADD32(ctx, child, "multicast", 3169 &stats->tx_frames, "Multicast Frames"); 3170 NFE_SYSCTL_STAT_ADD32(ctx, child, "broadcast", 3171 &stats->tx_pause, "Broadcast Frames"); 3172 } 3173 } 3174 3175 #undef NFE_SYSCTL_STAT_ADD32 3176 #undef NFE_SYSCTL_STAT_ADD64 3177 3178 static void 3179 nfe_stats_clear(struct nfe_softc *sc) 3180 { 3181 int i, mib_cnt; 3182 3183 if ((sc->nfe_flags & NFE_MIB_V1) != 0) 3184 mib_cnt = NFE_NUM_MIB_STATV1; 3185 else if ((sc->nfe_flags & (NFE_MIB_V2 | NFE_MIB_V3)) != 0) 3186 mib_cnt = NFE_NUM_MIB_STATV2; 3187 else 3188 return; 3189 3190 for (i = 0; i < mib_cnt; i++) 3191 NFE_READ(sc, NFE_TX_OCTET + i * sizeof(uint32_t)); 3192 3193 if ((sc->nfe_flags & NFE_MIB_V3) != 0) { 3194 NFE_READ(sc, NFE_TX_UNICAST); 3195 NFE_READ(sc, NFE_TX_MULTICAST); 3196 NFE_READ(sc, NFE_TX_BROADCAST); 3197 } 3198 } 3199 3200 static void 3201 nfe_stats_update(struct nfe_softc *sc) 3202 { 3203 struct nfe_hw_stats *stats; 3204 3205 NFE_LOCK_ASSERT(sc); 3206 3207 if ((sc->nfe_flags & (NFE_MIB_V1 | NFE_MIB_V2 | NFE_MIB_V3)) == 0) 3208 return; 3209 3210 stats = &sc->nfe_stats; 3211 stats->tx_octets += NFE_READ(sc, NFE_TX_OCTET); 3212 stats->tx_zero_rexmits += NFE_READ(sc, NFE_TX_ZERO_REXMIT); 3213 stats->tx_one_rexmits += NFE_READ(sc, NFE_TX_ONE_REXMIT); 3214 stats->tx_multi_rexmits += NFE_READ(sc, NFE_TX_MULTI_REXMIT); 3215 stats->tx_late_cols += NFE_READ(sc, NFE_TX_LATE_COL); 3216 stats->tx_fifo_underuns += NFE_READ(sc, NFE_TX_FIFO_UNDERUN); 3217 stats->tx_carrier_losts += NFE_READ(sc, NFE_TX_CARRIER_LOST); 3218 stats->tx_excess_deferals += NFE_READ(sc, NFE_TX_EXCESS_DEFERRAL); 3219 stats->tx_retry_errors += NFE_READ(sc, NFE_TX_RETRY_ERROR); 3220 stats->rx_frame_errors += NFE_READ(sc, NFE_RX_FRAME_ERROR); 3221 stats->rx_extra_bytes += NFE_READ(sc, NFE_RX_EXTRA_BYTES); 3222 stats->rx_late_cols += NFE_READ(sc, NFE_RX_LATE_COL); 3223 stats->rx_runts += NFE_READ(sc, NFE_RX_RUNT); 3224 stats->rx_jumbos += NFE_READ(sc, NFE_RX_JUMBO); 3225 stats->rx_fifo_overuns += NFE_READ(sc, NFE_RX_FIFO_OVERUN); 3226 stats->rx_crc_errors += NFE_READ(sc, NFE_RX_CRC_ERROR); 3227 stats->rx_fae += NFE_READ(sc, NFE_RX_FAE); 3228 stats->rx_len_errors += NFE_READ(sc, NFE_RX_LEN_ERROR); 3229 stats->rx_unicast += NFE_READ(sc, NFE_RX_UNICAST); 3230 stats->rx_multicast += NFE_READ(sc, NFE_RX_MULTICAST); 3231 stats->rx_broadcast += NFE_READ(sc, NFE_RX_BROADCAST); 3232 3233 if ((sc->nfe_flags & NFE_MIB_V2) != 0) { 3234 stats->tx_deferals += NFE_READ(sc, NFE_TX_DEFERAL); 3235 stats->tx_frames += NFE_READ(sc, NFE_TX_FRAME); 3236 stats->rx_octets += NFE_READ(sc, NFE_RX_OCTET); 3237 stats->tx_pause += NFE_READ(sc, NFE_TX_PAUSE); 3238 stats->rx_pause += NFE_READ(sc, NFE_RX_PAUSE); 3239 stats->rx_drops += NFE_READ(sc, NFE_RX_DROP); 3240 } 3241 3242 if ((sc->nfe_flags & NFE_MIB_V3) != 0) { 3243 stats->tx_unicast += NFE_READ(sc, NFE_TX_UNICAST); 3244 stats->tx_multicast += NFE_READ(sc, NFE_TX_MULTICAST); 3245 stats->tx_broadcast += NFE_READ(sc, NFE_TX_BROADCAST); 3246 } 3247 } 3248 3249 static void 3250 nfe_set_linkspeed(struct nfe_softc *sc) 3251 { 3252 struct mii_softc *miisc; 3253 struct mii_data *mii; 3254 int aneg, i, phyno; 3255 3256 NFE_LOCK_ASSERT(sc); 3257 3258 mii = device_get_softc(sc->nfe_miibus); 3259 mii_pollstat(mii); 3260 aneg = 0; 3261 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 3262 (IFM_ACTIVE | IFM_AVALID)) { 3263 switch IFM_SUBTYPE(mii->mii_media_active) { 3264 case IFM_10_T: 3265 case IFM_100_TX: 3266 return; 3267 case IFM_1000_T: 3268 aneg++; 3269 break; 3270 default: 3271 break; 3272 } 3273 } 3274 miisc = LIST_FIRST(&mii->mii_phys); 3275 phyno = miisc->mii_phy; 3276 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3277 PHY_RESET(miisc); 3278 nfe_miibus_writereg(sc->nfe_dev, phyno, MII_100T2CR, 0); 3279 nfe_miibus_writereg(sc->nfe_dev, phyno, 3280 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 3281 nfe_miibus_writereg(sc->nfe_dev, phyno, 3282 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 3283 DELAY(1000); 3284 if (aneg != 0) { 3285 /* 3286 * Poll link state until nfe(4) get a 10/100Mbps link. 3287 */ 3288 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 3289 mii_pollstat(mii); 3290 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 3291 == (IFM_ACTIVE | IFM_AVALID)) { 3292 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3293 case IFM_10_T: 3294 case IFM_100_TX: 3295 nfe_mac_config(sc, mii); 3296 return; 3297 default: 3298 break; 3299 } 3300 } 3301 NFE_UNLOCK(sc); 3302 pause("nfelnk", hz); 3303 NFE_LOCK(sc); 3304 } 3305 if (i == MII_ANEGTICKS_GIGE) 3306 device_printf(sc->nfe_dev, 3307 "establishing a link failed, WOL may not work!"); 3308 } 3309 /* 3310 * No link, force MAC to have 100Mbps, full-duplex link. 3311 * This is the last resort and may/may not work. 3312 */ 3313 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 3314 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 3315 nfe_mac_config(sc, mii); 3316 } 3317 3318 static void 3319 nfe_set_wol(struct nfe_softc *sc) 3320 { 3321 if_t ifp; 3322 uint32_t wolctl; 3323 int pmc; 3324 uint16_t pmstat; 3325 3326 NFE_LOCK_ASSERT(sc); 3327 3328 if (pci_find_cap(sc->nfe_dev, PCIY_PMG, &pmc) != 0) 3329 return; 3330 ifp = sc->nfe_ifp; 3331 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 3332 wolctl = NFE_WOL_MAGIC; 3333 else 3334 wolctl = 0; 3335 NFE_WRITE(sc, NFE_WOL_CTL, wolctl); 3336 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) { 3337 nfe_set_linkspeed(sc); 3338 if ((sc->nfe_flags & NFE_PWR_MGMT) != 0) 3339 NFE_WRITE(sc, NFE_PWR2_CTL, 3340 NFE_READ(sc, NFE_PWR2_CTL) & ~NFE_PWR2_GATE_CLOCKS); 3341 /* Enable RX. */ 3342 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, 0); 3343 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, 0); 3344 NFE_WRITE(sc, NFE_RX_CTL, NFE_READ(sc, NFE_RX_CTL) | 3345 NFE_RX_START); 3346 } 3347 /* Request PME if WOL is requested. */ 3348 pmstat = pci_read_config(sc->nfe_dev, pmc + PCIR_POWER_STATUS, 2); 3349 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3350 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 3351 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3352 pci_write_config(sc->nfe_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3353 } 3354