1 /******************************************************************************* 2 3 Copyright (c) 2006-2007, Myricom Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Myricom Inc, nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 POSSIBILITY OF SUCH DAMAGE. 27 28 $FreeBSD$ 29 30 ***************************************************************************/ 31 32 #define MXGE_ETH_STOPPED 0 33 #define MXGE_ETH_STOPPING 1 34 #define MXGE_ETH_STARTING 2 35 #define MXGE_ETH_RUNNING 3 36 #define MXGE_ETH_OPEN_FAILED 4 37 38 #define MXGE_FW_OFFSET 1024*1024 39 #define MXGE_EEPROM_STRINGS_SIZE 256 40 #define MXGE_MAX_SEND_DESC 128 41 42 #if (__FreeBSD_version < 800005) 43 #define MXGE_VIRT_JUMBOS 1 44 #else 45 #define MXGE_VIRT_JUMBOS 0 46 #endif 47 48 #ifndef VLAN_CAPABILITIES 49 #define VLAN_CAPABILITIES(ifp) 50 #define mxge_vlans_active(sc) (sc)->ifp->if_nvlans 51 #else 52 #define mxge_vlans_active(sc) (sc)->ifp->if_vlantrunk 53 #endif 54 55 #ifndef VLAN_TAG_VALUE 56 #define MXGE_NEW_VLAN_API 57 #endif 58 59 #ifndef IFCAP_LRO 60 #define IFCAP_LRO 0 61 #endif 62 63 #ifndef IFCAP_TSO 64 #define IFCAP_TSO 0 65 #endif 66 67 #ifndef IFCAP_TSO4 68 #define IFCAP_TSO4 0 69 #endif 70 71 #ifndef CSUM_TSO 72 #define CSUM_TSO 0 73 #endif 74 75 76 typedef struct { 77 void *addr; 78 bus_addr_t bus_addr; 79 bus_dma_tag_t dmat; 80 bus_dmamap_t map; 81 } mxge_dma_t; 82 83 84 typedef struct { 85 mcp_slot_t *entry; 86 mxge_dma_t dma; 87 int cnt; 88 int idx; 89 int mask; 90 } mxge_rx_done_t; 91 92 typedef struct 93 { 94 uint32_t data0; 95 uint32_t data1; 96 uint32_t data2; 97 } mxge_cmd_t; 98 99 struct mxge_rx_buffer_state { 100 struct mbuf *m; 101 bus_dmamap_t map; 102 }; 103 104 struct mxge_tx_buffer_state { 105 struct mbuf *m; 106 bus_dmamap_t map; 107 int flag; 108 }; 109 110 typedef struct 111 { 112 volatile mcp_kreq_ether_recv_t *lanai; /* lanai ptr for recv ring */ 113 mcp_kreq_ether_recv_t *shadow; /* host shadow of recv ring */ 114 struct mxge_rx_buffer_state *info; 115 bus_dma_tag_t dmat; 116 bus_dmamap_t extra_map; 117 int cnt; 118 int nbufs; 119 int cl_size; 120 int alloc_fail; 121 int mask; /* number of rx slots -1 */ 122 } mxge_rx_ring_t; 123 124 typedef struct 125 { 126 struct mtx mtx; 127 volatile mcp_kreq_ether_send_t *lanai; /* lanai ptr for sendq */ 128 mcp_kreq_ether_send_t *req_list; /* host shadow of sendq */ 129 char *req_bytes; 130 bus_dma_segment_t *seg_list; 131 struct mxge_tx_buffer_state *info; 132 bus_dma_tag_t dmat; 133 int req; /* transmits submitted */ 134 int mask; /* number of transmit slots -1 */ 135 int done; /* transmits completed */ 136 int pkt_done; /* packets completed */ 137 int max_desc; /* max descriptors per xmit */ 138 int stall; /* #times hw queue exhausted */ 139 int wake; /* #times irq re-enabled xmit */ 140 int watchdog_req; /* cache of req */ 141 int watchdog_done; /* cache of done */ 142 int watchdog_rx_pause; /* cache of pause rq recvd */ 143 int defrag; 144 char mtx_name[16]; 145 } mxge_tx_ring_t; 146 147 struct lro_entry; 148 struct lro_entry 149 { 150 SLIST_ENTRY(lro_entry) next; 151 struct mbuf *m_head; 152 struct mbuf *m_tail; 153 int timestamp; 154 struct ip *ip; 155 uint32_t tsval; 156 uint32_t tsecr; 157 uint32_t source_ip; 158 uint32_t dest_ip; 159 uint32_t next_seq; 160 uint32_t ack_seq; 161 uint32_t len; 162 uint32_t data_csum; 163 uint16_t window; 164 uint16_t source_port; 165 uint16_t dest_port; 166 uint16_t append_cnt; 167 uint16_t mss; 168 169 }; 170 SLIST_HEAD(lro_head, lro_entry); 171 172 struct mxge_softc; 173 typedef struct mxge_softc mxge_softc_t; 174 175 struct mxge_slice_state { 176 mxge_softc_t *sc; 177 mxge_tx_ring_t tx; /* transmit ring */ 178 mxge_rx_ring_t rx_small; 179 mxge_rx_ring_t rx_big; 180 mxge_rx_done_t rx_done; 181 mcp_irq_data_t *fw_stats; 182 volatile uint32_t *irq_claim; 183 u_long ipackets; 184 struct lro_head lro_active; 185 struct lro_head lro_free; 186 int lro_queued; 187 int lro_flushed; 188 int lro_bad_csum; 189 mxge_dma_t fw_stats_dma; 190 struct sysctl_oid *sysctl_tree; 191 struct sysctl_ctx_list sysctl_ctx; 192 char scratch[256]; 193 }; 194 195 struct mxge_softc { 196 struct ifnet* ifp; 197 struct mxge_slice_state *ss; 198 int csum_flag; /* rx_csums? */ 199 int tx_boundary; /* boundary transmits cannot cross*/ 200 int lro_cnt; 201 bus_dma_tag_t parent_dmat; 202 volatile uint8_t *sram; 203 int sram_size; 204 volatile uint32_t *irq_deassert; 205 mcp_cmd_response_t *cmd; 206 mxge_dma_t cmd_dma; 207 mxge_dma_t zeropad_dma; 208 struct pci_dev *pdev; 209 int legacy_irq; 210 int link_state; 211 unsigned int rdma_tags_available; 212 int intr_coal_delay; 213 volatile uint32_t *intr_coal_delay_ptr; 214 int wc; 215 struct mtx cmd_mtx; 216 struct mtx driver_mtx; 217 int wake_queue; 218 int stop_queue; 219 int down_cnt; 220 int watchdog_resets; 221 int watchdog_countdown; 222 int pause; 223 struct resource *mem_res; 224 struct resource *irq_res; 225 struct resource **msix_irq_res; 226 struct resource *msix_table_res; 227 struct resource *msix_pba_res; 228 void *ih; 229 void **msix_ih; 230 char *fw_name; 231 char eeprom_strings[MXGE_EEPROM_STRINGS_SIZE]; 232 char fw_version[128]; 233 int fw_ver_major; 234 int fw_ver_minor; 235 int fw_ver_tiny; 236 int adopted_rx_filter_bug; 237 device_t dev; 238 struct ifmedia media; 239 int read_dma; 240 int write_dma; 241 int read_write_dma; 242 int fw_multicast_support; 243 int link_width; 244 int max_mtu; 245 int tx_defrag; 246 int media_flags; 247 int need_media_probe; 248 int num_slices; 249 int rx_ring_size; 250 mxge_dma_t dmabench_dma; 251 struct callout co_hdl; 252 struct sysctl_oid *slice_sysctl_tree; 253 struct sysctl_ctx_list slice_sysctl_ctx; 254 char *mac_addr_string; 255 uint8_t mac_addr[6]; /* eeprom mac address */ 256 char product_code_string[64]; 257 char serial_number_string[64]; 258 char cmd_mtx_name[16]; 259 char driver_mtx_name[16]; 260 }; 261 262 #define MXGE_PCI_VENDOR_MYRICOM 0x14c1 263 #define MXGE_PCI_DEVICE_Z8E 0x0008 264 #define MXGE_PCI_DEVICE_Z8E_9 0x0009 265 #define MXGE_XFP_COMPLIANCE_BYTE 131 266 267 #define MXGE_HIGHPART_TO_U32(X) \ 268 (sizeof (X) == 8) ? ((uint32_t)((uint64_t)(X) >> 32)) : (0) 269 #define MXGE_LOWPART_TO_U32(X) ((uint32_t)(X)) 270 271 struct mxge_media_type 272 { 273 int flag; 274 uint8_t bitmask; 275 char *name; 276 }; 277 278 /* implement our own memory barriers, since bus_space_barrier 279 cannot handle write-combining regions */ 280 281 #if defined (__GNUC__) 282 #if #cpu(i386) || defined __i386 || defined i386 || defined __i386__ || #cpu(x86_64) || defined __x86_64__ 283 #define mb() __asm__ __volatile__ ("sfence;": : :"memory") 284 #elif #cpu(sparc64) || defined sparc64 || defined __sparcv9 285 #define mb() __asm__ __volatile__ ("membar #MemIssue": : :"memory") 286 #elif #cpu(sparc) || defined sparc || defined __sparc__ 287 #define mb() __asm__ __volatile__ ("stbar;": : :"memory") 288 #else 289 #define mb() /* XXX just to make this compile */ 290 #endif 291 #else 292 #error "unknown compiler" 293 #endif 294 295 static inline void 296 mxge_pio_copy(volatile void *to_v, void *from_v, size_t size) 297 { 298 register volatile uintptr_t *to; 299 volatile uintptr_t *from; 300 size_t i; 301 302 to = (volatile uintptr_t *) to_v; 303 from = from_v; 304 for (i = (size / sizeof (uintptr_t)); i; i--) { 305 *to = *from; 306 to++; 307 from++; 308 } 309 310 } 311 312 void mxge_lro_flush(struct mxge_slice_state *ss, struct lro_entry *lro); 313 int mxge_lro_rx(struct mxge_slice_state *ss, struct mbuf *m_head, 314 uint32_t csum); 315 316 317 318 /* 319 This file uses Myri10GE driver indentation. 320 321 Local Variables: 322 c-file-style:"linux" 323 tab-width:8 324 End: 325 */ 326