1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/module.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/sbuf.h> 42 #include <vm/uma.h> 43 #include <machine/stdarg.h> 44 #include <machine/resource.h> 45 #include <machine/bus.h> 46 #include <sys/rman.h> 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include "mvs.h" 50 51 /* local prototypes */ 52 static int mvs_setup_interrupt(device_t dev); 53 static void mvs_intr(void *data); 54 static int mvs_suspend(device_t dev); 55 static int mvs_resume(device_t dev); 56 static int mvs_ctlr_setup(device_t dev); 57 58 static struct { 59 uint32_t id; 60 uint8_t rev; 61 const char *name; 62 int ports; 63 int quirks; 64 } mvs_ids[] = { 65 {0x504011ab, 0x00, "Marvell 88SX5040", 4, MVS_Q_GENI}, 66 {0x504111ab, 0x00, "Marvell 88SX5041", 4, MVS_Q_GENI}, 67 {0x508011ab, 0x00, "Marvell 88SX5080", 8, MVS_Q_GENI}, 68 {0x508111ab, 0x00, "Marvell 88SX5081", 8, MVS_Q_GENI}, 69 {0x604011ab, 0x00, "Marvell 88SX6040", 4, MVS_Q_GENII}, 70 {0x604111ab, 0x00, "Marvell 88SX6041", 4, MVS_Q_GENII}, 71 {0x604211ab, 0x00, "Marvell 88SX6042", 4, MVS_Q_GENIIE}, 72 {0x608011ab, 0x00, "Marvell 88SX6080", 8, MVS_Q_GENII}, 73 {0x608111ab, 0x00, "Marvell 88SX6081", 8, MVS_Q_GENII}, 74 {0x704211ab, 0x00, "Marvell 88SX7042", 4, MVS_Q_GENIIE|MVS_Q_CT}, 75 {0x02419005, 0x00, "Adaptec 1420SA", 4, MVS_Q_GENII}, 76 {0x02439005, 0x00, "Adaptec 1430SA", 4, MVS_Q_GENIIE|MVS_Q_CT}, 77 {0x00000000, 0x00, NULL, 0, 0} 78 }; 79 80 static int 81 mvs_probe(device_t dev) 82 { 83 char buf[64]; 84 int i; 85 uint32_t devid = pci_get_devid(dev); 86 uint8_t revid = pci_get_revid(dev); 87 88 for (i = 0; mvs_ids[i].id != 0; i++) { 89 if (mvs_ids[i].id == devid && 90 mvs_ids[i].rev <= revid) { 91 snprintf(buf, sizeof(buf), "%s SATA controller", 92 mvs_ids[i].name); 93 device_set_desc_copy(dev, buf); 94 return (BUS_PROBE_DEFAULT); 95 } 96 } 97 return (ENXIO); 98 } 99 100 static int 101 mvs_attach(device_t dev) 102 { 103 struct mvs_controller *ctlr = device_get_softc(dev); 104 device_t child; 105 int error, unit, i; 106 uint32_t devid = pci_get_devid(dev); 107 uint8_t revid = pci_get_revid(dev); 108 109 ctlr->dev = dev; 110 i = 0; 111 while (mvs_ids[i].id != 0 && 112 (mvs_ids[i].id != devid || 113 mvs_ids[i].rev > revid)) 114 i++; 115 ctlr->channels = mvs_ids[i].ports; 116 ctlr->quirks = mvs_ids[i].quirks; 117 ctlr->ccc = 0; 118 resource_int_value(device_get_name(dev), 119 device_get_unit(dev), "ccc", &ctlr->ccc); 120 ctlr->cccc = 8; 121 resource_int_value(device_get_name(dev), 122 device_get_unit(dev), "cccc", &ctlr->cccc); 123 if (ctlr->ccc == 0 || ctlr->cccc == 0) { 124 ctlr->ccc = 0; 125 ctlr->cccc = 0; 126 } 127 if (ctlr->ccc > 100000) 128 ctlr->ccc = 100000; 129 device_printf(dev, 130 "Gen-%s, %d %sGbps ports, Port Multiplier %s%s\n", 131 ((ctlr->quirks & MVS_Q_GENI) ? "I" : 132 ((ctlr->quirks & MVS_Q_GENII) ? "II" : "IIe")), 133 ctlr->channels, 134 ((ctlr->quirks & MVS_Q_GENI) ? "1.5" : "3"), 135 ((ctlr->quirks & MVS_Q_GENI) ? 136 "not supported" : "supported"), 137 ((ctlr->quirks & MVS_Q_GENIIE) ? 138 " with FBS" : "")); 139 mtx_init(&ctlr->mtx, "MVS controller lock", NULL, MTX_DEF); 140 /* We should have a memory BAR(0). */ 141 ctlr->r_rid = PCIR_BAR(0); 142 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 143 &ctlr->r_rid, RF_ACTIVE))) 144 return ENXIO; 145 /* Setup our own memory management for channels. */ 146 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 147 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 148 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 149 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 150 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 151 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 152 return (error); 153 } 154 if ((error = rman_manage_region(&ctlr->sc_iomem, 155 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 156 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 157 rman_fini(&ctlr->sc_iomem); 158 return (error); 159 } 160 pci_enable_busmaster(dev); 161 mvs_ctlr_setup(dev); 162 /* Setup interrupts. */ 163 if (mvs_setup_interrupt(dev)) { 164 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 165 rman_fini(&ctlr->sc_iomem); 166 return ENXIO; 167 } 168 /* Attach all channels on this controller */ 169 for (unit = 0; unit < ctlr->channels; unit++) { 170 child = device_add_child(dev, "mvsch", -1); 171 if (child == NULL) 172 device_printf(dev, "failed to add channel device\n"); 173 else 174 device_set_ivars(child, (void *)(intptr_t)unit); 175 } 176 bus_generic_attach(dev); 177 return 0; 178 } 179 180 static int 181 mvs_detach(device_t dev) 182 { 183 struct mvs_controller *ctlr = device_get_softc(dev); 184 185 /* Detach & delete all children */ 186 device_delete_children(dev); 187 188 /* Free interrupt. */ 189 if (ctlr->irq.r_irq) { 190 bus_teardown_intr(dev, ctlr->irq.r_irq, 191 ctlr->irq.handle); 192 bus_release_resource(dev, SYS_RES_IRQ, 193 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 194 } 195 pci_release_msi(dev); 196 /* Free memory. */ 197 rman_fini(&ctlr->sc_iomem); 198 if (ctlr->r_mem) 199 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 200 mtx_destroy(&ctlr->mtx); 201 return (0); 202 } 203 204 static int 205 mvs_ctlr_setup(device_t dev) 206 { 207 struct mvs_controller *ctlr = device_get_softc(dev); 208 int i, ccc = ctlr->ccc, cccc = ctlr->cccc, ccim = 0; 209 210 /* Mask chip interrupts */ 211 ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0x00000000); 212 /* Mask PCI interrupts */ 213 ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x00000000); 214 /* Clear PCI interrupts */ 215 ATA_OUTL(ctlr->r_mem, CHIP_PCIIC, 0x00000000); 216 if (ccc && bootverbose) { 217 device_printf(dev, 218 "CCC with %dus/%dcmd enabled\n", 219 ctlr->ccc, ctlr->cccc); 220 } 221 ccc *= 150; 222 /* Configure chip-global CCC */ 223 if (ctlr->channels > 4 && (ctlr->quirks & MVS_Q_GENI) == 0) { 224 ATA_OUTL(ctlr->r_mem, CHIP_ICT, cccc); 225 ATA_OUTL(ctlr->r_mem, CHIP_ITT, ccc); 226 ATA_OUTL(ctlr->r_mem, CHIP_ICC, ~CHIP_ICC_ALL_PORTS); 227 if (ccc) 228 ccim |= IC_ALL_PORTS_COAL_DONE; 229 ccc = 0; 230 cccc = 0; 231 } 232 for (i = 0; i < ctlr->channels / 4; i++) { 233 /* Configure per-HC CCC */ 234 ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_ICT, cccc); 235 ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_ITT, ccc); 236 if (ccc) 237 ccim |= (IC_HC0_COAL_DONE << (i * IC_HC_SHIFT)); 238 /* Clear HC interrupts */ 239 ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_IC, 0x00000000); 240 } 241 /* Enable chip interrupts */ 242 ctlr->gmim = (ccim ? ccim : (IC_DONE_HC0 | IC_DONE_HC1)) | 243 IC_ERR_HC0 | IC_ERR_HC1; 244 ctlr->mim = ctlr->gmim | ctlr->pmim; 245 ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim); 246 /* Enable PCI interrupts */ 247 ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x007fffff); 248 return (0); 249 } 250 251 static void 252 mvs_edma(device_t dev, device_t child, int mode) 253 { 254 struct mvs_controller *ctlr = device_get_softc(dev); 255 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 256 int bit = IC_DONE_IRQ << (unit * 2 + unit / 4) ; 257 258 if (ctlr->ccc == 0) 259 return; 260 /* CCC is not working for non-EDMA mode. Unmask device interrupts. */ 261 mtx_lock(&ctlr->mtx); 262 if (mode == MVS_EDMA_OFF) 263 ctlr->pmim |= bit; 264 else 265 ctlr->pmim &= ~bit; 266 ctlr->mim = ctlr->gmim | ctlr->pmim; 267 if (!ctlr->msia) 268 ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim); 269 mtx_unlock(&ctlr->mtx); 270 } 271 272 static int 273 mvs_suspend(device_t dev) 274 { 275 struct mvs_controller *ctlr = device_get_softc(dev); 276 277 bus_generic_suspend(dev); 278 /* Mask chip interrupts */ 279 ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0x00000000); 280 /* Mask PCI interrupts */ 281 ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x00000000); 282 return 0; 283 } 284 285 static int 286 mvs_resume(device_t dev) 287 { 288 289 mvs_ctlr_setup(dev); 290 return (bus_generic_resume(dev)); 291 } 292 293 static int 294 mvs_setup_interrupt(device_t dev) 295 { 296 struct mvs_controller *ctlr = device_get_softc(dev); 297 int msi = 0; 298 299 /* Process hints. */ 300 resource_int_value(device_get_name(dev), 301 device_get_unit(dev), "msi", &msi); 302 if (msi < 0) 303 msi = 0; 304 else if (msi > 0) 305 msi = min(1, pci_msi_count(dev)); 306 /* Allocate MSI if needed/present. */ 307 if (msi && pci_alloc_msi(dev, &msi) != 0) 308 msi = 0; 309 ctlr->msi = msi; 310 /* Allocate all IRQs. */ 311 ctlr->irq.r_irq_rid = msi ? 1 : 0; 312 if (!(ctlr->irq.r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 313 &ctlr->irq.r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 314 device_printf(dev, "unable to map interrupt\n"); 315 return (ENXIO); 316 } 317 if ((bus_setup_intr(dev, ctlr->irq.r_irq, ATA_INTR_FLAGS, NULL, 318 mvs_intr, ctlr, &ctlr->irq.handle))) { 319 device_printf(dev, "unable to setup interrupt\n"); 320 bus_release_resource(dev, SYS_RES_IRQ, 321 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 322 ctlr->irq.r_irq = NULL; 323 return (ENXIO); 324 } 325 return (0); 326 } 327 328 /* 329 * Common case interrupt handler. 330 */ 331 static void 332 mvs_intr(void *data) 333 { 334 struct mvs_controller *ctlr = data; 335 struct mvs_intr_arg arg; 336 void (*function)(void *); 337 int p; 338 u_int32_t ic, aic; 339 340 ic = ATA_INL(ctlr->r_mem, CHIP_MIC); 341 if (ctlr->msi) { 342 /* We have to mask MSI during processing. */ 343 mtx_lock(&ctlr->mtx); 344 ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0); 345 ctlr->msia = 1; /* Deny MIM update during processing. */ 346 mtx_unlock(&ctlr->mtx); 347 } else if (ic == 0) 348 return; 349 /* Acknowledge all-ports CCC interrupt. */ 350 if (ic & IC_ALL_PORTS_COAL_DONE) 351 ATA_OUTL(ctlr->r_mem, CHIP_ICC, ~CHIP_ICC_ALL_PORTS); 352 for (p = 0; p < ctlr->channels; p++) { 353 if ((p & 3) == 0) { 354 if (p != 0) 355 ic >>= 1; 356 if ((ic & IC_HC0) == 0) { 357 p += 3; 358 ic >>= 8; 359 continue; 360 } 361 /* Acknowledge interrupts of this HC. */ 362 aic = 0; 363 if (ic & (IC_DONE_IRQ << 0)) 364 aic |= HC_IC_DONE(0) | HC_IC_DEV(0); 365 if (ic & (IC_DONE_IRQ << 2)) 366 aic |= HC_IC_DONE(1) | HC_IC_DEV(1); 367 if (ic & (IC_DONE_IRQ << 4)) 368 aic |= HC_IC_DONE(2) | HC_IC_DEV(2); 369 if (ic & (IC_DONE_IRQ << 6)) 370 aic |= HC_IC_DONE(3) | HC_IC_DEV(3); 371 if (ic & IC_HC0_COAL_DONE) 372 aic |= HC_IC_COAL; 373 ATA_OUTL(ctlr->r_mem, HC_BASE(p == 4) + HC_IC, ~aic); 374 } 375 /* Call per-port interrupt handler. */ 376 arg.cause = ic & (IC_ERR_IRQ|IC_DONE_IRQ); 377 if ((arg.cause != 0) && 378 (function = ctlr->interrupt[p].function)) { 379 arg.arg = ctlr->interrupt[p].argument; 380 function(&arg); 381 } 382 ic >>= 2; 383 } 384 if (ctlr->msi) { 385 /* Unmasking MSI triggers next interrupt, if needed. */ 386 mtx_lock(&ctlr->mtx); 387 ctlr->msia = 0; /* Allow MIM update. */ 388 ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim); 389 mtx_unlock(&ctlr->mtx); 390 } 391 } 392 393 static struct resource * 394 mvs_alloc_resource(device_t dev, device_t child, int type, int *rid, 395 rman_res_t start, rman_res_t end, rman_res_t count, 396 u_int flags) 397 { 398 struct mvs_controller *ctlr = device_get_softc(dev); 399 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 400 struct resource *res = NULL; 401 int offset = HC_BASE(unit >> 2) + PORT_BASE(unit & 0x03); 402 rman_res_t st; 403 404 switch (type) { 405 case SYS_RES_MEMORY: 406 st = rman_get_start(ctlr->r_mem); 407 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 408 st + offset + PORT_SIZE - 1, PORT_SIZE, RF_ACTIVE, child); 409 if (res) { 410 bus_space_handle_t bsh; 411 bus_space_tag_t bst; 412 bsh = rman_get_bushandle(ctlr->r_mem); 413 bst = rman_get_bustag(ctlr->r_mem); 414 bus_space_subregion(bst, bsh, offset, PORT_SIZE, &bsh); 415 rman_set_bushandle(res, bsh); 416 rman_set_bustag(res, bst); 417 } 418 break; 419 case SYS_RES_IRQ: 420 if (*rid == ATA_IRQ_RID) 421 res = ctlr->irq.r_irq; 422 break; 423 } 424 return (res); 425 } 426 427 static int 428 mvs_release_resource(device_t dev, device_t child, int type, int rid, 429 struct resource *r) 430 { 431 432 switch (type) { 433 case SYS_RES_MEMORY: 434 rman_release_resource(r); 435 return (0); 436 case SYS_RES_IRQ: 437 if (rid != ATA_IRQ_RID) 438 return ENOENT; 439 return (0); 440 } 441 return (EINVAL); 442 } 443 444 static int 445 mvs_setup_intr(device_t dev, device_t child, struct resource *irq, 446 int flags, driver_filter_t *filter, driver_intr_t *function, 447 void *argument, void **cookiep) 448 { 449 struct mvs_controller *ctlr = device_get_softc(dev); 450 int unit = (intptr_t)device_get_ivars(child); 451 452 if (filter != NULL) { 453 printf("mvs.c: we cannot use a filter here\n"); 454 return (EINVAL); 455 } 456 ctlr->interrupt[unit].function = function; 457 ctlr->interrupt[unit].argument = argument; 458 return (0); 459 } 460 461 static int 462 mvs_teardown_intr(device_t dev, device_t child, struct resource *irq, 463 void *cookie) 464 { 465 struct mvs_controller *ctlr = device_get_softc(dev); 466 int unit = (intptr_t)device_get_ivars(child); 467 468 ctlr->interrupt[unit].function = NULL; 469 ctlr->interrupt[unit].argument = NULL; 470 return (0); 471 } 472 473 static int 474 mvs_print_child(device_t dev, device_t child) 475 { 476 int retval; 477 478 retval = bus_print_child_header(dev, child); 479 retval += printf(" at channel %d", 480 (int)(intptr_t)device_get_ivars(child)); 481 retval += bus_print_child_footer(dev, child); 482 483 return (retval); 484 } 485 486 static int 487 mvs_child_location(device_t dev, device_t child, struct sbuf *sb) 488 { 489 490 sbuf_printf(sb, "channel=%d", 491 (int)(intptr_t)device_get_ivars(child)); 492 return (0); 493 } 494 495 static bus_dma_tag_t 496 mvs_get_dma_tag(device_t bus, device_t child) 497 { 498 499 return (bus_get_dma_tag(bus)); 500 } 501 502 static device_method_t mvs_methods[] = { 503 DEVMETHOD(device_probe, mvs_probe), 504 DEVMETHOD(device_attach, mvs_attach), 505 DEVMETHOD(device_detach, mvs_detach), 506 DEVMETHOD(device_suspend, mvs_suspend), 507 DEVMETHOD(device_resume, mvs_resume), 508 DEVMETHOD(bus_print_child, mvs_print_child), 509 DEVMETHOD(bus_alloc_resource, mvs_alloc_resource), 510 DEVMETHOD(bus_release_resource, mvs_release_resource), 511 DEVMETHOD(bus_setup_intr, mvs_setup_intr), 512 DEVMETHOD(bus_teardown_intr,mvs_teardown_intr), 513 DEVMETHOD(bus_child_location, mvs_child_location), 514 DEVMETHOD(bus_get_dma_tag, mvs_get_dma_tag), 515 DEVMETHOD(mvs_edma, mvs_edma), 516 { 0, 0 } 517 }; 518 static driver_t mvs_driver = { 519 "mvs", 520 mvs_methods, 521 sizeof(struct mvs_controller) 522 }; 523 DRIVER_MODULE(mvs, pci, mvs_driver, mvs_devclass, 0, 0); 524 MODULE_PNP_INFO("W32:vendor/device", pci, mvs, mvs_ids, 525 nitems(mvs_ids) - 1); 526 MODULE_VERSION(mvs, 1); 527 MODULE_DEPEND(mvs, cam, 1, 1, 1); 528